From 14a4057959f8ee0a2249eb2abd64fd6b1f571d98 Mon Sep 17 00:00:00 2001 From: Ian Wisbon Date: Thu, 10 Feb 2011 17:15:15 -0500 Subject: Digi Release Code - 02142011 Missing Files Fix --- arch/arm/configs/imx23evk_updater_defconfig | 1177 + arch/arm/configs/imx5_android_ccwmx51js_defconfig | 2099 + arch/arm/configs/imx5_android_defconfig | 2256 + arch/arm/configs/imx5_updater_defconfig | 1697 + arch/arm/mach-mx23/include/mach/regs-ocotp.h | 311 + arch/arm/mach-mx23/otp.c | 437 + arch/arm/mach-mx28/include/mach/regs-ocotp.h | 239 + arch/arm/mach-mx5/clock_mx50.c | 3554 ++ arch/arm/mach-mx5/displays/hdmi_ad9389.h | 168 + arch/arm/mach-mx5/displays/lcd.h | 135 + arch/arm/mach-mx5/displays/vga.h | 64 + arch/arm/mach-mx5/dma-apbh.c | 225 + arch/arm/mach-mx5/dma-apbh.h | 35 + arch/arm/mach-mx5/dmaengine.c | 641 + arch/arm/mach-mx5/early_setup.c | 29 + arch/arm/mach-mx5/mx50_arm2.c | 1278 + arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c | 418 + arch/arm/mach-mx5/mx50_ddr_freq.S | 479 + arch/arm/mach-mx5/mx50_rdp.c | 1186 + arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c | 418 + arch/arm/mach-mx5/mx50_suspend.S | 234 + arch/arm/mach-mx5/mx50_wfi.S | 66 + arch/arm/mach-mx5/regs-apbh.h | 512 + arch/arm/mach-mx5/sdma_script_code_mx50.h | 130 + arch/arm/plat-mxc/include/mach/dmaengine.h | 493 + arch/arm/plat-mxc/include/mach/iomux-mx50.h | 575 + arch/arm/plat-mxc/include/mach/iomux-mx51.h | 416 + arch/arm/plat-mxc/include/mach/iomux-mx53.h | 579 + arch/arm/plat-mxs/include/mach/unique-id.h | 30 + arch/arm/plat-mxs/unique-id.c | 198 + drivers/ata/ahci.h | 332 + drivers/ata/ahci_platform.c | 191 + drivers/ata/libahci.c | 2091 + drivers/char/fsl_otp.c | 239 + drivers/char/fsl_otp.h | 234 + drivers/char/regs-ocotp-v2.h | 239 + drivers/crypto/dcp_bootstream_ioctl.h | 32 + drivers/dma/pxp/Makefile | 2 + drivers/dma/pxp/pxp_device.c | 511 + drivers/dma/pxp/pxp_dma.c | 1438 + drivers/dma/pxp/regs-pxp.h | 949 + drivers/input/keyboard/mxc_pwrkey.c | 147 + drivers/media/video/mxc/output/mxc_pxp_v4l2.c | 1237 + drivers/media/video/mxc/output/mxc_pxp_v4l2.h | 82 + drivers/misc/fsl_cache.c | 85 + drivers/misc/pmem.c | 1351 + drivers/misc/uid_stat.c | 153 + drivers/mtd/nand/gpmi-nfc/Makefile | 11 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h | 550 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h | 557 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h | 567 + .../mtd/nand/gpmi-nfc/gpmi-nfc-event-reporting.c | 307 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h | 416 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h | 421 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h | 511 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c | 1037 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c | 924 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c | 866 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c | 839 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c | 1908 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c | 2630 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c | 59 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c | 297 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c | 82 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h | 645 + drivers/mxc/amd-gpu/Kconfig | 13 + drivers/mxc/amd-gpu/Makefile | 31 + drivers/mxc/amd-gpu/common/gsl_cmdstream.c | 239 + drivers/mxc/amd-gpu/common/gsl_cmdwindow.c | 136 + drivers/mxc/amd-gpu/common/gsl_context.c | 74 + drivers/mxc/amd-gpu/common/gsl_debug_pm4.c | 1015 + drivers/mxc/amd-gpu/common/gsl_device.c | 683 + drivers/mxc/amd-gpu/common/gsl_drawctxt.c | 1796 + drivers/mxc/amd-gpu/common/gsl_driver.c | 329 + drivers/mxc/amd-gpu/common/gsl_g12.c | 993 + drivers/mxc/amd-gpu/common/gsl_intrmgr.c | 305 + drivers/mxc/amd-gpu/common/gsl_log.c | 591 + drivers/mxc/amd-gpu/common/gsl_memmgr.c | 949 + drivers/mxc/amd-gpu/common/gsl_mmu.c | 1036 + drivers/mxc/amd-gpu/common/gsl_ringbuffer.c | 1154 + drivers/mxc/amd-gpu/common/gsl_sharedmem.c | 937 + drivers/mxc/amd-gpu/common/gsl_tbdump.c | 228 + drivers/mxc/amd-gpu/common/gsl_yamato.c | 887 + drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl | 327 + drivers/mxc/amd-gpu/common/pm4_microcode.inl | 815 + drivers/mxc/amd-gpu/include/api/gsl_displayapi.h | 86 + drivers/mxc/amd-gpu/include/api/gsl_klibapi.h | 135 + drivers/mxc/amd-gpu/include/api/gsl_libapi.h | 142 + drivers/mxc/amd-gpu/include/api/gsl_pm4types.h | 157 + drivers/mxc/amd-gpu/include/api/gsl_properties.h | 94 + drivers/mxc/amd-gpu/include/api/gsl_types.h | 479 + drivers/mxc/amd-gpu/include/api/gsl_utils.h | 43 + drivers/mxc/amd-gpu/include/gsl.h | 79 + drivers/mxc/amd-gpu/include/gsl_buildconfig.h | 55 + drivers/mxc/amd-gpu/include/gsl_cmdstream.h | 62 + drivers/mxc/amd-gpu/include/gsl_cmdwindow.h | 51 + drivers/mxc/amd-gpu/include/gsl_config.h | 221 + drivers/mxc/amd-gpu/include/gsl_context.h | 45 + drivers/mxc/amd-gpu/include/gsl_debug.h | 126 + drivers/mxc/amd-gpu/include/gsl_device.h | 142 + drivers/mxc/amd-gpu/include/gsl_display.h | 62 + drivers/mxc/amd-gpu/include/gsl_drawctxt.h | 110 + drivers/mxc/amd-gpu/include/gsl_driver.h | 106 + drivers/mxc/amd-gpu/include/gsl_hal.h | 151 + drivers/mxc/amd-gpu/include/gsl_halconfig.h | 49 + drivers/mxc/amd-gpu/include/gsl_intrmgr.h | 104 + drivers/mxc/amd-gpu/include/gsl_ioctl.h | 238 + drivers/mxc/amd-gpu/include/gsl_log.h | 74 + drivers/mxc/amd-gpu/include/gsl_memmgr.h | 122 + drivers/mxc/amd-gpu/include/gsl_mmu.h | 183 + drivers/mxc/amd-gpu/include/gsl_ringbuffer.h | 235 + drivers/mxc/amd-gpu/include/gsl_sharedmem.h | 110 + drivers/mxc/amd-gpu/include/gsl_tbdump.h | 38 + drivers/mxc/amd-gpu/include/reg/g12_reg.h | 41 + drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h | 291 + drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h | 3775 ++ drivers/mxc/amd-gpu/include/reg/yamato.h | 66 + .../amd-gpu/include/reg/yamato/10/yamato_enum.h | 1895 + .../amd-gpu/include/reg/yamato/10/yamato_genenum.h | 1703 + .../amd-gpu/include/reg/yamato/10/yamato_genreg.h | 3404 ++ .../amd-gpu/include/reg/yamato/10/yamato_mask.h | 5920 ++ .../amd-gpu/include/reg/yamato/10/yamato_offset.h | 590 + .../amd-gpu/include/reg/yamato/10/yamato_random.h | 223 + .../include/reg/yamato/10/yamato_registers.h | 14292 +++++ .../amd-gpu/include/reg/yamato/10/yamato_shift.h | 4183 ++ .../amd-gpu/include/reg/yamato/10/yamato_struct.h | 52571 ++++++++++++++++++ .../amd-gpu/include/reg/yamato/10/yamato_typedef.h | 550 + .../mxc/amd-gpu/include/reg/yamato/10/yamatoix.h | 169 + .../amd-gpu/include/reg/yamato/14/yamato_enum.h | 1867 + .../amd-gpu/include/reg/yamato/14/yamato_genenum.h | 1674 + .../amd-gpu/include/reg/yamato/14/yamato_genreg.h | 3310 ++ .../mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h | 95 + .../amd-gpu/include/reg/yamato/14/yamato_mask.h | 5739 ++ .../amd-gpu/include/reg/yamato/14/yamato_offset.h | 581 + .../amd-gpu/include/reg/yamato/14/yamato_random.h | 221 + .../include/reg/yamato/14/yamato_registers.h | 13962 +++++ .../amd-gpu/include/reg/yamato/14/yamato_shift.h | 4078 ++ .../amd-gpu/include/reg/yamato/14/yamato_struct.h | 51301 +++++++++++++++++ .../amd-gpu/include/reg/yamato/14/yamato_typedef.h | 540 + .../amd-gpu/include/reg/yamato/22/yamato_enum.h | 1897 + .../amd-gpu/include/reg/yamato/22/yamato_genenum.h | 1703 + .../amd-gpu/include/reg/yamato/22/yamato_genreg.h | 3405 ++ .../mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h | 95 + .../amd-gpu/include/reg/yamato/22/yamato_mask.h | 5908 ++ .../amd-gpu/include/reg/yamato/22/yamato_offset.h | 591 + .../amd-gpu/include/reg/yamato/22/yamato_random.h | 223 + .../include/reg/yamato/22/yamato_registers.h | 14280 +++++ .../amd-gpu/include/reg/yamato/22/yamato_shift.h | 4184 ++ .../amd-gpu/include/reg/yamato/22/yamato_struct.h | 52583 ++++++++++++++++++ .../amd-gpu/include/reg/yamato/22/yamato_typedef.h | 550 + drivers/mxc/amd-gpu/os/include/os_types.h | 138 + drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h | 813 + drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c | 661 + drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c | 579 + .../mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h | 142 + drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c | 964 + .../amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c | 269 + .../amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h | 90 + .../mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c | 221 + .../mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h | 46 + drivers/mxc/amd-gpu/platform/hal/linux/misc.c | 129 + drivers/net/fec_switch.c | 4255 ++ drivers/net/fec_switch.h | 1121 + drivers/regulator/max17135-regulator.c | 749 + drivers/rtc/alarm.c | 567 + drivers/spi/spi_mxs.c | 711 + drivers/spi/spi_mxs.h | 52 + drivers/switch/Kconfig | 15 + drivers/switch/Makefile | 4 + drivers/switch/switch_class.c | 174 + drivers/switch/switch_gpio.c | 171 + drivers/usb/gadget/android.c | 376 + drivers/usb/gadget/f_acm.h | 24 + drivers/usb/gadget/f_adb.c | 685 + drivers/usb/gadget/f_adb.h | 25 + drivers/usb/gadget/f_mass_storage.c | 3025 + drivers/usb/gadget/f_mass_storage.h | 52 + drivers/video/mxc/ad9389.c | 815 + drivers/video/mxc/elcdif_regs.h | 678 + drivers/video/mxc/epdc_regs.h | 301 + drivers/video/mxc/ldb.c | 1448 + drivers/video/mxc/mxc_elcdif_fb.c | 1445 + drivers/video/mxc/mxc_epdc_fb.c | 3187 ++ drivers/video/mxc/mxcfb_sii9022.c | 252 + drivers/video/mxs/regs-tvenc.h | 583 + drivers/video/mxs/tvenc.c | 279 + firmware/imx/epdc_E60.fw.ihex | 45914 ++++++++++++++++ firmware/imx/epdc_E97.fw.ihex | 54512 +++++++++++++++++++ include/linux/ahci_platform.h | 29 + include/linux/android_aid.h | 26 + include/linux/android_alarm.h | 62 + include/linux/android_pmem.h | 97 + include/linux/ashmem.h | 48 + include/linux/earlysuspend.h | 56 + include/linux/fsl_cache.h | 25 + include/linux/gpmi-nfc.h | 123 + include/linux/ldb.h | 88 + include/linux/mmc/pm.h | 30 + include/linux/mxc_srtc.h | 25 + include/linux/pxp_dma.h | 221 + include/linux/regulator/max17135.h | 58 + include/linux/switch.h | 53 + include/linux/uid_stat.h | 24 + include/linux/usb/android.h | 50 + include/linux/wakelock.h | 97 + include/video/ad9389.h | 58 + kernel/power/consoleearlysuspend.c | 112 + kernel/power/earlysuspend.c | 183 + kernel/power/fbearlysuspend.c | 153 + kernel/power/userwakelock.c | 236 + kernel/power/wakelock.c | 637 + mm/ashmem.c | 696 + sound/soc/codecs/cs42888.c | 1196 + sound/soc/codecs/cs42888.h | 31 + sound/soc/imx/imx-3stack-cs42888.c | 410 + 215 files changed, 446812 insertions(+) create mode 100644 arch/arm/configs/imx23evk_updater_defconfig create mode 100644 arch/arm/configs/imx5_android_ccwmx51js_defconfig create mode 100644 arch/arm/configs/imx5_android_defconfig create mode 100644 arch/arm/configs/imx5_updater_defconfig create mode 100644 arch/arm/mach-mx23/include/mach/regs-ocotp.h create mode 100644 arch/arm/mach-mx23/otp.c create mode 100644 arch/arm/mach-mx28/include/mach/regs-ocotp.h create mode 100644 arch/arm/mach-mx5/clock_mx50.c create mode 100644 arch/arm/mach-mx5/displays/hdmi_ad9389.h create mode 100644 arch/arm/mach-mx5/displays/lcd.h create mode 100644 arch/arm/mach-mx5/displays/vga.h create mode 100644 arch/arm/mach-mx5/dma-apbh.c create mode 100644 arch/arm/mach-mx5/dma-apbh.h create mode 100644 arch/arm/mach-mx5/dmaengine.c create mode 100644 arch/arm/mach-mx5/early_setup.c create mode 100644 arch/arm/mach-mx5/mx50_arm2.c create mode 100644 arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c create mode 100644 arch/arm/mach-mx5/mx50_ddr_freq.S create mode 100644 arch/arm/mach-mx5/mx50_rdp.c create mode 100644 arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c create mode 100644 arch/arm/mach-mx5/mx50_suspend.S create mode 100644 arch/arm/mach-mx5/mx50_wfi.S create mode 100644 arch/arm/mach-mx5/regs-apbh.h create mode 100644 arch/arm/mach-mx5/sdma_script_code_mx50.h create mode 100644 arch/arm/plat-mxc/include/mach/dmaengine.h create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx50.h create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51.h create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx53.h create mode 100644 arch/arm/plat-mxs/include/mach/unique-id.h create mode 100644 arch/arm/plat-mxs/unique-id.c create mode 100644 drivers/ata/ahci.h create mode 100644 drivers/ata/ahci_platform.c create mode 100644 drivers/ata/libahci.c create mode 100755 drivers/char/fsl_otp.c create mode 100755 drivers/char/fsl_otp.h create mode 100755 drivers/char/regs-ocotp-v2.h create mode 100644 drivers/crypto/dcp_bootstream_ioctl.h create mode 100644 drivers/dma/pxp/Makefile create mode 100644 drivers/dma/pxp/pxp_device.c create mode 100644 drivers/dma/pxp/pxp_dma.c create mode 100644 drivers/dma/pxp/regs-pxp.h create mode 100644 drivers/input/keyboard/mxc_pwrkey.c create mode 100644 drivers/media/video/mxc/output/mxc_pxp_v4l2.c create mode 100644 drivers/media/video/mxc/output/mxc_pxp_v4l2.h create mode 100644 drivers/misc/fsl_cache.c create mode 100644 drivers/misc/pmem.c create mode 100644 drivers/misc/uid_stat.c create mode 100644 drivers/mtd/nand/gpmi-nfc/Makefile create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-event-reporting.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h create mode 100644 drivers/mxc/amd-gpu/Kconfig create mode 100644 drivers/mxc/amd-gpu/Makefile create mode 100644 drivers/mxc/amd-gpu/common/gsl_cmdstream.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_cmdwindow.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_context.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_debug_pm4.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_device.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_drawctxt.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_driver.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_g12.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_intrmgr.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_log.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_memmgr.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_mmu.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_ringbuffer.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_sharedmem.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_tbdump.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_yamato.c create mode 100644 drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl create mode 100644 drivers/mxc/amd-gpu/common/pm4_microcode.inl create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_displayapi.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_klibapi.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_libapi.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_pm4types.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_properties.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_types.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_utils.h create mode 100644 drivers/mxc/amd-gpu/include/gsl.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_buildconfig.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_cmdstream.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_cmdwindow.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_config.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_context.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_debug.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_device.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_display.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_drawctxt.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_driver.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_hal.h create mode 100755 drivers/mxc/amd-gpu/include/gsl_halconfig.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_intrmgr.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_ioctl.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_log.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_memmgr.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_mmu.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_ringbuffer.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_sharedmem.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_tbdump.h create mode 100644 drivers/mxc/amd-gpu/include/reg/g12_reg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h create mode 100644 drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h create mode 100644 drivers/mxc/amd-gpu/os/include/os_types.h create mode 100644 drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h create mode 100644 drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/misc.c create mode 100644 drivers/net/fec_switch.c create mode 100644 drivers/net/fec_switch.h create mode 100644 drivers/regulator/max17135-regulator.c create mode 100644 drivers/rtc/alarm.c create mode 100644 drivers/spi/spi_mxs.c create mode 100644 drivers/spi/spi_mxs.h create mode 100644 drivers/switch/Kconfig create mode 100644 drivers/switch/Makefile create mode 100644 drivers/switch/switch_class.c create mode 100644 drivers/switch/switch_gpio.c create mode 100644 drivers/usb/gadget/android.c create mode 100644 drivers/usb/gadget/f_acm.h create mode 100644 drivers/usb/gadget/f_adb.c create mode 100644 drivers/usb/gadget/f_adb.h create mode 100755 drivers/usb/gadget/f_mass_storage.c create mode 100644 drivers/usb/gadget/f_mass_storage.h create mode 100644 drivers/video/mxc/ad9389.c create mode 100644 drivers/video/mxc/elcdif_regs.h create mode 100644 drivers/video/mxc/epdc_regs.h create mode 100644 drivers/video/mxc/ldb.c create mode 100644 drivers/video/mxc/mxc_elcdif_fb.c create mode 100644 drivers/video/mxc/mxc_epdc_fb.c create mode 100644 drivers/video/mxc/mxcfb_sii9022.c create mode 100644 drivers/video/mxs/regs-tvenc.h create mode 100644 drivers/video/mxs/tvenc.c create mode 100644 firmware/imx/epdc_E60.fw.ihex create mode 100644 firmware/imx/epdc_E97.fw.ihex create mode 100644 include/linux/ahci_platform.h create mode 100644 include/linux/android_aid.h create mode 100644 include/linux/android_alarm.h create mode 100644 include/linux/android_pmem.h create mode 100644 include/linux/ashmem.h create mode 100644 include/linux/earlysuspend.h create mode 100644 include/linux/fsl_cache.h create mode 100644 include/linux/gpmi-nfc.h create mode 100644 include/linux/ldb.h create mode 100644 include/linux/mmc/pm.h create mode 100644 include/linux/mxc_srtc.h create mode 100644 include/linux/pxp_dma.h create mode 100644 include/linux/regulator/max17135.h create mode 100644 include/linux/switch.h create mode 100644 include/linux/uid_stat.h create mode 100644 include/linux/usb/android.h create mode 100644 include/linux/wakelock.h create mode 100644 include/video/ad9389.h create mode 100644 kernel/power/consoleearlysuspend.c create mode 100644 kernel/power/earlysuspend.c create mode 100644 kernel/power/fbearlysuspend.c create mode 100644 kernel/power/userwakelock.c create mode 100644 kernel/power/wakelock.c create mode 100644 mm/ashmem.c create mode 100644 sound/soc/codecs/cs42888.c create mode 100644 sound/soc/codecs/cs42888.h create mode 100644 sound/soc/imx/imx-3stack-cs42888.c diff --git a/arch/arm/configs/imx23evk_updater_defconfig b/arch/arm/configs/imx23evk_updater_defconfig new file mode 100644 index 000000000000..f6a430b5bf5f --- /dev/null +++ b/arch/arm/configs/imx23evk_updater_defconfig @@ -0,0 +1,1177 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31 +# Thu May 6 16:41:59 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_FIQ=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="-updater" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +CONFIG_ARCH_MXS=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=12 +CONFIG_VECTORS_PHY_ADDR=0 + +# +# Freescale i.MXS implementations +# +# CONFIG_ARCH_MX28 is not set +CONFIG_ARCH_MX23=y +CONFIG_MACH_MX23EVK=y +CONFIG_MXS_ICOLL=y +CONFIG_MXS_EARLY_CONSOLE=y +CONFIG_MXS_DMA_ENGINE=y +CONFIG_MXS_LRADC=y +CONFIG_MXS_PWM_CHANNELS=8 + +# +# Freescale Application UART: +# +CONFIG_MXS_AUART_DMA_SUPPORT=y +CONFIG_MXS_AUART_PORTS=5 +# CONFIG_MXS_AUART0_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART0_DMA_ENABLE is not set +CONFIG_MXS_AUART1_DEVICE_ENABLE=y +# CONFIG_MXS_AUART1_DMA_ENABLE is not set +# CONFIG_MXS_AUART2_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART2_DMA_ENABLE is not set +# CONFIG_MXS_AUART3_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART3_DMA_ENABLE is not set +# CONFIG_MXS_AUART4_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART4_DMA_ENABLE is not set +CONFIG_MXS_RAM_FREQ_SCALING=y +# CONFIG_MXS_RAM_MDDR is not set +CONFIG_MXS_RAM_DDR=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0,115200 rdinit=/linuxrc" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_SUSPEND is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_GPMI_NFC=y +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=128 +CONFIG_MTD_UBI_BEB_RESERVE=2 +CONFIG_MTD_UBI_GLUEBI=y + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_MXS_PERSISTENT=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_MXS_VIIM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXS_DUART=y +CONFIG_SERIAL_MXS_AUART=y +CONFIG_SERIAL_MXS_DUART_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_SPI is not set +CONFIG_FSL_OTP=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXS=y +# CONFIG_FB_MXS_LCD_43WVF1G is not set +CONFIG_FB_MXS_LCD_LMS430=y +# CONFIG_FB_MXS_TVENC is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_ILI9320 is not set +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +CONFIG_BACKLIGHT_MXS=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_LOGO is not set +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=y +CONFIG_FSL_UTP=y +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +CONFIG_MMC_MXS=y +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_MXS=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +CONFIG_REGULATOR_MXS=y +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +# CONFIG_UBIFS_FS_ZLIB is not set +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_DCP is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/imx5_android_ccwmx51js_defconfig b/arch/arm/configs/imx5_android_ccwmx51js_defconfig new file mode 100644 index 000000000000..7159eb55c4d4 --- /dev/null +++ b/arch/arm/configs/imx5_android_ccwmx51js_defconfig @@ -0,0 +1,2099 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31 +# Wed Jan 26 17:12:17 2011 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_ASHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_FREEZER=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=96 +CONFIG_UTMI_MXC=y + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX3 is not set +# CONFIG_ARCH_MX25 is not set +# CONFIG_ARCH_MX35 is not set +# CONFIG_ARCH_MX37 is not set +CONFIG_ARCH_MX5=y +CONFIG_MXC_SDMA_API=y +CONFIG_SDMA_IRAM=y +CONFIG_I2C_MXC_SELECT2=y +# CONFIG_I2C_MXC_SELECT3 is not set +CONFIG_FORCE_MAX_ZONEORDER=13 +CONFIG_ARCH_MXC_HAS_NFC_V3=y +CONFIG_ARCH_MX51=y +# CONFIG_ARCH_MX53 is not set +CONFIG_MX5_OPTIONS=y +# CONFIG_MACH_MX51_3DS is not set +# CONFIG_MACH_MX51_BABBAGE is not set +# CONFIG_MACH_MX53_EVK is not set +# CONFIG_MACH_MX50_ARM2 is not set +CONFIG_MODULE_CCXMX51=y +CONFIG_LATE_CPU_CLK_ENABLE=y +# CONFIG_MACH_MX50_RDP is not set +CONFIG_MACH_CCWMX51JS=y +# CONFIG_MACH_CCWMX51 is not set +# CONFIG_MACH_CCMX51JS is not set +# CONFIG_MACH_CCMX51 is not set +# CONFIG_JSCCWMX51_V1 is not set +CONFIG_JSCCWMX51_V2=y +# CONFIG_JSCCWMX51_CUSTOM is not set + +# +# MX5x Options: +# +CONFIG_MXC_NAND_SWAP_BI=y +CONFIG_ARCH_MXC_HAS_NFC_V3_2=y + +# +# Serial Port Options +# +CONFIG_UART1_ENABLED=y +CONFIG_UART1_2WIRE_ENABLED=y +# CONFIG_UART1_CTS_RTS_ENABLED is not set +# CONFIG_UART1_FULL_UART_ENABLED is not set +# CONFIG_UART1_IRDA_ENABLED is not set +CONFIG_UART2_ENABLED=y + +# +# UART2 CTS/RTS is not available on the ConnectCore Wi-i.MX51 JumpStart board if +# + +# +# the support for Host1 of the Freescale USB controller is enabled. +# +# CONFIG_UART2_IRDA_ENABLED is not set +CONFIG_UART3_ENABLED=y +# CONFIG_UART3_CTS_RTS_ENABLED is not set +# CONFIG_UART3_IRDA_ENABLED is not set + +# +# SPI Interface Options +# +CONFIG_SPI_MXC_SELECT1=y +CONFIG_SPI_MXC_SELECT1_SS1=y +# CONFIG_SPI_MXC_SELECT2 is not set +# CONFIG_SPI_MXC_SELECT3 is not set + +# +# I2C Interface options +# + +# +# SD/MMC Interface options +# +CONFIG_ESDHCI_MXC_SELECT1=y +CONFIG_ESDHCI_MXC_SELECT3=y + +# +# Video Interface(s) +# +# CONFIG_CCWMX51_DEFAULT_VIDEO_32BPP is not set +CONFIG_CCWMX51_DEFAULT_VIDEO_16BPP=y +CONFIG_CCWMX51_DEFAULT_VIDEO_BPP=16 +CONFIG_CCWMX51_DISP0=y +# CONFIG_CCWMX51_DISP0_RGB888 is not set +CONFIG_CCWMX51_DISP0_RGB666=y + +# +# To enable the Display 2 Video interface, disable the FEC (under network drivers) +# + +# +# and set 18bit color mode for the Display 1 +# +# CONFIG_CCWMX51_SECOND_TOUCH is not set +CONFIG_MXC_TZIC=y +CONFIG_ISP1504_MXC=y +# CONFIG_MXC_IRQ_PRIOR is not set +# CONFIG_MXC_PWM is not set +CONFIG_ARCH_MXC_IOMUX_V3=y +# CONFIG_MXC_DVFS_PER is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_IFAR=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_458693=y +CONFIG_ARM_ERRATA_460075=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_IMX=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HAS_WAKELOCK=y +CONFIG_HAS_EARLYSUSPEND=y +CONFIG_WAKELOCK=y +CONFIG_WAKELOCK_STAT=y +CONFIG_USER_WAKELOCK=y +CONFIG_EARLYSUSPEND=y +# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set +# CONFIG_CONSOLE_EARLYSUSPEND is not set +CONFIG_FB_EARLYSUSPEND=y +CONFIG_APM_EMULATION=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=y +# CONFIG_BT_HCIBTSDIO is not set +# CONFIG_BT_HCIUART is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +CONFIG_BT_HCIVHCI=y +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +CONFIG_MAC80211=y +# CONFIG_MAC80211_DEFAULT_PS is not set +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 + +# +# Rate control algorithm selection +# +# CONFIG_MAC80211_RC_PID is not set +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_MXC is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MXC_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_IMX_NFC is not set +CONFIG_MTD_NAND_MXC_V3=y +# CONFIG_MTD_NAND_MXC_SWECC is not set +# CONFIG_MTD_NAND_MXC_FORCE_CE is not set +# CONFIG_MXC_NAND_LOW_LEVEL_ERASE is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +CONFIG_ANDROID_PMEM=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +CONFIG_UID_STAT=y +CONFIG_FSL_CACHE=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +# CONFIG_SCSI_WAIT_SCAN is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_CS89x0 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +CONFIG_FEC=y +# CONFIG_FEC_1588 is not set +# CONFIG_FEC2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_APMPOWER is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_MXC is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_MXC=y +CONFIG_TOUCH_MXC_DELTA_X=10 +CONFIG_TOUCH_MXC_DELTA_Y=10 +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_MXC_IIM is not set +# CONFIG_MXS_VIIM is not set +# CONFIG_IMX_SIM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXC=y +CONFIG_SERIAL_MXC_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_IMX is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_IMX is not set +CONFIG_I2C_MXC=y +# CONFIG_I2C_MXC_HS is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_I2C_SLAVE is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_MXC=y +# CONFIG_SPI_MXC_TEST_LOOPBACK is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_APM_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_MXC_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA9875 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_ADV7343 is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_MXC_CAMERA is not set +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set +# CONFIG_VIDEO_MXC_PXP_V4L2 is not set +# CONFIG_VIDEO_MXC_OPL is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_V4L_USB_DRIVERS is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXC=y +CONFIG_FB_MXC_SYNC_PANEL=y +# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_TVOUT_TVE is not set +# CONFIG_FB_MXC_LDB is not set +# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SII9022 is not set +# CONFIG_FB_MXC_CH7026 is not set +# CONFIG_FB_MXC_TVOUT_CH7024 is not set +CONFIG_VIDEO_AD9389=y +# CONFIG_FB_MXC_ASYNC_PANEL is not set +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_SEQUENCER=y +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_HRTIMER is not set +CONFIG_SND_DYNAMIC_MINORS=y +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_MXC_SOC=y +CONFIG_SND_MXC_SOC_SSI=y +# CONFIG_SND_MXC_SOC_IRAM is not set +# CONFIG_SND_SOC_IMX_3STACK_SGTL5000 is not set +# CONFIG_SND_SOC_IMX_3STACK_AK4647 is not set +# CONFIG_SND_SOC_IMX_3STACK_WM8580 is not set +CONFIG_SND_SOC_IMX_CCWMX51_WM8753=y +# CONFIG_SND_SOC_IMX_3STACK_AK5702 is not set +# CONFIG_SND_SOC_IMX_3STACK_BLUETOOTH is not set +# CONFIG_SND_SOC_IMX_3STACK_CS42888 is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_WM8753=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ARC=y +CONFIG_USB_EHCI_ARC_H1=y +CONFIG_USB_EHCI_ARC_OTG=y +# CONFIG_USB_STATIC_IRAM is not set +# CONFIG_USB_EHCI_FSL_MC13783 is not set +# CONFIG_USB_EHCI_FSL_1301 is not set +# CONFIG_USB_EHCI_FSL_1504 is not set +CONFIG_USB_EHCI_FSL_UTMI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +CONFIG_USB_STORAGE_USBAT=y +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +# CONFIG_USB_EZUSB is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +CONFIG_USB_SERIAL_OPTION=y +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +# CONFIG_USB_STATIC_IRAM_PPH is not set +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_ANDROID=y +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MXC_OTG=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_IMX_ESDHCI=y +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_SWITCH=y +# CONFIG_SWITCH_GPIO is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_INTF_ALARM=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_MXC is not set +# CONFIG_RTC_DRV_MXC_V2 is not set +# CONFIG_RTC_DRV_IMXDI is not set +CONFIG_RTC_MC13892=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_LP3971 is not set +CONFIG_REGULATOR_MC13892=y +# CONFIG_REGULATOR_MAX17135 is not set +# CONFIG_UIO is not set +CONFIG_STAGING=y +# CONFIG_STAGING_EXCLUDE_BUILD is not set +# CONFIG_MEILHAUS is not set +# CONFIG_USB_IP_COMMON is not set +# CONFIG_ECHO is not set +# CONFIG_COMEDI is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_INPUT_MIMIO is not set +# CONFIG_TRANZPORT is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y +CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT=y +CONFIG_ANDROID_RAM_CONSOLE_EARLY_ADDR=0 +CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE=0 +CONFIG_ANDROID_TIMED_OUTPUT=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +# CONFIG_DST is not set +# CONFIG_POHMELFS is not set +# CONFIG_PLAN9AUTH is not set +# CONFIG_LINE6_USB is not set +# CONFIG_USB_SERIAL_QUATECH2 is not set +# CONFIG_USB_CPC is not set +# CONFIG_FB_UDL is not set + +# +# MXC support drivers +# +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3=y + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +CONFIG_MXC_PMIC=y +# CONFIG_MXC_PMIC_MC13783 is not set +CONFIG_MXC_PMIC_MC13892=y +# CONFIG_MXC_PMIC_I2C is not set +CONFIG_MXC_PMIC_SPI=y +# CONFIG_MXC_PMIC_MC34704 is not set +# CONFIG_MXC_PMIC_MC9SDZ60 is not set +# CONFIG_MXC_PMIC_CHARDEV is not set + +# +# MXC PMIC Client Drivers +# +CONFIG_MXC_MC13892_ADC=y +# CONFIG_MXC_MC13892_RTC is not set +# CONFIG_MXC_MC13892_LIGHT is not set +# CONFIG_MXC_MC13892_BATTERY is not set +# CONFIG_MXC_MC13892_CONNECTIVITY is not set +# CONFIG_MXC_MC13892_POWER is not set +# CONFIG_MXC_PMIC_MC9S08DZ60 is not set + +# +# MXC Security Drivers +# +# CONFIG_MXC_SECURITY_SCC is not set +# CONFIG_MXC_SECURITY_SCC2 is not set + +# +# SAHARA2 Security Hardware Support +# +# CONFIG_MXC_SAHARA is not set + +# +# MXC MPEG4 Encoder Kernel module support +# +# CONFIG_MXC_HMP4E is not set + +# +# MXC HARDWARE EVENT +# +# CONFIG_MXC_HWEVENT is not set + +# +# MXC VPU(Video Processing Unit) support +# +CONFIG_MXC_VPU=y +CONFIG_MXC_VPU_IRAM=y +# CONFIG_MXC_VPU_DEBUG is not set + +# +# MXC Asynchronous Sample Rate Converter support +# + +# +# MXC Bluetooth support +# + +# +# Broadcom GPS ioctrl support +# + +# +# MXC Media Local Bus Driver +# + +# +# i.MX ADC support +# +# CONFIG_IMX_ADC is not set + +# +# MXC GPU support +# +CONFIG_MXC_AMD_GPU=y + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +CONFIG_TMPFSDEV=y +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/imx5_android_defconfig b/arch/arm/configs/imx5_android_defconfig new file mode 100644 index 000000000000..4b0de5e1495f --- /dev/null +++ b/arch/arm/configs/imx5_android_defconfig @@ -0,0 +1,2256 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31 +# Fri Sep 17 14:25:25 2010 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_ASHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_FREEZER=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=96 +CONFIG_UTMI_MXC=y + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX3 is not set +# CONFIG_ARCH_MX25 is not set +# CONFIG_ARCH_MX35 is not set +# CONFIG_ARCH_MX37 is not set +CONFIG_ARCH_MX5=y +CONFIG_MXC_SDMA_API=y +CONFIG_SDMA_IRAM=y +CONFIG_FORCE_MAX_ZONEORDER=13 +CONFIG_ARCH_MXC_HAS_NFC_V3=y +CONFIG_ARCH_MX51=y +CONFIG_ARCH_MX53=y +CONFIG_ARCH_MX50=y +CONFIG_MX5_OPTIONS=y +CONFIG_MX5_MULTI_ARCH=y +CONFIG_MACH_MX51_3DS=y +CONFIG_MACH_MX51_BABBAGE=y +CONFIG_MACH_MX53_EVK=y +CONFIG_MACH_MX50_ARM2=y +CONFIG_MACH_MX50_RDP=y + +# +# MX5x Options: +# +CONFIG_ARCH_MXC_HAS_NFC_V3_2=y +CONFIG_MXC_TZIC=y +CONFIG_ISP1504_MXC=y +# CONFIG_MXC_IRQ_PRIOR is not set +CONFIG_MXC_PWM=y +CONFIG_ARCH_HAS_RNGC=y +CONFIG_ARCH_MXC_IOMUX_V3=y +CONFIG_MXC_DVFS_PER=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_IFAR=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HIGHMEM=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +CONFIG_RUNTIME_PHYS_OFFSET=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_IMX=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HAS_WAKELOCK=y +CONFIG_HAS_EARLYSUSPEND=y +CONFIG_WAKELOCK=y +CONFIG_WAKELOCK_STAT=y +CONFIG_USER_WAKELOCK=y +CONFIG_EARLYSUSPEND=y +# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set +# CONFIG_CONSOLE_EARLYSUSPEND is not set +CONFIG_FB_EARLYSUSPEND=y +CONFIG_APM_EMULATION=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=y +# CONFIG_BT_HCIBTSDIO is not set +# CONFIG_BT_HCIUART is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +CONFIG_BT_HCIVHCI=y +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_MXC is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_MXC_DATAFLASH=y +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_IMX_NFC is not set +CONFIG_MTD_NAND_MXC_V3=y +# CONFIG_MTD_NAND_MXC_SWECC is not set +# CONFIG_MTD_NAND_MXC_FORCE_CE is not set +# CONFIG_MXC_NAND_LOW_LEVEL_ERASE is not set +CONFIG_MTD_NAND_GPMI_NFC=y +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +CONFIG_ANDROID_PMEM=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +CONFIG_UID_STAT=y +CONFIG_FSL_CACHE=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=m +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_SATA_PMP is not set +# CONFIG_SATA_AHCI_PLATFORM is not set +CONFIG_ATA_SFF=y +# CONFIG_SATA_MV is not set +# CONFIG_PATA_PLATFORM is not set +CONFIG_PATA_FSL=m +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +CONFIG_SMSC911X=y +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_CS89x0 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +CONFIG_FEC=y +# CONFIG_FEC_1588 is not set +# CONFIG_FEC2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_WAN is not set +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=y +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_APMPOWER is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_MXC=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_MXC=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_FM_SI4702=m +CONFIG_MXC_IIM=y +CONFIG_MXS_VIIM=y +CONFIG_IMX_SIM=m + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXC=y +CONFIG_SERIAL_MXC_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_IMX is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_FSL_OTP=y +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_FSL_RNGC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_IMX is not set +CONFIG_I2C_MXC=y +CONFIG_I2C_MXC_HS=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_I2C_SLAVE is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_MXC=y +# CONFIG_SPI_MXC_TEST_LOOPBACK is not set +CONFIG_SPI_MXC_SELECT1=y +# CONFIG_SPI_MXC_SELECT2 is not set +# CONFIG_SPI_MXC_SELECT3 is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +CONFIG_W1=m +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_DS2482 is not set +CONFIG_W1_MASTER_MXC=m +# CONFIG_W1_MASTER_GPIO is not set + +# +# 1-wire Slaves +# +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2751 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +CONFIG_W1_SLAVE_DS2438=m +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +CONFIG_APM_POWER=y +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_SENSORS_ISL29003=y +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_MXC_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA9875 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_ADV7343 is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_VIVI is not set +CONFIG_VIDEO_MXC_CAMERA=y + +# +# MXC Camera/V4L2 PRP Features support +# +CONFIG_VIDEO_MXC_IPU_CAMERA=y +# CONFIG_VIDEO_MXC_CSI_CAMERA is not set +# CONFIG_MXC_CAMERA_MC521DA is not set +# CONFIG_MXC_EMMA_CAMERA_MICRON111 is not set +# CONFIG_MXC_CAMERA_OV2640_EMMA is not set +# CONFIG_MXC_CAMERA_MICRON111 is not set +# CONFIG_MXC_CAMERA_OV2640 is not set +CONFIG_MXC_CAMERA_OV3640=y +# CONFIG_MXC_TVIN_ADV7180 is not set +CONFIG_MXC_IPU_PRP_VF_SDC=y +CONFIG_MXC_IPU_PRP_ENC=y +CONFIG_MXC_IPU_CSI_ENC=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set +# CONFIG_VIDEO_MXC_PXP_V4L2 is not set +# CONFIG_VIDEO_MXC_OPL is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_USB_VICAM is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_QUICKCAM_MESSENGER is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_VIDEO_OVCAMCHIP is not set +# CONFIG_USB_OV511 is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_STV680 is not set +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_PWC is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXC=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL=y +CONFIG_FB_MXC_TVOUT_TVE=y +CONFIG_FB_MXC_LDB=y +# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SII9022 is not set +CONFIG_FB_MXC_CH7026=y +# CONFIG_FB_MXC_TVOUT_CH7024 is not set +# CONFIG_FB_MXC_ASYNC_PANEL is not set +CONFIG_FB_MXC_EINK_PANEL=y +# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_MXC=y +CONFIG_BACKLIGHT_MXC_MC13892=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +CONFIG_SND_MXC_SPDIF=m +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_MXC_SOC=y +CONFIG_SND_MXC_SOC_SSI=y +CONFIG_SND_MXC_SOC_IRAM=y +CONFIG_SND_SOC_IMX_3STACK_SGTL5000=y +# CONFIG_SND_SOC_IMX_3STACK_AK4647 is not set +# CONFIG_SND_SOC_IMX_3STACK_WM8580 is not set +# CONFIG_SND_SOC_IMX_3STACK_AK5702 is not set +# CONFIG_SND_SOC_IMX_3STACK_BLUETOOTH is not set +# CONFIG_SND_SOC_IMX_3STACK_CS42888 is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_SGTL5000=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +CONFIG_HID_APPLE=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +# CONFIG_HID_DRAGONRISE is not set +CONFIG_HID_EZKEY=m +# CONFIG_HID_KYE is not set +CONFIG_HID_GYRATION=m +# CONFIG_HID_KENSINGTON is not set +CONFIG_HID_LOGITECH=m +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +# CONFIG_HID_NTRIG is not set +CONFIG_HID_PANTHERLORD=m +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_HID_SUNPLUS=m +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ARC=y +CONFIG_USB_EHCI_ARC_OTG=y +# CONFIG_USB_STATIC_IRAM is not set +# CONFIG_USB_EHCI_FSL_MC13783 is not set +# CONFIG_USB_EHCI_FSL_1301 is not set +# CONFIG_USB_EHCI_FSL_1504 is not set +CONFIG_USB_EHCI_FSL_UTMI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +# CONFIG_USB_EZUSB is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +CONFIG_USB_SERIAL_OPTION=y +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +# CONFIG_USB_STATIC_IRAM_PPH is not set +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_ANDROID=y +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MXC_OTG=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set +CONFIG_SDIO_UNIFI_FS=m + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_MXC is not set +CONFIG_MMC_IMX_ESDHCI=y +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_MC13892=y +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_BD2802 is not set + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGERS is not set +CONFIG_SWITCH=y +# CONFIG_SWITCH_GPIO is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_INTF_ALARM=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_MXC is not set +# CONFIG_RTC_DRV_MXC_V2 is not set +# CONFIG_RTC_DRV_IMXDI is not set +CONFIG_RTC_MC13892=y +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +CONFIG_MXC_PXP=y +CONFIG_MXC_PXP_CLIENT_DEVICE=y +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_LP3971 is not set +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_MAX17135=y +CONFIG_UIO=y +# CONFIG_UIO_PDRV is not set +CONFIG_UIO_PDRV_GENIRQ=m +# CONFIG_UIO_SMX is not set +# CONFIG_UIO_SERCOS3 is not set +CONFIG_STAGING=y +# CONFIG_STAGING_EXCLUDE_BUILD is not set +# CONFIG_MEILHAUS is not set +# CONFIG_USB_IP_COMMON is not set +# CONFIG_ECHO is not set +# CONFIG_COMEDI is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_INPUT_MIMIO is not set +# CONFIG_TRANZPORT is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y +# CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION is not set +# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set +CONFIG_ANDROID_TIMED_OUTPUT=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +# CONFIG_DST is not set +# CONFIG_POHMELFS is not set +# CONFIG_PLAN9AUTH is not set +# CONFIG_LINE6_USB is not set +# CONFIG_USB_SERIAL_QUATECH2 is not set +# CONFIG_USB_CPC is not set +# CONFIG_FB_UDL is not set + +# +# MXC support drivers +# +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3=y + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +CONFIG_MXC_PMIC=y +# CONFIG_MXC_PMIC_MC13783 is not set +CONFIG_MXC_PMIC_MC13892=y +CONFIG_MXC_PMIC_I2C=y +CONFIG_MXC_PMIC_SPI=y +# CONFIG_MXC_PMIC_MC34704 is not set +# CONFIG_MXC_PMIC_MC9SDZ60 is not set +# CONFIG_MXC_PMIC_CHARDEV is not set + +# +# MXC PMIC Client Drivers +# +CONFIG_MXC_MC13892_ADC=y +CONFIG_MXC_MC13892_RTC=y +CONFIG_MXC_MC13892_LIGHT=y +CONFIG_MXC_MC13892_BATTERY=y +CONFIG_MXC_MC13892_CONNECTIVITY=y +CONFIG_MXC_MC13892_POWER=y +# CONFIG_MXC_PMIC_MC9S08DZ60 is not set + +# +# MXC Security Drivers +# +# CONFIG_MXC_SECURITY_SCC is not set +# CONFIG_MXC_SECURITY_SCC2 is not set +# CONFIG_MXC_SECURITY_RNG is not set + +# +# SAHARA2 Security Hardware Support +# +# CONFIG_MXC_SAHARA is not set + +# +# MXC MPEG4 Encoder Kernel module support +# +# CONFIG_MXC_HMP4E is not set + +# +# MXC HARDWARE EVENT +# +# CONFIG_MXC_HWEVENT is not set + +# +# MXC VPU(Video Processing Unit) support +# +CONFIG_MXC_VPU=y +CONFIG_MXC_VPU_IRAM=y +# CONFIG_MXC_VPU_DEBUG is not set + +# +# MXC Asynchronous Sample Rate Converter support +# + +# +# MXC Bluetooth support +# +CONFIG_MXC_BLUETOOTH=m + +# +# Broadcom GPS ioctrl support +# +CONFIG_GPS_IOCTRL=m + +# +# MXC Media Local Bus Driver +# +# CONFIG_MXC_MLB is not set + +# +# i.MX ADC support +# +# CONFIG_IMX_ADC is not set + +# +# MXC GPU support +# +CONFIG_MXC_AMD_GPU=y + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_DCP is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/imx5_updater_defconfig b/arch/arm/configs/imx5_updater_defconfig new file mode 100644 index 000000000000..f594185b5e0a --- /dev/null +++ b/arch/arm/configs/imx5_updater_defconfig @@ -0,0 +1,1697 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31 +# Tue Jul 27 15:14:58 2010 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_FREEZER=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=96 +CONFIG_UTMI_MXC=y + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX3 is not set +# CONFIG_ARCH_MX25 is not set +# CONFIG_ARCH_MX35 is not set +# CONFIG_ARCH_MX37 is not set +CONFIG_ARCH_MX5=y +CONFIG_MXC_SDMA_API=y +CONFIG_SDMA_IRAM=y +CONFIG_FORCE_MAX_ZONEORDER=13 +CONFIG_ARCH_MXC_HAS_NFC_V3=y +CONFIG_ARCH_MX51=y +CONFIG_ARCH_MX53=y +CONFIG_ARCH_MX50=y +CONFIG_MX5_OPTIONS=y +CONFIG_MX5_MULTI_ARCH=y +CONFIG_MACH_MX51_3DS=y +CONFIG_MACH_MX51_BABBAGE=y +CONFIG_MACH_MX53_EVK=y +CONFIG_MACH_MX50_ARM2=y + +# +# MX5x Options: +# +CONFIG_ARCH_MXC_HAS_NFC_V3_2=y +CONFIG_MXC_TZIC=y +CONFIG_ISP1504_MXC=y +# CONFIG_MXC_IRQ_PRIOR is not set +CONFIG_MXC_PWM=y +CONFIG_ARCH_MXC_IOMUX_V3=y +CONFIG_MXC_DVFS_PER=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_IFAR=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_VMSPLIT_3G is not set +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HIGHMEM=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +CONFIG_RUNTIME_PHYS_OFFSET=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_IMX=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_MXC is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_MXC_DATAFLASH=y +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_IMX_NFC is not set +CONFIG_MTD_NAND_MXC_V3=y +# CONFIG_MTD_NAND_MXC_SWECC is not set +# CONFIG_MTD_NAND_MXC_FORCE_CE is not set +# CONFIG_MXC_NAND_LOW_LEVEL_ERASE is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_APMPOWER is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_MXC=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_MXC=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_FM_SI4702=y +CONFIG_MXC_IIM=y +CONFIG_IMX_SIM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXC=y +CONFIG_SERIAL_MXC_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_IMX is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +CONFIG_FSL_OTP=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_IMX is not set +CONFIG_I2C_MXC=y +CONFIG_I2C_MXC_HS=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_I2C_SLAVE is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_MXC=y +# CONFIG_SPI_MXC_TEST_LOOPBACK is not set +CONFIG_SPI_MXC_SELECT1=y +# CONFIG_SPI_MXC_SELECT2 is not set +# CONFIG_SPI_MXC_SELECT3 is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +CONFIG_W1=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_DS2482 is not set +CONFIG_W1_MASTER_MXC=y +# CONFIG_W1_MASTER_GPIO is not set + +# +# 1-wire Slaves +# +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2751 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +CONFIG_W1_SLAVE_DS2438=y +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +CONFIG_APM_POWER=y +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_SENSORS_ISL29003=y +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +CONFIG_SOFT_WATCHDOG=y +CONFIG_MXC_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXC=y +CONFIG_FB_MXC_SYNC_PANEL=y +# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_TVOUT_TVE is not set +# CONFIG_FB_MXC_LDB is not set +# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_CH7026 is not set +# CONFIG_FB_MXC_TVOUT_CH7024 is not set +# CONFIG_FB_MXC_ASYNC_PANEL is not set +# CONFIG_FB_MXC_EINK_PANEL is not set +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_MXC=y +CONFIG_BACKLIGHT_MXC_MC13892=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +# CONFIG_HID_DRAGONRISE is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_KYE is not set +CONFIG_HID_GYRATION=y +# CONFIG_HID_KENSINGTON is not set +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +# CONFIG_HID_NTRIG is not set +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ARC=y +# CONFIG_USB_EHCI_ARC_OTG is not set +# CONFIG_USB_STATIC_IRAM is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +# CONFIG_USB_STATIC_IRAM_PPH is not set +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=y +CONFIG_FSL_UTP=y +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_MXC_OTG is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set +CONFIG_SDIO_UNIFI_FS=y + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_MXC is not set +CONFIG_MMC_IMX_ESDHCI=y +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_MC13892=y +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_BD2802 is not set + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGERS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_MXC is not set +# CONFIG_RTC_DRV_MXC_V2 is not set +# CONFIG_RTC_DRV_IMXDI is not set +CONFIG_RTC_MC13892=y +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +CONFIG_MXC_PXP=y +CONFIG_MXC_PXP_CLIENT_DEVICE=y +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_LP3971 is not set +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_MAX17135=y +CONFIG_UIO=y +# CONFIG_UIO_PDRV is not set +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_SMX is not set +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_STAGING is not set + +# +# MXC support drivers +# +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3=y + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +CONFIG_MXC_PMIC=y +# CONFIG_MXC_PMIC_MC13783 is not set +CONFIG_MXC_PMIC_MC13892=y +CONFIG_MXC_PMIC_I2C=y +CONFIG_MXC_PMIC_SPI=y +# CONFIG_MXC_PMIC_MC34704 is not set +# CONFIG_MXC_PMIC_MC9SDZ60 is not set +# CONFIG_MXC_PMIC_CHARDEV is not set + +# +# MXC PMIC Client Drivers +# +CONFIG_MXC_MC13892_ADC=y +CONFIG_MXC_MC13892_RTC=y +CONFIG_MXC_MC13892_LIGHT=y +CONFIG_MXC_MC13892_BATTERY=y +CONFIG_MXC_MC13892_CONNECTIVITY=y +CONFIG_MXC_MC13892_POWER=y +# CONFIG_MXC_PMIC_MC9S08DZ60 is not set + +# +# MXC Security Drivers +# +# CONFIG_MXC_SECURITY_SCC is not set +# CONFIG_MXC_SECURITY_SCC2 is not set +# CONFIG_MXC_SECURITY_RNG is not set + +# +# SAHARA2 Security Hardware Support +# +# CONFIG_MXC_SAHARA is not set + +# +# MXC MPEG4 Encoder Kernel module support +# +# CONFIG_MXC_HMP4E is not set + +# +# MXC HARDWARE EVENT +# +# CONFIG_MXC_HWEVENT is not set + +# +# MXC VPU(Video Processing Unit) support +# +# CONFIG_MXC_VPU is not set +# CONFIG_MXC_VPU_IRAM is not set + +# +# MXC Asynchronous Sample Rate Converter support +# + +# +# MXC Bluetooth support +# +CONFIG_MXC_BLUETOOTH=y + +# +# Broadcom GPS ioctrl support +# +CONFIG_GPS_IOCTRL=y + +# +# MXC Media Local Bus Driver +# +CONFIG_MXC_MLB=y + +# +# i.MX ADC support +# +# CONFIG_IMX_ADC is not set + +# +# MXC GPU support +# +# CONFIG_MXC_AMD_GPU is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_FILE_CAPABILITIES=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/mach-mx23/include/mach/regs-ocotp.h b/arch/arm/mach-mx23/include/mach/regs-ocotp.h new file mode 100644 index 000000000000..b0313dd67f93 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-ocotp.h @@ -0,0 +1,311 @@ +/* + * Freescale OCOTP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.21 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___OCOTP_H +#define __ARCH_ARM___OCOTP_H + + +#define HW_OCOTP_CTRL (0x00000000) +#define HW_OCOTP_CTRL_SET (0x00000004) +#define HW_OCOTP_CTRL_CLR (0x00000008) +#define HW_OCOTP_CTRL_TOG (0x0000000c) + +#define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BF_OCOTP_CTRL_WR_UNLOCK(v) \ + (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK) +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77 +#define BP_OCOTP_CTRL_RSRVD2 14 +#define BM_OCOTP_CTRL_RSRVD2 0x0000C000 +#define BF_OCOTP_CTRL_RSRVD2(v) \ + (((v) << 14) & BM_OCOTP_CTRL_RSRVD2) +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 +#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 +#define BP_OCOTP_CTRL_RSRVD1 10 +#define BM_OCOTP_CTRL_RSRVD1 0x00000C00 +#define BF_OCOTP_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_CTRL_RSRVD1) +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_RSRVD0 5 +#define BM_OCOTP_CTRL_RSRVD0 0x000000E0 +#define BF_OCOTP_CTRL_RSRVD0(v) \ + (((v) << 5) & BM_OCOTP_CTRL_RSRVD0) +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000001F +#define BF_OCOTP_CTRL_ADDR(v) \ + (((v) << 0) & BM_OCOTP_CTRL_ADDR) + +#define HW_OCOTP_DATA (0x00000010) + +#define BP_OCOTP_DATA_DATA 0 +#define BM_OCOTP_DATA_DATA 0xFFFFFFFF +#define BF_OCOTP_DATA_DATA(v) (v) + +/* + * multi-register-define name HW_OCOTP_CUSTn + * base 0x00000020 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CUSTn(n) (0x00000020 + (n) * 0x10) +#define BP_OCOTP_CUSTn_BITS 0 +#define BM_OCOTP_CUSTn_BITS 0xFFFFFFFF +#define BF_OCOTP_CUSTn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_CRYPTOn + * base 0x00000060 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CRYPTOn(n) (0x00000060 + (n) * 0x10) +#define BP_OCOTP_CRYPTOn_BITS 0 +#define BM_OCOTP_CRYPTOn_BITS 0xFFFFFFFF +#define BF_OCOTP_CRYPTOn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_HWCAPn + * base 0x000000A0 + * count 6 + * offset 0x10 + */ +#define HW_OCOTP_HWCAPn(n) (0x000000a0 + (n) * 0x10) +#define BP_OCOTP_HWCAPn_BITS 0 +#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF +#define BF_OCOTP_HWCAPn_BITS(v) (v) + +#define HW_OCOTP_SWCAP (0x00000100) + +#define BP_OCOTP_SWCAP_BITS 0 +#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF +#define BF_OCOTP_SWCAP_BITS(v) (v) + +#define HW_OCOTP_CUSTCAP (0x00000110) + +#define BM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9 0x80000000 +#define BM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10 0x40000000 +#define BP_OCOTP_CUSTCAP_RSRVD1 5 +#define BM_OCOTP_CUSTCAP_RSRVD1 0x3FFFFFE0 +#define BF_OCOTP_CUSTCAP_RSRVD1(v) \ + (((v) << 5) & BM_OCOTP_CUSTCAP_RSRVD1) +#define BM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE 0x00000010 +#define BM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG 0x00000008 +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 0x00000004 +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 0x00000002 +#define BM_OCOTP_CUSTCAP_RSRVD0 0x00000001 + +#define HW_OCOTP_LOCK (0x00000120) + +#define BM_OCOTP_LOCK_ROM7 0x80000000 +#define BM_OCOTP_LOCK_ROM6 0x40000000 +#define BM_OCOTP_LOCK_ROM5 0x20000000 +#define BM_OCOTP_LOCK_ROM4 0x10000000 +#define BM_OCOTP_LOCK_ROM3 0x08000000 +#define BM_OCOTP_LOCK_ROM2 0x04000000 +#define BM_OCOTP_LOCK_ROM1 0x02000000 +#define BM_OCOTP_LOCK_ROM0 0x01000000 +#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x00800000 +#define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x00400000 +#define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x00200000 +#define BM_OCOTP_LOCK_PIN 0x00100000 +#define BM_OCOTP_LOCK_OPS 0x00080000 +#define BM_OCOTP_LOCK_UN2 0x00040000 +#define BM_OCOTP_LOCK_UN1 0x00020000 +#define BM_OCOTP_LOCK_UN0 0x00010000 +#define BP_OCOTP_LOCK_UNALLOCATED 11 +#define BM_OCOTP_LOCK_UNALLOCATED 0x0000F800 +#define BF_OCOTP_LOCK_UNALLOCATED(v) \ + (((v) << 11) & BM_OCOTP_LOCK_UNALLOCATED) +#define BM_OCOTP_LOCK_ROM_SHADOW 0x00000400 +#define BM_OCOTP_LOCK_CUSTCAP 0x00000200 +#define BM_OCOTP_LOCK_HWSW 0x00000100 +#define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x00000080 +#define BM_OCOTP_LOCK_HWSW_SHADOW 0x00000040 +#define BM_OCOTP_LOCK_CRYPTODCP 0x00000020 +#define BM_OCOTP_LOCK_CRYPTOKEY 0x00000010 +#define BM_OCOTP_LOCK_CUST3 0x00000008 +#define BM_OCOTP_LOCK_CUST2 0x00000004 +#define BM_OCOTP_LOCK_CUST1 0x00000002 +#define BM_OCOTP_LOCK_CUST0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_OPSn + * base 0x00000130 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_OPSn(n) (0x00000130 + (n) * 0x10) +#define BP_OCOTP_OPSn_BITS 0 +#define BM_OCOTP_OPSn_BITS 0xFFFFFFFF +#define BF_OCOTP_OPSn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_UNn + * base 0x00000170 + * count 3 + * offset 0x10 + */ +#define HW_OCOTP_UNn(n) (0x00000170 + (n) * 0x10) +#define BP_OCOTP_UNn_BITS 0 +#define BM_OCOTP_UNn_BITS 0xFFFFFFFF +#define BF_OCOTP_UNn_BITS(v) (v) + +#define HW_OCOTP_ROM0 (0x000001a0) + +#define BP_OCOTP_ROM0_BOOT_MODE 24 +#define BM_OCOTP_ROM0_BOOT_MODE 0xFF000000 +#define BF_OCOTP_ROM0_BOOT_MODE(v) \ + (((v) << 24) & BM_OCOTP_ROM0_BOOT_MODE) +#define BM_OCOTP_ROM0_ENABLE_PJTAG_12MA_DRIVE 0x00800000 +#define BM_OCOTP_ROM0_USE_PARALLEL_JTAG 0x00400000 +#define BP_OCOTP_ROM0_SD_POWER_GATE_GPIO 20 +#define BM_OCOTP_ROM0_SD_POWER_GATE_GPIO 0x00300000 +#define BF_OCOTP_ROM0_SD_POWER_GATE_GPIO(v) \ + (((v) << 20) & BM_OCOTP_ROM0_SD_POWER_GATE_GPIO) +#define BP_OCOTP_ROM0_SD_POWER_UP_DELAY 14 +#define BM_OCOTP_ROM0_SD_POWER_UP_DELAY 0x000FC000 +#define BF_OCOTP_ROM0_SD_POWER_UP_DELAY(v) \ + (((v) << 14) & BM_OCOTP_ROM0_SD_POWER_UP_DELAY) +#define BP_OCOTP_ROM0_SD_BUS_WIDTH 12 +#define BM_OCOTP_ROM0_SD_BUS_WIDTH 0x00003000 +#define BF_OCOTP_ROM0_SD_BUS_WIDTH(v) \ + (((v) << 12) & BM_OCOTP_ROM0_SD_BUS_WIDTH) +#define BP_OCOTP_ROM0_SSP_SCK_INDEX 8 +#define BM_OCOTP_ROM0_SSP_SCK_INDEX 0x00000F00 +#define BF_OCOTP_ROM0_SSP_SCK_INDEX(v) \ + (((v) << 8) & BM_OCOTP_ROM0_SSP_SCK_INDEX) +#define BM_OCOTP_ROM0_RSRVD3 0x00000080 +#define BM_OCOTP_ROM0_DISABLE_SPI_NOR_FAST_ READ 0x00000040 +#define BM_OCOTP_ROM0_ENABLE_USB_BOOT_SERIAL_NUM 0x00000020 +#define BM_OCOTP_ROM0_ENABLE_UNENCRYPTED_ BOOT 0x00000010 +#define BM_OCOTP_ROM0_SD_MBR_BOOT 0x00000008 +#define BM_OCOTP_ROM0_RSRVD2 0x00000004 +#define BM_OCOTP_ROM0_RSRVD1 0x00000002 +#define BM_OCOTP_ROM0_RSRVD0 0x00000001 + +#define HW_OCOTP_ROM1 (0x000001b0) + +#define BP_OCOTP_ROM1_RSRVD1 30 +#define BM_OCOTP_ROM1_RSRVD1 0xC0000000 +#define BF_OCOTP_ROM1_RSRVD1(v) \ + (((v) << 30) & BM_OCOTP_ROM1_RSRVD1) +#define BP_OCOTP_ROM1_USE_ALT_GPMI_RDY3 28 +#define BM_OCOTP_ROM1_USE_ALT_GPMI_RDY3 0x30000000 +#define BF_OCOTP_ROM1_USE_ALT_GPMI_RDY3(v) \ + (((v) << 28) & BM_OCOTP_ROM1_USE_ALT_GPMI_RDY3) +#define BP_OCOTP_ROM1_USE_ALT_GPMI_CE3 26 +#define BM_OCOTP_ROM1_USE_ALT_GPMI_CE3 0x0C000000 +#define BF_OCOTP_ROM1_USE_ALT_GPMI_CE3(v) \ + (((v) << 26) & BM_OCOTP_ROM1_USE_ALT_GPMI_CE3) +#define BM_OCOTP_ROM1_USE_ALT_GPMI_RDY2 0x02000000 +#define BM_OCOTP_ROM1_USE_ALT_GPMI_CE2 0x01000000 +#define BM_OCOTP_ROM1_ENABLE_NAND3_CE_RDY_PULLUP 0x00800000 +#define BM_OCOTP_ROM1_ENABLE_NAND2_CE_RDY_PULLUP 0x00400000 +#define BM_OCOTP_ROM1_ENABLE_NAND1_CE_RDY_PULLUP 0x00200000 +#define BM_OCOTP_ROM1_ENABLE_NAND0_CE_RDY_PULLUP 0x00100000 +#define BM_OCOTP_ROM1_UNTOUCH_INTERNAL_SSP_PULLUP 0x00080000 +#define BM_OCOTP_ROM1_SSP2_EXT_PULLUP 0x00040000 +#define BM_OCOTP_ROM1_SSP1_EXT_PULLUP 0x00020000 +#define BM_OCOTP_ROM1_SD_INCREASE_INIT_SEQ_TIME 0x00010000 +#define BM_OCOTP_ROM1_SD_INIT_SEQ_2_ENABLE 0x00008000 +#define BM_OCOTP_ROM1_SD_CMD0_DISABLE 0x00004000 +#define BM_OCOTP_ROM1_SD_INIT_SEQ_1_DISABLE 0x00002000 +#define BM_OCOTP_ROM1_USE_ALT_SSP1_DATA4_7 0x00001000 +#define BP_OCOTP_ROM1_BOOT_SEARCH_COUNT 8 +#define BM_OCOTP_ROM1_BOOT_SEARCH_COUNT 0x00000F00 +#define BF_OCOTP_ROM1_BOOT_SEARCH_COUNT(v) \ + (((v) << 8) & BM_OCOTP_ROM1_BOOT_SEARCH_COUNT) +#define BP_OCOTP_ROM1_RSRVD0 3 +#define BM_OCOTP_ROM1_RSRVD0 0x000000F8 +#define BF_OCOTP_ROM1_RSRVD0(v) \ + (((v) << 3) & BM_OCOTP_ROM1_RSRVD0) +#define BP_OCOTP_ROM1_NUMBER_OF_NANDS 0 +#define BM_OCOTP_ROM1_NUMBER_OF_NANDS 0x00000007 +#define BF_OCOTP_ROM1_NUMBER_OF_NANDS(v) \ + (((v) << 0) & BM_OCOTP_ROM1_NUMBER_OF_NANDS) + +#define HW_OCOTP_ROM2 (0x000001c0) + +#define BP_OCOTP_ROM2_USB_VID 16 +#define BM_OCOTP_ROM2_USB_VID 0xFFFF0000 +#define BF_OCOTP_ROM2_USB_VID(v) \ + (((v) << 16) & BM_OCOTP_ROM2_USB_VID) +#define BP_OCOTP_ROM2_USB_PID 0 +#define BM_OCOTP_ROM2_USB_PID 0x0000FFFF +#define BF_OCOTP_ROM2_USB_PID(v) \ + (((v) << 0) & BM_OCOTP_ROM2_USB_PID) + +#define HW_OCOTP_ROM3 (0x000001d0) + +#define BP_OCOTP_ROM3_RSRVD1 10 +#define BM_OCOTP_ROM3_RSRVD1 0xFFFFFC00 +#define BF_OCOTP_ROM3_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_ROM3_RSRVD1) +#define BP_OCOTP_ROM3_RSRVD0 0 +#define BM_OCOTP_ROM3_RSRVD0 0x000003FF +#define BF_OCOTP_ROM3_RSRVD0(v) \ + (((v) << 0) & BM_OCOTP_ROM3_RSRVD0) + +#define HW_OCOTP_ROM4 (0x000001e0) + +#define BP_OCOTP_ROM4_BITS 0 +#define BM_OCOTP_ROM4_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM4_BITS(v) (v) + +#define HW_OCOTP_ROM5 (0x000001f0) + +#define BP_OCOTP_ROM5_BITS 0 +#define BM_OCOTP_ROM5_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM5_BITS(v) (v) + +#define HW_OCOTP_ROM6 (0x00000200) + +#define BP_OCOTP_ROM6_BITS 0 +#define BM_OCOTP_ROM6_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM6_BITS(v) (v) + +#define HW_OCOTP_ROM7 (0x00000210) + +#define BP_OCOTP_ROM7_BITS 0 +#define BM_OCOTP_ROM7_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM7_BITS(v) (v) + +#define HW_OCOTP_VERSION (0x00000220) + +#define BP_OCOTP_VERSION_MAJOR 24 +#define BM_OCOTP_VERSION_MAJOR 0xFF000000 +#define BF_OCOTP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_OCOTP_VERSION_MAJOR) +#define BP_OCOTP_VERSION_MINOR 16 +#define BM_OCOTP_VERSION_MINOR 0x00FF0000 +#define BF_OCOTP_VERSION_MINOR(v) \ + (((v) << 16) & BM_OCOTP_VERSION_MINOR) +#define BP_OCOTP_VERSION_STEP 0 +#define BM_OCOTP_VERSION_STEP 0x0000FFFF +#define BF_OCOTP_VERSION_STEP(v) \ + (((v) << 0) & BM_OCOTP_VERSION_STEP) +#endif /* __ARCH_ARM___OCOTP_H */ diff --git a/arch/arm/mach-mx23/otp.c b/arch/arm/mach-mx23/otp.c new file mode 100644 index 000000000000..7bec45f3754c --- /dev/null +++ b/arch/arm/mach-mx23/otp.c @@ -0,0 +1,437 @@ +/* + * Unique ID manipulation: Freescale STMP378X OTP bits read/write procedures + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static DEFINE_MUTEX(otp_mutex); +static unsigned otp_mode; +static unsigned long otp_hclk_saved; +static u32 otp_voltage_saved; + +static int otp_full; /* = 0. By default, show/set only customer bits */ +#define OTP_USER_OFFSET 0 +#define OTP_USER_SIZE 4 + +#define REGS_OCOTP_BASE (IO_ADDRESS(OCOTP_PHYS_ADDR)) +#define BF(value, field) (((value) << BP_##field) & BM_##field) +/** + * otp_wait_busy - wait for completion of operation + * + * @flags: flags that should be clear in addition to _BUSY and _ERROR + * + * Returns 0 on success or -ETIMEDOUT on error + **/ +static int otp_wait_busy(u32 flags) +{ + int count; + u32 c; + + for (count = 10000; count >= 0; count--) { + c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL); + if (!(c & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR | flags))) + break; + cpu_relax(); + } + if (count < 0) + return -ETIMEDOUT; + return 0; +} + +/** + * otp_open - open OTP bits for read or write access + * + * @mode: either O_RDONLY or O_WRONLY + * + * Returns 0 on success, error code otherwise + **/ +static int otp_open(int mode) +{ + int r; + struct clk *hclk; + int err; + + if (!mutex_trylock(&otp_mutex)) { + printk(KERN_ERR"%s: already opened\n", __func__); + return -EAGAIN; + } + + if (mode == O_RDONLY) { + pr_debug("%s: read-only mode\n", __func__); + + r = otp_wait_busy(0); + if (r) { + err = -ETIMEDOUT; + goto out; + } + + /* 2. Set RD_BANK_OPEN */ + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + udelay(10); + + otp_wait_busy(0); + } + + else if (mode == O_WRONLY) { + pr_debug("%s: write-only mode\n", __func__); + hclk = clk_get(NULL, "hclk"); + if (IS_ERR(hclk)) { + err = PTR_ERR(hclk); + goto out; + } + + /* + WARNING ACHTUNG UWAGA + + the code below changes HCLK clock rate to 24M. This is + required to write OTP bits (7.2.2 in STMP378x Target + Specification), and might affect LCD operation, for example. + Moreover, this hacky code changes VDDIO to 2.8V; and resto- + res it only on otp_close(). This may affect... anything. + + You are warned now. + */ + otp_hclk_saved = clk_get_rate(hclk); + clk_set_rate(hclk, 24000); + /* Set the voltage to 2.8V */ + otp_voltage_saved = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + __raw_writel( + (otp_voltage_saved & ~BM_POWER_VDDIOCTRL_TRG) | 0x00, REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + + r = otp_wait_busy(BM_OCOTP_CTRL_RD_BANK_OPEN); + if (r < 0) { + __raw_writel(otp_voltage_saved, REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + clk_set_rate(hclk, otp_hclk_saved); + clk_put(hclk); + err = -ETIMEDOUT; + goto out; + } + + clk_put(hclk); + } + + else { + pr_debug("%s: unknown mode '%d'\n", __func__, mode); + err = -EINVAL; + goto out; + } + + otp_mode = mode; + return 0; +out: + mutex_unlock(&otp_mutex); + pr_debug("%s: status %d\n", __func__, err); + return err; +} + +/** + * otp_close - close the OTP bits after opening by otp_open + **/ +static void otp_close(void) +{ + struct clk *hclk; + + if (!mutex_is_locked(&otp_mutex)) { + printk(KERN_ERR"%s: wasn't opened\n", __func__); + return; + } + + if (otp_mode == O_RDONLY) { + /* 5. clear RD_BANK_OPEN */ + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, REGS_OCOTP_BASE + HW_OCOTP_CTRL_CLR); + } + + else if (otp_mode == O_WRONLY) { + hclk = clk_get(NULL, "hclk"); + clk_set_rate(hclk, otp_hclk_saved); + __raw_writel(otp_voltage_saved, REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + otp_wait_busy(0); + __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS, REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS); + } + + else { + return; /* -EINVAL. Who does really check close? */ + } + + otp_mode = 0; + mutex_unlock(&otp_mutex); +} + +/** + * otp_read_bits - read the content of OTP + * + * @start: offset from 0, in u32's + * @len: number of OTP u32's to read + * @bits: caller-allocated buffer to save bits + * @size: size of @bits + * + * Returns number of u32's saved to buffer + **/ +static size_t otp_read_bits(int start, int len, u32 *bits, size_t size) +{ + int ofs; + + BUG_ON(!mutex_is_locked(&otp_mutex)); + + /* read all stuff that caller needs */ + if (start + len > 4 * 8) /* 4 banks, 8 registers each */ + len = 4 * 8 - start; + + for (ofs = start; ofs < len; ofs++) { + if (size/sizeof(*bits) <= 0) /* we drained out the buffer */ + break; + *bits = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTn(ofs)); + bits++; + size -= sizeof(*bits); + } + + return ofs - start; /* number of u32's that we saved to buffer */ +} + +/** + * otp_write_bits - store OTP bits + * + * @offset: offset from 0, in u32's + * @data: the u32 to write + * @magic: the magic value to be stored in UNLOCK field + * + **/ +static int otp_write_bits(int offset, u32 data, u32 magic) +{ + u32 c; + int r; + + BUG_ON(!mutex_is_locked(&otp_mutex)); + + if (offset < 0 || offset > 0x1F) + return -EINVAL; + + c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL); + c &= ~BM_OCOTP_CTRL_ADDR; + c |= BF(offset, OCOTP_CTRL_ADDR); + c |= BF(magic, OCOTP_CTRL_WR_UNLOCK); + __raw_writel(c, REGS_OCOTP_BASE + HW_OCOTP_CTRL); + + __raw_writel(data, REGS_OCOTP_BASE + HW_OCOTP_DATA); + + r = otp_wait_busy(0); + if (r < 0) + return r; + + udelay(2); + return 0; +} + +static ssize_t otp_id_show(void *context, char *page, int ascii) +{ + char s[60]; + int ret; + int n, i, j, r; + u32 otp_bits[4 * 8]; + + r = otp_open(O_RDONLY); + if (r < 0) + return 0; + n = otp_read_bits(0, 4 * 8, otp_bits, sizeof(otp_bits)); + otp_close(); + + ret = 0; + + + if (ascii) { + + strcpy(page, ""); + ret = 0; + + if (otp_full) { + for (i = 0; i < 4; i++) { + + ret += sprintf(s, "Bank %d: ", i); + strcat(page, s); + + for (j = 0; j < 8; j++) { + + if (i * 4 + j > n) + break; + ret += sprintf(s, "%08X ", + otp_bits[i * 4 + j]); + strcat(page, s); + } + + strcat(page, "\n"); + ret++; + } + } else { + for (i = 0; i < OTP_USER_SIZE; i++) { + ret += sprintf(s, "%08X ", + otp_bits[i + OTP_USER_OFFSET]); + strcat(page, s); + } + strcat(page, "\n"); + ret++; + } + } else { + + if (otp_full) { + memcpy(page, otp_bits, sizeof(otp_bits)); + ret = sizeof(otp_bits); + } else { + memcpy(page, otp_bits + OTP_USER_OFFSET, + OTP_USER_SIZE * sizeof(u32)); + ret = OTP_USER_SIZE * sizeof(u32); + } + } + + return ret; +} + +static int otp_check_dry_run(const char *page, size_t count) +{ + if (count >= 3 && memcmp(page, "+++", 3) == 0) + return 3; + return 0; +} + +static ssize_t otp_id_store(void *context, const char *page, + size_t count, int ascii) +{ + int r = 0; + const char *p, *cp, *d; + unsigned long index, value; + char tmps[20]; /* subject of strtoul */ + int dry_run; + + r = otp_open(O_WRONLY); + if (r < 0) { + printk(KERN_ERR"Cannot open OTP in WRITE mode\n"); + return r; + } + + if (ascii) { + + dry_run = otp_check_dry_run(page, count); + if (dry_run > 0) + page += dry_run; + + index = 0; + cp = page; + + memset(tmps, 0, sizeof(tmps)); + + for (index = 0, cp = page; cp != NULL; index++) { + p = strchr(cp, ','); + + d = strchr(cp, ':'); + if (d && (!p || d < p)) { + strncpy(tmps, cp, + min_t(int, d - cp, sizeof(tmps) - 1)); + r = strict_strtoul(tmps, 0, &index); + if (r < 0) { + pr_debug("Cannot parse '%s'\n", tmps); + break; + } + cp = d + 1; + } + + memset(tmps, 0, sizeof(tmps)); + + if (!p) + strncpy(tmps, cp, sizeof(tmps)); + else + strncpy(tmps, cp, + min_t(int, p - cp, sizeof(tmps) - 1)); + r = strict_strtoul(tmps, 0, &value); + if (r < 0) { + pr_debug("Cannot parse '%s'\n", tmps); + break; + } + + memset(tmps, 0, sizeof(tmps)); + + cp = p ? ++p : NULL; + + if (!otp_full) { + index += OTP_USER_OFFSET; + if (index > OTP_USER_SIZE) { + printk(KERN_ERR"Cannot write at " + "offset %ld\n", index); + continue; + } + } + + r = 0; + if (!dry_run) { + pr_debug("Index %ld, value 0x%08lx\n", + index, value); + r = otp_write_bits(index, value, 0x3e77); + } else + printk(KERN_NOTICE + "Dry-run: writing 0x%08lX => [%ld]\n", + value, index); + if (r < 0) + break; + } + } else { + printk(KERN_ERR"Binary write is not supported\n"); + r = -ENOSYS; + } + otp_close(); + return (r >= 0) ? count : r; +} + +static struct uid_ops otp_ops = { + .id_show = otp_id_show, + .id_store = otp_id_store, +}; + +static int __init_or_module otp_init(void) +{ + void *p; + + mutex_init(&otp_mutex); + p = uid_provider_init("otp", &otp_ops, NULL); + if (IS_ERR(p)) + return PTR_ERR(p); + return 0; +} + +static void __exit otp_remove(void) +{ + uid_provider_remove("otp"); +} + +module_param(otp_full, int, 0600); +module_init(otp_init); +module_exit(otp_remove); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("dmitry pervushin "); +MODULE_DESCRIPTION("Unique ID: OTP"); diff --git a/arch/arm/mach-mx28/include/mach/regs-ocotp.h b/arch/arm/mach-mx28/include/mach/regs-ocotp.h new file mode 100644 index 000000000000..7907250116ec --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-ocotp.h @@ -0,0 +1,239 @@ +/* + * Freescale OCOTP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.21 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___OCOTP_H +#define __ARCH_ARM___OCOTP_H + + +#define HW_OCOTP_CTRL (0x00000000) +#define HW_OCOTP_CTRL_SET (0x00000004) +#define HW_OCOTP_CTRL_CLR (0x00000008) +#define HW_OCOTP_CTRL_TOG (0x0000000c) + +#define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BF_OCOTP_CTRL_WR_UNLOCK(v) \ + (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK) +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77 +#define BP_OCOTP_CTRL_RSRVD2 14 +#define BM_OCOTP_CTRL_RSRVD2 0x0000C000 +#define BF_OCOTP_CTRL_RSRVD2(v) \ + (((v) << 14) & BM_OCOTP_CTRL_RSRVD2) +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 +#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 +#define BP_OCOTP_CTRL_RSRVD1 10 +#define BM_OCOTP_CTRL_RSRVD1 0x00000C00 +#define BF_OCOTP_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_CTRL_RSRVD1) +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_RSRVD0 6 +#define BM_OCOTP_CTRL_RSRVD0 0x000000C0 +#define BF_OCOTP_CTRL_RSRVD0(v) \ + (((v) << 6) & BM_OCOTP_CTRL_RSRVD0) +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000003F +#define BF_OCOTP_CTRL_ADDR(v) \ + (((v) << 0) & BM_OCOTP_CTRL_ADDR) + +#define HW_OCOTP_DATA (0x00000010) + +#define BP_OCOTP_DATA_DATA 0 +#define BM_OCOTP_DATA_DATA 0xFFFFFFFF +#define BF_OCOTP_DATA_DATA(v) (v) + +/* + * multi-register-define name HW_OCOTP_CUSTn + * base 0x00000020 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CUSTn(n) (0x00000020 + (n) * 0x10) +#define BP_OCOTP_CUSTn_BITS 0 +#define BM_OCOTP_CUSTn_BITS 0xFFFFFFFF +#define BF_OCOTP_CUSTn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_CRYPTOn + * base 0x00000060 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CRYPTOn(n) (0x00000060 + (n) * 0x10) +#define BP_OCOTP_CRYPTOn_BITS 0 +#define BM_OCOTP_CRYPTOn_BITS 0xFFFFFFFF +#define BF_OCOTP_CRYPTOn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_HWCAPn + * base 0x000000A0 + * count 6 + * offset 0x10 + */ +#define HW_OCOTP_HWCAPn(n) (0x000000a0 + (n) * 0x10) +#define BP_OCOTP_HWCAPn_BITS 0 +#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF +#define BF_OCOTP_HWCAPn_BITS(v) (v) + +#define HW_OCOTP_SWCAP (0x00000100) + +#define BP_OCOTP_SWCAP_BITS 0 +#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF +#define BF_OCOTP_SWCAP_BITS(v) (v) + +#define HW_OCOTP_CUSTCAP (0x00000110) + +#define BP_OCOTP_CUSTCAP_RSRVD1 3 +#define BM_OCOTP_CUSTCAP_RSRVD1 0xFFFFFFF8 +#define BF_OCOTP_CUSTCAP_RSRVD1(v) \ + (((v) << 3) & BM_OCOTP_CUSTCAP_RSRVD1) +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 0x00000004 +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 0x00000002 +#define BM_OCOTP_CUSTCAP_RSRVD0 0x00000001 + +#define HW_OCOTP_LOCK (0x00000120) + +#define BM_OCOTP_LOCK_ROM7 0x80000000 +#define BM_OCOTP_LOCK_ROM6 0x40000000 +#define BM_OCOTP_LOCK_ROM5 0x20000000 +#define BM_OCOTP_LOCK_ROM4 0x10000000 +#define BM_OCOTP_LOCK_ROM3 0x08000000 +#define BM_OCOTP_LOCK_ROM2 0x04000000 +#define BM_OCOTP_LOCK_ROM1 0x02000000 +#define BM_OCOTP_LOCK_ROM0 0x01000000 +#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x00800000 +#define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x00400000 +#define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x00200000 +#define BM_OCOTP_LOCK_PIN 0x00100000 +#define BM_OCOTP_LOCK_OPS 0x00080000 +#define BM_OCOTP_LOCK_UN2 0x00040000 +#define BM_OCOTP_LOCK_UN1 0x00020000 +#define BM_OCOTP_LOCK_UN0 0x00010000 +#define BM_OCOTP_LOCK_SRK 0x00008000 +#define BP_OCOTP_LOCK_UNALLOCATED 12 +#define BM_OCOTP_LOCK_UNALLOCATED 0x00007000 +#define BF_OCOTP_LOCK_UNALLOCATED(v) \ + (((v) << 12) & BM_OCOTP_LOCK_UNALLOCATED) +#define BM_OCOTP_LOCK_SRK_SHADOW 0x00000800 +#define BM_OCOTP_LOCK_ROM_SHADOW 0x00000400 +#define BM_OCOTP_LOCK_CUSTCAP 0x00000200 +#define BM_OCOTP_LOCK_HWSW 0x00000100 +#define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x00000080 +#define BM_OCOTP_LOCK_HWSW_SHADOW 0x00000040 +#define BM_OCOTP_LOCK_CRYPTODCP 0x00000020 +#define BM_OCOTP_LOCK_CRYPTOKEY 0x00000010 +#define BM_OCOTP_LOCK_CUST3 0x00000008 +#define BM_OCOTP_LOCK_CUST2 0x00000004 +#define BM_OCOTP_LOCK_CUST1 0x00000002 +#define BM_OCOTP_LOCK_CUST0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_OPSn + * base 0x00000130 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_OPSn(n) (0x00000130 + (n) * 0x10) +#define BP_OCOTP_OPSn_BITS 0 +#define BM_OCOTP_OPSn_BITS 0xFFFFFFFF +#define BF_OCOTP_OPSn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_UNn + * base 0x00000170 + * count 3 + * offset 0x10 + */ +#define HW_OCOTP_UNn(n) (0x00000170 + (n) * 0x10) +#define BP_OCOTP_UNn_BITS 0 +#define BM_OCOTP_UNn_BITS 0xFFFFFFFF +#define BF_OCOTP_UNn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_ROMn + * base 0x000001A0 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_ROMn(n) (0x000001a0 + (n) * 0x10) +#define BP_OCOTP_ROMn_BOOT_MODE 24 +#define BM_OCOTP_ROMn_BOOT_MODE 0xFF000000 +#define BF_OCOTP_ROMn_BOOT_MODE(v) \ + (((v) << 24) & BM_OCOTP_ROMn_BOOT_MODE) +#define BP_OCOTP_ROMn_SD_MMC_MODE 22 +#define BM_OCOTP_ROMn_SD_MMC_MODE 0x00C00000 +#define BF_OCOTP_ROMn_SD_MMC_MODE(v) \ + (((v) << 22) & BM_OCOTP_ROMn_SD_MMC_MODE) +#define BP_OCOTP_ROMn_SD_POWER_GATE_GPIO 20 +#define BM_OCOTP_ROMn_SD_POWER_GATE_GPIO 0x00300000 +#define BF_OCOTP_ROMn_SD_POWER_GATE_GPIO(v) \ + (((v) << 20) & BM_OCOTP_ROMn_SD_POWER_GATE_GPIO) +#define BP_OCOTP_ROMn_SD_POWER_UP_DELAY 14 +#define BM_OCOTP_ROMn_SD_POWER_UP_DELAY 0x000FC000 +#define BF_OCOTP_ROMn_SD_POWER_UP_DELAY(v) \ + (((v) << 14) & BM_OCOTP_ROMn_SD_POWER_UP_DELAY) +#define BP_OCOTP_ROMn_SD_BUS_WIDTH 12 +#define BM_OCOTP_ROMn_SD_BUS_WIDTH 0x00003000 +#define BF_OCOTP_ROMn_SD_BUS_WIDTH(v) \ + (((v) << 12) & BM_OCOTP_ROMn_SD_BUS_WIDTH) +#define BP_OCOTP_ROMn_SSP_SCK_INDEX 8 +#define BM_OCOTP_ROMn_SSP_SCK_INDEX 0x00000F00 +#define BF_OCOTP_ROMn_SSP_SCK_INDEX(v) \ + (((v) << 8) & BM_OCOTP_ROMn_SSP_SCK_INDEX) +#define BM_OCOTP_ROMn_EMMC_USE_DDR 0x00000080 +#define BM_OCOTP_ROMn_DISABLE_SPI_NOR_FAST_READ 0x00000040 +#define BM_OCOTP_ROMn_ENABLE_USB_BOOT_SERIAL_NUM 0x00000020 +#define BM_OCOTP_ROMn_ENABLE_UNENCRYPTED_BOOT 0x00000010 +#define BM_OCOTP_ROMn_SD_MBR_BOOT 0x00000008 +#define BM_OCOTP_ROMn_RSRVD2 0x00000004 +#define BM_OCOTP_ROMn_RSRVD1 0x00000002 +#define BM_OCOTP_ROMn_RSRVD0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_SRKn + * base 0x00000220 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_SRKn(n) (0x00000220 + (n) * 0x10) +#define BP_OCOTP_SRKn_BITS 0 +#define BM_OCOTP_SRKn_BITS 0xFFFFFFFF +#define BF_OCOTP_SRKn_BITS(v) (v) + +#define HW_OCOTP_VERSION (0x000002a0) + +#define BP_OCOTP_VERSION_MAJOR 24 +#define BM_OCOTP_VERSION_MAJOR 0xFF000000 +#define BF_OCOTP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_OCOTP_VERSION_MAJOR) +#define BP_OCOTP_VERSION_MINOR 16 +#define BM_OCOTP_VERSION_MINOR 0x00FF0000 +#define BF_OCOTP_VERSION_MINOR(v) \ + (((v) << 16) & BM_OCOTP_VERSION_MINOR) +#define BP_OCOTP_VERSION_STEP 0 +#define BM_OCOTP_VERSION_STEP 0x0000FFFF +#define BF_OCOTP_VERSION_STEP(v) \ + (((v) << 0) & BM_OCOTP_VERSION_STEP) +#endif /* __ARCH_ARM___OCOTP_H */ diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c new file mode 100644 index 000000000000..a2a3c82fba77 --- /dev/null +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -0,0 +1,3554 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" + +static struct clk pll1_main_clk; +static struct clk pll1_sw_clk; +static struct clk pll2_sw_clk; +static struct clk pll3_sw_clk; +static struct clk apbh_dma_clk; +static struct clk apll_clk; +static struct clk pfd0_clk; +static struct clk pfd1_clk; +static struct clk pfd2_clk; +static struct clk pfd3_clk; +static struct clk pfd4_clk; +static struct clk pfd5_clk; +static struct clk pfd6_clk; +static struct clk pfd7_clk; +static struct clk lp_apm_clk; +static struct clk weim_clk[]; +static struct clk ddr_clk; +static struct clk axi_a_clk; +static struct clk axi_b_clk; +static struct clk gpu2d_clk; +static int cpu_curr_wp; +static struct cpu_wp *cpu_wp_tbl; + +static void __iomem *pll1_base; +static void __iomem *pll2_base; +static void __iomem *pll3_base; +static void __iomem *apll_base; + +extern int cpu_wp_nr; +extern int lp_high_freq; +extern int lp_med_freq; +void __iomem *databahn; + +#define DDR_SYNC_MODE 0x30000 +#define SPIN_DELAY 1000000 /* in nanoseconds */ +#define WAIT(exp, timeout) \ +({ \ + struct timespec nstimeofday; \ + struct timespec curtime; \ + int result = 1; \ + getnstimeofday(&nstimeofday); \ + while (!(exp)) { \ + getnstimeofday(&curtime); \ + if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \ + result = 0; \ + break; \ + } \ + } \ + result; \ +}) + +extern int mxc_jtag_enabled; +extern int uart_at_24; +extern int cpufreq_trig_needed; +extern int low_bus_freq_mode; + +static int cpu_clk_set_wp(int wp); +extern void propagate_rate(struct clk *tclk); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); + +static struct clk esdhc3_clk[]; + +static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) +{ + u32 min_pre, temp_pre, old_err, err; + + if (div >= 512) { + *pre = 8; + *post = 64; + } else if (div >= 8) { + min_pre = (div - 1) / 64 + 1; + old_err = 8; + for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { + err = div % temp_pre; + if (err == 0) { + *pre = temp_pre; + break; + } + err = temp_pre - err; + if (err < old_err) { + old_err = err; + *pre = temp_pre; + } + } + *post = (div + *pre - 1) / *pre; + } else if (div < 8) { + *pre = div; + *post = 1; + } +} + +static int _clk_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq++; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq++; + + return 0; +} + +static int _clk_enable_inrun(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq--; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq--; +} + +static void _clk_disable_inwait(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); +} + +static unsigned long _clk_round_rate_div(struct clk *clk, + unsigned long rate, + u32 max_div, + u32 *new_div) +{ + u32 div; + + div = DIV_ROUND_UP(clk->parent->rate, rate); + if (div > max_div) + div = max_div; + else if (div == 0) + div++; + if (new_div != NULL) + *new_div = div; + + return clk->parent->rate / div; +} +/* + * For the 4-to-1 muxed input clock + */ +static inline u32 _get_mux(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, struct clk *m3) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else + BUG(); + + return 0; +} + +/* + * For the 4-to-1 muxed input clock + */ +static inline u32 _get_mux8(struct clk *parent, struct clk *m0, struct clk *m1, + struct clk *m2, struct clk *m3, struct clk *m4, + struct clk *m5, struct clk *m6, struct clk *m7) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else if (parent == m4) + return 4; + else if (parent == m5) + return 5; + else if (parent == m6) + return 6; + else if (parent == m7) + return 7; + else + BUG(); + + return 0; +} + +static inline void __iomem *_get_pll_base(struct clk *pll) +{ + if (pll == &pll1_main_clk) + return pll1_base; + else if (pll == &pll2_sw_clk) + return pll2_base; + else if (pll == &pll3_sw_clk) + return pll3_base; + else + BUG(); + + return NULL; +} + +static struct clk ckih_clk = { + .name = "ckih", + .flags = RATE_PROPAGATES, +}; + +static struct clk ckih2_clk = { + .name = "ckih2", + .flags = RATE_PROPAGATES, +}; + +static struct clk osc_clk = { + .name = "osc", + .flags = RATE_PROPAGATES, +}; + +static int apll_enable(struct clk *clk) +{ + __raw_writel(1, apll_base + MXC_ANADIG_MISC_SET); + return 0; +} + +static void apll_disable(struct clk *clk) +{ + __raw_writel(1, apll_base + MXC_ANADIG_MISC_CLR); +} + +static struct clk apll_clk = { + .name = "apll", + .rate = 480000000, + .enable = apll_enable, + .disable = apll_disable, + .flags = RATE_PROPAGATES, +}; + +static void pfd_recalc(struct clk *clk) +{ + u32 frac; + u64 rate; + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.enable(&apbh_dma_clk); + frac = __raw_readl(apll_base + + (int)clk->enable_reg) >> clk->enable_shift; + frac &= MXC_ANADIG_PFD_FRAC_MASK; + rate = (u64)clk->parent->rate * 18; + do_div(rate, frac); + clk->rate = rate; + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.disable(&apbh_dma_clk); +} + +static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate) +{ + u32 frac; + u64 tmp; + tmp = (u64)clk->parent->rate * 18; + do_div(tmp, rate); + frac = tmp; + frac = frac < 18 ? 18 : frac; + frac = frac > 35 ? 35 : frac; + do_div(tmp, frac); + return tmp; +} + +static int pfd_set_rate(struct clk *clk, unsigned long rate) +{ + u32 frac; + u64 tmp; + + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.enable(&apbh_dma_clk); + tmp = (u64)clk->parent->rate * 18; + do_div(tmp, rate); + frac = tmp; + frac = frac < 18 ? 18 : frac; + frac = frac > 35 ? 35 : frac; + /* clear clk frac bits */ + __raw_writel(MXC_ANADIG_PFD_FRAC_MASK << clk->enable_shift, + apll_base + (int)clk->enable_reg + 8); + /* set clk frac bits */ + __raw_writel(frac << clk->enable_shift, + apll_base + (int)clk->enable_reg + 4); + + tmp = (u64)clk->parent->rate * 18; + do_div(tmp, frac); + clk->rate = tmp; + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.disable(&apbh_dma_clk); + return 0; +} + +static int pfd_enable(struct clk *clk) +{ + int index; + + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.enable(&apbh_dma_clk); + index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk, + &pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk); + __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET), + apll_base + MXC_ANADIG_PLLCTRL_CLR); + /* clear clk gate bit */ + __raw_writel((1 << (clk->enable_shift + 7)), + apll_base + (int)clk->enable_reg + 8); + + /* check lock bit */ + if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) + & MXC_ANADIG_APLL_LOCK, 50000)) { + __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK, + apll_base + MXC_ANADIG_PLLCTRL_CLR); + __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK, + apll_base + MXC_ANADIG_PLLCTRL_SET); + if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) + & MXC_ANADIG_APLL_LOCK, SPIN_DELAY)) + panic("pfd_enable failed!\n"); + } + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.disable(&apbh_dma_clk); + return 0; +} + +static void pfd_disable(struct clk *clk) +{ + int index; + + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.enable(&apbh_dma_clk); + index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk, + &pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk); + /* set clk gate bit */ + __raw_writel((1 << (clk->enable_shift + 7)), + apll_base + (int)clk->enable_reg + 4); + __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET), + apll_base + MXC_ANADIG_PLLCTRL_SET); + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.disable(&apbh_dma_clk); +} + +static struct clk pfd0_clk = { + .name = "pfd0", + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC0, + .enable_shift = MXC_ANADIG_PFD0_FRAC_OFFSET, + .recalc = pfd_recalc, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk pfd1_clk = { + .name = "pfd1", + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC0, + .enable_shift = MXC_ANADIG_PFD1_FRAC_OFFSET, + .recalc = pfd_recalc, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk pfd2_clk = { + .name = "pfd2", + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC0, + .enable_shift = MXC_ANADIG_PFD2_FRAC_OFFSET, + .recalc = pfd_recalc, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk pfd3_clk = { + .name = "pfd3", + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC0, + .enable_shift = MXC_ANADIG_PFD3_FRAC_OFFSET, + .recalc = pfd_recalc, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk pfd4_clk = { + .name = "pfd4", + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC1, + .enable_shift = MXC_ANADIG_PFD4_FRAC_OFFSET, + .recalc = pfd_recalc, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk pfd5_clk = { + .name = "pfd5", + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC1, + .enable_shift = MXC_ANADIG_PFD5_FRAC_OFFSET, + .recalc = pfd_recalc, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk pfd6_clk = { + .name = "pfd6", + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC1, + .enable_shift = MXC_ANADIG_PFD6_FRAC_OFFSET, + .recalc = pfd_recalc, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk pfd7_clk = { + .name = "pfd7", + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC1, + .enable_shift = MXC_ANADIG_PFD7_FRAC_OFFSET, + .recalc = pfd_recalc, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk ckil_clk = { + .name = "ckil", + .flags = RATE_PROPAGATES, +}; + +static void _clk_pll_recalc(struct clk *clk) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; + void __iomem *pllbase; + s64 temp; + + pllbase = _get_pll_base(clk); + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; + + if (pll_hfsm == 0) { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); + } else { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); + } + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; + /* Sign extend to 32-bits */ + if (mfn >= 0x04000000) { + mfn |= 0xFC000000; + mfn_abs = -mfn; + } + + ref_clk = 2 * clk->parent->rate; + if (dbl != 0) + ref_clk *= 2; + + ref_clk /= (pdf + 1); + temp = (u64) ref_clk * mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + clk->rate = temp; +} + +static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, reg1; + void __iomem *pllbase; + + long mfi, pdf, mfn, mfd = 999999; + s64 temp64; + unsigned long quad_parent_rate; + unsigned long pll_hfsm, dp_ctl; + + pllbase = _get_pll_base(clk); + + quad_parent_rate = 4*clk->parent->rate; + pdf = mfi = -1; + while (++pdf < 16 && mfi < 5) + mfi = rate * (pdf+1) / quad_parent_rate; + if (mfi > 15) + return -1; + pdf--; + + temp64 = rate*(pdf+1) - quad_parent_rate*mfi; + do_div(temp64, quad_parent_rate/1000000); + mfn = (long)temp64; + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + /* use dpdck0_2 */ + __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + if (pll_hfsm == 0) { + reg = mfi<<4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); + } else { + reg = mfi<<4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); + } + /* If auto restart is disabled, restart the PLL and + * wait for it to lock. + */ + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); + if (reg & MXC_PLL_DP_CTL_UPEN) { + reg = __raw_readl(pllbase + MXC_PLL_DP_CONFIG); + if (!(reg & MXC_PLL_DP_CONFIG_AREN)) { + reg1 = __raw_readl(pllbase + MXC_PLL_DP_CTL); + reg1 |= MXC_PLL_DP_CTL_RST; + __raw_writel(reg1, pllbase + MXC_PLL_DP_CTL); + } + /* Wait for lock */ + if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL) + & MXC_PLL_DP_CTL_LRF, SPIN_DELAY)) + panic("pll_set_rate: pll relock failed\n"); + } + clk->rate = rate; + return 0; +} + +static int _clk_pll_enable(struct clk *clk) +{ + u32 reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); + + if (reg & MXC_PLL_DP_CTL_UPEN) + return 0; + + reg |= MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); + + /* Wait for lock */ + if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF, + SPIN_DELAY)) + panic("pll relock failed\n"); + return 0; +} + +static void _clk_pll_disable(struct clk *clk) +{ + u32 reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); +} + +static struct clk pll1_main_clk = { + .name = "pll1_main_clk", + .parent = &osc_clk, + .recalc = _clk_pll_recalc, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CCSR); + + if (parent == &pll1_main_clk) { + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + /* Set the step_clk parent to be lp_apm, to save power. */ + mux = _get_mux(&lp_apm_clk, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = __raw_readl(MXC_CCM_CCSR); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + } else { + if (parent == &lp_apm_clk) { + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + reg = __raw_readl(MXC_CCM_CCSR); + mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + } else { + mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CCSR); + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + + } + } + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static void _clk_pll1_sw_recalc(struct clk *clk) +{ + u32 reg, div; + div = 1; + reg = __raw_readl(MXC_CCM_CCSR); + + if (clk->parent == &pll2_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> + MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; + } else if (clk->parent == &pll3_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> + MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; + } + clk->rate = clk->parent->rate / div; +} + +/* pll1 switch clock */ +static struct clk pll1_sw_clk = { + .name = "pll1_sw_clk", + .parent = &pll1_main_clk, + .set_parent = _clk_pll1_sw_set_parent, + .recalc = _clk_pll1_sw_recalc, + .flags = RATE_PROPAGATES, +}; + +static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCSR); + + if (parent == &pll2_sw_clk) { + reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; + } else { + reg = (reg & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL); + reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; + } + __raw_writel(reg, MXC_CCM_CCSR); + return 0; +} + +/* same as pll2_main_clk. These two clocks should always be the same */ +static struct clk pll2_sw_clk = { + .name = "pll2", + .parent = &osc_clk, + .recalc = _clk_pll_recalc, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_pll_set_rate, + .set_parent = _clk_pll2_sw_set_parent, + .flags = RATE_PROPAGATES, +}; + +/* same as pll3_main_clk. These two clocks should always be the same */ +static struct clk pll3_sw_clk = { + .name = "pll3", + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .recalc = _clk_pll_recalc, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + if (parent == &osc_clk) + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; + else if (parent == &apll_clk) + reg = __raw_readl(MXC_CCM_CCSR) | MXC_CCM_CCSR_LP_APM_SEL; + else + return -EINVAL; + + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static struct clk lp_apm_clk = { + .name = "lp_apm", + .parent = &osc_clk, + .set_parent = _clk_lp_apm_set_parent, + .flags = RATE_PROPAGATES, +}; + +static void _clk_arm_recalc(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; + clk->rate = clk->parent->rate / div; +} + +static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) +{ + u32 i; + for (i = 0; i < cpu_wp_nr; i++) { + if (rate == cpu_wp_tbl[i].cpu_rate) + break; + } + if (i >= cpu_wp_nr) + return -EINVAL; + cpu_clk_set_wp(i); + + return 0; +} + +static unsigned long _clk_cpu_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 i; + u32 wp; + + for (i = 0; i < cpu_wp_nr; i++) { + if (rate == cpu_wp_tbl[i].cpu_rate) + break; + } + + if (i > cpu_wp_nr) + wp = 0; + + return cpu_wp_tbl[wp].cpu_rate; +} + + +static struct clk cpu_clk = { + .name = "cpu_clk", + .parent = &pll1_sw_clk, + .recalc = _clk_arm_recalc, + .set_rate = _clk_cpu_set_rate, + .round_rate = _clk_cpu_round_rate, +}; + +/* TODO: Need to sync with GPC to determine if DVFS is in place so that + * the DVFS_PODF divider can be applied in CDCR register. + */ +static void _clk_main_bus_recalc(struct clk *clk) +{ + u32 div = 0; + + if (dvfs_per_divider_active() || low_bus_freq_mode) + div = (__raw_readl(MXC_CCM_CDCR) & 0x3); + clk->rate = clk->parent->rate / (div + 1); +} + +static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CBCDR) & ~MX50_CCM_CBCDR_PERIPH_CLK_SEL_MASK; + reg |= (mux << MX50_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + return 0; +} + +static struct clk main_bus_clk = { + .name = "main_bus_clk", + .parent = &pll2_sw_clk, + .set_parent = _clk_main_bus_set_parent, + .recalc = _clk_main_bus_recalc, + .flags = RATE_PROPAGATES, +}; + +static void _clk_axi_a_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AXI_A_PODF_MASK) >> + MXC_CCM_CBCDR_AXI_A_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) + & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY), SPIN_DELAY)) + panic("pll _clk_axi_a_set_rate failed\n"); + clk->rate = rate; + + return 0; +} + +static unsigned long _clk_axi_a_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + + +static struct clk axi_a_clk = { + .name = "axi_a_clk", + .parent = &main_bus_clk, + .recalc = _clk_axi_a_recalc, + .set_rate = _clk_axi_a_set_rate, + .round_rate = _clk_axi_a_round_rate, + .flags = RATE_PROPAGATES, +}; + +static void _clk_axi_b_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AXI_B_PODF_MASK) >> + MXC_CCM_CBCDR_AXI_B_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) + & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY), SPIN_DELAY)) + panic("_clk_axi_b_set_rate failed\n"); + + clk->rate = rate; + + return 0; +} + +static unsigned long _clk_axi_b_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + + +static struct clk axi_b_clk = { + .name = "axi_b_clk", + .parent = &main_bus_clk, + .recalc = _clk_axi_b_recalc, + .set_rate = _clk_axi_b_set_rate, + .round_rate = _clk_axi_b_round_rate, + .flags = RATE_PROPAGATES, +}; + +static void _clk_ahb_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + + +static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY), + SPIN_DELAY)) + panic("_clk_ahb_set_rate failed\n"); + clk->rate = rate; + + return 0; +} + +static unsigned long _clk_ahb_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + + +static struct clk ahb_clk = { + .name = "ahb_clk", + .parent = &main_bus_clk, + .recalc = _clk_ahb_recalc, + .set_rate = _clk_ahb_set_rate, + .round_rate = _clk_ahb_round_rate, + .flags = RATE_PROPAGATES, +}; + +static int _clk_max_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + + /* Handshake with MAX when LPM is entered. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + + +static void _clk_max_disable(struct clk *clk) +{ + u32 reg; + + _clk_disable_inwait(clk); + + /* No Handshake with MAX when LPM is entered as its disabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + + +static struct clk ahb_max_clk = { + .name = "max_clk", + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG14_OFFSET, + .enable = _clk_max_enable, + .disable = _clk_max_disable, +}; + + +static struct clk ahbmux1_clk = { + .name = "ahbmux1_clk", + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG8_OFFSET, + .disable = _clk_disable_inwait, +}; + +static void _clk_ipg_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static struct clk ipg_clk = { + .name = "ipg_clk", + .parent = &ahb_clk, + .recalc = _clk_ipg_recalc, + .flags = RATE_PROPAGATES, +}; + +static void _clk_ipg_per_recalc(struct clk *clk) +{ + u32 reg, prediv1, prediv2, podf; + + if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { + /* the main_bus_clk is the one before the DVFS engine */ + reg = __raw_readl(MXC_CCM_CBCDR); + prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; + prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; + podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (prediv1 * prediv2 * podf); + } else if (clk->parent == &ipg_clk) { + clk->rate = ipg_clk.rate; + } else { + BUG(); + } +} + +static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &main_bus_clk, &lp_apm_clk, &ipg_clk, NULL); + if (mux == 2) { + reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + } else { + reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + if (mux == 0) + reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + else + reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + } + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk ipg_perclk = { + .name = "ipg_perclk", + .parent = &lp_apm_clk, + .recalc = _clk_ipg_per_recalc, + .set_parent = _clk_ipg_per_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk ipmux1_clk = { + .name = "ipmux1", + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk ipmux2_clk = { + .name = "ipmux2", + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static int _clk_sys_clk_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg &= ~(MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK | + MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK); + if (__raw_readl(MXC_CCM_CLKSEQ_BYPASS) & 0x1) + reg |= MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK; + else + reg |= MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_CLK_SYS); + return 0; +} + +static void _clk_sys_clk_disable(struct clk *clk) +{ + u32 reg, reg1; + + reg1 = (__raw_readl(databahn + DATABAHN_CTL_REG55)) + & DDR_SYNC_MODE; + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg &= ~(MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK | + MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK); + if (__raw_readl(MXC_CCM_CLKSEQ_BYPASS) & 0x1) + reg |= 1 << MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET; + else { + /* If DDR is sourced from SYS_CLK (in Sync mode), we cannot + * gate its clock when ARM is in wait if the DDR is not in + * self refresh. + */ + if (reg1 == DDR_SYNC_MODE) + reg |= 3 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET; + else + reg |= 1 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET; + } + __raw_writel(reg, MXC_CCM_CLK_SYS); +} + +static struct clk sys_clk = { + .name = "sys_clk", + .enable = _clk_sys_clk_enable, + .disable = _clk_sys_clk_disable, +}; + + +static int _clk_weim_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CBCDR); + if (parent == &ahb_clk) + reg |= MX50_CCM_CBCDR_WEIM_CLK_SEL; + else if (parent == &main_bus_clk) + reg &= ~MX50_CCM_CBCDR_WEIM_CLK_SEL; + else + BUG(); + __raw_writel(reg, MXC_CCM_CBCDR); + + return 0; +} + +static void _clk_weim_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >> + MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static int _clk_weim_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY), + SPIN_DELAY)) + panic("_clk_emi_slow_set_rate failed\n"); + clk->rate = rate; + + return 0; +} + +static unsigned long _clk_weim_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + +static struct clk weim_clk[] = { + { + .name = "weim_clk", + .parent = &main_bus_clk, + .set_parent = _clk_weim_set_parent, + .recalc = _clk_weim_recalc, + .set_rate = _clk_weim_set_rate, + .round_rate = _clk_weim_round_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG8_OFFSET, + .disable = _clk_disable_inwait, + .flags = RATE_PROPAGATES, + .secondary = &weim_clk[1], + }, + { + .name = "weim_ipg_clk", + .parent = &ipg_clk, + .secondary = &sys_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG9_OFFSET, + .disable = _clk_disable_inwait, + } +}; + +static int _clk_ocram_enable(struct clk *clk) +{ + return 0; +} + +static void _clk_ocram_disable(struct clk *clk) +{ +} + +static struct clk ocram_clk = { + .name = "ocram_clk", + .parent = &sys_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG1_OFFSET, + .enable = _clk_ocram_enable, + .disable = _clk_ocram_disable, +}; + +static struct clk aips_tz1_clk = { + .name = "aips_tz1_clk", + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk aips_tz2_clk = { + .name = "aips_tz2_clk", + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk gpc_dvfs_clk = { + .name = "gpc_dvfs_clk", + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static int _clk_sdma_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + + /* Handshake with SDMA when LPM is entered. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static void _clk_sdma_disable(struct clk *clk) +{ + u32 reg; + + _clk_disable(clk); + /* No handshake with SDMA as its not enabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + + +static struct clk sdma_clk[] = { + { + .name = "sdma_ahb_clk", + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG15_OFFSET, + .enable = _clk_sdma_enable, + .disable = _clk_sdma_disable, + }, + { + .name = "sdma_ipg_clk", + .parent = &ipg_clk, + .secondary = &ddr_clk, + }, +}; + +static struct clk spba_clk = { + .name = "spba_clk", + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static void _clk_uart_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk uart_main_clk = { + .name = "uart_main_clk", + .parent = &pll2_sw_clk, + .recalc = _clk_uart_recalc, + .set_parent = _clk_uart_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk uart1_clk[] = { + { + .name = "uart_clk", + .id = 0, + .parent = &uart_main_clk, + .secondary = &uart1_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#ifdef UART1_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .name = "uart_ipg_clk", + .id = 0, + .parent = &ipg_clk, +#ifdef UART1_DMA_ENABLE + .secondary = &aips_tz1_clk, +#endif + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG3_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart2_clk[] = { + { + .name = "uart_clk", + .id = 1, + .parent = &uart_main_clk, + .secondary = &uart2_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#ifdef UART2_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .name = "uart_ipg_clk", + .id = 1, + .parent = &ipg_clk, +#ifdef UART2_DMA_ENABLE + .secondary = &aips_tz1_clk, +#endif + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart3_clk[] = { + { + .name = "uart_clk", + .id = 2, + .parent = &uart_main_clk, + .secondary = &uart3_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#ifdef UART3_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .name = "uart_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart4_clk[] = { + { + .name = "uart_clk", + .id = 3, + .parent = &uart_main_clk, + .secondary = &uart4_clk[1], + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#ifdef UART4_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .name = "uart_ipg_clk", + .id = 3, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart5_clk[] = { + { + .name = "uart_clk", + .id = 4, + .parent = &uart_main_clk, + .secondary = &uart5_clk[1], + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#ifdef UART5_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .name = "uart_ipg_clk", + .id = 4, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk gpt_clk[] = { + { + .name = "gpt_clk", + .parent = &ipg_perclk, + .id = 0, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "gpt_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "gpt_32k_clk", + .id = 0, + .parent = &ckil_clk, + }, +}; + +static struct clk pwm1_clk[] = { + { + .name = "pwm", + .parent = &ipg_perclk, + .id = 0, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &pwm1_clk[1], + }, + { + .name = "pwm_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG5_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, + { + .name = "pwm_32k_clk", + .id = 0, + .parent = &ckil_clk, + }, +}; + +static struct clk pwm2_clk[] = { + { + .name = "pwm", + .parent = &ipg_perclk, + .id = 1, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &pwm2_clk[1], + }, + { + .name = "pwm_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG7_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, + { + .name = "pwm_32k_clk", + .id = 1, + .parent = &ckil_clk, + }, +}; + +static struct clk i2c_clk[] = { + { + .name = "i2c_clk", + .id = 0, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "i2c_clk", + .id = 1, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "i2c_clk", + .id = 2, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static void _clk_cspi_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR2); + prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_cspi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk cspi_main_clk = { + .name = "cspi_main_clk", + .parent = &pll3_sw_clk, + .recalc = _clk_cspi_recalc, + .set_parent = _clk_cspi_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk cspi1_clk[] = { + { + .name = "cspi_clk", + .id = 0, + .parent = &cspi_main_clk, + .secondary = &cspi1_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "cspi_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG9_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, +}; + +static struct clk cspi2_clk[] = { + { + .name = "cspi_clk", + .id = 1, + .parent = &cspi_main_clk, + .secondary = &cspi2_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "cspi_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .secondary = &aips_tz2_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG11_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, +}; + +static struct clk cspi3_clk = { + .name = "cspi_clk", + .id = 2, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &aips_tz2_clk, +}; + +static int _clk_ssi_lp_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &ckih_clk, &lp_apm_clk, &ckih2_clk, NULL); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi_lp_apm_clk = { + .name = "ssi_lp_apm_clk", + .parent = &ckih_clk, + .set_parent = _clk_ssi_lp_apm_set_parent, +}; + +static void _clk_ssi1_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS1CDR); + prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK) >> + MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} +static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi1_clk[] = { + { + .name = "ssi_clk", + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi1_set_parent, + .secondary = &ssi1_clk[1], + .recalc = _clk_ssi1_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &ssi1_clk[2], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_dep_clk", + .id = 0, + .parent = &aips_tz2_clk, + }, +}; + +static void _clk_ssi2_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS2CDR); + prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK) >> + MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK) >> + MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi2_clk[] = { + { + .name = "ssi_clk", + .id = 1, + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi2_set_parent, + .secondary = &ssi2_clk[1], + .recalc = _clk_ssi2_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .secondary = &ssi2_clk[2], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_dep_clk", + .id = 1, + .parent = &spba_clk, + }, +}; + +static void _clk_ssi_ext1_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + clk->rate = clk->parent->rate; + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CS1CDR); + prediv = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK) >> + MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (prediv * podf); + } +} + +static int _clk_ssi_ext1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || div > 512) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~(MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK | + MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS1CDR); + + clk->rate = rate; + + return 0; +} + +static int _clk_ssi_ext1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &ssi1_clk[0]) { + reg |= MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL; + } else { + reg &= ~MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &ssi_lp_apm_clk); + reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_ssi_ext1_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 pre, post; + u32 div = clk->parent->rate / rate; + + if (clk->parent->rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return clk->parent->rate / (pre * post); +} + +static struct clk ssi_ext1_clk = { + .name = "ssi_ext1_clk", + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi_ext1_set_parent, + .set_rate = _clk_ssi_ext1_set_rate, + .round_rate = _clk_ssi_ext1_round_rate, + .recalc = _clk_ssi_ext1_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static void _clk_ssi_ext2_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + clk->rate = clk->parent->rate; + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CS2CDR); + prediv = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK) >> + MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK) >> + MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (prediv * podf); + } +} + +static int _clk_ssi_ext2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &ssi2_clk[0]) { + reg |= MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL; + } else { + reg &= ~MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &ssi_lp_apm_clk); + reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi_ext2_clk = { + .name = "ssi_ext2_clk", + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi_ext2_set_parent, + .recalc = _clk_ssi_ext2_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG15_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk tmax2_clk = { + .name = "tmax2_clk", + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG1_OFFSET, + .disable = _clk_disable, +}; + +static struct clk usb_ahb_clk = { + .name = "usb_ahb_clk", + .parent = &ipg_clk, + .secondary = &ddr_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG13_OFFSET, + .disable = _clk_disable, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk usb_phy_clk[] = { + { + .name = "usb_phy1_clk", + .id = 0, + .parent = &osc_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG5_OFFSET, + .disable = _clk_disable, + }, + { + .name = "usb_phy2_clk", + .id = 1, + .parent = &osc_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG6_OFFSET, + .disable = _clk_disable, + } +}; + +static struct clk esdhc_dep_clks = { + .name = "sd_dep_clk", + .parent = &spba_clk, + .secondary = &ddr_clk, +}; + +static void _clk_esdhc1_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = reg & ~MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK; + reg |= mux << MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + + +static int _clk_esdhc1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set sdhc1 clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR1) & + ~(MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK | + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + clk->rate = rate; + return 0; +} + +static struct clk esdhc1_clk[] = { + { + .name = "esdhc_clk", + .id = 0, + .parent = &pll2_sw_clk, + .set_parent = _clk_esdhc1_set_parent, + .recalc = _clk_esdhc1_recalc, + .set_rate = _clk_esdhc1_set_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG1_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc1_clk[1], + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .name = "esdhc_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &esdhc1_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG0_OFFSET, + .disable = _clk_disable, + }, + { + .name = "esdhc_sec_clk", + .id = 0, + .parent = &tmax2_clk, + .secondary = &esdhc_dep_clks, + }, + +}; + +static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MX50_CCM_CSCMR1_ESDHC2_CLK_SEL; + else if (parent == &esdhc3_clk[0]) + reg |= MX50_CCM_CSCMR1_ESDHC2_CLK_SEL; + else + BUG(); + __raw_writel(reg, MXC_CCM_CSCMR1); + return 0; +} + +static struct clk esdhc2_clk[] = { + { + .name = "esdhc_clk", + .id = 1, + .parent = &esdhc1_clk[0], + .set_parent = _clk_esdhc2_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG3_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc2_clk[1], + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .name = "esdhc_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .secondary = &esdhc2_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG2_OFFSET, + .disable = _clk_disable, + }, + { + .name = "esdhc_sec_clk", + .id = 0, + .parent = &tmax2_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + mux = _get_mux8(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &lp_apm_clk, &pfd0_clk, + &pfd1_clk, &pfd4_clk, &osc_clk); + reg = reg & ~MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK; + reg |= mux << MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static void _clk_esdhc3_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_esdhc3_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set sdhc1 clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR1) & + ~(MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK | + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + clk->rate = rate; + return 0; +} + + +static struct clk esdhc3_clk[] = { + { + .name = "esdhc_clk", + .id = 2, + .parent = &pll2_sw_clk, + .set_parent = _clk_esdhc3_set_parent, + .recalc = _clk_esdhc3_recalc, + .set_rate = _clk_esdhc3_set_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG5_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc3_clk[1], + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .name = "esdhc_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .secondary = &esdhc3_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG4_OFFSET, + .disable = _clk_disable, + }, + { + .name = "esdhc_sec_clk", + .id = 0, + .parent = &ahb_max_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MX50_CCM_CSCMR1_ESDHC4_CLK_SEL; + else if (parent == &esdhc3_clk[0]) + reg |= MX50_CCM_CSCMR1_ESDHC4_CLK_SEL; + else + BUG(); + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk esdhc4_clk[] = { + { + .name = "esdhc_clk", + .id = 3, + .parent = &esdhc1_clk[0], + .set_parent = _clk_esdhc4_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG7_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc4_clk[1], + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .name = "esdhc_ipg_clk", + .id = 3, + .parent = &ipg_clk, + .secondary = &esdhc4_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG6_OFFSET, + .disable = _clk_disable, + }, + { + .name = "esdhc_sec_clk", + .id = 0, + .parent = &tmax2_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CLK_DDR); + if (parent == &pfd0_clk) + reg |= MXC_CCM_CLK_DDR_DDR_PFD_SEL; + else if (parent == &pll1_sw_clk) + reg &= ~MXC_CCM_CLK_DDR_DDR_PFD_SEL; + else + return -EINVAL; + __raw_writel(reg, MXC_CCM_CLK_DDR); + return 0; +} + +static void _clk_ddr_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CLK_DDR); + div = (reg & MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK) >> + MXC_CCM_CLK_DDR_DDR_DIV_PLL_OFFSET; + if (div) + clk->rate = clk->parent->rate / div; + else + clk->rate = 0; +} + +static int _clk_ddr_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + reg = (__raw_readl(databahn + DATABAHN_CTL_REG55)) & + DDR_SYNC_MODE; + if (reg != DDR_SYNC_MODE) { + reg = __raw_readl(MXC_CCM_CLK_DDR); + reg |= MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_CLK_DDR); + } + return 0; +} + +static void _clk_ddr_disable(struct clk *clk) +{ + _clk_disable_inwait(clk); +} + + +static struct clk ddr_clk = { + .name = "ddr_clk", + .parent = &pll1_sw_clk, + .secondary = &sys_clk, + .set_parent = _clk_ddr_set_parent, + .recalc = _clk_ddr_recalc, + .enable = _clk_ddr_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG15_OFFSET, + .disable = _clk_ddr_disable, +}; + +static void _clk_pgc_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR1); + div = (reg & MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET; + div = 1 >> div; + clk->rate = clk->parent->rate / div; +} + +static struct clk pgc_clk = { + .name = "pgc_clk", + .parent = &ipg_clk, + .recalc = _clk_pgc_recalc, +}; + +/*usb OTG clock */ +static struct clk usb_clk = { + .name = "usb_clk", + .rate = 60000000, +}; + +static struct clk rtc_clk = { + .name = "rtc_clk", + .parent = &ckil_clk, + .secondary = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG14_OFFSET, + .disable = _clk_disable, +}; + +struct clk rng_clk = { + .name = "rng_clk", + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG1_OFFSET, + .disable = _clk_disable, +}; + +static struct clk owire_clk = { + /* 1w driver come from upstream and use owire as clock name*/ + .name = "owire", + .parent = &ipg_perclk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG11_OFFSET, + .disable = _clk_disable, +}; + +static struct clk fec_clk[] = { + { + .name = "fec_clk", + .parent = &ipg_clk, + .secondary = &fec_clk[1], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG12_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .name = "fec_sec1_clk", + .parent = &aips_tz2_clk, + .secondary = &ddr_clk, + }, +}; + +static int gpmi_clk_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_GPMI); + reg |= MXC_CCM_GPMI_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_GPMI); + _clk_enable(clk); + return 0; +} + +static void gpmi_clk_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_GPMI); + reg &= ~MXC_CCM_GPMI_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_GPMI); + _clk_disable(clk); +} + +static int bch_clk_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_BCH); + reg |= MXC_CCM_BCH_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_BCH); + _clk_enable(clk); + return 0; +} + +static void bch_clk_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_BCH); + reg &= ~MXC_CCM_BCH_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_BCH); + _clk_disable(clk); +} + +static struct clk gpmi_nfc_clk[] = { + { + .name = "gpmi-nfc", + .parent = &osc_clk, + .secondary = &gpmi_nfc_clk[1], + .enable = gpmi_clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG9_OFFSET, + .disable = gpmi_clk_disable, + }, + { + .name = "gpmi-apb", + .parent = &ahb_clk, + .secondary = &gpmi_nfc_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG8_OFFSET, + .disable = _clk_disable, + }, + { + .name = "bch", + .parent = &osc_clk, + .secondary = &gpmi_nfc_clk[3], + .enable = bch_clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG0_OFFSET, + .disable = bch_clk_disable, + }, + { + .name = "bch-apb", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG12_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk ocotp_clk = { + .name = "ocotp_ctrl_apb", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG13_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &weim_clk[0], &ahb_clk); + reg = (reg & ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk gpu2d_clk = { + .name = "gpu2d_clk", + .parent = &axi_a_clk, + .secondary = &ddr_clk, + .set_parent = _clk_gpu2d_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG7_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk apbh_dma_clk = { + .name = "apbh_dma_clk", + .parent = &ahb_clk, + .secondary = &ddr_clk, + .enable = _clk_enable, + .disable = _clk_disable_inwait, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG10_OFFSET, +}; + +struct clk dcp_clk = { + .name = "dcp_clk", + .id = 0, + .parent = &ahb_clk, + .secondary = &apbh_dma_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG11_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_display_axi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); + mux = _get_mux(parent, &osc_clk, &pfd2_clk, &pll1_sw_clk, NULL); + reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_MASK) | + (mux << MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); + + return 0; +} + +static void _clk_display_axi_recalc(struct clk *clk) +{ + u32 div; + + div = __raw_readl(MXC_CCM_DISPLAY_AXI); + div &= MXC_CCM_DISPLAY_AXI_DIV_MASK; + if (div == 0) { /* gated off */ + clk->rate = clk->parent->rate; + } else { + clk->rate = clk->parent->rate / div; + } +} + +static unsigned long _clk_display_axi_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 max_div = (2 << 6) - 1; + return _clk_round_rate_div(clk, rate, max_div, NULL); +} + +static int _clk_display_axi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 new_div, max_div; + u32 reg; + + max_div = (2 << 6) - 1; + clk->rate = _clk_round_rate_div(clk, rate, max_div, &new_div); + + reg = __raw_readl(MXC_CCM_DISPLAY_AXI); + reg &= ~MXC_CCM_DISPLAY_AXI_DIV_MASK; + reg |= new_div << MXC_CCM_DISPLAY_AXI_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_DISPLAY_AXI); + + while (__raw_readl(MXC_CCM_CSR2) & MXC_CCM_CSR2_DISPLAY_AXI_BUSY) + ; + return 0; +} + +static struct clk display_axi_clk = { + .name = "display_axi", + .parent = &osc_clk, + .secondary = &apbh_dma_clk, + .set_parent = _clk_display_axi_set_parent, + .recalc = _clk_display_axi_recalc, + .set_rate = _clk_display_axi_set_rate, + .round_rate = _clk_display_axi_round_rate, + .enable = _clk_enable, + .disable = _clk_disable, + .enable_reg = MXC_CCM_DISPLAY_AXI, + .enable_shift = MXC_CCM_DISPLAY_AXI_CLKGATE_OFFSET, + .flags = RATE_PROPAGATES, +}; + +/* TODO: check Auto-Slow Mode */ +static struct clk pxp_axi_clk = { + .name = "pxp_axi", + .parent = &display_axi_clk, + .enable = _clk_enable, + .disable = _clk_disable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG9_OFFSET, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk elcdif_axi_clk = { + .name = "elcdif_axi", + .parent = &display_axi_clk, + .enable = _clk_enable, + .disable = _clk_disable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG10_OFFSET, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static int _clk_elcdif_pix_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); + mux = _get_mux(parent, &osc_clk, &pfd6_clk, &pll1_sw_clk, &ckih_clk); + reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_MASK) | + (mux << MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); + + return 0; +} + +static void _clk_elcdif_pix_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_ELCDIFPIX); + prediv = ((reg & MXC_CCM_ELCDIFPIX_CLK_PRED_MASK) >> + MXC_CCM_ELCDIFPIX_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_ELCDIFPIX_CLK_PODF_MASK) >> + MXC_CCM_ELCDIFPIX_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static unsigned long _clk_elcdif_pix_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 max_div = (2 << 12) - 1; + return _clk_round_rate_div(clk, rate, max_div, NULL); +} + +static int _clk_elcdif_pix_set_rate(struct clk *clk, unsigned long rate) +{ + u32 new_div, max_div; + u32 reg; + + max_div = (2 << 12) - 1; + clk->rate = _clk_round_rate_div(clk, rate, max_div, &new_div); + + reg = __raw_readl(MXC_CCM_ELCDIFPIX); + /* Pre-divider set to 1 - only use PODF for clk dividing */ + reg &= ~MXC_CCM_ELCDIFPIX_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_ELCDIFPIX_CLK_PRED_OFFSET; + reg &= ~MXC_CCM_ELCDIFPIX_CLK_PODF_MASK; + reg |= new_div << MXC_CCM_ELCDIFPIX_CLK_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_ELCDIFPIX); + + return 0; +} + +static int _clk_elcdif_pix_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + reg = __raw_readl(MXC_CCM_ELCDIFPIX); + reg |= 0x3 << MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET; + __raw_writel(reg, MXC_CCM_ELCDIFPIX); + return 0; +} + +static void _clk_elcdif_pix_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_ELCDIFPIX); + reg &= ~MXC_CCM_ELCDIFPIX_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_ELCDIFPIX); + _clk_disable(clk); +} + +static struct clk elcdif_pix_clk = { + .name = "elcdif_pix", + .parent = &osc_clk, + .secondary = &ddr_clk, + .enable = _clk_elcdif_pix_enable, + .disable = _clk_elcdif_pix_disable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG6_OFFSET, + .set_parent = _clk_elcdif_pix_set_parent, + .recalc = _clk_elcdif_pix_recalc, + .round_rate = _clk_elcdif_pix_round_rate, + .set_rate = _clk_elcdif_pix_set_rate, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static int _clk_epdc_axi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); + mux = _get_mux(parent, &osc_clk, &pfd3_clk, &pll1_sw_clk, NULL); + reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_MASK) | + (mux << MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); + + return 0; +} + +static void _clk_epdc_axi_recalc(struct clk *clk) +{ + u32 div; + + div = __raw_readl(MXC_CCM_EPDC_AXI); + div &= MXC_CCM_EPDC_AXI_DIV_MASK; + if (div == 0) { /* gated off */ + clk->rate = clk->parent->rate; + } else { + clk->rate = clk->parent->rate / div; + } +} + +static unsigned long _clk_epdc_axi_round_rate_div(struct clk *clk, + unsigned long rate, + u32 *new_div) +{ + u32 div, max_div; + + max_div = (2 << 6) - 1; + div = DIV_ROUND_UP(clk->parent->rate, rate); + if (div > max_div) + div = max_div; + else if (div == 0) + div++; + if (new_div != NULL) + *new_div = div; + return clk->parent->rate / div; +} + +static unsigned long _clk_epdc_axi_round_rate(struct clk *clk, + unsigned long rate) +{ + return _clk_epdc_axi_round_rate_div(clk, rate, NULL); +} + +static int _clk_epdc_axi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 new_div; + u32 reg; + + clk->rate = _clk_epdc_axi_round_rate_div(clk, rate, &new_div); + + reg = __raw_readl(MXC_CCM_EPDC_AXI); + reg &= ~MXC_CCM_EPDC_AXI_DIV_MASK; + reg |= new_div << MXC_CCM_EPDC_AXI_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_EPDC_AXI); + + while (__raw_readl(MXC_CCM_CSR2) & MXC_CCM_CSR2_EPDC_AXI_BUSY) + ; + + return 0; +} + +static int _clk_epdc_axi_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + reg = __raw_readl(MXC_CCM_EPDC_AXI); + reg |= MXC_CCM_EPDC_AXI_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_EPDC_AXI); + + return 0; +} + +static void _clk_epdc_axi_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_EPDC_AXI); + reg &= ~MXC_CCM_EPDC_AXI_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_EPDC_AXI); + _clk_disable(clk); +} + +/* TODO: check Auto-Slow Mode */ +static struct clk epdc_axi_clk = { + .name = "epdc_axi", + .parent = &osc_clk, + .secondary = &apbh_dma_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG8_OFFSET, + .set_parent = _clk_epdc_axi_set_parent, + .recalc = _clk_epdc_axi_recalc, + .set_rate = _clk_epdc_axi_set_rate, + .round_rate = _clk_epdc_axi_round_rate, + .enable = _clk_epdc_axi_enable, + .disable = _clk_epdc_axi_disable, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + + +static int _clk_epdc_pix_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); + mux = _get_mux(parent, &osc_clk, &pfd5_clk, &pll1_sw_clk, &ckih_clk); + reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_MASK) | + (mux << MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); + + return 0; +} + +static void _clk_epdc_pix_recalc(struct clk *clk) +{ + u32 div; + + div = __raw_readl(MXC_CCM_EPDCPIX); + div &= MXC_CCM_EPDC_PIX_CLK_PODF_MASK; + if (div == 0) { /* gated off */ + clk->rate = clk->parent->rate; + } else { + clk->rate = clk->parent->rate / div; + } +} + +static unsigned long _clk_epdc_pix_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 max_div = (2 << 12) - 1; + return _clk_round_rate_div(clk, rate, max_div, NULL); +} + +static int _clk_epdc_pix_set_rate(struct clk *clk, unsigned long rate) +{ + u32 new_div, max_div; + u32 reg; + + max_div = (2 << 12) - 1; + clk->rate = _clk_round_rate_div(clk, rate, max_div, &new_div); + + reg = __raw_readl(MXC_CCM_EPDCPIX); + /* Pre-divider set to 1 - only use PODF for clk dividing */ + reg &= ~MXC_CCM_EPDC_PIX_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_EPDC_PIX_CLK_PRED_OFFSET; + reg &= ~MXC_CCM_EPDC_PIX_CLK_PODF_MASK; + reg |= new_div << MXC_CCM_EPDC_PIX_CLK_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_EPDCPIX); + + while (__raw_readl(MXC_CCM_CSR2) & MXC_CCM_CSR2_EPDC_PIX_BUSY) + ; + + return 0; +} + +static int _clk_epdc_pix_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + reg = __raw_readl(MXC_CCM_EPDCPIX); + reg |= MXC_CCM_EPDC_PIX_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_EPDCPIX); + + return 0; +} + +static void _clk_epdc_pix_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_EPDCPIX); + reg &= ~MXC_CCM_EPDC_PIX_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_EPDCPIX); + _clk_disable(clk); +} + +/* TODO: check Auto-Slow Mode */ +static struct clk epdc_pix_clk = { + .name = "epdc_pix", + .parent = &osc_clk, + .secondary = &apbh_dma_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG5_OFFSET, + .set_parent = _clk_epdc_pix_set_parent, + .recalc = _clk_epdc_pix_recalc, + .set_rate = _clk_epdc_pix_set_rate, + .round_rate = _clk_epdc_pix_round_rate, + .enable = _clk_epdc_pix_enable, + .disable = _clk_epdc_pix_disable, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static void cko1_recalc(struct clk *clk) +{ + unsigned long rate; + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= MX50_CCM_CCOSR_CKO1_DIV_MASK; + reg = reg >> MX50_CCM_CCOSR_CKO1_DIV_OFFSET; + rate = clk->parent->rate; + clk->rate = rate / (reg + 1); +} + +static int cko1_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg |= MX50_CCM_CCOSR_CKO1_EN; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static void cko1_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MX50_CCM_CCOSR_CKO1_EN; + __raw_writel(reg, MXC_CCM_CCOSR); +} + +static int cko1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + div = (clk->parent->rate/rate - 1) & 0x7; + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MX50_CCM_CCOSR_CKO1_DIV_MASK; + reg |= div << MX50_CCM_CCOSR_CKO1_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static unsigned long cko1_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + div = div < 1 ? 1 : div; + div = div > 8 ? 8 : div; + return clk->parent->rate / div; +} + +static int cko1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 sel, reg, fast; + + if (parent == &cpu_clk) { + sel = 0; + fast = 1; + } else if (parent == &pll1_sw_clk) { + sel = 1; + fast = 1; + } else if (parent == &pll2_sw_clk) { + sel = 2; + fast = 1; + } else if (parent == &pll3_sw_clk) { + sel = 3; + fast = 1; + } else if (parent == &apll_clk) { + sel = 0; + fast = 0; + } else if (parent == &pfd0_clk) { + sel = 1; + fast = 0; + } else if (parent == &pfd1_clk) { + sel = 2; + fast = 0; + } else if (parent == &pfd2_clk) { + sel = 3; + fast = 0; + } else if (parent == &pfd3_clk) { + sel = 4; + fast = 0; + } else if (parent == &pfd4_clk) { + sel = 5; + fast = 0; + } else if (parent == &pfd5_clk) { + sel = 6; + fast = 0; + } else if (parent == &pfd6_clk) { + sel = 7; + fast = 0; + } else if (parent == &weim_clk[0]) { + sel = 10; + fast = 0; + } else if (parent == &ahb_clk) { + sel = 11; + fast = 0; + } else if (parent == &ipg_clk) { + sel = 12; + fast = 0; + } else if (parent == &ipg_perclk) { + sel = 13; + fast = 0; + } else if (parent == &pfd7_clk) { + sel = 15; + fast = 0; + } else + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MX50_CCM_CCOSR_CKO1_SEL_MASK; + reg |= sel << MX50_CCM_CCOSR_CKO1_SEL_OFFSET; + if (fast) + reg &= ~MX50_CCM_CCOSR_CKO1_SLOW_SEL; + else + reg |= MX50_CCM_CCOSR_CKO1_SLOW_SEL; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static struct clk cko1_clk = { + .name = "cko1_clk", + .parent = &pll1_sw_clk, + .recalc = cko1_recalc, + .enable = cko1_enable, + .disable = cko1_disable, + .set_rate = cko1_set_rate, + .round_rate = cko1_round_rate, + .set_parent = cko1_set_parent, +}; + +static struct clk *mxc_clks[] = { + &osc_clk, + &ckih_clk, + &ckih2_clk, + &ckil_clk, + &pll1_main_clk, + &pll1_sw_clk, + &pll2_sw_clk, + &pll3_sw_clk, + &apll_clk, + &pfd0_clk, + &pfd1_clk, + &pfd2_clk, + &pfd3_clk, + &pfd4_clk, + &pfd5_clk, + &pfd6_clk, + &pfd7_clk, + &ipmux1_clk, + &ipmux2_clk, + &gpc_dvfs_clk, + &lp_apm_clk, + &cpu_clk, + &main_bus_clk, + &axi_a_clk, + &axi_b_clk, + &ahb_clk, + &ahb_max_clk, + &ipg_clk, + &ipg_perclk, + &ahbmux1_clk, + &aips_tz1_clk, + &aips_tz2_clk, + &sdma_clk[0], + &sdma_clk[1], + &uart_main_clk, + &uart1_clk[0], + &uart1_clk[1], + &uart2_clk[0], + &uart2_clk[1], + &uart3_clk[0], + &uart3_clk[1], + &spba_clk, + &i2c_clk[0], + &i2c_clk[1], + &gpt_clk[0], + &gpt_clk[1], + &gpt_clk[2], + &pwm1_clk[0], + &pwm1_clk[1], + &pwm1_clk[2], + &pwm2_clk[0], + &pwm2_clk[1], + &pwm2_clk[2], + &cspi_main_clk, + &cspi1_clk[0], + &cspi1_clk[1], + &cspi2_clk[0], + &cspi2_clk[1], + &cspi3_clk, + &ssi_lp_apm_clk, + &ssi1_clk[0], + &ssi1_clk[1], + &ssi1_clk[2], + &ssi2_clk[0], + &ssi2_clk[1], + &ssi2_clk[2], + &ssi_ext1_clk, + &ssi_ext2_clk, + &tmax2_clk, + &usb_ahb_clk, + &usb_phy_clk[0], + &usb_clk, + &esdhc1_clk[0], + &esdhc1_clk[1], + &esdhc2_clk[0], + &esdhc2_clk[1], + &esdhc3_clk[0], + &esdhc3_clk[1], + &esdhc4_clk[0], + &esdhc4_clk[1], + &esdhc_dep_clks, + &weim_clk[0], + &weim_clk[1], + &ddr_clk, + &pgc_clk, + &rtc_clk, + &rng_clk, + &dcp_clk, + &owire_clk, + &fec_clk[0], + &fec_clk[1], + &gpu2d_clk, + &cko1_clk, + &display_axi_clk, + &pxp_axi_clk, + &elcdif_axi_clk, + &epdc_axi_clk, + &epdc_pix_clk, + &elcdif_pix_clk, + &gpmi_nfc_clk[0], + &gpmi_nfc_clk[1], + &gpmi_nfc_clk[2], + &gpmi_nfc_clk[3], + &ocotp_clk, +}; + +static void clk_tree_init(void) +{ + u32 reg; + + ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); + + /* + *Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at + * 8MHz, its derived from lp_apm. + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; + reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + /* set pll1_main_clk parent */ + pll1_main_clk.parent = &osc_clk; + + /* set pll2_sw_clk parent */ + pll2_sw_clk.parent = &osc_clk; + + /* set pll3_clk parent */ + pll3_sw_clk.parent = &osc_clk; + + /* set weim_clk parent */ + weim_clk[0].parent = &main_bus_clk; + reg = __raw_readl(MXC_CCM_CBCDR); + if ((reg & MX50_CCM_CBCDR_WEIM_CLK_SEL) != 0) + weim_clk[0].parent = &ahb_clk; + + /* set ipg_perclk parent */ + ipg_perclk.parent = &lp_apm_clk; + reg = __raw_readl(MXC_CCM_CBCMR); + if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) { + ipg_perclk.parent = &ipg_clk; + } else { + if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0) + ipg_perclk.parent = &main_bus_clk; + } +} + +int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1) +{ + __iomem void *base; + struct clk **clkp; + int i = 0, j = 0, reg; + int wp_cnt = 0; + + pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K); + pll2_base = ioremap(MX53_BASE_ADDR(PLL2_BASE_ADDR), SZ_4K); + pll3_base = ioremap(MX53_BASE_ADDR(PLL3_BASE_ADDR), SZ_4K); + apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K); + + /* Turn off all possible clocks */ + if (mxc_jtag_enabled) { + __raw_writel(1 << MXC_CCM_CCGR0_CG0_OFFSET | + 3 << MXC_CCM_CCGR0_CG2_OFFSET | + 3 << MXC_CCM_CCGR0_CG3_OFFSET | + 3 << MXC_CCM_CCGR0_CG4_OFFSET | + 3 << MXC_CCM_CCGR0_CG8_OFFSET | + 1 << MXC_CCM_CCGR0_CG12_OFFSET | + 1 << MXC_CCM_CCGR0_CG13_OFFSET | + 1 << MXC_CCM_CCGR0_CG14_OFFSET, MXC_CCM_CCGR0); + } else { + __raw_writel(1 << MXC_CCM_CCGR0_CG0_OFFSET | + 3 << MXC_CCM_CCGR0_CG3_OFFSET | + 3 << MXC_CCM_CCGR0_CG8_OFFSET | + 1 << MXC_CCM_CCGR0_CG12_OFFSET | + 1 << MXC_CCM_CCGR0_CG13_OFFSET | + 3 << MXC_CCM_CCGR0_CG14_OFFSET, MXC_CCM_CCGR0); + } + + __raw_writel(0, MXC_CCM_CCGR1); + __raw_writel(0, MXC_CCM_CCGR2); + __raw_writel(0, MXC_CCM_CCGR3); + __raw_writel(0, MXC_CCM_CCGR4); + + __raw_writel(3 << MXC_CCM_CCGR5_CG6_OFFSET | + 1 << MXC_CCM_CCGR5_CG8_OFFSET | + 3 << MXC_CCM_CCGR5_CG9_OFFSET, MXC_CCM_CCGR5); + + __raw_writel(3 << MXC_CCM_CCGR6_CG0_OFFSET | + 3 << MXC_CCM_CCGR6_CG1_OFFSET | + 2 << MXC_CCM_CCGR6_CG14_OFFSET | + 3 << MXC_CCM_CCGR6_CG15_OFFSET, MXC_CCM_CCGR6); + + __raw_writel(0, MXC_CCM_CCGR7); + + ckil_clk.rate = ckil; + osc_clk.rate = osc; + ckih_clk.rate = ckih1; + + usb_phy_clk[0].enable_reg = MXC_CCM_CCGR4; + usb_phy_clk[0].enable_shift = MXC_CCM_CCGR4_CG5_OFFSET; + + clk_tree_init(); + + for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) + clk_register(*clkp); + + clk_register(&uart4_clk[0]); + clk_register(&uart4_clk[1]); + clk_register(&uart5_clk[0]); + clk_register(&uart5_clk[1]); + clk_register(&i2c_clk[2]); + clk_register(&usb_phy_clk[1]); + clk_register(&ocram_clk); + clk_register(&apbh_dma_clk); + clk_register(&sys_clk); + + /* set DDR clock parent */ + reg = __raw_readl(MXC_CCM_CLK_DDR) & + MXC_CCM_CLK_DDR_DDR_PFD_SEL; + if (reg) + clk_set_parent(&ddr_clk, &pfd0_clk); + else + clk_set_parent(&ddr_clk, &pll1_sw_clk); + + clk_set_parent(&esdhc1_clk[0], &pll2_sw_clk); + clk_set_parent(&esdhc1_clk[2], &tmax2_clk); + clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]); + clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk); + + /* This will propagate to all children and init all the clock rates */ + propagate_rate(&osc_clk); + propagate_rate(&ckih_clk); + propagate_rate(&ckil_clk); + propagate_rate(&pll1_sw_clk); + propagate_rate(&pll2_sw_clk); + propagate_rate(&pll3_sw_clk); + propagate_rate(&apll_clk); + + clk_enable(&cpu_clk); + + clk_enable(&main_bus_clk); + + clk_enable(&ocotp_clk); + + databahn = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K); + + /* Initialise the parents to be axi_b, parents are set to + * axi_a when the clocks are enabled. + */ + + clk_set_parent(&gpu2d_clk, &axi_a_clk); + + /* move cspi to 24MHz */ + clk_set_parent(&cspi_main_clk, &lp_apm_clk); + clk_set_rate(&cspi_main_clk, 12000000); + + /* + * Set DISPLAY_AXI to 200Mhz + * For Display AXI, source clocks must be + * enabled before dividers can be changed + */ + clk_enable(&display_axi_clk); + clk_enable(&elcdif_axi_clk); + clk_enable(&pxp_axi_clk); + clk_set_parent(&display_axi_clk, &pfd2_clk); + clk_set_rate(&display_axi_clk, 200000000); + clk_disable(&display_axi_clk); + clk_disable(&pxp_axi_clk); + clk_disable(&elcdif_axi_clk); + + clk_enable(&elcdif_pix_clk); + clk_set_parent(&elcdif_pix_clk, &pll1_sw_clk); + clk_disable(&elcdif_pix_clk); + + /* + * Enable and set EPDC AXI to 200MHz + * For EPDC AXI, source clocks must be + * enabled before dividers can be changed + */ + clk_enable(&epdc_axi_clk); + clk_set_parent(&epdc_axi_clk, &pfd3_clk); + clk_set_rate(&epdc_axi_clk, 200000000); + clk_disable(&epdc_axi_clk); + + clk_set_parent(&epdc_pix_clk, &pfd5_clk); + + /* Move SSI clocks to SSI_LP_APM clock */ + clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk); + + clk_set_parent(&ssi1_clk[0], &ssi_lp_apm_clk); + /* set the SSI dividers to divide by 2 */ + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS1CDR); + + clk_set_parent(&ssi2_clk[0], &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CS2CDR); + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS2CDR); + + /* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */ + clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]); + clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]); + + /* move usb_phy_clk to 24MHz */ + clk_set_parent(&usb_phy_clk[0], &osc_clk); + clk_set_parent(&usb_phy_clk[1], &osc_clk); + + /* move gpmi-nfc to 24MHz */ + clk_set_parent(&gpmi_nfc_clk[0], &osc_clk); + + /* set SDHC root clock as 200MHZ*/ + clk_set_rate(&esdhc1_clk[0], 200000000); + clk_set_rate(&esdhc3_clk[0], 200000000); + + /* Set the current working point. */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + /* Update the cpu working point table based on the PLL1 freq + * at boot time + */ + if (pll1_main_clk.rate <= cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) + wp_cnt = 1; + else if (pll1_main_clk.rate <= cpu_wp_tbl[1].cpu_rate && + pll1_main_clk.rate > cpu_wp_tbl[2].cpu_rate) + wp_cnt = cpu_wp_nr - 1; + else + wp_cnt = cpu_wp_nr; + + cpu_wp_tbl[0].cpu_rate = pll1_main_clk.rate; + + if (wp_cnt == 1) { + cpu_wp_tbl[0] = cpu_wp_tbl[cpu_wp_nr - 1]; + memset(&cpu_wp_tbl[cpu_wp_nr - 1], 0, sizeof(struct cpu_wp)); + memset(&cpu_wp_tbl[cpu_wp_nr - 2], 0, sizeof(struct cpu_wp)); + } else if (wp_cnt < cpu_wp_nr) { + for (i = 0; i < wp_cnt; i++) + cpu_wp_tbl[i] = cpu_wp_tbl[i+1]; + memset(&cpu_wp_tbl[i], 0, sizeof(struct cpu_wp)); + } + + if (wp_cnt < cpu_wp_nr) { + set_num_cpu_wp(wp_cnt); + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + } + + + for (j = 0; j < cpu_wp_nr; j++) { + /* Change the CPU podf divider based on the boot up + * pll1 rate. + */ + cpu_wp_tbl[j].cpu_podf = max( + (int)((pll1_main_clk.rate / cpu_wp_tbl[j].cpu_rate) + - 1), 0); + if (pll1_main_clk.rate/(cpu_wp_tbl[j].cpu_podf + 1) > + cpu_wp_tbl[j].cpu_rate) { + cpu_wp_tbl[j].cpu_podf++; + cpu_wp_tbl[j].cpu_rate = + pll1_main_clk.rate/ + (1000 * (cpu_wp_tbl[j].cpu_podf + 1)); + cpu_wp_tbl[j].cpu_rate *= 1000; + } + if (pll1_main_clk.rate/(cpu_wp_tbl[j].cpu_podf + 1) < + cpu_wp_tbl[j].cpu_rate) { + cpu_wp_tbl[j].cpu_rate = pll1_main_clk.rate; + } + cpu_wp_tbl[j].pll_rate = pll1_main_clk.rate; + } + /* Set the current working point. */ + for (i = 0; i < cpu_wp_nr; i++) { + if (clk_get_rate(&cpu_clk) == cpu_wp_tbl[i].cpu_rate) { + cpu_curr_wp = i; + break; + } + } + if (i > cpu_wp_nr) + BUG(); + + propagate_rate(&osc_clk); + propagate_rate(&pll1_sw_clk); + propagate_rate(&pll2_sw_clk); + propagate_rate(&pll3_sw_clk); + + clk_set_parent(&uart_main_clk, &lp_apm_clk); + clk_set_parent(&gpu2d_clk, &axi_b_clk); + + clk_set_parent(&weim_clk[0], &ahb_clk); + clk_set_rate(&weim_clk[0], clk_round_rate(&weim_clk[0], 130000000)); + + /* Do the following just to disable the PLL since its not used */ + clk_enable(&pll3_sw_clk); + clk_disable(&pll3_sw_clk); + + base = ioremap(MX53_BASE_ADDR(GPT1_BASE_ADDR), SZ_4K); + mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); + return 0; +} + +/*! + * Setup cpu clock based on working point. + * @param wp cpu freq working point + * @return 0 on success or error code on failure. + */ +static int cpu_clk_set_wp(int wp) +{ + struct cpu_wp *p; + u32 reg; + + if (wp == cpu_curr_wp) + return 0; + + p = &cpu_wp_tbl[wp]; + + /* + * leave the PLL1 freq unchanged. + */ + reg = __raw_readl(MXC_CCM_CACRR); + reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK; + reg |= cpu_wp_tbl[wp].cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CACRR); + cpu_curr_wp = wp; + cpu_clk.rate = cpu_wp_tbl[wp].cpu_rate; + +#if defined(CONFIG_CPU_FREQ) + cpufreq_trig_needed = 1; +#endif + return 0; +} diff --git a/arch/arm/mach-mx5/displays/hdmi_ad9389.h b/arch/arm/mach-mx5/displays/hdmi_ad9389.h new file mode 100644 index 000000000000..2a29cd783b48 --- /dev/null +++ b/arch/arm/mach-mx5/displays/hdmi_ad9389.h @@ -0,0 +1,168 @@ +/* + * arch/arm/mach-mx5/displays/hdmi_ad9389.h + * + * Copyright (C) 2010 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_CCWMX51_DISPLAYS_HDMI_AD9389_H__ +#define __ASM_ARCH_MXC_CCWMX51_DISPLAYS_HDMI_AD9389_H__ + +static struct fb_videomode ad9389_1280x720x24 = { + .name = "1280x720", + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 20100, + .left_margin = 32, + .right_margin = 48, + .upper_margin = 7, + .lower_margin = 3, + .hsync_len = 32, + .vsync_len = 6, +}; + +static struct fb_videomode ad9389_1360x768x24 = { + .name = "1360x768", + .refresh = 60, + .xres = 1360, + .yres = 768, + .pixclock = 16000, + .left_margin = 139, + .right_margin = 256, + .upper_margin = 3, + .lower_margin = 18, + .hsync_len = 76, + .vsync_len = 6, +}; + + +static struct fb_videomode ad9389_1366x768x24 = { + .name = "1366x768", + .refresh = 60, + .xres = 1366, + .yres = 768, + .pixclock = 16000, + .left_margin = 139, + .right_margin = 256, + .upper_margin = 3, + .lower_margin = 18, + .hsync_len = 76, + .vsync_len = 6, +}; + +static struct fb_videomode ad9389_1920x1080x24 = { + .name = "1920x1080", + .refresh = 60, + .xres = 1920, + .yres = 1080, + .pixclock = 7560, + .left_margin = 148, + .right_margin = 88, + .upper_margin = 36, + .lower_margin = 4, + .hsync_len = 44, + .vsync_len = 5, +}; + +static struct fb_videomode ad9389_1024x768x24 = { + .name = "1024x768", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15384, /* pico seconds of 65.0MHz */ + .left_margin = 160, + .right_margin = 24, + .upper_margin = 29, + .lower_margin = 3, + .hsync_len = 136, + .vsync_len = 6, +}; + +static struct fb_videomode ad9389_custom_1 = { + .name = "custom1", + .refresh = 0, + .xres = 0, + .yres = 0, + .pixclock = 0, + .left_margin = 0, + .right_margin = 0, + .upper_margin = 0, + .lower_margin = 0, + .hsync_len = 0, + .vsync_len = 0, + .sync = 0, +}; + +static struct fb_videomode ad9389_custom_2 = { + .name = "custom2", + .refresh = 0, + .xres = 0, + .yres = 0, + .pixclock = 0, + .left_margin = 0, + .right_margin = 0, + .upper_margin = 0, + .lower_margin = 0, + .hsync_len = 0, + .vsync_len = 0, + .sync = 0, +}; + +struct ccwmx51_lcd_pdata ad9389_panel_list[] = { + { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "1280x720", + .mode = &ad9389_1280x720x24, + }, + .bl_enable = NULL, + }, { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "1360x768", + .mode = &ad9389_1360x768x24, + }, + .bl_enable = NULL, + }, { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "1366x768", + .mode = &ad9389_1366x768x24, + }, + .bl_enable = NULL, + }, { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "1920x1080", + .mode = &ad9389_1920x1080x24, + }, + .bl_enable = NULL, + }, { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "1024x768", + .mode = &ad9389_1024x768x24, + }, + .bl_enable = NULL, + }, { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "custom1", + .mode = &ad9389_custom_1, + }, + .bl_enable = NULL, + }, { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "custom2", + .mode = &ad9389_custom_2, + }, + .bl_enable = NULL, + }, +}; +#endif /* __ASM_ARCH_MXC_CCWMX51_DISPLAYS_HDMI_AD9389_H__ */ \ No newline at end of file diff --git a/arch/arm/mach-mx5/displays/lcd.h b/arch/arm/mach-mx5/displays/lcd.h new file mode 100644 index 000000000000..f2af740ebf85 --- /dev/null +++ b/arch/arm/mach-mx5/displays/lcd.h @@ -0,0 +1,135 @@ +/* + * arch/arm/mach-mx5/displays/lcd.h + * + * Copyright (C) 2010 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_CCWMX51_DISPLAYS_LCD_H__ +#define __ASM_ARCH_MXC_CCWMX51_DISPLAYS_LCD_H__ + +#include "../iomux.h" + +#if defined (CONFIG_JSCCWMX51_V1) +#include "../drivers/mxc/ipu3/ipu_regs.h" + +/** + * This code is only valide to enable/disable the backlight of the second + * display, on the first version of the JumpStart Board (JSCCWMX51 RevA). + * Newer versions use a GPIO to enable the BL of the second display. + */ +void ipu_ccwmx51_disp1_enable(int enable) +{ + uint32_t tmp; + + tmp = __raw_readl(DI_GENERAL(1)); + tmp &= ~DI_GEN_POLARITY_4; + if (enable) + tmp |= DI_GEN_POLARITY_4; + __raw_writel(tmp, DI_GENERAL(1)); +} +#endif + +static void lcd_bl_enable_lq70(int enable, int vif) +{ + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), !enable); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN12), !enable); + if (vif == 0) + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), !enable); + else if (vif == 1) +#ifdef CONFIG_JSCCWMX51_V1 + ipu_ccwmx51_disp1_enable(enable); +#elif defined(CONFIG_JSCCWMX51_V2) + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN12), !enable); +#else +#error "A function to enable/disalbe the display have to be specified" +#endif +} + +static void lcd_init(int vif) +{ + /* Initialize lcd enable gpio and video interface lines */ + gpio_video_active(vif, PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); +} + +static struct fb_videomode lq70y3dg3b = { + .name = "LQ070Y3DG3B", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 44000, + .left_margin = 0, + .right_margin = 50, + .upper_margin = 25, + .lower_margin = 10, + .hsync_len = 128, + .vsync_len = 10, + .vmode = FB_VMODE_NONINTERLACED, + .sync = FB_SYNC_EXT, + .flag = 0, +}; + +static struct fb_videomode lcd_custom_1 = { + .name = "custom1", + .refresh = 0, + .xres = 0, + .yres = 0, + .pixclock = 0, + .left_margin = 0, + .right_margin = 0, + .upper_margin = 0, + .lower_margin = 0, + .hsync_len = 0, + .vsync_len = 0, + .vmode = FB_VMODE_NONINTERLACED, + .sync = FB_SYNC_EXT, +}; + +static struct fb_videomode lcd_custom_2 = { + .name = "custom2", + .refresh = 0, + .xres = 0, + .yres = 0, + .pixclock = 0, + .left_margin = 0, + .right_margin = 0, + .upper_margin = 0, + .lower_margin = 0, + .hsync_len = 0, + .vsync_len = 0, + .vmode = FB_VMODE_NONINTERLACED, + .sync = FB_SYNC_EXT, +}; + +struct ccwmx51_lcd_pdata lcd_panel_list[] = { + { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "LQ070Y3DG3B", + .mode = &lq70y3dg3b, + }, + .bl_enable = lcd_bl_enable_lq70, + .init = &lcd_init, + }, { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "custom1", + .mode = &lcd_custom_1, + }, + .bl_enable = NULL, + .init = &lcd_init, + }, { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "custom2", + .mode = &lcd_custom_2, + }, + .bl_enable = NULL, + .init = &lcd_init, + }, +}; +#endif /* __ASM_ARCH_MXC_CCWMX51_DISPLAYS_LCD_H__ */ diff --git a/arch/arm/mach-mx5/displays/vga.h b/arch/arm/mach-mx5/displays/vga.h new file mode 100644 index 000000000000..3e5a913c643a --- /dev/null +++ b/arch/arm/mach-mx5/displays/vga.h @@ -0,0 +1,64 @@ +/* + * arch/arm/mach-mx5/displays/vga.h + * + * Copyright (C) 2010 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_CCWMX51_DISPLAYS_VGA_H__ +#define __ASM_ARCH_MXC_CCWMX51_DISPLAYS_VGA_H__ + +static struct fb_videomode vga_custom_1 = { + .name = "custom1", + .refresh = 0, + .xres = 0, + .yres = 0, + .pixclock = 0, + .left_margin = 0, + .right_margin = 0, + .upper_margin = 0, + .lower_margin = 0, + .hsync_len = 0, + .vsync_len = 0, + .vmode = FB_VMODE_NONINTERLACED, + .sync = FB_SYNC_EXT, +}; + +static struct fb_videomode vga_custom_2 = { + .name = "custom1", + .refresh = 0, + .xres = 0, + .yres = 0, + .pixclock = 0, + .left_margin = 0, + .right_margin = 0, + .upper_margin = 0, + .lower_margin = 0, + .hsync_len = 0, + .vsync_len = 0, + .vmode = FB_VMODE_NONINTERLACED, + .sync = FB_SYNC_EXT, +}; + +struct ccwmx51_lcd_pdata vga_panel_list[] = { + { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "custom1", + .mode = &vga_custom_1, + }, + .bl_enable = NULL, + }, { + .fb_pdata = { + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "custom2", + .mode = &vga_custom_2, + }, + .bl_enable = NULL, + }, +}; +#endif /* __ASM_ARCH_MXC_CCWMX51_DISPLAYS_VGA_H__ */ \ No newline at end of file diff --git a/arch/arm/mach-mx5/dma-apbh.c b/arch/arm/mach-mx5/dma-apbh.c new file mode 100644 index 000000000000..d61756135667 --- /dev/null +++ b/arch/arm/mach-mx5/dma-apbh.c @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "regs-apbh.h" + +#ifndef BM_APBH_CTRL0_APB_BURST_EN +#define BM_APBH_CTRL0_APB_BURST_EN BM_APBH_CTRL0_APB_BURST4_EN +#endif + +static int mxs_dma_apbh_enable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + unsigned int sem; + struct mxs_dma_device *pdev = pchan->dma; + struct mxs_dma_desc *pdesc; + + pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); + if (pdesc == NULL) + return -EFAULT; + + sem = __raw_readl(pdev->base + HW_APBH_CHn_SEMA(chan)); + sem = (sem & BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; + if (pchan->flags & MXS_DMA_FLAGS_BUSY) { + + if (pdesc->cmd.cmd.bits.chain == 0) + return 0; + if (sem < 2) { + if (!sem) + return 0; + pdesc = list_entry(pdesc->node.next, + struct mxs_dma_desc, node); + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBH_CHn_NXTCMDAR(chan)); + } + sem = pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(BF_APBH_CHn_SEMA_INCREMENT_SEMA(sem), + pdev->base + HW_APBH_CHn_SEMA(chan)); + pchan->active_num += sem; + return 0; + } + + pchan->active_num += pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBH_CHn_NXTCMDAR(chan)); + __raw_writel(pchan->active_num, pdev->base + HW_APBH_CHn_SEMA(chan)); + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL0_CLR); + return 0; +} + +static void mxs_dma_apbh_disable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + struct mxs_dma_device *pdev = pchan->dma; + __raw_writel(1 << (chan + BP_APBH_CTRL0_CLKGATE_CHANNEL), + pdev->base + HW_APBH_CTRL0_SET); +} + +static void mxs_dma_apbh_reset(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << (chan + BP_APBH_CHANNEL_CTRL_RESET_CHANNEL), + pdev->base + HW_APBH_CHANNEL_CTRL_SET); +} + +static void mxs_dma_apbh_freeze(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBH_CHANNEL_CTRL_SET); +} + +static void +mxs_dma_apbh_unfreeze(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBH_CHANNEL_CTRL_CLR); +} + +static void mxs_dma_apbh_info(struct mxs_dma_device *pdev, + unsigned int chan, struct mxs_dma_info *info) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBH_CTRL2); + info->status = reg >> chan; + info->buf_addr = __raw_readl(pdev->base + HW_APBH_CHn_BAR(chan)); +} + +static int +mxs_dma_apbh_read_semaphore(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBH_CHn_SEMA(chan)); + return (reg & BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; +} + +static void +mxs_dma_apbh_enable_irq(struct mxs_dma_device *pdev, + unsigned int chan, int enable) +{ + if (enable) + __raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL1_SET); + else + __raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL1_CLR); + +} + +static int +mxs_dma_apbh_irq_is_pending(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBH_CTRL1); + reg |= __raw_readl(pdev->base + HW_APBH_CTRL2); + return reg & (1 << chan); +} + +static void mxs_dma_apbh_ack_irq(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL1_CLR); + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL2_CLR); +} + +static struct mxs_dma_device mxs_dma_apbh = { + .name = "mxs-dma-apbh", + .enable = mxs_dma_apbh_enable, + .disable = mxs_dma_apbh_disable, + .reset = mxs_dma_apbh_reset, + .freeze = mxs_dma_apbh_freeze, + .unfreeze = mxs_dma_apbh_unfreeze, + .info = mxs_dma_apbh_info, + .read_semaphore = mxs_dma_apbh_read_semaphore, + .enable_irq = mxs_dma_apbh_enable_irq, + .irq_is_pending = mxs_dma_apbh_irq_is_pending, + .ack_irq = mxs_dma_apbh_ack_irq, +}; + +static int __devinit dma_apbh_probe(struct platform_device *pdev) +{ + int i; + struct resource *res; + struct mxs_dma_plat_data *plat; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOMEM; + mxs_dma_apbh.base = ioremap(res->start, res->end); + __raw_writel(BM_APBH_CTRL0_SFTRST, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(mxs_dma_apbh.base + HW_APBH_CTRL0_CLR) & + BM_APBH_CTRL0_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -ETIME; + __raw_writel(BM_APBH_CTRL0_CLKGATE, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + plat = (struct mxs_dma_plat_data *)pdev->dev.platform_data; + if (!plat) + return -ENODEV; + if (plat->burst8) + __raw_writel(BM_APBH_CTRL0_AHB_BURST8_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_SET); + else + __raw_writel(BM_APBH_CTRL0_AHB_BURST8_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + if (plat->burst) + __raw_writel(BM_APBH_CTRL0_APB_BURST_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_SET); + else + __raw_writel(BM_APBH_CTRL0_APB_BURST_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + mxs_dma_apbh.pdev = pdev; + mxs_dma_apbh.chan_base = plat->chan_base; + mxs_dma_apbh.chan_num = plat->chan_num; + platform_set_drvdata(pdev, &mxs_dma_apbh); + return mxs_dma_device_register(&mxs_dma_apbh); +} + +static int __devexit dma_apbh_remove(struct platform_device *pdev) +{ + iounmap(mxs_dma_apbh.base); + return 0; +} + +static struct platform_driver dma_apbh_driver = { + .probe = dma_apbh_probe, + .remove = __devexit_p(dma_apbh_remove), + .driver = { + .name = "mxs-dma-apbh"}, +}; + +static int __init mxs_dma_apbh_init(void) +{ + return platform_driver_register(&dma_apbh_driver); +} + +fs_initcall(mxs_dma_apbh_init); diff --git a/arch/arm/mach-mx5/dma-apbh.h b/arch/arm/mach-mx5/dma-apbh.h new file mode 100644 index 000000000000..9d8d1de53ecf --- /dev/null +++ b/arch/arm/mach-mx5/dma-apbh.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DMA_H__ +#define __ASM_ARCH_MACH_DMA_H__ + +enum { + MXS_DMA_CHANNEL_AHB_APBH = 0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = MXS_DMA_CHANNEL_AHB_APBH, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_SSP, + MXS_MAX_DMA_CHANNELS, +}; +#endif diff --git a/arch/arm/mach-mx5/dmaengine.c b/arch/arm/mach-mx5/dmaengine.c new file mode 100644 index 000000000000..b8aad6c0b73f --- /dev/null +++ b/arch/arm/mach-mx5/dmaengine.c @@ -0,0 +1,641 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dma-apbh.h" + +static void *mxs_dma_pool; +static int mxs_dma_alignment = MXS_DMA_ALIGNMENT; + +/* + * The mutex that arbitrates access to the array of structures that represent + * all the DMA channels in the system (see mxs_dma_channels, below). + */ + +static DEFINE_MUTEX(mxs_dma_mutex); + +/* + * The list of DMA drivers that manage various DMA channels. A DMA device + * driver registers to manage DMA channels by calling mxs_dma_device_register(). + */ + +static LIST_HEAD(mxs_dma_devices); + +/* + * The array of struct mxs_dma_chan that represent every DMA channel in the + * system. The index of the structure in the array indicates the specific DMA + * hardware it represents (see mach-mx28/include/mach/dma.h). + */ + +static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS]; + +int mxs_dma_request(int channel, struct device *dev, const char *name) +{ + int ret = 0; + struct mxs_dma_chan *pchan; + + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + + if (!dev || !name) + return -EINVAL; + pchan = mxs_dma_channels + channel; + mutex_lock(&mxs_dma_mutex); + if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID) { + ret = -ENODEV; + goto out; + } + if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED) { + ret = -EBUSY; + goto out; + } + pchan->flags |= MXS_DMA_FLAGS_ALLOCATED; + pchan->name = name; + pchan->dev = (unsigned long)dev; + pchan->active_num = 0; + pchan->pending_num = 0; + spin_lock_init(&pchan->lock); + INIT_LIST_HEAD(&pchan->active); + INIT_LIST_HEAD(&pchan->done); +out: + mutex_unlock(&mxs_dma_mutex); + return ret; +} +EXPORT_SYMBOL(mxs_dma_request); + +void mxs_dma_release(int channel, struct device *dev) +{ + struct mxs_dma_chan *pchan; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + + if (pchan->flags & MXS_DMA_FLAGS_BUSY) + return; + + if (pchan->dev != (unsigned long)dev) + return; + + mutex_lock(&mxs_dma_mutex); + pchan->dev = 0; + pchan->active_num = 0; + pchan->pending_num = 0; + pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED; + mutex_unlock(&mxs_dma_mutex); +} +EXPORT_SYMBOL(mxs_dma_release); + +int mxs_dma_enable(int channel) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + pdma = pchan->dma; + mutex_lock(&mxs_dma_mutex); + spin_lock_irqsave(&pchan->lock, flags); + if (pchan->pending_num && pdma->enable) + ret = pdma->enable(pchan, channel - pdma->chan_base); + pchan->flags |= MXS_DMA_FLAGS_BUSY; + spin_unlock_irqrestore(&pchan->lock, flags); + mutex_unlock(&mxs_dma_mutex); + return ret; +} +EXPORT_SYMBOL(mxs_dma_enable); + +void mxs_dma_disable(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + if (!(pchan->flags & MXS_DMA_FLAGS_BUSY)) + return; + pdma = pchan->dma; + mutex_lock(&mxs_dma_mutex); + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->disable) + pdma->disable(pchan, channel - pdma->chan_base); + pchan->flags &= ~MXS_DMA_FLAGS_BUSY; + pchan->active_num = 0; + pchan->pending_num = 0; + list_splice_init(&pchan->active, &pchan->done); + spin_unlock_irqrestore(&pchan->lock, flags); + mutex_unlock(&mxs_dma_mutex); +} +EXPORT_SYMBOL(mxs_dma_disable); + +int mxs_dma_get_info(int channel, struct mxs_dma_info *info) +{ + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + + if (!info) + return -EINVAL; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EFAULT; + pdma = pchan->dma; + if (pdma->info) + pdma->info(pdma, channel - pdma->chan_base, info); + return 0; +} +EXPORT_SYMBOL(mxs_dma_get_info); + +int mxs_dma_cooked(int channel, struct list_head *head) +{ + int sem; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct list_head *p, *q; + struct mxs_dma_desc *pdesc; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + sem = mxs_dma_read_semaphore(channel); + if (sem < 0) + return sem; + if (sem == pchan->active_num) + return 0; + BUG_ON(sem > pchan->active_num); + spin_lock_irqsave(&pchan->lock, flags); + list_for_each_safe(p, q, &pchan->active) { + if ((pchan->active_num) <= sem) + break; + pdesc = list_entry(p, struct mxs_dma_desc, node); + pdesc->flags &= ~MXS_DMA_DESC_READY; + if (head) + list_move_tail(p, head); + else + list_move_tail(p, &pchan->done); + if (pdesc->flags & MXS_DMA_DESC_LAST) + pchan->active_num--; + } + if (sem == 0) + pchan->flags &= ~MXS_DMA_FLAGS_BUSY; + spin_unlock_irqrestore(&pchan->lock, flags); + + BUG_ON(sem != pchan->active_num); + return 0; +} +EXPORT_SYMBOL(mxs_dma_cooked); + +void mxs_dma_reset(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->reset) + pdma->reset(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_reset); + +void mxs_dma_freeze(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->freeze) + pdma->freeze(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_freeze); + +void mxs_dma_unfreeze(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->unfreeze) + pdma->unfreeze(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_unfreeze); + +int mxs_dma_read_semaphore(int channel) +{ + int ret = -EINVAL; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return ret; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return ret; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->read_semaphore) + ret = pdma->read_semaphore(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_read_semaphore); + +void mxs_dma_enable_irq(int channel, int en) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->enable_irq) + pdma->enable_irq(pdma, channel - pdma->chan_base, en); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_enable_irq); + +int mxs_dma_irq_is_pending(int channel) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return ret; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return ret; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->irq_is_pending) + ret = pdma->irq_is_pending(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_irq_is_pending); + +void mxs_dma_ack_irq(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->ack_irq) + pdma->ack_irq(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_ack_irq); + +void mxs_dma_set_target(int channel, int target) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + if (pchan->flags & MXS_DMA_FLAGS_BUSY) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->set_target) + pdma->set_target(pdma, channel - pdma->chan_base, target); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_set_target); + +/* mxs dma utility function */ +struct mxs_dma_desc *mxs_dma_alloc_desc(void) +{ + struct mxs_dma_desc *pdesc; + unsigned int address; + if (mxs_dma_pool == NULL) + return NULL; + + pdesc = dma_pool_alloc(mxs_dma_pool, GFP_KERNEL, &address); + if (pdesc == NULL) + return NULL; + memset(pdesc, 0, sizeof(*pdesc)); + pdesc->address = address; + return pdesc; +}; +EXPORT_SYMBOL(mxs_dma_alloc_desc); + +void mxs_dma_free_desc(struct mxs_dma_desc *pdesc) +{ + if (pdesc == NULL) + return; + + if (mxs_dma_pool == NULL) + return; + + dma_pool_free(mxs_dma_pool, pdesc, pdesc->address); +} +EXPORT_SYMBOL(mxs_dma_free_desc); + +int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_desc *last; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + pdma = pchan->dma; + pdesc->cmd.next = mxs_dma_cmd_address(pdesc); + pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST; + spin_lock_irqsave(&pchan->lock, flags); + if (!list_empty(&pchan->active)) { + + last = list_entry(pchan->active.prev, + struct mxs_dma_desc, node); + + pdesc->flags &= ~MXS_DMA_DESC_FIRST; + last->flags &= ~MXS_DMA_DESC_LAST; + + last->cmd.next = mxs_dma_cmd_address(pdesc); + last->cmd.cmd.bits.chain = 1; + } + pdesc->flags |= MXS_DMA_DESC_READY; + if (pdesc->flags & MXS_DMA_DESC_FIRST) + pchan->pending_num++; + list_add_tail(&pdesc->node, &pchan->active); +out: + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_desc_append); + +int mxs_dma_desc_add_list(int channel, struct list_head *head) +{ + int ret = 0, size = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + struct list_head *p; + struct mxs_dma_desc *prev = NULL, *pcur; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + if (list_empty(head)) + return 0; + + pdma = pchan->dma; + list_for_each(p, head) { + pcur = list_entry(p, struct mxs_dma_desc, node); + if (!(pcur->cmd.cmd.bits.dec_sem || pcur->cmd.cmd.bits.chain)) + return -EINVAL; + if (prev) + prev->cmd.next = mxs_dma_cmd_address(pcur); + else + pcur->flags |= MXS_DMA_DESC_FIRST; + pcur->flags |= MXS_DMA_DESC_READY; + prev = pcur; + size++; + } + pcur = list_first_entry(head, struct mxs_dma_desc, node); + prev->cmd.next = mxs_dma_cmd_address(pcur); + prev->flags |= MXS_DMA_DESC_LAST; + + spin_lock_irqsave(&pchan->lock, flags); + if (!list_empty(&pchan->active)) { + pcur = list_entry(pchan->active.next, + struct mxs_dma_desc, node); + if (pcur->cmd.cmd.bits.dec_sem != prev->cmd.cmd.bits.dec_sem) { + ret = -EFAULT; + goto out; + } + prev->cmd.next = mxs_dma_cmd_address(pcur); + prev = list_entry(pchan->active.prev, + struct mxs_dma_desc, node); + pcur = list_first_entry(head, struct mxs_dma_desc, node); + pcur->flags &= ~MXS_DMA_DESC_FIRST; + prev->flags &= ~MXS_DMA_DESC_LAST; + prev->cmd.next = mxs_dma_cmd_address(pcur); + } + list_splice(head, &pchan->active); + pchan->pending_num += size; + if (!(pcur->cmd.cmd.bits.dec_sem) && (pcur->flags & MXS_DMA_DESC_FIRST)) + pchan->pending_num += 1; + else + pchan->pending_num += size; +out: + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_desc_add_list); + +int mxs_dma_get_cooked(int channel, struct list_head *head) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + if (head == NULL) + return 0; + + spin_lock_irqsave(&pchan->lock, flags); + list_splice(&pchan->done, head); + spin_unlock_irqrestore(&pchan->lock, flags); + return 0; +} +EXPORT_SYMBOL(mxs_dma_get_cooked); + +int mxs_dma_device_register(struct mxs_dma_device *pdev) +{ + int i; + struct mxs_dma_chan *pchan; + + if (pdev == NULL || !pdev->chan_num) + return -EINVAL; + + if ((pdev->chan_base >= MXS_MAX_DMA_CHANNELS) || + ((pdev->chan_base + pdev->chan_num) > MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + + mutex_lock(&mxs_dma_mutex); + pchan = mxs_dma_channels + pdev->chan_base; + for (i = 0; i < pdev->chan_num; i++, pchan++) { + pchan->dma = pdev; + pchan->flags = MXS_DMA_FLAGS_VALID; + } + list_add(&pdev->node, &mxs_dma_devices); + mutex_unlock(&mxs_dma_mutex); + return 0; +} +EXPORT_SYMBOL(mxs_dma_device_register); + +static int __init mxs_dma_alignment_setup(char *line) +{ + get_option(&line, &mxs_dma_alignment); + mxs_dma_alignment = (mxs_dma_alignment + 3) & (~3); + mxs_dma_alignment = max(mxs_dma_alignment, MXS_DMA_ALIGNMENT); + return 1; +}; + +__setup("mxs-dma-alignment=", mxs_dma_alignment_setup); + +static int mxs_dmaengine_init(void) +{ + mxs_dma_pool = dma_pool_create("mxs_dma", NULL, + sizeof(struct mxs_dma_desc), + mxs_dma_alignment, PAGE_SIZE); + if (mxs_dma_pool == NULL) + return -ENOMEM; + return 0; +} + +subsys_initcall(mxs_dmaengine_init); + +#ifdef CONFIG_PROC_FS + +static void *mxs_dma_proc_seq_start(struct seq_file *file, loff_t * index) +{ + if (*index >= MXS_MAX_DMA_CHANNELS) + return NULL; + return mxs_dma_channels + *index; +} + +static void *mxs_dma_proc_seq_next(struct seq_file *file, void *data, + loff_t *index) +{ + if (data == NULL) + return NULL; + + if (*index >= MXS_MAX_DMA_CHANNELS) + return NULL; + + return mxs_dma_channels + (*index)++; +} + +static void mxs_dma_proc_seq_stop(struct seq_file *file, void *data) +{ +} + +static int mxs_dma_proc_seq_show(struct seq_file *file, void *data) +{ + int result; + struct mxs_dma_chan *pchan = (struct mxs_dma_chan *)data; + struct mxs_dma_device *pdev = pchan->dma; + result = seq_printf(file, "%s-channel%-d (%s)\n", + pdev->name, + pchan - mxs_dma_channels, + pchan->name ? pchan->name : "idle"); + return result; +} + +static const struct seq_operations mxc_dma_proc_seq_ops = { + .start = mxs_dma_proc_seq_start, + .next = mxs_dma_proc_seq_next, + .stop = mxs_dma_proc_seq_stop, + .show = mxs_dma_proc_seq_show +}; + +static int mxs_dma_proc_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &mxc_dma_proc_seq_ops); +} + +static const struct file_operations mxs_dma_proc_info_ops = { + .open = mxs_dma_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int __init mxs_dmaengine_info_init(void) +{ + struct proc_dir_entry *res; + res = create_proc_entry("dma-engine", 0, NULL); + if (!res) { + printk(KERN_ERR "Failed to create dma info file \n"); + return -ENOMEM; + } + res->proc_fops = &mxs_dma_proc_info_ops; + return 0; +} + +late_initcall(mxs_dmaengine_info_init); +#endif diff --git a/arch/arm/mach-mx5/early_setup.c b/arch/arm/mach-mx5/early_setup.c new file mode 100644 index 000000000000..dd731d7f822e --- /dev/null +++ b/arch/arm/mach-mx5/early_setup.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include + +int __initdata primary_di = { 0 }; +static int __init di_setup(char *__unused) +{ + primary_di = 1; + return 1; +} +__setup("di1_primary", di_setup); + diff --git a/arch/arm/mach-mx5/mx50_arm2.c b/arch/arm/mach-mx5/mx50_arm2.c new file mode 100644 index 000000000000..13de0971ace4 --- /dev/null +++ b/arch/arm/mach-mx5/mx50_arm2.c @@ -0,0 +1,1278 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "devices.h" +#include "crm_regs.h" +#include "usb.h" +#include "dma-apbh.h" + +#define SD1_WP (3*32 + 19) /*GPIO_4_19 */ +#define SD1_CD (0*32 + 27) /*GPIO_1_27 */ +#define SD2_WP (4*32 + 16) /*GPIO_5_16 */ +#define SD2_CD (4*32 + 17) /*GPIO_5_17 */ +#define SD3_WP (4*32 + 28) /*GPIO_5_28 */ +#define SD3_CD (3*32 + 4) /*GPIO_4_4 */ +#define HP_DETECT (3*32 + 15) /*GPIO_4_15 */ +#define PWR_INT (3*32 + 18) /*GPIO_4_18 */ + +#define EPDC_D0 (2*32 + 1) /*GPIO_3_0 */ +#define EPDC_D1 (2*32 + 2) /*GPIO_3_1 */ +#define EPDC_D2 (2*32 + 3) /*GPIO_3_2 */ +#define EPDC_D3 (2*32 + 4) /*GPIO_3_3 */ +#define EPDC_D4 (2*32 + 5) /*GPIO_3_4 */ +#define EPDC_D5 (2*32 + 6) /*GPIO_3_5 */ +#define EPDC_D6 (2*32 + 7) /*GPIO_3_6 */ +#define EPDC_D7 (2*32 + 8) /*GPIO_3_7 */ +#define EPDC_GDCLK (2*32 + 16) /*GPIO_3_16 */ +#define EPDC_GDSP (2*32 + 17) /*GPIO_3_17 */ +#define EPDC_GDOE (2*32 + 18) /*GPIO_3_18 */ +#define EPDC_GDRL (2*32 + 19) /*GPIO_3_19 */ +#define EPDC_SDCLK (2*32 + 20) /*GPIO_3_20 */ +#define EPDC_SDOE (2*32 + 23) /*GPIO_3_23 */ +#define EPDC_SDLE (2*32 + 24) /*GPIO_3_24 */ +#define EPDC_SDSHR (2*32 + 26) /*GPIO_3_26 */ +#define EPDC_BDR0 (3*32 + 23) /*GPIO_4_23 */ +#define EPDC_SDCE0 (3*32 + 25) /*GPIO_4_25 */ +#define EPDC_SDCE1 (3*32 + 26) /*GPIO_4_26 */ +#define EPDC_SDCE2 (3*32 + 27) /*GPIO_4_27 */ + +#define EPDC_PMIC_WAKE (5*32 + 16) /*GPIO_6_16 */ +#define EPDC_PMIC_INT (5*32 + 17) /*GPIO_6_17 */ +#define EPDC_VCOM (3*32 + 21) /*GPIO_4_21 */ +#define EPDC_PWRSTAT (2*32 + 28) /*GPIO_3_28 */ +#define EPDC_ELCDIF_BACKLIGHT (1*32 + 18) /*GPIO_2_18 */ +#define CSPI_CS1 (3*32 + 13) /*GPIO_4_13 */ +#define CSPI_CS2 (3*32 + 11) /*GPIO_4_11*/ + +extern int __init mx50_arm2_init_mc13892(void); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); +static int num_cpu_wp = 2; + +static struct pad_desc mx50_armadillo2[] = { + /* SD1 */ + MX50_PAD_ECSPI2_SS0__GPIO_4_19, + MX50_PAD_EIM_CRE__GPIO_1_27, + MX50_PAD_SD1_CMD__SD1_CMD, + + MX50_PAD_SD1_CLK__SD1_CLK, + MX50_PAD_SD1_D0__SD1_D0, + MX50_PAD_SD1_D1__SD1_D1, + MX50_PAD_SD1_D2__SD1_D2, + MX50_PAD_SD1_D3__SD1_D3, + + /* SD2 */ + MX50_PAD_SD2_CD__GPIO_5_17, + MX50_PAD_SD2_WP__GPIO_5_16, + MX50_PAD_SD2_CMD__SD2_CMD, + MX50_PAD_SD2_CLK__SD2_CLK, + MX50_PAD_SD2_D0__SD2_D0, + MX50_PAD_SD2_D1__SD2_D1, + MX50_PAD_SD2_D2__SD2_D2, + MX50_PAD_SD2_D3__SD2_D3, + MX50_PAD_SD2_D4__SD2_D4, + MX50_PAD_SD2_D5__SD2_D5, + MX50_PAD_SD2_D6__SD2_D6, + MX50_PAD_SD2_D7__SD2_D7, + + /* SD3 */ + MX50_PAD_SD3_WP__GPIO_5_28, + MX50_PAD_KEY_COL2__GPIO_4_4, + MX50_PAD_SD3_CMD__SD3_CMD, + MX50_PAD_SD3_CLK__SD3_CLK, + MX50_PAD_SD3_D0__SD3_D0, + MX50_PAD_SD3_D1__SD3_D1, + MX50_PAD_SD3_D2__SD3_D2, + MX50_PAD_SD3_D3__SD3_D3, + MX50_PAD_SD3_D4__SD3_D4, + MX50_PAD_SD3_D5__SD3_D5, + MX50_PAD_SD3_D6__SD3_D6, + MX50_PAD_SD3_D7__SD3_D7, + + MX50_PAD_SSI_RXD__SSI_RXD, + MX50_PAD_SSI_TXD__SSI_TXD, + MX50_PAD_SSI_TXC__SSI_TXC, + MX50_PAD_SSI_TXFS__SSI_TXFS, + + /* LINE1_DETECT (headphone detect) */ + MX50_PAD_ECSPI1_SS0__GPIO_4_15, + + /* PWR_INT */ + MX50_PAD_ECSPI2_MISO__GPIO_4_18, + + /* UART pad setting */ + MX50_PAD_UART1_TXD__UART1_TXD, + MX50_PAD_UART1_RXD__UART1_RXD, + MX50_PAD_UART1_CTS__UART1_CTS, + MX50_PAD_UART1_RTS__UART1_RTS, + MX50_PAD_UART2_TXD__UART2_TXD, + MX50_PAD_UART2_RXD__UART2_RXD, + MX50_PAD_UART2_CTS__UART2_CTS, + MX50_PAD_UART2_RTS__UART2_RTS, + + MX50_PAD_I2C1_SCL__I2C1_SCL, + MX50_PAD_I2C1_SDA__I2C1_SDA, + MX50_PAD_I2C2_SCL__I2C2_SCL, + MX50_PAD_I2C2_SDA__I2C2_SDA, + MX50_PAD_I2C3_SCL__I2C3_SCL, + MX50_PAD_I2C3_SDA__I2C3_SDA, + + /* EPDC pins */ + MX50_PAD_EPDC_D0__EPDC_D0, + MX50_PAD_EPDC_D1__EPDC_D1, + MX50_PAD_EPDC_D2__EPDC_D2, + MX50_PAD_EPDC_D3__EPDC_D3, + MX50_PAD_EPDC_D4__EPDC_D4, + MX50_PAD_EPDC_D5__EPDC_D5, + MX50_PAD_EPDC_D6__EPDC_D6, + MX50_PAD_EPDC_D7__EPDC_D7, + MX50_PAD_EPDC_GDCLK__EPDC_GDCLK, + MX50_PAD_EPDC_GDSP__EPDC_GDSP, + MX50_PAD_EPDC_GDOE__EPDC_GDOE , + MX50_PAD_EPDC_GDRL__EPDC_GDRL, + MX50_PAD_EPDC_SDCLK__EPDC_SDCLK, + MX50_PAD_EPDC_SDOE__EPDC_SDOE, + MX50_PAD_EPDC_SDLE__EPDC_SDLE, + MX50_PAD_EPDC_SDSHR__EPDC_SDSHR, + MX50_PAD_EPDC_BDR0__EPDC_BDR0, + MX50_PAD_EPDC_SDCE0__EPDC_SDCE0, + MX50_PAD_EPDC_SDCE1__EPDC_SDCE1, + MX50_PAD_EPDC_SDCE2__EPDC_SDCE2, + + MX50_PAD_EPDC_PWRSTAT__GPIO_3_28, + MX50_PAD_EPDC_VCOM0__GPIO_4_21, + + MX50_PAD_DISP_D8__DISP_D8, + MX50_PAD_DISP_D9__DISP_D9, + MX50_PAD_DISP_D10__DISP_D10, + MX50_PAD_DISP_D11__DISP_D11, + MX50_PAD_DISP_D12__DISP_D12, + MX50_PAD_DISP_D13__DISP_D13, + MX50_PAD_DISP_D14__DISP_D14, + MX50_PAD_DISP_D15__DISP_D15, + MX50_PAD_DISP_RS__ELCDIF_VSYNC, + + /* ELCDIF contrast */ + MX50_PAD_DISP_BUSY__GPIO_2_18, + + MX50_PAD_DISP_CS__ELCDIF_HSYNC, + MX50_PAD_DISP_RD__ELCDIF_EN, + MX50_PAD_DISP_WR__ELCDIF_PIXCLK, + + /* EPD PMIC WAKEUP */ + MX50_PAD_UART4_TXD__GPIO_6_16, + + /* EPD PMIC intr */ + MX50_PAD_UART4_RXD__GPIO_6_17, + + MX50_PAD_EPITO__USBH1_PWR, + /* Need to comment below line if + * one needs to debug owire. + */ + MX50_PAD_OWIRE__USBH1_OC, + MX50_PAD_PWM2__USBOTG_PWR, + MX50_PAD_PWM1__USBOTG_OC, + + MX50_PAD_SSI_RXC__FEC_MDIO, + MX50_PAD_SSI_RXC__FEC_MDIO, + MX50_PAD_DISP_D0__FEC_TXCLK, + MX50_PAD_DISP_D1__FEC_RX_ER, + MX50_PAD_DISP_D2__FEC_RX_DV, + MX50_PAD_DISP_D3__FEC_RXD1, + MX50_PAD_DISP_D4__FEC_RXD0, + MX50_PAD_DISP_D5__FEC_TX_EN, + MX50_PAD_DISP_D6__FEC_TXD1, + MX50_PAD_DISP_D7__FEC_TXD0, + MX50_PAD_SSI_RXFS__FEC_MDC, + + MX50_PAD_CSPI_SS0__CSPI_SS0, + MX50_PAD_ECSPI1_MOSI__CSPI_SS1, + MX50_PAD_CSPI_MOSI__CSPI_MOSI, + MX50_PAD_CSPI_MISO__CSPI_MISO, +}; + +static struct pad_desc mx50_gpmi_nand[] = { + MX50_PIN_EIM_DA8__NANDF_CLE, + MX50_PIN_EIM_DA9__NANDF_ALE, + MX50_PIN_EIM_DA10__NANDF_CE0, + MX50_PIN_EIM_DA11__NANDF_CE1, + MX50_PIN_EIM_DA12__NANDF_CE2, + MX50_PIN_EIM_DA13__NANDF_CE3, + MX50_PIN_EIM_DA14__NANDF_READY, + MX50_PIN_EIM_DA15__NANDF_DQS, + MX50_PIN_SD3_D4__NANDF_D0, + MX50_PIN_SD3_D5__NANDF_D1, + MX50_PIN_SD3_D6__NANDF_D2, + MX50_PIN_SD3_D7__NANDF_D3, + MX50_PIN_SD3_D0__NANDF_D4, + MX50_PIN_SD3_D1__NANDF_D5, + MX50_PIN_SD3_D2__NANDF_D6, + MX50_PIN_SD3_D3__NANDF_D7, + MX50_PIN_SD3_CLK__NANDF_RDN, + MX50_PIN_SD3_CMD__NANDF_WRN, + MX50_PIN_SD3_WP__NANDF_RESETN, +}; + +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, + .num_wp = 2, +}; + +/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1050000,}, + { + .pll_rate = 800000000, + .cpu_rate = 160000000, + .pdf = 4, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 4, + .cpu_voltage = 850000,}, +}; + +static struct cpu_wp *mx50_arm2_get_cpu_wp(int *wp) +{ + *wp = num_cpu_wp; + return cpu_wp_auto; +} + +static void mx50_arm2_set_num_cpu_wp(int num) +{ + num_cpu_wp = num; + return; +} + +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 1, +}; + +static struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, + .phy_mask = ~1UL, +}; + +/* workaround for cspi chipselect pin may not keep correct level when idle */ +static void mx50_arm2_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + break; + case 2: + break; + case 3: + switch (chipselect) { + case 0x1: + { + struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__CSPI_SS0; + struct pad_desc cspi_cs1 = MX50_PAD_ECSPI1_MOSI__GPIO_4_13; + + /* pull up/down deassert it */ + mxc_iomux_v3_setup_pad(&cspi_ss0); + mxc_iomux_v3_setup_pad(&cspi_cs1); + + gpio_request(CSPI_CS1, "cspi-cs1"); + gpio_direction_input(CSPI_CS1); + } + break; + case 0x2: + { + struct pad_desc cspi_ss1 = MX50_PAD_ECSPI1_MOSI__CSPI_SS1; + struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__GPIO_4_11; + + /*disable other ss */ + mxc_iomux_v3_setup_pad(&cspi_ss1); + mxc_iomux_v3_setup_pad(&cspi_ss0); + + /* pull up/down deassert it */ + gpio_request(CSPI_CS2, "cspi-cs2"); + gpio_direction_input(CSPI_CS2); + } + break; + default: + break; + } + break; + + default: + break; + } +} + +static void mx50_arm2_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + break; + case 2: + break; + case 3: + switch (chipselect) { + case 0x1: + gpio_free(CSPI_CS1); + break; + case 0x2: + gpio_free(CSPI_CS2); + break; + default: + break; + } + break; + default: + break; + } + +} + +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, + .chipselect_active = mx50_arm2_gpio_spi_chipselect_active, + .chipselect_inactive = mx50_arm2_gpio_spi_chipselect_inactive, +}; + +static struct mxc_spi_master mxcspi3_data = { + .maxchipselect = 4, + .spi_version = 7, + .chipselect_active = mx50_arm2_gpio_spi_chipselect_active, + .chipselect_inactive = mx50_arm2_gpio_spi_chipselect_inactive, +}; + +static struct mxc_i2c_platform_data mxci2c_data = { + .i2c_clk = 100000, +}; + +static struct mxc_srtc_platform_data srtc_data = { + .srtc_sec_mode_addr = OCOTP_CTRL_BASE_ADDR + 0x80, +}; + +static int z160_version = 1; + +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +static struct regulator_init_data max17135_init_data[] __initdata = { + { + .constraints = { + .name = "DISPLAY", + }, + }, { + .constraints = { + .name = "GVDD", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "GVEE", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINN", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINP", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "VCOM", + .min_uV = mV_to_uV(-4325), + .max_uV = mV_to_uV(-500), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + }, { + .constraints = { + .name = "VNEG", + .min_uV = V_to_uV(-15), + .max_uV = V_to_uV(-15), + }, + }, { + .constraints = { + .name = "VPOS", + .min_uV = V_to_uV(15), + .max_uV = V_to_uV(15), + }, + }, +}; + +static void epdc_get_pins(void) +{ + /* Claim GPIOs for EPDC pins - used during power up/down */ + gpio_request(EPDC_D0, "epdc_d0"); + gpio_request(EPDC_D1, "epdc_d1"); + gpio_request(EPDC_D2, "epdc_d2"); + gpio_request(EPDC_D3, "epdc_d3"); + gpio_request(EPDC_D4, "epdc_d4"); + gpio_request(EPDC_D5, "epdc_d5"); + gpio_request(EPDC_D6, "epdc_d6"); + gpio_request(EPDC_D7, "epdc_d7"); + gpio_request(EPDC_GDCLK, "epdc_gdclk"); + gpio_request(EPDC_GDSP, "epdc_gdsp"); + gpio_request(EPDC_GDOE, "epdc_gdoe"); + gpio_request(EPDC_GDRL, "epdc_gdrl"); + gpio_request(EPDC_SDCLK, "epdc_sdclk"); + gpio_request(EPDC_SDOE, "epdc_sdoe"); + gpio_request(EPDC_SDLE, "epdc_sdle"); + gpio_request(EPDC_SDSHR, "epdc_sdshr"); + gpio_request(EPDC_BDR0, "epdc_bdr0"); + gpio_request(EPDC_SDCE0, "epdc_sdce0"); + gpio_request(EPDC_SDCE1, "epdc_sdce1"); + gpio_request(EPDC_SDCE2, "epdc_sdce2"); +} + +static void epdc_put_pins(void) +{ + gpio_free(EPDC_D0); + gpio_free(EPDC_D1); + gpio_free(EPDC_D2); + gpio_free(EPDC_D3); + gpio_free(EPDC_D4); + gpio_free(EPDC_D5); + gpio_free(EPDC_D6); + gpio_free(EPDC_D7); + gpio_free(EPDC_GDCLK); + gpio_free(EPDC_GDSP); + gpio_free(EPDC_GDOE); + gpio_free(EPDC_GDRL); + gpio_free(EPDC_SDCLK); + gpio_free(EPDC_SDOE); + gpio_free(EPDC_SDLE); + gpio_free(EPDC_SDSHR); + gpio_free(EPDC_BDR0); + gpio_free(EPDC_SDCE0); + gpio_free(EPDC_SDCE1); + gpio_free(EPDC_SDCE2); +} + +static void epdc_enable_pins(void) +{ + struct pad_desc epdc_d0 = MX50_PAD_EPDC_D0__EPDC_D0; + struct pad_desc epdc_d1 = MX50_PAD_EPDC_D1__EPDC_D1; + struct pad_desc epdc_d2 = MX50_PAD_EPDC_D2__EPDC_D2; + struct pad_desc epdc_d3 = MX50_PAD_EPDC_D3__EPDC_D3; + struct pad_desc epdc_d4 = MX50_PAD_EPDC_D4__EPDC_D4; + struct pad_desc epdc_d5 = MX50_PAD_EPDC_D5__EPDC_D5; + struct pad_desc epdc_d6 = MX50_PAD_EPDC_D6__EPDC_D6; + struct pad_desc epdc_d7 = MX50_PAD_EPDC_D7__EPDC_D7; + struct pad_desc epdc_gdclk = MX50_PAD_EPDC_GDCLK__EPDC_GDCLK; + struct pad_desc epdc_gdsp = MX50_PAD_EPDC_GDSP__EPDC_GDSP; + struct pad_desc epdc_gdoe = MX50_PAD_EPDC_GDOE__EPDC_GDOE; + struct pad_desc epdc_gdrl = MX50_PAD_EPDC_GDRL__EPDC_GDRL; + struct pad_desc epdc_sdclk = MX50_PAD_EPDC_SDCLK__EPDC_SDCLK; + struct pad_desc epdc_sdoe = MX50_PAD_EPDC_SDOE__EPDC_SDOE; + struct pad_desc epdc_sdle = MX50_PAD_EPDC_SDLE__EPDC_SDLE; + struct pad_desc epdc_sdshr = MX50_PAD_EPDC_SDSHR__EPDC_SDSHR; + struct pad_desc epdc_bdr0 = MX50_PAD_EPDC_BDR0__EPDC_BDR0; + struct pad_desc epdc_sdce0 = MX50_PAD_EPDC_SDCE0__EPDC_SDCE0; + struct pad_desc epdc_sdce1 = MX50_PAD_EPDC_SDCE1__EPDC_SDCE1; + struct pad_desc epdc_sdce2 = MX50_PAD_EPDC_SDCE2__EPDC_SDCE2; + + /* Configure MUX settings to enable EPDC use */ + mxc_iomux_v3_setup_pad(&epdc_d0); + mxc_iomux_v3_setup_pad(&epdc_d1); + mxc_iomux_v3_setup_pad(&epdc_d2); + mxc_iomux_v3_setup_pad(&epdc_d3); + mxc_iomux_v3_setup_pad(&epdc_d4); + mxc_iomux_v3_setup_pad(&epdc_d5); + mxc_iomux_v3_setup_pad(&epdc_d6); + mxc_iomux_v3_setup_pad(&epdc_d7); + mxc_iomux_v3_setup_pad(&epdc_gdclk); + mxc_iomux_v3_setup_pad(&epdc_gdsp); + mxc_iomux_v3_setup_pad(&epdc_gdoe); + mxc_iomux_v3_setup_pad(&epdc_gdrl); + mxc_iomux_v3_setup_pad(&epdc_sdclk); + mxc_iomux_v3_setup_pad(&epdc_sdoe); + mxc_iomux_v3_setup_pad(&epdc_sdle); + mxc_iomux_v3_setup_pad(&epdc_sdshr); + mxc_iomux_v3_setup_pad(&epdc_bdr0); + mxc_iomux_v3_setup_pad(&epdc_sdce0); + mxc_iomux_v3_setup_pad(&epdc_sdce1); + mxc_iomux_v3_setup_pad(&epdc_sdce2); + + gpio_direction_input(EPDC_D0); + gpio_direction_input(EPDC_D1); + gpio_direction_input(EPDC_D2); + gpio_direction_input(EPDC_D3); + gpio_direction_input(EPDC_D4); + gpio_direction_input(EPDC_D5); + gpio_direction_input(EPDC_D6); + gpio_direction_input(EPDC_D7); + gpio_direction_input(EPDC_GDCLK); + gpio_direction_input(EPDC_GDSP); + gpio_direction_input(EPDC_GDOE); + gpio_direction_input(EPDC_GDRL); + gpio_direction_input(EPDC_SDCLK); + gpio_direction_input(EPDC_SDOE); + gpio_direction_input(EPDC_SDLE); + gpio_direction_input(EPDC_SDSHR); + gpio_direction_input(EPDC_BDR0); + gpio_direction_input(EPDC_SDCE0); + gpio_direction_input(EPDC_SDCE1); + gpio_direction_input(EPDC_SDCE2); +} + +static void epdc_disable_pins(void) +{ + struct pad_desc epdc_d0 = MX50_PAD_EPDC_D0__GPIO_3_0; + struct pad_desc epdc_d1 = MX50_PAD_EPDC_D1__GPIO_3_1; + struct pad_desc epdc_d2 = MX50_PAD_EPDC_D2__GPIO_3_2; + struct pad_desc epdc_d3 = MX50_PAD_EPDC_D3__GPIO_3_3; + struct pad_desc epdc_d4 = MX50_PAD_EPDC_D4__GPIO_3_4; + struct pad_desc epdc_d5 = MX50_PAD_EPDC_D5__GPIO_3_5; + struct pad_desc epdc_d6 = MX50_PAD_EPDC_D6__GPIO_3_6; + struct pad_desc epdc_d7 = MX50_PAD_EPDC_D7__GPIO_3_7; + struct pad_desc epdc_gdclk = MX50_PAD_EPDC_GDCLK__GPIO_3_16; + struct pad_desc epdc_gdsp = MX50_PAD_EPDC_GDSP__GPIO_3_17; + struct pad_desc epdc_gdoe = MX50_PAD_EPDC_GDOE__GPIO_3_18; + struct pad_desc epdc_gdrl = MX50_PAD_EPDC_GDRL__GPIO_3_19; + struct pad_desc epdc_sdclk = MX50_PAD_EPDC_SDCLK__GPIO_3_20; + struct pad_desc epdc_sdoe = MX50_PAD_EPDC_SDOE__GPIO_3_23; + struct pad_desc epdc_sdle = MX50_PAD_EPDC_SDLE__GPIO_3_24; + struct pad_desc epdc_sdshr = MX50_PAD_EPDC_SDSHR__GPIO_3_26; + struct pad_desc epdc_bdr0 = MX50_PAD_EPDC_BDR0__GPIO_4_23; + struct pad_desc epdc_sdce0 = MX50_PAD_EPDC_SDCE0__GPIO_4_25; + struct pad_desc epdc_sdce1 = MX50_PAD_EPDC_SDCE1__GPIO_4_26; + struct pad_desc epdc_sdce2 = MX50_PAD_EPDC_SDCE2__GPIO_4_27; + + /* Configure MUX settings for EPDC pins to + * GPIO and drive to 0. */ + mxc_iomux_v3_setup_pad(&epdc_d0); + mxc_iomux_v3_setup_pad(&epdc_d1); + mxc_iomux_v3_setup_pad(&epdc_d2); + mxc_iomux_v3_setup_pad(&epdc_d3); + mxc_iomux_v3_setup_pad(&epdc_d4); + mxc_iomux_v3_setup_pad(&epdc_d5); + mxc_iomux_v3_setup_pad(&epdc_d6); + mxc_iomux_v3_setup_pad(&epdc_d7); + mxc_iomux_v3_setup_pad(&epdc_gdclk); + mxc_iomux_v3_setup_pad(&epdc_gdsp); + mxc_iomux_v3_setup_pad(&epdc_gdoe); + mxc_iomux_v3_setup_pad(&epdc_gdrl); + mxc_iomux_v3_setup_pad(&epdc_sdclk); + mxc_iomux_v3_setup_pad(&epdc_sdoe); + mxc_iomux_v3_setup_pad(&epdc_sdle); + mxc_iomux_v3_setup_pad(&epdc_sdshr); + mxc_iomux_v3_setup_pad(&epdc_bdr0); + mxc_iomux_v3_setup_pad(&epdc_sdce0); + mxc_iomux_v3_setup_pad(&epdc_sdce1); + mxc_iomux_v3_setup_pad(&epdc_sdce2); + + gpio_direction_output(EPDC_D0, 0); + gpio_direction_output(EPDC_D1, 0); + gpio_direction_output(EPDC_D2, 0); + gpio_direction_output(EPDC_D3, 0); + gpio_direction_output(EPDC_D4, 0); + gpio_direction_output(EPDC_D5, 0); + gpio_direction_output(EPDC_D6, 0); + gpio_direction_output(EPDC_D7, 0); + gpio_direction_output(EPDC_GDCLK, 0); + gpio_direction_output(EPDC_GDSP, 0); + gpio_direction_output(EPDC_GDOE, 0); + gpio_direction_output(EPDC_GDRL, 0); + gpio_direction_output(EPDC_SDCLK, 0); + gpio_direction_output(EPDC_SDOE, 0); + gpio_direction_output(EPDC_SDLE, 0); + gpio_direction_output(EPDC_SDSHR, 0); + gpio_direction_output(EPDC_BDR0, 0); + gpio_direction_output(EPDC_SDCE0, 0); + gpio_direction_output(EPDC_SDCE1, 0); + gpio_direction_output(EPDC_SDCE2, 0); +} + +static struct fb_videomode e60_mode = { + .name = "E60", + .refresh = 50, + .xres = 800, + .yres = 600, + .pixclock = 20000000, + .left_margin = 10, + .right_margin = 217, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct fb_videomode e97_mode = { + .name = "E97", + .refresh = 50, + .xres = 1200, + .yres = 825, + .pixclock = 32000000, + .left_margin = 8, + .right_margin = 125, + .upper_margin = 4, + .lower_margin = 17, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct mxc_epdc_fb_mode panel_modes[] = { + { + &e60_mode, + 4, 10, 20, 10, 20, 480, 20, 0, 1, 1, + }, + { + &e97_mode, + 8, 10, 20, 10, 20, 580, 20, 0, 1, 3, + }, +}; + +static struct mxc_epdc_fb_platform_data epdc_data = { + .epdc_mode = panel_modes, + .num_modes = ARRAY_SIZE(panel_modes), + .get_pins = epdc_get_pins, + .put_pins = epdc_put_pins, + .enable_pins = epdc_enable_pins, + .disable_pins = epdc_disable_pins, +}; + + +static struct max17135_platform_data max17135_pdata __initdata = { + .vneg_pwrup = 1, + .gvee_pwrup = 1, + .vpos_pwrup = 2, + .gvdd_pwrup = 1, + .gvdd_pwrdn = 1, + .vpos_pwrdn = 2, + .gvee_pwrdn = 1, + .vneg_pwrdn = 1, + .gpio_pmic_pwrgood = EPDC_PWRSTAT, + .gpio_pmic_vcom_ctrl = EPDC_VCOM, + .gpio_pmic_wakeup = EPDC_PMIC_WAKE, + .gpio_pmic_intr = EPDC_PMIC_INT, + .regulator_init = max17135_init_data, +}; + +static int __initdata max17135_pass_num = { 1 }; +static int __initdata max17135_vcom = { -1250000 }; +/* + * Parse user specified options (`max17135:') + * example: + * max17135:pass=2,vcom=-1250000 + */ +static int __init max17135_setup(char *options) +{ + char *opt; + while ((opt = strsep(&options, ",")) != NULL) { + if (!*opt) + continue; + if (!strncmp(opt, "pass=", 5)) + max17135_pass_num = + simple_strtoul(opt + 5, NULL, 0); + if (!strncmp(opt, "vcom=", 5)) { + int offs = 5; + if (opt[5] == '-') + offs = 6; + max17135_vcom = + simple_strtoul(opt + offs, NULL, 0); + max17135_vcom = -max17135_vcom; + } + } + return 1; +} + +__setup("max17135:", max17135_setup); + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, + { + .type = "backlight-i2c", + .addr = 0x2c, + }, + { + .type = "eeprom", + .addr = 0x50, + }, +}; + +static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { + { + I2C_BOARD_INFO("max17135", 0x48), + .platform_data = &max17135_pdata, + }, +}; + +static struct mtd_partition mxc_dataflash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x000100000,}, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL,}, +}; + +static struct flash_platform_data mxc_spi_flash_data[] = { + { + .name = "mxc_dataflash", + .parts = mxc_dataflash_partitions, + .nr_parts = ARRAY_SIZE(mxc_dataflash_partitions), + .type = "at45db321d",} +}; + + +static struct spi_board_info mxc_dataflash_device[] __initdata = { + { + .modalias = "mxc_dataflash", + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 3, + .chip_select = 1, + .platform_data = &mxc_spi_flash_data[0],}, +}; + +static int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + if (to_platform_device(dev)->id == 0) + rc = gpio_get_value(SD1_WP); + else if (to_platform_device(dev)->id == 1) + rc = gpio_get_value(SD2_WP); + else if (to_platform_device(dev)->id == 2) + rc = gpio_get_value(SD3_WP); + + return rc; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret = 0; + if (to_platform_device(dev)->id == 0) + ret = gpio_get_value(SD1_CD); + else if (to_platform_device(dev)->id == 1) + ret = gpio_get_value(SD2_CD); + else if (to_platform_device(dev)->id == 2) + ret = gpio_get_value(SD3_CD); + + return ret; +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc2_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static struct mxc_mmc_platform_data mmc3_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_DATA_DDR, + .min_clk = 400000, + .max_clk = 40000000, + .dll_override_en = 1, + .dll_delay_cells = 0xc, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .clk_always_on = 1, +}; + +static int mxc_sgtl5000_amp_enable(int enable) +{ +/* TO DO */ + return 0; +} + +static int headphone_det_status(void) +{ + return (gpio_get_value(HP_DETECT) != 0); +} + +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .hp_irq = IOMUX_TO_IRQ_V3(HP_DETECT), + .hp_status = headphone_det_status, + .amp_enable = mxc_sgtl5000_amp_enable, + .sysclk = 12288000, +}; + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", +}; + +static struct pad_desc armadillo2_wvga_pads[] = { + MX50_PAD_DISP_D0__DISP_D0, + MX50_PAD_DISP_D1__DISP_D1, + MX50_PAD_DISP_D2__DISP_D2, + MX50_PAD_DISP_D3__DISP_D3, + MX50_PAD_DISP_D4__DISP_D4, + MX50_PAD_DISP_D5__DISP_D5, + MX50_PAD_DISP_D6__DISP_D6, + MX50_PAD_DISP_D7__DISP_D7, +}; + +static void wvga_reset(void) +{ + mxc_iomux_v3_setup_multiple_pads(armadillo2_wvga_pads, \ + ARRAY_SIZE(armadillo2_wvga_pads)); + return; +} + +static struct mxc_lcd_platform_data lcd_wvga_data = { + .reset = wvga_reset, +}; + +static struct platform_device lcd_wvga_device = { + .name = "lcd_claa", + .dev = { + .platform_data = &lcd_wvga_data, + }, +}; + +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = V4L2_PIX_FMT_RGB565, + .mode_str = "CLAA-WVGA", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, +}; + +static int __initdata enable_w1 = { 0 }; +static int __init w1_setup(char *__unused) +{ + enable_w1 = 1; + return cpu_is_mx50(); +} + +__setup("w1", w1_setup); + +int enable_gpmi_nand = { 0 }; +static int __init gpmi_nand_setup(char *__unused) +{ + enable_gpmi_nand = 1; + return 1; +} + +__setup("gpmi:nand", gpmi_nand_setup); + +static struct mxs_dma_plat_data dma_apbh_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBH, + .chan_num = MXS_MAX_DMA_CHANNELS, +}; + +static int gpmi_nfc_platform_init(unsigned int max_chip_count) +{ + return !enable_gpmi_nand; +} + +static void gpmi_nfc_platform_exit(unsigned int max_chip_count) +{ +} + +static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 }; + +static struct gpmi_nfc_platform_data gpmi_nfc_platform_data = { + .nfc_version = 2, + .boot_rom_version = 1, + .clock_name = "gpmi-nfc", + .platform_init = gpmi_nfc_platform_init, + .platform_exit = gpmi_nfc_platform_exit, + .min_prop_delay_in_ns = 5, + .max_prop_delay_in_ns = 9, + .max_chip_count = 2, + .boot_area_size_in_bytes = 20 * SZ_1M, + .partition_source_types = gpmi_nfc_partition_source_types, + .partitions = 0, + .partition_count = 0, +}; + +static struct android_pmem_platform_data android_pmem_pdata = { + .name = "pmem_adsp", + .start = 0, + .size = SZ_4M, + .no_allocator = 0, + .cached = PMEM_NONCACHE_NORMAL, +}; + +static struct android_pmem_platform_data android_pmem_gpu_pdata = { + .name = "pmem_gpu", + .start = 0, + .size = SZ_32M, + .no_allocator = 0, + .cached = PMEM_CACHE_ENABLE, +}; + +static struct android_usb_platform_data android_usb_pdata = { + .vendor_id = 0x0bb4, + .product_id = 0x0c01, + .adb_product_id = 0x0c02, + .version = 0x0100, + .product_name = "Android Phone", + .manufacturer_name = "Freescale", + .nluns = 3, +}; + +/* OTP data */ +/* Building up eight registers's names of a bank */ +#define BANK(a, b, c, d, e, f, g, h) \ + {\ + ("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \ + ("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \ + } + +#define BANKS (5) +#define BANK_ITEMS (8) +static const char *bank_reg_desc[BANKS][BANK_ITEMS] = { + BANK(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6), + BANK(MEM0, MEM1, MEM2, MEM3, MEM4, MEM5, GP0, GP1), + BANK(SCC0, SCC1, SCC2, SCC3, SCC4, SCC5, SCC6, SCC7), + BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), + BANK(SJC0, SJC1, MAC0, MAC1, HWCAP0, HWCAP1, HWCAP2, SWCAP), +}; + +static struct fsl_otp_data otp_data = { + .fuse_name = (char **)bank_reg_desc, + .fuse_num = BANKS * BANK_ITEMS, +}; +#undef BANK +#undef BANKS +#undef BANK_ITEMS + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + struct tag *t; + int size; + + mxc_set_cpu_type(MXC_CPU_MX50); + + get_cpu_wp = mx50_arm2_get_cpu_wp; + set_num_cpu_wp = mx50_arm2_set_num_cpu_wp; + + for_each_tag(t, tags) { + if (t->hdr.tag != ATAG_MEM) + continue; + size = t->u.mem.size; + + android_pmem_pdata.start = + PHYS_OFFSET + size - android_pmem_pdata.size; + android_pmem_gpu_pdata.start = + android_pmem_pdata.start - android_pmem_gpu_pdata.size; +#if 0 + gpu_device.resource[5].start = + android_pmem_gpu_pdata.start - SZ_16M; + gpu_device.resource[5].end = + gpu_device.resource[5].start + SZ_16M - 1; +#endif + size -= android_pmem_pdata.size; + size -= android_pmem_gpu_pdata.size; + //size -= SZ_16M; + t->u.mem.size = size; + } +} + +static void __init mx50_arm2_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx50_armadillo2, \ + ARRAY_SIZE(mx50_armadillo2)); + + gpio_request(SD1_WP, "sdhc1-wp"); + gpio_direction_input(SD1_WP); + + gpio_request(SD1_CD, "sdhc1-cd"); + gpio_direction_input(SD1_CD); + + gpio_request(SD2_WP, "sdhc2-wp"); + gpio_direction_input(SD2_WP); + + gpio_request(SD2_CD, "sdhc2-cd"); + gpio_direction_input(SD2_CD); + + gpio_request(SD3_WP, "sdhc3-wp"); + gpio_direction_input(SD3_WP); + + gpio_request(SD3_CD, "sdhc3-cd"); + gpio_direction_input(SD3_CD); + + gpio_request(HP_DETECT, "hp-det"); + gpio_direction_input(HP_DETECT); + + gpio_request(PWR_INT, "pwr-int"); + gpio_direction_input(PWR_INT); + + gpio_request(EPDC_PMIC_WAKE, "epdc-pmic-wake"); + gpio_direction_output(EPDC_PMIC_WAKE, 0); + + gpio_request(EPDC_VCOM, "epdc-vcom"); + gpio_direction_output(EPDC_VCOM, 0); + + gpio_request(EPDC_PMIC_INT, "epdc-pmic-int"); + gpio_direction_input(EPDC_PMIC_INT); + + gpio_request(EPDC_PWRSTAT, "epdc-pwrstat"); + gpio_direction_input(EPDC_PWRSTAT); + + /* ELCDIF backlight */ + gpio_request(EPDC_ELCDIF_BACKLIGHT, "elcdif-backlight"); + gpio_direction_output(EPDC_ELCDIF_BACKLIGHT, 1); + + if (enable_w1) { + struct pad_desc one_wire = MX50_PAD_OWIRE__OWIRE; + mxc_iomux_v3_setup_pad(&one_wire); + } + + if (enable_gpmi_nand) + mxc_iomux_v3_setup_multiple_pads(mx50_gpmi_nand, \ + ARRAY_SIZE(mx50_gpmi_nand)); +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + /* SD card detect irqs */ + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(SD1_CD); + mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(SD2_CD); + mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(SD2_CD); + mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ_V3(SD3_CD); + mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ_V3(SD3_CD); + + mxc_cpu_common_init(); + mxc_register_gpios(); + mx50_arm2_io_init(); + + mxc_register_device(&mxc_dma_device, NULL); + //mxc_register_device(&mxs_dma_apbh_device, &dma_apbh_data); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxcspi1_device, &mxcspi1_data); + mxc_register_device(&mxcspi3_device, &mxcspi3_data); + mxc_register_device(&mxci2c_devices[0], &mxci2c_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c_data); + mxc_register_device(&mxci2c_devices[2], &mxci2c_data); + + mxc_register_device(&mxc_rtc_device, &srtc_data); + mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); + mxc_register_device(&gpu_device, &z160_version); + mxc_register_device(&mxc_pxp_device, NULL); + mxc_register_device(&mxc_pxp_client_device, NULL); + mxc_register_device(&mxc_pxp_v4l2, NULL); + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + mxc_register_device(&busfreq_device, NULL); + + /* + mxc_register_device(&mx53_lpmode_device, NULL); + mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); + */ + +/* mxc_register_device(&mxc_keypad_device, &keypad_plat_data); */ + + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc2_device, &mmc2_data); + mxc_register_device(&mxcsdhc3_device, &mmc3_data); + mxc_register_device(&mxc_ssi1_device, NULL); + mxc_register_device(&mxc_ssi2_device, NULL); + mxc_register_device(&mxc_fec_device, &fec_data); + spi_register_board_info(mxc_dataflash_device, + ARRAY_SIZE(mxc_dataflash_device)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + max17135_pdata.pass_num = max17135_pass_num; + max17135_pdata.vcom_uV = max17135_vcom; + i2c_register_board_info(2, mxc_i2c2_board_info, + ARRAY_SIZE(mxc_i2c2_board_info)); + + mxc_register_device(&epdc_device, &epdc_data); + mxc_register_device(&lcd_wvga_device, &lcd_wvga_data); + mxc_register_device(&elcdif_device, &fb_data[0]); + mxc_register_device(&mxs_viim, NULL); + + mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata); + mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata); + mxc_register_device(&android_usb_device, &android_usb_pdata); + + mx50_arm2_init_mc13892(); +/* + pm_power_off = mxc_power_off; + */ + mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); + mxc_register_device(&gpmi_nfc_device, &gpmi_nfc_platform_data); + mx5_usb_dr_init(); + mx5_usbh1_init(); + + mxc_register_device(&mxc_rngb_device, NULL); + mxc_register_device(&dcp_device, NULL); + mxc_register_device(&fsl_otp_device, &otp_data); +} + +static void __init mx50_arm2_timer_init(void) +{ + struct clk *uart_clk; + + mx50_clocks_init(32768, 24000000, 22579200); + + uart_clk = clk_get(NULL, "uart_clk.0"); + early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx50_arm2_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX50_ARM2 data structure. + */ +MACHINE_START(MX50_ARM2, "Freescale MX50 ARM2 Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c b/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c new file mode 100644 index 000000000000..05b8462ade40 --- /dev/null +++ b/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c @@ -0,0 +1,418 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +/* Coin cell charger enable */ +#define COINCHEN_LSH 23 +#define COINCHEN_WID 1 +/* Coin cell charger voltage setting */ +#define VCOIN_LSH 20 +#define VCOIN_WID 3 + +/* Coin Charger voltage */ +#define VCOIN_2_5V 0x0 +#define VCOIN_2_7V 0x1 +#define VCOIN_2_8V 0x2 +#define VCOIN_2_9V 0x3 +#define VCOIN_3_0V 0x4 +#define VCOIN_3_1V 0x5 +#define VCOIN_3_2V 0x6 +#define VCOIN_3_3V 0x7 + +/* Keeps VSRTC and CLK32KMCU on for all states */ +#define DRM_LSH 4 +#define DRM_WID 1 + +/* regulator standby mask */ +#define GEN1_STBY_MASK (1 << 1) +#define IOHI_STBY_MASK (1 << 4) +#define DIG_STBY_MASK (1 << 10) +#define GEN2_STBY_MASK (1 << 13) +#define PLL_STBY_MASK (1 << 16) +#define USB2_STBY_MASK (1 << 19) + +#define GEN3_STBY_MASK (1 << 1) +#define CAM_STBY_MASK (1 << 7) +#define VIDEO_STBY_MASK (1 << 13) +#define AUDIO_STBY_MASK (1 << 16) +#define SD_STBY_MASK (1 << 19) + +#define REG_MODE_0_ALL_MASK (DIG_STBY_MASK | GEN1_STBY_MASK) +#define REG_MODE_1_ALL_MASK (CAM_STBY_MASK | VIDEO_STBY_MASK |\ + AUDIO_STBY_MASK | SD_STBY_MASK) + +/* switch mode setting */ +#define SW1MODE_LSB 0 +#define SW2MODE_LSB 10 +#define SW3MODE_LSB 0 +#define SW4MODE_LSB 8 + +#define SWMODE_MASK 0xF +#define SWMODE_AUTO 0x8 + +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +static struct regulator_consumer_supply vgen1_consumers[] = { + { + /* sgtl5000 */ + .supply = "VDDA", + .dev_name = "1-000a", + }, + { + /* sgtl5000 */ + .supply = "VDDIO", + .dev_name = "1-000a", + }, +}; + +struct mc13892; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 850000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .name = "VIOHI", + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb_init = { + .constraints = { + .name = "VUSB", + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data swbst_init = { + .constraints = { + .name = "SWBST", + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .name = "VDIG", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(1200), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data vpll_init = { + .constraints = { + .name = "VPLL", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vusb2_init = { + .constraints = { + .name = "VUSB2", + .min_uV = mV_to_uV(2400), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vvideo_init = { + .constraints = { + .name = "VVIDEO", + .min_uV = mV_to_uV(2775), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data vaudio_init = { + .constraints = { + .name = "VAUDIO", + .min_uV = mV_to_uV(2300), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vsd_init = { + .constraints = { + .name = "VSD", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + } +}; + +static struct regulator_init_data vcam_init = { + .constraints = { + .name = "VCAM", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, + .always_on = 1, + } +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "VGEN1", + .min_uV = mV_to_uV(3000), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vgen1_consumers), + .consumer_supplies = vgen1_consumers, +}; + +static struct regulator_init_data vgen2_init = { + .constraints = { + .name = "VGEN2", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + } +}; + +static struct regulator_init_data vgen3_init = { + .constraints = { + .name = "VGEN3", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + } +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .name = "GPO1", + } +}; + +static struct regulator_init_data gpo2_init = { + .constraints = { + .name = "GPO2", + } +}; + +static struct regulator_init_data gpo3_init = { + .constraints = { + .name = "GPO3", + } +}; + +static struct regulator_init_data gpo4_init = { + .constraints = { + .name = "GPO4", + } +}; + +static int mc13892_regulator_init(struct mc13892 *mc13892) +{ + unsigned int value, register_mask; + printk("Initializing regulators for mx50 arm2.\n"); + + /* enable standby controll for all regulators */ + pmic_read_reg(REG_MODE_0, &value, 0xffffff); + value |= REG_MODE_0_ALL_MASK; + pmic_write_reg(REG_MODE_0, value, 0xffffff); + + pmic_read_reg(REG_MODE_1, &value, 0xffffff); + value |= REG_MODE_1_ALL_MASK; + pmic_write_reg(REG_MODE_1, value, 0xffffff); + + /* enable switch audo mode */ + pmic_read_reg(REG_IDENTIFICATION, &value, 0xffffff); + /* only for mc13892 2.0A */ + if ((value & 0x0000FFFF) == 0x45d0) { + pmic_read_reg(REG_SW_4, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW1MODE_LSB) | + (SWMODE_MASK << SW2MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW1MODE_LSB) | + (SWMODE_AUTO << SW2MODE_LSB); + pmic_write_reg(REG_SW_4, value, 0xffffff); + + pmic_read_reg(REG_SW_5, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW3MODE_LSB) | + (SWMODE_MASK << SW4MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW3MODE_LSB) | + (SWMODE_AUTO << SW4MODE_LSB); + pmic_write_reg(REG_SW_5, value, 0xffffff); + } + /* Enable coin cell charger */ + value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V); + register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); + +#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) + value = BITFVAL(DRM, 1); + register_mask = BITFMASK(DRM); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); +#endif + + mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); + mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); + mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); + mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); + mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); + mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); + mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); + mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); + mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); + mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); + mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); + mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); + mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); + mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); + mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); + mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); + mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); + mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); + mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); + mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); + mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); + + regulator_has_full_constraints(); + + return 0; +} + +static struct mc13892_platform_data mc13892_plat = { + .init = mc13892_regulator_init, +}; + +static struct spi_board_info __initdata mc13892_spi_device = { + .modalias = "pmic_spi", + .irq = IOMUX_TO_IRQ_V3(114), + .max_speed_hz = 6000000, /* max spi SCK clock speed in HZ */ + .bus_num = 3, + .chip_select = 0, + .platform_data = &mc13892_plat, +}; + + +int __init mx50_arm2_init_mc13892(void) +{ + return spi_register_board_info(&mc13892_spi_device, 1); +} diff --git a/arch/arm/mach-mx5/mx50_ddr_freq.S b/arch/arm/mach-mx5/mx50_ddr_freq.S new file mode 100644 index 000000000000..7628b6a7c7e6 --- /dev/null +++ b/arch/arm/mach-mx5/mx50_ddr_freq.S @@ -0,0 +1,479 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include + +/* + * mx50_ddr_freq_change + * + * Idle the processor (eg, wait for interrupt). + * Make sure DDR is in self-refresh. + * IRQs are already disabled. + */ +ENTRY(mx50_ddr_freq_change) + stmfd sp!, {r3,r4,r5,r6} @ Save registers + + mov r6, r0 @save CCM address + mov r5, r1 @save DataBahn address + mov r4, r2 @save new freq requested + + ldr r0, [r6, #0x90] + + /* If Databahn is in LPM4, exit that mode first. */ + ldr r1,[r5, #0x50] @Store LPM mode in r1. + mov r0, r1 + bic r0, #0x1F + str r0,[r5, #0x50] + +LoopCKE2: + /*Wait for CKE = 1 */ + ldr r0,[r5, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + bne LoopCKE2 + + /* + * Make sure the DDR is self-refresh, before switching its frequency + * and clock source + */ + + /* Step 1: Enter self-refresh mode */ + ldr r0,[r5, #0x4c] + orr r0,r0,#0x1 + str r0,[r5, #0x4c] + + /* Step 2: Poll the CKE_STATUS bit. */ +LoopCKE0: + /* Wait for CKE = 0 */ + ldr r0,[r5, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + beq LoopCKE0 + + /* Step 3: Mask the DLL lock state change, set bit 8 in int_mask. */ + ldr r0, [r5, #0xac] + orr r0, r0, #0x100 + str r0, [r5, #0xac] + + /* Step 4: Stop the Controller. */ + ldr r0,[r5] + bic r0, r0, #0x1 + str r0,[r5] + + /* Step 5: Clear the DLL lock state change bit 8 in int_ack */ + ldr r0, [r5, #0xa8] + orr r0, r0, #0x1000000 + str r0, [r5, #0xa8] + + /* Step 6: Clear the interrupt mask for DLL lock state. + * Bit 8 in int_mask */ + ldr r0, [r5, #0xac] + bic r0, r0, #0x100 + str r0, [r5, #0xac] + + /* Change the freq now */ + /* If the freq req is below 24MHz, set DDR to synchronous mode. + * else set to async mode. */ + ldr r0, =24000000 + cmp r4, r0 + bgt Async_Mode + + /* Set the DDR to be Synchronous + mode. */ + /* Set the Databahn to sync mode. */ + ldr r0, [r5, #0xdc] + orr r0, r0, #0x30000 + str r0, [r5, #0xdc] + + /* Turn OFF the DDR_CKLGATE_MASK in MXC_CCM_DDR */ + ldr r0, [r6, #0x98] + bic r0, r0, #0xC0000000 + str r0, [r6, #0x98] + + /* Check if XTAL can source the DDR. */ + ldr r0, =24000000 + cmp r4, r0 + ble databahn_ddr_24 + + /*Source DDR from PLL1. Setup the dividers accordingly. */ + ldr r0, =800000000 + ldr r3, =1 +Loop1: + sub r0, r0, r4 + cmp r0, r4 + blt Div_Found + add r3, r3, #1 + bgt Loop1 + +Div_Found: + ldr r0, [r6, #0x94] + bic r0, r0, #0x3f + orr r0, r0, r3 + str r0, [r6, #0x94] + /* Set the DDR to sourced from PLL1 in sync path */ + ldr r0, [r6, #0x90] + orr r0, r0, #0x3 + str r0, [r6, #0x90] + + /* Turn OFF the DDR_CKLGATE_MASK in MXC_CCM_DDR */ + ldr r0, [r6, #0x98] + bic r0, r0, #0xC0000000 + str r0, [r6, #0x98] + + ldr r0, =24000000 + cmp r4, r0 + beq databahn_ddr_24 + + b Ddr_not_24 + +databahn_ddr_24: + ldr r0, =0x00000003 + str r0, [r5, #0x08] + ldr r0, =0x000012c0 + str r0, [r5, #0x0c] + + ldr r0, =0x00000018 + str r0, [r5, #0x10] + ldr r0, =0x000000f0 + str r0, [r5, #0x14] + ldr r0, =0x02010b0c + str r0, [r5, #0x18] + ldr r0, =0x02020102 + str r0, [r5, #0x1c] + + ldr r0, =0x05010102 + str r0, [r5, #0x20] + ldr r0, =0x01000103 + str r0, [r5, #0x28] + ldr r0, =0x04030101 + str r0, [r5, #0x2c] + + ldr r0, =0x00000202 + str r0, [r5, #0x34] + ldr r0, =0x00000001 + str r0, [r5, #0x38] + ldr r0, =0x00000401 + str r0, [r5, #0x3c] + + ldr r0, =0x00050056 + str r0, [r5, #0x40] + ldr r0, =0x00040004 + str r0, [r5, #0x48] + + ldr r0, =0x00040022 + str r0, [r5, #0x6c] + + ldr r0, =0x00040022 + str r0, [r5, #0x78] + + ldr r0, =0x00180000 + str r0, [r5, #0x80] + ldr r0, =0x00000009 + str r0, [r5, #0x84] + ldr r0, =0x02400003 + str r0, [r5, #0x88] + ldr r0, =0x01000200 + str r0, [r5, #0x8c] + + ldr r0, =0x00000000 + str r0, [r5, #0xcc] + + ldr r0, =0x01000201 + str r0, [r5, #0xd0] + ldr r0, =0x01010301 + str r0, [r5, #0xd4] + ldr r0, =0x00000101 + str r0, [r5, #0xd8] + + ldr r0, =0x02000602 + str r0, [r5, #0x104] + ldr r0, =0x00560000 + str r0, [r5, #0x108] + ldr r0, =0x00560056 + str r0, [r5, #0x10c] + + ldr r0, =0x00560056 + str r0, [r5, #0x110] + ldr r0, =0x03060056 + str r0, [r5, #0x114] + + /* Set the Databahn DLL in bypass mode */ + /* PHY Register settings. */ + ldr r0, =0x00000100 + str r0, [r5, #0x200] + ldr r0, =0x000f1100 + str r0, [r5, #0x204] + ldr r0, =0xf3003a27 + str r0, [r5, #0x208] + ldr r0, =0x074002c1 + str r0, [r5, #0x20c] + + ldr r0, =0xf3003a27 + str r0, [r5, #0x210] + ldr r0, =0x074002c1 + str r0, [r5, #0x214] + ldr r0, =0xf3003a27 + str r0, [r5, #0x218] + ldr r0, =0x074002c1 + str r0, [r5, #0x21c] + + ldr r0, =0xf3003a27 + str r0, [r5, #0x220] + ldr r0, =0x074002c1 + str r0, [r5, #0x224] + ldr r0, =0xf3003a27 + str r0, [r5, #0x228] + ldr r0, =0x074002c1 + str r0, [r5, #0x22c] + + ldr r0, =0x00810004 + str r0, [r5, #0x234] + ldr r0, =0x30219f14 + str r0, [r5, #0x238] + ldr r0, =0x00219f01 + str r0, [r5, #0x23c] + + ldr r0, =0x30219f14 + str r0, [r5, #0x240] + ldr r0, =0x00219f01 + str r0, [r5, #0x244] + ldr r0, =0x30219f14 + str r0, [r5, #0x248] + ldr r0, =0x00219f01 + str r0, [r5, #0x24c] + + ldr r0, =0x30219f14 + str r0, [r5, #0x250] + ldr r0, =0x00219f01 + str r0, [r5, #0x254] + ldr r0, =0x30219f14 + str r0, [r5, #0x258] + ldr r0, =0x00219f01 + str r0, [r5, #0x25c] + + b Setup_Done + +Async_Mode: + /* Set the Databahn to async mode. */ + ldr r0, [r5, #0xdc] + and r0, r0, #0xfffcffff + str r0, [r5, #0xdc] + + /*Source DDR from PLL1. Setup the dividers accordingly. */ + ldr r0, =800000000 + ldr r3, =1 +Loop2: + sub r0, r0, r4 + cmp r0, r4 + blt Div_Found1 + add r3, r3, #1 + bgt Loop2 + +Div_Found1: + ldr r0, [r6, #0x98] + bic r0, r0, #0x3f + orr r0, r0, r3 + str r0, [r6, #0x98] + + /* Set the DDR to sourced from PLL1 in async path */ + ldr r0, [r6, #0x98] + bic r0, r0, #0x40 + str r0, [r6, #0x98] + + /* Turn ON the DDR_CKLGATE_MASK in MXC_CCM_DDR */ + ldr r0, [r6, #0x98] + orr r0, r0, #0x40000000 + str r0, [r6, #0x98] + + ldr r0, =24000000 + cmp r4, r0 + beq databahn_ddr_24 + +Ddr_not_24: + ldr r0, =0x0000001b + str r0, [r5, #0x8] + ldr r0, =0x0000d056 + str r0, [r5, #0xc] + + ldr r0, =0x0000010b + str r0, [r5, #0x10] + ldr r0, =0x00000a6b + str r0, [r5, #0x14] + ldr r0, =0x02020d0c + str r0, [r5, #0x18] + ldr r0, =0x0c110302 + str r0, [r5, #0x1c] + + ldr r0, =0x05020503 + str r0, [r5, #0x20] + ldr r0, =0x01000403 + str r0, [r5, #0x28] + ldr r0, =0x09040501 + str r0, [r5, #0x2c] + + ldr r0, =0x00000e02 + str r0, [r5, #0x34] + ldr r0, =0x00000006 + str r0, [r5, #0x38] + ldr r0, =0x00002301 + str r0, [r5, #0x3c] + + ldr r0, =0x00050408 + str r0, [r5, #0x40] + ldr r0, =0x00260026 + str r0, [r5, #0x48] + + ldr r0, =0x00040042 + str r0, [r5, #0x6c] + + ldr r0, =0x00040042 + str r0, [r5, #0x78] + + ldr r0, =0x010b0000 + str r0, [r5, #0x80] + ldr r0, =0x00000060 + str r0, [r5, #0x84] + ldr r0, =0x02400018 + str r0, [r5, #0x88] + ldr r0, =0x01000e00 + str r0, [r5, #0x8c] + + ldr r0, =0x01000000 + str r0, [r5, #0xcc] + + ldr r0, =0x01000201 + str r0, [r5, #0xd0] + ldr r0, =0x00000200 + str r0, [r5, #0xd4] + ldr r0, =0x00000102 + str r0, [r5, #0xd8] + + ldr r0, =0x02000802 + str r0, [r5, #0x104] + ldr r0, =0x04080000 + str r0, [r5, #0x108] + ldr r0, =0x04080408 + str r0, [r5, #0x10c] + + ldr r0, =0x04080408 + str r0, [r5, #0x110] + ldr r0, =0x03060408 + str r0, [r5, #0x114] + + /* PHY setting for 266MHz */ + ldr r0, =0x00000000 + str r0, [r5, #0x200] + ldr r0, =0x00000000 + str r0, [r5, #0x204] + ldr r0, =0xf5003a27 + str r0, [r5, #0x208] + + ldr r0, =0xf5003a27 + str r0, [r5, #0x210] + ldr r0, =0xf5003a27 + str r0, [r5, #0x218] + + ldr r0, =0xf5003a27 + str r0, [r5, #0x220] + ldr r0, =0xf5003a27 + str r0, [r5, #0x228] + + ldr r0, =0x074002e1 + str r0, [r5, #0x20c] + ldr r0, =0x074002e1 + str r0, [r5, #0x214] + ldr r0, =0x074002e1 + str r0, [r5, #0x21c] + ldr r0, =0x074002e1 + str r0, [r5, #0x224] + ldr r0, =0x074002e1 + str r0, [r5, #0x22c] + + ldr r0, =0x00810006 + str r0, [r5, #0x234] + ldr r0, =0x20099414 + str r0, [r5, #0x238] + ldr r0, =0x000a1401 + str r0, [r5, #0x23c] + + ldr r0, =0x20099414 + str r0, [r5, #0x240] + ldr r0, =0x000a1401 + str r0, [r5, #0x244] + ldr r0, =0x20099414 + str r0, [r5, #0x248] + ldr r0, =0x000a1401 + str r0, [r5, #0x24c] + + ldr r0, =0x20099414 + str r0, [r5, #0x250] + ldr r0, =0x000a1401 + str r0, [r5, #0x254] + ldr r0, =0x20099414 + str r0, [r5, #0x258] + ldr r0, =0x000a1401 + str r0, [r5, #0x25c] + + b Setup_Done + + +Setup_Done: + /* Start controller */ + ldr r0,[r5] + orr r0, r0,#0x1 + str r0,[r5] + + /* Poll the DLL lock state change in int_status reg*/ + /* DLL is bypassed in the 24MHz mode, so no waiting for DLL to lock. */ + ldr r0, =24000000 + cmp r4, r0 + beq Exit_Self_Refresh +DllLock: + ldr r0, [r5, #0xa8] + and r0, r0, #0x100 + ldr r2, =0x100 + cmp r0, r2 + bne DllLock + + /*Leave self-refresh mode */ +Exit_Self_Refresh: + ldr r0,[r5, #0x4c] + and r0,r0,#0xfffffffe + str r0,[r5, #0x4c] + +LoopCKE1: + /*Wait for CKE = 1 */ + ldr r0,[r5, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + bne LoopCKE1 + + /* Put the databahn back to into the LPM mode. */ + str r1,[r5, #0x50] + + /* Restore registers */ + ldmfd sp!, {r3,r4,r5,r6} + mov pc, lr + + .type mx50_do_ddr_freq_change, #object +ENTRY(mx50_do_ddr_freq_change) + .word mx50_ddr_freq_change + .size mx50_ddr_freq_change, . - mx50_ddr_freq_change diff --git a/arch/arm/mach-mx5/mx50_rdp.c b/arch/arm/mach-mx5/mx50_rdp.c new file mode 100644 index 000000000000..4a99419b265d --- /dev/null +++ b/arch/arm/mach-mx5/mx50_rdp.c @@ -0,0 +1,1186 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "devices.h" +#include "usb.h" +#include "crm_regs.h" + +#define SD1_WP (3*32 + 19) /*GPIO_4_19 */ +#define SD1_CD (0*32 + 27) /*GPIO_1_27 */ +#define SD2_WP (4*32 + 16) /*GPIO_5_16 */ +#define SD2_CD (4*32 + 17) /*GPIO_5_17 */ +#define HP_DETECT (3*32 + 15) /*GPIO_4_15 */ +#define PWR_INT (3*32 + 18) /*GPIO_4_18 */ + +#define EPDC_D0 (2*32 + 1) /*GPIO_3_0 */ +#define EPDC_D1 (2*32 + 2) /*GPIO_3_1 */ +#define EPDC_D2 (2*32 + 3) /*GPIO_3_2 */ +#define EPDC_D3 (2*32 + 4) /*GPIO_3_3 */ +#define EPDC_D4 (2*32 + 5) /*GPIO_3_4 */ +#define EPDC_D5 (2*32 + 6) /*GPIO_3_5 */ +#define EPDC_D6 (2*32 + 7) /*GPIO_3_6 */ +#define EPDC_D7 (2*32 + 8) /*GPIO_3_7 */ +#define EPDC_GDCLK (2*32 + 16) /*GPIO_3_16 */ +#define EPDC_GDSP (2*32 + 17) /*GPIO_3_17 */ +#define EPDC_GDOE (2*32 + 18) /*GPIO_3_18 */ +#define EPDC_GDRL (2*32 + 19) /*GPIO_3_19 */ +#define EPDC_SDCLK (2*32 + 20) /*GPIO_3_20 */ +#define EPDC_SDOE (2*32 + 23) /*GPIO_3_23 */ +#define EPDC_SDLE (2*32 + 24) /*GPIO_3_24 */ +#define EPDC_SDSHR (2*32 + 26) /*GPIO_3_26 */ +#define EPDC_BDR0 (3*32 + 23) /*GPIO_4_23 */ +#define EPDC_SDCE0 (3*32 + 25) /*GPIO_4_25 */ +#define EPDC_SDCE1 (3*32 + 26) /*GPIO_4_26 */ +#define EPDC_SDCE2 (3*32 + 27) /*GPIO_4_27 */ + +#define EPDC_PMIC_WAKE (5*32 + 16) /*GPIO_6_16 */ +#define EPDC_PMIC_INT (5*32 + 17) /*GPIO_6_17 */ +#define EPDC_VCOM (3*32 + 21) /*GPIO_4_21 */ +#define EPDC_PWRSTAT (2*32 + 28) /*GPIO_3_28 */ +#define EPDC_ELCDIF_BACKLIGHT (1*32 + 18) /*GPIO_2_18 */ +#define CSPI_CS1 (3*32 + 13) /*GPIO_4_13 */ +#define CSPI_CS2 (3*32 + 11) /*GPIO_4_11*/ +#define SGTL_OSCEN (5*32 + 8) /*GPIO_6_8*/ +#define FEC_EN (5*32 + 23) /*GPIO_6_23*/ +#define FEC_RESET_B (3*32 + 12) /*GPIO_4_12*/ + +extern int __init mx50_rdp_init_mc13892(void); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); +static int num_cpu_wp = 2; + +static struct pad_desc mx50_rdp[] = { + /* SD1 */ + MX50_PAD_ECSPI2_SS0__GPIO_4_19, + MX50_PAD_EIM_CRE__GPIO_1_27, + MX50_PAD_SD1_CMD__SD1_CMD, + + MX50_PAD_SD1_CLK__SD1_CLK, + MX50_PAD_SD1_D0__SD1_D0, + MX50_PAD_SD1_D1__SD1_D1, + MX50_PAD_SD1_D2__SD1_D2, + MX50_PAD_SD1_D3__SD1_D3, + + /* SD2 */ + MX50_PAD_SD2_CD__GPIO_5_17, + MX50_PAD_SD2_WP__GPIO_5_16, + MX50_PAD_SD2_CMD__SD2_CMD, + MX50_PAD_SD2_CLK__SD2_CLK, + MX50_PAD_SD2_D0__SD2_D0, + MX50_PAD_SD2_D1__SD2_D1, + MX50_PAD_SD2_D2__SD2_D2, + MX50_PAD_SD2_D3__SD2_D3, + MX50_PAD_SD2_D4__SD2_D4, + MX50_PAD_SD2_D5__SD2_D5, + MX50_PAD_SD2_D6__SD2_D6, + MX50_PAD_SD2_D7__SD2_D7, + + /* SD3 */ + MX50_PAD_SD3_CMD__SD3_CMD, + MX50_PAD_SD3_CLK__SD3_CLK, + MX50_PAD_SD3_D0__SD3_D0, + MX50_PAD_SD3_D1__SD3_D1, + MX50_PAD_SD3_D2__SD3_D2, + MX50_PAD_SD3_D3__SD3_D3, + MX50_PAD_SD3_D4__SD3_D4, + MX50_PAD_SD3_D5__SD3_D5, + MX50_PAD_SD3_D6__SD3_D6, + MX50_PAD_SD3_D7__SD3_D7, + + MX50_PAD_SSI_RXD__SSI_RXD, + MX50_PAD_SSI_TXD__SSI_TXD, + MX50_PAD_SSI_TXC__SSI_TXC, + MX50_PAD_SSI_TXFS__SSI_TXFS, + + /* HP_DET_B (headphone detect) */ + MX50_PAD_ECSPI1_SS0__GPIO_4_15, + + /* PWR_INT */ + MX50_PAD_ECSPI2_MISO__GPIO_4_18, + + /* UART pad setting */ + MX50_PAD_UART1_TXD__UART1_TXD, + MX50_PAD_UART1_RXD__UART1_RXD, + MX50_PAD_UART1_RTS__UART1_RTS, + MX50_PAD_UART2_TXD__UART2_TXD, + MX50_PAD_UART2_RXD__UART2_RXD, + MX50_PAD_UART2_CTS__UART2_CTS, + MX50_PAD_UART2_RTS__UART2_RTS, + + MX50_PAD_I2C1_SCL__I2C1_SCL, + MX50_PAD_I2C1_SDA__I2C1_SDA, + MX50_PAD_I2C2_SCL__I2C2_SCL, + MX50_PAD_I2C2_SDA__I2C2_SDA, + + /* EPDC pins */ + MX50_PAD_EPDC_D0__EPDC_D0, + MX50_PAD_EPDC_D1__EPDC_D1, + MX50_PAD_EPDC_D2__EPDC_D2, + MX50_PAD_EPDC_D3__EPDC_D3, + MX50_PAD_EPDC_D4__EPDC_D4, + MX50_PAD_EPDC_D5__EPDC_D5, + MX50_PAD_EPDC_D6__EPDC_D6, + MX50_PAD_EPDC_D7__EPDC_D7, + MX50_PAD_EPDC_GDCLK__EPDC_GDCLK, + MX50_PAD_EPDC_GDSP__EPDC_GDSP, + MX50_PAD_EPDC_GDOE__EPDC_GDOE , + MX50_PAD_EPDC_GDRL__EPDC_GDRL, + MX50_PAD_EPDC_SDCLK__EPDC_SDCLK, + MX50_PAD_EPDC_SDOE__EPDC_SDOE, + MX50_PAD_EPDC_SDLE__EPDC_SDLE, + MX50_PAD_EPDC_SDSHR__EPDC_SDSHR, + MX50_PAD_EPDC_BDR0__EPDC_BDR0, + MX50_PAD_EPDC_SDCE0__EPDC_SDCE0, + MX50_PAD_EPDC_SDCE1__EPDC_SDCE1, + MX50_PAD_EPDC_SDCE2__EPDC_SDCE2, + + MX50_PAD_EPDC_PWRSTAT__GPIO_3_28, + MX50_PAD_EPDC_VCOM0__GPIO_4_21, + + MX50_PAD_DISP_D8__DISP_D8, + MX50_PAD_DISP_D9__DISP_D9, + MX50_PAD_DISP_D10__DISP_D10, + MX50_PAD_DISP_D11__DISP_D11, + MX50_PAD_DISP_D12__DISP_D12, + MX50_PAD_DISP_D13__DISP_D13, + MX50_PAD_DISP_D14__DISP_D14, + MX50_PAD_DISP_D15__DISP_D15, + MX50_PAD_DISP_RS__ELCDIF_VSYNC, + + /* ELCDIF contrast */ + MX50_PAD_DISP_BUSY__GPIO_2_18, + + MX50_PAD_DISP_CS__ELCDIF_HSYNC, + MX50_PAD_DISP_RD__ELCDIF_EN, + MX50_PAD_DISP_WR__ELCDIF_PIXCLK, + + /* EPD PMIC WAKEUP */ + MX50_PAD_UART4_TXD__GPIO_6_16, + + /* EPD PMIC intr */ + MX50_PAD_UART4_RXD__GPIO_6_17, + + MX50_PAD_EPITO__USBH1_PWR, + /* Need to comment below line if + * one needs to debug owire. + */ + MX50_PAD_OWIRE__USBH1_OC, + MX50_PAD_PWM2__USBOTG_PWR, + MX50_PAD_I2C3_SCL__USBOTG_OC, + + MX50_PAD_SSI_RXC__FEC_MDIO, + MX50_PAD_SSI_RXC__FEC_MDIO, + MX50_PAD_DISP_D0__FEC_TXCLK, + MX50_PAD_DISP_D1__FEC_RX_ER, + MX50_PAD_DISP_D2__FEC_RX_DV, + MX50_PAD_DISP_D3__FEC_RXD1, + MX50_PAD_DISP_D4__FEC_RXD0, + MX50_PAD_DISP_D5__FEC_TX_EN, + MX50_PAD_DISP_D6__FEC_TXD1, + MX50_PAD_DISP_D7__FEC_TXD0, + MX50_PAD_SSI_RXFS__FEC_MDC, + MX50_PAD_I2C3_SDA__GPIO_6_23, + MX50_PAD_ECSPI1_SCLK__GPIO_4_12, + + MX50_PAD_CSPI_SS0__CSPI_SS0, + MX50_PAD_ECSPI1_MOSI__CSPI_SS1, + MX50_PAD_CSPI_MOSI__CSPI_MOSI, + MX50_PAD_CSPI_MISO__CSPI_MISO, + + /* SGTL500_OSC_EN */ + MX50_PAD_UART1_CTS__GPIO_6_8, + + /* Keypad */ + MX50_PAD_KEY_COL0__KEY_COL0, + MX50_PAD_KEY_ROW0__KEY_ROW0, + MX50_PAD_KEY_COL1__KEY_COL1, + MX50_PAD_KEY_ROW1__KEY_ROW1, + MX50_PAD_KEY_COL2__KEY_COL2, + MX50_PAD_KEY_ROW2__KEY_ROW2, + +}; + +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, + .num_wp = 2, +}; + +/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1050000,}, + { + .pll_rate = 800000000, + .cpu_rate = 160000000, + .pdf = 4, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 4, + .cpu_voltage = 850000,}, +}; + +static struct cpu_wp *mx50_rdp_get_cpu_wp(int *wp) +{ + *wp = num_cpu_wp; + return cpu_wp_auto; +} + +static void mx50_rdp_set_num_cpu_wp(int num) +{ + num_cpu_wp = num; + return; +} + +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 1, +}; + +static struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, + .phy_mask = ~1UL, +}; + +static u16 keymapping[8] = { + KEY_F1, KEY_UP, KEY_SELECT, KEY_LEFT, + KEY_ENTER, KEY_RIGHT, KEY_MENU, KEY_DOWN, +}; + +static struct keypad_data keypad_plat_data = { + .rowmax = 3, + .colmax = 3, + .irq = MXC_INT_KPP, + .learning = 0, + .delay = 2, + .matrix = keymapping, +}; + + +/* workaround for cspi chipselect pin may not keep correct level when idle */ +static void mx50_rdp_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + break; + case 2: + break; + case 3: + switch (chipselect) { + case 0x1: + { + struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__CSPI_SS0; + struct pad_desc cspi_cs1 = + MX50_PAD_ECSPI1_MOSI__GPIO_4_13; + + /* pull up/down deassert it */ + mxc_iomux_v3_setup_pad(&cspi_ss0); + mxc_iomux_v3_setup_pad(&cspi_cs1); + + gpio_request(CSPI_CS1, "cspi-cs1"); + gpio_direction_input(CSPI_CS1); + } + break; + case 0x2: + { + struct pad_desc cspi_ss1 = + MX50_PAD_ECSPI1_MOSI__CSPI_SS1; + struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__GPIO_4_11; + + /*disable other ss */ + mxc_iomux_v3_setup_pad(&cspi_ss1); + mxc_iomux_v3_setup_pad(&cspi_ss0); + + /* pull up/down deassert it */ + gpio_request(CSPI_CS2, "cspi-cs2"); + gpio_direction_input(CSPI_CS2); + } + break; + default: + break; + } + break; + + default: + break; + } +} + +static void mx50_arm2_usb_set_vbus(bool enable) +{ + printk(KERN_DEBUG "%s, enable is %d\n", __func__, enable); + if (enable) + USBCTRL |= UCTRL_O_PWR_POL; + else + USBCTRL &= ~UCTRL_O_PWR_POL; +} + +static void mx50_rdp_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + break; + case 2: + break; + case 3: + switch (chipselect) { + case 0x1: + gpio_free(CSPI_CS1); + break; + case 0x2: + gpio_free(CSPI_CS2); + break; + default: + break; + } + break; + default: + break; + } + +} + +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, + .chipselect_active = mx50_rdp_gpio_spi_chipselect_active, + .chipselect_inactive = mx50_rdp_gpio_spi_chipselect_inactive, +}; + +static struct mxc_spi_master mxcspi3_data = { + .maxchipselect = 4, + .spi_version = 7, + .chipselect_active = mx50_rdp_gpio_spi_chipselect_active, + .chipselect_inactive = mx50_rdp_gpio_spi_chipselect_inactive, +}; + +static struct mxc_i2c_platform_data mxci2c_data = { + .i2c_clk = 100000, +}; + +static struct mxc_srtc_platform_data srtc_data = { + .srtc_sec_mode_addr = OCOTP_CTRL_BASE_ADDR + 0x80, +}; + +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +static struct regulator_init_data max17135_init_data[] __initdata = { + { + .constraints = { + .name = "DISPLAY", + }, + }, { + .constraints = { + .name = "GVDD", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "GVEE", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINN", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINP", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "VCOM", + .min_uV = mV_to_uV(-4325), + .max_uV = mV_to_uV(-500), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + }, { + .constraints = { + .name = "VNEG", + .min_uV = V_to_uV(-15), + .max_uV = V_to_uV(-15), + }, + }, { + .constraints = { + .name = "VPOS", + .min_uV = V_to_uV(15), + .max_uV = V_to_uV(15), + }, + }, +}; + +static void epdc_get_pins(void) +{ + /* Claim GPIOs for EPDC pins - used during power up/down */ + gpio_request(EPDC_D0, "epdc_d0"); + gpio_request(EPDC_D1, "epdc_d1"); + gpio_request(EPDC_D2, "epdc_d2"); + gpio_request(EPDC_D3, "epdc_d3"); + gpio_request(EPDC_D4, "epdc_d4"); + gpio_request(EPDC_D5, "epdc_d5"); + gpio_request(EPDC_D6, "epdc_d6"); + gpio_request(EPDC_D7, "epdc_d7"); + gpio_request(EPDC_GDCLK, "epdc_gdclk"); + gpio_request(EPDC_GDSP, "epdc_gdsp"); + gpio_request(EPDC_GDOE, "epdc_gdoe"); + gpio_request(EPDC_GDRL, "epdc_gdrl"); + gpio_request(EPDC_SDCLK, "epdc_sdclk"); + gpio_request(EPDC_SDOE, "epdc_sdoe"); + gpio_request(EPDC_SDLE, "epdc_sdle"); + gpio_request(EPDC_SDSHR, "epdc_sdshr"); + gpio_request(EPDC_BDR0, "epdc_bdr0"); + gpio_request(EPDC_SDCE0, "epdc_sdce0"); + gpio_request(EPDC_SDCE1, "epdc_sdce1"); + gpio_request(EPDC_SDCE2, "epdc_sdce2"); +} + +static void epdc_put_pins(void) +{ + gpio_free(EPDC_D0); + gpio_free(EPDC_D1); + gpio_free(EPDC_D2); + gpio_free(EPDC_D3); + gpio_free(EPDC_D4); + gpio_free(EPDC_D5); + gpio_free(EPDC_D6); + gpio_free(EPDC_D7); + gpio_free(EPDC_GDCLK); + gpio_free(EPDC_GDSP); + gpio_free(EPDC_GDOE); + gpio_free(EPDC_GDRL); + gpio_free(EPDC_SDCLK); + gpio_free(EPDC_SDOE); + gpio_free(EPDC_SDLE); + gpio_free(EPDC_SDSHR); + gpio_free(EPDC_BDR0); + gpio_free(EPDC_SDCE0); + gpio_free(EPDC_SDCE1); + gpio_free(EPDC_SDCE2); +} + +static void epdc_enable_pins(void) +{ + struct pad_desc epdc_d0 = MX50_PAD_EPDC_D0__EPDC_D0; + struct pad_desc epdc_d1 = MX50_PAD_EPDC_D1__EPDC_D1; + struct pad_desc epdc_d2 = MX50_PAD_EPDC_D2__EPDC_D2; + struct pad_desc epdc_d3 = MX50_PAD_EPDC_D3__EPDC_D3; + struct pad_desc epdc_d4 = MX50_PAD_EPDC_D4__EPDC_D4; + struct pad_desc epdc_d5 = MX50_PAD_EPDC_D5__EPDC_D5; + struct pad_desc epdc_d6 = MX50_PAD_EPDC_D6__EPDC_D6; + struct pad_desc epdc_d7 = MX50_PAD_EPDC_D7__EPDC_D7; + struct pad_desc epdc_gdclk = MX50_PAD_EPDC_GDCLK__EPDC_GDCLK; + struct pad_desc epdc_gdsp = MX50_PAD_EPDC_GDSP__EPDC_GDSP; + struct pad_desc epdc_gdoe = MX50_PAD_EPDC_GDOE__EPDC_GDOE; + struct pad_desc epdc_gdrl = MX50_PAD_EPDC_GDRL__EPDC_GDRL; + struct pad_desc epdc_sdclk = MX50_PAD_EPDC_SDCLK__EPDC_SDCLK; + struct pad_desc epdc_sdoe = MX50_PAD_EPDC_SDOE__EPDC_SDOE; + struct pad_desc epdc_sdle = MX50_PAD_EPDC_SDLE__EPDC_SDLE; + struct pad_desc epdc_sdshr = MX50_PAD_EPDC_SDSHR__EPDC_SDSHR; + struct pad_desc epdc_bdr0 = MX50_PAD_EPDC_BDR0__EPDC_BDR0; + struct pad_desc epdc_sdce0 = MX50_PAD_EPDC_SDCE0__EPDC_SDCE0; + struct pad_desc epdc_sdce1 = MX50_PAD_EPDC_SDCE1__EPDC_SDCE1; + struct pad_desc epdc_sdce2 = MX50_PAD_EPDC_SDCE2__EPDC_SDCE2; + + /* Configure MUX settings to enable EPDC use */ + mxc_iomux_v3_setup_pad(&epdc_d0); + mxc_iomux_v3_setup_pad(&epdc_d1); + mxc_iomux_v3_setup_pad(&epdc_d2); + mxc_iomux_v3_setup_pad(&epdc_d3); + mxc_iomux_v3_setup_pad(&epdc_d4); + mxc_iomux_v3_setup_pad(&epdc_d5); + mxc_iomux_v3_setup_pad(&epdc_d6); + mxc_iomux_v3_setup_pad(&epdc_d7); + mxc_iomux_v3_setup_pad(&epdc_gdclk); + mxc_iomux_v3_setup_pad(&epdc_gdsp); + mxc_iomux_v3_setup_pad(&epdc_gdoe); + mxc_iomux_v3_setup_pad(&epdc_gdrl); + mxc_iomux_v3_setup_pad(&epdc_sdclk); + mxc_iomux_v3_setup_pad(&epdc_sdoe); + mxc_iomux_v3_setup_pad(&epdc_sdle); + mxc_iomux_v3_setup_pad(&epdc_sdshr); + mxc_iomux_v3_setup_pad(&epdc_bdr0); + mxc_iomux_v3_setup_pad(&epdc_sdce0); + mxc_iomux_v3_setup_pad(&epdc_sdce1); + mxc_iomux_v3_setup_pad(&epdc_sdce2); + + gpio_direction_input(EPDC_D0); + gpio_direction_input(EPDC_D1); + gpio_direction_input(EPDC_D2); + gpio_direction_input(EPDC_D3); + gpio_direction_input(EPDC_D4); + gpio_direction_input(EPDC_D5); + gpio_direction_input(EPDC_D6); + gpio_direction_input(EPDC_D7); + gpio_direction_input(EPDC_GDCLK); + gpio_direction_input(EPDC_GDSP); + gpio_direction_input(EPDC_GDOE); + gpio_direction_input(EPDC_GDRL); + gpio_direction_input(EPDC_SDCLK); + gpio_direction_input(EPDC_SDOE); + gpio_direction_input(EPDC_SDLE); + gpio_direction_input(EPDC_SDSHR); + gpio_direction_input(EPDC_BDR0); + gpio_direction_input(EPDC_SDCE0); + gpio_direction_input(EPDC_SDCE1); + gpio_direction_input(EPDC_SDCE2); +} + +static void epdc_disable_pins(void) +{ + struct pad_desc epdc_d0 = MX50_PAD_EPDC_D0__GPIO_3_0; + struct pad_desc epdc_d1 = MX50_PAD_EPDC_D1__GPIO_3_1; + struct pad_desc epdc_d2 = MX50_PAD_EPDC_D2__GPIO_3_2; + struct pad_desc epdc_d3 = MX50_PAD_EPDC_D3__GPIO_3_3; + struct pad_desc epdc_d4 = MX50_PAD_EPDC_D4__GPIO_3_4; + struct pad_desc epdc_d5 = MX50_PAD_EPDC_D5__GPIO_3_5; + struct pad_desc epdc_d6 = MX50_PAD_EPDC_D6__GPIO_3_6; + struct pad_desc epdc_d7 = MX50_PAD_EPDC_D7__GPIO_3_7; + struct pad_desc epdc_gdclk = MX50_PAD_EPDC_GDCLK__GPIO_3_16; + struct pad_desc epdc_gdsp = MX50_PAD_EPDC_GDSP__GPIO_3_17; + struct pad_desc epdc_gdoe = MX50_PAD_EPDC_GDOE__GPIO_3_18; + struct pad_desc epdc_gdrl = MX50_PAD_EPDC_GDRL__GPIO_3_19; + struct pad_desc epdc_sdclk = MX50_PAD_EPDC_SDCLK__GPIO_3_20; + struct pad_desc epdc_sdoe = MX50_PAD_EPDC_SDOE__GPIO_3_23; + struct pad_desc epdc_sdle = MX50_PAD_EPDC_SDLE__GPIO_3_24; + struct pad_desc epdc_sdshr = MX50_PAD_EPDC_SDSHR__GPIO_3_26; + struct pad_desc epdc_bdr0 = MX50_PAD_EPDC_BDR0__GPIO_4_23; + struct pad_desc epdc_sdce0 = MX50_PAD_EPDC_SDCE0__GPIO_4_25; + struct pad_desc epdc_sdce1 = MX50_PAD_EPDC_SDCE1__GPIO_4_26; + struct pad_desc epdc_sdce2 = MX50_PAD_EPDC_SDCE2__GPIO_4_27; + + /* Configure MUX settings for EPDC pins to + * GPIO and drive to 0. */ + mxc_iomux_v3_setup_pad(&epdc_d0); + mxc_iomux_v3_setup_pad(&epdc_d1); + mxc_iomux_v3_setup_pad(&epdc_d2); + mxc_iomux_v3_setup_pad(&epdc_d3); + mxc_iomux_v3_setup_pad(&epdc_d4); + mxc_iomux_v3_setup_pad(&epdc_d5); + mxc_iomux_v3_setup_pad(&epdc_d6); + mxc_iomux_v3_setup_pad(&epdc_d7); + mxc_iomux_v3_setup_pad(&epdc_gdclk); + mxc_iomux_v3_setup_pad(&epdc_gdsp); + mxc_iomux_v3_setup_pad(&epdc_gdoe); + mxc_iomux_v3_setup_pad(&epdc_gdrl); + mxc_iomux_v3_setup_pad(&epdc_sdclk); + mxc_iomux_v3_setup_pad(&epdc_sdoe); + mxc_iomux_v3_setup_pad(&epdc_sdle); + mxc_iomux_v3_setup_pad(&epdc_sdshr); + mxc_iomux_v3_setup_pad(&epdc_bdr0); + mxc_iomux_v3_setup_pad(&epdc_sdce0); + mxc_iomux_v3_setup_pad(&epdc_sdce1); + mxc_iomux_v3_setup_pad(&epdc_sdce2); + + gpio_direction_output(EPDC_D0, 0); + gpio_direction_output(EPDC_D1, 0); + gpio_direction_output(EPDC_D2, 0); + gpio_direction_output(EPDC_D3, 0); + gpio_direction_output(EPDC_D4, 0); + gpio_direction_output(EPDC_D5, 0); + gpio_direction_output(EPDC_D6, 0); + gpio_direction_output(EPDC_D7, 0); + gpio_direction_output(EPDC_GDCLK, 0); + gpio_direction_output(EPDC_GDSP, 0); + gpio_direction_output(EPDC_GDOE, 0); + gpio_direction_output(EPDC_GDRL, 0); + gpio_direction_output(EPDC_SDCLK, 0); + gpio_direction_output(EPDC_SDOE, 0); + gpio_direction_output(EPDC_SDLE, 0); + gpio_direction_output(EPDC_SDSHR, 0); + gpio_direction_output(EPDC_BDR0, 0); + gpio_direction_output(EPDC_SDCE0, 0); + gpio_direction_output(EPDC_SDCE1, 0); + gpio_direction_output(EPDC_SDCE2, 0); +} + +static struct fb_videomode e60_mode = { + .name = "E60", + .refresh = 50, + .xres = 800, + .yres = 600, + .pixclock = 20000000, + .left_margin = 10, + .right_margin = 217, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct fb_videomode e97_mode = { + .name = "E97", + .refresh = 50, + .xres = 1200, + .yres = 825, + .pixclock = 32000000, + .left_margin = 8, + .right_margin = 125, + .upper_margin = 4, + .lower_margin = 17, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct mxc_epdc_fb_mode panel_modes[] = { + { + &e60_mode, + 4, 10, 20, 10, 20, 480, 20, 0, 1, 1, + }, + { + &e97_mode, + 8, 10, 20, 10, 20, 580, 20, 0, 1, 3, + }, +}; + +static struct mxc_epdc_fb_platform_data epdc_data = { + .epdc_mode = panel_modes, + .num_modes = ARRAY_SIZE(panel_modes), + .get_pins = epdc_get_pins, + .put_pins = epdc_put_pins, + .enable_pins = epdc_enable_pins, + .disable_pins = epdc_disable_pins, +}; + +static struct max17135_platform_data max17135_pdata __initdata = { + .vneg_pwrup = 1, + .gvee_pwrup = 1, + .vpos_pwrup = 2, + .gvdd_pwrup = 1, + .gvdd_pwrdn = 1, + .vpos_pwrdn = 2, + .gvee_pwrdn = 1, + .vneg_pwrdn = 1, + .gpio_pmic_pwrgood = EPDC_PWRSTAT, + .gpio_pmic_vcom_ctrl = EPDC_VCOM, + .gpio_pmic_wakeup = EPDC_PMIC_WAKE, + .gpio_pmic_intr = EPDC_PMIC_INT, + .regulator_init = max17135_init_data, + .pass_num = 1, + .vcom_uV = -1250000, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + I2C_BOARD_INFO("max17135", 0x48), + .platform_data = &max17135_pdata, + }, + { + .type = "accelerometer", + .addr = 0x1c, + }, + { + .type = "eeprom", + .addr = 0x50, + }, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, +}; + +static struct mtd_partition mxc_dataflash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x000100000,}, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL,}, +}; + +static struct flash_platform_data mxc_spi_flash_data[] = { + { + .name = "mxc_dataflash", + .parts = mxc_dataflash_partitions, + .nr_parts = ARRAY_SIZE(mxc_dataflash_partitions), + .type = "at45db321d",} +}; + + +static struct spi_board_info mxc_dataflash_device[] __initdata = { + { + .modalias = "mxc_dataflash", + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 3, + .chip_select = 1, + .platform_data = &mxc_spi_flash_data[0],}, +}; + +static int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + if (to_platform_device(dev)->id == 0) + rc = gpio_get_value(SD1_WP); + else if (to_platform_device(dev)->id == 1) + rc = gpio_get_value(SD2_WP); + else if (to_platform_device(dev)->id == 2) + rc = 0; + + return rc; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret = 0; + if (to_platform_device(dev)->id == 0) + ret = gpio_get_value(SD1_CD); + else if (to_platform_device(dev)->id == 1) + ret = gpio_get_value(SD2_CD); + else if (to_platform_device(dev)->id == 2) + ret = 1; + + return ret; +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc2_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static struct mxc_mmc_platform_data mmc3_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static int mxc_sgtl5000_amp_enable(int enable) +{ +/* TO DO */ + return 0; +} + +static int headphone_det_status(void) +{ + return (gpio_get_value(HP_DETECT) != 0); +} + +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .hp_irq = IOMUX_TO_IRQ_V3(HP_DETECT), + .hp_status = headphone_det_status, + .amp_enable = mxc_sgtl5000_amp_enable, + .sysclk = 12288000, +}; + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", +}; + +static struct pad_desc rdp_wvga_pads[] = { + MX50_PAD_DISP_D0__DISP_D0, + MX50_PAD_DISP_D1__DISP_D1, + MX50_PAD_DISP_D2__DISP_D2, + MX50_PAD_DISP_D3__DISP_D3, + MX50_PAD_DISP_D4__DISP_D4, + MX50_PAD_DISP_D5__DISP_D5, + MX50_PAD_DISP_D6__DISP_D6, + MX50_PAD_DISP_D7__DISP_D7, +}; + +static void wvga_reset(void) +{ + mxc_iomux_v3_setup_multiple_pads(rdp_wvga_pads, \ + ARRAY_SIZE(rdp_wvga_pads)); + return; +} + +static struct mxc_lcd_platform_data lcd_wvga_data = { + .reset = wvga_reset, +}; + +static struct platform_device lcd_wvga_device = { + .name = "lcd_claa", + .dev = { + .platform_data = &lcd_wvga_data, + }, +}; + +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = V4L2_PIX_FMT_RGB565, + .mode_str = "CLAA-WVGA", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, +}; + +static int __initdata enable_w1 = { 0 }; +static int __init w1_setup(char *__unused) +{ + enable_w1 = 1; + return cpu_is_mx50(); +} + +__setup("w1", w1_setup); + +static struct android_pmem_platform_data android_pmem_pdata = { + .name = "pmem_adsp", + .start = 0, + .size = SZ_4M, + .no_allocator = 0, + .cached = PMEM_NONCACHE_NORMAL, +}; + +static struct android_pmem_platform_data android_pmem_gpu_pdata = { + .name = "pmem_gpu", + .start = 0, + .size = SZ_32M, + .no_allocator = 0, + .cached = PMEM_CACHE_ENABLE, +}; + +static struct android_usb_platform_data android_usb_pdata = { + .vendor_id = 0x0bb4, + .product_id = 0x0c01, + .adb_product_id = 0x0c02, + .version = 0x0100, + .product_name = "Android Phone", + .manufacturer_name = "Freescale", + .nluns = 3, +}; + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + struct tag *t; + int size; + + mxc_set_cpu_type(MXC_CPU_MX50); + + get_cpu_wp = mx50_rdp_get_cpu_wp; + set_num_cpu_wp = mx50_rdp_set_num_cpu_wp; + + for_each_tag(t, tags) { + if (t->hdr.tag != ATAG_MEM) + continue; + size = t->u.mem.size; + + android_pmem_pdata.start = + PHYS_OFFSET + size - android_pmem_pdata.size; + android_pmem_gpu_pdata.start = + android_pmem_pdata.start - android_pmem_gpu_pdata.size; +#if 0 + gpu_device.resource[5].start = + android_pmem_gpu_pdata.start - SZ_16M; + gpu_device.resource[5].end = + gpu_device.resource[5].start + SZ_16M - 1; +#endif + size -= android_pmem_pdata.size; + size -= android_pmem_gpu_pdata.size; + //size -= SZ_16M; + t->u.mem.size = size; + } +} + +static void __init mx50_rdp_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx50_rdp, \ + ARRAY_SIZE(mx50_rdp)); + + gpio_request(SD1_WP, "sdhc1-wp"); + gpio_direction_input(SD1_WP); + + gpio_request(SD1_CD, "sdhc1-cd"); + gpio_direction_input(SD1_CD); + + gpio_request(SD2_WP, "sdhc2-wp"); + gpio_direction_input(SD2_WP); + + gpio_request(SD2_CD, "sdhc2-cd"); + gpio_direction_input(SD2_CD); + + gpio_request(HP_DETECT, "hp-det"); + gpio_direction_input(HP_DETECT); + + gpio_request(PWR_INT, "pwr-int"); + gpio_direction_input(PWR_INT); + + gpio_request(EPDC_PMIC_WAKE, "epdc-pmic-wake"); + gpio_direction_output(EPDC_PMIC_WAKE, 0); + + gpio_request(EPDC_VCOM, "epdc-vcom"); + gpio_direction_output(EPDC_VCOM, 0); + + gpio_request(EPDC_PMIC_INT, "epdc-pmic-int"); + gpio_direction_input(EPDC_PMIC_INT); + + gpio_request(EPDC_PWRSTAT, "epdc-pwrstat"); + gpio_direction_input(EPDC_PWRSTAT); + + /* ELCDIF backlight */ + gpio_request(EPDC_ELCDIF_BACKLIGHT, "elcdif-backlight"); + gpio_direction_output(EPDC_ELCDIF_BACKLIGHT, 1); + + if (enable_w1) { + struct pad_desc one_wire = MX50_PAD_OWIRE__OWIRE; + mxc_iomux_v3_setup_pad(&one_wire); + } + + /* SGTL5000_OSC_EN */ + gpio_request(SGTL_OSCEN, "sgtl5000-osc-en"); + gpio_direction_output(SGTL_OSCEN, 1); + + gpio_request(FEC_EN, "fec-en"); + gpio_direction_output(FEC_EN, 0); + + gpio_request(FEC_RESET_B, "fec-reset_b"); + gpio_direction_output(FEC_RESET_B, 0); + udelay(500); + gpio_set_value(FEC_RESET_B, 1); + +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + /* SD card detect irqs */ + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(SD1_CD); + mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(SD2_CD); + mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(SD2_CD); + + mxc_cpu_common_init(); + mxc_register_gpios(); + mx50_rdp_io_init(); + + mxc_register_device(&mxc_dma_device, NULL); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxcspi1_device, &mxcspi1_data); + mxc_register_device(&mxcspi3_device, &mxcspi3_data); + mxc_register_device(&mxci2c_devices[0], &mxci2c_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c_data); + mxc_register_device(&mxci2c_devices[2], &mxci2c_data); + + mxc_register_device(&mxc_rtc_device, &srtc_data); + mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); + mxc_register_device(&gpu_device, NULL); + mxc_register_device(&mxc_pxp_device, NULL); + mxc_register_device(&mxc_pxp_client_device, NULL); + mxc_register_device(&mxc_pxp_v4l2, NULL); + mxc_register_device(&busfreq_device, NULL); + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + + /* + mxc_register_device(&mx53_lpmode_device, NULL); + mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); + */ + /* + mxc_register_device(&mxc_keypad_device, &keypad_plat_data); + */ + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc2_device, &mmc2_data); + mxc_register_device(&mxcsdhc3_device, &mmc3_data); + mxc_register_device(&mxc_ssi1_device, NULL); + mxc_register_device(&mxc_ssi2_device, NULL); + mxc_register_device(&mxc_fec_device, &fec_data); + spi_register_board_info(mxc_dataflash_device, + ARRAY_SIZE(mxc_dataflash_device)); + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + + mxc_register_device(&epdc_device, &epdc_data); + mxc_register_device(&lcd_wvga_device, &lcd_wvga_data); + mxc_register_device(&elcdif_device, &fb_data[0]); + mxc_register_device(&mxs_viim, NULL); + + mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata); + mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata); + mxc_register_device(&android_usb_device, &android_usb_pdata); + mxc_register_device(&mxc_powerkey_device, NULL); + mx50_rdp_init_mc13892(); +/* + pm_power_off = mxc_power_off; + */ + mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); + mx5_set_otghost_vbus_func(mx50_arm2_usb_set_vbus); + mx5_usb_dr_init(); + mx5_usbh1_init(); +} + +static void __init mx50_rdp_timer_init(void) +{ + struct clk *uart_clk; + + mx50_clocks_init(32768, 24000000, 22579200); + + uart_clk = clk_get(NULL, "uart_clk.0"); + early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx50_rdp_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX50_RDP data structure. + */ +MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") + /* Maintainer: Freescale Semiconductor, Inc. */ + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c b/arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c new file mode 100644 index 000000000000..e8411cec72b5 --- /dev/null +++ b/arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c @@ -0,0 +1,418 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +/* Coin cell charger enable */ +#define COINCHEN_LSH 23 +#define COINCHEN_WID 1 +/* Coin cell charger voltage setting */ +#define VCOIN_LSH 20 +#define VCOIN_WID 3 + +/* Coin Charger voltage */ +#define VCOIN_2_5V 0x0 +#define VCOIN_2_7V 0x1 +#define VCOIN_2_8V 0x2 +#define VCOIN_2_9V 0x3 +#define VCOIN_3_0V 0x4 +#define VCOIN_3_1V 0x5 +#define VCOIN_3_2V 0x6 +#define VCOIN_3_3V 0x7 + +/* Keeps VSRTC and CLK32KMCU on for all states */ +#define DRM_LSH 4 +#define DRM_WID 1 + +/* regulator standby mask */ +#define GEN1_STBY_MASK (1 << 1) +#define IOHI_STBY_MASK (1 << 4) +#define DIG_STBY_MASK (1 << 10) +#define GEN2_STBY_MASK (1 << 13) +#define PLL_STBY_MASK (1 << 16) +#define USB2_STBY_MASK (1 << 19) + +#define GEN3_STBY_MASK (1 << 1) +#define CAM_STBY_MASK (1 << 7) +#define VIDEO_STBY_MASK (1 << 13) +#define AUDIO_STBY_MASK (1 << 16) +#define SD_STBY_MASK (1 << 19) + +#define REG_MODE_0_ALL_MASK (DIG_STBY_MASK | GEN1_STBY_MASK) +#define REG_MODE_1_ALL_MASK (CAM_STBY_MASK | VIDEO_STBY_MASK |\ + AUDIO_STBY_MASK | SD_STBY_MASK) + +/* switch mode setting */ +#define SW1MODE_LSB 0 +#define SW2MODE_LSB 10 +#define SW3MODE_LSB 0 +#define SW4MODE_LSB 8 + +#define SWMODE_MASK 0xF +#define SWMODE_AUTO 0x8 + +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +static struct regulator_consumer_supply vgen1_consumers[] = { + { + /* sgtl5000 */ + .supply = "VDDA", + .dev_name = "1-000a", + }, + { + /* sgtl5000 */ + .supply = "VDDIO", + .dev_name = "1-000a", + }, +}; + +struct mc13892; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 850000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .name = "VIOHI", + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb_init = { + .constraints = { + .name = "VUSB", + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data swbst_init = { + .constraints = { + .name = "SWBST", + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .name = "VDIG", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(1200), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data vpll_init = { + .constraints = { + .name = "VPLL", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vusb2_init = { + .constraints = { + .name = "VUSB2", + .min_uV = mV_to_uV(2400), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vvideo_init = { + .constraints = { + .name = "VVIDEO", + .min_uV = mV_to_uV(2775), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data vaudio_init = { + .constraints = { + .name = "VAUDIO", + .min_uV = mV_to_uV(2300), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vsd_init = { + .constraints = { + .name = "VSD", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + } +}; + +static struct regulator_init_data vcam_init = { + .constraints = { + .name = "VCAM", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, + .always_on = 1, + } +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "VGEN1", + .min_uV = mV_to_uV(3000), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vgen1_consumers), + .consumer_supplies = vgen1_consumers, +}; + +static struct regulator_init_data vgen2_init = { + .constraints = { + .name = "VGEN2", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + } +}; + +static struct regulator_init_data vgen3_init = { + .constraints = { + .name = "VGEN3", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + } +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .name = "GPO1", + } +}; + +static struct regulator_init_data gpo2_init = { + .constraints = { + .name = "GPO2", + } +}; + +static struct regulator_init_data gpo3_init = { + .constraints = { + .name = "GPO3", + } +}; + +static struct regulator_init_data gpo4_init = { + .constraints = { + .name = "GPO4", + } +}; + +static int mc13892_regulator_init(struct mc13892 *mc13892) +{ + unsigned int value, register_mask; + printk("Initializing regulators for mx50 rdp.\n"); + + /* enable standby controll for all regulators */ + pmic_read_reg(REG_MODE_0, &value, 0xffffff); + value |= REG_MODE_0_ALL_MASK; + pmic_write_reg(REG_MODE_0, value, 0xffffff); + + pmic_read_reg(REG_MODE_1, &value, 0xffffff); + value |= REG_MODE_1_ALL_MASK; + pmic_write_reg(REG_MODE_1, value, 0xffffff); + + /* enable switch audo mode */ + pmic_read_reg(REG_IDENTIFICATION, &value, 0xffffff); + /* only for mc13892 2.0A */ + if ((value & 0x0000FFFF) == 0x45d0) { + pmic_read_reg(REG_SW_4, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW1MODE_LSB) | + (SWMODE_MASK << SW2MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW1MODE_LSB) | + (SWMODE_AUTO << SW2MODE_LSB); + pmic_write_reg(REG_SW_4, value, 0xffffff); + + pmic_read_reg(REG_SW_5, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW3MODE_LSB) | + (SWMODE_MASK << SW4MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW3MODE_LSB) | + (SWMODE_AUTO << SW4MODE_LSB); + pmic_write_reg(REG_SW_5, value, 0xffffff); + } + /* Enable coin cell charger */ + value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V); + register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); + +#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) + value = BITFVAL(DRM, 1); + register_mask = BITFMASK(DRM); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); +#endif + + mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); + mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); + mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); + mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); + mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); + mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); + mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); + mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); + mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); + mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); + mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); + mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); + mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); + mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); + mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); + mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); + mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); + mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); + mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); + mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); + mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); + + regulator_has_full_constraints(); + + return 0; +} + +static struct mc13892_platform_data mc13892_plat = { + .init = mc13892_regulator_init, +}; + +static struct spi_board_info __initdata mc13892_spi_device = { + .modalias = "pmic_spi", + .irq = IOMUX_TO_IRQ_V3(114), + .max_speed_hz = 6000000, /* max spi SCK clock speed in HZ */ + .bus_num = 3, + .chip_select = 0, + .platform_data = &mc13892_plat, +}; + + +int __init mx50_rdp_init_mc13892(void) +{ + return spi_register_board_info(&mc13892_spi_device, 1); +} diff --git a/arch/arm/mach-mx5/mx50_suspend.S b/arch/arm/mach-mx5/mx50_suspend.S new file mode 100644 index 000000000000..4d9e1b49a23d --- /dev/null +++ b/arch/arm/mach-mx5/mx50_suspend.S @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include + +#define ARM_CTRL_DCACHE 1 << 2 +#define ARM_CTRL_ICACHE 1 << 12 +#define ARM_AUXCR_L2EN 1 << 1 + +/* + * mx50_suspend + * + * Suspend the processor (eg, wait for interrupt). + * Set the DDR into Self Refresh + * IRQs are already disabled. + */ +ENTRY(mx50_suspend) + stmfd sp!, {r4,r5,r6,r7,r8, r9,r10,r11} @ Save registers + + mov r6, r0 @save databahn address + +/* Before putting DDR into self-refresh, make sure + any LPM mode that the DDR might be in is exited. +*/ + /* If Databahn is in LPM4, exit that mode first. */ + ldr r8,[r6, #0x50] @Store LPM mode in r8 + mov r0, r8 + bic r0, r0, #0x1F + str r0,[r6, #0x50] + + + /* Disable L1 caches */ + mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg + bic r0, r0, #ARM_CTRL_ICACHE @ Disable ICache + bic r0, r0, #ARM_CTRL_DCACHE @ Disable DCache + mcr p15, 0, r0, c1, c0, 0 @ Update system control reg + + mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR + ands r3, r0, #0x7000000 @ Isolate level of coherency + mov r3, r3, lsr #23 @ Cache level value (naturally aligned) + beq FinishedClean + mov r10, #0 +Loop1Clean: + add r2, r10, r10, lsr #1 @ Work out cache level + mov r1, r0, lsr r2 @ R0 bottom 3 bits = Cache Type + @ for this level + and r1, r1, #7 @ Get those 3 bits alone + cmp r1, #2 + blt SkipClean @ No cache or only instruction cache + @ at this level + mcr p15, 2, r10, c0, c0, 0 @ Write the Cache Size selection register + mov r1, #0 + .long 0xF57FF06F @ ISB + mrc p15, 1, r1, c0, c0, 0 @ Reads current Cache Size ID register + and r2, r1, #7 @ Extract the line length field + add r2, r2, #4 @ Add 4 for the line length offset + @ (log2 16 bytes) + ldr r4, =0x3FF + ands r4, r4, r1, lsr #3 @ R4 is the max number on the + @ way size (right aligned) + clz r5, r4 @ R5 is the bit position of the way + @ size increment + ldr r7, =0x00007FFF + ands r7, r7, r1, lsr #13 @ R7 is the max number of the index + @ size (right aligned) +Loop2Clean: + mov r9, r4 @ R9 working copy of the max way size + @ (right aligned) +Loop3Clean: + orr r11, r10, r9, lsl r5 @ Factor in the way number and cache + @ number into R11 + orr r11, r11, r7, lsl r2 @ Factor in the index number + mcr p15, 0, r11, c7, c14, 2 @ Clean and invalidate by set/way + subs r9, r9, #1 @ Decrement the way number + bge Loop3Clean + subs r7, r7, #1 @ Decrement the index + bge Loop2Clean +SkipClean: + add r10, r10, #2 @ Increment the cache number + cmp r3, r10 + bgt Loop1Clean + +FinishedClean: + + /* Disable L2 cache */ + mrc p15, 0, r0, c1, c0, 1 @ R0 = auxiliary control reg + bic r0, r0, #ARM_AUXCR_L2EN @ Disable L2 cache + mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg + +/* Wait for the databahn to idle + Meaning, no access to the databahn is + being made. +*/ +EnterWFI: + ldr r0,[r6, #0x13c] + and r0, r0, #0x100 + ldr r2, =0x100 + cmp r0, r2 + beq EnterWFI + + /* Enter self-refresh mode */ + ldr r0,[r6, #0x4c] + orr r0,r0,#0x1 + str r0,[r6, #0x4c] + +LoopCKE0: + /* Wait for CKE = 0 */ + ldr r0,[r6, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + beq LoopCKE0 + + /* Stop controller */ + ldr r0,[r6] + bic r0, r0, #0x1 + str r0,[r6] + + .long 0xe320f003 @ Opcode for WFI + + /* Start controller */ + ldr r0,[r6] + orr r0,r0,#0x1 + str r0,[r6] + +LoopPHY: + /* Wait for PHY ready */ + ldr r0,[r6, #0x264] + and r0, r0, #0xfffffffe + ldr r2, =0x0 + cmp r0, r2 + beq LoopPHY + + /*Leave self-refresh mode */ + ldr r0,[r6, #0x4c] + and r0,r0,#0xfffffffe + str r0,[r6, #0x4c] + +LoopCKE1: + /*Wait for CKE = 1 */ + ldr r0,[r6, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + bne LoopCKE1 + + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ Invalidate inst cache + +/* Invalidate data caches */ + mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR + ands r3, r0, #0x7000000 @ Isolate level of coherency + mov r3, r3, lsr #23 @ Cache level value (naturally aligned) + beq FinishedInvalidate + mov r10, #0 +Loop1Invalidate: + add r2, r10, r10, lsr #1 @ Work out cache level + mov r1, r0, lsr r2 @ R0 bottom 3 bits = Cache + @ Type for this level + and r1, r1, #7 @ Get those 3 bits alone + cmp r1, #2 + blt SkipInvalidate @ No cache or only instruction cache + @at this level + mcr p15, 2, r10, c0, c0, 0 @ Write the Cache Size selection register + mov r1, #0 + .long 0xF57FF06F @ ISB + mrc p15, 1, r1, c0, c0, 0 @ Reads current Cache Size ID register + and r2, r1, #7 @ Extract the line length field + add r2, r2, #4 @ Add 4 for the line length offset + @(log2 16 bytes) + ldr r4, =0x3FF + ands r4, r4, r1, lsr #3 @ R4 is the max number on the way + @size (right aligned) + clz r5, r4 @ R5 is the bit position of the way + @ size increment + ldr r7, =0x00007FFF + ands r7, r7, r1, lsr #13 @ R7 is the max number of the + @ index size (right aligned) +Loop2Invalidate: + mov r9, r4 @ R9 working copy of the max way + @ size (right aligned) +Loop3Invalidate: + orr r11, r10, r9, lsl r5 @ Factor in the way number and cache + @ number into R11 + orr r11, r11, r7, lsl r2 @ Factor in the index number + mcr p15, 0, r11, c7, c6, 2 @ Invalidate by set/way + subs r9, r9, #1 @ Decrement the way number + bge Loop3Invalidate + subs r7, r7, #1 @ Decrement the index + bge Loop2Invalidate +SkipInvalidate: + add r10, r10, #2 @ Increment the cache number + cmp r3, r10 + bgt Loop1Invalidate + +FinishedInvalidate: + + /* Enable L2 cache */ + mrc p15, 0, r0, c1, c0, 1 @ R0 = auxiliary control reg + orr r0, r0, #ARM_AUXCR_L2EN @ Enable L2 cache + mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg + + /* Enable L1 caches */ + mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg + orr r0, r0, #ARM_CTRL_ICACHE @ Enable ICache + orr r0, r0, #ARM_CTRL_DCACHE @ Enable DCache + mcr p15, 0, r0, c1, c0, 0 @ Update system control reg + + /* restore LPM mode. */ + str r8, [r6, #0x50] + + /* Restore registers */ + ldmfd sp!, {r4,r5,r6,r7,r8,r9,r10,r11} + mov pc, lr + + .type mx50_do_suspend, #object +ENTRY(mx50_do_suspend) + .word mx50_suspend + .size mx50_suspend, . - mx50_suspend diff --git a/arch/arm/mach-mx5/mx50_wfi.S b/arch/arm/mach-mx5/mx50_wfi.S new file mode 100644 index 000000000000..b0d984c4527d --- /dev/null +++ b/arch/arm/mach-mx5/mx50_wfi.S @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include + +/* + * mx50_wait + * + * Idle the processor (eg, wait for interrupt). + * Make sure DDR is in self-refresh. + * IRQs are already disabled. + */ +ENTRY(mx50_wait) + stmfd sp!, {r3,r4,r5,r6,r7,r8,r9,r10,r11} @ Save registers + + mov r6, r0 @save CCM address + mov r5, r1 @save DataBahn address + + /* + * Make sure the DDR is self-refresh, before setting the clock bits. + */ + + /* Step 2: Poll the CKE_STATUS bit. */ +LoopCKE0: + /* Wait for CKE = 0 */ + ldr r0,[r5, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + beq LoopCKE0 + + /* Set the DDR_CLKGATE to 0x1. */ + ldr r0, [r6, #0x98] + bic r0, r0, #0x80000000 + str r0, [r6, #0x98] + + .long 0xe320f003 @ Opcode for WFI + + /* Set the DDR_CLKGATE to 0x3. */ + ldr r0, [r6, #0x98] + orr r0, r0, #0xC0000000 + str r0, [r6, #0x98] + + /* Restore registers */ + ldmfd sp!, {r3,r4,r5,r6,r7,r8,r9,r10,r11} + mov pc, lr + + .type mx50_do_wait, #object +ENTRY(mx50_do_wait) + .word mx50_wait + .size mx50_wait, . - mx50_wait diff --git a/arch/arm/mach-mx5/regs-apbh.h b/arch/arm/mach-mx5/regs-apbh.h new file mode 100644 index 000000000000..23b9f4baa404 --- /dev/null +++ b/arch/arm/mach-mx5/regs-apbh.h @@ -0,0 +1,512 @@ +/* + * Freescale APBH Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.3 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___APBH_H +#define __ARCH_ARM___APBH_H + + +#define HW_APBH_CTRL0 (0x00000000) +#define HW_APBH_CTRL0_SET (0x00000004) +#define HW_APBH_CTRL0_CLR (0x00000008) +#define HW_APBH_CTRL0_TOG (0x0000000c) + +#define BM_APBH_CTRL0_SFTRST 0x80000000 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 +#define BM_APBH_CTRL0_APB_BURST_EN 0x10000000 +#define BP_APBH_CTRL0_RSVD0 16 +#define BM_APBH_CTRL0_RSVD0 0x0FFF0000 +#define BF_APBH_CTRL0_RSVD0(v) \ + (((v) << 16) & BM_APBH_CTRL0_RSVD0) +#define BP_APBH_CTRL0_CLKGATE_CHANNEL 0 +#define BM_APBH_CTRL0_CLKGATE_CHANNEL 0x0000FFFF +#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CTRL0_CLKGATE_CHANNEL) +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x0001 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x0002 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x0004 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x0008 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND4 0x0010 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND5 0x0020 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND6 0x0040 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND7 0x0080 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP 0x0100 + +#define HW_APBH_CTRL1 (0x00000010) +#define HW_APBH_CTRL1_SET (0x00000014) +#define HW_APBH_CTRL1_CLR (0x00000018) +#define HW_APBH_CTRL1_TOG (0x0000001c) + +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN 0x80000000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN 0x40000000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN 0x20000000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN 0x10000000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN 0x08000000 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN 0x04000000 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN 0x02000000 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN 0x01000000 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ 0x00008000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ 0x00004000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ 0x00002000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ 0x00001000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ 0x00000800 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ 0x00000400 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ 0x00000200 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ 0x00000100 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 + +#define HW_APBH_CTRL2 (0x00000020) +#define HW_APBH_CTRL2_SET (0x00000024) +#define HW_APBH_CTRL2_CLR (0x00000028) +#define HW_APBH_CTRL2_TOG (0x0000002c) + +#define BM_APBH_CTRL2_CH15_ERROR_STATUS 0x80000000 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH14_ERROR_STATUS 0x40000000 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH13_ERROR_STATUS 0x20000000 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH12_ERROR_STATUS 0x10000000 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH11_ERROR_STATUS 0x08000000 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH10_ERROR_STATUS 0x04000000 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH9_ERROR_STATUS 0x02000000 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH8_ERROR_STATUS 0x01000000 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH7_ERROR_STATUS 0x00800000 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH6_ERROR_STATUS 0x00400000 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH5_ERROR_STATUS 0x00200000 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH4_ERROR_STATUS 0x00100000 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH3_ERROR_STATUS 0x00080000 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH2_ERROR_STATUS 0x00040000 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH1_ERROR_STATUS 0x00020000 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH0_ERROR_STATUS 0x00010000 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH15_ERROR_IRQ 0x00008000 +#define BM_APBH_CTRL2_CH14_ERROR_IRQ 0x00004000 +#define BM_APBH_CTRL2_CH13_ERROR_IRQ 0x00002000 +#define BM_APBH_CTRL2_CH12_ERROR_IRQ 0x00001000 +#define BM_APBH_CTRL2_CH11_ERROR_IRQ 0x00000800 +#define BM_APBH_CTRL2_CH10_ERROR_IRQ 0x00000400 +#define BM_APBH_CTRL2_CH9_ERROR_IRQ 0x00000200 +#define BM_APBH_CTRL2_CH8_ERROR_IRQ 0x00000100 +#define BM_APBH_CTRL2_CH7_ERROR_IRQ 0x00000080 +#define BM_APBH_CTRL2_CH6_ERROR_IRQ 0x00000040 +#define BM_APBH_CTRL2_CH5_ERROR_IRQ 0x00000020 +#define BM_APBH_CTRL2_CH4_ERROR_IRQ 0x00000010 +#define BM_APBH_CTRL2_CH3_ERROR_IRQ 0x00000008 +#define BM_APBH_CTRL2_CH2_ERROR_IRQ 0x00000004 +#define BM_APBH_CTRL2_CH1_ERROR_IRQ 0x00000002 +#define BM_APBH_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define HW_APBH_CHANNEL_CTRL (0x00000030) +#define HW_APBH_CHANNEL_CTRL_SET (0x00000034) +#define HW_APBH_CHANNEL_CTRL_CLR (0x00000038) +#define HW_APBH_CHANNEL_CTRL_TOG (0x0000003c) + +#define BP_APBH_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBH_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 +#define BF_APBH_CHANNEL_CTRL_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBH_CHANNEL_CTRL_RESET_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND0 0x0001 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND1 0x0002 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND2 0x0004 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND3 0x0008 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND4 0x0010 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND5 0x0020 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND6 0x0040 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND7 0x0080 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP 0x0100 +#define BP_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0x0000FFFF +#define BF_APBH_CHANNEL_CTRL_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND0 0x0001 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND1 0x0002 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND2 0x0004 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND3 0x0008 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND4 0x0010 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND5 0x0020 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND6 0x0040 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND7 0x0080 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP 0x0100 + +#define HW_APBH_DEVSEL (0x00000040) + +#define BP_APBH_DEVSEL_CH15 30 +#define BM_APBH_DEVSEL_CH15 0xC0000000 +#define BF_APBH_DEVSEL_CH15(v) \ + (((v) << 30) & BM_APBH_DEVSEL_CH15) +#define BP_APBH_DEVSEL_CH14 28 +#define BM_APBH_DEVSEL_CH14 0x30000000 +#define BF_APBH_DEVSEL_CH14(v) \ + (((v) << 28) & BM_APBH_DEVSEL_CH14) +#define BP_APBH_DEVSEL_CH13 26 +#define BM_APBH_DEVSEL_CH13 0x0C000000 +#define BF_APBH_DEVSEL_CH13(v) \ + (((v) << 26) & BM_APBH_DEVSEL_CH13) +#define BP_APBH_DEVSEL_CH12 24 +#define BM_APBH_DEVSEL_CH12 0x03000000 +#define BF_APBH_DEVSEL_CH12(v) \ + (((v) << 24) & BM_APBH_DEVSEL_CH12) +#define BP_APBH_DEVSEL_CH11 22 +#define BM_APBH_DEVSEL_CH11 0x00C00000 +#define BF_APBH_DEVSEL_CH11(v) \ + (((v) << 22) & BM_APBH_DEVSEL_CH11) +#define BP_APBH_DEVSEL_CH10 20 +#define BM_APBH_DEVSEL_CH10 0x00300000 +#define BF_APBH_DEVSEL_CH10(v) \ + (((v) << 20) & BM_APBH_DEVSEL_CH10) +#define BP_APBH_DEVSEL_CH9 18 +#define BM_APBH_DEVSEL_CH9 0x000C0000 +#define BF_APBH_DEVSEL_CH9(v) \ + (((v) << 18) & BM_APBH_DEVSEL_CH9) +#define BP_APBH_DEVSEL_CH8 16 +#define BM_APBH_DEVSEL_CH8 0x00030000 +#define BF_APBH_DEVSEL_CH8(v) \ + (((v) << 16) & BM_APBH_DEVSEL_CH8) +#define BP_APBH_DEVSEL_CH7 14 +#define BM_APBH_DEVSEL_CH7 0x0000C000 +#define BF_APBH_DEVSEL_CH7(v) \ + (((v) << 14) & BM_APBH_DEVSEL_CH7) +#define BP_APBH_DEVSEL_CH6 12 +#define BM_APBH_DEVSEL_CH6 0x00003000 +#define BF_APBH_DEVSEL_CH6(v) \ + (((v) << 12) & BM_APBH_DEVSEL_CH6) +#define BP_APBH_DEVSEL_CH5 10 +#define BM_APBH_DEVSEL_CH5 0x00000C00 +#define BF_APBH_DEVSEL_CH5(v) \ + (((v) << 10) & BM_APBH_DEVSEL_CH5) +#define BP_APBH_DEVSEL_CH4 8 +#define BM_APBH_DEVSEL_CH4 0x00000300 +#define BF_APBH_DEVSEL_CH4(v) \ + (((v) << 8) & BM_APBH_DEVSEL_CH4) +#define BP_APBH_DEVSEL_CH3 6 +#define BM_APBH_DEVSEL_CH3 0x000000C0 +#define BF_APBH_DEVSEL_CH3(v) \ + (((v) << 6) & BM_APBH_DEVSEL_CH3) +#define BP_APBH_DEVSEL_CH2 4 +#define BM_APBH_DEVSEL_CH2 0x00000030 +#define BF_APBH_DEVSEL_CH2(v) \ + (((v) << 4) & BM_APBH_DEVSEL_CH2) +#define BP_APBH_DEVSEL_CH1 2 +#define BM_APBH_DEVSEL_CH1 0x0000000C +#define BF_APBH_DEVSEL_CH1(v) \ + (((v) << 2) & BM_APBH_DEVSEL_CH1) +#define BP_APBH_DEVSEL_CH0 0 +#define BM_APBH_DEVSEL_CH0 0x00000003 +#define BF_APBH_DEVSEL_CH0(v) \ + (((v) << 0) & BM_APBH_DEVSEL_CH0) + +#define HW_APBH_DMA_BURST_SIZE (0x00000050) + +#define BP_APBH_DMA_BURST_SIZE_CH15 30 +#define BM_APBH_DMA_BURST_SIZE_CH15 0xC0000000 +#define BF_APBH_DMA_BURST_SIZE_CH15(v) \ + (((v) << 30) & BM_APBH_DMA_BURST_SIZE_CH15) +#define BP_APBH_DMA_BURST_SIZE_CH14 28 +#define BM_APBH_DMA_BURST_SIZE_CH14 0x30000000 +#define BF_APBH_DMA_BURST_SIZE_CH14(v) \ + (((v) << 28) & BM_APBH_DMA_BURST_SIZE_CH14) +#define BP_APBH_DMA_BURST_SIZE_CH13 26 +#define BM_APBH_DMA_BURST_SIZE_CH13 0x0C000000 +#define BF_APBH_DMA_BURST_SIZE_CH13(v) \ + (((v) << 26) & BM_APBH_DMA_BURST_SIZE_CH13) +#define BP_APBH_DMA_BURST_SIZE_CH12 24 +#define BM_APBH_DMA_BURST_SIZE_CH12 0x03000000 +#define BF_APBH_DMA_BURST_SIZE_CH12(v) \ + (((v) << 24) & BM_APBH_DMA_BURST_SIZE_CH12) +#define BP_APBH_DMA_BURST_SIZE_CH11 22 +#define BM_APBH_DMA_BURST_SIZE_CH11 0x00C00000 +#define BF_APBH_DMA_BURST_SIZE_CH11(v) \ + (((v) << 22) & BM_APBH_DMA_BURST_SIZE_CH11) +#define BP_APBH_DMA_BURST_SIZE_CH10 20 +#define BM_APBH_DMA_BURST_SIZE_CH10 0x00300000 +#define BF_APBH_DMA_BURST_SIZE_CH10(v) \ + (((v) << 20) & BM_APBH_DMA_BURST_SIZE_CH10) +#define BP_APBH_DMA_BURST_SIZE_CH9 18 +#define BM_APBH_DMA_BURST_SIZE_CH9 0x000C0000 +#define BF_APBH_DMA_BURST_SIZE_CH9(v) \ + (((v) << 18) & BM_APBH_DMA_BURST_SIZE_CH9) +#define BP_APBH_DMA_BURST_SIZE_CH8 16 +#define BM_APBH_DMA_BURST_SIZE_CH8 0x00030000 +#define BF_APBH_DMA_BURST_SIZE_CH8(v) \ + (((v) << 16) & BM_APBH_DMA_BURST_SIZE_CH8) +#define BV_APBH_DMA_BURST_SIZE_CH8__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH8__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH8__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH7 14 +#define BM_APBH_DMA_BURST_SIZE_CH7 0x0000C000 +#define BF_APBH_DMA_BURST_SIZE_CH7(v) \ + (((v) << 14) & BM_APBH_DMA_BURST_SIZE_CH7) +#define BP_APBH_DMA_BURST_SIZE_CH6 12 +#define BM_APBH_DMA_BURST_SIZE_CH6 0x00003000 +#define BF_APBH_DMA_BURST_SIZE_CH6(v) \ + (((v) << 12) & BM_APBH_DMA_BURST_SIZE_CH6) +#define BP_APBH_DMA_BURST_SIZE_CH5 10 +#define BM_APBH_DMA_BURST_SIZE_CH5 0x00000C00 +#define BF_APBH_DMA_BURST_SIZE_CH5(v) \ + (((v) << 10) & BM_APBH_DMA_BURST_SIZE_CH5) +#define BP_APBH_DMA_BURST_SIZE_CH4 8 +#define BM_APBH_DMA_BURST_SIZE_CH4 0x00000300 +#define BF_APBH_DMA_BURST_SIZE_CH4(v) \ + (((v) << 8) & BM_APBH_DMA_BURST_SIZE_CH4) +#define BP_APBH_DMA_BURST_SIZE_CH3 6 +#define BM_APBH_DMA_BURST_SIZE_CH3 0x000000C0 +#define BF_APBH_DMA_BURST_SIZE_CH3(v) \ + (((v) << 6) & BM_APBH_DMA_BURST_SIZE_CH3) +#define BP_APBH_DMA_BURST_SIZE_CH2 4 +#define BM_APBH_DMA_BURST_SIZE_CH2 0x00000030 +#define BF_APBH_DMA_BURST_SIZE_CH2(v) \ + (((v) << 4) & BM_APBH_DMA_BURST_SIZE_CH2) +#define BP_APBH_DMA_BURST_SIZE_CH1 2 +#define BM_APBH_DMA_BURST_SIZE_CH1 0x0000000C +#define BF_APBH_DMA_BURST_SIZE_CH1(v) \ + (((v) << 2) & BM_APBH_DMA_BURST_SIZE_CH1) +#define BP_APBH_DMA_BURST_SIZE_CH0 0 +#define BM_APBH_DMA_BURST_SIZE_CH0 0x00000003 +#define BF_APBH_DMA_BURST_SIZE_CH0(v) \ + (((v) << 0) & BM_APBH_DMA_BURST_SIZE_CH0) + +#define HW_APBH_DEBUG (0x00000060) + +#define BP_APBH_DEBUG_RSVD 1 +#define BM_APBH_DEBUG_RSVD 0xFFFFFFFE +#define BF_APBH_DEBUG_RSVD(v) \ + (((v) << 1) & BM_APBH_DEBUG_RSVD) +#define BM_APBH_DEBUG_GPMI_ONE_FIFO 0x00000001 + +/* + * multi-register-define name HW_APBH_CHn_CURCMDAR + * base 0x00000100 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CURCMDAR(n) (0x00000100 + (n) * 0x70) +#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_NXTCMDAR + * base 0x00000110 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_NXTCMDAR(n) (0x00000110 + (n) * 0x70) +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_CMD + * base 0x00000120 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CMD(n) (0x00000120 + (n) * 0x70) +#define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBH_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) +#define BP_APBH_CHn_CMD_RSVD1 9 +#define BM_APBH_CHn_CMD_RSVD1 0x00000E00 +#define BF_APBH_CHn_CMD_RSVD1(v) \ + (((v) << 9) & BM_APBH_CHn_CMD_RSVD1) +#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_COMMAND 0x00000003 +#define BF_APBH_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 + +/* + * multi-register-define name HW_APBH_CHn_BAR + * base 0x00000130 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_BAR(n) (0x00000130 + (n) * 0x70) +#define BP_APBH_CHn_BAR_ADDRESS 0 +#define BM_APBH_CHn_BAR_ADDRESS 0xFFFFFFFF +#define BF_APBH_CHn_BAR_ADDRESS(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_SEMA + * base 0x00000140 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_SEMA(n) (0x00000140 + (n) * 0x70) +#define BP_APBH_CHn_SEMA_RSVD2 24 +#define BM_APBH_CHn_SEMA_RSVD2 0xFF000000 +#define BF_APBH_CHn_SEMA_RSVD2(v) \ + (((v) << 24) & BM_APBH_CHn_SEMA_RSVD2) +#define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBH_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) +#define BP_APBH_CHn_SEMA_RSVD1 8 +#define BM_APBH_CHn_SEMA_RSVD1 0x0000FF00 +#define BF_APBH_CHn_SEMA_RSVD1(v) \ + (((v) << 8) & BM_APBH_CHn_SEMA_RSVD1) +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) + +/* + * multi-register-define name HW_APBH_CHn_DEBUG1 + * base 0x00000150 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG1(n) (0x00000150 + (n) * 0x70) +#define BM_APBH_CHn_DEBUG1_REQ 0x80000000 +#define BM_APBH_CHn_DEBUG1_BURST 0x40000000 +#define BM_APBH_CHn_DEBUG1_KICK 0x20000000 +#define BM_APBH_CHn_DEBUG1_END 0x10000000 +#define BM_APBH_CHn_DEBUG1_SENSE 0x08000000 +#define BM_APBH_CHn_DEBUG1_READY 0x04000000 +#define BM_APBH_CHn_DEBUG1_LOCK 0x02000000 +#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 +#define BP_APBH_CHn_DEBUG1_RSVD1 5 +#define BM_APBH_CHn_DEBUG1_RSVD1 0x000FFFE0 +#define BF_APBH_CHn_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_APBH_CHn_DEBUG1_RSVD1) +#define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x0000001F +#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG1_STATEMACHINE) +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_READY 0x1F + +/* + * multi-register-define name HW_APBH_CHn_DEBUG2 + * base 0x00000160 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG2(n) (0x00000160 + (n) * 0x70) +#define BP_APBH_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBH_CHn_DEBUG2_APB_BYTES 0xFFFF0000 +#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) \ + (((v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES) +#define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBH_CHn_DEBUG2_AHB_BYTES 0x0000FFFF +#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG2_AHB_BYTES) + +#define HW_APBH_VERSION (0x00000800) + +#define BP_APBH_VERSION_MAJOR 24 +#define BM_APBH_VERSION_MAJOR 0xFF000000 +#define BF_APBH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_APBH_VERSION_MAJOR) +#define BP_APBH_VERSION_MINOR 16 +#define BM_APBH_VERSION_MINOR 0x00FF0000 +#define BF_APBH_VERSION_MINOR(v) \ + (((v) << 16) & BM_APBH_VERSION_MINOR) +#define BP_APBH_VERSION_STEP 0 +#define BM_APBH_VERSION_STEP 0x0000FFFF +#define BF_APBH_VERSION_STEP(v) \ + (((v) << 0) & BM_APBH_VERSION_STEP) +#endif /* __ARCH_ARM___APBH_H */ diff --git a/arch/arm/mach-mx5/sdma_script_code_mx50.h b/arch/arm/mach-mx5/sdma_script_code_mx50.h new file mode 100644 index 000000000000..bac8c6f87bda --- /dev/null +++ b/arch/arm/mach-mx5/sdma_script_code_mx50.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/******************************************************************************* + + SDMA RELEASE LABEL: "SDMA_CODEX.01.00.00" + +*******************************************************************************/ + +#ifndef SDMA_SCRIPT_CODE_MX50_H +#define SDMA_SCRIPT_CODE_MX50_H + + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define start_ADDR_MX50 0 +#define start_SIZE_MX50 18 + +#define core_ADDR_MX50 80 +#define core_SIZE_MX50 232 + +#define common_ADDR_MX50 312 +#define common_SIZE_MX50 330 + +#define ap_2_ap_ADDR_MX50 642 +#define ap_2_ap_SIZE_MX50 41 + +#define app_2_mcu_ADDR_MX50 683 +#define app_2_mcu_SIZE_MX50 64 + +#define mcu_2_app_ADDR_MX50 747 +#define mcu_2_app_SIZE_MX50 70 + +#define uart_2_mcu_ADDR_MX50 817 +#define uart_2_mcu_SIZE_MX50 74 + +#define shp_2_mcu_ADDR_MX50 891 +#define shp_2_mcu_SIZE_MX50 69 + +#define mcu_2_shp_ADDR_MX50 960 +#define mcu_2_shp_SIZE_MX50 72 + +#define uartsh_2_mcu_ADDR_MX50 1032 +#define uartsh_2_mcu_SIZE_MX50 68 + +#define loop_DMAs_routines_ADDR_MX50 1100 +#define loop_DMAs_routines_SIZE_MX50 227 + +#define test_ADDR_MX50 1327 +#define test_SIZE_MX50 63 + +#define signature_ADDR_MX50 1023 +#define signature_SIZE_MX50 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define mcu_2_ssiapp_ADDR_MX50 6144 +#define mcu_2_ssiapp_SIZE_MX50 96 + +#define mcu_2_ssish_ADDR_MX50 6240 +#define mcu_2_ssish_SIZE_MX50 95 + +/*! +* SDMA RAM image start address and size +*/ + +#define RAM_CODE_START_ADDR_MX50 6144 +#define RAM_CODE_SIZE_MX50 191 + +/*! +* Buffer that holds the SDMA RAM image +*/ +__attribute__ ((__aligned__(4))) +static const short sdma_code_mx50[] = +{ +0xc1e3, 0x57db, 0x52f3, 0x6a01, 0x008f, 0x00d5, 0x7d01, 0x008d, +0x05a0, 0x5deb, 0x0478, 0x7d03, 0x0479, 0x7d2c, 0x7c36, 0x0479, +0x7c1f, 0x56ee, 0x0f00, 0x0660, 0x7d05, 0x6509, 0x7e43, 0x620a, +0x7e41, 0x981e, 0x620a, 0x7e3e, 0x6509, 0x7e3c, 0x0512, 0x0512, +0x02ad, 0x0760, 0x7d03, 0x55fb, 0x6dd3, 0x9829, 0x55fb, 0x1d04, +0x6dd3, 0x6ac8, 0x7f2f, 0x1f01, 0x2003, 0x4800, 0x7ce4, 0x9851, +0x55fb, 0x6dd7, 0x0015, 0x7805, 0x6209, 0x6ac8, 0x6209, 0x6ac8, +0x6dd7, 0x9850, 0x55fb, 0x6dd7, 0x0015, 0x0015, 0x7805, 0x620a, +0x6ac8, 0x620a, 0x6ac8, 0x6dd7, 0x9850, 0x55fb, 0x6dd7, 0x0015, +0x0015, 0x0015, 0x7805, 0x620b, 0x6ac8, 0x620b, 0x6ac8, 0x6dd7, +0x7c09, 0x6ddf, 0x7f07, 0x0000, 0x55eb, 0x4d00, 0x7d07, 0xc1fa, +0x57db, 0x9804, 0x0007, 0x68cc, 0x680c, 0xc213, 0xc20a, 0x9801, +0xc1d9, 0xc1e3, 0x57db, 0x52f3, 0x6a21, 0x008f, 0x00d5, 0x7d01, +0x008d, 0x05a0, 0x5deb, 0x56fb, 0x0478, 0x7d03, 0x0479, 0x7d32, +0x7c39, 0x0479, 0x7c28, 0x0b70, 0x0311, 0x53eb, 0x0f00, 0x0360, +0x7d05, 0x6509, 0x7e3f, 0x620a, 0x7e3d, 0x9882, 0x620a, 0x7e3a, +0x6509, 0x7e38, 0x0512, 0x0512, 0x02ad, 0x0760, 0x7d0a, 0x5a06, +0x7f31, 0x1f01, 0x2003, 0x4800, 0x7cea, 0x0b70, 0x0311, 0x5313, +0x98b3, 0x5a26, 0x7f27, 0x1f01, 0x2003, 0x4800, 0x7ce0, 0x0b70, +0x0311, 0x5313, 0x98b3, 0x0015, 0x7804, 0x6209, 0x5a06, 0x6209, +0x5a26, 0x98b2, 0x0015, 0x0015, 0x7804, 0x620a, 0x5a06, 0x620a, +0x5a26, 0x98b2, 0x0015, 0x0015, 0x0015, 0x7804, 0x620b, 0x5a06, +0x620b, 0x5a26, 0x7c07, 0x0000, 0x55eb, 0x4d00, 0x7d06, 0xc1fa, +0x57db, 0x9865, 0x0007, 0x680c, 0xc213, 0xc20a, 0x9862 +}; +#endif diff --git a/arch/arm/plat-mxc/include/mach/dmaengine.h b/arch/arm/plat-mxc/include/mach/dmaengine.h new file mode 100644 index 000000000000..1b28fb3b881f --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dmaengine.h @@ -0,0 +1,493 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_DMA_H +#define __ASM_ARM_ARCH_DMA_H + +#ifndef ARCH_DMA_PIO_WORDS +#define DMA_PIO_WORDS 15 +#else +#define DMA_PIO_WORDS ARCH_DMA_PIO_WORDS +#endif + +#define MXS_DMA_ALIGNMENT 8 + +/** + * struct mxs_dma_cmd_bits - MXS DMA hardware command bits. + * + * This structure describes the in-memory layout of the command bits in a DMA + * command. See the appropriate reference manual for a detailed description + * of what these bits mean to the DMA hardware. + */ +struct mxs_dma_cmd_bits { + unsigned int command:2; +#define NO_DMA_XFER 0x00 +#define DMA_WRITE 0x01 +#define DMA_READ 0x02 +#define DMA_SENSE 0x03 + + unsigned int chain:1; + unsigned int irq:1; + unsigned int nand_lock:1; + unsigned int nand_wait_4_ready:1; + unsigned int dec_sem:1; + unsigned int wait4end:1; + unsigned int halt_on_terminate:1; + unsigned int terminate_flush:1; + unsigned int resv2:2; + unsigned int pio_words:4; + unsigned int bytes:16; +}; + +/** + * struct mxs_dma_cmd - MXS DMA hardware command. + * + * This structure describes the in-memory layout of an entire DMA command, + * including space for the maximum number of PIO accesses. See the appropriate + * reference manual for a detailed description of what these fields mean to the + * DMA hardware. + */ +struct mxs_dma_cmd { + unsigned long next; + union { + unsigned long data; + struct mxs_dma_cmd_bits bits; + } cmd; + union { + dma_addr_t address; + unsigned long alternate; + }; + unsigned long pio_words[DMA_PIO_WORDS]; +}; + +/** + * struct mxs_dma_desc - MXS DMA command descriptor. + * + * This structure incorporates an MXS DMA hardware command structure, along + * with metadata. + * + * @cmd: The MXS DMA hardware command block. + * @flags: Flags that represent the state of this DMA descriptor. + * @address: The physical address of this descriptor. + * @buffer: A convenient place for software to put the virtual address of the + * associated data buffer (the physical address of the buffer + * appears in the DMA command). The MXS platform DMA software doesn't + * use this field -- it is provided as a convenience. + * @node: Links this structure into a list. + */ +struct mxs_dma_desc { + struct mxs_dma_cmd cmd; + unsigned int flags; +#define MXS_DMA_DESC_READY 0x80000000 +#define MXS_DMA_DESC_FIRST 0x00000001 +#define MXS_DMA_DESC_LAST 0x00000002 + dma_addr_t address; + void *buffer; + struct list_head node; +}; + +struct mxs_dma_info { + unsigned int status; +#define MXS_DMA_INFO_ERR 0x00000001 +#define MXS_DMA_INFO_ERR_STAT 0x00010000 + unsigned int buf_addr; +}; + +/** + * struct mxs_dma_chan - MXS DMA channel + * + * This structure represents a single DMA channel. The MXS platform code + * maintains an array of these structures to represent every DMA channel in the + * system (see mxs_dma_channels). + * + * @name: A human-readable string that describes how this channel is + * being used or what software "owns" it. This field is set when + * when the channel is reserved by mxs_dma_request(). + * @dev: A pointer to a struct device *, cast to an unsigned long, and + * representing the software that "owns" the channel. This field + * is set when when the channel is reserved by mxs_dma_request(). + * @lock: Arbitrates access to this channel. + * @dma: A pointer to a struct mxs_dma_device representing the driver + * code that operates this channel. + * @flags: Flag bits that represent the state of this channel. + * @active_num: If the channel is not busy, this value is zero. If the channel + * is busy, this field contains the number of DMA command + * descriptors at the head of the active list that the hardware + * has been told to process. This value is set at the moment the + * channel is enabled by mxs_dma_enable(). More descriptors may + * arrive after the channel is enabled, so the number of + * descriptors on the active list may be greater than this value. + * In fact, it should always be active_num + pending_num. + * @pending_num: The number of DMA command descriptors at the tail of the + * active list that the hardware has not been told to process. + * @active: The list of DMA command descriptors either currently being + * processed by the hardware or waiting to be processed. + * Descriptors being processed appear at the head of the list, + * while pending descriptors appear at the tail. The total number + * should always be active_num + pending_num. + * @done: The list of DMA command descriptors that have either been + * processed by the DMA hardware or aborted by a call to + * mxs_dma_disable(). + */ +struct mxs_dma_chan { + const char *name; + unsigned long dev; + spinlock_t lock; + struct mxs_dma_device *dma; + unsigned int flags; +#define MXS_DMA_FLAGS_IDLE 0x00000000 +#define MXS_DMA_FLAGS_BUSY 0x00000001 +#define MXS_DMA_FLAGS_FREE 0x00000000 +#define MXS_DMA_FLAGS_ALLOCATED 0x00010000 +#define MXS_DMA_FLAGS_VALID 0x80000000 + unsigned int active_num; + unsigned int pending_num; + struct list_head active; + struct list_head done; +}; + +/** + * struct mxs_dma_device - DMA channel driver interface. + * + * This structure represents the driver that operates a DMA channel. Every + * struct mxs_dma_chan contains a pointer to a structure of this type, which is + * installed when the driver registers to "own" the channel (see + * mxs_dma_device_register()). + */ +struct mxs_dma_device { + struct list_head node; + const char *name; + void __iomem *base; + unsigned int chan_base; + unsigned int chan_num; + unsigned int data; + struct platform_device *pdev; + + /* operations */ + int (*enable) (struct mxs_dma_chan *, unsigned int); + void (*disable) (struct mxs_dma_chan *, unsigned int); + void (*reset) (struct mxs_dma_device *, unsigned int); + void (*freeze) (struct mxs_dma_device *, unsigned int); + void (*unfreeze) (struct mxs_dma_device *, unsigned int); + int (*read_semaphore) (struct mxs_dma_device *, unsigned int); + void (*add_semaphore) (struct mxs_dma_device *, unsigned int, unsigned); + void (*info)(struct mxs_dma_device *, + unsigned int, struct mxs_dma_info *info); + void (*enable_irq) (struct mxs_dma_device *, unsigned int, int); + int (*irq_is_pending) (struct mxs_dma_device *, unsigned int); + void (*ack_irq) (struct mxs_dma_device *, unsigned int); + + void (*set_target) (struct mxs_dma_device *, unsigned int, int); +}; + +/** + * mxs_dma_device_register - Register a DMA driver. + * + * This function registers a driver for a contiguous group of DMA channels (the + * ordering of DMA channels is specified by the globally unique DMA channel + * numbers given in mach/dma.h). + * + * @pdev: A pointer to a structure that represents the driver. This structure + * contains fields that specify the first DMA channel number and the + * number of channels. + */ +extern int mxs_dma_device_register(struct mxs_dma_device *pdev); + +/** + * mxs_dma_request - Request to reserve a DMA channel. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @dev: A pointer to a struct device representing the channel "owner." + * @name: A human-readable string that identifies the channel owner or the + * purpose of the channel. + */ +extern int mxs_dma_request(int channel, struct device *dev, const char *name); + +/** + * mxs_dma_release - Release a DMA channel. + * + * This function releases a DMA channel from its current owner. + * + * The channel will NOT be released if it's marked "busy" (see + * mxs_dma_enable()). + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @dev: A pointer to a struct device representing the channel "owner." If + * this doesn't match the owner given to mxs_dma_request(), the + * channel will NOT be released. + */ +extern void mxs_dma_release(int channel, struct device *dev); + +/** + * mxs_dma_enable - Enable a DMA channel. + * + * If the given channel has any DMA descriptors on its active list, this + * function causes the DMA hardware to begin processing them. + * + * This function marks the DMA channel as "busy," whether or not there are any + * descriptors to process. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_enable(int channel); + +/** + * mxs_dma_disable - Disable a DMA channel. + * + * This function shuts down a DMA channel and marks it as "not busy." Any + * descriptors on the active list are immediately moved to the head of the + * "done" list, whether or not they have actually been processed by the + * hardware. The "ready" flags of these descriptors are NOT cleared, so they + * still appear to be active. + * + * This function immediately shuts down a DMA channel's hardware, aborting any + * I/O that may be in progress, potentially leaving I/O hardware in an undefined + * state. It is unwise to call this function if there is ANY chance the hardware + * is still processing a command. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_disable(int channel); + +/** + * mxs_dma_reset - Resets the DMA channel hardware. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_reset(int channel); + +/** + * mxs_dma_freeze - Freeze a DMA channel. + * + * This function causes the channel to continuously fail arbitration for bus + * access, which halts all forward progress without losing any state. A call to + * mxs_dma_unfreeze() will cause the channel to continue its current operation + * with no ill effect. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_freeze(int channel); + +/** + * mxs_dma_unfreeze - Unfreeze a DMA channel. + * + * This function reverses the effect of mxs_dma_freeze(), enabling the DMA + * channel to continue from where it was frozen. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ + +extern void mxs_dma_unfreeze(int channel); + +/* get dma channel information */ +extern int mxs_dma_get_info(int channel, struct mxs_dma_info *info); + +/** + * mxs_dma_cooked - Clean up processed DMA descriptors. + * + * This function removes processed DMA descriptors from the "active" list. Pass + * in a non-NULL list head to get the descriptors moved to your list. Pass NULL + * to get the descriptors moved to the channel's "done" list. Descriptors on + * the "done" list can be retrieved with mxs_dma_get_cooked(). + * + * This function marks the DMA channel as "not busy" if no unprocessed + * descriptors remain on the "active" list. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: If this is not NULL, it is the list to which the processed + * descriptors should be moved. If this list is NULL, the descriptors + * will be moved to the "done" list. + */ +extern int mxs_dma_cooked(int channel, struct list_head *head); + +/** + * mxs_dma_read_semaphore - Read a DMA channel's hardware semaphore. + * + * As used by the MXS platform's DMA software, the DMA channel's hardware + * semaphore reflects the number of DMA commands the hardware will process, but + * has not yet finished. This is a volatile value read directly from hardware, + * so it must be be viewed as immediately stale. + * + * If the channel is not marked busy, or has finished processing all its + * commands, this value should be zero. + * + * See mxs_dma_append() for details on how DMA command blocks must be configured + * to maintain the expected behavior of the semaphore's value. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_read_semaphore(int channel); + +/** + * mxs_dma_irq_is_pending - Check if a DMA interrupt is pending. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_irq_is_pending(int channel); + +/** + * mxs_dma_enable_irq - Enable or disable DMA interrupt. + * + * This function enables the given DMA channel to interrupt the CPU. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @en: True if the interrupt for this channel should be enabled. False + * otherwise. + */ +extern void mxs_dma_enable_irq(int channel, int en); + +/** + * mxs_dma_ack_irq - Clear DMA interrupt. + * + * The software that is using the DMA channel must register to receive its + * interrupts and, when they arrive, must call this function to clear them. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_ack_irq(int channel); + +/** + * mxs_dma_set_target - Set the target for a DMA channel. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @target: Indicates the target for the channel. + */ +extern void mxs_dma_set_target(int channel, int target); + +/* mxs dma utility functions */ +extern struct mxs_dma_desc *mxs_dma_alloc_desc(void); +extern void mxs_dma_free_desc(struct mxs_dma_desc *); + +/** + * mxs_dma_cmd_address - Return the address of the command within a descriptor. + * + * @desc: The DMA descriptor of interest. + */ +static inline unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc) +{ + return desc->address += offsetof(struct mxs_dma_desc, cmd); +} + +/** + * mxs_dma_desc_pending - Check if descriptor is on a channel's active list. + * + * This function returns the state of a descriptor's "ready" flag. This flag is + * usually set only if the descriptor appears on a channel's active list. The + * descriptor may or may not have already been processed by the hardware. + * + * The "ready" flag is set when the descriptor is submitted to a channel by a + * call to mxs_dma_append() or mxs_dma_append_list(). The "ready" flag is + * cleared when a processed descriptor is moved off the active list by a call + * to mxs_dma_cooked(). The "ready" flag is NOT cleared if the descriptor is + * aborted by a call to mxs_dma_disable(). + * + * @desc: The DMA descriptor of interest. + */ +static inline int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc) +{ + return pdesc->flags & MXS_DMA_DESC_READY; +} + +/** + * mxs_dma_desc_append - Add a DMA descriptor to a channel. + * + * If the descriptor list for this channel is not empty, this function sets the + * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so + * it will chain to the new descriptor's command. + * + * Then, this function marks the new descriptor as "ready," adds it to the end + * of the active descriptor list, and increments the count of pending + * descriptors. + * + * The MXS platform DMA software imposes some rules on DMA commands to maintain + * important invariants. These rules are NOT checked, but they must be carefully + * applied by software that uses MXS DMA channels. + * + * Invariant: + * The DMA channel's hardware semaphore must reflect the number of DMA + * commands the hardware will process, but has not yet finished. + * + * Explanation: + * A DMA channel begins processing commands when its hardware semaphore is + * written with a value greater than zero, and it stops processing commands + * when the semaphore returns to zero. + * + * When a channel finishes a DMA command, it will decrement its semaphore if + * the DECREMENT_SEMAPHORE bit is set in that command's flags bits. + * + * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set, + * unless it suits the purposes of the software. For example, one could + * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE + * bit set only in the last one. Then, setting the DMA channel's hardware + * semaphore to one would cause the entire series of five commands to be + * processed. However, this example would violate the invariant given above. + * + * Rule: + * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA + * channel's hardware semaphore will be decremented EVERY time a command is + * processed. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @pdesc: A pointer to the new descriptor. + */ +extern int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); + +/** + * mxs_dma_desc_add_list - Add a list of DMA descriptors to a channel. + * + * This function marks all the new descriptors as "ready," adds them to the end + * of the active descriptor list, and adds the length of the list to the count + * of pending descriptors. + * + * See mxs_dma_desc_append() for important rules that apply to incoming DMA + * descriptors. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: A pointer to the head of the list of DMA descriptors to add. + */ +extern int mxs_dma_desc_add_list(int channel, struct list_head *head); + +/** + * mxs_dma_desc_get_cooked - Retrieve processed DMA descriptors. + * + * This function moves all the descriptors from the DMA channel's "done" list to + * the head of the given list. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: A pointer to the head of the list that will receive the + * descriptors on the "done" list. + */ +extern int mxs_dma_get_cooked(int channel, struct list_head *head); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h new file mode 100644 index 000000000000..2e1785add1ca --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h @@ -0,0 +1,575 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX50_H__ +#define __MACH_IOMUX_MX50_H__ + +#include + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +#define NON_MUX_I 0x3FF +#define NON_PAD_I 0x7FF + +#define IOMUX_TO_IRQ_V3(pin) (MXC_GPIO_IRQ_START + pin) + +#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH) + +#define MX50_WVGA_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH) + +#define MX50_SD_PAD_CTRL (PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST) + +#define MX50_SD3_PAD_DAT (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) +#define MX50_SD3_PAD_CMD (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) +#define MX50_SD3_PAD_CLK (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) +#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE) +#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) +#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) + +#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH) + +#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) + +#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) + +/* HP detect */ +#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, \ + PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, \ + PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL) + + +/* SD1 */ +#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) + +/* SD2 */ +#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) + +/* SD3 */ +#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, \ + MX50_SD3_PAD_CMD) +#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, \ + MX50_SD3_PAD_CLK) +#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) + +/* OWIRE */ +#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, \ + MX50_OWIRE_PAD_CTRL) + +/* SSI */ +#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, \ + NO_PAD_CTRL) + +/* UART1 and UART2 */ +#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, \ + MX50_UART_PAD_CTRL) + +/* I2C1, I2C2, I2C3 */ +#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) + +/* EPDC */ +#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, \ + 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) + +/* USB */ +#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, \ + MX50_USB_PAD_CTRL) +#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, \ + MX50_USB_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, \ + MX50_USB_PAD_CTRL) + + +/* FEC */ +#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, \ + MX50_FEC_PAD_CTRL) +#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x0, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, \ + PAD_CTL_DSE_HIGH) + +/* WVGA */ +#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x0, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x0, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x0, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x0, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x0, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x0, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x0, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x0, 0, \ + MX50_WVGA_PAD_CTRL) + +/* CSPI */ +#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, \ + NO_PAD_CTRL) + +/* NAND */ +#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, \ + PAD_CTL_PKE | \ + PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP) +#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) + +/* Keypad */ +#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, \ + NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX53_H__ */ + diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h new file mode 100644 index 000000000000..0125534a4f34 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -0,0 +1,416 @@ +/* + * Copyright (C) 2009-2010 Amit Kucheria + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MACH_IOMUX_MX51_H__ +#define __MACH_IOMUX_MX51_H__ + +#include + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +#define IOMUX_TO_IRQ_V3(pin) (MXC_GPIO_IRQ_START + pin) + +/* Pad control groupings */ +#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH) +#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) +#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ + PAD_CTL_SRE_FAST) + +#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE) +#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE) +#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + +#define MX51_PAD_CTRL_6 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_DVS) +#define MX51_PAD_CTRL_7 MX51_UART2_PAD_CTRL +#define MX51_PAD_CTRL_8 (PAD_CTL_HYS | PAD_CTL_PKE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH) +#define MX51_PAD_CTRL_9 (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_10 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_11 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define MX51_PAD_CTRL_12 (PAD_CTL_PKE | PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) +#define MX51_PAD_CTRL_13 (PAD_CTL_PKE | PAD_CTL_PUE) + +#define MX51_SDHC_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) + + + +/* + * The naming convention for the pad modes is MX51_PAD___ + * If or refers to a GPIO, it is named + * GPIO__ see also iomux-v3.h + */ + +/* PAD MUX ALT INPSE PATH PADCTRL */ +/* EIM */ +#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, \ + 0x9b4, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, \ + 0x9b0, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, MX51_PAD_CTRL_7) + +/* UART3 */ +#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL) + +#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, PAD_CTL_PKE) +#define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, MX51_PAD_CTRL_3) + +#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12C, 1, 0x0, 0, MX51_PAD_CTRL_2) + +#define MX51_PAD_NANDF_RB5__GPIO_3_13 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) + +/* FEC */ +#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) +#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) +#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) + +#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, PAD_CTL_SRE_SLOW) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, PAD_CTL_SRE_SLOW) +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, MX51_PAD_CTRL_7) +#define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, MX51_PAD_CTRL_7) +#define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, MX51_PAD_CTRL_12) +#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_PAD_CTRL_8) +#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, \ + IOMUX_CONFIG_SION, \ + 0x0, 0, MX51_PAD_CTRL_8) + +/* Audio */ +#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 0, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 0, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 0, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 0, 0x0, 0, MX51_PAD_CTRL_10) + +/* CSPI */ +#define MX51_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_PAD_CTRL_11) +#define MX51_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_PAD_CTRL_11) + +#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) + +/* UART1 */ +#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) +#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) +#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL) +#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL) + +/* UART2 */ +#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL) +#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL) + +#define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, MX51_PAD_CTRL_1) +#define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_OWIRE_LINE__SPDIF_OUT1 IOMUX_PAD(0x638, 0x248, 6, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0, 0, MX51_I2C_PAD_CTRL | MX51_PAD_CTRL_13) +#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) + +/* I2C2 */ +#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION, \ + 0x09b8, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION, \ + 0x9bc, 1, MX51_I2C_PAD_CTRL) + +#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, MX51_PAD_CTRL_7) +#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, MX51_PAD_CTRL_7) +#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33C, 3, 0x9a0, 1, MX51_PAD_CTRL_7) +#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) + +/* SD1 */ +#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) + +/* SD2 */ +#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1 | IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) + +#define MX51_PAD_GPIO_1_2__PWM_PWMO IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, 2 | IOMUX_CONFIG_SION, 0x9bc, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, IOMUX_CONFIG_SION, 0x0 , 1, MX51_PAD_CTRL_6) +#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h new file mode 100644 index 000000000000..ed2460a40815 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -0,0 +1,579 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX53_H__ +#define __MACH_IOMUX_MX53_H__ + +#include + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +#define IOMUX_TO_IRQ_V3(pin) (MXC_GPIO_IRQ_START + pin) + +#define NON_MUX_I 0x3FF +#define NON_PAD_I 0x7FF + +#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define MX53_SDHC_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define MX53_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | PAD_CTL_DSE_HIGH) +#define MX53_ESAI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE |\ + PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define PAD_CTRL_1 (PAD_CTL_HYS | PAD_CTL_DSE_HIGH) +#define PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH) +#define PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_HYS) +#define PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) +#define PAD_CTRL_5 (PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) + +#define PAD_CTRL_6 (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) +#define PAD_CTRL_7 (PAD_CTL_DSE_HIGH | PAD_CTL_SRE_SLOW) +#define PAD_CTRL_8 (PAD_CTL_HYS | PAD_CTL_PKE) + +#define PAD_CTRL_9 (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) + +#define PAD_CTRL_10 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) + +#define PAD_CTRL_11 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) + +#define PAD_CTRL_12 (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) + + +#define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, \ + PAD_CTRL_9 | PAD_CTRL_2) +#define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) + +/* NAND */ +#define MX53_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, PAD_CTRL_11) +#define MX53_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, PAD_CTRL_11) +#define MX53_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, PAD_CTRL_10) + +/* SPI */ +#define MX53_PAD_EIM_EB2__CSPI_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, PAD_CTRL_1) +#define MX53_PAD_EIM_D19__CSPI_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 3, PAD_CTRL_1) + +/* PWM */ +#define MX53_PAD_GPIO_1__PWMO IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, NO_PAD_CTRL) + +/* Camera */ +#define MX53_PAD_CSI0_VSYNC__CSI0_VSYNC IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__CSI0_HSYNC IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, NO_PAD_CTRL) + +/* IPU */ +#define MX53_PAD_CSI0_D12__CSI0_D12 IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D13__CSI0_D13 IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D14__CSI0_D14 IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D15__CSI0_D15 IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D16__CSI0_D16 IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D17__CSI0_D17 IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D18__CSI0_D18 IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D19__CSI0_D19 IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x0, 0, NO_PAD_CTRL) + +/* Display */ +#define MX53_PAD_DI0_DISP_CLK__DI0_DISP_CLK IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, PAD_CTRL_5) +#define MX53_PAD_DI0_PIN15__DI0_PIN15 IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, PAD_CTRL_5) +#define MX53_PAD_DI0_PIN2__DI0_PIN2 IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DI0_PIN3__DI0_PIN3 IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT0__DISP0_DAT0 IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT1__DISP0_DAT1 IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT2__DISP0_DAT2 IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT3__DISP0_DAT3 IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT4__DISP0_DAT4 IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT5__DISP0_DAT5 IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT6__DISP0_DAT6 IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT7__DISP0_DAT7 IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT8__DISP0_DAT8 IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT9__DISP0_DAT9 IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT10__DISP0_DAT10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT11__DISP0_DAT11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT12__DISP0_DAT12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT13__DISP0_DAT13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT14__DISP0_DAT14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT15__DISP0_DAT15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT16__DISP0_DAT16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT17__DISP0_DAT17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT18__DISP0_DAT18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT19__DISP0_DAT19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT20__DISP0_DAT20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT21__DISP0_DAT21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT22__DISP0_DAT22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT23__DISP0_DAT23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, PAD_CTRL_7) + +/* CAN*/ +#define MX53_PAD_KEY_COL2__TXCAN1 IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_KEY_ROW2__RXCAN1 IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, PAD_CTRL_3) +#define MX53_PAD_KEY_COL4__TXCAN2 IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_KEY_ROW4__RXCAN2 IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, PAD_CTRL_3) + +/* AUD5 */ +#define MX53_PAD_KEY_COL0__AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__AUD5_TXD IOMUX_PAD(0x350, 0x28, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__AUD5_TXFS IOMUX_PAD(0x354, 0x2C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__AUD5_RXD IOMUX_PAD(0x358, 0x30, 2, 0x0, 0, NO_PAD_CTRL) + +/* I2C1 */ +#define MX53_PAD_CSI0_D8__I2C1_SDA IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, PAD_CTRL_9) +#define MX53_PAD_CSI0_D9__I2C1_SCL IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, PAD_CTRL_9) + +/* I2C2 */ +#define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, PAD_CTRL_9) +#define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, PAD_CTRL_9) + +/* UART1 */ +#define MX53_PAD_CSI0_D10__UART1_TXD IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_D11__UART1_RXD IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL) + +/* UART2 */ +#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DMARQ__UART2_TXD IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, NO_PAD_CTRL) + +/* UART3 */ +#define MX53_PAD_ATA_CS_0__UART3_TXD IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) + +/* CSPI */ +#define MX53_PAD_EIM_D16__CSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, PAD_CTRL_1) +#define MX53_PAD_EIM_D17__CSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, PAD_CTRL_1) +#define MX53_PAD_EIM_D18__CSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, PAD_CTRL_1) + +/* LVDS0 */ +#define MX53_PAD_LVDS0_TX3_P__LVDS0_TX3 IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__LVDS0_CLK IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__LVDS0_TX2 IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__LVDS0_TX1 IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__LVDS0_TX0 IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, NO_PAD_CTRL) + +/* LVDS1 */ +#define MX53_PAD_LVDS1_TX3_P__LVDS1_TX3 IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__LVDS1_TX2 IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__LVDS1_CLK IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__LVDS1_TX1 IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__LVDS1_TX0 IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) + +/* SD1 */ +#define MX53_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x674, 0x2EC, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x67C, 0x2F4, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX53_SDHC_PAD_CTRL | PAD_CTL_HYS) +#define MX53_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) + +/* SD2 */ +#define MX53_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__SD2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__SD2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__SD2_DAT2 IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__SD2_DAT3 IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA12__SD2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA13__SD2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA14__SD2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA15__SD2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, NO_PAD_CTRL) + +/* SD3 */ +#define MX53_PAD_ATA_DATA8__SD3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA9__SD3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA10__SD3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA11__SD3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA0__SD3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA1__SD3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA2__SD3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA3__SD3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_RESET_B__SD3_CMD IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_IORDY__SD3_CLK IOMUX_PAD(0x60C, 0x28C, 2, \ + 0x0, 0, MX53_SDHC_PAD_CTRL | PAD_CTL_HYS) + +/* USB */ +#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) + +/* FEC */ +#define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, MX53_FEC_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__FEC_REF_CLK IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_CRS_DV__FEC_CRS_DV IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_RXD1__FEC_RXD1 IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_RXD0__FEC_RXD0 IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_FEC_TXD1__FEC_TXD1 IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_FEC_TXD0__FEC_TXD0 IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX53_PAD_GPIO_0__SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, NO_PAD_CTRL) + +/* MLB */ +#define MX53_PAD_GPIO_2__MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, \ + PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) +#define MX53_PAD_GPIO_3__MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, \ + PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) +#define MX53_PAD_GPIO_6__MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, \ + PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) + +/* SPDIF */ +#define MX53_PAD_GPIO_19__SPDIF_TX1 IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, \ + PAD_CTRL_3 | PAD_CTL_PUS_100K_UP) + +/* ESAI */ +#define MX53_PAD_FEC_MDIO__ESAI_SCKR IOMUX_PAD(0x5C4, 0x248, 2, \ + 0x7DC, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__ESAI_FSR IOMUX_PAD(0x5C8, 0x24C, 2, \ + 0x7CC, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__ESAI_HCKR IOMUX_PAD(0x5CC, 0x250, 2, \ + 0x7D4, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__ESAI_SCKT IOMUX_PAD(0x5D0, 0x254, 2, \ + 0x7E0, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__ESAI_FST IOMUX_PAD(0x5D4, 0x258, 2, \ + 0x7D0, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__ESAI_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, \ + 0x7D8, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__ESAI_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, \ + 0x7F0, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__ESAI_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, \ + 0x7EC, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__ESAI_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, \ + 0x7F4, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_MDC__ESAI_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, \ + 0x7F8, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__ESAI_TX0 IOMUX_PAD(0x5B8, 0x240, 3, \ + 0x7E4, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__ESAI_TX1 IOMUX_PAD(0x5BC, 0x244, 3, \ + 0x7E8, 0, MX53_ESAI_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX53_H__ */ diff --git a/arch/arm/plat-mxs/include/mach/unique-id.h b/arch/arm/plat-mxs/include/mach/unique-id.h new file mode 100644 index 000000000000..de5e04342ef5 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/unique-id.h @@ -0,0 +1,30 @@ +/* + * Unique ID interface for ID storage providers + * + * Embedded Alley Solutions, Inc + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __UNIQUE_ID_H +#define __UNIQUE_ID_H + +struct uid_ops { + ssize_t (*id_show)(void *context, char *page, int ascii); + ssize_t (*id_store)(void *context, const char *page, + size_t count, int ascii); +}; + +struct kobject *uid_provider_init(const char *name, + struct uid_ops *ops, void *context); +void uid_provider_remove(const char *name); +#endif diff --git a/arch/arm/plat-mxs/unique-id.c b/arch/arm/plat-mxs/unique-id.c new file mode 100644 index 000000000000..35c0fcdab605 --- /dev/null +++ b/arch/arm/plat-mxs/unique-id.c @@ -0,0 +1,198 @@ +/* + * Unique ID manipulation sysfs access generic functions + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static int unlock; +static spinlock_t u_lock; +static const unsigned long UID_AUTOLOCK_TIMEOUT = HZ * 60 * 3; +static struct timer_list u_timer; + +static void uid_timer_autolock(unsigned long param) +{ + struct timer_list *tmr = (struct timer_list *)param; + + if (spin_trylock(&u_lock)) { + if (unlock) + pr_debug("%s: locked down.\n", __func__); + unlock = 0; + spin_unlock(&u_lock); + } + mod_timer(tmr, jiffies + UID_AUTOLOCK_TIMEOUT); +} + +static LIST_HEAD(uid_provider_list); + +struct uid_provider { + struct kobject *kobj; + struct list_head list; + struct uid_ops *ops; + void *context; +}; + +static struct uid_provider *uid_provider_find(const char *name); + +#define UID_FWD_SYSFS_FILE(var, file, param) \ + static ssize_t var##_show(struct kobject *kobj, \ + struct kobj_attribute *attr, char *buf) \ + { \ + struct uid_provider *p = \ + uid_provider_find(kobject_name(kobj)); \ + ssize_t r; \ + BUG_ON(p == NULL); \ + r = (p->ops && p->ops->file##_show) ? \ + p->ops->file##_show(p->context, buf, param) : 0;\ + return r; \ + } \ + \ + static ssize_t var##_store(struct kobject *kobj, \ + struct kobj_attribute *attr, const char *buf, \ + size_t count) \ + { \ + struct uid_provider *p = \ + uid_provider_find(kobject_name(kobj)); \ + ssize_t r; \ + int ul; \ + BUG_ON(p == NULL); \ + spin_lock(&u_lock); \ + ul = unlock; \ + spin_unlock(&u_lock); \ + if (ul) \ + r = (p->ops && p->ops->file##_store) ? \ + p->ops->file##_store(p->context, buf, count, param) \ + : count; \ + else \ + r = -EACCES; \ + return r; \ + } + +struct kobject *uid_kobj; + +#define UID_ATTR(_name, _varname) \ + static struct kobj_attribute _varname##_attr = \ + __ATTR(_name, 0644, _varname##_show, _varname##_store) + +UID_FWD_SYSFS_FILE(id, id, 1); +UID_FWD_SYSFS_FILE(id_bin, id, 0); +UID_ATTR(id, id); +UID_ATTR(id.bin, id_bin); + +static struct attribute *uid_attrs[] = { + &id_attr.attr, + &id_bin_attr.attr, + NULL +}; + +static struct attribute_group uid_attr_group = { + .attrs = uid_attrs, +}; + +struct kobject *uid_provider_init(const char *name, + struct uid_ops *ops, void *context) +{ + struct uid_provider *new; + int err; + + new = kzalloc(sizeof(*new), GFP_KERNEL); + if (!new) { + err = -ENOMEM; + goto out; + } + + new->kobj = kobject_create_and_add(name, uid_kobj); + if (!new->kobj) { + err = -ENOMEM; + goto out; + } + new->ops = ops; + new->context = context; + + err = sysfs_create_group(new->kobj, &uid_attr_group); + if (err) + goto out2; + + list_add_tail(&new->list, &uid_provider_list); + return new->kobj; +out2: + kobject_del(new->kobj); +out: + kfree(new); + return ERR_PTR(err); +} +EXPORT_SYMBOL_GPL(uid_provider_init); + +static struct uid_provider *uid_provider_find(const char *name) +{ + struct uid_provider *p; + + list_for_each_entry(p, &uid_provider_list, list) { + if (strcmp(kobject_name(p->kobj), name) == 0) + return p; + } + return NULL; +} + +void uid_provider_remove(const char *name) +{ + struct uid_provider *p; + + p = uid_provider_find(name); + if (!p) + return; + kobject_del(p->kobj); + list_del(&p->list); + kfree(p); +} +EXPORT_SYMBOL_GPL(uid_provider_remove); + +static int uid_sysfs_init(void) +{ + int error; + + uid_kobj = kobject_create_and_add("uid", NULL); + if (!uid_kobj) { + error = -ENOMEM; + goto out1; + } + + spin_lock_init(&u_lock); + setup_timer(&u_timer, uid_timer_autolock, (unsigned long)&u_timer); + + /* try to lock each 3 minutes */ + mod_timer(&u_timer, jiffies + UID_AUTOLOCK_TIMEOUT); + return 0; + +out1: + printk(KERN_ERR"%s failed, error %d.", __func__, error); + return error; +} + +module_param(unlock, int, 0600) +core_initcall(uid_sysfs_init); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("dmitry pervushin "); +MODULE_DESCRIPTION("Unique ID simple framework"); diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h new file mode 100644 index 000000000000..111a878d9188 --- /dev/null +++ b/drivers/ata/ahci.h @@ -0,0 +1,332 @@ +/* + * ahci.h - Common AHCI SATA definitions and declarations + * + * Maintained by: Jeff Garzik + * Please ALWAYS copy linux-ide@vger.kernel.org + * on emails. + * + * Copyright 2004-2005 Red Hat, Inc. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * libata documentation is available via 'make {ps|pdf}docs', + * as Documentation/DocBook/libata.* + * + * AHCI hardware documentation: + * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf + * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf + * + */ + +#ifndef _AHCI_H +#define _AHCI_H + +#include + +/* Enclosure Management Control */ +#define EM_CTRL_MSG_TYPE 0x000f0000 + +/* Enclosure Management LED Message Type */ +#define EM_MSG_LED_HBA_PORT 0x0000000f +#define EM_MSG_LED_PMP_SLOT 0x0000ff00 +#define EM_MSG_LED_VALUE 0xffff0000 +#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 +#define EM_MSG_LED_VALUE_OFF 0xfff80000 +#define EM_MSG_LED_VALUE_ON 0x00010000 + +enum { + AHCI_MAX_PORTS = 32, + AHCI_MAX_SG = 168, /* hardware max is 64K */ + AHCI_DMA_BOUNDARY = 0xffffffff, + AHCI_MAX_CMDS = 32, + AHCI_CMD_SZ = 32, + AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, + AHCI_RX_FIS_SZ = 256, + AHCI_CMD_TBL_CDB = 0x40, + AHCI_CMD_TBL_HDR_SZ = 0x80, + AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), + AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, + AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + + AHCI_RX_FIS_SZ, + AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + + AHCI_CMD_TBL_AR_SZ + + (AHCI_RX_FIS_SZ * 16), + AHCI_IRQ_ON_SG = (1 << 31), + AHCI_CMD_ATAPI = (1 << 5), + AHCI_CMD_WRITE = (1 << 6), + AHCI_CMD_PREFETCH = (1 << 7), + AHCI_CMD_RESET = (1 << 8), + AHCI_CMD_CLR_BUSY = (1 << 10), + + RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ + RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ + RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ + + /* global controller registers */ + HOST_CAP = 0x00, /* host capabilities */ + HOST_CTL = 0x04, /* global host control */ + HOST_IRQ_STAT = 0x08, /* interrupt status */ + HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ + HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ + HOST_EM_LOC = 0x1c, /* Enclosure Management location */ + HOST_EM_CTL = 0x20, /* Enclosure Management Control */ + HOST_CAP2 = 0x24, /* host capabilities, extended */ + + /* HOST_CTL bits */ + HOST_RESET = (1 << 0), /* reset controller; self-clear */ + HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ + HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ + + /* HOST_CAP bits */ + HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ + HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ + HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ + HOST_CAP_PART = (1 << 13), /* Partial state capable */ + HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ + HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ + HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ + HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ + HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ + HOST_CAP_CLO = (1 << 24), /* Command List Override support */ + HOST_CAP_LED = (1 << 25), /* Supports activity LED */ + HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ + HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ + HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ + HOST_CAP_SNTF = (1 << 29), /* SNotification register */ + HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ + HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ + + /* HOST_CAP2 bits */ + HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ + HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ + HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ + + /* registers for each SATA port */ + PORT_LST_ADDR = 0x00, /* command list DMA addr */ + PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ + PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ + PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ + PORT_IRQ_STAT = 0x10, /* interrupt status */ + PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ + PORT_CMD = 0x18, /* port command */ + PORT_TFDATA = 0x20, /* taskfile data */ + PORT_SIG = 0x24, /* device TF signature */ + PORT_CMD_ISSUE = 0x38, /* command issue */ + PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ + PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ + PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ + PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ + PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ + PORT_FBS = 0x40, /* FIS-based Switching */ + + /* PORT_IRQ_{STAT,MASK} bits */ + PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ + PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ + PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ + PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ + PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ + PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ + PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ + PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ + + PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ + PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ + PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ + PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ + PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ + PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ + PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ + PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ + PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ + + PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | + PORT_IRQ_IF_ERR | + PORT_IRQ_CONNECT | + PORT_IRQ_PHYRDY | + PORT_IRQ_UNK_FIS | + PORT_IRQ_BAD_PMP, + PORT_IRQ_ERROR = PORT_IRQ_FREEZE | + PORT_IRQ_TF_ERR | + PORT_IRQ_HBUS_DATA_ERR, + DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | + PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | + PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, + + /* PORT_CMD bits */ + PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ + PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ + PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ + PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ + PORT_CMD_PMP = (1 << 17), /* PMP attached */ + PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ + PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ + PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ + PORT_CMD_CLO = (1 << 3), /* Command list override */ + PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ + PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ + PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ + + PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ + PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ + PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ + PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ + + PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ + PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ + PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ + PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ + PORT_FBS_SDE = (1 << 2), /* FBS single device error */ + PORT_FBS_DEC = (1 << 1), /* FBS device error clear */ + PORT_FBS_EN = (1 << 0), /* Enable FBS */ + + /* hpriv->flags bits */ + AHCI_HFLAG_NO_NCQ = (1 << 0), + AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ + AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ + AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ + AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ + AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ + AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ + AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ + AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ + AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ + AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ + AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as + link offline */ + AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */ + + /* ap->flags bits */ + + AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | + ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | + ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | + ATA_FLAG_IPM, + + ICH_MAP = 0x90, /* ICH MAP register */ + + /* em constants */ + EM_MAX_SLOTS = 8, + EM_MAX_RETRY = 5, + + /* em_ctl bits */ + EM_CTL_RST = (1 << 9), /* Reset */ + EM_CTL_TM = (1 << 8), /* Transmit Message */ + EM_CTL_ALHD = (1 << 26), /* Activity LED */ +}; + +struct ahci_cmd_hdr { + __le32 opts; + __le32 status; + __le32 tbl_addr; + __le32 tbl_addr_hi; + __le32 reserved[4]; +}; + +struct ahci_sg { + __le32 addr; + __le32 addr_hi; + __le32 reserved; + __le32 flags_size; +}; + +struct ahci_em_priv { + enum sw_activity blink_policy; + struct timer_list timer; + unsigned long saved_activity; + unsigned long activity; + unsigned long led_state; +}; + +struct ahci_port_priv { + struct ata_link *active_link; + struct ahci_cmd_hdr *cmd_slot; + dma_addr_t cmd_slot_dma; + void *cmd_tbl; + dma_addr_t cmd_tbl_dma; + void *rx_fis; + dma_addr_t rx_fis_dma; + /* for NCQ spurious interrupt analysis */ + unsigned int ncq_saw_d2h:1; + unsigned int ncq_saw_dmas:1; + unsigned int ncq_saw_sdb:1; + u32 intr_mask; /* interrupts to enable */ + bool fbs_supported; /* set iff FBS is supported */ + bool fbs_enabled; /* set iff FBS is enabled */ + int fbs_last_dev; /* save FBS.DEV of last FIS */ + /* enclosure management info per PM slot */ + struct ahci_em_priv em_priv[EM_MAX_SLOTS]; +}; + +struct ahci_host_priv { + void __iomem * mmio; /* bus-independant mem map */ + unsigned int flags; /* AHCI_HFLAG_* */ + u32 cap; /* cap to use */ + u32 cap2; /* cap2 to use */ + u32 port_map; /* port map to use */ + u32 saved_cap; /* saved initial cap */ + u32 saved_cap2; /* saved initial cap2 */ + u32 saved_port_map; /* saved initial port_map */ + u32 em_loc; /* enclosure management location */ +}; + +extern int ahci_em_messages; +extern int ahci_ignore_sss; + +extern struct scsi_host_template ahci_sht; +extern struct ata_port_operations ahci_ops; + +void ahci_save_initial_config(struct device *dev, + struct ahci_host_priv *hpriv, + unsigned int force_port_map, + unsigned int mask_port_map); +void ahci_init_controller(struct ata_host *host); +int ahci_reset_controller(struct ata_host *host); + +int ahci_do_softreset(struct ata_link *link, unsigned int *class, + int pmp, unsigned long deadline, + int (*check_ready)(struct ata_link *link)); + +int ahci_stop_engine(struct ata_port *ap); +void ahci_start_engine(struct ata_port *ap); +int ahci_check_ready(struct ata_link *link); +int ahci_kick_engine(struct ata_port *ap); +void ahci_set_em_messages(struct ahci_host_priv *hpriv, + struct ata_port_info *pi); +int ahci_reset_em(struct ata_host *host); +irqreturn_t ahci_interrupt(int irq, void *dev_instance); +void ahci_print_info(struct ata_host *host, const char *scc_s); + +static inline void __iomem *__ahci_port_base(struct ata_host *host, + unsigned int port_no) +{ + struct ahci_host_priv *hpriv = host->private_data; + void __iomem *mmio = hpriv->mmio; + + return mmio + 0x100 + (port_no * 0x80); +} + +static inline void __iomem *ahci_port_base(struct ata_port *ap) +{ + return __ahci_port_base(ap->host, ap->port_no); +} + +static inline int ahci_nr_ports(u32 cap) +{ + return (cap & 0x1f) + 1; +} + +#endif /* _AHCI_H */ diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c new file mode 100644 index 000000000000..42cdd7363fad --- /dev/null +++ b/drivers/ata/ahci_platform.c @@ -0,0 +1,191 @@ +/* + * AHCI SATA platform driver + * + * Copyright 2004-2005 Red Hat, Inc. + * Jeff Garzik + * Copyright 2010 MontaVista Software, LLC. + * Anton Vorontsov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ahci.h" + +static int __init ahci_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ahci_platform_data *pdata = dev->platform_data; + struct ata_port_info pi = { + .flags = AHCI_FLAG_COMMON, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_ops, + }; + const struct ata_port_info *ppi[] = { &pi, NULL }; + struct ahci_host_priv *hpriv; + struct ata_host *host; + struct resource *mem; + int irq; + int n_ports; + int i; + int rc; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(dev, "no mmio space\n"); + return -EINVAL; + } + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) { + dev_err(dev, "no irq\n"); + return -EINVAL; + } + + if (pdata && pdata->init) { + rc = pdata->init(dev); + if (rc) + return rc; + } + + if (pdata && pdata->ata_port_info) + pi = *pdata->ata_port_info; + + hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); + if (!hpriv) { + rc = -ENOMEM; + goto err0; + } + + hpriv->flags |= (unsigned long)pi.private_data; + + hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem)); + if (!hpriv->mmio) { + dev_err(dev, "can't map %pR\n", mem); + rc = -ENOMEM; + goto err0; + } + + ahci_save_initial_config(dev, hpriv, + pdata ? pdata->force_port_map : 0, + pdata ? pdata->mask_port_map : 0); + + /* prepare host */ + if (hpriv->cap & HOST_CAP_NCQ) + pi.flags |= ATA_FLAG_NCQ; + + if (hpriv->cap & HOST_CAP_PMP) + pi.flags |= ATA_FLAG_PMP; + + ahci_set_em_messages(hpriv, &pi); + + /* CAP.NP sometimes indicate the index of the last enabled + * port, at other times, that of the last possible port, so + * determining the maximum port number requires looking at + * both CAP.NP and port_map. + */ + n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); + + host = ata_host_alloc_pinfo(dev, ppi, n_ports); + if (!host) { + rc = -ENOMEM; + goto err0; + } + + host->private_data = hpriv; + + if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) + host->flags |= ATA_HOST_PARALLEL_SCAN; + else + printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n"); + + if (pi.flags & ATA_FLAG_EM) + ahci_reset_em(host); + + for (i = 0; i < host->n_ports; i++) { + struct ata_port *ap = host->ports[i]; + + ata_port_desc(ap, "mmio %pR", mem); + ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80); + + /* set initial link pm policy */ + ap->pm_policy = NOT_AVAILABLE; + + /* set enclosure management message type */ + if (ap->flags & ATA_FLAG_EM) + ap->em_message_type = ahci_em_messages; + + /* disabled/not-implemented port */ + if (!(hpriv->port_map & (1 << i))) + ap->ops = &ata_dummy_port_ops; + } + + rc = ahci_reset_controller(host); + if (rc) + goto err0; + + ahci_init_controller(host); + ahci_print_info(host, "platform"); + + rc = ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED, + &ahci_sht); + if (rc) + goto err0; + + return 0; +err0: + if (pdata && pdata->exit) + pdata->exit(dev); + return rc; +} + +static int __devexit ahci_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ahci_platform_data *pdata = dev->platform_data; + struct ata_host *host = dev_get_drvdata(dev); + + ata_host_detach(host); + + if (pdata && pdata->exit) + pdata->exit(dev); + + return 0; +} + +static struct platform_driver ahci_driver = { + .probe = ahci_probe, + .remove = __devexit_p(ahci_remove), + .driver = { + .name = "ahci", + .owner = THIS_MODULE, + }, +}; + +static int __init ahci_init(void) +{ + return platform_driver_probe(&ahci_driver, ahci_probe); +} +module_init(ahci_init); + +static void __exit ahci_exit(void) +{ + platform_driver_unregister(&ahci_driver); +} +module_exit(ahci_exit); + +MODULE_DESCRIPTION("AHCI SATA platform driver"); +MODULE_AUTHOR("Anton Vorontsov "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:ahci"); diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c new file mode 100644 index 000000000000..38e1b4e9ecf4 --- /dev/null +++ b/drivers/ata/libahci.c @@ -0,0 +1,2091 @@ +/* + * libahci.c - Common AHCI SATA low-level routines + * + * Maintained by: Jeff Garzik + * Please ALWAYS copy linux-ide@vger.kernel.org + * on emails. + * + * Copyright 2004-2005 Red Hat, Inc. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * libata documentation is available via 'make {ps|pdf}docs', + * as Documentation/DocBook/libata.* + * + * AHCI hardware documentation: + * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf + * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ahci.h" + +static int ahci_skip_host_reset; +int ahci_ignore_sss; +EXPORT_SYMBOL_GPL(ahci_ignore_sss); + +module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); +MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); + +module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); +MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); + +static int ahci_enable_alpm(struct ata_port *ap, + enum link_pm policy); +static void ahci_disable_alpm(struct ata_port *ap); +static ssize_t ahci_led_show(struct ata_port *ap, char *buf); +static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, + size_t size); +static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, + ssize_t size); + + + +static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); +static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); +static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); +static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); +static int ahci_port_start(struct ata_port *ap); +static void ahci_port_stop(struct ata_port *ap); +static void ahci_qc_prep(struct ata_queued_cmd *qc); +static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); +static void ahci_freeze(struct ata_port *ap); +static void ahci_thaw(struct ata_port *ap); +static void ahci_enable_fbs(struct ata_port *ap); +static void ahci_disable_fbs(struct ata_port *ap); +static void ahci_pmp_attach(struct ata_port *ap); +static void ahci_pmp_detach(struct ata_port *ap); +static int ahci_softreset(struct ata_link *link, unsigned int *class, + unsigned long deadline); +static int ahci_hardreset(struct ata_link *link, unsigned int *class, + unsigned long deadline); +static void ahci_postreset(struct ata_link *link, unsigned int *class); +static void ahci_error_handler(struct ata_port *ap); +static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); +static int ahci_port_resume(struct ata_port *ap); +static void ahci_dev_config(struct ata_device *dev); +static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, + u32 opts); +#ifdef CONFIG_PM +static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); +#endif +static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); +static ssize_t ahci_activity_store(struct ata_device *dev, + enum sw_activity val); +static void ahci_init_sw_activity(struct ata_link *link); + +static ssize_t ahci_show_host_caps(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t ahci_show_host_cap2(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t ahci_show_host_version(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t ahci_show_port_cmd(struct device *dev, + struct device_attribute *attr, char *buf); + +static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); +static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); +static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); +static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); + +static struct device_attribute *ahci_shost_attrs[] = { + &dev_attr_link_power_management_policy, + &dev_attr_em_message_type, + &dev_attr_em_message, + &dev_attr_ahci_host_caps, + &dev_attr_ahci_host_cap2, + &dev_attr_ahci_host_version, + &dev_attr_ahci_port_cmd, + NULL +}; + +static struct device_attribute *ahci_sdev_attrs[] = { + &dev_attr_sw_activity, + &dev_attr_unload_heads, + NULL +}; + +struct scsi_host_template ahci_sht = { + ATA_NCQ_SHT("ahci"), + .can_queue = AHCI_MAX_CMDS - 1, + .sg_tablesize = AHCI_MAX_SG, + .dma_boundary = AHCI_DMA_BOUNDARY, + .shost_attrs = ahci_shost_attrs, + .sdev_attrs = ahci_sdev_attrs, +}; +EXPORT_SYMBOL_GPL(ahci_sht); + +struct ata_port_operations ahci_ops = { + .inherits = &sata_pmp_port_ops, + + .qc_defer = ahci_pmp_qc_defer, + .qc_prep = ahci_qc_prep, + .qc_issue = ahci_qc_issue, + .qc_fill_rtf = ahci_qc_fill_rtf, + + .freeze = ahci_freeze, + .thaw = ahci_thaw, + .softreset = ahci_softreset, + .hardreset = ahci_hardreset, + .postreset = ahci_postreset, + .pmp_softreset = ahci_softreset, + .error_handler = ahci_error_handler, + .post_internal_cmd = ahci_post_internal_cmd, + .dev_config = ahci_dev_config, + + .scr_read = ahci_scr_read, + .scr_write = ahci_scr_write, + .pmp_attach = ahci_pmp_attach, + .pmp_detach = ahci_pmp_detach, + + .enable_pm = ahci_enable_alpm, + .disable_pm = ahci_disable_alpm, + .em_show = ahci_led_show, + .em_store = ahci_led_store, + .sw_activity_show = ahci_activity_show, + .sw_activity_store = ahci_activity_store, +#ifdef CONFIG_PM + .port_suspend = ahci_port_suspend, + .port_resume = ahci_port_resume, +#endif + .port_start = ahci_port_start, + .port_stop = ahci_port_stop, +}; +EXPORT_SYMBOL_GPL(ahci_ops); + +int ahci_em_messages = 1; +EXPORT_SYMBOL_GPL(ahci_em_messages); +module_param(ahci_em_messages, int, 0444); +/* add other LED protocol types when they become supported */ +MODULE_PARM_DESC(ahci_em_messages, + "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED"); + +static void ahci_enable_ahci(void __iomem *mmio) +{ + int i; + u32 tmp; + + /* turn on AHCI_EN */ + tmp = readl(mmio + HOST_CTL); + if (tmp & HOST_AHCI_EN) + return; + + /* Some controllers need AHCI_EN to be written multiple times. + * Try a few times before giving up. + */ + for (i = 0; i < 5; i++) { + tmp |= HOST_AHCI_EN; + writel(tmp, mmio + HOST_CTL); + tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ + if (tmp & HOST_AHCI_EN) + return; + msleep(10); + } + + WARN_ON(1); +} + +static ssize_t ahci_show_host_caps(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct Scsi_Host *shost = class_to_shost(dev); + struct ata_port *ap = ata_shost_to_port(shost); + struct ahci_host_priv *hpriv = ap->host->private_data; + + return sprintf(buf, "%x\n", hpriv->cap); +} + +static ssize_t ahci_show_host_cap2(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct Scsi_Host *shost = class_to_shost(dev); + struct ata_port *ap = ata_shost_to_port(shost); + struct ahci_host_priv *hpriv = ap->host->private_data; + + return sprintf(buf, "%x\n", hpriv->cap2); +} + +static ssize_t ahci_show_host_version(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct Scsi_Host *shost = class_to_shost(dev); + struct ata_port *ap = ata_shost_to_port(shost); + struct ahci_host_priv *hpriv = ap->host->private_data; + void __iomem *mmio = hpriv->mmio; + + return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); +} + +static ssize_t ahci_show_port_cmd(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct Scsi_Host *shost = class_to_shost(dev); + struct ata_port *ap = ata_shost_to_port(shost); + void __iomem *port_mmio = ahci_port_base(ap); + + return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); +} + +/** + * ahci_save_initial_config - Save and fixup initial config values + * @dev: target AHCI device + * @hpriv: host private area to store config values + * @force_port_map: force port map to a specified value + * @mask_port_map: mask out particular bits from port map + * + * Some registers containing configuration info might be setup by + * BIOS and might be cleared on reset. This function saves the + * initial values of those registers into @hpriv such that they + * can be restored after controller reset. + * + * If inconsistent, config values are fixed up by this function. + * + * LOCKING: + * None. + */ +void ahci_save_initial_config(struct device *dev, + struct ahci_host_priv *hpriv, + unsigned int force_port_map, + unsigned int mask_port_map) +{ + void __iomem *mmio = hpriv->mmio; + u32 cap, cap2, vers, port_map; + int i; + + /* make sure AHCI mode is enabled before accessing CAP */ + ahci_enable_ahci(mmio); + + /* Values prefixed with saved_ are written back to host after + * reset. Values without are used for driver operation. + */ + hpriv->saved_cap = cap = readl(mmio + HOST_CAP); + hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); + + /* CAP2 register is only defined for AHCI 1.2 and later */ + vers = readl(mmio + HOST_VERSION); + if ((vers >> 16) > 1 || + ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) + hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); + else + hpriv->saved_cap2 = cap2 = 0; + + /* some chips have errata preventing 64bit use */ + if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { + dev_printk(KERN_INFO, dev, + "controller can't do 64bit DMA, forcing 32bit\n"); + cap &= ~HOST_CAP_64; + } + + if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { + dev_printk(KERN_INFO, dev, + "controller can't do NCQ, turning off CAP_NCQ\n"); + cap &= ~HOST_CAP_NCQ; + } + + if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { + dev_printk(KERN_INFO, dev, + "controller can do NCQ, turning on CAP_NCQ\n"); + cap |= HOST_CAP_NCQ; + } + + if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { + dev_printk(KERN_INFO, dev, + "controller can't do PMP, turning off CAP_PMP\n"); + cap &= ~HOST_CAP_PMP; + } + + if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { + dev_printk(KERN_INFO, dev, + "controller can't do SNTF, turning off CAP_SNTF\n"); + cap &= ~HOST_CAP_SNTF; + } + + if (force_port_map && port_map != force_port_map) { + dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n", + port_map, force_port_map); + port_map = force_port_map; + } + + if (mask_port_map) { + dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n", + port_map, + port_map & mask_port_map); + port_map &= mask_port_map; + } + + /* cross check port_map and cap.n_ports */ + if (port_map) { + int map_ports = 0; + + for (i = 0; i < AHCI_MAX_PORTS; i++) + if (port_map & (1 << i)) + map_ports++; + + /* If PI has more ports than n_ports, whine, clear + * port_map and let it be generated from n_ports. + */ + if (map_ports > ahci_nr_ports(cap)) { + dev_printk(KERN_WARNING, dev, + "implemented port map (0x%x) contains more " + "ports than nr_ports (%u), using nr_ports\n", + port_map, ahci_nr_ports(cap)); + port_map = 0; + } + } + + /* fabricate port_map from cap.nr_ports */ + if (!port_map) { + port_map = (1 << ahci_nr_ports(cap)) - 1; + dev_printk(KERN_WARNING, dev, + "forcing PORTS_IMPL to 0x%x\n", port_map); + + /* write the fixed up value to the PI register */ + hpriv->saved_port_map = port_map; + } + + /* record values to use during operation */ + hpriv->cap = cap; + hpriv->cap2 = cap2; + hpriv->port_map = port_map; +} +EXPORT_SYMBOL_GPL(ahci_save_initial_config); + +/** + * ahci_restore_initial_config - Restore initial config + * @host: target ATA host + * + * Restore initial config stored by ahci_save_initial_config(). + * + * LOCKING: + * None. + */ +static void ahci_restore_initial_config(struct ata_host *host) +{ + struct ahci_host_priv *hpriv = host->private_data; + void __iomem *mmio = hpriv->mmio; + + writel(hpriv->saved_cap, mmio + HOST_CAP); + if (hpriv->saved_cap2) + writel(hpriv->saved_cap2, mmio + HOST_CAP2); + writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); + (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ +} + +static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) +{ + static const int offset[] = { + [SCR_STATUS] = PORT_SCR_STAT, + [SCR_CONTROL] = PORT_SCR_CTL, + [SCR_ERROR] = PORT_SCR_ERR, + [SCR_ACTIVE] = PORT_SCR_ACT, + [SCR_NOTIFICATION] = PORT_SCR_NTF, + }; + struct ahci_host_priv *hpriv = ap->host->private_data; + + if (sc_reg < ARRAY_SIZE(offset) && + (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) + return offset[sc_reg]; + return 0; +} + +static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) +{ + void __iomem *port_mmio = ahci_port_base(link->ap); + int offset = ahci_scr_offset(link->ap, sc_reg); + + if (offset) { + *val = readl(port_mmio + offset); + return 0; + } + return -EINVAL; +} + +static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) +{ + void __iomem *port_mmio = ahci_port_base(link->ap); + int offset = ahci_scr_offset(link->ap, sc_reg); + + if (offset) { + writel(val, port_mmio + offset); + return 0; + } + return -EINVAL; +} + +void ahci_start_engine(struct ata_port *ap) +{ + void __iomem *port_mmio = ahci_port_base(ap); + u32 tmp; + + /* start DMA */ + tmp = readl(port_mmio + PORT_CMD); + tmp |= PORT_CMD_START; + writel(tmp, port_mmio + PORT_CMD); + readl(port_mmio + PORT_CMD); /* flush */ +} +EXPORT_SYMBOL_GPL(ahci_start_engine); + +int ahci_stop_engine(struct ata_port *ap) +{ + void __iomem *port_mmio = ahci_port_base(ap); + u32 tmp; + + tmp = readl(port_mmio + PORT_CMD); + + /* check if the HBA is idle */ + if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) + return 0; + + /* setting HBA to idle */ + tmp &= ~PORT_CMD_START; + writel(tmp, port_mmio + PORT_CMD); + + /* wait for engine to stop. This could be as long as 500 msec */ + tmp = ata_wait_register(port_mmio + PORT_CMD, + PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); + if (tmp & PORT_CMD_LIST_ON) + return -EIO; + + return 0; +} +EXPORT_SYMBOL_GPL(ahci_stop_engine); + +static void ahci_start_fis_rx(struct ata_port *ap) +{ + void __iomem *port_mmio = ahci_port_base(ap); + struct ahci_host_priv *hpriv = ap->host->private_data; + struct ahci_port_priv *pp = ap->private_data; + u32 tmp; + + /* set FIS registers */ + if (hpriv->cap & HOST_CAP_64) + writel((pp->cmd_slot_dma >> 16) >> 16, + port_mmio + PORT_LST_ADDR_HI); + writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); + + if (hpriv->cap & HOST_CAP_64) + writel((pp->rx_fis_dma >> 16) >> 16, + port_mmio + PORT_FIS_ADDR_HI); + writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); + + /* enable FIS reception */ + tmp = readl(port_mmio + PORT_CMD); + tmp |= PORT_CMD_FIS_RX; + writel(tmp, port_mmio + PORT_CMD); + + /* flush */ + readl(port_mmio + PORT_CMD); +} + +static int ahci_stop_fis_rx(struct ata_port *ap) +{ + void __iomem *port_mmio = ahci_port_base(ap); + u32 tmp; + + /* disable FIS reception */ + tmp = readl(port_mmio + PORT_CMD); + tmp &= ~PORT_CMD_FIS_RX; + writel(tmp, port_mmio + PORT_CMD); + + /* wait for completion, spec says 500ms, give it 1000 */ + tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, + PORT_CMD_FIS_ON, 10, 1000); + if (tmp & PORT_CMD_FIS_ON) + return -EBUSY; + + return 0; +} + +static void ahci_power_up(struct ata_port *ap) +{ + struct ahci_host_priv *hpriv = ap->host->private_data; + void __iomem *port_mmio = ahci_port_base(ap); + u32 cmd; + + cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; + + /* spin up device */ + if (hpriv->cap & HOST_CAP_SSS) { + cmd |= PORT_CMD_SPIN_UP; + writel(cmd, port_mmio + PORT_CMD); + } + + /* wake up link */ + writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); +} + +static void ahci_disable_alpm(struct ata_port *ap) +{ + struct ahci_host_priv *hpriv = ap->host->private_data; + void __iomem *port_mmio = ahci_port_base(ap); + u32 cmd; + struct ahci_port_priv *pp = ap->private_data; + + /* IPM bits should be disabled by libata-core */ + /* get the existing command bits */ + cmd = readl(port_mmio + PORT_CMD); + + /* disable ALPM and ASP */ + cmd &= ~PORT_CMD_ASP; + cmd &= ~PORT_CMD_ALPE; + + /* force the interface back to active */ + cmd |= PORT_CMD_ICC_ACTIVE; + + /* write out new cmd value */ + writel(cmd, port_mmio + PORT_CMD); + cmd = readl(port_mmio + PORT_CMD); + + /* wait 10ms to be sure we've come out of any low power state */ + msleep(10); + + /* clear out any PhyRdy stuff from interrupt status */ + writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); + + /* go ahead and clean out PhyRdy Change from Serror too */ + ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); + + /* + * Clear flag to indicate that we should ignore all PhyRdy + * state changes + */ + hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; + + /* + * Enable interrupts on Phy Ready. + */ + pp->intr_mask |= PORT_IRQ_PHYRDY; + writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); + + /* + * don't change the link pm policy - we can be called + * just to turn of link pm temporarily + */ +} + +static int ahci_enable_alpm(struct ata_port *ap, + enum link_pm policy) +{ + struct ahci_host_priv *hpriv = ap->host->private_data; + void __iomem *port_mmio = ahci_port_base(ap); + u32 cmd; + struct ahci_port_priv *pp = ap->private_data; + u32 asp; + + /* Make sure the host is capable of link power management */ + if (!(hpriv->cap & HOST_CAP_ALPM)) + return -EINVAL; + + switch (policy) { + case MAX_PERFORMANCE: + case NOT_AVAILABLE: + /* + * if we came here with NOT_AVAILABLE, + * it just means this is the first time we + * have tried to enable - default to max performance, + * and let the user go to lower power modes on request. + */ + ahci_disable_alpm(ap); + return 0; + case MIN_POWER: + /* configure HBA to enter SLUMBER */ + asp = PORT_CMD_ASP; + break; + case MEDIUM_POWER: + /* configure HBA to enter PARTIAL */ + asp = 0; + break; + default: + return -EINVAL; + } + + /* + * Disable interrupts on Phy Ready. This keeps us from + * getting woken up due to spurious phy ready interrupts + * TBD - Hot plug should be done via polling now, is + * that even supported? + */ + pp->intr_mask &= ~PORT_IRQ_PHYRDY; + writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); + + /* + * Set a flag to indicate that we should ignore all PhyRdy + * state changes since these can happen now whenever we + * change link state + */ + hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; + + /* get the existing command bits */ + cmd = readl(port_mmio + PORT_CMD); + + /* + * Set ASP based on Policy + */ + cmd |= asp; + + /* + * Setting this bit will instruct the HBA to aggressively + * enter a lower power link state when it's appropriate and + * based on the value set above for ASP + */ + cmd |= PORT_CMD_ALPE; + + /* write out new cmd value */ + writel(cmd, port_mmio + PORT_CMD); + cmd = readl(port_mmio + PORT_CMD); + + /* IPM bits should be set by libata-core */ + return 0; +} + +#ifdef CONFIG_PM +static void ahci_power_down(struct ata_port *ap) +{ + struct ahci_host_priv *hpriv = ap->host->private_data; + void __iomem *port_mmio = ahci_port_base(ap); + u32 cmd, scontrol; + + if (!(hpriv->cap & HOST_CAP_SSS)) + return; + + /* put device into listen mode, first set PxSCTL.DET to 0 */ + scontrol = readl(port_mmio + PORT_SCR_CTL); + scontrol &= ~0xf; + writel(scontrol, port_mmio + PORT_SCR_CTL); + + /* then set PxCMD.SUD to 0 */ + cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; + cmd &= ~PORT_CMD_SPIN_UP; + writel(cmd, port_mmio + PORT_CMD); +} +#endif + +static void ahci_start_port(struct ata_port *ap) +{ + struct ahci_port_priv *pp = ap->private_data; + struct ata_link *link; + struct ahci_em_priv *emp; + ssize_t rc; + int i; + + /* enable FIS reception */ + ahci_start_fis_rx(ap); + + /* enable DMA */ + ahci_start_engine(ap); + + /* turn on LEDs */ + if (ap->flags & ATA_FLAG_EM) { + ata_for_each_link(link, ap, EDGE) { + emp = &pp->em_priv[link->pmp]; + + /* EM Transmit bit maybe busy during init */ + for (i = 0; i < EM_MAX_RETRY; i++) { + rc = ahci_transmit_led_message(ap, + emp->led_state, + 4); + if (rc == -EBUSY) + msleep(1); + else + break; + } + } + } + + if (ap->flags & ATA_FLAG_SW_ACTIVITY) + ata_for_each_link(link, ap, EDGE) + ahci_init_sw_activity(link); + +} + +static int ahci_deinit_port(struct ata_port *ap, const char **emsg) +{ + int rc; + + /* disable DMA */ + rc = ahci_stop_engine(ap); + if (rc) { + *emsg = "failed to stop engine"; + return rc; + } + + /* disable FIS reception */ + rc = ahci_stop_fis_rx(ap); + if (rc) { + *emsg = "failed stop FIS RX"; + return rc; + } + + return 0; +} + +int ahci_reset_controller(struct ata_host *host) +{ + struct ahci_host_priv *hpriv = host->private_data; + void __iomem *mmio = hpriv->mmio; + u32 tmp; + + /* we must be in AHCI mode, before using anything + * AHCI-specific, such as HOST_RESET. + */ + ahci_enable_ahci(mmio); + + /* global controller reset */ + if (!ahci_skip_host_reset) { + tmp = readl(mmio + HOST_CTL); + if ((tmp & HOST_RESET) == 0) { + writel(tmp | HOST_RESET, mmio + HOST_CTL); + readl(mmio + HOST_CTL); /* flush */ + } + + /* + * to perform host reset, OS should set HOST_RESET + * and poll until this bit is read to be "0". + * reset must complete within 1 second, or + * the hardware should be considered fried. + */ + tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET, + HOST_RESET, 10, 1000); + + if (tmp & HOST_RESET) { + dev_printk(KERN_ERR, host->dev, + "controller reset failed (0x%x)\n", tmp); + return -EIO; + } + + /* turn on AHCI mode */ + ahci_enable_ahci(mmio); + + /* Some registers might be cleared on reset. Restore + * initial values. + */ + ahci_restore_initial_config(host); + } else + dev_printk(KERN_INFO, host->dev, + "skipping global host reset\n"); + + return 0; +} +EXPORT_SYMBOL_GPL(ahci_reset_controller); + +static void ahci_sw_activity(struct ata_link *link) +{ + struct ata_port *ap = link->ap; + struct ahci_port_priv *pp = ap->private_data; + struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; + + if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) + return; + + emp->activity++; + if (!timer_pending(&emp->timer)) + mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); +} + +static void ahci_sw_activity_blink(unsigned long arg) +{ + struct ata_link *link = (struct ata_link *)arg; + struct ata_port *ap = link->ap; + struct ahci_port_priv *pp = ap->private_data; + struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; + unsigned long led_message = emp->led_state; + u32 activity_led_state; + unsigned long flags; + + led_message &= EM_MSG_LED_VALUE; + led_message |= ap->port_no | (link->pmp << 8); + + /* check to see if we've had activity. If so, + * toggle state of LED and reset timer. If not, + * turn LED to desired idle state. + */ + spin_lock_irqsave(ap->lock, flags); + if (emp->saved_activity != emp->activity) { + emp->saved_activity = emp->activity; + /* get the current LED state */ + activity_led_state = led_message & EM_MSG_LED_VALUE_ON; + + if (activity_led_state) + activity_led_state = 0; + else + activity_led_state = 1; + + /* clear old state */ + led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; + + /* toggle state */ + led_message |= (activity_led_state << 16); + mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); + } else { + /* switch to idle */ + led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; + if (emp->blink_policy == BLINK_OFF) + led_message |= (1 << 16); + } + spin_unlock_irqrestore(ap->lock, flags); + ahci_transmit_led_message(ap, led_message, 4); +} + +static void ahci_init_sw_activity(struct ata_link *link) +{ + struct ata_port *ap = link->ap; + struct ahci_port_priv *pp = ap->private_data; + struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; + + /* init activity stats, setup timer */ + emp->saved_activity = emp->activity = 0; + setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); + + /* check our blink policy and set flag for link if it's enabled */ + if (emp->blink_policy) + link->flags |= ATA_LFLAG_SW_ACTIVITY; +} + +int ahci_reset_em(struct ata_host *host) +{ + struct ahci_host_priv *hpriv = host->private_data; + void __iomem *mmio = hpriv->mmio; + u32 em_ctl; + + em_ctl = readl(mmio + HOST_EM_CTL); + if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) + return -EINVAL; + + writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); + return 0; +} +EXPORT_SYMBOL_GPL(ahci_reset_em); + +static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, + ssize_t size) +{ + struct ahci_host_priv *hpriv = ap->host->private_data; + struct ahci_port_priv *pp = ap->private_data; + void __iomem *mmio = hpriv->mmio; + u32 em_ctl; + u32 message[] = {0, 0}; + unsigned long flags; + int pmp; + struct ahci_em_priv *emp; + + /* get the slot number from the message */ + pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; + if (pmp < EM_MAX_SLOTS) + emp = &pp->em_priv[pmp]; + else + return -EINVAL; + + spin_lock_irqsave(ap->lock, flags); + + /* + * if we are still busy transmitting a previous message, + * do not allow + */ + em_ctl = readl(mmio + HOST_EM_CTL); + if (em_ctl & EM_CTL_TM) { + spin_unlock_irqrestore(ap->lock, flags); + return -EBUSY; + } + + /* + * create message header - this is all zero except for + * the message size, which is 4 bytes. + */ + message[0] |= (4 << 8); + + /* ignore 0:4 of byte zero, fill in port info yourself */ + message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); + + /* write message to EM_LOC */ + writel(message[0], mmio + hpriv->em_loc); + writel(message[1], mmio + hpriv->em_loc+4); + + /* save off new led state for port/slot */ + emp->led_state = state; + + /* + * tell hardware to transmit the message + */ + writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); + + spin_unlock_irqrestore(ap->lock, flags); + return size; +} + +static ssize_t ahci_led_show(struct ata_port *ap, char *buf) +{ + struct ahci_port_priv *pp = ap->private_data; + struct ata_link *link; + struct ahci_em_priv *emp; + int rc = 0; + + ata_for_each_link(link, ap, EDGE) { + emp = &pp->em_priv[link->pmp]; + rc += sprintf(buf, "%lx\n", emp->led_state); + } + return rc; +} + +static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, + size_t size) +{ + int state; + int pmp; + struct ahci_port_priv *pp = ap->private_data; + struct ahci_em_priv *emp; + + state = simple_strtoul(buf, NULL, 0); + + /* get the slot number from the message */ + pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; + if (pmp < EM_MAX_SLOTS) + emp = &pp->em_priv[pmp]; + else + return -EINVAL; + + /* mask off the activity bits if we are in sw_activity + * mode, user should turn off sw_activity before setting + * activity led through em_message + */ + if (emp->blink_policy) + state &= ~EM_MSG_LED_VALUE_ACTIVITY; + + return ahci_transmit_led_message(ap, state, size); +} + +static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) +{ + struct ata_link *link = dev->link; + struct ata_port *ap = link->ap; + struct ahci_port_priv *pp = ap->private_data; + struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; + u32 port_led_state = emp->led_state; + + /* save the desired Activity LED behavior */ + if (val == OFF) { + /* clear LFLAG */ + link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); + + /* set the LED to OFF */ + port_led_state &= EM_MSG_LED_VALUE_OFF; + port_led_state |= (ap->port_no | (link->pmp << 8)); + ahci_transmit_led_message(ap, port_led_state, 4); + } else { + link->flags |= ATA_LFLAG_SW_ACTIVITY; + if (val == BLINK_OFF) { + /* set LED to ON for idle */ + port_led_state &= EM_MSG_LED_VALUE_OFF; + port_led_state |= (ap->port_no | (link->pmp << 8)); + port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ + ahci_transmit_led_message(ap, port_led_state, 4); + } + } + emp->blink_policy = val; + return 0; +} + +static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) +{ + struct ata_link *link = dev->link; + struct ata_port *ap = link->ap; + struct ahci_port_priv *pp = ap->private_data; + struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; + + /* display the saved value of activity behavior for this + * disk. + */ + return sprintf(buf, "%d\n", emp->blink_policy); +} + +static void ahci_port_init(struct device *dev, struct ata_port *ap, + int port_no, void __iomem *mmio, + void __iomem *port_mmio) +{ + const char *emsg = NULL; + int rc; + u32 tmp; + + /* make sure port is not active */ + rc = ahci_deinit_port(ap, &emsg); + if (rc) + dev_warn(dev, "%s (%d)\n", emsg, rc); + + /* clear SError */ + tmp = readl(port_mmio + PORT_SCR_ERR); + VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); + writel(tmp, port_mmio + PORT_SCR_ERR); + + /* clear port IRQ */ + tmp = readl(port_mmio + PORT_IRQ_STAT); + VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); + if (tmp) + writel(tmp, port_mmio + PORT_IRQ_STAT); + + writel(1 << port_no, mmio + HOST_IRQ_STAT); +} + +void ahci_init_controller(struct ata_host *host) +{ + struct ahci_host_priv *hpriv = host->private_data; + void __iomem *mmio = hpriv->mmio; + int i; + void __iomem *port_mmio; + u32 tmp; + + for (i = 0; i < host->n_ports; i++) { + struct ata_port *ap = host->ports[i]; + + port_mmio = ahci_port_base(ap); + if (ata_port_is_dummy(ap)) + continue; + + ahci_port_init(host->dev, ap, i, mmio, port_mmio); + } + + tmp = readl(mmio + HOST_CTL); + VPRINTK("HOST_CTL 0x%x\n", tmp); + writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); + tmp = readl(mmio + HOST_CTL); + VPRINTK("HOST_CTL 0x%x\n", tmp); +} +EXPORT_SYMBOL_GPL(ahci_init_controller); + +static void ahci_dev_config(struct ata_device *dev) +{ + struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; + + if (hpriv->flags & AHCI_HFLAG_SECT255) { + dev->max_sectors = 255; + ata_dev_printk(dev, KERN_INFO, + "SB600 AHCI: limiting to 255 sectors per cmd\n"); + } +} + +static unsigned int ahci_dev_classify(struct ata_port *ap) +{ + void __iomem *port_mmio = ahci_port_base(ap); + struct ata_taskfile tf; + u32 tmp; + + tmp = readl(port_mmio + PORT_SIG); + tf.lbah = (tmp >> 24) & 0xff; + tf.lbam = (tmp >> 16) & 0xff; + tf.lbal = (tmp >> 8) & 0xff; + tf.nsect = (tmp) & 0xff; + + return ata_dev_classify(&tf); +} + +static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, + u32 opts) +{ + dma_addr_t cmd_tbl_dma; + + cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; + + pp->cmd_slot[tag].opts = cpu_to_le32(opts); + pp->cmd_slot[tag].status = 0; + pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); + pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); +} + +int ahci_kick_engine(struct ata_port *ap) +{ + void __iomem *port_mmio = ahci_port_base(ap); + struct ahci_host_priv *hpriv = ap->host->private_data; + u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; + u32 tmp; + int busy, rc; + + /* stop engine */ + rc = ahci_stop_engine(ap); + if (rc) + goto out_restart; + + /* need to do CLO? + * always do CLO if PMP is attached (AHCI-1.3 9.2) + */ + busy = status & (ATA_BUSY | ATA_DRQ); + if (!busy && !sata_pmp_attached(ap)) { + rc = 0; + goto out_restart; + } + + if (!(hpriv->cap & HOST_CAP_CLO)) { + rc = -EOPNOTSUPP; + goto out_restart; + } + + /* perform CLO */ + tmp = readl(port_mmio + PORT_CMD); + tmp |= PORT_CMD_CLO; + writel(tmp, port_mmio + PORT_CMD); + + rc = 0; + tmp = ata_wait_register(port_mmio + PORT_CMD, + PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); + if (tmp & PORT_CMD_CLO) + rc = -EIO; + + /* restart engine */ + out_restart: + ahci_start_engine(ap); + return rc; +} +EXPORT_SYMBOL_GPL(ahci_kick_engine); + +static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, + struct ata_taskfile *tf, int is_cmd, u16 flags, + unsigned long timeout_msec) +{ + const u32 cmd_fis_len = 5; /* five dwords */ + struct ahci_port_priv *pp = ap->private_data; + void __iomem *port_mmio = ahci_port_base(ap); + u8 *fis = pp->cmd_tbl; + u32 tmp; + + /* prep the command */ + ata_tf_to_fis(tf, pmp, is_cmd, fis); + ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); + + /* issue & wait */ + writel(1, port_mmio + PORT_CMD_ISSUE); + + if (timeout_msec) { + tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, + 1, timeout_msec); + if (tmp & 0x1) { + ahci_kick_engine(ap); + return -EBUSY; + } + } else + readl(port_mmio + PORT_CMD_ISSUE); /* flush */ + + return 0; +} + +int ahci_do_softreset(struct ata_link *link, unsigned int *class, + int pmp, unsigned long deadline, + int (*check_ready)(struct ata_link *link)) +{ + struct ata_port *ap = link->ap; + struct ahci_host_priv *hpriv = ap->host->private_data; + const char *reason = NULL; + unsigned long now, msecs; + struct ata_taskfile tf; + int rc; + + DPRINTK("ENTER\n"); + + /* prepare for SRST (AHCI-1.1 10.4.1) */ + rc = ahci_kick_engine(ap); + if (rc && rc != -EOPNOTSUPP) + ata_link_printk(link, KERN_WARNING, + "failed to reset engine (errno=%d)\n", rc); + + ata_tf_init(link->device, &tf); + + /* issue the first D2H Register FIS */ + msecs = 0; + now = jiffies; + if (time_after(now, deadline)) + msecs = jiffies_to_msecs(deadline - now); + + tf.ctl |= ATA_SRST; + if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, + AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { + rc = -EIO; + reason = "1st FIS failed"; + goto fail; + } + + /* spec says at least 5us, but be generous and sleep for 1ms */ + msleep(1); + + /* issue the second D2H Register FIS */ + tf.ctl &= ~ATA_SRST; + ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); + + /* wait for link to become ready */ + rc = ata_wait_after_reset(link, deadline, check_ready); + if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { + /* + * Workaround for cases where link online status can't + * be trusted. Treat device readiness timeout as link + * offline. + */ + ata_link_printk(link, KERN_INFO, + "device not ready, treating as offline\n"); + *class = ATA_DEV_NONE; + } else if (rc) { + /* link occupied, -ENODEV too is an error */ + reason = "device not ready"; + goto fail; + } else + *class = ahci_dev_classify(ap); + + DPRINTK("EXIT, class=%u\n", *class); + return 0; + + fail: + ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); + return rc; +} + +int ahci_check_ready(struct ata_link *link) +{ + void __iomem *port_mmio = ahci_port_base(link->ap); + u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; + + return ata_check_ready(status); +} +EXPORT_SYMBOL_GPL(ahci_check_ready); + +static int ahci_softreset(struct ata_link *link, unsigned int *class, + unsigned long deadline) +{ + int pmp = sata_srst_pmp(link); + + DPRINTK("ENTER\n"); + + return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); +} +EXPORT_SYMBOL_GPL(ahci_do_softreset); + +static int ahci_hardreset(struct ata_link *link, unsigned int *class, + unsigned long deadline) +{ + const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); + struct ata_port *ap = link->ap; + struct ahci_port_priv *pp = ap->private_data; + u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; + struct ata_taskfile tf; + bool online; + int rc; + + DPRINTK("ENTER\n"); + + ahci_stop_engine(ap); + + /* clear D2H reception area to properly wait for D2H FIS */ + ata_tf_init(link->device, &tf); + tf.command = 0x80; + ata_tf_to_fis(&tf, 0, 0, d2h_fis); + + rc = sata_link_hardreset(link, timing, deadline, &online, + ahci_check_ready); + + ahci_start_engine(ap); + + if (online) + *class = ahci_dev_classify(ap); + + DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); + return rc; +} + +static void ahci_postreset(struct ata_link *link, unsigned int *class) +{ + struct ata_port *ap = link->ap; + void __iomem *port_mmio = ahci_port_base(ap); + u32 new_tmp, tmp; + + ata_std_postreset(link, class); + + /* Make sure port's ATAPI bit is set appropriately */ + new_tmp = tmp = readl(port_mmio + PORT_CMD); + if (*class == ATA_DEV_ATAPI) + new_tmp |= PORT_CMD_ATAPI; + else + new_tmp &= ~PORT_CMD_ATAPI; + if (new_tmp != tmp) { + writel(new_tmp, port_mmio + PORT_CMD); + readl(port_mmio + PORT_CMD); /* flush */ + } +} + +static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) +{ + struct scatterlist *sg; + struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; + unsigned int si; + + VPRINTK("ENTER\n"); + + /* + * Next, the S/G list. + */ + for_each_sg(qc->sg, sg, qc->n_elem, si) { + dma_addr_t addr = sg_dma_address(sg); + u32 sg_len = sg_dma_len(sg); + + ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); + ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); + ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); + } + + return si; +} + +static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct ahci_port_priv *pp = ap->private_data; + + if (!sata_pmp_attached(ap) || pp->fbs_enabled) + return ata_std_qc_defer(qc); + else + return sata_pmp_qc_defer_cmd_switch(qc); +} + +static void ahci_qc_prep(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct ahci_port_priv *pp = ap->private_data; + int is_atapi = ata_is_atapi(qc->tf.protocol); + void *cmd_tbl; + u32 opts; + const u32 cmd_fis_len = 5; /* five dwords */ + unsigned int n_elem; + + /* + * Fill in command table information. First, the header, + * a SATA Register - Host to Device command FIS. + */ + cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; + + ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); + if (is_atapi) { + memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); + memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); + } + + n_elem = 0; + if (qc->flags & ATA_QCFLAG_DMAMAP) + n_elem = ahci_fill_sg(qc, cmd_tbl); + + /* + * Fill in command slot information. + */ + opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); + if (qc->tf.flags & ATA_TFLAG_WRITE) + opts |= AHCI_CMD_WRITE; + if (is_atapi) + opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; + + ahci_fill_cmd_slot(pp, qc->tag, opts); +} + +static void ahci_fbs_dec_intr(struct ata_port *ap) +{ + struct ahci_port_priv *pp = ap->private_data; + void __iomem *port_mmio = ahci_port_base(ap); + u32 fbs = readl(port_mmio + PORT_FBS); + int retries = 3; + + DPRINTK("ENTER\n"); + BUG_ON(!pp->fbs_enabled); + + /* time to wait for DEC is not specified by AHCI spec, + * add a retry loop for safety. + */ + writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); + fbs = readl(port_mmio + PORT_FBS); + while ((fbs & PORT_FBS_DEC) && retries--) { + udelay(1); + fbs = readl(port_mmio + PORT_FBS); + } + + if (fbs & PORT_FBS_DEC) + dev_printk(KERN_ERR, ap->host->dev, + "failed to clear device error\n"); +} + +static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) +{ + struct ahci_host_priv *hpriv = ap->host->private_data; + struct ahci_port_priv *pp = ap->private_data; + struct ata_eh_info *host_ehi = &ap->link.eh_info; + struct ata_link *link = NULL; + struct ata_queued_cmd *active_qc; + struct ata_eh_info *active_ehi; + bool fbs_need_dec = false; + u32 serror; + + /* determine active link with error */ + if (pp->fbs_enabled) { + void __iomem *port_mmio = ahci_port_base(ap); + u32 fbs = readl(port_mmio + PORT_FBS); + int pmp = fbs >> PORT_FBS_DWE_OFFSET; + + if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) && + ata_link_online(&ap->pmp_link[pmp])) { + link = &ap->pmp_link[pmp]; + fbs_need_dec = true; + } + + } else + ata_for_each_link(link, ap, EDGE) + if (ata_link_active(link)) + break; + + if (!link) + link = &ap->link; + + active_qc = ata_qc_from_tag(ap, link->active_tag); + active_ehi = &link->eh_info; + + /* record irq stat */ + ata_ehi_clear_desc(host_ehi); + ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); + + /* AHCI needs SError cleared; otherwise, it might lock up */ + ahci_scr_read(&ap->link, SCR_ERROR, &serror); + ahci_scr_write(&ap->link, SCR_ERROR, serror); + host_ehi->serror |= serror; + + /* some controllers set IRQ_IF_ERR on device errors, ignore it */ + if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) + irq_stat &= ~PORT_IRQ_IF_ERR; + + if (irq_stat & PORT_IRQ_TF_ERR) { + /* If qc is active, charge it; otherwise, the active + * link. There's no active qc on NCQ errors. It will + * be determined by EH by reading log page 10h. + */ + if (active_qc) + active_qc->err_mask |= AC_ERR_DEV; + else + active_ehi->err_mask |= AC_ERR_DEV; + + if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) + host_ehi->serror &= ~SERR_INTERNAL; + } + + if (irq_stat & PORT_IRQ_UNK_FIS) { + u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); + + active_ehi->err_mask |= AC_ERR_HSM; + active_ehi->action |= ATA_EH_RESET; + ata_ehi_push_desc(active_ehi, + "unknown FIS %08x %08x %08x %08x" , + unk[0], unk[1], unk[2], unk[3]); + } + + if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { + active_ehi->err_mask |= AC_ERR_HSM; + active_ehi->action |= ATA_EH_RESET; + ata_ehi_push_desc(active_ehi, "incorrect PMP"); + } + + if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { + host_ehi->err_mask |= AC_ERR_HOST_BUS; + host_ehi->action |= ATA_EH_RESET; + ata_ehi_push_desc(host_ehi, "host bus error"); + } + + if (irq_stat & PORT_IRQ_IF_ERR) { + if (fbs_need_dec) + active_ehi->err_mask |= AC_ERR_DEV; + else { + host_ehi->err_mask |= AC_ERR_ATA_BUS; + host_ehi->action |= ATA_EH_RESET; + } + + ata_ehi_push_desc(host_ehi, "interface fatal error"); + } + + if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { + ata_ehi_hotplugged(host_ehi); + ata_ehi_push_desc(host_ehi, "%s", + irq_stat & PORT_IRQ_CONNECT ? + "connection status changed" : "PHY RDY changed"); + } + + /* okay, let's hand over to EH */ + + if (irq_stat & PORT_IRQ_FREEZE) + ata_port_freeze(ap); + else if (fbs_need_dec) { + ata_link_abort(link); + ahci_fbs_dec_intr(ap); + } else + ata_port_abort(ap); +} + +static void ahci_port_intr(struct ata_port *ap) +{ + void __iomem *port_mmio = ahci_port_base(ap); + struct ata_eh_info *ehi = &ap->link.eh_info; + struct ahci_port_priv *pp = ap->private_data; + struct ahci_host_priv *hpriv = ap->host->private_data; + int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); + u32 status, qc_active = 0; + int rc; + + status = readl(port_mmio + PORT_IRQ_STAT); + writel(status, port_mmio + PORT_IRQ_STAT); + + /* ignore BAD_PMP while resetting */ + if (unlikely(resetting)) + status &= ~PORT_IRQ_BAD_PMP; + + /* If we are getting PhyRdy, this is + * just a power state change, we should + * clear out this, plus the PhyRdy/Comm + * Wake bits from Serror + */ + if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && + (status & PORT_IRQ_PHYRDY)) { + status &= ~PORT_IRQ_PHYRDY; + ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); + } + + if (unlikely(status & PORT_IRQ_ERROR)) { + ahci_error_intr(ap, status); + return; + } + + if (status & PORT_IRQ_SDB_FIS) { + /* If SNotification is available, leave notification + * handling to sata_async_notification(). If not, + * emulate it by snooping SDB FIS RX area. + * + * Snooping FIS RX area is probably cheaper than + * poking SNotification but some constrollers which + * implement SNotification, ICH9 for example, don't + * store AN SDB FIS into receive area. + */ + if (hpriv->cap & HOST_CAP_SNTF) + sata_async_notification(ap); + else { + /* If the 'N' bit in word 0 of the FIS is set, + * we just received asynchronous notification. + * Tell libata about it. + * + * Lack of SNotification should not appear in + * ahci 1.2, so the workaround is unnecessary + * when FBS is enabled. + */ + if (pp->fbs_enabled) + WARN_ON_ONCE(1); + else { + const __le32 *f = pp->rx_fis + RX_FIS_SDB; + u32 f0 = le32_to_cpu(f[0]); + if (f0 & (1 << 15)) + sata_async_notification(ap); + } + } + } + + /* pp->active_link is not reliable once FBS is enabled, both + * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because + * NCQ and non-NCQ commands may be in flight at the same time. + */ + if (pp->fbs_enabled) { + if (ap->qc_active) { + qc_active = readl(port_mmio + PORT_SCR_ACT); + qc_active |= readl(port_mmio + PORT_CMD_ISSUE); + } + } else { + /* pp->active_link is valid iff any command is in flight */ + if (ap->qc_active && pp->active_link->sactive) + qc_active = readl(port_mmio + PORT_SCR_ACT); + else + qc_active = readl(port_mmio + PORT_CMD_ISSUE); + } + + + rc = ata_qc_complete_multiple(ap, qc_active); + + /* while resetting, invalid completions are expected */ + if (unlikely(rc < 0 && !resetting)) { + ehi->err_mask |= AC_ERR_HSM; + ehi->action |= ATA_EH_RESET; + ata_port_freeze(ap); + } +} + +irqreturn_t ahci_interrupt(int irq, void *dev_instance) +{ + struct ata_host *host = dev_instance; + struct ahci_host_priv *hpriv; + unsigned int i, handled = 0; + void __iomem *mmio; + u32 irq_stat, irq_masked; + + VPRINTK("ENTER\n"); + + hpriv = host->private_data; + mmio = hpriv->mmio; + + /* sigh. 0xffffffff is a valid return from h/w */ + irq_stat = readl(mmio + HOST_IRQ_STAT); + if (!irq_stat) + return IRQ_NONE; + + irq_masked = irq_stat & hpriv->port_map; + + spin_lock(&host->lock); + + for (i = 0; i < host->n_ports; i++) { + struct ata_port *ap; + + if (!(irq_masked & (1 << i))) + continue; + + ap = host->ports[i]; + if (ap) { + ahci_port_intr(ap); + VPRINTK("port %u\n", i); + } else { + VPRINTK("port %u (no irq)\n", i); + if (ata_ratelimit()) + dev_printk(KERN_WARNING, host->dev, + "interrupt on disabled port %u\n", i); + } + + handled = 1; + } + + /* HOST_IRQ_STAT behaves as level triggered latch meaning that + * it should be cleared after all the port events are cleared; + * otherwise, it will raise a spurious interrupt after each + * valid one. Please read section 10.6.2 of ahci 1.1 for more + * information. + * + * Also, use the unmasked value to clear interrupt as spurious + * pending event on a dummy port might cause screaming IRQ. + */ + writel(irq_stat, mmio + HOST_IRQ_STAT); + + spin_unlock(&host->lock); + + VPRINTK("EXIT\n"); + + return IRQ_RETVAL(handled); +} +EXPORT_SYMBOL_GPL(ahci_interrupt); + +static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + void __iomem *port_mmio = ahci_port_base(ap); + struct ahci_port_priv *pp = ap->private_data; + + /* Keep track of the currently active link. It will be used + * in completion path to determine whether NCQ phase is in + * progress. + */ + pp->active_link = qc->dev->link; + + if (qc->tf.protocol == ATA_PROT_NCQ) + writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); + + if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { + u32 fbs = readl(port_mmio + PORT_FBS); + fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); + fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; + writel(fbs, port_mmio + PORT_FBS); + pp->fbs_last_dev = qc->dev->link->pmp; + } + + writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); + + ahci_sw_activity(qc->dev->link); + + return 0; +} + +static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) +{ + struct ahci_port_priv *pp = qc->ap->private_data; + u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; + + if (pp->fbs_enabled) + d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; + + ata_tf_from_fis(d2h_fis, &qc->result_tf); + return true; +} + +static void ahci_freeze(struct ata_port *ap) +{ + void __iomem *port_mmio = ahci_port_base(ap); + + /* turn IRQ off */ + writel(0, port_mmio + PORT_IRQ_MASK); +} + +static void ahci_thaw(struct ata_port *ap) +{ + struct ahci_host_priv *hpriv = ap->host->private_data; + void __iomem *mmio = hpriv->mmio; + void __iomem *port_mmio = ahci_port_base(ap); + u32 tmp; + struct ahci_port_priv *pp = ap->private_data; + + /* clear IRQ */ + tmp = readl(port_mmio + PORT_IRQ_STAT); + writel(tmp, port_mmio + PORT_IRQ_STAT); + writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); + + /* turn IRQ back on */ + writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); +} + +static void ahci_error_handler(struct ata_port *ap) +{ + if (!(ap->pflags & ATA_PFLAG_FROZEN)) { + /* restart engine */ + ahci_stop_engine(ap); + ahci_start_engine(ap); + } + + sata_pmp_error_handler(ap); +} + +static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + + /* make DMA engine forget about the failed command */ + if (qc->flags & ATA_QCFLAG_FAILED) + ahci_kick_engine(ap); +} + +static void ahci_enable_fbs(struct ata_port *ap) +{ + struct ahci_port_priv *pp = ap->private_data; + void __iomem *port_mmio = ahci_port_base(ap); + u32 fbs; + int rc; + + if (!pp->fbs_supported) + return; + + fbs = readl(port_mmio + PORT_FBS); + if (fbs & PORT_FBS_EN) { + pp->fbs_enabled = true; + pp->fbs_last_dev = -1; /* initialization */ + return; + } + + rc = ahci_stop_engine(ap); + if (rc) + return; + + writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); + fbs = readl(port_mmio + PORT_FBS); + if (fbs & PORT_FBS_EN) { + dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n"); + pp->fbs_enabled = true; + pp->fbs_last_dev = -1; /* initialization */ + } else + dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n"); + + ahci_start_engine(ap); +} + +static void ahci_disable_fbs(struct ata_port *ap) +{ + struct ahci_port_priv *pp = ap->private_data; + void __iomem *port_mmio = ahci_port_base(ap); + u32 fbs; + int rc; + + if (!pp->fbs_supported) + return; + + fbs = readl(port_mmio + PORT_FBS); + if ((fbs & PORT_FBS_EN) == 0) { + pp->fbs_enabled = false; + return; + } + + rc = ahci_stop_engine(ap); + if (rc) + return; + + writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); + fbs = readl(port_mmio + PORT_FBS); + if (fbs & PORT_FBS_EN) + dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n"); + else { + dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n"); + pp->fbs_enabled = false; + } + + ahci_start_engine(ap); +} + +static void ahci_pmp_attach(struct ata_port *ap) +{ + void __iomem *port_mmio = ahci_port_base(ap); + struct ahci_port_priv *pp = ap->private_data; + u32 cmd; + + cmd = readl(port_mmio + PORT_CMD); + cmd |= PORT_CMD_PMP; + writel(cmd, port_mmio + PORT_CMD); + + ahci_enable_fbs(ap); + + pp->intr_mask |= PORT_IRQ_BAD_PMP; + writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); +} + +static void ahci_pmp_detach(struct ata_port *ap) +{ + void __iomem *port_mmio = ahci_port_base(ap); + struct ahci_port_priv *pp = ap->private_data; + u32 cmd; + + ahci_disable_fbs(ap); + + cmd = readl(port_mmio + PORT_CMD); + cmd &= ~PORT_CMD_PMP; + writel(cmd, port_mmio + PORT_CMD); + + pp->intr_mask &= ~PORT_IRQ_BAD_PMP; + writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); +} + +static int ahci_port_resume(struct ata_port *ap) +{ + ahci_power_up(ap); + ahci_start_port(ap); + + if (sata_pmp_attached(ap)) + ahci_pmp_attach(ap); + else + ahci_pmp_detach(ap); + + return 0; +} + +#ifdef CONFIG_PM +static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) +{ + const char *emsg = NULL; + int rc; + + rc = ahci_deinit_port(ap, &emsg); + if (rc == 0) + ahci_power_down(ap); + else { + ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); + ahci_start_port(ap); + } + + return rc; +} +#endif + +static int ahci_port_start(struct ata_port *ap) +{ + struct ahci_host_priv *hpriv = ap->host->private_data; + struct device *dev = ap->host->dev; + struct ahci_port_priv *pp; + void *mem; + dma_addr_t mem_dma; + size_t dma_sz, rx_fis_sz; + + pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); + if (!pp) + return -ENOMEM; + + /* check FBS capability */ + if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { + void __iomem *port_mmio = ahci_port_base(ap); + u32 cmd = readl(port_mmio + PORT_CMD); + if (cmd & PORT_CMD_FBSCP) + pp->fbs_supported = true; + else + dev_printk(KERN_WARNING, dev, + "The port is not capable of FBS\n"); + } + + if (pp->fbs_supported) { + dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; + rx_fis_sz = AHCI_RX_FIS_SZ * 16; + } else { + dma_sz = AHCI_PORT_PRIV_DMA_SZ; + rx_fis_sz = AHCI_RX_FIS_SZ; + } + + mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); + if (!mem) + return -ENOMEM; + memset(mem, 0, dma_sz); + + /* + * First item in chunk of DMA memory: 32-slot command table, + * 32 bytes each in size + */ + pp->cmd_slot = mem; + pp->cmd_slot_dma = mem_dma; + + mem += AHCI_CMD_SLOT_SZ; + mem_dma += AHCI_CMD_SLOT_SZ; + + /* + * Second item: Received-FIS area + */ + pp->rx_fis = mem; + pp->rx_fis_dma = mem_dma; + + mem += rx_fis_sz; + mem_dma += rx_fis_sz; + + /* + * Third item: data area for storing a single command + * and its scatter-gather table + */ + pp->cmd_tbl = mem; + pp->cmd_tbl_dma = mem_dma; + + /* + * Save off initial list of interrupts to be enabled. + * This could be changed later + */ + pp->intr_mask = DEF_PORT_IRQ; + + ap->private_data = pp; + + /* engage engines, captain */ + return ahci_port_resume(ap); +} + +static void ahci_port_stop(struct ata_port *ap) +{ + const char *emsg = NULL; + int rc; + + /* de-initialize port */ + rc = ahci_deinit_port(ap, &emsg); + if (rc) + ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); +} + +void ahci_print_info(struct ata_host *host, const char *scc_s) +{ + struct ahci_host_priv *hpriv = host->private_data; + void __iomem *mmio = hpriv->mmio; + u32 vers, cap, cap2, impl, speed; + const char *speed_s; + + vers = readl(mmio + HOST_VERSION); + cap = hpriv->cap; + cap2 = hpriv->cap2; + impl = hpriv->port_map; + + speed = (cap >> 20) & 0xf; + if (speed == 1) + speed_s = "1.5"; + else if (speed == 2) + speed_s = "3"; + else if (speed == 3) + speed_s = "6"; + else + speed_s = "?"; + + dev_info(host->dev, + "AHCI %02x%02x.%02x%02x " + "%u slots %u ports %s Gbps 0x%x impl %s mode\n" + , + + (vers >> 24) & 0xff, + (vers >> 16) & 0xff, + (vers >> 8) & 0xff, + vers & 0xff, + + ((cap >> 8) & 0x1f) + 1, + (cap & 0x1f) + 1, + speed_s, + impl, + scc_s); + + dev_info(host->dev, + "flags: " + "%s%s%s%s%s%s%s" + "%s%s%s%s%s%s%s" + "%s%s%s%s%s%s\n" + , + + cap & HOST_CAP_64 ? "64bit " : "", + cap & HOST_CAP_NCQ ? "ncq " : "", + cap & HOST_CAP_SNTF ? "sntf " : "", + cap & HOST_CAP_MPS ? "ilck " : "", + cap & HOST_CAP_SSS ? "stag " : "", + cap & HOST_CAP_ALPM ? "pm " : "", + cap & HOST_CAP_LED ? "led " : "", + cap & HOST_CAP_CLO ? "clo " : "", + cap & HOST_CAP_ONLY ? "only " : "", + cap & HOST_CAP_PMP ? "pmp " : "", + cap & HOST_CAP_FBS ? "fbs " : "", + cap & HOST_CAP_PIO_MULTI ? "pio " : "", + cap & HOST_CAP_SSC ? "slum " : "", + cap & HOST_CAP_PART ? "part " : "", + cap & HOST_CAP_CCC ? "ccc " : "", + cap & HOST_CAP_EMS ? "ems " : "", + cap & HOST_CAP_SXS ? "sxs " : "", + cap2 & HOST_CAP2_APST ? "apst " : "", + cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", + cap2 & HOST_CAP2_BOH ? "boh " : "" + ); +} +EXPORT_SYMBOL_GPL(ahci_print_info); + +void ahci_set_em_messages(struct ahci_host_priv *hpriv, + struct ata_port_info *pi) +{ + u8 messages; + void __iomem *mmio = hpriv->mmio; + u32 em_loc = readl(mmio + HOST_EM_LOC); + u32 em_ctl = readl(mmio + HOST_EM_CTL); + + if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) + return; + + messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; + + /* we only support LED message type right now */ + if ((messages & 0x01) && (ahci_em_messages == 1)) { + /* store em_loc */ + hpriv->em_loc = ((em_loc >> 16) * 4); + pi->flags |= ATA_FLAG_EM; + if (!(em_ctl & EM_CTL_ALHD)) + pi->flags |= ATA_FLAG_SW_ACTIVITY; + } +} +EXPORT_SYMBOL_GPL(ahci_set_em_messages); + +MODULE_AUTHOR("Jeff Garzik"); +MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/fsl_otp.c b/drivers/char/fsl_otp.c new file mode 100755 index 000000000000..1a7db625f243 --- /dev/null +++ b/drivers/char/fsl_otp.c @@ -0,0 +1,239 @@ +/* + * Freescale On-Chip OTP driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fsl_otp.h" + +static DEFINE_MUTEX(otp_mutex); +static struct kobject *otp_kobj; +static struct attribute **attrs; +static struct kobj_attribute *kattr; +static struct attribute_group attr_group; +static struct fsl_otp_data *otp_data; + +static inline unsigned int get_reg_index(struct kobj_attribute *tmp) +{ + return tmp - kattr; +} + +static int otp_wait_busy(u32 flags) +{ + int count; + u32 c; + + for (count = 10000; count >= 0; count--) { + c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL); + if (!(c & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR | flags))) + break; + cpu_relax(); + } + if (count < 0) + return -ETIMEDOUT; + return 0; +} + +static ssize_t otp_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + unsigned int index = get_reg_index(attr); + u32 value = 0; + + /* sanity check */ + if (index >= otp_data->fuse_num) + return 0; + + mutex_lock(&otp_mutex); + + if (otp_read_prepare()) { + mutex_unlock(&otp_mutex); + return 0; + } + value = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTn(index)); + otp_read_post(); + + mutex_unlock(&otp_mutex); + return sprintf(buf, "0x%x\n", value); +} + +static int otp_write_bits(int addr, u32 data, u32 magic) +{ + u32 c; /* for control register */ + + /* init the control register */ + c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL); + c &= ~BM_OCOTP_CTRL_ADDR; + c |= BF(addr, OCOTP_CTRL_ADDR); + c |= BF(magic, OCOTP_CTRL_WR_UNLOCK); + __raw_writel(c, REGS_OCOTP_BASE + HW_OCOTP_CTRL); + + /* init the data register */ + __raw_writel(data, REGS_OCOTP_BASE + HW_OCOTP_DATA); + otp_wait_busy(0); + + mdelay(2); /* Write Postamble */ + return 0; +} + +static ssize_t otp_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + unsigned int index = get_reg_index(attr); + int value; + + /* sanity check */ + if (index >= otp_data->fuse_num) + return 0; + + sscanf(buf, "0x%x", &value); + + mutex_lock(&otp_mutex); + if (otp_write_prepare(otp_data)) { + mutex_unlock(&otp_mutex); + return 0; + } + otp_write_bits(index, value, 0x3e77); + otp_write_post(); + mutex_unlock(&otp_mutex); + return count; +} + +static void free_otp_attr(void) +{ + kfree(attrs); + attrs = NULL; + + kfree(kattr); + kattr = NULL; +} + +static int __init alloc_otp_attr(struct fsl_otp_data *pdata) +{ + int i; + + otp_data = pdata; /* get private data */ + + /* The last one is NULL, which is used to detect the end */ + attrs = kzalloc((otp_data->fuse_num + 1) * sizeof(attrs[0]), + GFP_KERNEL); + kattr = kzalloc(otp_data->fuse_num * sizeof(struct kobj_attribute), + GFP_KERNEL); + + if (!attrs || !kattr) + goto error_out; + + for (i = 0; i < otp_data->fuse_num; i++) { + kattr[i].attr.name = pdata->fuse_name[i]; + kattr[i].attr.mode = 0600; + kattr[i].show = otp_show; + kattr[i].store = otp_store; + + attrs[i] = &kattr[i].attr; + } + memset(&attr_group, 0, sizeof(attr_group)); + attr_group.attrs = attrs; + return 0; + +error_out: + free_otp_attr(); + return -ENOMEM; +} + +static int __devinit fsl_otp_probe(struct platform_device *pdev) +{ + int retval; + struct fsl_otp_data *pdata; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) + return -ENODEV; + + retval = alloc_otp_attr(pdata); + if (retval) + return retval; + + retval = map_ocotp_addr(pdev); + if (retval) + goto error; + + otp_kobj = kobject_create_and_add("fsl_otp", NULL); + if (!otp_kobj) { + retval = -ENOMEM; + goto error; + } + + retval = sysfs_create_group(otp_kobj, &attr_group); + if (retval) + goto error; + + mutex_init(&otp_mutex); + return 0; +error: + kobject_put(otp_kobj); + otp_kobj = NULL; + free_otp_attr(); + unmap_ocotp_addr(); + return retval; +} + +static int otp_remove(struct platform_device *pdev) +{ + kobject_put(otp_kobj); + otp_kobj = NULL; + + free_otp_attr(); + unmap_ocotp_addr(); + return 0; +} + +static struct platform_driver ocotp_driver = { + .probe = fsl_otp_probe, + .remove = otp_remove, + .driver = { + .name = "ocotp", + .owner = THIS_MODULE, + }, +}; + +static int __init fsl_otp_init(void) +{ + return platform_driver_register(&ocotp_driver); +} + +static void __exit fsl_otp_exit(void) +{ + platform_driver_unregister(&ocotp_driver); +} +module_init(fsl_otp_init); +module_exit(fsl_otp_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Huang Shijie "); +MODULE_DESCRIPTION("Common driver for OTP controller"); diff --git a/drivers/char/fsl_otp.h b/drivers/char/fsl_otp.h new file mode 100755 index 000000000000..72ec23450dce --- /dev/null +++ b/drivers/char/fsl_otp.h @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __FREESCALE_OTP__ +#define __FREESCALE_OTP__ + +#define log(a, ...) printk(KERN_INFO "[ %s : %.3d ] "a"\n", \ + __func__, __LINE__, ## __VA_ARGS__) + +static int otp_wait_busy(u32 flags); + +/* IMX23 and IMX28 share most of the defination ========================= */ +#if (defined(CONFIG_ARCH_MX23) || defined(CONFIG_ARCH_MX28)) + +#include +#include +#include +#include +#include + +#if defined(CONFIG_ARCH_MX23) +#include +#else +#include +#endif + +#define REGS_OCOTP_BASE (IO_ADDRESS(OCOTP_PHYS_ADDR)) +#define BF(value, field) (((value) << BP_##field) & BM_##field) + +static unsigned long otp_hclk_saved; +static u32 otp_voltage_saved; +struct regulator *regu; + +/* open the bank for the imx23/imx28 */ +static int otp_read_prepare(void) +{ + int r; + + /* [1] set the HCLK */ + /* [2] check BUSY and ERROR bit */ + r = otp_wait_busy(0); + if (r < 0) + goto error; + + /* [3] open bank */ + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + udelay(10); + + /* [4] wait for BUSY */ + r = otp_wait_busy(0); + return 0; +error: + return r; +} + +static int otp_read_post(void) +{ + /* [5] close bank */ + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_CLR); + return 0; +} + +static int otp_write_prepare(struct fsl_otp_data *otp_data) +{ + struct clk *hclk; + int err = 0; + + /* [1] HCLK to 24MHz. */ + hclk = clk_get(NULL, "hclk"); + if (IS_ERR(hclk)) { + err = PTR_ERR(hclk); + goto out; + } + /* + WARNING ACHTUNG UWAGA + + the code below changes HCLK clock rate to 24M. This is + required to write OTP bits (7.2.2 in STMP378x Target + Specification), and might affect LCD operation, for example. + Moreover, this hacky code changes VDDIO to 2.8V; and resto- + res it only on otp_close(). This may affect... anything. + + You are warned now. + */ + otp_hclk_saved = clk_get_rate(hclk); + clk_set_rate(hclk, 24000); + + /* [2] The voltage is set to 2.8V */ + regu = regulator_get(NULL, otp_data->regulator_name); + otp_voltage_saved = regulator_get_voltage(regu); + regulator_set_voltage(regu, 2800000, 2800000); + + /* [3] wait for BUSY and ERROR */ + err = otp_wait_busy(BM_OCOTP_CTRL_RD_BANK_OPEN); +out: + return err; +} + +static int otp_write_post(void) +{ + struct clk *hclk; + + hclk = clk_get(NULL, "hclk"); + + /* restore the clock and voltage */ + clk_set_rate(hclk, otp_hclk_saved); + regulator_set_voltage(regu, otp_voltage_saved, otp_voltage_saved); + otp_wait_busy(0); + + /* reset */ + __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS); + return 0; +} + +static int __init map_ocotp_addr(struct platform_device *pdev) +{ + return 0; +} +static void unmap_ocotp_addr(void) +{ +} + +#elif defined(CONFIG_ARCH_MX5) /* IMX5 below ============================= */ + +#include +#include +#include +#include "regs-ocotp-v2.h" + +static void *otp_base; +#define REGS_OCOTP_BASE ((unsigned long)otp_base) +#define HW_OCOTP_CUSTn(n) (0x00000030 + (n) * 0x10) +#define BF(value, field) (((value) << BP_##field) & BM_##field) + +#define DEF_RELEX (15) /* > 10.5ns */ + +static int set_otp_timing(void) +{ + struct clk *apb_clk; + unsigned long clk_rate = 0; + unsigned long relex, sclk_count, rd_busy; + u32 timing = 0; + + /* [1] get the clock. It needs the AHB clock,though doc writes APB.*/ + apb_clk = clk_get(NULL, "ahb_clk"); + if (IS_ERR(apb_clk)) { + log("we can not find the clock"); + return -1; + } + clk_rate = clk_get_rate(apb_clk); + + /* do optimization for too many zeros */ + relex = clk_rate / (1000000000 / DEF_RELEX) + 1; + sclk_count = clk_rate / (1000000000 / 5000) + 1 + DEF_RELEX; + rd_busy = clk_rate / (1000000000 / 300) + 1; + + timing = BF(relex, OCOTP_TIMING_RELAX); + timing |= BF(sclk_count, OCOTP_TIMING_SCLK_COUNT); + timing |= BF(rd_busy, OCOTP_TIMING_RD_BUSY); + + __raw_writel(timing, REGS_OCOTP_BASE + HW_OCOTP_TIMING); + return 0; +} + +/* IMX5 does not need to open the bank anymore */ +static int otp_read_prepare(void) +{ + return set_otp_timing(); +} +static int otp_read_post(void) +{ + return 0; +} + +static int otp_write_prepare(struct fsl_otp_data *otp_data) +{ + int ret = 0; + + /* [1] set timing */ + ret = set_otp_timing(); + if (ret) + return ret; + + /* [2] wait */ + otp_wait_busy(0); + return 0; +} +static int otp_write_post(void) +{ + /* Reload all the shadow registers */ + __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + udelay(1); + otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS); + return 0; +} + +static int __init map_ocotp_addr(struct platform_device *pdev) +{ + struct resource *res; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + otp_base = ioremap(res->start, SZ_8K); + if (!otp_base) { + log("Can not remap the OTP iomem!"); + return -1; + } + return 0; +} + +static void unmap_ocotp_addr(void) +{ + iounmap(otp_base); + otp_base = NULL; +} +#endif /* CONFIG_ARCH_MX5 */ +#endif diff --git a/drivers/char/regs-ocotp-v2.h b/drivers/char/regs-ocotp-v2.h new file mode 100755 index 000000000000..91eaed0a5be9 --- /dev/null +++ b/drivers/char/regs-ocotp-v2.h @@ -0,0 +1,239 @@ +/* + * Freescale OCOTP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.12 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___OCOTP_H +#define __ARCH_ARM___OCOTP_H + + +#define HW_OCOTP_CTRL (0x00000000) +#define HW_OCOTP_CTRL_SET (0x00000004) +#define HW_OCOTP_CTRL_CLR (0x00000008) +#define HW_OCOTP_CTRL_TOG (0x0000000c) + +#define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BF_OCOTP_CTRL_WR_UNLOCK(v) \ + (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK) +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77 +#define BP_OCOTP_CTRL_RSRVD2 14 +#define BM_OCOTP_CTRL_RSRVD2 0x0000C000 +#define BF_OCOTP_CTRL_RSRVD2(v) \ + (((v) << 14) & BM_OCOTP_CTRL_RSRVD2) +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 +#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 +#define BP_OCOTP_CTRL_RSRVD1 10 +#define BM_OCOTP_CTRL_RSRVD1 0x00000C00 +#define BF_OCOTP_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_CTRL_RSRVD1) +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_RSRVD0 6 +#define BM_OCOTP_CTRL_RSRVD0 0x000000C0 +#define BF_OCOTP_CTRL_RSRVD0(v) \ + (((v) << 6) & BM_OCOTP_CTRL_RSRVD0) +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000003F +#define BF_OCOTP_CTRL_ADDR(v) \ + (((v) << 0) & BM_OCOTP_CTRL_ADDR) + +#define HW_OCOTP_TIMING (0x00000010) + +#define BP_OCOTP_TIMING_RSRVD0 22 +#define BM_OCOTP_TIMING_RSRVD0 0xFFC00000 +#define BF_OCOTP_TIMING_RSRVD0(v) \ + (((v) << 22) & BM_OCOTP_TIMING_RSRVD0) +#define BP_OCOTP_TIMING_RD_BUSY 16 +#define BM_OCOTP_TIMING_RD_BUSY 0x003F0000 +#define BF_OCOTP_TIMING_RD_BUSY(v) \ + (((v) << 16) & BM_OCOTP_TIMING_RD_BUSY) +#define BP_OCOTP_TIMING_RELAX 12 +#define BM_OCOTP_TIMING_RELAX 0x0000F000 +#define BF_OCOTP_TIMING_RELAX(v) \ + (((v) << 12) & BM_OCOTP_TIMING_RELAX) +#define BP_OCOTP_TIMING_SCLK_COUNT 0 +#define BM_OCOTP_TIMING_SCLK_COUNT 0x00000FFF +#define BF_OCOTP_TIMING_SCLK_COUNT(v) \ + (((v) << 0) & BM_OCOTP_TIMING_SCLK_COUNT) + +#define HW_OCOTP_DATA (0x00000020) + +#define BP_OCOTP_DATA_DATA 0 +#define BM_OCOTP_DATA_DATA 0xFFFFFFFF +#define BF_OCOTP_DATA_DATA(v) (v) + +#define HW_OCOTP_LOCK (0x00000030) + +#define BP_OCOTP_LOCK_UNALLOCATED 26 +#define BM_OCOTP_LOCK_UNALLOCATED 0xFC000000 +#define BF_OCOTP_LOCK_UNALLOCATED(v) \ + (((v) << 26) & BM_OCOTP_LOCK_UNALLOCATED) +#define BM_OCOTP_LOCK_PIN 0x02000000 +#define BM_OCOTP_LOCK_DCPKEY_ALT 0x01000000 +#define BM_OCOTP_LOCK_SCC_ALT 0x00800000 +#define BM_OCOTP_LOCK_DCPKEY 0x00400000 +#define BM_OCOTP_LOCK_SWCAP_SHADOW 0x00200000 +#define BM_OCOTP_LOCK_SWCAP 0x00100000 +#define BM_OCOTP_LOCK_HWCAP_SHADOW 0x00080000 +#define BM_OCOTP_LOCK_HWCAP 0x00040000 +#define BM_OCOTP_LOCK_MAC_SHADOW 0x00020000 +#define BM_OCOTP_LOCK_MAC 0x00010000 +#define BM_OCOTP_LOCK_SJC_SHADOW 0x00008000 +#define BM_OCOTP_LOCK_SJC 0x00004000 +#define BM_OCOTP_LOCK_SRK_SHADOW 0x00002000 +#define BM_OCOTP_LOCK_SRK 0x00001000 +#define BM_OCOTP_LOCK_SCC_SHADOW 0x00000800 +#define BM_OCOTP_LOCK_SCC 0x00000400 +#define BM_OCOTP_LOCK_GP_SHADOW 0x00000200 +#define BM_OCOTP_LOCK_GP 0x00000100 +#define BM_OCOTP_LOCK_MEM_MISC_SHADOW 0x00000080 +#define BM_OCOTP_LOCK_MEM_TRIM_SHADOW 0x00000040 +#define BM_OCOTP_LOCK_MEM_TRIM 0x00000020 +#define BM_OCOTP_LOCK_CFG_MISC_SHADOW 0x00000010 +#define BM_OCOTP_LOCK_CFG_BOOT_SHADOW 0x00000008 +#define BM_OCOTP_LOCK_CFG_BOOT 0x00000004 +#define BM_OCOTP_LOCK_CFG_TESTER_SHADOW 0x00000002 +#define BM_OCOTP_LOCK_CFG_TESTER 0x00000001 + +/* + * multi-register-define name HW_OCOTP_CFGn + * base 0x00000040 + * count 7 + * offset 0x10 + */ +#define HW_OCOTP_CFGn(n) (0x00000040 + (n) * 0x10) +#define BP_OCOTP_CFGn_BITS 0 +#define BM_OCOTP_CFGn_BITS 0xFFFFFFFF +#define BF_OCOTP_CFGn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_MEMn + * base 0x000000B0 + * count 6 + * offset 0x10 + */ +#define HW_OCOTP_MEMn(n) (0x000000b0 + (n) * 0x10) +#define BP_OCOTP_MEMn_BITS 0 +#define BM_OCOTP_MEMn_BITS 0xFFFFFFFF +#define BF_OCOTP_MEMn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_GPn + * base 0x00000110 + * count 2 + * offset 0x10 + */ +#define HW_OCOTP_GPn(n) (0x00000110 + (n) * 0x10) +#define BP_OCOTP_GPn_BITS 0 +#define BM_OCOTP_GPn_BITS 0xFFFFFFFF +#define BF_OCOTP_GPn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_SCCn + * base 0x00000130 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_SCCn(n) (0x00000130 + (n) * 0x10) +#define BP_OCOTP_SCCn_BITS 0 +#define BM_OCOTP_SCCn_BITS 0xFFFFFFFF +#define BF_OCOTP_SCCn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_SRKn + * base 0x000001B0 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_SRKn(n) (0x000001b0 + (n) * 0x10) +#define BP_OCOTP_SRKn_BITS 0 +#define BM_OCOTP_SRKn_BITS 0xFFFFFFFF +#define BF_OCOTP_SRKn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_SJC_RESPn + * base 0x00000230 + * count 2 + * offset 0x10 + */ +#define HW_OCOTP_SJC_RESPn(n) (0x00000230 + (n) * 0x10) +#define BP_OCOTP_SJC_RESPn_BITS 0 +#define BM_OCOTP_SJC_RESPn_BITS 0xFFFFFFFF +#define BF_OCOTP_SJC_RESPn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_MACn + * base 0x00000250 + * count 2 + * offset 0x10 + */ +#define HW_OCOTP_MACn(n) (0x00000250 + (n) * 0x10) +#define BP_OCOTP_MACn_BITS 0 +#define BM_OCOTP_MACn_BITS 0xFFFFFFFF +#define BF_OCOTP_MACn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_HWCAPn + * base 0x00000270 + * count 3 + * offset 0x10 + */ +#define HW_OCOTP_HWCAPn(n) (0x00000270 + (n) * 0x10) +#define BP_OCOTP_HWCAPn_BITS 0 +#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF +#define BF_OCOTP_HWCAPn_BITS(v) (v) + +#define HW_OCOTP_SWCAP (0x000002a0) + +#define BP_OCOTP_SWCAP_BITS 0 +#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF +#define BF_OCOTP_SWCAP_BITS(v) (v) + +#define HW_OCOTP_SCS (0x000002b0) +#define HW_OCOTP_SCS_SET (0x000002b4) +#define HW_OCOTP_SCS_CLR (0x000002b8) +#define HW_OCOTP_SCS_TOG (0x000002bc) + +#define BM_OCOTP_SCS_LOCK 0x80000000 +#define BP_OCOTP_SCS_SPARE 1 +#define BM_OCOTP_SCS_SPARE 0x7FFFFFFE +#define BF_OCOTP_SCS_SPARE(v) \ + (((v) << 1) & BM_OCOTP_SCS_SPARE) +#define BM_OCOTP_SCS_HAB_JDE 0x00000001 + +#define HW_OCOTP_VERSION (0x000002c0) + +#define BP_OCOTP_VERSION_MAJOR 24 +#define BM_OCOTP_VERSION_MAJOR 0xFF000000 +#define BF_OCOTP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_OCOTP_VERSION_MAJOR) +#define BP_OCOTP_VERSION_MINOR 16 +#define BM_OCOTP_VERSION_MINOR 0x00FF0000 +#define BF_OCOTP_VERSION_MINOR(v) \ + (((v) << 16) & BM_OCOTP_VERSION_MINOR) +#define BP_OCOTP_VERSION_STEP 0 +#define BM_OCOTP_VERSION_STEP 0x0000FFFF +#define BF_OCOTP_VERSION_STEP(v) \ + (((v) << 0) & BM_OCOTP_VERSION_STEP) +#endif /* __ARCH_ARM___OCOTP_H */ diff --git a/drivers/crypto/dcp_bootstream_ioctl.h b/drivers/crypto/dcp_bootstream_ioctl.h new file mode 100644 index 000000000000..7c0c07d5a72d --- /dev/null +++ b/drivers/crypto/dcp_bootstream_ioctl.h @@ -0,0 +1,32 @@ +/* + * Freescale DCP driver for bootstream update. Only handles the OTP KEY + * case and can only encrypt/decrypt. + * + * Author: Pantelis Antoniou + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef DCP_BOOTSTREAM_IOCTL_H +#define DCP_BOOTSTREAM_IOCTL_H + +/* remember to have included the proper _IO definition + * file before hand. + * For user space it's + */ + +#define DBS_IOCTL_BASE 'd' + +#define DBS_ENC _IOW(DBS_IOCTL_BASE, 0x00, uint8_t[16]) +#define DBS_DEC _IOW(DBS_IOCTL_BASE, 0x01, uint8_t[16]) + +#endif diff --git a/drivers/dma/pxp/Makefile b/drivers/dma/pxp/Makefile new file mode 100644 index 000000000000..88e51a7fb1e2 --- /dev/null +++ b/drivers/dma/pxp/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_MXC_PXP) += pxp_dma.o +obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o diff --git a/drivers/dma/pxp/pxp_device.c b/drivers/dma/pxp/pxp_device.c new file mode 100644 index 000000000000..74176d3da9d3 --- /dev/null +++ b/drivers/dma/pxp/pxp_device.c @@ -0,0 +1,511 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static atomic_t open_count = ATOMIC_INIT(0); + +static DEFINE_SPINLOCK(pxp_mem_lock); +static DEFINE_SPINLOCK(pxp_chan_lock); +static LIST_HEAD(head); +static LIST_HEAD(list); +static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL]; + +struct pxp_chan_handle { + int chan_id; + int hist_status; +}; + +/* To track the allocated memory buffer */ +struct memalloc_record { + struct list_head list; + struct pxp_mem_desc mem; +}; + +struct pxp_chan_info { + int chan_id; + struct dma_chan *dma_chan; + struct list_head list; +}; + +static int pxp_alloc_dma_buffer(struct pxp_mem_desc *mem) +{ + mem->cpu_addr = (unsigned long) + dma_alloc_coherent(NULL, PAGE_ALIGN(mem->size), + (dma_addr_t *) (&mem->phys_addr), + GFP_DMA | GFP_KERNEL); + pr_debug("[ALLOC] mem alloc phys_addr = 0x%x\n", mem->phys_addr); + if ((void *)(mem->cpu_addr) == NULL) { + printk(KERN_ERR "Physical memory allocation error!\n"); + return -1; + } + return 0; +} + +static void pxp_free_dma_buffer(struct pxp_mem_desc *mem) +{ + if (mem->cpu_addr != 0) { + dma_free_coherent(0, PAGE_ALIGN(mem->size), + (void *)mem->cpu_addr, mem->phys_addr); + } +} + +static int pxp_free_buffers(void) +{ + struct memalloc_record *rec, *n; + struct pxp_mem_desc mem; + + list_for_each_entry_safe(rec, n, &head, list) { + mem = rec->mem; + if (mem.cpu_addr != 0) { + pxp_free_dma_buffer(&mem); + pr_debug("[FREE] freed paddr=0x%08X\n", mem.phys_addr); + /* delete from list */ + list_del(&rec->list); + kfree(rec); + } + } + + return 0; +} + +/* Callback function triggered after PxP receives an EOF interrupt */ +static void pxp_dma_done(void *arg) +{ + struct pxp_tx_desc *tx_desc = to_tx_desc(arg); + struct dma_chan *chan = tx_desc->txd.chan; + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + int chan_id = pxp_chan->dma_chan.chan_id; + + pr_debug("DMA Done ISR, chan_id %d\n", chan_id); + + irq_info[chan_id].irq_pending++; + irq_info[chan_id].hist_status = tx_desc->hist_status; + + wake_up_interruptible(&(irq_info[chan_id].waitq)); +} + +static int pxp_ioc_config_chan(unsigned long arg) +{ + struct scatterlist sg[3]; + struct pxp_tx_desc *desc; + struct dma_async_tx_descriptor *txd; + struct pxp_chan_info *info; + struct pxp_config_data pxp_conf; + dma_cookie_t cookie; + int chan_id; + int i, length, ret; + + ret = copy_from_user(&pxp_conf, + (struct pxp_config_data *)arg, + sizeof(struct pxp_config_data)); + if (ret) + return -EFAULT; + + chan_id = pxp_conf.chan_id; + if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL) + return -ENODEV; + + init_waitqueue_head(&(irq_info[chan_id].waitq)); + + /* find the channel */ + spin_lock(&pxp_chan_lock); + list_for_each_entry(info, &list, list) { + if (info->dma_chan->chan_id == chan_id) + break; + } + spin_unlock(&pxp_chan_lock); + + sg_init_table(sg, 3); + + txd = + info->dma_chan->device->device_prep_slave_sg(info->dma_chan, + sg, 3, + DMA_TO_DEVICE, + DMA_PREP_INTERRUPT); + if (!txd) { + pr_err("Error preparing a DMA transaction descriptor.\n"); + return -EIO; + } + + txd->callback_param = txd; + txd->callback = pxp_dma_done; + + desc = to_tx_desc(txd); + + length = desc->len; + for (i = 0; i < length; i++) { + if (i == 0) { /* S0 */ + memcpy(&desc->proc_data, + &pxp_conf.proc_data, + sizeof(struct pxp_proc_data)); + memcpy(&desc->layer_param.s0_param, + &pxp_conf.s0_param, + sizeof(struct pxp_layer_param)); + } else if (i == 1) { /* Output */ + memcpy(&desc->layer_param.out_param, + &pxp_conf.out_param, + sizeof(struct pxp_layer_param)); + } else { + /* OverLay */ + memcpy(&desc->layer_param.ol_param, + &pxp_conf.ol_param, + sizeof(struct pxp_layer_param)); + } + + desc = desc->next; + } + + cookie = txd->tx_submit(txd); + if (cookie < 0) { + pr_err("Error tx_submit\n"); + return -EIO; + } + + return 0; +} + +static int pxp_device_open(struct inode *inode, struct file *filp) +{ + atomic_inc(&open_count); + + return 0; +} + +static int pxp_device_release(struct inode *inode, struct file *filp) +{ + if (atomic_dec_and_test(&open_count)) + pxp_free_buffers(); + + return 0; +} + +static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct memalloc_record *rec, *n; + int request_size, found; + + request_size = vma->vm_end - vma->vm_start; + found = 0; + + pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n", + (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff), + request_size); + + spin_lock(&pxp_mem_lock); + list_for_each_entry_safe(rec, n, &head, list) { + if (rec->mem.phys_addr == (vma->vm_pgoff << PAGE_SHIFT) && + (rec->mem.size <= request_size)) { + found = 1; + break; + } + } + spin_unlock(&pxp_mem_lock); + + if (found == 0) + return -ENOMEM; + + vma->vm_flags |= VM_IO | VM_RESERVED; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + request_size, vma->vm_page_prot) ? -EAGAIN : 0; +} + +static int pxp_device_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + + switch (cmd) { + case PXP_IOC_GET_CHAN: + { + struct pxp_chan_info *info; + dma_cap_mask_t mask; + + pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__); + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + pr_err("%d: alloc err\n", __LINE__); + return -ENOMEM; + } + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_cap_set(DMA_PRIVATE, mask); + info->dma_chan = dma_request_channel(mask, NULL, NULL); + if (!info->dma_chan) { + pr_err("Unsccessfully received channel!\n"); + kfree(info); + return -EBUSY; + } + pr_debug("Successfully received channel." + "chan_id %d\n", info->dma_chan->chan_id); + + spin_lock(&pxp_chan_lock); + list_add_tail(&info->list, &list); + spin_unlock(&pxp_chan_lock); + + if (put_user + (info->dma_chan->chan_id, (u32 __user *) arg)) + return -EFAULT; + + break; + } + case PXP_IOC_PUT_CHAN: + { + int chan_id; + struct pxp_chan_info *info; + + if (get_user(chan_id, (u32 __user *) arg)) + return -EFAULT; + + if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL) + return -ENODEV; + + spin_lock(&pxp_chan_lock); + list_for_each_entry(info, &list, list) { + if (info->dma_chan->chan_id == chan_id) + break; + } + spin_unlock(&pxp_chan_lock); + + pr_debug("%d release chan_id %d\n", __LINE__, + info->dma_chan->chan_id); + /* REVISIT */ + dma_release_channel(info->dma_chan); + spin_lock(&pxp_chan_lock); + list_del_init(&info->list); + spin_unlock(&pxp_chan_lock); + kfree(info); + + break; + } + case PXP_IOC_CONFIG_CHAN: + { + + int ret; + + ret = pxp_ioc_config_chan(arg); + if (ret) + return ret; + + break; + } + case PXP_IOC_START_CHAN: + { + struct pxp_chan_info *info; + int chan_id; + + if (get_user(chan_id, (u32 __user *) arg)) + return -EFAULT; + + /* find the channel */ + spin_lock(&pxp_chan_lock); + list_for_each_entry(info, &list, list) { + if (info->dma_chan->chan_id == chan_id) + break; + } + spin_unlock(&pxp_chan_lock); + + dma_async_issue_pending(info->dma_chan); + + break; + } + case PXP_IOC_GET_PHYMEM: + { + struct memalloc_record *rec; + + rec = kzalloc(sizeof(*rec), GFP_KERNEL); + if (!rec) + return -ENOMEM; + + ret = copy_from_user(&(rec->mem), + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) { + kfree(rec); + return -EFAULT; + } + + pr_debug("[ALLOC] mem alloc size = 0x%x\n", + rec->mem.size); + + ret = pxp_alloc_dma_buffer(&(rec->mem)); + if (ret == -1) { + kfree(rec); + printk(KERN_ERR + "Physical memory allocation error!\n"); + break; + } + ret = copy_to_user((void __user *)arg, &(rec->mem), + sizeof(struct pxp_mem_desc)); + if (ret) { + kfree(rec); + ret = -EFAULT; + break; + } + + spin_lock(&pxp_mem_lock); + list_add(&rec->list, &head); + spin_unlock(&pxp_mem_lock); + + break; + } + case PXP_IOC_PUT_PHYMEM: + { + struct memalloc_record *rec, *n; + struct pxp_mem_desc pxp_mem; + + ret = copy_from_user(&pxp_mem, + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EACCES; + + pr_debug("[FREE] mem freed cpu_addr = 0x%x\n", + pxp_mem.cpu_addr); + if ((void *)pxp_mem.cpu_addr != NULL) + pxp_free_dma_buffer(&pxp_mem); + + spin_lock(&pxp_mem_lock); + list_for_each_entry_safe(rec, n, &head, list) { + if (rec->mem.cpu_addr == pxp_mem.cpu_addr) { + /* delete from list */ + list_del(&rec->list); + kfree(rec); + break; + } + } + spin_unlock(&pxp_mem_lock); + + break; + } + case PXP_IOC_WAIT4CMPLT: + { + struct pxp_chan_handle chan_handle; + int ret, chan_id; + + ret = copy_from_user(&chan_handle, + (struct pxp_chan_handle *)arg, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + + chan_id = chan_handle.chan_id; + if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL) + return -ENODEV; + + if (!wait_event_interruptible_timeout + (irq_info[chan_id].waitq, + (irq_info[chan_id].irq_pending != 0), 2 * HZ)) { + pr_warning("pxp blocking: timeout.\n"); + return -ETIME; + } else if (signal_pending(current)) { + printk(KERN_WARNING + "pxp interrupt received.\n"); + return -ERESTARTSYS; + } else + irq_info[chan_id].irq_pending--; + + chan_handle.hist_status = irq_info[chan_id].hist_status; + ret = copy_to_user((struct pxp_chan_handle *)arg, + &chan_handle, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + break; + } + default: + break; + } + + return 0; +} + +static const struct file_operations pxp_device_fops = { + .open = pxp_device_open, + .release = pxp_device_release, + .ioctl = pxp_device_ioctl, + .mmap = pxp_device_mmap, +}; + +static struct miscdevice pxp_device_miscdev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "pxp_device", + .fops = &pxp_device_fops, +}; + +static int __devinit pxp_device_probe(struct platform_device *pdev) +{ + int ret; + + /* PxP DMA interface */ + dmaengine_get(); + + ret = misc_register(&pxp_device_miscdev); + if (ret) + return ret; + + pr_debug("PxP_Device Probe Successfully\n"); + return 0; +} + +static int __devexit pxp_device_remove(struct platform_device *pdev) +{ + misc_deregister(&pxp_device_miscdev); + + dmaengine_put(); + + return 0; +} + +static struct platform_driver pxp_client_driver = { + .probe = pxp_device_probe, + .remove = __exit_p(pxp_device_remove), + .driver = { + .name = "pxp-device", + .owner = THIS_MODULE, + }, +}; + +static int __init pxp_device_init(void) +{ + return platform_driver_register(&pxp_client_driver); +} + +static void __exit pxp_device_exit(void) +{ + platform_driver_unregister(&pxp_client_driver); +} + +module_init(pxp_device_init); +module_exit(pxp_device_exit); + +MODULE_DESCRIPTION("i.MX PxP client driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/pxp/pxp_dma.c b/drivers/dma/pxp/pxp_dma.c new file mode 100644 index 000000000000..b8648049de89 --- /dev/null +++ b/drivers/dma/pxp/pxp_dma.c @@ -0,0 +1,1438 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regs-pxp.h" + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +static LIST_HEAD(head); + +struct pxp_dma { + struct dma_device dma; +}; + +struct pxps { + struct platform_device *pdev; + struct clk *clk; + void __iomem *base; + int irq; /* PXP IRQ to the CPU */ + + spinlock_t lock; + struct mutex mutex_clk; + int clk_stat; +#define CLK_STAT_OFF 0 +#define CLK_STAT_ON 1 + + struct device *dev; + struct pxp_dma pxp_dma; + struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; + struct work_struct work; + struct workqueue_struct *workqueue; + wait_queue_head_t done; + + /* describes most recent processing configuration */ + struct pxp_config_data pxp_conf_state; + + /* to turn clock off when pxp is inactive */ + struct timer_list clk_timer; +}; + +#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) +#define to_pxp(id) container_of(id, struct pxps, pxp_dma) + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +#define PXP_WAITCON ((__raw_readl(pxp->base + HW_PXP_STAT) & \ + BM_PXP_STAT_IRQ) != BM_PXP_STAT_IRQ) + +static uint32_t pxp_s0_formats[] = { + PXP_PIX_FMT_RGB24, + PXP_PIX_FMT_RGB565, + PXP_PIX_FMT_RGB555, + PXP_PIX_FMT_YUV420P, + PXP_PIX_FMT_YUV422P, +}; + +/* + * PXP common functions + */ +static void dump_pxp_reg(struct pxps *pxp) +{ + dev_dbg(pxp->dev, "PXP_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CTRL)); + dev_dbg(pxp->dev, "PXP_STAT 0x%x", + __raw_readl(pxp->base + HW_PXP_STAT)); + dev_dbg(pxp->dev, "PXP_OUTBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_OUTBUF)); + dev_dbg(pxp->dev, "PXP_OUTBUF2 0x%x", + __raw_readl(pxp->base + HW_PXP_OUTBUF2)); + dev_dbg(pxp->dev, "PXP_OUTSIZE 0x%x", + __raw_readl(pxp->base + HW_PXP_OUTSIZE)); + dev_dbg(pxp->dev, "PXP_S0BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_S0BUF)); + dev_dbg(pxp->dev, "PXP_S0UBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_S0UBUF)); + dev_dbg(pxp->dev, "PXP_S0VBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_S0VBUF)); + dev_dbg(pxp->dev, "PXP_S0PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_S0PARAM)); + dev_dbg(pxp->dev, "PXP_S0BACKGROUND 0x%x", + __raw_readl(pxp->base + HW_PXP_S0BACKGROUND)); + dev_dbg(pxp->dev, "PXP_S0CROP 0x%x", + __raw_readl(pxp->base + HW_PXP_S0CROP)); + dev_dbg(pxp->dev, "PXP_S0SCALE 0x%x", + __raw_readl(pxp->base + HW_PXP_S0SCALE)); + dev_dbg(pxp->dev, "PXP_OLn 0x%x", + __raw_readl(pxp->base + HW_PXP_OLn(0))); + dev_dbg(pxp->dev, "PXP_OLnSIZE 0x%x", + __raw_readl(pxp->base + HW_PXP_OLnSIZE(0))); + dev_dbg(pxp->dev, "PXP_OLnPARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_OLnPARAM(0))); + dev_dbg(pxp->dev, "PXP_CSCCOEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSCCOEF0)); + dev_dbg(pxp->dev, "PXP_CSCCOEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSCCOEF1)); + dev_dbg(pxp->dev, "PXP_CSCCOEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSCCOEF2)); + dev_dbg(pxp->dev, "PXP_CSC2CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2CTRL)); + dev_dbg(pxp->dev, "PXP_CSC2COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF0)); + dev_dbg(pxp->dev, "PXP_CSC2COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF1)); + dev_dbg(pxp->dev, "PXP_CSC2COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2COEF3 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF3)); + dev_dbg(pxp->dev, "PXP_CSC2COEF4 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF4)); + dev_dbg(pxp->dev, "PXP_CSC2COEF5 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF5)); + dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_CTRL)); + dev_dbg(pxp->dev, "PXP_LUT 0x%x", __raw_readl(pxp->base + HW_PXP_LUT)); + dev_dbg(pxp->dev, "PXP_HIST_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST_CTRL)); + dev_dbg(pxp->dev, "PXP_HIST2_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST2_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST4_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST4_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM2 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM2)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM3 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM3)); +} + +static bool is_yuv(pix_fmt) +{ + if ((pix_fmt == PXP_PIX_FMT_YUYV) | + (pix_fmt == PXP_PIX_FMT_UYVY) | + (pix_fmt == PXP_PIX_FMT_Y41P) | + (pix_fmt == PXP_PIX_FMT_YUV444) | + (pix_fmt == PXP_PIX_FMT_NV12) | + (pix_fmt == PXP_PIX_FMT_GREY) | + (pix_fmt == PXP_PIX_FMT_YVU410P) | + (pix_fmt == PXP_PIX_FMT_YUV410P) | + (pix_fmt == PXP_PIX_FMT_YVU420P) | + (pix_fmt == PXP_PIX_FMT_YUV420P) | + (pix_fmt == PXP_PIX_FMT_YUV420P2) | + (pix_fmt == PXP_PIX_FMT_YVU422P) | + (pix_fmt == PXP_PIX_FMT_YUV422P)) { + return true; + } else { + return false; + } +} + +static void pxp_set_ctrl(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 ctrl; + u32 fmt_ctrl; + + /* Configure S0 input format */ + switch (pxp_conf->s0_param.pixel_fmt) { + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__YUV420; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__YUV422; + break; + default: + fmt_ctrl = 0; + } + ctrl = BF_PXP_CTRL_S0_FORMAT(fmt_ctrl); + + /* Configure output format based on out_channel format */ + switch (pxp_conf->out_param.pixel_fmt) { + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__MONOC8; + break; + default: + fmt_ctrl = 0; + } + ctrl |= BF_PXP_CTRL_OUTBUF_FORMAT(fmt_ctrl); + + ctrl |= BM_PXP_CTRL_CROP; + + if (proc_data->scaling) + ctrl |= BM_PXP_CTRL_SCALE; + if (proc_data->vflip) + ctrl |= BM_PXP_CTRL_VFLIP; + if (proc_data->hflip) + ctrl |= BM_PXP_CTRL_HFLIP; + if (proc_data->rotate) + ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90); + + __raw_writel(ctrl, pxp->base + HW_PXP_CTRL); +} + +static int pxp_start(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET); + __raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET); + + return 0; +} + +static void pxp_set_outbuf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + __raw_writel(out_params->paddr, pxp->base + HW_PXP_OUTBUF); + + __raw_writel(BF_PXP_OUTSIZE_WIDTH(out_params->width) | + BF_PXP_OUTSIZE_HEIGHT(out_params->height), + pxp->base + HW_PXP_OUTSIZE); +} + +static void pxp_set_s0colorkey(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (s0_params->color_key == -1) { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_S0COLORKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_S0COLORKEYHIGH); + } else { + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_S0COLORKEYLOW); + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_S0COLORKEYHIGH); + } +} + +static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no]; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_OLCOLORKEYLOW); + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_OLCOLORKEYHIGH); + } else { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_OLCOLORKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_OLCOLORKEYHIGH); + } +} + +static void pxp_set_oln(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + dma_addr_t phys_addr = olparams_data->paddr; + __raw_writel(phys_addr, pxp->base + HW_PXP_OLn(layer_no)); + + /* Fixme */ + __raw_writel(BF_PXP_OLnSIZE_WIDTH(olparams_data->width >> 3) | + BF_PXP_OLnSIZE_HEIGHT(olparams_data->height >> 3), + pxp->base + HW_PXP_OLnSIZE(layer_no)); +} + +static void pxp_set_olparam(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + u32 olparam; + + olparam = BF_PXP_OLnPARAM_ALPHA(olparams_data->global_alpha); + if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB24) + olparam |= + BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB888); + else + olparam |= + BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB565); + if (olparams_data->global_alpha_enable) + olparam |= + BF_PXP_OLnPARAM_ALPHA_CNTL + (BV_PXP_OLnPARAM_ALPHA_CNTL__Override); + if (olparams_data->color_key_enable) + olparam |= BM_PXP_OLnPARAM_ENABLE_COLORKEY; + if (olparams_data->combine_enable) + olparam |= BM_PXP_OLnPARAM_ENABLE; + __raw_writel(olparam, pxp->base + HW_PXP_OLnPARAM(layer_no)); +} + +static void pxp_set_s0param(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0params_data = &pxp_conf->s0_param; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 s0param; + + s0param = BF_PXP_S0PARAM_XBASE(proc_data->drect.left >> 3); + s0param |= BF_PXP_S0PARAM_YBASE(proc_data->drect.top >> 3); + s0param |= BF_PXP_S0PARAM_WIDTH(s0params_data->width >> 3); + s0param |= BF_PXP_S0PARAM_HEIGHT(s0params_data->height >> 3); + __raw_writel(s0param, pxp->base + HW_PXP_S0PARAM); +} + +static void pxp_set_s0crop(struct pxps *pxp) +{ + u32 s0crop; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + + s0crop = BF_PXP_S0CROP_XBASE(proc_data->srect.left >> 3); + s0crop |= BF_PXP_S0CROP_YBASE(proc_data->srect.top >> 3); + s0crop |= BF_PXP_S0CROP_WIDTH(proc_data->drect.width >> 3); + s0crop |= BF_PXP_S0CROP_HEIGHT(proc_data->drect.height >> 3); + __raw_writel(s0crop, pxp->base + HW_PXP_S0CROP); +} + +static int pxp_set_scaling(struct pxps *pxp) +{ + int ret = 0; + u32 xscale, yscale, s0scale; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + struct pxp_layer_param *s0params_data = &pxp->pxp_conf_state.s0_param; + + if ((s0params_data->pixel_fmt != PXP_PIX_FMT_YUV420P) && + (s0params_data->pixel_fmt != PXP_PIX_FMT_YUV422P)) { + proc_data->scaling = 0; + ret = -EINVAL; + goto out; + } + + if ((proc_data->srect.width == proc_data->drect.width) && + (proc_data->srect.height == proc_data->drect.height)) { + proc_data->scaling = 0; + __raw_writel(0x10001000, pxp->base + HW_PXP_S0SCALE); + goto out; + } + + proc_data->scaling = 1; + xscale = proc_data->srect.width * 0x1000 / proc_data->drect.width; + yscale = proc_data->srect.height * 0x1000 / proc_data->drect.height; + if (xscale > PXP_DOWNSCALE_THRESHOLD) + xscale = PXP_DOWNSCALE_THRESHOLD; + if (yscale > PXP_DOWNSCALE_THRESHOLD) + yscale = PXP_DOWNSCALE_THRESHOLD; + s0scale = BF_PXP_S0SCALE_YSCALE(yscale) | BF_PXP_S0SCALE_XSCALE(xscale); + __raw_writel(s0scale, pxp->base + HW_PXP_S0SCALE); + +out: + pxp_set_ctrl(pxp); + + return ret; +} + +static void pxp_set_bg(struct pxps *pxp) +{ + __raw_writel(pxp->pxp_conf_state.proc_data.bgcolor, + pxp->base + HW_PXP_S0BACKGROUND); +} + +static void pxp_set_lut(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + u32 reg_val; + int i; + + if (pxp_conf->proc_data.lut_transform == PXP_LUT_NONE) { + __raw_writel(BM_PXP_LUT_CTRL_BYPASS, + pxp->base + HW_PXP_LUT_CTRL); + } else if (pxp_conf->proc_data.lut_transform == PXP_LUT_INVERT) { + /* Fill out LUT table with 8-bit inverted values */ + + /* Initialize LUT address to 0 and clear bypass bit */ + __raw_writel(0, pxp->base + HW_PXP_LUT_CTRL); + + /* LUT address pointer auto-increments after each data write */ + for (i = 0; i < 256; i++) { + reg_val = + __raw_readl(pxp->base + + HW_PXP_LUT_CTRL) & BM_PXP_LUT_CTRL_ADDR; + reg_val = ~reg_val & BM_PXP_LUT_DATA; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT); + } + } +} + +static void pxp_set_csc(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + bool input_is_YUV = is_yuv(s0_params->pixel_fmt); + bool output_is_YUV = is_yuv(out_params->pixel_fmt); + + if (input_is_YUV && output_is_YUV) { + /* + * Input = YUV, Output = YUV + * No CSC unless we need to do combining + */ + if (ol_params->combine_enable) { + /* Must convert to RGB for combining with RGB overlay */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x04030000, pxp->base + HW_PXP_CSCCOEF0); + __raw_writel(0x01230208, pxp->base + HW_PXP_CSCCOEF1); + __raw_writel(0x076b079c, pxp->base + HW_PXP_CSCCOEF2); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2COEF5); + } else { + /* Input & Output both YUV, so bypass both CSCs */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL); + } + } else if (input_is_YUV && !output_is_YUV) { + /* + * Input = YUV, Output = RGB + * Use CSC1 to convert to RGB + */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x84ab01f0, pxp->base + HW_PXP_CSCCOEF0); + __raw_writel(0x01230204, pxp->base + HW_PXP_CSCCOEF1); + __raw_writel(0x0730079c, pxp->base + HW_PXP_CSCCOEF2); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL); + } else if (!input_is_YUV && output_is_YUV) { + /* + * Input = RGB, Output = YUV + * Use CSC2 to convert to YUV + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2COEF5); + } else { + /* + * Input = RGB, Output = RGB + * Input & Output both RGB, so bypass both CSCs + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL); + } + + /* YCrCb colorspace */ + /* Not sure when we use this...no YCrCb formats are defined for PxP */ + /* + __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR); + __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR); + __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR); + */ + +} + +static void pxp_set_s0buf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + dma_addr_t Y, U, V; + + Y = s0_params->paddr; + __raw_writel(Y, pxp->base + HW_PXP_S0BUF); + if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GREY)) { + /* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */ + int s = 2; + U = Y + (s0_params->width * s0_params->height); + V = U + ((s0_params->width * s0_params->height) >> s); + __raw_writel(U, pxp->base + HW_PXP_S0UBUF); + __raw_writel(V, pxp->base + HW_PXP_S0VBUF); + } +} + +/** + * pxp_config() - configure PxP for a processing task + * @pxps: PXP context. + * @pxp_chan: PXP channel. + * @return: 0 on success or negative error code on failure. + */ +static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) +{ + struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state; + int ol_nr; + int i; + + /* Configure PxP regs */ + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + ol_nr = pxp_conf_data->layer_nr - 2; + while (ol_nr > 0) { + i = pxp_conf_data->layer_nr - 2 - ol_nr; + pxp_set_oln(i, pxp); + pxp_set_olparam(i, pxp); + /* only the color key in higher overlay will take effect. */ + pxp_set_olcolorkey(i, pxp); + ol_nr--; + } + pxp_set_s0colorkey(pxp); + pxp_set_csc(pxp); + pxp_set_bg(pxp); + pxp_set_lut(pxp); + + pxp_set_s0buf(pxp); + pxp_set_outbuf(pxp); + + return 0; +} + +static void pxp_clk_enable(struct pxps *pxp) +{ + mutex_lock(&pxp->mutex_clk); + + if (pxp->clk_stat == CLK_STAT_ON) { + mutex_unlock(&pxp->mutex_clk); + return; + } + + clk_enable(pxp->clk); + pxp->clk_stat = CLK_STAT_ON; + + mutex_unlock(&pxp->mutex_clk); +} + +static void pxp_clk_disable(struct pxps *pxp) +{ + mutex_lock(&pxp->mutex_clk); + + if (pxp->clk_stat == CLK_STAT_OFF) { + mutex_unlock(&pxp->mutex_clk); + return; + } + + clk_disable(pxp->clk); + pxp->clk_stat = CLK_STAT_OFF; + + mutex_unlock(&pxp->mutex_clk); +} + +static void pxp_clkoff_timer(unsigned long arg) +{ + struct pxps *pxp = (struct pxps *)arg; + + pxp_clk_disable(pxp); +} + +static struct pxp_tx_desc *pxpdma_first_active(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->active_list.next, struct pxp_tx_desc, list); +} + +static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); +} + +/* called with pxp_chan->lock held */ +static void __pxpdma_dostart(struct pxp_channel *pxp_chan) +{ + struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child; + int i = 0; + + /* so far we presume only one transaction on active_list */ + /* S0 */ + desc = pxpdma_first_active(pxp_chan); + memcpy(&pxp->pxp_conf_state.s0_param, + &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); + memcpy(&pxp->pxp_conf_state.proc_data, + &desc->proc_data, sizeof(struct pxp_proc_data)); + + /* Save PxP configuration */ + list_for_each_entry(child, &desc->txd.tx_list, list) { + if (i == 0) { /* Output */ + memcpy(&pxp->pxp_conf_state.out_param, + &child->layer_param.out_param, + sizeof(struct pxp_layer_param)); + } else { /* Overlay */ + memcpy(&pxp->pxp_conf_state.ol_param[i - 1], + &child->layer_param.ol_param, + sizeof(struct pxp_layer_param)); + } + + i++; + } + pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.s0_param.width, + pxp->pxp_conf_state.s0_param.height, + pxp->pxp_conf_state.s0_param.paddr); + pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.out_param.width, + pxp->pxp_conf_state.out_param.height, + pxp->pxp_conf_state.out_param.paddr); +} + +static void pxpdma_dostart_work(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + struct pxp_channel *pxp_chan = NULL; + unsigned long flags, flags1; + + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + spin_lock_irqsave(&pxp->lock, flags); + if (list_empty(&head)) { + spin_unlock_irqrestore(&pxp->lock, flags); + return; + } + + pxp_chan = list_entry(head.next, struct pxp_channel, list); + + spin_lock_irqsave(&pxp_chan->lock, flags1); + if (!list_empty(&pxp_chan->active_list)) { + struct pxp_tx_desc *desc; + /* REVISIT */ + desc = pxpdma_first_active(pxp_chan); + __pxpdma_dostart(pxp_chan); + } + spin_unlock_irqrestore(&pxp_chan->lock, flags1); + + /* Configure PxP */ + pxp_config(pxp, pxp_chan); + + pxp_start(pxp); + + spin_unlock_irqrestore(&pxp->lock, flags); +} + +static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct list_head *list) +{ + struct pxp_tx_desc *desc = NULL; + do { + desc = pxpdma_first_queued(pxp_chan); + list_move_tail(&desc->list, list); + } while (!list_empty(&pxp_chan->queue)); +} + +static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct pxp_tx_desc *desc = to_tx_desc(tx); + struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); + dma_cookie_t cookie; + unsigned long flags; + + dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); + + mutex_lock(&pxp_chan->chan_mutex); + + cookie = pxp_chan->dma_chan.cookie; + + if (++cookie < 0) + cookie = 1; + + /* from dmaengine.h: "last cookie value returned to client" */ + pxp_chan->dma_chan.cookie = cookie; + tx->cookie = cookie; + + /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ + spin_lock_irqsave(&pxp_chan->lock, flags); + + /* Here we add the tx descriptor to our PxP task queue. */ + list_add_tail(&desc->list, &pxp_chan->queue); + + spin_unlock_irqrestore(&pxp_chan->lock, flags); + + dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); + + mutex_unlock(&pxp_chan->chan_mutex); + return cookie; +} + +/* Called with pxp_chan->chan_mutex held */ +static int pxp_desc_alloc(struct pxp_channel *pxp_chan, int n) +{ + struct pxp_tx_desc *desc = vmalloc(n * sizeof(struct pxp_tx_desc)); + + if (!desc) + return -ENOMEM; + + pxp_chan->n_tx_desc = n; + pxp_chan->desc = desc; + INIT_LIST_HEAD(&pxp_chan->active_list); + INIT_LIST_HEAD(&pxp_chan->queue); + INIT_LIST_HEAD(&pxp_chan->free_list); + + while (n--) { + struct dma_async_tx_descriptor *txd = &desc->txd; + + memset(txd, 0, sizeof(*txd)); + dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); + txd->tx_submit = pxp_tx_submit; + + list_add(&desc->list, &pxp_chan->free_list); + + desc++; + } + + return 0; +} + +/** + * pxp_init_channel() - initialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_init_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + unsigned long flags; + struct pxps *pxp = to_pxp(pxp_dma); + int ret = 0, n_desc = 0; + + /* + * We are using _virtual_ channel here. + * Each channel contains all parameters of corresponding layers + * for one transaction; each layer is represented as one descriptor + * (i.e., pxp_tx_desc) here. + */ + + spin_lock_irqsave(&pxp->lock, flags); + + /* max desc nr: S0+OL+OUT = 1+8+1 */ + n_desc = 16; + + spin_unlock_irqrestore(&pxp->lock, flags); + + if (n_desc && !pxp_chan->desc) + ret = pxp_desc_alloc(pxp_chan, n_desc); + + return ret; +} + +/** + * pxp_uninit_channel() - uninitialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_uninit_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + int ret = 0; + + if (pxp_chan->desc) + vfree(pxp_chan->desc); + + pxp_chan->desc = NULL; + + return ret; +} + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = dev_id; + struct pxp_channel *pxp_chan; + struct pxp_tx_desc *desc; + dma_async_tx_callback callback; + void *callback_param; + unsigned long flags, flags1; + u32 hist_status; + + dump_pxp_reg(pxp); + + hist_status = + __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS; + + __raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR); + + mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(4000)); + + spin_lock_irqsave(&pxp->lock, flags); + + if (list_empty(&head)) { + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + spin_lock_irqsave(&pxp_chan->lock, flags1); + pxp_chan = list_entry(head.next, struct pxp_channel, list); + list_del_init(&pxp_chan->list); + + if (list_empty(&pxp_chan->active_list)) { + pr_debug("PXP_IRQ pxp_chan->active_list empty. chan_id %d\n", + pxp_chan->dma_chan.chan_id); + spin_unlock_irqrestore(&pxp_chan->lock, flags1); + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + /* Get descriptor and call callback */ + desc = pxpdma_first_active(pxp_chan); + + pxp_chan->completed = desc->txd.cookie; + + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + /* Send histogram status back to caller */ + desc->hist_status = hist_status; + + if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) + callback(callback_param); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + list_splice_init(&desc->txd.tx_list, &pxp_chan->free_list); + list_move(&desc->list, &pxp_chan->free_list); + + list_del(&pxp_chan->list); + + wake_up(&pxp->done); + + spin_unlock_irqrestore(&pxp_chan->lock, flags1); + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +static struct pxp_tx_desc *pxp_desc_get(struct pxp_channel *pxp_chan) +{ + struct pxp_tx_desc *desc, *_desc; + struct pxp_tx_desc *ret = NULL; + unsigned long flags; + + spin_lock_irqsave(&pxp_chan->lock, flags); + list_for_each_entry_safe(desc, _desc, &pxp_chan->free_list, list) { + list_del_init(&desc->list); + ret = desc; + break; + } + spin_unlock_irqrestore(&pxp_chan->lock, flags); + + return ret; +} + +static void pxpdma_desc_put(struct pxp_channel *pxp_chan, + struct pxp_tx_desc *desc) +{ + if (desc) { + struct device *dev = &pxp_chan->dma_chan.dev->device; + struct pxp_tx_desc *child; + unsigned long flags; + + spin_lock_irqsave(&pxp_chan->lock, flags); + list_for_each_entry(child, &desc->txd.tx_list, list) + dev_info(dev, "moving child desc %p to freelist\n", child); + list_splice_init(&desc->txd.tx_list, &pxp_chan->free_list); + dev_info(dev, "moving desc %p to freelist\n", desc); + list_add(&desc->list, &pxp_chan->free_list); + spin_unlock_irqrestore(&pxp_chan->lock, flags); + } +} + +/* Allocate and initialise a transfer descriptor. */ +static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, + struct scatterlist + *sgl, + unsigned int sg_len, + enum dma_data_direction + direction, + unsigned long tx_flags) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *first = NULL, *prev = NULL; + struct scatterlist *sg; + unsigned long flags; + dma_addr_t phys_addr; + int i; + + if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) { + dev_err(chan->device->dev, "Invalid DMA direction %d!\n", + direction); + return NULL; + } + + if (unlikely(sg_len < 2)) + return NULL; + + spin_lock_irqsave(&pxp_chan->lock, flags); + for_each_sg(sgl, sg, sg_len, i) { + desc = pxp_desc_get(pxp_chan); + if (!desc) { + pxpdma_desc_put(pxp_chan, first); + dev_err(chan->device->dev, "Can't get DMA desc.\n"); + spin_unlock_irqrestore(&pxp_chan->lock, flags); + return NULL; + } + + phys_addr = sg_dma_address(sg); + + if (!first) { + first = desc; + + desc->layer_param.s0_param.paddr = phys_addr; + } else { + list_add_tail(&desc->list, &first->txd.tx_list); + prev->next = desc; + desc->next = NULL; + + if (i == 1) + desc->layer_param.out_param.paddr = phys_addr; + else + desc->layer_param.ol_param.paddr = phys_addr; + } + + prev = desc; + } + spin_unlock_irqrestore(&pxp_chan->lock, flags); + + pxp->pxp_conf_state.layer_nr = sg_len; + first->txd.flags = tx_flags; + first->len = sg_len; + pr_debug("%s:%d first %p, first->len %d, flags %08x\n", + __func__, __LINE__, first, first->len, first->txd.flags); + + return &first->txd; +} + +static void pxp_issue_pending(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + unsigned long flags0, flags; + + spin_lock_irqsave(&pxp->lock, flags0); + spin_lock_irqsave(&pxp_chan->lock, flags); + + if (!list_empty(&pxp_chan->queue)) { + pxpdma_dequeue(pxp_chan, &pxp_chan->active_list); + pxp_chan->status = PXP_CHANNEL_READY; + list_add_tail(&pxp_chan->list, &head); + } else { + spin_unlock_irqrestore(&pxp_chan->lock, flags); + spin_unlock_irqrestore(&pxp->lock, flags0); + return; + } + spin_unlock_irqrestore(&pxp_chan->lock, flags); + spin_unlock_irqrestore(&pxp->lock, flags0); + + pxp_clk_enable(pxp); + if (!wait_event_interruptible_timeout(pxp->done, PXP_WAITCON, 2 * HZ) || + signal_pending(current)) { + pxp_clk_disable(pxp); + return; + } + + queue_work(pxp->workqueue, &pxp->work); +} + +static void __pxp_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + unsigned long flags; + + cancel_work_sync(&to_pxp(pxp_dma)->work); + + /* pchan->queue is modified in ISR, have to spinlock */ + spin_lock_irqsave(&pxp_chan->lock, flags); + list_splice_init(&pxp_chan->queue, &pxp_chan->free_list); + list_splice_init(&pxp_chan->active_list, &pxp_chan->free_list); + + spin_unlock_irqrestore(&pxp_chan->lock, flags); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; +} + +static void pxp_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + mutex_lock(&pxp_chan->chan_mutex); + __pxp_terminate_all(chan); + mutex_unlock(&pxp_chan->chan_mutex); +} + +static int pxp_alloc_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + int ret; + + /* dmaengine.c now guarantees to only offer free channels */ + BUG_ON(chan->client_count > 1); + WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); + + chan->cookie = 1; + pxp_chan->completed = -ENXIO; + + pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); + ret = pxp_init_channel(pxp_dma, pxp_chan); + if (ret < 0) + goto err_chan; + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", + chan->chan_id, pxp_chan->eof_irq); + + return ret; + +err_chan: + return ret; +} + +static void pxp_free_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + + mutex_lock(&pxp_chan->chan_mutex); + + __pxp_terminate_all(chan); + + pxp_chan->status = PXP_CHANNEL_FREE; + + pxp_uninit_channel(pxp_dma, pxp_chan); + + mutex_unlock(&pxp_chan->chan_mutex); +} + +static enum dma_status pxp_is_tx_complete(struct dma_chan *chan, + dma_cookie_t cookie, + dma_cookie_t *done, + dma_cookie_t *used) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + if (done) + *done = pxp_chan->completed; + if (used) + *used = chan->cookie; + if (cookie != chan->cookie) + return DMA_ERROR; + return DMA_SUCCESS; +} + +static int pxp_hw_init(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 reg_val; + int i; + + /* Pull PxP out of reset */ + __raw_writel(0, pxp->base + HW_PXP_CTRL); + + /* Config defaults */ + + /* Initialize non-channel-specific PxP parameters */ + proc_data->drect.left = proc_data->srect.left = 0; + proc_data->drect.top = proc_data->srect.top = 0; + proc_data->drect.width = proc_data->srect.width = 0; + proc_data->drect.height = proc_data->srect.height = 0; + proc_data->scaling = 0; + proc_data->hflip = 0; + proc_data->vflip = 0; + proc_data->rotate = 0; + proc_data->bgcolor = 0; + + /* Initialize S0 channel parameters */ + pxp_conf->s0_param.pixel_fmt = pxp_s0_formats[0]; + pxp_conf->s0_param.width = 0; + pxp_conf->s0_param.height = 0; + pxp_conf->s0_param.color_key = -1; + pxp_conf->s0_param.color_key_enable = false; + + /* Initialize OL channel parameters */ + for (i = 0; i < 8; i++) { + pxp_conf->ol_param[i].combine_enable = false; + pxp_conf->ol_param[i].width = 0; + pxp_conf->ol_param[i].height = 0; + pxp_conf->ol_param[i].pixel_fmt = PXP_PIX_FMT_RGB565; + pxp_conf->ol_param[i].color_key_enable = false; + pxp_conf->ol_param[i].color_key = -1; + pxp_conf->ol_param[i].global_alpha_enable = false; + pxp_conf->ol_param[i].global_alpha = 0; + pxp_conf->ol_param[i].local_alpha_enable = false; + } + + /* Initialize Output channel parameters */ + pxp_conf->out_param.width = 0; + pxp_conf->out_param.height = 0; + pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_RGB565; + + proc_data->overlay_state = 0; + + /* Write default h/w config */ + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + for (i = 0; i < 8; i++) { + pxp_set_oln(i, pxp); + pxp_set_olparam(i, pxp); + pxp_set_olcolorkey(i, pxp); + } + pxp_set_s0colorkey(pxp); + pxp_set_csc(pxp); + pxp_set_bg(pxp); + pxp_set_lut(pxp); + + /* One-time histogram configuration */ + reg_val = + BF_PXP_HIST_CTRL_PANEL_MODE(BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST_CTRL); + + reg_val = BF_PXP_HIST2_PARAM_VALUE0(0x00) | + BF_PXP_HIST2_PARAM_VALUE1(0x00F); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST2_PARAM); + + reg_val = BF_PXP_HIST4_PARAM_VALUE0(0x00) | + BF_PXP_HIST4_PARAM_VALUE1(0x05) | + BF_PXP_HIST4_PARAM_VALUE2(0x0A) | BF_PXP_HIST4_PARAM_VALUE3(0x0F); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST4_PARAM); + + reg_val = BF_PXP_HIST8_PARAM0_VALUE0(0x00) | + BF_PXP_HIST8_PARAM0_VALUE1(0x02) | + BF_PXP_HIST8_PARAM0_VALUE2(0x04) | BF_PXP_HIST8_PARAM0_VALUE3(0x06); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM0); + reg_val = BF_PXP_HIST8_PARAM1_VALUE4(0x09) | + BF_PXP_HIST8_PARAM1_VALUE5(0x0B) | + BF_PXP_HIST8_PARAM1_VALUE6(0x0D) | BF_PXP_HIST8_PARAM1_VALUE7(0x0F); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM1); + + reg_val = BF_PXP_HIST16_PARAM0_VALUE0(0x00) | + BF_PXP_HIST16_PARAM0_VALUE1(0x01) | + BF_PXP_HIST16_PARAM0_VALUE2(0x02) | + BF_PXP_HIST16_PARAM0_VALUE3(0x03); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM0); + reg_val = BF_PXP_HIST16_PARAM1_VALUE4(0x04) | + BF_PXP_HIST16_PARAM1_VALUE5(0x05) | + BF_PXP_HIST16_PARAM1_VALUE6(0x06) | + BF_PXP_HIST16_PARAM1_VALUE7(0x07); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM1); + reg_val = BF_PXP_HIST16_PARAM2_VALUE8(0x08) | + BF_PXP_HIST16_PARAM2_VALUE9(0x09) | + BF_PXP_HIST16_PARAM2_VALUE10(0x0A) | + BF_PXP_HIST16_PARAM2_VALUE11(0x0B); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM2); + reg_val = BF_PXP_HIST16_PARAM3_VALUE12(0x0C) | + BF_PXP_HIST16_PARAM3_VALUE13(0x0D) | + BF_PXP_HIST16_PARAM3_VALUE14(0x0E) | + BF_PXP_HIST16_PARAM3_VALUE15(0x0F); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM3); + + return 0; +} + +static int pxp_dma_init(struct pxps *pxp) +{ + struct pxp_dma *pxp_dma = &pxp->pxp_dma; + struct dma_device *dma = &pxp_dma->dma; + int i; + + dma_cap_set(DMA_SLAVE, dma->cap_mask); + dma_cap_set(DMA_PRIVATE, dma->cap_mask); + + /* Compulsory common fields */ + dma->dev = pxp->dev; + dma->device_alloc_chan_resources = pxp_alloc_chan_resources; + dma->device_free_chan_resources = pxp_free_chan_resources; + dma->device_is_tx_complete = pxp_is_tx_complete; + dma->device_issue_pending = pxp_issue_pending; + + /* Compulsory for DMA_SLAVE fields */ + dma->device_prep_slave_sg = pxp_prep_slave_sg; + dma->device_terminate_all = pxp_terminate_all; + + /* Initialize PxP Channels */ + INIT_LIST_HEAD(&dma->channels); + for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { + struct pxp_channel *pxp_chan = pxp->channel + i; + struct dma_chan *dma_chan = &pxp_chan->dma_chan; + + spin_lock_init(&pxp_chan->lock); + mutex_init(&pxp_chan->chan_mutex); + + /* Only one EOF IRQ for PxP, shared by all channels */ + pxp_chan->eof_irq = pxp->irq; + pxp_chan->status = PXP_CHANNEL_FREE; + pxp_chan->completed = -ENXIO; + snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), + "PXP EOF %d", i); + + dma_chan->device = &pxp_dma->dma; + dma_chan->cookie = 1; + dma_chan->chan_id = i; + list_add_tail(&dma_chan->device_node, &dma->channels); + } + + return dma_async_device_register(&pxp_dma->dma); +} + +static int pxp_probe(struct platform_device *pdev) +{ + struct pxps *pxp; + struct resource *res; + int irq; + int err = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0); + if (!res || irq < 0) { + err = -ENODEV; + goto exit; + } + + pxp = kzalloc(sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + pxp->dev = &pdev->dev; + + platform_set_drvdata(pdev, pxp); + pxp->irq = irq; + + spin_lock_init(&pxp->lock); + mutex_init(&pxp->mutex_clk); + + if (!request_mem_region(res->start, resource_size(res), "pxp-mem")) { + err = -EBUSY; + goto freepxp; + } + + pxp->base = ioremap(res->start, SZ_4K); + pxp->pdev = pdev; + + pxp->clk = clk_get(NULL, "pxp_axi"); + clk_enable(pxp->clk); + + err = pxp_hw_init(pxp); + if (err) { + dev_err(&pdev->dev, "failed to initialize hardware\n"); + goto release; + } + clk_disable(pxp->clk); + + err = request_irq(pxp->irq, pxp_irq, 0, "pxp-irq", pxp); + if (err) + goto release; + /* Initialize DMA engine */ + err = pxp_dma_init(pxp); + if (err < 0) + goto err_dma_init; + + init_waitqueue_head(&pxp->done); + INIT_WORK(&pxp->work, pxpdma_dostart_work); + pxp->workqueue = create_singlethread_workqueue("pxp_dma"); + init_timer(&pxp->clk_timer); + pxp->clk_timer.function = pxp_clkoff_timer; + pxp->clk_timer.data = (unsigned long)pxp; +exit: + return err; +err_dma_init: + free_irq(pxp->irq, pxp); +release: + release_mem_region(res->start, resource_size(res)); +freepxp: + kfree(pxp); + dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe function\n"); + return err; +} + +static int __devexit pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + cancel_work_sync(&pxp->work); + + del_timer_sync(&pxp->clk_timer); + free_irq(pxp->irq, pxp); + clk_disable(pxp->clk); + clk_put(pxp->clk); + iounmap(pxp->base); + + kfree(pxp); + + return 0; +} + +#ifdef CONFIG_PM +static int pxp_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + pxp_clk_enable(pxp); + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} + +static int pxp_resume(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + pxp_clk_enable(pxp); + /* Pull PxP out of reset */ + __raw_writel(0, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +static struct platform_driver pxp_driver = { + .driver = { + .name = "mxc-pxp", + }, + .probe = pxp_probe, + .remove = __exit_p(pxp_remove), + .suspend = pxp_suspend, + .resume = pxp_resume, +}; + +static int __init pxp_init(void) +{ + return platform_driver_register(&pxp_driver); +} + +subsys_initcall(pxp_init); + +static void __exit pxp_exit(void) +{ + platform_driver_unregister(&pxp_driver); +} + +module_exit(pxp_exit); + +MODULE_DESCRIPTION("i.MX PxP driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/pxp/regs-pxp.h b/drivers/dma/pxp/regs-pxp.h new file mode 100644 index 000000000000..b0c1b00fdfa0 --- /dev/null +++ b/drivers/dma/pxp/regs-pxp.h @@ -0,0 +1,949 @@ +/* + * Freescale PXP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.6 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BM_PXP_CTRL_RSVD 0x20000000 +#define BM_PXP_CTRL_EN_REPEAT 0x10000000 +#define BP_PXP_CTRL_INTERLACED_OUTPUT 26 +#define BM_PXP_CTRL_INTERLACED_OUTPUT 0x0C000000 +#define BF_PXP_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 26) & BM_PXP_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_CTRL_INTERLACED_INPUT 24 +#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 +#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ + (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) +#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_ALPHA_OUTPUT 0x00400000 +#define BM_PXP_CTRL_IN_PLACE 0x00200000 +#define BM_PXP_CTRL_DELTA 0x00100000 +#define BM_PXP_CTRL_CROP 0x00080000 +#define BM_PXP_CTRL_SCALE 0x00040000 +#define BM_PXP_CTRL_UPSAMPLE 0x00020000 +#define BM_PXP_CTRL_SUBSAMPLE 0x00010000 +#define BP_PXP_CTRL_S0_FORMAT 12 +#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 +#define BF_PXP_CTRL_S0_FORMAT(v) \ + (((v) << 12) & BM_PXP_CTRL_S0_FORMAT) +#define BV_PXP_CTRL_S0_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_S0_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_S0_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_S0_FORMAT__YUV422 0x8 +#define BV_PXP_CTRL_S0_FORMAT__YUV420 0x9 +#define BV_PXP_CTRL_S0_FORMAT__UYVY1P422 0xA +#define BV_PXP_CTRL_S0_FORMAT__VYUY1P422 0xB +#define BV_PXP_CTRL_S0_FORMAT__YUV2P422 0xC +#define BV_PXP_CTRL_S0_FORMAT__YUV2P420 0xD +#define BV_PXP_CTRL_S0_FORMAT__YVU2P422 0xE +#define BV_PXP_CTRL_S0_FORMAT__YVU2P420 0xF +#define BM_PXP_CTRL_VFLIP 0x00000800 +#define BM_PXP_CTRL_HFLIP 0x00000400 +#define BP_PXP_CTRL_ROTATE 8 +#define BM_PXP_CTRL_ROTATE 0x00000300 +#define BF_PXP_CTRL_ROTATE(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE) +#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 +#define BP_PXP_CTRL_OUTBUF_FORMAT 4 +#define BM_PXP_CTRL_OUTBUF_FORMAT 0x000000F0 +#define BF_PXP_CTRL_OUTBUF_FORMAT(v) \ + (((v) << 4) & BM_PXP_CTRL_OUTBUF_FORMAT) +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB8888 0x0 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888P 0x2 +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB1555 0x3 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV444 0x7 +#define BV_PXP_CTRL_OUTBUF_FORMAT__MONOC8 0x8 +#define BV_PXP_CTRL_OUTBUF_FORMAT__MONOC4 0x9 +#define BV_PXP_CTRL_OUTBUF_FORMAT__UYVY1P422 0xA +#define BV_PXP_CTRL_OUTBUF_FORMAT__VYUY1P422 0xB +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P422 0xC +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P420 0xD +#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P422 0xE +#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P420 0xF +#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000008 +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_RSVD2 8 +#define BM_PXP_STAT_RSVD2 0x0000FF00 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 8) & BM_PXP_STAT_RSVD2) +#define BP_PXP_STAT_AXI_ERROR_ID 4 +#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 +#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 +#define BM_PXP_STAT_IRQ 0x00000001 + +#define HW_PXP_OUTBUF (0x00000020) + +#define BP_PXP_OUTBUF_ADDR 0 +#define BM_PXP_OUTBUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUTBUF_ADDR(v) (v) + +#define HW_PXP_OUTBUF2 (0x00000030) + +#define BP_PXP_OUTBUF2_ADDR 0 +#define BM_PXP_OUTBUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUTBUF2_ADDR(v) (v) + +#define HW_PXP_OUTSIZE (0x00000040) + +#define BP_PXP_OUTSIZE_ALPHA 24 +#define BM_PXP_OUTSIZE_ALPHA 0xFF000000 +#define BF_PXP_OUTSIZE_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUTSIZE_ALPHA) +#define BP_PXP_OUTSIZE_WIDTH 12 +#define BM_PXP_OUTSIZE_WIDTH 0x00FFF000 +#define BF_PXP_OUTSIZE_WIDTH(v) \ + (((v) << 12) & BM_PXP_OUTSIZE_WIDTH) +#define BP_PXP_OUTSIZE_HEIGHT 0 +#define BM_PXP_OUTSIZE_HEIGHT 0x00000FFF +#define BF_PXP_OUTSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OUTSIZE_HEIGHT) + +#define HW_PXP_S0BUF (0x00000050) + +#define BP_PXP_S0BUF_ADDR 0 +#define BM_PXP_S0BUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0BUF_ADDR(v) (v) + +#define HW_PXP_S0UBUF (0x00000060) + +#define BP_PXP_S0UBUF_ADDR 0 +#define BM_PXP_S0UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0UBUF_ADDR(v) (v) + +#define HW_PXP_S0VBUF (0x00000070) + +#define BP_PXP_S0VBUF_ADDR 0 +#define BM_PXP_S0VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0VBUF_ADDR(v) (v) + +#define HW_PXP_S0PARAM (0x00000080) + +#define BP_PXP_S0PARAM_XBASE 24 +#define BM_PXP_S0PARAM_XBASE 0xFF000000 +#define BF_PXP_S0PARAM_XBASE(v) \ + (((v) << 24) & BM_PXP_S0PARAM_XBASE) +#define BP_PXP_S0PARAM_YBASE 16 +#define BM_PXP_S0PARAM_YBASE 0x00FF0000 +#define BF_PXP_S0PARAM_YBASE(v) \ + (((v) << 16) & BM_PXP_S0PARAM_YBASE) +#define BP_PXP_S0PARAM_WIDTH 8 +#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 +#define BF_PXP_S0PARAM_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0PARAM_WIDTH) +#define BP_PXP_S0PARAM_HEIGHT 0 +#define BM_PXP_S0PARAM_HEIGHT 0x000000FF +#define BF_PXP_S0PARAM_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0PARAM_HEIGHT) + +#define HW_PXP_S0BACKGROUND (0x00000090) + +#define BP_PXP_S0BACKGROUND_COLOR 0 +#define BM_PXP_S0BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_S0BACKGROUND_COLOR(v) (v) + +#define HW_PXP_S0CROP (0x000000a0) + +#define BP_PXP_S0CROP_XBASE 24 +#define BM_PXP_S0CROP_XBASE 0xFF000000 +#define BF_PXP_S0CROP_XBASE(v) \ + (((v) << 24) & BM_PXP_S0CROP_XBASE) +#define BP_PXP_S0CROP_YBASE 16 +#define BM_PXP_S0CROP_YBASE 0x00FF0000 +#define BF_PXP_S0CROP_YBASE(v) \ + (((v) << 16) & BM_PXP_S0CROP_YBASE) +#define BP_PXP_S0CROP_WIDTH 8 +#define BM_PXP_S0CROP_WIDTH 0x0000FF00 +#define BF_PXP_S0CROP_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0CROP_WIDTH) +#define BP_PXP_S0CROP_HEIGHT 0 +#define BM_PXP_S0CROP_HEIGHT 0x000000FF +#define BF_PXP_S0CROP_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0CROP_HEIGHT) + +#define HW_PXP_S0SCALE (0x000000b0) + +#define BM_PXP_S0SCALE_RSVD2 0x80000000 +#define BP_PXP_S0SCALE_YSCALE 16 +#define BM_PXP_S0SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_S0SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_S0SCALE_YSCALE) +#define BM_PXP_S0SCALE_RSVD1 0x00008000 +#define BP_PXP_S0SCALE_XSCALE 0 +#define BM_PXP_S0SCALE_XSCALE 0x00007FFF +#define BF_PXP_S0SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_S0SCALE_XSCALE) + +#define HW_PXP_S0OFFSET (0x000000c0) + +#define BP_PXP_S0OFFSET_RSVD2 28 +#define BM_PXP_S0OFFSET_RSVD2 0xF0000000 +#define BF_PXP_S0OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_S0OFFSET_RSVD2) +#define BP_PXP_S0OFFSET_YOFFSET 16 +#define BM_PXP_S0OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_S0OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_S0OFFSET_YOFFSET) +#define BP_PXP_S0OFFSET_RSVD1 12 +#define BM_PXP_S0OFFSET_RSVD1 0x0000F000 +#define BF_PXP_S0OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_S0OFFSET_RSVD1) +#define BP_PXP_S0OFFSET_XOFFSET 0 +#define BM_PXP_S0OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_S0OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_S0OFFSET_XOFFSET) + +#define HW_PXP_CSCCOEF0 (0x000000d0) + +#define BM_PXP_CSCCOEF0_YCBCR_MODE 0x80000000 +#define BM_PXP_CSCCOEF0_BYPASS 0x40000000 +#define BM_PXP_CSCCOEF0_RSVD1 0x20000000 +#define BP_PXP_CSCCOEF0_C0 18 +#define BM_PXP_CSCCOEF0_C0 0x1FFC0000 +#define BF_PXP_CSCCOEF0_C0(v) \ + (((v) << 18) & BM_PXP_CSCCOEF0_C0) +#define BP_PXP_CSCCOEF0_UV_OFFSET 9 +#define BM_PXP_CSCCOEF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSCCOEF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSCCOEF0_UV_OFFSET) +#define BP_PXP_CSCCOEF0_Y_OFFSET 0 +#define BM_PXP_CSCCOEF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSCCOEF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSCCOEF0_Y_OFFSET) + +#define HW_PXP_CSCCOEF1 (0x000000e0) + +#define BP_PXP_CSCCOEF1_RSVD1 27 +#define BM_PXP_CSCCOEF1_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEF1_RSVD1) +#define BP_PXP_CSCCOEF1_C1 16 +#define BM_PXP_CSCCOEF1_C1 0x07FF0000 +#define BF_PXP_CSCCOEF1_C1(v) \ + (((v) << 16) & BM_PXP_CSCCOEF1_C1) +#define BP_PXP_CSCCOEF1_RSVD0 11 +#define BM_PXP_CSCCOEF1_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEF1_RSVD0) +#define BP_PXP_CSCCOEF1_C4 0 +#define BM_PXP_CSCCOEF1_C4 0x000007FF +#define BF_PXP_CSCCOEF1_C4(v) \ + (((v) << 0) & BM_PXP_CSCCOEF1_C4) + +#define HW_PXP_CSCCOEF2 (0x000000f0) + +#define BP_PXP_CSCCOEF2_RSVD1 27 +#define BM_PXP_CSCCOEF2_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEF2_RSVD1) +#define BP_PXP_CSCCOEF2_C2 16 +#define BM_PXP_CSCCOEF2_C2 0x07FF0000 +#define BF_PXP_CSCCOEF2_C2(v) \ + (((v) << 16) & BM_PXP_CSCCOEF2_C2) +#define BP_PXP_CSCCOEF2_RSVD0 11 +#define BM_PXP_CSCCOEF2_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEF2_RSVD0) +#define BP_PXP_CSCCOEF2_C3 0 +#define BM_PXP_CSCCOEF2_C3 0x000007FF +#define BF_PXP_CSCCOEF2_C3(v) \ + (((v) << 0) & BM_PXP_CSCCOEF2_C3) + +#define HW_PXP_NEXT (0x00000100) +#define HW_PXP_NEXT_SET (0x00000104) +#define HW_PXP_NEXT_CLR (0x00000108) +#define HW_PXP_NEXT_TOG (0x0000010c) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BM_PXP_NEXT_ENABLED 0x00000001 + +#define HW_PXP_S0COLORKEYLOW (0x00000180) + +#define BP_PXP_S0COLORKEYLOW_RSVD1 24 +#define BM_PXP_S0COLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYLOW_RSVD1) +#define BP_PXP_S0COLORKEYLOW_PIXEL 0 +#define BM_PXP_S0COLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYLOW_PIXEL) + +#define HW_PXP_S0COLORKEYHIGH (0x00000190) + +#define BP_PXP_S0COLORKEYHIGH_RSVD1 24 +#define BM_PXP_S0COLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYHIGH_RSVD1) +#define BP_PXP_S0COLORKEYHIGH_PIXEL 0 +#define BM_PXP_S0COLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYHIGH_PIXEL) + +#define HW_PXP_OLCOLORKEYLOW (0x000001a0) + +#define BP_PXP_OLCOLORKEYLOW_RSVD1 24 +#define BM_PXP_OLCOLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYLOW_RSVD1) +#define BP_PXP_OLCOLORKEYLOW_PIXEL 0 +#define BM_PXP_OLCOLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYLOW_PIXEL) + +#define HW_PXP_OLCOLORKEYHIGH (0x000001b0) + +#define BP_PXP_OLCOLORKEYHIGH_RSVD1 24 +#define BM_PXP_OLCOLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYHIGH_RSVD1) +#define BP_PXP_OLCOLORKEYHIGH_PIXEL 0 +#define BM_PXP_OLCOLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYHIGH_PIXEL) + +#define HW_PXP_DEBUGCTRL (0x000001d0) + +#define BP_PXP_DEBUGCTRL_RSVD 8 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFFF00 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 8) & BM_PXP_DEBUGCTRL_RSVD) +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__S0REGS 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__PXBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1 0x8 + +#define HW_PXP_DEBUG (0x000001e0) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x000001f0) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) + +/* + * multi-register-define name HW_PXP_OLn + * base 0x00000200 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLn(n) (0x00000200 + (n) * 0x40) +#define BP_PXP_OLn_ADDR 0 +#define BM_PXP_OLn_ADDR 0xFFFFFFFF +#define BF_PXP_OLn_ADDR(v) (v) + +/* + * multi-register-define name HW_PXP_OLnSIZE + * base 0x00000210 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnSIZE(n) (0x00000210 + (n) * 0x40) +#define BP_PXP_OLnSIZE_XBASE 24 +#define BM_PXP_OLnSIZE_XBASE 0xFF000000 +#define BF_PXP_OLnSIZE_XBASE(v) \ + (((v) << 24) & BM_PXP_OLnSIZE_XBASE) +#define BP_PXP_OLnSIZE_YBASE 16 +#define BM_PXP_OLnSIZE_YBASE 0x00FF0000 +#define BF_PXP_OLnSIZE_YBASE(v) \ + (((v) << 16) & BM_PXP_OLnSIZE_YBASE) +#define BP_PXP_OLnSIZE_WIDTH 8 +#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 +#define BF_PXP_OLnSIZE_WIDTH(v) \ + (((v) << 8) & BM_PXP_OLnSIZE_WIDTH) +#define BP_PXP_OLnSIZE_HEIGHT 0 +#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF +#define BF_PXP_OLnSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OLnSIZE_HEIGHT) + +/* + * multi-register-define name HW_PXP_OLnPARAM + * base 0x00000220 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM(n) (0x00000220 + (n) * 0x40) +#define BP_PXP_OLnPARAM_RSVD1 20 +#define BM_PXP_OLnPARAM_RSVD1 0xFFF00000 +#define BF_PXP_OLnPARAM_RSVD1(v) \ + (((v) << 20) & BM_PXP_OLnPARAM_RSVD1) +#define BP_PXP_OLnPARAM_ROP 16 +#define BM_PXP_OLnPARAM_ROP 0x000F0000 +#define BF_PXP_OLnPARAM_ROP(v) \ + (((v) << 16) & BM_PXP_OLnPARAM_ROP) +#define BV_PXP_OLnPARAM_ROP__MASKOL 0x0 +#define BV_PXP_OLnPARAM_ROP__MASKNOTOL 0x1 +#define BV_PXP_OLnPARAM_ROP__MASKOLNOT 0x2 +#define BV_PXP_OLnPARAM_ROP__MERGEOL 0x3 +#define BV_PXP_OLnPARAM_ROP__MERGENOTOL 0x4 +#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT 0x5 +#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL 0x6 +#define BV_PXP_OLnPARAM_ROP__NOT 0x7 +#define BV_PXP_OLnPARAM_ROP__NOTMASKOL 0x8 +#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL 0x9 +#define BV_PXP_OLnPARAM_ROP__XOROL 0xA +#define BV_PXP_OLnPARAM_ROP__NOTXOROL 0xB +#define BP_PXP_OLnPARAM_ALPHA 8 +#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 +#define BF_PXP_OLnPARAM_ALPHA(v) \ + (((v) << 8) & BM_PXP_OLnPARAM_ALPHA) +#define BP_PXP_OLnPARAM_FORMAT 4 +#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 +#define BF_PXP_OLnPARAM_FORMAT(v) \ + (((v) << 4) & BM_PXP_OLnPARAM_FORMAT) +#define BV_PXP_OLnPARAM_FORMAT__ARGB8888 0x0 +#define BV_PXP_OLnPARAM_FORMAT__RGB888 0x1 +#define BV_PXP_OLnPARAM_FORMAT__ARGB1555 0x3 +#define BV_PXP_OLnPARAM_FORMAT__RGB565 0x4 +#define BV_PXP_OLnPARAM_FORMAT__RGB555 0x5 +#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 +#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 +#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 +#define BF_PXP_OLnPARAM_ALPHA_CNTL(v) \ + (((v) << 1) & BM_PXP_OLnPARAM_ALPHA_CNTL) +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded 0x0 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override 0x1 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply 0x2 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs 0x3 +#define BM_PXP_OLnPARAM_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PXP_OLnPARAM2 + * base 0x00000230 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM2(n) (0x00000230 + (n) * 0x40) +#define BP_PXP_OLnPARAM2_RSVD 0 +#define BM_PXP_OLnPARAM2_RSVD 0xFFFFFFFF +#define BF_PXP_OLnPARAM2_RSVD(v) (v) + +#define HW_PXP_CSC2CTRL (0x00000400) + +#define BP_PXP_CSC2CTRL_RSVD 3 +#define BM_PXP_CSC2CTRL_RSVD 0xFFFFFFF8 +#define BF_PXP_CSC2CTRL_RSVD(v) \ + (((v) << 3) & BM_PXP_CSC2CTRL_RSVD) +#define BP_PXP_CSC2CTRL_CSC_MODE 1 +#define BM_PXP_CSC2CTRL_CSC_MODE 0x00000006 +#define BF_PXP_CSC2CTRL_CSC_MODE(v) \ + (((v) << 1) & BM_PXP_CSC2CTRL_CSC_MODE) +#define BV_PXP_CSC2CTRL_CSC_MODE__YUV2RGB 0x0 +#define BV_PXP_CSC2CTRL_CSC_MODE__YCbCr2RGB 0x1 +#define BV_PXP_CSC2CTRL_CSC_MODE__RGB2YUV 0x2 +#define BV_PXP_CSC2CTRL_CSC_MODE__RGB2YCbCr 0x3 +#define BM_PXP_CSC2CTRL_BYPASS 0x00000001 + +#define HW_PXP_CSC2COEF0 (0x00000410) + +#define BP_PXP_CSC2COEF0_RSVD1 27 +#define BM_PXP_CSC2COEF0_RSVD1 0xF8000000 +#define BF_PXP_CSC2COEF0_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2COEF0_RSVD1) +#define BP_PXP_CSC2COEF0_A2 16 +#define BM_PXP_CSC2COEF0_A2 0x07FF0000 +#define BF_PXP_CSC2COEF0_A2(v) \ + (((v) << 16) & BM_PXP_CSC2COEF0_A2) +#define BP_PXP_CSC2COEF0_RSVD0 11 +#define BM_PXP_CSC2COEF0_RSVD0 0x0000F800 +#define BF_PXP_CSC2COEF0_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2COEF0_RSVD0) +#define BP_PXP_CSC2COEF0_A1 0 +#define BM_PXP_CSC2COEF0_A1 0x000007FF +#define BF_PXP_CSC2COEF0_A1(v) \ + (((v) << 0) & BM_PXP_CSC2COEF0_A1) + +#define HW_PXP_CSC2COEF1 (0x00000420) + +#define BP_PXP_CSC2COEF1_RSVD1 27 +#define BM_PXP_CSC2COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC2COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2COEF1_RSVD1) +#define BP_PXP_CSC2COEF1_B1 16 +#define BM_PXP_CSC2COEF1_B1 0x07FF0000 +#define BF_PXP_CSC2COEF1_B1(v) \ + (((v) << 16) & BM_PXP_CSC2COEF1_B1) +#define BP_PXP_CSC2COEF1_RSVD0 11 +#define BM_PXP_CSC2COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC2COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2COEF1_RSVD0) +#define BP_PXP_CSC2COEF1_A3 0 +#define BM_PXP_CSC2COEF1_A3 0x000007FF +#define BF_PXP_CSC2COEF1_A3(v) \ + (((v) << 0) & BM_PXP_CSC2COEF1_A3) + +#define HW_PXP_CSC2COEF2 (0x00000430) + +#define BP_PXP_CSC2COEF2_RSVD1 27 +#define BM_PXP_CSC2COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC2COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2COEF2_RSVD1) +#define BP_PXP_CSC2COEF2_B3 16 +#define BM_PXP_CSC2COEF2_B3 0x07FF0000 +#define BF_PXP_CSC2COEF2_B3(v) \ + (((v) << 16) & BM_PXP_CSC2COEF2_B3) +#define BP_PXP_CSC2COEF2_RSVD0 11 +#define BM_PXP_CSC2COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC2COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2COEF2_RSVD0) +#define BP_PXP_CSC2COEF2_B2 0 +#define BM_PXP_CSC2COEF2_B2 0x000007FF +#define BF_PXP_CSC2COEF2_B2(v) \ + (((v) << 0) & BM_PXP_CSC2COEF2_B2) + +#define HW_PXP_CSC2COEF3 (0x00000440) + +#define BP_PXP_CSC2COEF3_RSVD1 27 +#define BM_PXP_CSC2COEF3_RSVD1 0xF8000000 +#define BF_PXP_CSC2COEF3_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2COEF3_RSVD1) +#define BP_PXP_CSC2COEF3_C2 16 +#define BM_PXP_CSC2COEF3_C2 0x07FF0000 +#define BF_PXP_CSC2COEF3_C2(v) \ + (((v) << 16) & BM_PXP_CSC2COEF3_C2) +#define BP_PXP_CSC2COEF3_RSVD0 11 +#define BM_PXP_CSC2COEF3_RSVD0 0x0000F800 +#define BF_PXP_CSC2COEF3_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2COEF3_RSVD0) +#define BP_PXP_CSC2COEF3_C1 0 +#define BM_PXP_CSC2COEF3_C1 0x000007FF +#define BF_PXP_CSC2COEF3_C1(v) \ + (((v) << 0) & BM_PXP_CSC2COEF3_C1) + +#define HW_PXP_CSC2COEF4 (0x00000450) + +#define BP_PXP_CSC2COEF4_RSVD1 25 +#define BM_PXP_CSC2COEF4_RSVD1 0xFE000000 +#define BF_PXP_CSC2COEF4_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2COEF4_RSVD1) +#define BP_PXP_CSC2COEF4_D1 16 +#define BM_PXP_CSC2COEF4_D1 0x01FF0000 +#define BF_PXP_CSC2COEF4_D1(v) \ + (((v) << 16) & BM_PXP_CSC2COEF4_D1) +#define BP_PXP_CSC2COEF4_RSVD0 11 +#define BM_PXP_CSC2COEF4_RSVD0 0x0000F800 +#define BF_PXP_CSC2COEF4_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2COEF4_RSVD0) +#define BP_PXP_CSC2COEF4_C3 0 +#define BM_PXP_CSC2COEF4_C3 0x000007FF +#define BF_PXP_CSC2COEF4_C3(v) \ + (((v) << 0) & BM_PXP_CSC2COEF4_C3) + +#define HW_PXP_CSC2COEF5 (0x00000460) + +#define BP_PXP_CSC2COEF5_RSVD1 25 +#define BM_PXP_CSC2COEF5_RSVD1 0xFE000000 +#define BF_PXP_CSC2COEF5_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2COEF5_RSVD1) +#define BP_PXP_CSC2COEF5_D3 16 +#define BM_PXP_CSC2COEF5_D3 0x01FF0000 +#define BF_PXP_CSC2COEF5_D3(v) \ + (((v) << 16) & BM_PXP_CSC2COEF5_D3) +#define BP_PXP_CSC2COEF5_RSVD0 9 +#define BM_PXP_CSC2COEF5_RSVD0 0x0000FE00 +#define BF_PXP_CSC2COEF5_RSVD0(v) \ + (((v) << 9) & BM_PXP_CSC2COEF5_RSVD0) +#define BP_PXP_CSC2COEF5_D2 0 +#define BM_PXP_CSC2COEF5_D2 0x000001FF +#define BF_PXP_CSC2COEF5_D2(v) \ + (((v) << 0) & BM_PXP_CSC2COEF5_D2) + +#define HW_PXP_LUT_CTRL (0x00000470) + +#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 +#define BP_PXP_LUT_CTRL_RSVD 8 +#define BM_PXP_LUT_CTRL_RSVD 0x7FFFFF00 +#define BF_PXP_LUT_CTRL_RSVD(v) \ + (((v) << 8) & BM_PXP_LUT_CTRL_RSVD) +#define BP_PXP_LUT_CTRL_ADDR 0 +#define BM_PXP_LUT_CTRL_ADDR 0x000000FF +#define BF_PXP_LUT_CTRL_ADDR(v) \ + (((v) << 0) & BM_PXP_LUT_CTRL_ADDR) + +#define HW_PXP_LUT (0x00000480) + +#define BP_PXP_LUT_RSVD 8 +#define BM_PXP_LUT_RSVD 0xFFFFFF00 +#define BF_PXP_LUT_RSVD(v) \ + (((v) << 8) & BM_PXP_LUT_RSVD) +#define BP_PXP_LUT_DATA 0 +#define BM_PXP_LUT_DATA 0x000000FF +#define BF_PXP_LUT_DATA(v) \ + (((v) << 0) & BM_PXP_LUT_DATA) + +#define HW_PXP_HIST_CTRL (0x00000490) + +#define BP_PXP_HIST_CTRL_RSVD 6 +#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0 +#define BF_PXP_HIST_CTRL_RSVD(v) \ + (((v) << 6) & BM_PXP_HIST_CTRL_RSVD) +#define BP_PXP_HIST_CTRL_PANEL_MODE 4 +#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030 +#define BF_PXP_HIST_CTRL_PANEL_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE) +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4 0x0 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8 0x1 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3 +#define BP_PXP_HIST_CTRL_STATUS 0 +#define BM_PXP_HIST_CTRL_STATUS 0x0000000F +#define BF_PXP_HIST_CTRL_STATUS(v) \ + (((v) << 0) & BM_PXP_HIST_CTRL_STATUS) + +#define HW_PXP_HIST2_PARAM (0x000004a0) + +#define BP_PXP_HIST2_PARAM_RSVD 16 +#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 +#define BF_PXP_HIST2_PARAM_RSVD(v) \ + (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) +#define BP_PXP_HIST2_PARAM_RSVD1 13 +#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST2_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1) +#define BP_PXP_HIST2_PARAM_VALUE1 8 +#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST2_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) +#define BP_PXP_HIST2_PARAM_RSVD0 5 +#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST2_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0) +#define BP_PXP_HIST2_PARAM_VALUE0 0 +#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST2_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) + +#define HW_PXP_HIST4_PARAM (0x000004b0) + +#define BP_PXP_HIST4_PARAM_RSVD3 29 +#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000 +#define BF_PXP_HIST4_PARAM_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3) +#define BP_PXP_HIST4_PARAM_VALUE3 24 +#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000 +#define BF_PXP_HIST4_PARAM_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) +#define BP_PXP_HIST4_PARAM_RSVD2 21 +#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000 +#define BF_PXP_HIST4_PARAM_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2) +#define BP_PXP_HIST4_PARAM_VALUE2 16 +#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000 +#define BF_PXP_HIST4_PARAM_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) +#define BP_PXP_HIST4_PARAM_RSVD1 13 +#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST4_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1) +#define BP_PXP_HIST4_PARAM_VALUE1 8 +#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST4_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) +#define BP_PXP_HIST4_PARAM_RSVD0 5 +#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST4_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0) +#define BP_PXP_HIST4_PARAM_VALUE0 0 +#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST4_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) + +#define HW_PXP_HIST8_PARAM0 (0x000004c0) + +#define BP_PXP_HIST8_PARAM0_RSVD3 29 +#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3) +#define BP_PXP_HIST8_PARAM0_VALUE3 24 +#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) +#define BP_PXP_HIST8_PARAM0_RSVD2 21 +#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2) +#define BP_PXP_HIST8_PARAM0_VALUE2 16 +#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) +#define BP_PXP_HIST8_PARAM0_RSVD1 13 +#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1) +#define BP_PXP_HIST8_PARAM0_VALUE1 8 +#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) +#define BP_PXP_HIST8_PARAM0_RSVD0 5 +#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0) +#define BP_PXP_HIST8_PARAM0_VALUE0 0 +#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) + +#define HW_PXP_HIST8_PARAM1 (0x000004d0) + +#define BP_PXP_HIST8_PARAM1_RSVD7 29 +#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7) +#define BP_PXP_HIST8_PARAM1_VALUE7 24 +#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) +#define BP_PXP_HIST8_PARAM1_RSVD6 21 +#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6) +#define BP_PXP_HIST8_PARAM1_VALUE6 16 +#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) +#define BP_PXP_HIST8_PARAM1_RSVD5 13 +#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5) +#define BP_PXP_HIST8_PARAM1_VALUE5 8 +#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) +#define BP_PXP_HIST8_PARAM1_RSVD4 5 +#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4) +#define BP_PXP_HIST8_PARAM1_VALUE4 0 +#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM0 (0x000004e0) + +#define BP_PXP_HIST16_PARAM0_RSVD3 29 +#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3) +#define BP_PXP_HIST16_PARAM0_VALUE3 24 +#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) +#define BP_PXP_HIST16_PARAM0_RSVD2 21 +#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2) +#define BP_PXP_HIST16_PARAM0_VALUE2 16 +#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) +#define BP_PXP_HIST16_PARAM0_RSVD1 13 +#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1) +#define BP_PXP_HIST16_PARAM0_VALUE1 8 +#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) +#define BP_PXP_HIST16_PARAM0_RSVD0 5 +#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0) +#define BP_PXP_HIST16_PARAM0_VALUE0 0 +#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) + +#define HW_PXP_HIST16_PARAM1 (0x000004f0) + +#define BP_PXP_HIST16_PARAM1_RSVD7 29 +#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7) +#define BP_PXP_HIST16_PARAM1_VALUE7 24 +#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) +#define BP_PXP_HIST16_PARAM1_RSVD6 21 +#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6) +#define BP_PXP_HIST16_PARAM1_VALUE6 16 +#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) +#define BP_PXP_HIST16_PARAM1_RSVD5 13 +#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5) +#define BP_PXP_HIST16_PARAM1_VALUE5 8 +#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) +#define BP_PXP_HIST16_PARAM1_RSVD4 5 +#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4) +#define BP_PXP_HIST16_PARAM1_VALUE4 0 +#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM2 (0x00000500) + +#define BP_PXP_HIST16_PARAM2_RSVD11 29 +#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000 +#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11) +#define BP_PXP_HIST16_PARAM2_VALUE11 24 +#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000 +#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) +#define BP_PXP_HIST16_PARAM2_RSVD10 21 +#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000 +#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10) +#define BP_PXP_HIST16_PARAM2_VALUE10 16 +#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000 +#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) +#define BP_PXP_HIST16_PARAM2_RSVD9 13 +#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000 +#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9) +#define BP_PXP_HIST16_PARAM2_VALUE9 8 +#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00 +#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) +#define BP_PXP_HIST16_PARAM2_RSVD8 5 +#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0 +#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8) +#define BP_PXP_HIST16_PARAM2_VALUE8 0 +#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F +#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) + +#define HW_PXP_HIST16_PARAM3 (0x00000510) + +#define BP_PXP_HIST16_PARAM3_RSVD15 29 +#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000 +#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15) +#define BP_PXP_HIST16_PARAM3_VALUE15 24 +#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000 +#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) +#define BP_PXP_HIST16_PARAM3_RSVD14 21 +#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000 +#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14) +#define BP_PXP_HIST16_PARAM3_VALUE14 16 +#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000 +#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) +#define BP_PXP_HIST16_PARAM3_RSVD13 13 +#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000 +#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13) +#define BP_PXP_HIST16_PARAM3_VALUE13 8 +#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00 +#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) +#define BP_PXP_HIST16_PARAM3_RSVD12 5 +#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0 +#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12) +#define BP_PXP_HIST16_PARAM3_VALUE12 0 +#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F +#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/drivers/input/keyboard/mxc_pwrkey.c b/drivers/input/keyboard/mxc_pwrkey.c new file mode 100644 index 000000000000..9621f1e3d78f --- /dev/null +++ b/drivers/input/keyboard/mxc_pwrkey.c @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../arch/arm/mach-mx5/mx51_pins.h" +#define KEYCODE_ONOFF KEY_F4 + +#if 1 +#define pk_printf printk +#else +#define pk_printf(...) +#endif + +/*! Input device structure. */ +struct input_dev *mxcpwrkey_dev = NULL; +static bool key_press=false; +static void power_key_event_handler(void) +{ + if (!key_press) { + key_press = true; + input_report_key(mxcpwrkey_dev, KEYCODE_ONOFF, 1); + pk_printf("%s_KeyUP\n",__func__); + }else { + if (key_press){ + key_press = false; + input_report_key(mxcpwrkey_dev, KEYCODE_ONOFF, 0); + pk_printf("%s_KeyDown\n",__func__); + } + } + +} +static int mxcpwrkey_probe(struct platform_device *pdev) +{ + int retval,err; + pmic_event_callback_t power_key_event; + + printk("I.MX5 powerkey probe\n"); +/* + init_completion(&pk_cmd_done); + pwrkey_task = kthread_run(powerkey_thread, pdev, "powerkey"); + if (IS_ERR(pwrkey_task)) { + err = PTR_ERR(pwrkey_task); + printk(KERN_ERR "powerkey: Failed to start powerkey_thread, err: %d\n", err); + goto err1; + } +*/ + mxcpwrkey_dev = input_allocate_device(); + if (!mxcpwrkey_dev) { + printk(KERN_ERR + "mxcpwrkey_dev: not enough memory for input device\n"); + retval = -ENOMEM; + goto err1; + } + + mxcpwrkey_dev->name = "mxc_power_key"; + mxcpwrkey_dev->phys = "mxcpwrkey/input0";; + mxcpwrkey_dev->id.bustype = BUS_HOST ; + mxcpwrkey_dev->evbit[0] = BIT_MASK(EV_KEY) ; + + + power_key_event.param = NULL; + power_key_event.func = (void *)power_key_event_handler; + pmic_event_subscribe(EVENT_PWRONI, power_key_event); + + input_set_capability(mxcpwrkey_dev, EV_KEY, KEYCODE_ONOFF); + + retval = input_register_device(mxcpwrkey_dev); + if (retval < 0) { + printk(KERN_ERR + "mxcpwrkey_dev: failed to register input device\n"); + goto err2; + } + return 0; + + err2: + input_free_device(mxcpwrkey_dev); + err1: + return retval; +} +static int mxcpwrkey_remove(struct platform_device *pdev) +{ + return 0; +} +static int mxc_pwrkey_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} +static int mxc_pwrkey_resume(struct platform_device *pdev) +{ + return 0; +} +static struct platform_driver mxcpwrkey_driver = { + .driver = { + .name = "mxcpwrkey", + }, + .probe = mxcpwrkey_probe, + .remove = mxcpwrkey_remove, + .suspend = mxc_pwrkey_suspend, + .resume = mxc_pwrkey_resume, +}; +static int __init mxcpwrkey_init(void) +{ + platform_driver_register(&mxcpwrkey_driver); + return 0; +} + +static void __exit mxcpwrkey_exit(void) +{ + platform_driver_unregister(&mxcpwrkey_driver); +} +module_init(mxcpwrkey_init); +module_exit(mxcpwrkey_exit); + + +MODULE_AUTHOR("eben"); +MODULE_DESCRIPTION("MXC power key Driver"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/media/video/mxc/output/mxc_pxp_v4l2.c b/drivers/media/video/mxc/output/mxc_pxp_v4l2.c new file mode 100644 index 000000000000..2855bb675d1d --- /dev/null +++ b/drivers/media/video/mxc/output/mxc_pxp_v4l2.c @@ -0,0 +1,1237 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "mxc_pxp_v4l2.h" + +#define PXP_DRIVER_NAME "pxp-v4l2" +#define PXP_DRIVER_MAJOR 2 +#define PXP_DRIVER_MINOR 0 + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +#define V4L2_OUTPUT_TYPE_INTERNAL 4 + +static struct pxp_data_format pxp_s0_formats[] = { + { + .name = "24-bit RGB", + .bpp = 4, + .fourcc = V4L2_PIX_FMT_RGB24, + .colorspace = V4L2_COLORSPACE_SRGB, + }, { + .name = "16-bit RGB 5:6:5", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_RGB565, + .colorspace = V4L2_COLORSPACE_SRGB, + }, { + .name = "16-bit RGB 5:5:5", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_RGB555, + .colorspace = V4L2_COLORSPACE_SRGB, + }, { + .name = "YUV 4:2:0 Planar", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_YUV420, + .colorspace = V4L2_COLORSPACE_JPEG, + }, { + .name = "YUV 4:2:2 Planar", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_YUV422P, + .colorspace = V4L2_COLORSPACE_JPEG, + }, +}; + +static unsigned int v4l2_fmt_to_pxp_fmt(u32 v4l2_pix_fmt) +{ + u32 pxp_fmt = 0; + + if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB24) + pxp_fmt = PXP_PIX_FMT_RGB24; + else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB565) + pxp_fmt = PXP_PIX_FMT_RGB565; + else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB555) + pxp_fmt = PXP_PIX_FMT_RGB555; + else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB555) + pxp_fmt = PXP_PIX_FMT_RGB555; + else if (v4l2_pix_fmt == V4L2_PIX_FMT_YUV420) + pxp_fmt = PXP_PIX_FMT_YUV420P; + else if (v4l2_pix_fmt == V4L2_PIX_FMT_YUV422P) + pxp_fmt = PXP_PIX_FMT_YUV422P; + + return pxp_fmt; +} +struct v4l2_queryctrl pxp_controls[] = { + { + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Horizontal Flip", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + }, { + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Vertical Flip", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + }, { + .id = V4L2_CID_PRIVATE_BASE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Rotation", + .minimum = 0, + .maximum = 270, + .step = 90, + .default_value = 0, + .flags = 0, + }, { + .id = V4L2_CID_PRIVATE_BASE + 1, + .name = "Background Color", + .minimum = 0, + .maximum = 0xFFFFFF, + .step = 1, + .default_value = 0, + .flags = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_PRIVATE_BASE + 2, + .name = "Set S0 Chromakey", + .minimum = -1, + .maximum = 0xFFFFFF, + .step = 1, + .default_value = -1, + .flags = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_PRIVATE_BASE + 3, + .name = "YUV Colorspace", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + .type = V4L2_CTRL_TYPE_BOOLEAN, + }, +}; + +/* callback function */ +static void video_dma_done(void *arg) +{ + struct pxp_tx_desc *tx_desc = to_tx_desc(arg); + struct dma_chan *chan = tx_desc->txd.chan; + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxps *pxp = pxp_chan->client; + struct videobuf_buffer *vb; + + dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n", + tx_desc->txd.cookie, + pxp->active ? sg_dma_address(&pxp->active->sg[0]) : 0); + + spin_lock(&pxp->lock); + if (pxp->active) { + vb = &pxp->active->vb; + + list_del_init(&vb->queue); + vb->state = VIDEOBUF_DONE; + do_gettimeofday(&vb->ts); + vb->field_count++; + wake_up(&vb->done); + } + + if (list_empty(&pxp->outq)) { + pxp->active = NULL; + spin_unlock(&pxp->lock); + + return; + } + + pxp->active = list_entry(pxp->outq.next, + struct pxp_buffer, vb.queue); + pxp->active->vb.state = VIDEOBUF_ACTIVE; + spin_unlock(&pxp->lock); +} + +static int acquire_dma_channel(struct pxps *pxp) +{ + dma_cap_mask_t mask; + struct dma_chan *chan; + struct pxp_channel **pchan = &pxp->pxp_channel[0]; + + if (*pchan) { + struct videobuf_buffer *vb, *_vb; + dma_release_channel(&(*pchan)->dma_chan); + *pchan = NULL; + pxp->active = NULL; + list_for_each_entry_safe(vb, _vb, &pxp->outq, queue) { + list_del_init(&vb->queue); + vb->state = VIDEOBUF_ERROR; + wake_up(&vb->done); + } + } + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_cap_set(DMA_PRIVATE, mask); + chan = dma_request_channel(mask, NULL, NULL); + if (!chan) + return -EBUSY; + + *pchan = to_pxp_channel(chan); + (*pchan)->client = pxp; + + return 0; +} + +static int _get_fbinfo(struct fb_info **fbi) +{ + int i; + for (i = 0; i < num_registered_fb; i++) { + char *idstr = registered_fb[i]->fix.id; + if (strcmp(idstr, "mxc_elcdif_fb") == 0) { + *fbi = registered_fb[i]; + return 0; + } + } + + return -ENODEV; +} + +static int pxp_set_fbinfo(struct pxps *pxp) +{ + struct fb_info *fbi; + struct v4l2_framebuffer *fb = &pxp->fb; + int err; + + err = _get_fbinfo(&fbi); + if (err) + return err; + + fb->fmt.width = fbi->var.xres; + fb->fmt.height = fbi->var.yres; + if (fbi->var.bits_per_pixel == 16) + fb->fmt.pixelformat = V4L2_PIX_FMT_RGB565; + else + fb->fmt.pixelformat = V4L2_PIX_FMT_RGB24; + fb->base = (void *)fbi->fix.smem_start; + + return 0; +} + +static int _get_cur_fb_blank(struct pxps *pxp) +{ + struct fb_info *fbi; + mm_segment_t old_fs; + int err = 0; + + err = _get_fbinfo(&fbi); + if (err) + return err; + + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + err = fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_BLANK, + (unsigned int)(&pxp->fb_blank)); + set_fs(old_fs); + } + + return err; +} + +static int set_fb_blank(int blank) +{ + struct fb_info *fbi; + int err = 0; + + err = _get_fbinfo(&fbi); + if (err) + return err; + + acquire_console_sem(); + fb_blank(fbi, blank); + release_console_sem(); + + return err; +} + +static int pxp_set_cstate(struct pxps *pxp, struct v4l2_control *vc) +{ + + if (vc->id == V4L2_CID_HFLIP) { + pxp->pxp_conf.proc_data.hflip = vc->value; + } else if (vc->id == V4L2_CID_VFLIP) { + pxp->pxp_conf.proc_data.vflip = vc->value; + } else if (vc->id == V4L2_CID_PRIVATE_BASE) { + if (vc->value % 90) + return -ERANGE; + pxp->pxp_conf.proc_data.rotate = vc->value; + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) { + pxp->pxp_conf.proc_data.bgcolor = vc->value; + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) { + pxp->pxp_conf.s0_param.color_key = vc->value; + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) { + pxp->pxp_conf.proc_data.yuv = vc->value; + } + + return 0; +} + +static int pxp_get_cstate(struct pxps *pxp, struct v4l2_control *vc) +{ + if (vc->id == V4L2_CID_HFLIP) + vc->value = pxp->pxp_conf.proc_data.hflip; + else if (vc->id == V4L2_CID_VFLIP) + vc->value = pxp->pxp_conf.proc_data.vflip; + else if (vc->id == V4L2_CID_PRIVATE_BASE) + vc->value = pxp->pxp_conf.proc_data.rotate; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) + vc->value = pxp->pxp_conf.proc_data.bgcolor; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) + vc->value = pxp->pxp_conf.s0_param.color_key; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) + vc->value = pxp->pxp_conf.proc_data.yuv; + + return 0; +} + +static int pxp_enumoutput(struct file *file, void *fh, + struct v4l2_output *o) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + if ((o->index < 0) || (o->index > 1)) + return -EINVAL; + + memset(o, 0, sizeof(struct v4l2_output)); + if (o->index == 0) { + strcpy(o->name, "PxP Display Output"); + pxp->output = 0; + } else { + strcpy(o->name, "PxP Virtual Output"); + pxp->output = 1; + } + o->type = V4L2_OUTPUT_TYPE_INTERNAL; + o->std = 0; + o->reserved[0] = pxp->outb_phys; + + return 0; +} + +static int pxp_g_output(struct file *file, void *fh, + unsigned int *i) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + *i = pxp->output; + + return 0; +} + +static int pxp_s_output(struct file *file, void *fh, + unsigned int i) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_pix_format *fmt = &pxp->fb.fmt; + int bpp; + + if ((i < 0) || (i > 1)) + return -EINVAL; + + if (pxp->outb) + return 0; + + /* Output buffer is same format as fbdev */ + if (fmt->pixelformat == V4L2_PIX_FMT_RGB24) + bpp = 4; + else + bpp = 2; + + pxp->outb_size = fmt->width * fmt->height * bpp; + pxp->outb = kmalloc(fmt->width * fmt->height * bpp, GFP_KERNEL); + pxp->outb_phys = virt_to_phys(pxp->outb); + dma_map_single(NULL, pxp->outb, + fmt->width * fmt->height * bpp, DMA_TO_DEVICE); + + pxp->pxp_conf.out_param.width = fmt->width; + pxp->pxp_conf.out_param.height = fmt->height; + if (fmt->pixelformat == V4L2_PIX_FMT_RGB24) + pxp->pxp_conf.out_param.pixel_fmt = PXP_PIX_FMT_RGB24; + else + pxp->pxp_conf.out_param.pixel_fmt = PXP_PIX_FMT_RGB565; + + return 0; +} + +static int pxp_enum_fmt_video_output(struct file *file, void *fh, + struct v4l2_fmtdesc *fmt) +{ + enum v4l2_buf_type type = fmt->type; + int index = fmt->index; + + if ((fmt->index < 0) || (fmt->index >= ARRAY_SIZE(pxp_s0_formats))) + return -EINVAL; + + memset(fmt, 0, sizeof(struct v4l2_fmtdesc)); + fmt->index = index; + fmt->type = type; + fmt->pixelformat = pxp_s0_formats[index].fourcc; + strcpy(fmt->description, pxp_s0_formats[index].name); + + return 0; +} + +static int pxp_g_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct v4l2_pix_format *pf = &f->fmt.pix; + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct pxp_data_format *fmt = pxp->s0_fmt; + + pf->width = pxp->pxp_conf.s0_param.width; + pf->height = pxp->pxp_conf.s0_param.height; + pf->pixelformat = fmt->fourcc; + pf->field = V4L2_FIELD_NONE; + pf->bytesperline = fmt->bpp * pf->width; + pf->sizeimage = pf->bytesperline * pf->height; + pf->colorspace = fmt->colorspace; + pf->priv = 0; + + return 0; +} + +static struct pxp_data_format *pxp_get_format(struct v4l2_format *f) +{ + struct pxp_data_format *fmt; + int i; + + for (i = 0; i < ARRAY_SIZE(pxp_s0_formats); i++) { + fmt = &pxp_s0_formats[i]; + if (fmt->fourcc == f->fmt.pix.pixelformat) + break; + } + + if (i == ARRAY_SIZE(pxp_s0_formats)) + return NULL; + + return &pxp_s0_formats[i]; +} + +static int pxp_try_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + int w = f->fmt.pix.width; + int h = f->fmt.pix.height; + struct pxp_data_format *fmt = pxp_get_format(f); + + if (!fmt) + return -EINVAL; + + w = min(w, 2040); + w = max(w, 8); + h = min(h, 2040); + h = max(h, 8); + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.width = w; + f->fmt.pix.height = h; + f->fmt.pix.pixelformat = fmt->fourcc; + + return 0; +} + +static int pxp_s_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_pix_format *pf = &f->fmt.pix; + int ret; + + ret = acquire_dma_channel(pxp); + if (ret < 0) + return ret; + + ret = pxp_try_fmt_video_output(file, fh, f); + if (ret == 0) { + pxp->s0_fmt = pxp_get_format(f); + pxp->pxp_conf.s0_param.pixel_fmt = + v4l2_fmt_to_pxp_fmt(pxp->s0_fmt->fourcc); + pxp->pxp_conf.s0_param.width = pf->width; + pxp->pxp_conf.s0_param.height = pf->height; + } + + + return ret; +} + +static int pxp_g_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + + memset(wf, 0, sizeof(struct v4l2_window)); + wf->chromakey = pxp->s1_chromakey; + wf->global_alpha = pxp->global_alpha; + wf->field = V4L2_FIELD_NONE; + wf->clips = NULL; + wf->clipcount = 0; + wf->bitmap = NULL; + wf->w.left = pxp->pxp_conf.proc_data.srect.left; + wf->w.top = pxp->pxp_conf.proc_data.srect.top; + wf->w.width = pxp->pxp_conf.proc_data.srect.width; + wf->w.height = pxp->pxp_conf.proc_data.srect.height; + + return 0; +} + +static int pxp_try_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + struct v4l2_rect srect; + u32 s1_chromakey = wf->chromakey; + u8 global_alpha = wf->global_alpha; + + memcpy(&srect, &(wf->w), sizeof(struct v4l2_rect)); + + pxp_g_fmt_output_overlay(file, fh, f); + + wf->chromakey = s1_chromakey; + wf->global_alpha = global_alpha; + + /* Constrain parameters to the input buffer */ + wf->w.left = srect.left; + wf->w.top = srect.top; + wf->w.width = min(srect.width, + ((__s32)pxp->pxp_conf.s0_param.width - wf->w.left)); + wf->w.height = min(srect.height, + ((__s32)pxp->pxp_conf.s0_param.height - wf->w.top)); + + return 0; +} + +static int pxp_s_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + int ret = pxp_try_fmt_output_overlay(file, fh, f); + + if (ret == 0) { + pxp->global_alpha = wf->global_alpha; + pxp->s1_chromakey = wf->chromakey; + pxp->pxp_conf.proc_data.srect.left = wf->w.left; + pxp->pxp_conf.proc_data.srect.top = wf->w.top; + pxp->pxp_conf.proc_data.srect.width = wf->w.width; + pxp->pxp_conf.proc_data.srect.height = wf->w.height; + pxp->pxp_conf.ol_param[0].global_alpha = pxp->global_alpha; + pxp->pxp_conf.ol_param[0].color_key = pxp->s1_chromakey; + pxp->pxp_conf.ol_param[0].color_key_enable = + pxp->s1_chromakey_state; + } + + return ret; +} + +static int pxp_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *r) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_reqbufs(&pxp->s0_vbq, r); +} + +static int pxp_querybuf(struct file *file, void *priv, + struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_querybuf(&pxp->s0_vbq, b); +} + +static int pxp_qbuf(struct file *file, void *priv, + struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_qbuf(&pxp->s0_vbq, b); +} + +static int pxp_dqbuf(struct file *file, void *priv, + struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_dqbuf(&pxp->s0_vbq, b, file->f_flags & O_NONBLOCK); +} + +static int pxp_streamon(struct file *file, void *priv, + enum v4l2_buf_type t) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + if (t != V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + + _get_cur_fb_blank(pxp); + set_fb_blank(FB_BLANK_UNBLANK); + + ret = videobuf_streamon(&pxp->s0_vbq); + + if (!ret && (pxp->output == 0)) + mxc_elcdif_frame_addr_setup(pxp->outb_phys); + + return ret; +} + +static int pxp_streamoff(struct file *file, void *priv, + enum v4l2_buf_type t) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT)) + return -EINVAL; + + ret = videobuf_streamoff(&pxp->s0_vbq); + + if (!ret) + mxc_elcdif_frame_addr_setup((dma_addr_t)pxp->fb.base); + + if (pxp->fb_blank) + set_fb_blank(FB_BLANK_POWERDOWN); + + return ret; +} + +static int pxp_buf_setup(struct videobuf_queue *q, + unsigned int *count, unsigned *size) +{ + struct pxps *pxp = q->priv_data; + + *size = pxp->pxp_conf.s0_param.width * + pxp->pxp_conf.s0_param.height * pxp->s0_fmt->bpp; + + if (0 == *count) + *count = PXP_DEF_BUFS; + + return 0; +} + +static void pxp_buf_free(struct videobuf_queue *q, struct pxp_buffer *buf) +{ + struct videobuf_buffer *vb = &buf->vb; + struct dma_async_tx_descriptor *txd = buf->txd; + + BUG_ON(in_interrupt()); + + pr_debug("%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + /* + * This waits until this buffer is out of danger, i.e., until it is no + * longer in STATE_QUEUED or STATE_ACTIVE + */ + videobuf_waiton(vb, 0, 0); + if (txd) + async_tx_ack(txd); + + videobuf_dma_contig_free(q, vb); + buf->txd = NULL; + + vb->state = VIDEOBUF_NEEDS_INIT; +} + +static int pxp_buf_prepare(struct videobuf_queue *q, + struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct pxps *pxp = q->priv_data; + struct pxp_config_data *pxp_conf = &pxp->pxp_conf; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb); + struct pxp_tx_desc *desc; + int ret = 0; + int i, length; + + vb->width = pxp->pxp_conf.s0_param.width; + vb->height = pxp->pxp_conf.s0_param.height; + vb->size = vb->width * vb->height * pxp->s0_fmt->bpp; + vb->field = V4L2_FIELD_NONE; + if (vb->state != VIDEOBUF_NEEDS_INIT) + pxp_buf_free(q, buf); + + if (vb->state == VIDEOBUF_NEEDS_INIT) { + struct pxp_channel *pchan = pxp->pxp_channel[0]; + struct scatterlist *sg = &buf->sg; + + /* This actually (allocates and) maps buffers */ + ret = videobuf_iolock(q, vb, NULL); + if (ret) { + pr_err("fail to call videobuf_iolock, ret = %d\n", ret); + goto fail; + } + + /* + * sg[0] for input(S0) + * Sg[1] for output + */ + sg_init_table(sg, 3); + + buf->txd = pchan->dma_chan.device->device_prep_slave_sg( + &pchan->dma_chan, sg, 3, DMA_FROM_DEVICE, + DMA_PREP_INTERRUPT); + if (!buf->txd) { + ret = -EIO; + goto fail; + } + + buf->txd->callback_param = buf->txd; + buf->txd->callback = video_dma_done; + + desc = to_tx_desc(buf->txd); + length = desc->len; + for (i = 0; i < length; i++) { + if (i == 0) {/* S0 */ + memcpy(&desc->proc_data, proc_data, + sizeof(struct pxp_proc_data)); + pxp_conf->s0_param.paddr = + videobuf_to_dma_contig(vb); + memcpy(&desc->layer_param.s0_param, + &pxp_conf->s0_param, + sizeof(struct pxp_layer_param)); + } else if (i == 1) { /* Output */ + if (proc_data->rotate % 180) { + pxp_conf->out_param.width = + pxp->fb.fmt.height; + pxp_conf->out_param.height = + pxp->fb.fmt.width; + } else { + pxp_conf->out_param.width = + pxp->fb.fmt.width; + pxp_conf->out_param.height = + pxp->fb.fmt.height; + } + + pxp_conf->out_param.paddr = pxp->outb_phys; + memcpy(&desc->layer_param.out_param, + &pxp_conf->out_param, + sizeof(struct pxp_layer_param)); + } else if (pxp_conf->ol_param[0].combine_enable) { + /* Overlay */ + pxp_conf->ol_param[0].paddr = + (dma_addr_t)pxp->fb.base; + pxp_conf->ol_param[0].width = pxp->fb.fmt.width; + pxp_conf->ol_param[0].height = + pxp->fb.fmt.height; + pxp_conf->ol_param[0].pixel_fmt = + pxp_conf->out_param.pixel_fmt; + memcpy(&desc->layer_param.ol_param, + &pxp_conf->ol_param[0], + sizeof(struct pxp_layer_param)); + } + + desc = desc->next; + } + + vb->state = VIDEOBUF_PREPARED; + } + + return 0; + +fail: + pxp_buf_free(q, buf); + return ret; +} + + +static void pxp_buf_queue(struct videobuf_queue *q, + struct videobuf_buffer *vb) +{ + struct pxps *pxp = q->priv_data; + struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb); + struct dma_async_tx_descriptor *txd = buf->txd; + struct pxp_channel *pchan = pxp->pxp_channel[0]; + dma_cookie_t cookie; + + BUG_ON(!irqs_disabled()); + + list_add_tail(&vb->queue, &pxp->outq); + + if (!pxp->active) { + pxp->active = buf; + vb->state = VIDEOBUF_ACTIVE; + } else { + vb->state = VIDEOBUF_QUEUED; + } + + spin_unlock_irq(&pxp->lock); + + cookie = txd->tx_submit(txd); + dev_dbg(&pxp->pdev->dev, "Submitted cookie %d DMA 0x%08x\n", + cookie, sg_dma_address(&buf->sg[0])); + mdelay(5); + /* trigger ePxP */ + dma_async_issue_pending(&pchan->dma_chan); + + spin_lock_irq(&pxp->lock); + + if (cookie >= 0) + return; + + /* Submit error */ + pr_err("%s: Submit error\n", __func__); + vb->state = VIDEOBUF_PREPARED; + + list_del_init(&vb->queue); + + if (pxp->active == buf) + pxp->active = NULL; +} + +static void pxp_buf_release(struct videobuf_queue *q, + struct videobuf_buffer *vb) +{ + struct pxps *pxp = q->priv_data; + struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb); + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + if ((vb->state == VIDEOBUF_ACTIVE || vb->state == VIDEOBUF_QUEUED) && + !list_empty(&vb->queue)) { + vb->state = VIDEOBUF_ERROR; + + list_del_init(&vb->queue); + if (pxp->active == buf) + pxp->active = NULL; + } + spin_unlock_irqrestore(&pxp->lock, flags); + + pxp_buf_free(q, buf); +} + +static struct videobuf_queue_ops pxp_vbq_ops = { + .buf_setup = pxp_buf_setup, + .buf_prepare = pxp_buf_prepare, + .buf_queue = pxp_buf_queue, + .buf_release = pxp_buf_release, +}; + +static int pxp_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + memset(cap, 0, sizeof(*cap)); + strcpy(cap->driver, "pxp"); + strcpy(cap->card, "pxp"); + strlcpy(cap->bus_info, dev_name(&pxp->pdev->dev), + sizeof(cap->bus_info)); + + cap->version = (PXP_DRIVER_MAJOR << 8) + PXP_DRIVER_MINOR; + + cap->capabilities = V4L2_CAP_VIDEO_OUTPUT | + V4L2_CAP_VIDEO_OUTPUT_OVERLAY | + V4L2_CAP_STREAMING; + + return 0; +} + +static int pxp_g_fbuf(struct file *file, void *priv, + struct v4l2_framebuffer *fb) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + memset(fb, 0, sizeof(*fb)); + + fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY | + V4L2_FBUF_CAP_CHROMAKEY | + V4L2_FBUF_CAP_LOCAL_ALPHA | + V4L2_FBUF_CAP_GLOBAL_ALPHA; + + if (pxp->global_alpha_state) + fb->flags |= V4L2_FBUF_FLAG_GLOBAL_ALPHA; + if (pxp->s1_chromakey_state) + fb->flags |= V4L2_FBUF_FLAG_CHROMAKEY; + + return 0; +} + +static int pxp_s_fbuf(struct file *file, void *priv, + struct v4l2_framebuffer *fb) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + pxp->overlay_state = + (fb->flags & V4L2_FBUF_FLAG_OVERLAY) != 0; + pxp->global_alpha_state = + (fb->flags & V4L2_FBUF_FLAG_GLOBAL_ALPHA) != 0; + pxp->s1_chromakey_state = + (fb->flags & V4L2_FBUF_FLAG_CHROMAKEY) != 0; + + pxp->pxp_conf.ol_param[0].combine_enable = pxp->overlay_state; + pxp->pxp_conf.ol_param[0].global_alpha_enable = pxp->global_alpha_state; + + return 0; +} + +static int pxp_g_crop(struct file *file, void *fh, + struct v4l2_crop *c) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY) + return -EINVAL; + + c->c.left = pxp->pxp_conf.proc_data.drect.left; + c->c.top = pxp->pxp_conf.proc_data.drect.top; + c->c.width = pxp->pxp_conf.proc_data.drect.width; + c->c.height = pxp->pxp_conf.proc_data.drect.height; + + return 0; +} + +static int pxp_s_crop(struct file *file, void *fh, + struct v4l2_crop *c) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int l = c->c.left; + int t = c->c.top; + int w = c->c.width; + int h = c->c.height; + int fbw = pxp->fb.fmt.width; + int fbh = pxp->fb.fmt.height; + + if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY) + return -EINVAL; + + /* Constrain parameters to FB limits */ + w = min(w, fbw); + w = max(w, PXP_MIN_PIX); + h = min(h, fbh); + h = max(h, PXP_MIN_PIX); + if ((l + w) > fbw) + l = 0; + if ((t + h) > fbh) + t = 0; + + /* Round up values to PxP pixel block */ + l = roundup(l, PXP_MIN_PIX); + t = roundup(t, PXP_MIN_PIX); + w = roundup(w, PXP_MIN_PIX); + h = roundup(h, PXP_MIN_PIX); + + pxp->pxp_conf.proc_data.drect.left = l; + pxp->pxp_conf.proc_data.drect.top = t; + pxp->pxp_conf.proc_data.drect.width = w; + pxp->pxp_conf.proc_data.drect.height = h; + + return 0; +} + +static int pxp_queryctrl(struct file *file, void *priv, + struct v4l2_queryctrl *qc) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (qc->id && qc->id == pxp_controls[i].id) { + memcpy(qc, &(pxp_controls[i]), sizeof(*qc)); + return 0; + } + + return -EINVAL; +} + +static int pxp_g_ctrl(struct file *file, void *priv, + struct v4l2_control *vc) +{ + int i; + + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (vc->id == pxp_controls[i].id) + return pxp_get_cstate(pxp, vc); + + return -EINVAL; +} + +static int pxp_s_ctrl(struct file *file, void *priv, + struct v4l2_control *vc) +{ + int i; + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (vc->id == pxp_controls[i].id) { + if (vc->value < pxp_controls[i].minimum || + vc->value > pxp_controls[i].maximum) + return -ERANGE; + return pxp_set_cstate(pxp, vc); + } + + return -EINVAL; +} + +void pxp_release(struct video_device *vfd) +{ + struct pxps *pxp = video_get_drvdata(vfd); + + spin_lock(&pxp->lock); + video_device_release(vfd); + spin_unlock(&pxp->lock); +} + +static int pxp_open(struct file *file) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + mutex_lock(&pxp->mutex); + pxp->users++; + + if (pxp->users > 1) { + pxp->users--; + ret = -EBUSY; + goto out; + } +out: + mutex_unlock(&pxp->mutex); + if (ret) + return ret; + + videobuf_queue_dma_contig_init(&pxp->s0_vbq, + &pxp_vbq_ops, + &pxp->pdev->dev, + &pxp->lock, + V4L2_BUF_TYPE_VIDEO_OUTPUT, + V4L2_FIELD_NONE, + sizeof(struct pxp_buffer), + pxp); + dev_dbg(&pxp->pdev->dev, "call pxp_open\n"); + + return 0; +} + +static int pxp_close(struct file *file) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + videobuf_stop(&pxp->s0_vbq); + videobuf_mmap_free(&pxp->s0_vbq); + pxp->active = NULL; + kfree(pxp->outb); + pxp->outb = NULL; + + mutex_lock(&pxp->mutex); + pxp->users--; + mutex_unlock(&pxp->mutex); + + return 0; +} + +static int pxp_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret; + + ret = videobuf_mmap_mapper(&pxp->s0_vbq, vma); + + return ret; +} + +static const struct v4l2_file_operations pxp_fops = { + .owner = THIS_MODULE, + .open = pxp_open, + .release = pxp_close, + .ioctl = video_ioctl2, + .mmap = pxp_mmap, +}; + +static const struct v4l2_ioctl_ops pxp_ioctl_ops = { + .vidioc_querycap = pxp_querycap, + + .vidioc_reqbufs = pxp_reqbufs, + .vidioc_querybuf = pxp_querybuf, + .vidioc_qbuf = pxp_qbuf, + .vidioc_dqbuf = pxp_dqbuf, + + .vidioc_streamon = pxp_streamon, + .vidioc_streamoff = pxp_streamoff, + + .vidioc_enum_output = pxp_enumoutput, + .vidioc_g_output = pxp_g_output, + .vidioc_s_output = pxp_s_output, + + .vidioc_enum_fmt_vid_out = pxp_enum_fmt_video_output, + .vidioc_try_fmt_vid_out = pxp_try_fmt_video_output, + .vidioc_g_fmt_vid_out = pxp_g_fmt_video_output, + .vidioc_s_fmt_vid_out = pxp_s_fmt_video_output, + + .vidioc_try_fmt_vid_out_overlay = pxp_try_fmt_output_overlay, + .vidioc_g_fmt_vid_out_overlay = pxp_g_fmt_output_overlay, + .vidioc_s_fmt_vid_out_overlay = pxp_s_fmt_output_overlay, + + .vidioc_g_fbuf = pxp_g_fbuf, + .vidioc_s_fbuf = pxp_s_fbuf, + + .vidioc_g_crop = pxp_g_crop, + .vidioc_s_crop = pxp_s_crop, + + .vidioc_queryctrl = pxp_queryctrl, + .vidioc_g_ctrl = pxp_g_ctrl, + .vidioc_s_ctrl = pxp_s_ctrl, +}; + +static const struct video_device pxp_template = { + .name = "PxP", + .vfl_type = V4L2_CAP_VIDEO_OUTPUT | + V4L2_CAP_VIDEO_OVERLAY | + V4L2_CAP_STREAMING, + .fops = &pxp_fops, + .release = pxp_release, + .minor = -1, + .ioctl_ops = &pxp_ioctl_ops, +}; + +static int pxp_probe(struct platform_device *pdev) +{ + struct pxps *pxp; + int err = 0; + + pxp = kzalloc(sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + dev_set_drvdata(&pdev->dev, pxp); + + INIT_LIST_HEAD(&pxp->outq); + spin_lock_init(&pxp->lock); + mutex_init(&pxp->mutex); + + pxp->pdev = pdev; + + pxp->vdev = video_device_alloc(); + if (!pxp->vdev) { + dev_err(&pdev->dev, "video_device_alloc() failed\n"); + err = -ENOMEM; + goto freeirq; + } + + memcpy(pxp->vdev, &pxp_template, sizeof(pxp_template)); + video_set_drvdata(pxp->vdev, pxp); + + err = video_register_device(pxp->vdev, VFL_TYPE_GRABBER, 0); + if (err) { + dev_err(&pdev->dev, "failed to register video device\n"); + goto freevdev; + } + + err = pxp_set_fbinfo(pxp); + if (err) { + dev_err(&pdev->dev, "failed to call pxp_set_fbinfo\n"); + goto freevdev; + } + + dev_info(&pdev->dev, "initialized\n"); + +exit: + return err; + +freevdev: + video_device_release(pxp->vdev); + +freeirq: + kfree(pxp); + + return err; +} + +static int __devexit pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + video_unregister_device(pxp->vdev); + video_device_release(pxp->vdev); + + kfree(pxp); + + return 0; +} + +static struct platform_driver pxp_driver = { + .driver = { + .name = PXP_DRIVER_NAME, + }, + .probe = pxp_probe, + .remove = __exit_p(pxp_remove), +}; + + +static int __devinit pxp_init(void) +{ + return platform_driver_register(&pxp_driver); +} + +static void __exit pxp_exit(void) +{ + platform_driver_unregister(&pxp_driver); +} + +module_init(pxp_init); +module_exit(pxp_exit); + +MODULE_DESCRIPTION("MXC PxP V4L2 driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/output/mxc_pxp_v4l2.h b/drivers/media/video/mxc/output/mxc_pxp_v4l2.h new file mode 100644 index 000000000000..d17eea571374 --- /dev/null +++ b/drivers/media/video/mxc/output/mxc_pxp_v4l2.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#ifndef _MXC_PXP_V4L2_H +#define _MXC_PXP_V4L2_H + +#include +#include + +struct pxp_buffer { + /* Must be first! */ + struct videobuf_buffer vb; + + /* One descriptor per scatterlist (per frame) */ + struct dma_async_tx_descriptor *txd; + + struct scatterlist sg[3]; +}; + +struct pxps { + struct platform_device *pdev; + + spinlock_t lock; + struct mutex mutex; + int users; + + struct video_device *vdev; + + struct videobuf_queue s0_vbq; + struct pxp_buffer *active; + struct list_head outq; + struct pxp_channel *pxp_channel[1]; /* We need 1 channel */ + struct pxp_config_data pxp_conf; + + int output; + u32 *outb; + dma_addr_t outb_phys; + u32 outb_size; + + /* Current S0 configuration */ + struct pxp_data_format *s0_fmt; + + struct v4l2_framebuffer fb; + + /* Output overlay support */ + int overlay_state; + int global_alpha_state; + u8 global_alpha; + int s1_chromakey_state; + u32 s1_chromakey; + + int fb_blank; +}; + +struct pxp_data_format { + char *name; + unsigned int bpp; + u32 fourcc; + enum v4l2_colorspace colorspace; +}; + +#endif diff --git a/drivers/misc/fsl_cache.c b/drivers/misc/fsl_cache.c new file mode 100644 index 000000000000..3101aef60833 --- /dev/null +++ b/drivers/misc/fsl_cache.c @@ -0,0 +1,85 @@ +/* + * fsl_cache.c -- freescale cache driver + * + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + + +static int fsl_cache_ioctl(struct inode *ip, struct file *fp, + unsigned int cmd, unsigned long arg) +{ + struct fsl_cache_addr addr; + if (copy_from_user(&addr, (void __user *)arg, + sizeof(struct fsl_cache_addr))) { + printk(KERN_ERR "fsl_cache_ioctl failed!\n"); + return -EFAULT; + } + + if (addr.start <= 0 || addr.end <= addr.start) + return -EINVAL; + + switch (cmd) { + case FSLCACHE_IOCINV: + dmac_inv_range(addr.start, addr.end); + break; + case FSLCACHE_IOCCLEAN: + dmac_clean_range(addr.start, addr.end); + break; + case FSLCACHE_IOCFLUSH: + dmac_flush_range(addr.start, addr.end); + break; + default: + printk(KERN_ERR "fsl_cache ioctl: error cmd!\n"); + return -1; + } + return 0; +} + +static const struct file_operations misc_fops = { + .ioctl = fsl_cache_ioctl, +}; + +static struct miscdevice fsl_cache_device = { + .minor = MISC_DYNAMIC_MINOR, + .name = "fsl_cache", + .fops = &misc_fops, +}; + +static int __init fsl_cache_init(void) +{ + int error; + + error = misc_register(&fsl_cache_device); + if (error) { + printk(KERN_ERR "fsl_cache: misc_register failed!\n"); + return error; + } + return 0; +} + +static void __exit fsl_cache_exit(void) +{ + misc_deregister(&fsl_cache_device); +} + +module_init(fsl_cache_init); +module_exit(fsl_cache_exit); + +MODULE_DESCRIPTION("Freescale cache manipulation driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/misc/pmem.c b/drivers/misc/pmem.c new file mode 100644 index 000000000000..9e5e230aaad9 --- /dev/null +++ b/drivers/misc/pmem.c @@ -0,0 +1,1351 @@ +/* drivers/android/pmem.c + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PMEM_MAX_DEVICES 10 +#define PMEM_MAX_ORDER 128 +#define PMEM_MIN_ALLOC PAGE_SIZE + +#define PMEM_DEBUG 1 + +/* indicates that a refernce to this file has been taken via get_pmem_file, + * the file should not be released until put_pmem_file is called */ +#define PMEM_FLAGS_BUSY 0x1 +/* indicates that this is a suballocation of a larger master range */ +#define PMEM_FLAGS_CONNECTED 0x1 << 1 +/* indicates this is a master and not a sub allocation and that it is mmaped */ +#define PMEM_FLAGS_MASTERMAP 0x1 << 2 +/* submap and unsubmap flags indicate: + * 00: subregion has never been mmaped + * 10: subregion has been mmaped, reference to the mm was taken + * 11: subretion has ben released, refernece to the mm still held + * 01: subretion has been released, reference to the mm has been released + */ +#define PMEM_FLAGS_SUBMAP 0x1 << 3 +#define PMEM_FLAGS_UNSUBMAP 0x1 << 4 + + +struct pmem_data { + /* in alloc mode: an index into the bitmap + * in no_alloc mode: the size of the allocation */ + int index; + /* see flags above for descriptions */ + unsigned int flags; + /* protects this data field, if the mm_mmap sem will be held at the + * same time as this sem, the mm sem must be taken first (as this is + * the order for vma_open and vma_close ops */ + struct rw_semaphore sem; + /* info about the mmaping process */ + struct vm_area_struct *vma; + /* task struct of the mapping process */ + struct task_struct *task; + /* process id of teh mapping process */ + pid_t pid; + /* file descriptor of the master */ + int master_fd; + /* file struct of the master */ + struct file *master_file; + /* a list of currently available regions if this is a suballocation */ + struct list_head region_list; + /* a linked list of data so we can access them for debugging */ + struct list_head list; +#if PMEM_DEBUG + int ref; +#endif +}; + +struct pmem_bits { + unsigned allocated:1; /* 1 if allocated, 0 if free */ + unsigned order:7; /* size of the region in pmem space */ +}; + +struct pmem_region_node { + struct pmem_region region; + struct list_head list; +}; + +#define PMEM_DEBUG_MSGS 0 +#if PMEM_DEBUG_MSGS +#define DLOG(fmt,args...) \ + do { printk(KERN_INFO "[%s:%s:%d] "fmt, __FILE__, __func__, __LINE__, \ + ##args); } \ + while (0) +#else +#define DLOG(x...) do {} while (0) +#endif + +struct pmem_info { + struct miscdevice dev; + /* physical start address of the remaped pmem space */ + unsigned long base; + /* vitual start address of the remaped pmem space */ + unsigned char __iomem *vbase; + /* total size of the pmem space */ + unsigned long size; + /* number of entries in the pmem space */ + unsigned long num_entries; + /* pfn of the garbage page in memory */ + unsigned long garbage_pfn; + /* index of the garbage page in the pmem space */ + int garbage_index; + /* the bitmap for the region indicating which entries are allocated + * and which are free */ + struct pmem_bits *bitmap; + /* indicates the region should not be managed with an allocator */ + unsigned no_allocator; + /* indicates maps of this region should be cached, if a mix of + * cached and uncached is desired, set this and open the device with + * O_SYNC to get an uncached region */ + unsigned cached; + unsigned buffered; + /* in no_allocator mode the first mapper gets the whole space and sets + * this flag */ + unsigned allocated; + /* for debugging, creates a list of pmem file structs, the + * data_list_sem should be taken before pmem_data->sem if both are + * needed */ + struct semaphore data_list_sem; + struct list_head data_list; + /* pmem_sem protects the bitmap array + * a write lock should be held when modifying entries in bitmap + * a read lock should be held when reading data from bits or + * dereferencing a pointer into bitmap + * + * pmem_data->sem protects the pmem data of a particular file + * Many of the function that require the pmem_data->sem have a non- + * locking version for when the caller is already holding that sem. + * + * IF YOU TAKE BOTH LOCKS TAKE THEM IN THIS ORDER: + * down(pmem_data->sem) => down(bitmap_sem) + */ + struct rw_semaphore bitmap_sem; + + long (*ioctl)(struct file *, unsigned int, unsigned long); + int (*release)(struct inode *, struct file *); +}; + +static struct pmem_info pmem[PMEM_MAX_DEVICES]; +static int id_count; + +#define PMEM_IS_FREE(id, index) !(pmem[id].bitmap[index].allocated) +#define PMEM_ORDER(id, index) pmem[id].bitmap[index].order +#define PMEM_BUDDY_INDEX(id, index) (index ^ (1 << PMEM_ORDER(id, index))) +#define PMEM_NEXT_INDEX(id, index) (index + (1 << PMEM_ORDER(id, index))) +#define PMEM_OFFSET(index) (index * PMEM_MIN_ALLOC) +#define PMEM_START_ADDR(id, index) (PMEM_OFFSET(index) + pmem[id].base) +#define PMEM_LEN(id, index) ((1 << PMEM_ORDER(id, index)) * PMEM_MIN_ALLOC) +#define PMEM_END_ADDR(id, index) (PMEM_START_ADDR(id, index) + \ + PMEM_LEN(id, index)) +#define PMEM_START_VADDR(id, index) (PMEM_OFFSET(id, index) + pmem[id].vbase) +#define PMEM_END_VADDR(id, index) (PMEM_START_VADDR(id, index) + \ + PMEM_LEN(id, index)) +#define PMEM_REVOKED(data) (data->flags & PMEM_FLAGS_REVOKED) +#define PMEM_IS_PAGE_ALIGNED(addr) (!((addr) & (~PAGE_MASK))) +#define PMEM_IS_SUBMAP(data) ((data->flags & PMEM_FLAGS_SUBMAP) && \ + (!(data->flags & PMEM_FLAGS_UNSUBMAP))) + +static int pmem_release(struct inode *, struct file *); +static int pmem_mmap(struct file *, struct vm_area_struct *); +static int pmem_open(struct inode *, struct file *); +static long pmem_ioctl(struct file *, unsigned int, unsigned long); + +struct file_operations pmem_fops = { + .release = pmem_release, + .mmap = pmem_mmap, + .open = pmem_open, + .unlocked_ioctl = pmem_ioctl, +}; + +static int get_id(struct file *file) +{ + return MINOR(file->f_dentry->d_inode->i_rdev); +} + +int is_pmem_file(struct file *file) +{ + int id; + + if (unlikely(!file || !file->f_dentry || !file->f_dentry->d_inode)) + return 0; + id = get_id(file); + if (unlikely(id >= PMEM_MAX_DEVICES)) + return 0; + if (unlikely(file->f_dentry->d_inode->i_rdev != + MKDEV(MISC_MAJOR, pmem[id].dev.minor))) + return 0; + return 1; +} + +static int has_allocation(struct file *file) +{ + struct pmem_data *data; + /* check is_pmem_file first if not accessed via pmem_file_ops */ + + if (unlikely(!file->private_data)) + return 0; + data = (struct pmem_data *)file->private_data; + if (unlikely(data->index < 0)) + return 0; + return 1; +} + +static int is_master_owner(struct file *file) +{ + struct file *master_file; + struct pmem_data *data; + int put_needed, ret = 0; + + if (!is_pmem_file(file) || !has_allocation(file)) + return 0; + data = (struct pmem_data *)file->private_data; + if (PMEM_FLAGS_MASTERMAP & data->flags) + return 1; + master_file = fget_light(data->master_fd, &put_needed); + if (master_file && data->master_file == master_file) + ret = 1; + fput_light(master_file, put_needed); + return ret; +} + +static int pmem_free(int id, int index) +{ + /* caller should hold the write lock on pmem_sem! */ + int buddy, curr = index; + DLOG("index %d\n", index); + + if (pmem[id].no_allocator) { + pmem[id].allocated = 0; + return 0; + } + /* clean up the bitmap, merging any buddies */ + pmem[id].bitmap[curr].allocated = 0; + /* find a slots buddy Buddy# = Slot# ^ (1 << order) + * if the buddy is also free merge them + * repeat until the buddy is not free or end of the bitmap is reached + */ + do { + buddy = PMEM_BUDDY_INDEX(id, curr); + if (PMEM_IS_FREE(id, buddy) && + PMEM_ORDER(id, buddy) == PMEM_ORDER(id, curr)) { + PMEM_ORDER(id, buddy)++; + PMEM_ORDER(id, curr)++; + curr = min(buddy, curr); + } else { + break; + } + } while (curr < pmem[id].num_entries); + + return 0; +} + +static void pmem_revoke(struct file *file, struct pmem_data *data); + +static int pmem_release(struct inode *inode, struct file *file) +{ + struct pmem_data *data = (struct pmem_data *)file->private_data; + struct pmem_region_node *region_node; + struct list_head *elt, *elt2; + int id = get_id(file), ret = 0; + + + down(&pmem[id].data_list_sem); + /* if this file is a master, revoke all the memory in the connected + * files */ + if (PMEM_FLAGS_MASTERMAP & data->flags) { + struct pmem_data *sub_data; + list_for_each(elt, &pmem[id].data_list) { + sub_data = list_entry(elt, struct pmem_data, list); + down_read(&sub_data->sem); + if (PMEM_IS_SUBMAP(sub_data) && + file == sub_data->master_file) { + up_read(&sub_data->sem); + pmem_revoke(file, sub_data); + } else + up_read(&sub_data->sem); + } + } + list_del(&data->list); + up(&pmem[id].data_list_sem); + + + down_write(&data->sem); + + /* if its not a conencted file and it has an allocation, free it */ + if (!(PMEM_FLAGS_CONNECTED & data->flags) && has_allocation(file)) { + down_write(&pmem[id].bitmap_sem); + ret = pmem_free(id, data->index); + up_write(&pmem[id].bitmap_sem); + } + + /* if this file is a submap (mapped, connected file), downref the + * task struct */ + if (PMEM_FLAGS_SUBMAP & data->flags) + if (data->task) { + put_task_struct(data->task); + data->task = NULL; + } + + file->private_data = NULL; + + list_for_each_safe(elt, elt2, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, list); + list_del(elt); + kfree(region_node); + } + BUG_ON(!list_empty(&data->region_list)); + + up_write(&data->sem); + kfree(data); + if (pmem[id].release) + ret = pmem[id].release(inode, file); + + return ret; +} + +static int pmem_open(struct inode *inode, struct file *file) +{ + struct pmem_data *data; + int id = get_id(file); + int ret = 0; + + DLOG("current %u file %p(%d)\n", current->pid, file, file_count(file)); + /* setup file->private_data to indicate its unmapped */ + /* you can only open a pmem device one time */ + if (file->private_data != NULL) + return -1; + data = kmalloc(sizeof(struct pmem_data), GFP_KERNEL); + if (!data) { + printk("pmem: unable to allocate memory for pmem metadata."); + return -1; + } + data->flags = 0; + data->index = -1; + data->task = NULL; + data->vma = NULL; + data->pid = 0; + data->master_file = NULL; +#if PMEM_DEBUG + data->ref = 0; +#endif + INIT_LIST_HEAD(&data->region_list); + init_rwsem(&data->sem); + + file->private_data = data; + INIT_LIST_HEAD(&data->list); + + down(&pmem[id].data_list_sem); + list_add(&data->list, &pmem[id].data_list); + up(&pmem[id].data_list_sem); + return ret; +} + +static unsigned long pmem_order(unsigned long len) +{ + int i; + + len = (len + PMEM_MIN_ALLOC - 1)/PMEM_MIN_ALLOC; + len--; + for (i = 0; i < sizeof(len)*8; i++) + if (len >> i == 0) + break; + return i; +} + +static int pmem_allocate(int id, unsigned long len) +{ + /* caller should hold the write lock on pmem_sem! */ + /* return the corresponding pdata[] entry */ + int curr = 0; + int end = pmem[id].num_entries; + int best_fit = -1; + unsigned long order = pmem_order(len); + + if (pmem[id].no_allocator) { + DLOG("no allocator"); + if ((len > pmem[id].size) || pmem[id].allocated) + return -1; + pmem[id].allocated = 1; + return len; + } + + if (order > PMEM_MAX_ORDER) + return -1; + DLOG("order %lx\n", order); + + /* look through the bitmap: + * if you find a free slot of the correct order use it + * otherwise, use the best fit (smallest with size > order) slot + */ + while (curr < end) { + if (PMEM_IS_FREE(id, curr)) { + if (PMEM_ORDER(id, curr) == (unsigned char)order) { + /* set the not free bit and clear others */ + best_fit = curr; + break; + } + if (PMEM_ORDER(id, curr) > (unsigned char)order && + (best_fit < 0 || + PMEM_ORDER(id, curr) < PMEM_ORDER(id, best_fit))) + best_fit = curr; + } + curr = PMEM_NEXT_INDEX(id, curr); + } + + /* if best_fit < 0, there are no suitable slots, + * return an error + */ + if (best_fit < 0) { + printk("pmem: no space left to allocate!\n"); + return -1; + } + + /* now partition the best fit: + * split the slot into 2 buddies of order - 1 + * repeat until the slot is of the correct order + */ + while (PMEM_ORDER(id, best_fit) > (unsigned char)order) { + int buddy; + PMEM_ORDER(id, best_fit) -= 1; + buddy = PMEM_BUDDY_INDEX(id, best_fit); + PMEM_ORDER(id, buddy) = PMEM_ORDER(id, best_fit); + } + pmem[id].bitmap[best_fit].allocated = 1; + return best_fit; +} + +static pgprot_t phys_mem_access_prot(struct file *file, pgprot_t vma_prot) +{ + int id = get_id(file); +#ifdef pgprot_noncached + if (pmem[id].cached == PMEM_NONCACHE_DEVICE || file->f_flags & O_SYNC) + return pgprot_noncached(vma_prot); +#endif + +#ifdef pgprot_writecombine + else if (pmem[id].cached == PMEM_NONCACHE_NORMAL) + return pgprot_writecombine(vma_prot); +#endif + +#ifdef pgprot_ext_buffered + else if (pmem[id].buffered) + return pgprot_ext_buffered(vma_prot); +#endif + return vma_prot; +} + +static unsigned long pmem_start_addr(int id, struct pmem_data *data) +{ + if (pmem[id].no_allocator) + return PMEM_START_ADDR(id, 0); + else + return PMEM_START_ADDR(id, data->index); + +} + +static void *pmem_start_vaddr(int id, struct pmem_data *data) +{ + return pmem_start_addr(id, data) - pmem[id].base + pmem[id].vbase; +} + +static unsigned long pmem_len(int id, struct pmem_data *data) +{ + if (pmem[id].no_allocator) + return data->index; + else + return PMEM_LEN(id, data->index); +} + +static int pmem_map_garbage(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + int i, garbage_pages = len >> PAGE_SHIFT; + + vma->vm_flags |= VM_IO | VM_RESERVED | VM_PFNMAP | VM_SHARED | VM_WRITE; + for (i = 0; i < garbage_pages; i++) { + if (vm_insert_pfn(vma, vma->vm_start + offset + (i * PAGE_SIZE), + pmem[id].garbage_pfn)) + return -EAGAIN; + } + return 0; +} + +static int pmem_unmap_pfn_range(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + int garbage_pages; + DLOG("unmap offset %lx len %lx\n", offset, len); + + BUG_ON(!PMEM_IS_PAGE_ALIGNED(len)); + + garbage_pages = len >> PAGE_SHIFT; + zap_page_range(vma, vma->vm_start + offset, len, NULL); + pmem_map_garbage(id, vma, data, offset, len); + return 0; +} + +static int pmem_map_pfn_range(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + DLOG("map offset %lx len %lx\n", offset, len); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(vma->vm_start)); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(vma->vm_end)); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(len)); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(offset)); + + if (io_remap_pfn_range(vma, vma->vm_start + offset, + (pmem_start_addr(id, data) + offset) >> PAGE_SHIFT, + len, vma->vm_page_prot)) { + return -EAGAIN; + } + return 0; +} + +static int pmem_remap_pfn_range(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + /* hold the mm semp for the vma you are modifying when you call this */ + BUG_ON(!vma); + zap_page_range(vma, vma->vm_start + offset, len, NULL); + return pmem_map_pfn_range(id, vma, data, offset, len); +} + +static void pmem_vma_open(struct vm_area_struct *vma) +{ + struct file *file = vma->vm_file; + struct pmem_data *data = file->private_data; + int id = get_id(file); + /* this should never be called as we don't support copying pmem + * ranges via fork */ + BUG_ON(!has_allocation(file)); + down_write(&data->sem); + /* remap the garbage pages, forkers don't get access to the data */ + pmem_unmap_pfn_range(id, vma, data, 0, vma->vm_start - vma->vm_end); + up_write(&data->sem); +} + +static void pmem_vma_close(struct vm_area_struct *vma) +{ + struct file *file = vma->vm_file; + struct pmem_data *data = file->private_data; + + DLOG("current %u ppid %u file %p count %d\n", current->pid, + current->parent->pid, file, file_count(file)); + if (unlikely(!is_pmem_file(file) || !has_allocation(file))) { + printk(KERN_WARNING "pmem: something is very wrong, you are " + "closing a vm backing an allocation that doesn't " + "exist!\n"); + return; + } + down_write(&data->sem); + if (data->vma == vma) { + data->vma = NULL; + if ((data->flags & PMEM_FLAGS_CONNECTED) && + (data->flags & PMEM_FLAGS_SUBMAP)) + data->flags |= PMEM_FLAGS_UNSUBMAP; + } + /* the kernel is going to free this vma now anyway */ + up_write(&data->sem); +} + +static struct vm_operations_struct vm_ops = { + .open = pmem_vma_open, + .close = pmem_vma_close, +}; + +static int pmem_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct pmem_data *data; + int index; + unsigned long vma_size = vma->vm_end - vma->vm_start; + int ret = 0, id = get_id(file); + + if (vma->vm_pgoff || !PMEM_IS_PAGE_ALIGNED(vma_size)) { +#if PMEM_DEBUG + printk(KERN_ERR "pmem: mmaps must be at offset zero, aligned" + " and a multiple of pages_size.\n"); +#endif + return -EINVAL; + } + + data = (struct pmem_data *)file->private_data; + down_write(&data->sem); + /* check this file isn't already mmaped, for submaps check this file + * has never been mmaped */ + if ((data->flags & PMEM_FLAGS_MASTERMAP) || + (data->flags & PMEM_FLAGS_SUBMAP) || + (data->flags & PMEM_FLAGS_UNSUBMAP)) { +#if PMEM_DEBUG + printk(KERN_ERR "pmem: you can only mmap a pmem file once, " + "this file is already mmaped. %x\n", data->flags); +#endif + ret = -EINVAL; + goto error; + } + /* if file->private_data == unalloced, alloc*/ + if (data && data->index == -1) { + down_write(&pmem[id].bitmap_sem); + index = pmem_allocate(id, vma->vm_end - vma->vm_start); + up_write(&pmem[id].bitmap_sem); + data->index = index; + } + /* either no space was available or an error occured */ + if (!has_allocation(file)) { + ret = -EINVAL; + printk("pmem: could not find allocation for map.\n"); + goto error; + } + + if (pmem_len(id, data) < vma_size) { +#if PMEM_DEBUG + printk(KERN_WARNING "pmem: mmap size [%lu] does not match" + "size of backing region [%lu].\n", vma_size, + pmem_len(id, data)); +#endif + ret = -EINVAL; + goto error; + } + + vma->vm_pgoff = pmem_start_addr(id, data) >> PAGE_SHIFT; + vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_page_prot); + + if (data->flags & PMEM_FLAGS_CONNECTED) { + struct pmem_region_node *region_node; + struct list_head *elt; + if (pmem_map_garbage(id, vma, data, 0, vma_size)) { + printk("pmem: mmap failed in kernel!\n"); + ret = -EAGAIN; + goto error; + } + list_for_each(elt, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, + list); + DLOG("remapping file: %p %lx %lx\n", file, + region_node->region.offset, + region_node->region.len); + if (pmem_remap_pfn_range(id, vma, data, + region_node->region.offset, + region_node->region.len)) { + ret = -EAGAIN; + goto error; + } + } + data->flags |= PMEM_FLAGS_SUBMAP; + get_task_struct(current->group_leader); + data->task = current->group_leader; + data->vma = vma; +#if PMEM_DEBUG + data->pid = current->pid; +#endif + DLOG("submmapped file %p vma %p pid %u\n", file, vma, + current->pid); + } else { + if (pmem_map_pfn_range(id, vma, data, 0, vma_size)) { + printk(KERN_INFO "pmem: mmap failed in kernel!\n"); + ret = -EAGAIN; + goto error; + } + data->flags |= PMEM_FLAGS_MASTERMAP; + data->pid = current->pid; + } + vma->vm_ops = &vm_ops; +error: + up_write(&data->sem); + return ret; +} + +/* the following are the api for accessing pmem regions by other drivers + * from inside the kernel */ +int get_pmem_user_addr(struct file *file, unsigned long *start, + unsigned long *len) +{ + struct pmem_data *data; + if (!is_pmem_file(file) || !has_allocation(file)) { +#if PMEM_DEBUG + printk(KERN_INFO "pmem: requested pmem data from invalid" + "file.\n"); +#endif + return -1; + } + data = (struct pmem_data *)file->private_data; + down_read(&data->sem); + if (data->vma) { + *start = data->vma->vm_start; + *len = data->vma->vm_end - data->vma->vm_start; + } else { + *start = 0; + *len = 0; + } + up_read(&data->sem); + return 0; +} + +int get_pmem_addr(struct file *file, unsigned long *start, + unsigned long *vstart, unsigned long *len) +{ + struct pmem_data *data; + int id; + + if (!is_pmem_file(file) || !has_allocation(file)) { + return -1; + } + + data = (struct pmem_data *)file->private_data; + if (data->index == -1) { +#if PMEM_DEBUG + printk(KERN_INFO "pmem: requested pmem data from file with no " + "allocation.\n"); + return -1; +#endif + } + id = get_id(file); + + down_read(&data->sem); + *start = pmem_start_addr(id, data); + *len = pmem_len(id, data); + *vstart = (unsigned long)pmem_start_vaddr(id, data); + up_read(&data->sem); +#if PMEM_DEBUG + down_write(&data->sem); + data->ref++; + up_write(&data->sem); +#endif + return 0; +} + +int get_pmem_file(int fd, unsigned long *start, unsigned long *vstart, + unsigned long *len, struct file **filp) +{ + struct file *file; + + file = fget(fd); + if (unlikely(file == NULL)) { + printk(KERN_INFO "pmem: requested data from file descriptor " + "that doesn't exist."); + return -1; + } + + if (get_pmem_addr(file, start, vstart, len)) + goto end; + + if (filp) + *filp = file; + return 0; +end: + fput(file); + return -1; +} + +void put_pmem_file(struct file *file) +{ + struct pmem_data *data; + int id; + + if (!is_pmem_file(file)) + return; + id = get_id(file); + data = (struct pmem_data *)file->private_data; +#if PMEM_DEBUG + down_write(&data->sem); + if (data->ref == 0) { + printk("pmem: pmem_put > pmem_get %s (pid %d)\n", + pmem[id].dev.name, data->pid); + BUG(); + } + data->ref--; + up_write(&data->sem); +#endif + fput(file); +} + +void flush_pmem_file(struct file *file, unsigned long offset, unsigned long len) +{ + struct pmem_data *data; + int id; + void *vaddr; + struct pmem_region_node *region_node; + struct list_head *elt; + void *flush_start, *flush_end; + + if (!is_pmem_file(file) || !has_allocation(file)) { + return; + } + + id = get_id(file); + data = (struct pmem_data *)file->private_data; + if (!pmem[id].cached || file->f_flags & O_SYNC) + return; + + down_read(&data->sem); + vaddr = pmem_start_vaddr(id, data); + /* if this isn't a submmapped file, flush the whole thing */ + if (unlikely(!(data->flags & PMEM_FLAGS_CONNECTED))) { + dmac_flush_range(vaddr, vaddr + pmem_len(id, data)); + goto end; + } + /* otherwise, flush the region of the file we are drawing */ + list_for_each(elt, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, list); + if ((offset >= region_node->region.offset) && + ((offset + len) <= (region_node->region.offset + + region_node->region.len))) { + flush_start = vaddr + region_node->region.offset; + flush_end = flush_start + region_node->region.len; + dmac_flush_range(flush_start, flush_end); + break; + } + } +end: + up_read(&data->sem); +} + +static int pmem_connect(unsigned long connect, struct file *file) +{ + struct pmem_data *data = (struct pmem_data *)file->private_data; + struct pmem_data *src_data; + struct file *src_file; + int ret = 0, put_needed; + + down_write(&data->sem); + /* retrieve the src file and check it is a pmem file with an alloc */ + src_file = fget_light(connect, &put_needed); + DLOG("connect %p to %p\n", file, src_file); + if (!src_file) { + printk("pmem: src file not found!\n"); + ret = -EINVAL; + goto err_no_file; + } + if (unlikely(!is_pmem_file(src_file) || !has_allocation(src_file))) { + printk(KERN_INFO "pmem: src file is not a pmem file or has no " + "alloc!\n"); + ret = -EINVAL; + goto err_bad_file; + } + src_data = (struct pmem_data *)src_file->private_data; + + if (has_allocation(file) && (data->index != src_data->index)) { + printk("pmem: file is already mapped but doesn't match this" + " src_file!\n"); + ret = -EINVAL; + goto err_bad_file; + } + data->index = src_data->index; + data->flags |= PMEM_FLAGS_CONNECTED; + data->master_fd = connect; + data->master_file = src_file; + +err_bad_file: + fput_light(src_file, put_needed); +err_no_file: + up_write(&data->sem); + return ret; +} + +static void pmem_unlock_data_and_mm(struct pmem_data *data, + struct mm_struct *mm) +{ + up_write(&data->sem); + if (mm != NULL) { + up_write(&mm->mmap_sem); + mmput(mm); + } +} + +static int pmem_lock_data_and_mm(struct file *file, struct pmem_data *data, + struct mm_struct **locked_mm) +{ + int ret = 0; + struct mm_struct *mm = NULL; + *locked_mm = NULL; +lock_mm: + down_read(&data->sem); + if (PMEM_IS_SUBMAP(data)) { + mm = get_task_mm(data->task); + if (!mm) { +#if PMEM_DEBUG + printk("pmem: can't remap task is gone!\n"); +#endif + up_read(&data->sem); + return -1; + } + } + up_read(&data->sem); + + if (mm) + down_write(&mm->mmap_sem); + + down_write(&data->sem); + /* check that the file didn't get mmaped before we could take the + * data sem, this should be safe b/c you can only submap each file + * once */ + if (PMEM_IS_SUBMAP(data) && !mm) { + pmem_unlock_data_and_mm(data, mm); + up_write(&data->sem); + goto lock_mm; + } + /* now check that vma.mm is still there, it could have been + * deleted by vma_close before we could get the data->sem */ + if ((data->flags & PMEM_FLAGS_UNSUBMAP) && (mm != NULL)) { + /* might as well release this */ + if (data->flags & PMEM_FLAGS_SUBMAP) { + put_task_struct(data->task); + data->task = NULL; + /* lower the submap flag to show the mm is gone */ + data->flags &= ~(PMEM_FLAGS_SUBMAP); + } + pmem_unlock_data_and_mm(data, mm); + return -1; + } + *locked_mm = mm; + return ret; +} + +int pmem_remap(struct pmem_region *region, struct file *file, + unsigned operation) +{ + int ret; + struct pmem_region_node *region_node; + struct mm_struct *mm = NULL; + struct list_head *elt, *elt2; + int id = get_id(file); + struct pmem_data *data = (struct pmem_data *)file->private_data; + + /* pmem region must be aligned on a page boundry */ + if (unlikely(!PMEM_IS_PAGE_ALIGNED(region->offset) || + !PMEM_IS_PAGE_ALIGNED(region->len))) { +#if PMEM_DEBUG + printk("pmem: request for unaligned pmem suballocation " + "%lx %lx\n", region->offset, region->len); +#endif + return -EINVAL; + } + + /* if userspace requests a region of len 0, there's nothing to do */ + if (region->len == 0) + return 0; + + /* lock the mm and data */ + ret = pmem_lock_data_and_mm(file, data, &mm); + if (ret) + return 0; + + /* only the owner of the master file can remap the client fds + * that back in it */ + if (!is_master_owner(file)) { +#if PMEM_DEBUG + printk("pmem: remap requested from non-master process\n"); +#endif + ret = -EINVAL; + goto err; + } + + /* check that the requested range is within the src allocation */ + if (unlikely((region->offset > pmem_len(id, data)) || + (region->len > pmem_len(id, data)) || + (region->offset + region->len > pmem_len(id, data)))) { +#if PMEM_DEBUG + printk(KERN_INFO "pmem: suballoc doesn't fit in src_file!\n"); +#endif + ret = -EINVAL; + goto err; + } + + if (operation == PMEM_MAP) { + region_node = kmalloc(sizeof(struct pmem_region_node), + GFP_KERNEL); + if (!region_node) { + ret = -ENOMEM; +#if PMEM_DEBUG + printk(KERN_INFO "No space to allocate metadata!"); +#endif + goto err; + } + region_node->region = *region; + list_add(®ion_node->list, &data->region_list); + } else if (operation == PMEM_UNMAP) { + int found = 0; + list_for_each_safe(elt, elt2, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, + list); + if (region->len == 0 || + (region_node->region.offset == region->offset && + region_node->region.len == region->len)) { + list_del(elt); + kfree(region_node); + found = 1; + } + } + if (!found) { +#if PMEM_DEBUG + printk("pmem: Unmap region does not map any mapped " + "region!"); +#endif + ret = -EINVAL; + goto err; + } + } + + if (data->vma && PMEM_IS_SUBMAP(data)) { + if (operation == PMEM_MAP) + ret = pmem_remap_pfn_range(id, data->vma, data, + region->offset, region->len); + else if (operation == PMEM_UNMAP) + ret = pmem_unmap_pfn_range(id, data->vma, data, + region->offset, region->len); + } + +err: + pmem_unlock_data_and_mm(data, mm); + return ret; +} + +static void pmem_revoke(struct file *file, struct pmem_data *data) +{ + struct pmem_region_node *region_node; + struct list_head *elt, *elt2; + struct mm_struct *mm = NULL; + int id = get_id(file); + int ret = 0; + + data->master_file = NULL; + ret = pmem_lock_data_and_mm(file, data, &mm); + /* if lock_data_and_mm fails either the task that mapped the fd, or + * the vma that mapped it have already gone away, nothing more + * needs to be done */ + if (ret) + return; + /* unmap everything */ + /* delete the regions and region list nothing is mapped any more */ + if (data->vma) + list_for_each_safe(elt, elt2, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, + list); + pmem_unmap_pfn_range(id, data->vma, data, + region_node->region.offset, + region_node->region.len); + list_del(elt); + kfree(region_node); + } + /* delete the master file */ + pmem_unlock_data_and_mm(data, mm); +} + +static void pmem_get_size(struct pmem_region *region, struct file *file) +{ + struct pmem_data *data = (struct pmem_data *)file->private_data; + int id = get_id(file); + + if (!has_allocation(file)) { + region->offset = 0; + region->len = 0; + return; + } else { + region->offset = pmem_start_addr(id, data); + region->len = pmem_len(id, data); + } + DLOG("offset %lx len %lx\n", region->offset, region->len); +} + + +static long pmem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct pmem_data *data; + int id = get_id(file); + + switch (cmd) { + case PMEM_GET_PHYS: + { + struct pmem_region region; + DLOG("get_phys\n"); + if (!has_allocation(file)) { + region.offset = 0; + region.len = 0; + } else { + data = (struct pmem_data *)file->private_data; + region.offset = pmem_start_addr(id, data); + region.len = pmem_len(id, data); + } + printk(KERN_INFO "pmem: request for physical address of pmem region " + "from process %d.\n", current->pid); + if (copy_to_user((void __user *)arg, ®ion, + sizeof(struct pmem_region))) + return -EFAULT; + break; + } + case PMEM_MAP: + { + struct pmem_region region; + if (copy_from_user(®ion, (void __user *)arg, + sizeof(struct pmem_region))) + return -EFAULT; + data = (struct pmem_data *)file->private_data; + return pmem_remap(®ion, file, PMEM_MAP); + } + break; + case PMEM_UNMAP: + { + struct pmem_region region; + if (copy_from_user(®ion, (void __user *)arg, + sizeof(struct pmem_region))) + return -EFAULT; + data = (struct pmem_data *)file->private_data; + return pmem_remap(®ion, file, PMEM_UNMAP); + break; + } + case PMEM_GET_SIZE: + { + struct pmem_region region; + DLOG("get_size\n"); + pmem_get_size(®ion, file); + if (copy_to_user((void __user *)arg, ®ion, + sizeof(struct pmem_region))) + return -EFAULT; + break; + } + case PMEM_GET_TOTAL_SIZE: + { + struct pmem_region region; + DLOG("get total size\n"); + region.offset = 0; + get_id(file); + region.len = pmem[id].size; + if (copy_to_user((void __user *)arg, ®ion, + sizeof(struct pmem_region))) + return -EFAULT; + break; + } + case PMEM_ALLOCATE: + { + if (has_allocation(file)) + return -EINVAL; + data = (struct pmem_data *)file->private_data; + data->index = pmem_allocate(id, arg); + break; + } + case PMEM_CONNECT: + DLOG("connect\n"); + return pmem_connect(arg, file); + break; + case PMEM_CACHE_FLUSH: + { + struct pmem_region region; + DLOG("flush\n"); + if (copy_from_user(®ion, (void __user *)arg, + sizeof(struct pmem_region))) + return -EFAULT; + flush_pmem_file(file, region.offset, region.len); + break; + } + default: + if (pmem[id].ioctl) + return pmem[id].ioctl(file, cmd, arg); + return -EINVAL; + } + return 0; +} + +#if PMEM_DEBUG +static ssize_t debug_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static ssize_t debug_read(struct file *file, char __user *buf, size_t count, + loff_t *ppos) +{ + struct list_head *elt, *elt2; + struct pmem_data *data; + struct pmem_region_node *region_node; + int id = (int)file->private_data; + const int debug_bufmax = 4096; + static char buffer[4096]; + int n = 0; + + DLOG("debug open\n"); + n = scnprintf(buffer, debug_bufmax, + "pid #: mapped regions (offset, len) (offset,len)...\n"); + + down(&pmem[id].data_list_sem); + list_for_each(elt, &pmem[id].data_list) { + data = list_entry(elt, struct pmem_data, list); + down_read(&data->sem); + n += scnprintf(buffer + n, debug_bufmax - n, "pid %u:", + data->pid); + list_for_each(elt2, &data->region_list) { + region_node = list_entry(elt2, struct pmem_region_node, + list); + n += scnprintf(buffer + n, debug_bufmax - n, + "(%lx,%lx) ", + region_node->region.offset, + region_node->region.len); + } + n += scnprintf(buffer + n, debug_bufmax - n, "\n"); + up_read(&data->sem); + } + up(&pmem[id].data_list_sem); + + n++; + buffer[n] = 0; + return simple_read_from_buffer(buf, count, ppos, buffer, n); +} + +static struct file_operations debug_fops = { + .read = debug_read, + .open = debug_open, +}; +#endif + +#if 0 +static struct miscdevice pmem_dev = { + .name = "pmem", + .fops = &pmem_fops, +}; +#endif + +int pmem_setup(struct android_pmem_platform_data *pdata, + long (*ioctl)(struct file *, unsigned int, unsigned long), + int (*release)(struct inode *, struct file *)) +{ + int err = 0; + int i, index = 0; + int id = id_count; + id_count++; + + pmem[id].no_allocator = pdata->no_allocator; + pmem[id].cached = pdata->cached; + pmem[id].buffered = pdata->buffered; + pmem[id].base = pdata->start; + pmem[id].size = pdata->size; + pmem[id].ioctl = ioctl; + pmem[id].release = release; + init_rwsem(&pmem[id].bitmap_sem); + init_MUTEX(&pmem[id].data_list_sem); + INIT_LIST_HEAD(&pmem[id].data_list); + pmem[id].dev.name = pdata->name; + pmem[id].dev.minor = id; + pmem[id].dev.fops = &pmem_fops; + printk(KERN_INFO "%s: %d init\n", pdata->name, pdata->cached); + + err = misc_register(&pmem[id].dev); + if (err) { + printk(KERN_ALERT "Unable to register pmem driver!\n"); + goto err_cant_register_device; + } + pmem[id].num_entries = pmem[id].size / PMEM_MIN_ALLOC; + + pmem[id].bitmap = kmalloc(pmem[id].num_entries * + sizeof(struct pmem_bits), GFP_KERNEL); + if (!pmem[id].bitmap) + goto err_no_mem_for_metadata; + + memset(pmem[id].bitmap, 0, sizeof(struct pmem_bits) * + pmem[id].num_entries); + + for (i = sizeof(pmem[id].num_entries) * 8 - 1; i >= 0; i--) { + if ((pmem[id].num_entries) & 1<name, S_IFREG | S_IRUGO, NULL, (void *)id, + &debug_fops); +#endif + return 0; +error_cant_remap: + kfree(pmem[id].bitmap); +err_no_mem_for_metadata: + misc_deregister(&pmem[id].dev); +err_cant_register_device: + return -1; +} + +static int pmem_probe(struct platform_device *pdev) +{ + struct android_pmem_platform_data *pdata; + + if (!pdev || !pdev->dev.platform_data) { + printk(KERN_ALERT "Unable to probe pmem!\n"); + return -1; + } + pdata = pdev->dev.platform_data; + return pmem_setup(pdata, NULL, NULL); +} + + +static int pmem_remove(struct platform_device *pdev) +{ + int id = pdev->id; + __free_page(pfn_to_page(pmem[id].garbage_pfn)); + misc_deregister(&pmem[id].dev); + return 0; +} + +static struct platform_driver pmem_driver = { + .probe = pmem_probe, + .remove = pmem_remove, + .driver = { .name = "android_pmem" } +}; + + +static int __init pmem_init(void) +{ + return platform_driver_register(&pmem_driver); +} + +static void __exit pmem_exit(void) +{ + platform_driver_unregister(&pmem_driver); +} + +module_init(pmem_init); +module_exit(pmem_exit); + diff --git a/drivers/misc/uid_stat.c b/drivers/misc/uid_stat.c new file mode 100644 index 000000000000..43a548bab7ac --- /dev/null +++ b/drivers/misc/uid_stat.c @@ -0,0 +1,153 @@ +/* drivers/misc/uid_stat.c + * + * Copyright (C) 2008 - 2009 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(uid_lock); +static LIST_HEAD(uid_list); +static struct proc_dir_entry *parent; + +struct uid_stat { + struct list_head link; + uid_t uid; + atomic_t tcp_rcv; + atomic_t tcp_snd; +}; + +static struct uid_stat *find_uid_stat(uid_t uid) { + unsigned long flags; + struct uid_stat *entry; + + spin_lock_irqsave(&uid_lock, flags); + list_for_each_entry(entry, &uid_list, link) { + if (entry->uid == uid) { + spin_unlock_irqrestore(&uid_lock, flags); + return entry; + } + } + spin_unlock_irqrestore(&uid_lock, flags); + return NULL; +} + +static int tcp_snd_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + int len; + unsigned int bytes; + char *p = page; + struct uid_stat *uid_entry = (struct uid_stat *) data; + if (!data) + return 0; + + bytes = (unsigned int) (atomic_read(&uid_entry->tcp_snd) + INT_MIN); + p += sprintf(p, "%u\n", bytes); + len = (p - page) - off; + *eof = (len <= count) ? 1 : 0; + *start = page + off; + return len; +} + +static int tcp_rcv_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + int len; + unsigned int bytes; + char *p = page; + struct uid_stat *uid_entry = (struct uid_stat *) data; + if (!data) + return 0; + + bytes = (unsigned int) (atomic_read(&uid_entry->tcp_rcv) + INT_MIN); + p += sprintf(p, "%u\n", bytes); + len = (p - page) - off; + *eof = (len <= count) ? 1 : 0; + *start = page + off; + return len; +} + +/* Create a new entry for tracking the specified uid. */ +static struct uid_stat *create_stat(uid_t uid) { + unsigned long flags; + char uid_s[32]; + struct uid_stat *new_uid; + struct proc_dir_entry *entry; + + /* Create the uid stat struct and append it to the list. */ + if ((new_uid = kmalloc(sizeof(struct uid_stat), GFP_KERNEL)) == NULL) + return NULL; + + new_uid->uid = uid; + /* Counters start at INT_MIN, so we can track 4GB of network traffic. */ + atomic_set(&new_uid->tcp_rcv, INT_MIN); + atomic_set(&new_uid->tcp_snd, INT_MIN); + + spin_lock_irqsave(&uid_lock, flags); + list_add_tail(&new_uid->link, &uid_list); + spin_unlock_irqrestore(&uid_lock, flags); + + sprintf(uid_s, "%d", uid); + entry = proc_mkdir(uid_s, parent); + + /* Keep reference to uid_stat so we know what uid to read stats from. */ + create_proc_read_entry("tcp_snd", S_IRUGO, entry , tcp_snd_read_proc, + (void *) new_uid); + + create_proc_read_entry("tcp_rcv", S_IRUGO, entry, tcp_rcv_read_proc, + (void *) new_uid); + + return new_uid; +} + +int update_tcp_snd(uid_t uid, int size) { + struct uid_stat *entry; + if ((entry = find_uid_stat(uid)) == NULL && + ((entry = create_stat(uid)) == NULL)) { + return -1; + } + atomic_add(size, &entry->tcp_snd); + return 0; +} + +int update_tcp_rcv(uid_t uid, int size) { + struct uid_stat *entry; + if ((entry = find_uid_stat(uid)) == NULL && + ((entry = create_stat(uid)) == NULL)) { + return -1; + } + atomic_add(size, &entry->tcp_rcv); + return 0; +} + +static int __init uid_stat_init(void) +{ + parent = proc_mkdir("uid_stat", NULL); + if (!parent) { + pr_err("uid_stat: failed to create proc entry\n"); + return -1; + } + return 0; +} + +__initcall(uid_stat_init); diff --git a/drivers/mtd/nand/gpmi-nfc/Makefile b/drivers/mtd/nand/gpmi-nfc/Makefile new file mode 100644 index 000000000000..9df1b6454e90 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/Makefile @@ -0,0 +1,11 @@ +obj-$(CONFIG_MTD_NAND_GPMI_NFC) += gpmi-nfc.o +gpmi-nfc-objs += gpmi-nfc-main.o +gpmi-nfc-objs += gpmi-nfc-event-reporting.o +gpmi-nfc-objs += gpmi-nfc-hal-common.o +gpmi-nfc-objs += gpmi-nfc-hal-v0.o +gpmi-nfc-objs += gpmi-nfc-hal-v1.o +gpmi-nfc-objs += gpmi-nfc-hal-v2.o +gpmi-nfc-objs += gpmi-nfc-rom-common.o +gpmi-nfc-objs += gpmi-nfc-rom-v0.o +gpmi-nfc-objs += gpmi-nfc-rom-v1.o +gpmi-nfc-objs += gpmi-nfc-mil.o diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h new file mode 100644 index 000000000000..9af4feb29021 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h @@ -0,0 +1,550 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __GPMI_NFC_BCH_REGS_H +#define __GPMI_NFC_BCH_REGS_H + +/*============================================================================*/ + +#define HW_BCH_CTRL (0x00000000) +#define HW_BCH_CTRL_SET (0x00000004) +#define HW_BCH_CTRL_CLR (0x00000008) +#define HW_BCH_CTRL_TOG (0x0000000c) + +#define BM_BCH_CTRL_SFTRST 0x80000000 +#define BV_BCH_CTRL_SFTRST__RUN 0x0 +#define BV_BCH_CTRL_SFTRST__RESET 0x1 +#define BM_BCH_CTRL_CLKGATE 0x40000000 +#define BV_BCH_CTRL_CLKGATE__RUN 0x0 +#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1 +#define BP_BCH_CTRL_RSVD5 23 +#define BM_BCH_CTRL_RSVD5 0x3F800000 +#define BF_BCH_CTRL_RSVD5(v) (((v) << 23) & BM_BCH_CTRL_RSVD5) +#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000 +#define BP_BCH_CTRL_RSVD4 20 +#define BM_BCH_CTRL_RSVD4 0x00300000 +#define BF_BCH_CTRL_RSVD4(v) (((v) << 20) & BM_BCH_CTRL_RSVD4) +#define BP_BCH_CTRL_M2M_LAYOUT 18 +#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000 +#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT) +#define BM_BCH_CTRL_M2M_ENCODE 0x00020000 +#define BM_BCH_CTRL_M2M_ENABLE 0x00010000 +#define BP_BCH_CTRL_RSVD3 11 +#define BM_BCH_CTRL_RSVD3 0x0000F800 +#define BF_BCH_CTRL_RSVD3(v) (((v) << 11) & BM_BCH_CTRL_RSVD3) +#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400 +#define BM_BCH_CTRL_RSVD2 0x00000200 +#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 +#define BP_BCH_CTRL_RSVD1 4 +#define BM_BCH_CTRL_RSVD1 0x000000F0 +#define BF_BCH_CTRL_RSVD1(v) (((v) << 4) & BM_BCH_CTRL_RSVD1) +#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008 +#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004 +#define BM_BCH_CTRL_RSVD0 0x00000002 +#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 + +/*============================================================================*/ + +#define HW_BCH_STATUS0 (0x00000010) + +#define BP_BCH_STATUS0_HANDLE 20 +#define BM_BCH_STATUS0_HANDLE 0xFFF00000 +#define BF_BCH_STATUS0_HANDLE(v) \ + (((v) << 20) & BM_BCH_STATUS0_HANDLE) +#define BP_BCH_STATUS0_COMPLETED_CE 16 +#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 +#define BF_BCH_STATUS0_COMPLETED_CE(v) \ + (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE) +#define BP_BCH_STATUS0_STATUS_BLK0 8 +#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 +#define BF_BCH_STATUS0_STATUS_BLK0(v) \ + (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0) +#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04 +#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE +#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF +#define BP_BCH_STATUS0_RSVD1 5 +#define BM_BCH_STATUS0_RSVD1 0x000000E0 +#define BF_BCH_STATUS0_RSVD1(v) \ + (((v) << 5) & BM_BCH_STATUS0_RSVD1) +#define BM_BCH_STATUS0_ALLONES 0x00000010 +#define BM_BCH_STATUS0_CORRECTED 0x00000008 +#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 +#define BP_BCH_STATUS0_RSVD0 0 +#define BM_BCH_STATUS0_RSVD0 0x00000003 +#define BF_BCH_STATUS0_RSVD0(v) \ + (((v) << 0) & BM_BCH_STATUS0_RSVD0) + +/*============================================================================*/ + +#define HW_BCH_MODE (0x00000020) + +#define BP_BCH_MODE_RSVD 8 +#define BM_BCH_MODE_RSVD 0xFFFFFF00 +#define BF_BCH_MODE_RSVD(v) \ + (((v) << 8) & BM_BCH_MODE_RSVD) +#define BP_BCH_MODE_ERASE_THRESHOLD 0 +#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF +#define BF_BCH_MODE_ERASE_THRESHOLD(v) \ + (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD) + +/*============================================================================*/ + +#define HW_BCH_ENCODEPTR (0x00000030) + +#define BP_BCH_ENCODEPTR_ADDR 0 +#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF +#define BF_BCH_ENCODEPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DATAPTR (0x00000040) + +#define BP_BCH_DATAPTR_ADDR 0 +#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_DATAPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_METAPTR (0x00000050) + +#define BP_BCH_METAPTR_ADDR 0 +#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_METAPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_LAYOUTSELECT (0x00000070) + +#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 +#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000 +#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \ + (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT) +#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 +#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000 +#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \ + (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT) +#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 +#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000 +#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \ + (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT) +#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 +#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000 +#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \ + (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT) +#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 +#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000 +#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \ + (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT) +#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 +#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000 +#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \ + (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT) +#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 +#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000 +#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \ + (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT) +#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 +#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000 +#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \ + (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT) +#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 +#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000 +#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \ + (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT) +#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 +#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000 +#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \ + (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT) +#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 +#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00 +#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \ + (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT) +#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 +#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300 +#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \ + (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT) +#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 +#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0 +#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \ + (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT) +#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 +#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030 +#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \ + (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT) +#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 +#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C +#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \ + (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT) +#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 +#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003 +#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \ + (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT) + +/*============================================================================*/ + +#define HW_BCH_FLASH0LAYOUT0 (0x00000080) + +#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE) +#define BP_BCH_FLASH0LAYOUT0_ECC0 12 +#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0) +#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH0LAYOUT1 (0x00000090) + +#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH0LAYOUT1_ECCN 12 +#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN) +#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH1LAYOUT0 (0x000000a0) + +#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE) +#define BP_BCH_FLASH1LAYOUT0_ECC0 12 +#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0) +#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH1LAYOUT1 (0x000000b0) + +#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH1LAYOUT1_ECCN 12 +#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN) +#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH2LAYOUT0 (0x000000c0) + +#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE) +#define BP_BCH_FLASH2LAYOUT0_ECC0 12 +#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0) +#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH2LAYOUT1 (0x000000d0) + +#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH2LAYOUT1_ECCN 12 +#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN) +#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH3LAYOUT0 (0x000000e0) + +#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE) +#define BP_BCH_FLASH3LAYOUT0_ECC0 12 +#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0) +#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH3LAYOUT1 (0x000000f0) + +#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH3LAYOUT1_ECCN 12 +#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN) +#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_DEBUG0 (0x00000100) +#define HW_BCH_DEBUG0_SET (0x00000104) +#define HW_BCH_DEBUG0_CLR (0x00000108) +#define HW_BCH_DEBUG0_TOG (0x0000010c) + +#define BP_BCH_DEBUG0_RSVD1 27 +#define BM_BCH_DEBUG0_RSVD1 0xF8000000 +#define BF_BCH_DEBUG0_RSVD1(v) \ + (((v) << 27) & BM_BCH_DEBUG0_RSVD1) +#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x04000000 +#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x02000000 +#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 +#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000 +#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \ + (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000 +#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000 +#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800 +#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400 +#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 +#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 +#define BP_BCH_DEBUG0_RSVD0 6 +#define BM_BCH_DEBUG0_RSVD0 0x000000C0 +#define BF_BCH_DEBUG0_RSVD0(v) \ + (((v) << 6) & BM_BCH_DEBUG0_RSVD0) +#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 +#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F +#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \ + (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT) + +/*============================================================================*/ + +#define HW_BCH_DBGKESREAD (0x00000110) + +#define BP_BCH_DBGKESREAD_VALUES 0 +#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGKESREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGCSFEREAD (0x00000120) + +#define BP_BCH_DBGCSFEREAD_VALUES 0 +#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGCSFEREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGSYNDGENREAD (0x00000130) + +#define BP_BCH_DBGSYNDGENREAD_VALUES 0 +#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGAHBMREAD (0x00000140) + +#define BP_BCH_DBGAHBMREAD_VALUES 0 +#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGAHBMREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_BLOCKNAME (0x00000150) + +#define BP_BCH_BLOCKNAME_NAME 0 +#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF +#define BF_BCH_BLOCKNAME_NAME(v) (v) + +/*============================================================================*/ + +#define HW_BCH_VERSION (0x00000160) + +#define BP_BCH_VERSION_MAJOR 24 +#define BM_BCH_VERSION_MAJOR 0xFF000000 +#define BF_BCH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_BCH_VERSION_MAJOR) +#define BP_BCH_VERSION_MINOR 16 +#define BM_BCH_VERSION_MINOR 0x00FF0000 +#define BF_BCH_VERSION_MINOR(v) \ + (((v) << 16) & BM_BCH_VERSION_MINOR) +#define BP_BCH_VERSION_STEP 0 +#define BM_BCH_VERSION_STEP 0x0000FFFF +#define BF_BCH_VERSION_STEP(v) \ + (((v) << 0) & BM_BCH_VERSION_STEP) + +/*============================================================================*/ + +#endif diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h new file mode 100644 index 000000000000..692db086de4d --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h @@ -0,0 +1,557 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Xml Revision: 2.5 + * Template revision: 26195 + */ + +#ifndef __GPMI_NFC_BCH_REGS_H +#define __GPMI_NFC_BCH_REGS_H + +/*============================================================================*/ + +#define HW_BCH_CTRL (0x00000000) +#define HW_BCH_CTRL_SET (0x00000004) +#define HW_BCH_CTRL_CLR (0x00000008) +#define HW_BCH_CTRL_TOG (0x0000000c) + +#define BM_BCH_CTRL_SFTRST 0x80000000 +#define BV_BCH_CTRL_SFTRST__RUN 0x0 +#define BV_BCH_CTRL_SFTRST__RESET 0x1 +#define BM_BCH_CTRL_CLKGATE 0x40000000 +#define BV_BCH_CTRL_CLKGATE__RUN 0x0 +#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1 +#define BP_BCH_CTRL_RSVD5 23 +#define BM_BCH_CTRL_RSVD5 0x3F800000 +#define BF_BCH_CTRL_RSVD5(v) \ + (((v) << 23) & BM_BCH_CTRL_RSVD5) +#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000 +#define BP_BCH_CTRL_RSVD4 20 +#define BM_BCH_CTRL_RSVD4 0x00300000 +#define BF_BCH_CTRL_RSVD4(v) \ + (((v) << 20) & BM_BCH_CTRL_RSVD4) +#define BP_BCH_CTRL_M2M_LAYOUT 18 +#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000 +#define BF_BCH_CTRL_M2M_LAYOUT(v) \ + (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT) +#define BM_BCH_CTRL_M2M_ENCODE 0x00020000 +#define BM_BCH_CTRL_M2M_ENABLE 0x00010000 +#define BP_BCH_CTRL_RSVD3 11 +#define BM_BCH_CTRL_RSVD3 0x0000F800 +#define BF_BCH_CTRL_RSVD3(v) \ + (((v) << 11) & BM_BCH_CTRL_RSVD3) +#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400 +#define BM_BCH_CTRL_RSVD2 0x00000200 +#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 +#define BP_BCH_CTRL_RSVD1 4 +#define BM_BCH_CTRL_RSVD1 0x000000F0 +#define BF_BCH_CTRL_RSVD1(v) \ + (((v) << 4) & BM_BCH_CTRL_RSVD1) +#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008 +#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004 +#define BM_BCH_CTRL_RSVD0 0x00000002 +#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 + +/*============================================================================*/ + +#define HW_BCH_STATUS0 (0x00000010) + +#define BP_BCH_STATUS0_HANDLE 20 +#define BM_BCH_STATUS0_HANDLE 0xFFF00000 +#define BF_BCH_STATUS0_HANDLE(v) \ + (((v) << 20) & BM_BCH_STATUS0_HANDLE) +#define BP_BCH_STATUS0_COMPLETED_CE 16 +#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 +#define BF_BCH_STATUS0_COMPLETED_CE(v) \ + (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE) +#define BP_BCH_STATUS0_STATUS_BLK0 8 +#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 +#define BF_BCH_STATUS0_STATUS_BLK0(v) \ + (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0) +#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04 +#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE +#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF +#define BP_BCH_STATUS0_RSVD1 5 +#define BM_BCH_STATUS0_RSVD1 0x000000E0 +#define BF_BCH_STATUS0_RSVD1(v) \ + (((v) << 5) & BM_BCH_STATUS0_RSVD1) +#define BM_BCH_STATUS0_ALLONES 0x00000010 +#define BM_BCH_STATUS0_CORRECTED 0x00000008 +#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 +#define BP_BCH_STATUS0_RSVD0 0 +#define BM_BCH_STATUS0_RSVD0 0x00000003 +#define BF_BCH_STATUS0_RSVD0(v) \ + (((v) << 0) & BM_BCH_STATUS0_RSVD0) + +/*============================================================================*/ + +#define HW_BCH_MODE (0x00000020) + +#define BP_BCH_MODE_RSVD 8 +#define BM_BCH_MODE_RSVD 0xFFFFFF00 +#define BF_BCH_MODE_RSVD(v) \ + (((v) << 8) & BM_BCH_MODE_RSVD) +#define BP_BCH_MODE_ERASE_THRESHOLD 0 +#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF +#define BF_BCH_MODE_ERASE_THRESHOLD(v) \ + (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD) + +/*============================================================================*/ + +#define HW_BCH_ENCODEPTR (0x00000030) + +#define BP_BCH_ENCODEPTR_ADDR 0 +#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF +#define BF_BCH_ENCODEPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DATAPTR (0x00000040) + +#define BP_BCH_DATAPTR_ADDR 0 +#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_DATAPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_METAPTR (0x00000050) + +#define BP_BCH_METAPTR_ADDR 0 +#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_METAPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_LAYOUTSELECT (0x00000070) + +#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 +#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000 +#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \ + (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT) +#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 +#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000 +#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \ + (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT) +#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 +#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000 +#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \ + (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT) +#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 +#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000 +#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \ + (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT) +#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 +#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000 +#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \ + (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT) +#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 +#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000 +#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \ + (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT) +#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 +#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000 +#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \ + (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT) +#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 +#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000 +#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \ + (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT) +#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 +#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000 +#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \ + (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT) +#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 +#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000 +#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \ + (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT) +#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 +#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00 +#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \ + (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT) +#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 +#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300 +#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \ + (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT) +#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 +#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0 +#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \ + (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT) +#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 +#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030 +#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \ + (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT) +#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 +#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C +#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \ + (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT) +#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 +#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003 +#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \ + (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT) + +/*============================================================================*/ + +#define HW_BCH_FLASH0LAYOUT0 (0x00000080) + +#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE) +#define BP_BCH_FLASH0LAYOUT0_ECC0 12 +#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0) +#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH0LAYOUT1 (0x00000090) + +#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH0LAYOUT1_ECCN 12 +#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN) +#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH1LAYOUT0 (0x000000a0) + +#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE) +#define BP_BCH_FLASH1LAYOUT0_ECC0 12 +#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0) +#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH1LAYOUT1 (0x000000b0) + +#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH1LAYOUT1_ECCN 12 +#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN) +#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH2LAYOUT0 (0x000000c0) + +#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE) +#define BP_BCH_FLASH2LAYOUT0_ECC0 12 +#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0) +#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH2LAYOUT1 (0x000000d0) + +#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH2LAYOUT1_ECCN 12 +#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN) +#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH3LAYOUT0 (0x000000e0) + +#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE) +#define BP_BCH_FLASH3LAYOUT0_ECC0 12 +#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0) +#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH3LAYOUT1 (0x000000f0) + +#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH3LAYOUT1_ECCN 12 +#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN) +#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_DEBUG0 (0x00000100) +#define HW_BCH_DEBUG0_SET (0x00000104) +#define HW_BCH_DEBUG0_CLR (0x00000108) +#define HW_BCH_DEBUG0_TOG (0x0000010c) + +#define BP_BCH_DEBUG0_RSVD1 27 +#define BM_BCH_DEBUG0_RSVD1 0xF8000000 +#define BF_BCH_DEBUG0_RSVD1(v) \ + (((v) << 27) & BM_BCH_DEBUG0_RSVD1) +#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x04000000 +#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x02000000 +#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 +#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000 +#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \ + (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000 +#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000 +#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800 +#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400 +#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 +#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 +#define BP_BCH_DEBUG0_RSVD0 6 +#define BM_BCH_DEBUG0_RSVD0 0x000000C0 +#define BF_BCH_DEBUG0_RSVD0(v) \ + (((v) << 6) & BM_BCH_DEBUG0_RSVD0) +#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 +#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F +#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \ + (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT) + +/*============================================================================*/ + +#define HW_BCH_DBGKESREAD (0x00000110) + +#define BP_BCH_DBGKESREAD_VALUES 0 +#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGKESREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGCSFEREAD (0x00000120) + +#define BP_BCH_DBGCSFEREAD_VALUES 0 +#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGCSFEREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGSYNDGENREAD (0x00000130) + +#define BP_BCH_DBGSYNDGENREAD_VALUES 0 +#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGAHBMREAD (0x00000140) + +#define BP_BCH_DBGAHBMREAD_VALUES 0 +#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGAHBMREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_BLOCKNAME (0x00000150) + +#define BP_BCH_BLOCKNAME_NAME 0 +#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF +#define BF_BCH_BLOCKNAME_NAME(v) (v) + +/*============================================================================*/ + +#define HW_BCH_VERSION (0x00000160) + +#define BP_BCH_VERSION_MAJOR 24 +#define BM_BCH_VERSION_MAJOR 0xFF000000 +#define BF_BCH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_BCH_VERSION_MAJOR) +#define BP_BCH_VERSION_MINOR 16 +#define BM_BCH_VERSION_MINOR 0x00FF0000 +#define BF_BCH_VERSION_MINOR(v) \ + (((v) << 16) & BM_BCH_VERSION_MINOR) +#define BP_BCH_VERSION_STEP 0 +#define BM_BCH_VERSION_STEP 0x0000FFFF +#define BF_BCH_VERSION_STEP(v) \ + (((v) << 0) & BM_BCH_VERSION_STEP) + +/*============================================================================*/ + +#endif diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h new file mode 100644 index 000000000000..46c0ceb6ddff --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h @@ -0,0 +1,567 @@ +/* + * Freescale BCH Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.3 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___BCH_H +#define __ARCH_ARM___BCH_H + + +#define HW_BCH_CTRL (0x00000000) +#define HW_BCH_CTRL_SET (0x00000004) +#define HW_BCH_CTRL_CLR (0x00000008) +#define HW_BCH_CTRL_TOG (0x0000000c) + +#define BM_BCH_CTRL_SFTRST 0x80000000 +#define BV_BCH_CTRL_SFTRST__RUN 0x0 +#define BV_BCH_CTRL_SFTRST__RESET 0x1 +#define BM_BCH_CTRL_CLKGATE 0x40000000 +#define BV_BCH_CTRL_CLKGATE__RUN 0x0 +#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1 +#define BP_BCH_CTRL_RSVD5 23 +#define BM_BCH_CTRL_RSVD5 0x3F800000 +#define BF_BCH_CTRL_RSVD5(v) \ + (((v) << 23) & BM_BCH_CTRL_RSVD5) +#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000 +#define BP_BCH_CTRL_RSVD4 20 +#define BM_BCH_CTRL_RSVD4 0x00300000 +#define BF_BCH_CTRL_RSVD4(v) \ + (((v) << 20) & BM_BCH_CTRL_RSVD4) +#define BP_BCH_CTRL_M2M_LAYOUT 18 +#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000 +#define BF_BCH_CTRL_M2M_LAYOUT(v) \ + (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT) +#define BM_BCH_CTRL_M2M_ENCODE 0x00020000 +#define BM_BCH_CTRL_M2M_ENABLE 0x00010000 +#define BP_BCH_CTRL_RSVD3 11 +#define BM_BCH_CTRL_RSVD3 0x0000F800 +#define BF_BCH_CTRL_RSVD3(v) \ + (((v) << 11) & BM_BCH_CTRL_RSVD3) +#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400 +#define BM_BCH_CTRL_RSVD2 0x00000200 +#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 +#define BP_BCH_CTRL_RSVD1 4 +#define BM_BCH_CTRL_RSVD1 0x000000F0 +#define BF_BCH_CTRL_RSVD1(v) \ + (((v) << 4) & BM_BCH_CTRL_RSVD1) +#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008 +#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004 +#define BM_BCH_CTRL_RSVD0 0x00000002 +#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 + +#define HW_BCH_STATUS0 (0x00000010) + +#define BP_BCH_STATUS0_HANDLE 20 +#define BM_BCH_STATUS0_HANDLE 0xFFF00000 +#define BF_BCH_STATUS0_HANDLE(v) \ + (((v) << 20) & BM_BCH_STATUS0_HANDLE) +#define BP_BCH_STATUS0_COMPLETED_CE 16 +#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 +#define BF_BCH_STATUS0_COMPLETED_CE(v) \ + (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE) +#define BP_BCH_STATUS0_STATUS_BLK0 8 +#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 +#define BF_BCH_STATUS0_STATUS_BLK0(v) \ + (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0) +#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04 +#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE +#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF +#define BP_BCH_STATUS0_RSVD1 5 +#define BM_BCH_STATUS0_RSVD1 0x000000E0 +#define BF_BCH_STATUS0_RSVD1(v) \ + (((v) << 5) & BM_BCH_STATUS0_RSVD1) +#define BM_BCH_STATUS0_ALLONES 0x00000010 +#define BM_BCH_STATUS0_CORRECTED 0x00000008 +#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 +#define BP_BCH_STATUS0_RSVD0 0 +#define BM_BCH_STATUS0_RSVD0 0x00000003 +#define BF_BCH_STATUS0_RSVD0(v) \ + (((v) << 0) & BM_BCH_STATUS0_RSVD0) + +#define HW_BCH_MODE (0x00000020) + +#define BP_BCH_MODE_RSVD 8 +#define BM_BCH_MODE_RSVD 0xFFFFFF00 +#define BF_BCH_MODE_RSVD(v) \ + (((v) << 8) & BM_BCH_MODE_RSVD) +#define BP_BCH_MODE_ERASE_THRESHOLD 0 +#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF +#define BF_BCH_MODE_ERASE_THRESHOLD(v) \ + (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD) + +#define HW_BCH_ENCODEPTR (0x00000030) + +#define BP_BCH_ENCODEPTR_ADDR 0 +#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF +#define BF_BCH_ENCODEPTR_ADDR(v) (v) + +#define HW_BCH_DATAPTR (0x00000040) + +#define BP_BCH_DATAPTR_ADDR 0 +#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_DATAPTR_ADDR(v) (v) + +#define HW_BCH_METAPTR (0x00000050) + +#define BP_BCH_METAPTR_ADDR 0 +#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_METAPTR_ADDR(v) (v) + +#define HW_BCH_LAYOUTSELECT (0x00000070) + +#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 +#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000 +#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \ + (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT) +#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 +#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000 +#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \ + (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT) +#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 +#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000 +#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \ + (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT) +#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 +#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000 +#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \ + (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT) +#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 +#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000 +#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \ + (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT) +#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 +#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000 +#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \ + (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT) +#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 +#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000 +#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \ + (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT) +#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 +#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000 +#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \ + (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT) +#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 +#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000 +#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \ + (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT) +#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 +#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000 +#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \ + (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT) +#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 +#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00 +#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \ + (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT) +#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 +#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300 +#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \ + (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT) +#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 +#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0 +#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \ + (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT) +#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 +#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030 +#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \ + (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT) +#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 +#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C +#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \ + (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT) +#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 +#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003 +#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \ + (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT) + +#define HW_BCH_FLASH0LAYOUT0 (0x00000080) + +#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE) +#define BP_BCH_FLASH0LAYOUT0_ECC0 11 +#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F800 +#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \ + (((v) << 11) & BM_BCH_FLASH0LAYOUT0_ECC0) +#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC32 0x10 +#define BM_BCH_FLASH0LAYOUT0_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x000003FF +#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH0LAYOUT1 (0x00000090) + +#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH0LAYOUT1_ECCN 11 +#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F800 +#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \ + (((v) << 11) & BM_BCH_FLASH0LAYOUT1_ECCN) +#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC32 0x10 +#define BM_BCH_FLASH0LAYOUT1_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x000003FF +#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) + +#define HW_BCH_FLASH1LAYOUT0 (0x000000a0) + +#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE) +#define BP_BCH_FLASH1LAYOUT0_ECC0 11 +#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F800 +#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \ + (((v) << 11) & BM_BCH_FLASH1LAYOUT0_ECC0) +#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC32 0x10 +#define BM_BCH_FLASH1LAYOUT0_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x000003FF +#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH1LAYOUT1 (0x000000b0) + +#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH1LAYOUT1_ECCN 11 +#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F800 +#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \ + (((v) << 11) & BM_BCH_FLASH1LAYOUT1_ECCN) +#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC32 0x10 +#define BM_BCH_FLASH1LAYOUT1_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x000003FF +#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE) + +#define HW_BCH_FLASH2LAYOUT0 (0x000000c0) + +#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE) +#define BP_BCH_FLASH2LAYOUT0_ECC0 11 +#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F800 +#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \ + (((v) << 11) & BM_BCH_FLASH2LAYOUT0_ECC0) +#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC32 0x10 +#define BM_BCH_FLASH2LAYOUT0_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x000003FF +#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH2LAYOUT1 (0x000000d0) + +#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH2LAYOUT1_ECCN 11 +#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F800 +#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \ + (((v) << 11) & BM_BCH_FLASH2LAYOUT1_ECCN) +#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC32 0x10 +#define BM_BCH_FLASH2LAYOUT1_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x000003FF +#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE) + +#define HW_BCH_FLASH3LAYOUT0 (0x000000e0) + +#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE) +#define BP_BCH_FLASH3LAYOUT0_ECC0 11 +#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F800 +#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \ + (((v) << 11) & BM_BCH_FLASH3LAYOUT0_ECC0) +#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC32 0x10 +#define BM_BCH_FLASH3LAYOUT0_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x000003FF +#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH3LAYOUT1 (0x000000f0) + +#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH3LAYOUT1_ECCN 11 +#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F800 +#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \ + (((v) << 11) & BM_BCH_FLASH3LAYOUT1_ECCN) +#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC32 0x10 +#define BM_BCH_FLASH3LAYOUT1_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x000003FF +#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE) + +#define HW_BCH_DEBUG0 (0x00000100) +#define HW_BCH_DEBUG0_SET (0x00000104) +#define HW_BCH_DEBUG0_CLR (0x00000108) +#define HW_BCH_DEBUG0_TOG (0x0000010c) + +#define BP_BCH_DEBUG0_RSVD1 25 +#define BM_BCH_DEBUG0_RSVD1 0xFE000000 +#define BF_BCH_DEBUG0_RSVD1(v) \ + (((v) << 25) & BM_BCH_DEBUG0_RSVD1) +#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 +#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000 +#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \ + (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000 +#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000 +#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800 +#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400 +#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 +#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 +#define BP_BCH_DEBUG0_RSVD0 6 +#define BM_BCH_DEBUG0_RSVD0 0x000000C0 +#define BF_BCH_DEBUG0_RSVD0(v) \ + (((v) << 6) & BM_BCH_DEBUG0_RSVD0) +#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 +#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F +#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \ + (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT) + +#define HW_BCH_DBGKESREAD (0x00000110) + +#define BP_BCH_DBGKESREAD_VALUES 0 +#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGKESREAD_VALUES(v) (v) + +#define HW_BCH_DBGCSFEREAD (0x00000120) + +#define BP_BCH_DBGCSFEREAD_VALUES 0 +#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGCSFEREAD_VALUES(v) (v) + +#define HW_BCH_DBGSYNDGENREAD (0x00000130) + +#define BP_BCH_DBGSYNDGENREAD_VALUES 0 +#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v) + +#define HW_BCH_DBGAHBMREAD (0x00000140) + +#define BP_BCH_DBGAHBMREAD_VALUES 0 +#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGAHBMREAD_VALUES(v) (v) + +#define HW_BCH_BLOCKNAME (0x00000150) + +#define BP_BCH_BLOCKNAME_NAME 0 +#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF +#define BF_BCH_BLOCKNAME_NAME(v) (v) + +#define HW_BCH_VERSION (0x00000160) + +#define BP_BCH_VERSION_MAJOR 24 +#define BM_BCH_VERSION_MAJOR 0xFF000000 +#define BF_BCH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_BCH_VERSION_MAJOR) +#define BP_BCH_VERSION_MINOR 16 +#define BM_BCH_VERSION_MINOR 0x00FF0000 +#define BF_BCH_VERSION_MINOR(v) \ + (((v) << 16) & BM_BCH_VERSION_MINOR) +#define BP_BCH_VERSION_STEP 0 +#define BM_BCH_VERSION_STEP 0x0000FFFF +#define BF_BCH_VERSION_STEP(v) \ + (((v) << 0) & BM_BCH_VERSION_STEP) +#endif /* __ARCH_ARM___BCH_H */ diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-event-reporting.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-event-reporting.c new file mode 100644 index 000000000000..45574391b0f0 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-event-reporting.c @@ -0,0 +1,307 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +#if defined(EVENT_REPORTING) + +/* + * This variable and module parameter controls whether the driver reports event + * information by printing to the console. + */ + +static int report_events; +module_param(report_events, int, 0600); + +/** + * struct event - A single record in the event trace. + * + * @time: The time at which the event occurred. + * @nesting: Indicates function call nesting. + * @description: A description of the event. + */ + +struct event { + ktime_t time; + unsigned int nesting; + char *description; +}; + +/** + * The event trace. + * + * @overhead: The delay to take a time stamp and nothing else. + * @nesting: The current nesting level. + * @overflow: Indicates the trace overflowed. + * @next: Index of the next event to write. + * @events: The array of events. + */ + +#define MAX_EVENT_COUNT (200) + +static struct { + ktime_t overhead; + int nesting; + int overflow; + unsigned int next; + struct event events[MAX_EVENT_COUNT]; +} event_trace; + +/** + * gpmi_nfc_reset_event_trace() - Resets the event trace. + */ +void gpmi_nfc_reset_event_trace(void) +{ + event_trace.nesting = 0; + event_trace.overflow = false; + event_trace.next = 0; +} + +/** + * gpmi_nfc_add_event() - Adds an event to the event trace. + * + * @description: A description of the event. + * @delta: A delta to the nesting level for this event [-1, 0, 1]. + */ +void gpmi_nfc_add_event(char *description, int delta) +{ + struct event *event; + + if (!report_events) + return; + + if (event_trace.overflow) + return; + + if (event_trace.next >= MAX_EVENT_COUNT) { + event_trace.overflow = true; + return; + } + + event = event_trace.events + event_trace.next; + + event->time = ktime_get(); + + event->description = description; + + if (!delta) + event->nesting = event_trace.nesting; + else if (delta < 0) { + event->nesting = event_trace.nesting - 1; + event_trace.nesting -= 2; + } else { + event->nesting = event_trace.nesting + 1; + event_trace.nesting += 2; + } + + if (event_trace.nesting < 0) + event_trace.nesting = 0; + + event_trace.next++; + +} + +/** + * gpmi_nfc_start_event_trace() - Starts an event trace. + * + * @description: A description of the first event. + */ +void gpmi_nfc_start_event_trace(char *description) +{ + + ktime_t t0; + ktime_t t1; + + if (!report_events) + return; + + gpmi_nfc_reset_event_trace(); + + t0 = ktime_get(); + t1 = ktime_get(); + + event_trace.overhead = ktime_sub(t1, t0); + + gpmi_nfc_add_event(description, 1); + +} + +/** + * gpmi_nfc_dump_event_trace() - Dumps the event trace. + */ +void gpmi_nfc_dump_event_trace(void) +{ + unsigned int i; + time_t seconds; + long nanoseconds; + char line[100]; + int o; + struct event *first_event; + struct event *last_event; + struct event *matching_event; + struct event *event; + ktime_t delta; + + /* Check if event reporting is turned off. */ + + if (!report_events) + return; + + /* Print important facts about this event trace. */ + + pr_info("\n+----------------\n"); + + pr_info("| Overhead : [%d:%d]\n", event_trace.overhead.tv.sec, + event_trace.overhead.tv.nsec); + + if (!event_trace.next) { + pr_info("| No Events\n"); + return; + } + + first_event = event_trace.events; + last_event = event_trace.events + (event_trace.next - 1); + + delta = ktime_sub(last_event->time, first_event->time); + pr_info("| Elapsed Time: [%d:%d]\n", delta.tv.sec, delta.tv.nsec); + + if (event_trace.overflow) + pr_info("| Overflow!\n"); + + /* Print the events in this history. */ + + for (i = 0, event = event_trace.events; + i < event_trace.next; i++, event++) { + + /* Get the delta between this event and the previous event. */ + + if (!i) { + seconds = 0; + nanoseconds = 0; + } else { + delta = ktime_sub(event[0].time, event[-1].time); + seconds = delta.tv.sec; + nanoseconds = delta.tv.nsec; + } + + /* Print the current event. */ + + o = 0; + + o = snprintf(line, sizeof(line) - o, "| [%ld:% 10ld]%*s %s", + seconds, nanoseconds, + event->nesting, "", + event->description); + /* Check if this is the last event in a nested series. */ + + if (i && (event[0].nesting < event[-1].nesting)) { + + for (matching_event = event - 1;; matching_event--) { + + if (matching_event < event_trace.events) { + matching_event = 0; + break; + } + + if (matching_event->nesting == event->nesting) + break; + + } + + if (matching_event) { + delta = ktime_sub(event->time, + matching_event->time); + o += snprintf(line + o, sizeof(line) - o, + " <%d:%d]", delta.tv.sec, + delta.tv.nsec); + } + + } + + /* Check if this is the first event in a nested series. */ + + if ((i < event_trace.next - 1) && + (event[0].nesting < event[1].nesting)) { + + for (matching_event = event + 1;; matching_event++) { + + if (matching_event >= + (event_trace.events+event_trace.next)) { + matching_event = 0; + break; + } + + if (matching_event->nesting == event->nesting) + break; + + } + + if (matching_event) { + delta = ktime_sub(matching_event->time, + event->time); + o += snprintf(line + o, sizeof(line) - o, + " [%d:%d>", delta.tv.sec, + delta.tv.nsec); + } + + } + + pr_info("%s\n", line); + + } + + pr_info("+----------------\n"); + +} + +/** + * gpmi_nfc_stop_event_trace() - Stops an event trace. + * + * @description: A description of the last event. + */ +void gpmi_nfc_stop_event_trace(char *description) +{ + struct event *event; + + if (!report_events) + return; + + /* + * We want the end of the trace, no matter what happens. If the trace + * has already overflowed, or is about to, just jam this event into the + * last spot. Otherwise, add this event like any other. + */ + + if (event_trace.overflow || (event_trace.next >= MAX_EVENT_COUNT)) { + event = event_trace.events + (MAX_EVENT_COUNT - 1); + event->time = ktime_get(); + event->description = description; + event->nesting = 0; + } else { + gpmi_nfc_add_event(description, -1); + } + + gpmi_nfc_dump_event_trace(); + gpmi_nfc_reset_event_trace(); + +} + +#endif /* EVENT_REPORTING */ diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h new file mode 100644 index 000000000000..2f9fce609a34 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h @@ -0,0 +1,416 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __GPMI_NFC_GPMI_REGS_H +#define __GPMI_NFC_GPMI_REGS_H + +/*============================================================================*/ + +#define HW_GPMI_CTRL0 (0x00000000) +#define HW_GPMI_CTRL0_SET (0x00000004) +#define HW_GPMI_CTRL0_CLR (0x00000008) +#define HW_GPMI_CTRL0_TOG (0x0000000c) + +#define BM_GPMI_CTRL0_SFTRST 0x80000000 +#define BV_GPMI_CTRL0_SFTRST__RUN 0x0 +#define BV_GPMI_CTRL0_SFTRST__RESET 0x1 +#define BM_GPMI_CTRL0_CLKGATE 0x40000000 +#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 +#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_GPMI_CTRL0_RUN 0x20000000 +#define BV_GPMI_CTRL0_RUN__IDLE 0x0 +#define BV_GPMI_CTRL0_RUN__BUSY 0x1 +#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 +#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x08000000 +#define BM_GPMI_CTRL0_UDMA 0x04000000 +#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 +#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 +#define BP_GPMI_CTRL0_COMMAND_MODE 24 +#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 +#define BF_GPMI_CTRL0_COMMAND_MODE(v) \ + (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE) +#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 +#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 +#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 +#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 +#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 +#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 +#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 +#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 +#define BP_GPMI_CTRL0_CS 20 +#define BM_GPMI_CTRL0_CS 0x00300000 +#define BF_GPMI_CTRL0_CS(v) (((v) << 20) & BM_GPMI_CTRL0_CS) +#define BP_GPMI_CTRL0_ADDRESS 17 +#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 +#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & BM_GPMI_CTRL0_ADDRESS) +#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 +#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 +#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 +#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 +#define BP_GPMI_CTRL0_XFER_COUNT 0 +#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_GPMI_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT) + +/*============================================================================*/ + +#define HW_GPMI_COMPARE (0x00000010) + +#define BP_GPMI_COMPARE_MASK 16 +#define BM_GPMI_COMPARE_MASK 0xFFFF0000 +#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & BM_GPMI_COMPARE_MASK) +#define BP_GPMI_COMPARE_REFERENCE 0 +#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF +#define BF_GPMI_COMPARE_REFERENCE(v) \ + (((v) << 0) & BM_GPMI_COMPARE_REFERENCE) + +/*============================================================================*/ + +#define HW_GPMI_ECCCTRL (0x00000020) +#define HW_GPMI_ECCCTRL_SET (0x00000024) +#define HW_GPMI_ECCCTRL_CLR (0x00000028) +#define HW_GPMI_ECCCTRL_TOG (0x0000002c) + +#define BP_GPMI_ECCCTRL_HANDLE 16 +#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000 +#define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE) +#define BM_GPMI_ECCCTRL_RSVD2 0x00008000 +#define BP_GPMI_ECCCTRL_ECC_CMD 13 +#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 +#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD) +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1 +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3 +#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1 +#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 +#define BP_GPMI_ECCCTRL_RSVD1 9 +#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00 +#define BF_GPMI_ECCCTRL_RSVD1(v) (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1) +#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 +#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF +#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \ + (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK) +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF +#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x080 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x040 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x020 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x010 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x008 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x004 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x002 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x001 + +/*============================================================================*/ + +#define HW_GPMI_ECCCOUNT (0x00000030) + +#define BP_GPMI_ECCCOUNT_RSVD2 16 +#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000 +#define BF_GPMI_ECCCOUNT_RSVD2(v) (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2) +#define BP_GPMI_ECCCOUNT_COUNT 0 +#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF +#define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT) + +/*============================================================================*/ + +#define HW_GPMI_PAYLOAD (0x00000040) + +#define BP_GPMI_PAYLOAD_ADDRESS 2 +#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC +#define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) +#define BP_GPMI_PAYLOAD_RSVD0 0 +#define BM_GPMI_PAYLOAD_RSVD0 0x00000003 +#define BF_GPMI_PAYLOAD_RSVD0(v) (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0) + +/*============================================================================*/ + +#define HW_GPMI_AUXILIARY (0x00000050) + +#define BP_GPMI_AUXILIARY_ADDRESS 2 +#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC +#define BF_GPMI_AUXILIARY_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) +#define BP_GPMI_AUXILIARY_RSVD0 0 +#define BM_GPMI_AUXILIARY_RSVD0 0x00000003 +#define BF_GPMI_AUXILIARY_RSVD0(v) (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0) + +/*============================================================================*/ + +#define HW_GPMI_CTRL1 (0x00000060) +#define HW_GPMI_CTRL1_SET (0x00000064) +#define HW_GPMI_CTRL1_CLR (0x00000068) +#define HW_GPMI_CTRL1_TOG (0x0000006c) + +#define BP_GPMI_CTRL1_RSVD2 24 +#define BM_GPMI_CTRL1_RSVD2 0xFF000000 +#define BF_GPMI_CTRL1_RSVD2(v) \ + (((v) << 24) & BM_GPMI_CTRL1_RSVD2) +#define BM_GPMI_CTRL1_CE3_SEL 0x00800000 +#define BM_GPMI_CTRL1_CE2_SEL 0x00400000 +#define BM_GPMI_CTRL1_CE1_SEL 0x00200000 +#define BM_GPMI_CTRL1_CE0_SEL 0x00100000 +#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000 +#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 +#define BP_GPMI_CTRL1_GPMI_MODE 0 +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 +#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 +#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 +#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 +#define BP_GPMI_CTRL1_DLL_ENABLE 17 +#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000 +#define BP_GPMI_CTRL1_HALF_PERIOD 16 +#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000 +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 +#define BF_GPMI_CTRL1_RDN_DELAY(v) \ + (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY) +#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800 +#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 +#define BM_GPMI_CTRL1_BURST_EN 0x00000100 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x00000080 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x00000040 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x00000020 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x00000010 +#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 +#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 +#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 +#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002 +#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 +#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 +#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 + +/*============================================================================*/ + +#define HW_GPMI_TIMING0 (0x00000070) + +#define BP_GPMI_TIMING0_RSVD1 24 +#define BM_GPMI_TIMING0_RSVD1 0xFF000000 +#define BF_GPMI_TIMING0_RSVD1(v) \ + (((v) << 24) & BM_GPMI_TIMING0_RSVD1) +#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 +#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 +#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \ + (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP) +#define BP_GPMI_TIMING0_DATA_HOLD 8 +#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING0_DATA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD) +#define BP_GPMI_TIMING0_DATA_SETUP 0 +#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF +#define BF_GPMI_TIMING0_DATA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP) + +/*============================================================================*/ + +#define HW_GPMI_TIMING1 (0x00000080) + +#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 +#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) +#define BP_GPMI_TIMING1_RSVD1 0 +#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF +#define BF_GPMI_TIMING1_RSVD1(v) \ + (((v) << 0) & BM_GPMI_TIMING1_RSVD1) + +/*============================================================================*/ + +#define HW_GPMI_TIMING2 (0x00000090) + +#define BP_GPMI_TIMING2_UDMA_TRP 24 +#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000 +#define BF_GPMI_TIMING2_UDMA_TRP(v) \ + (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP) +#define BP_GPMI_TIMING2_UDMA_ENV 16 +#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000 +#define BF_GPMI_TIMING2_UDMA_ENV(v) \ + (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV) +#define BP_GPMI_TIMING2_UDMA_HOLD 8 +#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING2_UDMA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD) +#define BP_GPMI_TIMING2_UDMA_SETUP 0 +#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF +#define BF_GPMI_TIMING2_UDMA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP) + +/*============================================================================*/ + +#define HW_GPMI_DATA (0x000000a0) + +#define BP_GPMI_DATA_DATA 0 +#define BM_GPMI_DATA_DATA 0xFFFFFFFF +#define BF_GPMI_DATA_DATA(v) (v) + +/*============================================================================*/ + +#define HW_GPMI_STAT (0x000000b0) + +#define BM_GPMI_STAT_PRESENT 0x80000000 +#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 +#define BP_GPMI_STAT_RSVD1 12 +#define BM_GPMI_STAT_RSVD1 0x7FFFF000 +#define BF_GPMI_STAT_RSVD1(v) \ + (((v) << 12) & BM_GPMI_STAT_RSVD1) +#define BP_GPMI_STAT_RDY_TIMEOUT 8 +#define BM_GPMI_STAT_RDY_TIMEOUT 0x00000F00 +#define BF_GPMI_STAT_RDY_TIMEOUT(v) \ + (((v) << 8) & BM_GPMI_STAT_RDY_TIMEOUT) +#define BM_GPMI_STAT_ATA_IRQ 0x00000080 +#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000040 +#define BM_GPMI_STAT_FIFO_EMPTY 0x00000020 +#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 +#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 +#define BM_GPMI_STAT_FIFO_FULL 0x00000010 +#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 +#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 +#define BM_GPMI_STAT_DEV3_ERROR 0x00000008 +#define BM_GPMI_STAT_DEV2_ERROR 0x00000004 +#define BM_GPMI_STAT_DEV1_ERROR 0x00000002 +#define BM_GPMI_STAT_DEERROR 0x00000001 + +/*============================================================================*/ + +#define HW_GPMI_DEBUG (0x000000c0) + +#define BM_GPMI_DEBUG_READY3 0x80000000 +#define BM_GPMI_DEBUG_READY2 0x40000000 +#define BM_GPMI_DEBUG_READY1 0x20000000 +#define BM_GPMI_DEBUG_READY0 0x10000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x08000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x04000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x02000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x01000000 +#define BM_GPMI_DEBUG_SENSE3 0x00800000 +#define BM_GPMI_DEBUG_SENSE2 0x00400000 +#define BM_GPMI_DEBUG_SENSE1 0x00200000 +#define BM_GPMI_DEBUG_SENSE0 0x00100000 +#define BM_GPMI_DEBUG_DMAREQ3 0x00080000 +#define BM_GPMI_DEBUG_DMAREQ2 0x00040000 +#define BM_GPMI_DEBUG_DMAREQ1 0x00020000 +#define BM_GPMI_DEBUG_DMAREQ0 0x00010000 +#define BP_GPMI_DEBUG_CMD_END 12 +#define BM_GPMI_DEBUG_CMD_END 0x0000F000 +#define BF_GPMI_DEBUG_CMD_END(v) \ + (((v) << 12) & BM_GPMI_DEBUG_CMD_END) +#define BP_GPMI_DEBUG_UDMA_STATE 8 +#define BM_GPMI_DEBUG_UDMA_STATE 0x00000F00 +#define BF_GPMI_DEBUG_UDMA_STATE(v) \ + (((v) << 8) & BM_GPMI_DEBUG_UDMA_STATE) +#define BM_GPMI_DEBUG_BUSY 0x00000080 +#define BV_GPMI_DEBUG_BUSY__DISABLED 0x0 +#define BV_GPMI_DEBUG_BUSY__ENABLED 0x1 +#define BP_GPMI_DEBUG_PIN_STATE 4 +#define BM_GPMI_DEBUG_PIN_STATE 0x00000070 +#define BF_GPMI_DEBUG_PIN_STATE(v) \ + (((v) << 4) & BM_GPMI_DEBUG_PIN_STATE) +#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7 +#define BP_GPMI_DEBUG_MAIN_STATE 0 +#define BM_GPMI_DEBUG_MAIN_STATE 0x0000000F +#define BF_GPMI_DEBUG_MAIN_STATE(v) \ + (((v) << 0) & BM_GPMI_DEBUG_MAIN_STATE) +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xA + +/*============================================================================*/ + +#define HW_GPMI_VERSION (0x000000d0) + +#define BP_GPMI_VERSION_MAJOR 24 +#define BM_GPMI_VERSION_MAJOR 0xFF000000 +#define BF_GPMI_VERSION_MAJOR(v) (((v) << 24) & BM_GPMI_VERSION_MAJOR) +#define BP_GPMI_VERSION_MINOR 16 +#define BM_GPMI_VERSION_MINOR 0x00FF0000 +#define BF_GPMI_VERSION_MINOR(v) (((v) << 16) & BM_GPMI_VERSION_MINOR) +#define BP_GPMI_VERSION_STEP 0 +#define BM_GPMI_VERSION_STEP 0x0000FFFF +#define BF_GPMI_VERSION_STEP(v) (((v) << 0) & BM_GPMI_VERSION_STEP) + +/*============================================================================*/ + +#define HW_GPMI_DEBUG2 (0x000000e0) + +#define BP_GPMI_DEBUG2_RSVD1 16 +#define BM_GPMI_DEBUG2_RSVD1 0xFFFF0000 +#define BF_GPMI_DEBUG2_RSVD1(v) (((v) << 16) & BM_GPMI_DEBUG2_RSVD1) +#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 +#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000 +#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \ + (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE) +#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800 +#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400 +#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200 +#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100 +#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080 +#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040 +#define BP_GPMI_DEBUG2_RDN_TAP 0 +#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F +#define BF_GPMI_DEBUG2_RDN_TAP(v) (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP) + +/*============================================================================*/ + +#define HW_GPMI_DEBUG3 (0x000000f0) + +#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 +#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000 +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \ + (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 +#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF +#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \ + (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR) + +/*============================================================================*/ +#endif diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h new file mode 100644 index 000000000000..dcb3b7d3fc88 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h @@ -0,0 +1,421 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Xml Revision: 2.2 + * Template revision: 26195 + */ + +#ifndef __GPMI_NFC_GPMI_REGS_H +#define __GPMI_NFC_GPMI_REGS_H + +/*============================================================================*/ + +#define HW_GPMI_CTRL0 (0x00000000) +#define HW_GPMI_CTRL0_SET (0x00000004) +#define HW_GPMI_CTRL0_CLR (0x00000008) +#define HW_GPMI_CTRL0_TOG (0x0000000c) + +#define BM_GPMI_CTRL0_SFTRST 0x80000000 +#define BV_GPMI_CTRL0_SFTRST__RUN 0x0 +#define BV_GPMI_CTRL0_SFTRST__RESET 0x1 +#define BM_GPMI_CTRL0_CLKGATE 0x40000000 +#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 +#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_GPMI_CTRL0_RUN 0x20000000 +#define BV_GPMI_CTRL0_RUN__IDLE 0x0 +#define BV_GPMI_CTRL0_RUN__BUSY 0x1 +#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 +#define BM_GPMI_CTRL0_LOCK_CS 0x08000000 +#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 +#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 +#define BM_GPMI_CTRL0_UDMA 0x04000000 +#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 +#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 +#define BP_GPMI_CTRL0_COMMAND_MODE 24 +#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 +#define BF_GPMI_CTRL0_COMMAND_MODE(v) \ + (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE) +#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 +#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 +#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 +#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 +#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 +#define BP_GPMI_CTRL0_CS 20 +#define BM_GPMI_CTRL0_CS 0x00700000 +#define BF_GPMI_CTRL0_CS(v) \ + (((v) << 20) & BM_GPMI_CTRL0_CS) +#define BP_GPMI_CTRL0_ADDRESS 17 +#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 +#define BF_GPMI_CTRL0_ADDRESS(v) \ + (((v) << 17) & BM_GPMI_CTRL0_ADDRESS) +#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 +#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 +#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 +#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 +#define BP_GPMI_CTRL0_XFER_COUNT 0 +#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_GPMI_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT) + +/*============================================================================*/ + +#define HW_GPMI_COMPARE (0x00000010) + +#define BP_GPMI_COMPARE_MASK 16 +#define BM_GPMI_COMPARE_MASK 0xFFFF0000 +#define BF_GPMI_COMPARE_MASK(v) \ + (((v) << 16) & BM_GPMI_COMPARE_MASK) +#define BP_GPMI_COMPARE_REFERENCE 0 +#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF +#define BF_GPMI_COMPARE_REFERENCE(v) \ + (((v) << 0) & BM_GPMI_COMPARE_REFERENCE) + +/*============================================================================*/ + +#define HW_GPMI_ECCCTRL (0x00000020) +#define HW_GPMI_ECCCTRL_SET (0x00000024) +#define HW_GPMI_ECCCTRL_CLR (0x00000028) +#define HW_GPMI_ECCCTRL_TOG (0x0000002c) + +#define BP_GPMI_ECCCTRL_HANDLE 16 +#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000 +#define BF_GPMI_ECCCTRL_HANDLE(v) \ + (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE) +#define BM_GPMI_ECCCTRL_RSVD2 0x00008000 +#define BP_GPMI_ECCCTRL_ECC_CMD 13 +#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 +#define BF_GPMI_ECCCTRL_ECC_CMD(v) \ + (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD) +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE 0x1 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3 +#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 +#define BP_GPMI_ECCCTRL_RSVD1 9 +#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00 +#define BF_GPMI_ECCCTRL_RSVD1(v) \ + (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1) +#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 +#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF +#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \ + (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK) +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF + +/*============================================================================*/ + +#define HW_GPMI_ECCCOUNT (0x00000030) + +#define BP_GPMI_ECCCOUNT_RSVD2 16 +#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000 +#define BF_GPMI_ECCCOUNT_RSVD2(v) \ + (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2) +#define BP_GPMI_ECCCOUNT_COUNT 0 +#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF +#define BF_GPMI_ECCCOUNT_COUNT(v) \ + (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT) + +/*============================================================================*/ + +#define HW_GPMI_PAYLOAD (0x00000040) + +#define BP_GPMI_PAYLOAD_ADDRESS 2 +#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC +#define BF_GPMI_PAYLOAD_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) +#define BP_GPMI_PAYLOAD_RSVD0 0 +#define BM_GPMI_PAYLOAD_RSVD0 0x00000003 +#define BF_GPMI_PAYLOAD_RSVD0(v) \ + (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0) + +/*============================================================================*/ + +#define HW_GPMI_AUXILIARY (0x00000050) + +#define BP_GPMI_AUXILIARY_ADDRESS 2 +#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC +#define BF_GPMI_AUXILIARY_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) +#define BP_GPMI_AUXILIARY_RSVD0 0 +#define BM_GPMI_AUXILIARY_RSVD0 0x00000003 +#define BF_GPMI_AUXILIARY_RSVD0(v) \ + (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0) + +/*============================================================================*/ + +#define HW_GPMI_CTRL1 (0x00000060) +#define HW_GPMI_CTRL1_SET (0x00000064) +#define HW_GPMI_CTRL1_CLR (0x00000068) +#define HW_GPMI_CTRL1_TOG (0x0000006c) + +#define BP_GPMI_CTRL1_RSVD2 25 +#define BM_GPMI_CTRL1_RSVD2 0xFE000000 +#define BF_GPMI_CTRL1_RSVD2(v) \ + (((v) << 25) & BM_GPMI_CTRL1_RSVD2) +#define BM_GPMI_CTRL1_DECOUPLE_CS 0x01000000 +#define BP_GPMI_CTRL1_WRN_DLY_SEL 22 +#define BM_GPMI_CTRL1_WRN_DLY_SEL 0x00C00000 +#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \ + (((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL) +#define BM_GPMI_CTRL1_RSVD1 0x00200000 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN 0x00100000 +#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000 +#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 +#define BP_GPMI_CTRL1_DLL_ENABLE 17 +#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000 +#define BP_GPMI_CTRL1_HALF_PERIOD 16 +#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000 +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 +#define BF_GPMI_CTRL1_RDN_DELAY(v) \ + (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY) +#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800 +#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 +#define BM_GPMI_CTRL1_BURST_EN 0x00000100 +#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST 0x00000080 +#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 4 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 0x00000070 +#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) \ + (((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL) +#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 +#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 +#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 +#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002 +#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 +#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 +#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 + +/*============================================================================*/ + +#define HW_GPMI_TIMING0 (0x00000070) + +#define BP_GPMI_TIMING0_RSVD1 24 +#define BM_GPMI_TIMING0_RSVD1 0xFF000000 +#define BF_GPMI_TIMING0_RSVD1(v) \ + (((v) << 24) & BM_GPMI_TIMING0_RSVD1) +#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 +#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 +#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \ + (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP) +#define BP_GPMI_TIMING0_DATA_HOLD 8 +#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING0_DATA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD) +#define BP_GPMI_TIMING0_DATA_SETUP 0 +#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF +#define BF_GPMI_TIMING0_DATA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP) + +/*============================================================================*/ + +#define HW_GPMI_TIMING1 (0x00000080) + +#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 +#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) +#define BP_GPMI_TIMING1_RSVD1 0 +#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF +#define BF_GPMI_TIMING1_RSVD1(v) \ + (((v) << 0) & BM_GPMI_TIMING1_RSVD1) + +/*============================================================================*/ + +#define HW_GPMI_TIMING2 (0x00000090) + +#define BP_GPMI_TIMING2_UDMA_TRP 24 +#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000 +#define BF_GPMI_TIMING2_UDMA_TRP(v) \ + (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP) +#define BP_GPMI_TIMING2_UDMA_ENV 16 +#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000 +#define BF_GPMI_TIMING2_UDMA_ENV(v) \ + (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV) +#define BP_GPMI_TIMING2_UDMA_HOLD 8 +#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING2_UDMA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD) +#define BP_GPMI_TIMING2_UDMA_SETUP 0 +#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF +#define BF_GPMI_TIMING2_UDMA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP) + +/*============================================================================*/ + +#define HW_GPMI_DATA (0x000000a0) + +#define BP_GPMI_DATA_DATA 0 +#define BM_GPMI_DATA_DATA 0xFFFFFFFF +#define BF_GPMI_DATA_DATA(v) (v) + +#define HW_GPMI_STAT (0x000000b0) + +#define BP_GPMI_STAT_READY_BUSY 24 +#define BM_GPMI_STAT_READY_BUSY 0xFF000000 +#define BF_GPMI_STAT_READY_BUSY(v) \ + (((v) << 24) & BM_GPMI_STAT_READY_BUSY) +#define BP_GPMI_STAT_RDY_TIMEOUT 16 +#define BM_GPMI_STAT_RDY_TIMEOUT 0x00FF0000 +#define BF_GPMI_STAT_RDY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT) +#define BM_GPMI_STAT_DEV7_ERROR 0x00008000 +#define BM_GPMI_STAT_DEV6_ERROR 0x00004000 +#define BM_GPMI_STAT_DEV5_ERROR 0x00002000 +#define BM_GPMI_STAT_DEV4_ERROR 0x00001000 +#define BM_GPMI_STAT_DEV3_ERROR 0x00000800 +#define BM_GPMI_STAT_DEV2_ERROR 0x00000400 +#define BM_GPMI_STAT_DEERROR 0x00000200 +#define BM_GPMI_STAT_DEV0_ERROR 0x00000100 +#define BP_GPMI_STAT_RSVD1 5 +#define BM_GPMI_STAT_RSVD1 0x000000E0 +#define BF_GPMI_STAT_RSVD1(v) \ + (((v) << 5) & BM_GPMI_STAT_RSVD1) +#define BM_GPMI_STAT_ATA_IRQ 0x00000010 +#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000008 +#define BM_GPMI_STAT_FIFO_EMPTY 0x00000004 +#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 +#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 +#define BM_GPMI_STAT_FIFO_FULL 0x00000002 +#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 +#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 +#define BM_GPMI_STAT_PRESENT 0x00000001 +#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 + +/*============================================================================*/ + +#define HW_GPMI_DEBUG (0x000000c0) + +#define BP_GPMI_DEBUG_WAIT_FOR_READY_END 24 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END 0xFF000000 +#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \ + (((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END) +#define BP_GPMI_DEBUG_DMA_SENSE 16 +#define BM_GPMI_DEBUG_DMA_SENSE 0x00FF0000 +#define BF_GPMI_DEBUG_DMA_SENSE(v) \ + (((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE) +#define BP_GPMI_DEBUG_DMAREQ 8 +#define BM_GPMI_DEBUG_DMAREQ 0x0000FF00 +#define BF_GPMI_DEBUG_DMAREQ(v) \ + (((v) << 8) & BM_GPMI_DEBUG_DMAREQ) +#define BP_GPMI_DEBUG_CMD_END 0 +#define BM_GPMI_DEBUG_CMD_END 0x000000FF +#define BF_GPMI_DEBUG_CMD_END(v) \ + (((v) << 0) & BM_GPMI_DEBUG_CMD_END) + +/*============================================================================*/ + +#define HW_GPMI_VERSION (0x000000d0) + +#define BP_GPMI_VERSION_MAJOR 24 +#define BM_GPMI_VERSION_MAJOR 0xFF000000 +#define BF_GPMI_VERSION_MAJOR(v) \ + (((v) << 24) & BM_GPMI_VERSION_MAJOR) +#define BP_GPMI_VERSION_MINOR 16 +#define BM_GPMI_VERSION_MINOR 0x00FF0000 +#define BF_GPMI_VERSION_MINOR(v) \ + (((v) << 16) & BM_GPMI_VERSION_MINOR) +#define BP_GPMI_VERSION_STEP 0 +#define BM_GPMI_VERSION_STEP 0x0000FFFF +#define BF_GPMI_VERSION_STEP(v) \ + (((v) << 0) & BM_GPMI_VERSION_STEP) + +/*============================================================================*/ + +#define HW_GPMI_DEBUG2 (0x000000e0) + +#define BP_GPMI_DEBUG2_RSVD1 28 +#define BM_GPMI_DEBUG2_RSVD1 0xF0000000 +#define BF_GPMI_DEBUG2_RSVD1(v) \ + (((v) << 28) & BM_GPMI_DEBUG2_RSVD1) +#define BP_GPMI_DEBUG2_UDMA_STATE 24 +#define BM_GPMI_DEBUG2_UDMA_STATE 0x0F000000 +#define BF_GPMI_DEBUG2_UDMA_STATE(v) \ + (((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE) +#define BM_GPMI_DEBUG2_BUSY 0x00800000 +#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0 +#define BV_GPMI_DEBUG2_BUSY__ENABLED 0x1 +#define BP_GPMI_DEBUG2_PIN_STATE 20 +#define BM_GPMI_DEBUG2_PIN_STATE 0x00700000 +#define BF_GPMI_DEBUG2_PIN_STATE(v) \ + (((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE) +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR 0x2 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL 0x3 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD 0x6 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE 0x7 +#define BP_GPMI_DEBUG2_MAIN_STATE 16 +#define BM_GPMI_DEBUG2_MAIN_STATE 0x000F0000 +#define BF_GPMI_DEBUG2_MAIN_STATE(v) \ + (((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE) +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP 0x9 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE 0xA +#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 +#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000 +#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \ + (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE) +#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800 +#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400 +#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200 +#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100 +#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080 +#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040 +#define BP_GPMI_DEBUG2_RDN_TAP 0 +#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F +#define BF_GPMI_DEBUG2_RDN_TAP(v) \ + (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP) + +/*============================================================================*/ + +#define HW_GPMI_DEBUG3 (0x000000f0) + +#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 +#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000 +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \ + (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 +#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF +#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \ + (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR) + +/*============================================================================*/ + +#endif diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h new file mode 100644 index 000000000000..3baa9012da69 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h @@ -0,0 +1,511 @@ +/* + * Freescale GPMI Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.19 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___GPMI_H +#define __ARCH_ARM___GPMI_H + + +#define HW_GPMI_CTRL0 (0x00000000) +#define HW_GPMI_CTRL0_SET (0x00000004) +#define HW_GPMI_CTRL0_CLR (0x00000008) +#define HW_GPMI_CTRL0_TOG (0x0000000c) + +#define BM_GPMI_CTRL0_SFTRST 0x80000000 +#define BV_GPMI_CTRL0_SFTRST__RUN 0x0 +#define BV_GPMI_CTRL0_SFTRST__RESET 0x1 +#define BM_GPMI_CTRL0_CLKGATE 0x40000000 +#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 +#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_GPMI_CTRL0_RUN 0x20000000 +#define BV_GPMI_CTRL0_RUN__IDLE 0x0 +#define BV_GPMI_CTRL0_RUN__BUSY 0x1 +#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 +#define BM_GPMI_CTRL0_LOCK_CS 0x08000000 +#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 +#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 +#define BM_GPMI_CTRL0_UDMA 0x04000000 +#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 +#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 +#define BP_GPMI_CTRL0_COMMAND_MODE 24 +#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 +#define BF_GPMI_CTRL0_COMMAND_MODE(v) \ + (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE) +#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 +#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 +#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 +#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 +#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 +#define BP_GPMI_CTRL0_CS 20 +#define BM_GPMI_CTRL0_CS 0x00700000 +#define BF_GPMI_CTRL0_CS(v) \ + (((v) << 20) & BM_GPMI_CTRL0_CS) +#define BP_GPMI_CTRL0_ADDRESS 17 +#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 +#define BF_GPMI_CTRL0_ADDRESS(v) \ + (((v) << 17) & BM_GPMI_CTRL0_ADDRESS) +#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 +#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 +#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 +#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 +#define BP_GPMI_CTRL0_XFER_COUNT 0 +#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_GPMI_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT) + +#define HW_GPMI_COMPARE (0x00000010) + +#define BP_GPMI_COMPARE_MASK 16 +#define BM_GPMI_COMPARE_MASK 0xFFFF0000 +#define BF_GPMI_COMPARE_MASK(v) \ + (((v) << 16) & BM_GPMI_COMPARE_MASK) +#define BP_GPMI_COMPARE_REFERENCE 0 +#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF +#define BF_GPMI_COMPARE_REFERENCE(v) \ + (((v) << 0) & BM_GPMI_COMPARE_REFERENCE) + +#define HW_GPMI_ECCCTRL (0x00000020) +#define HW_GPMI_ECCCTRL_SET (0x00000024) +#define HW_GPMI_ECCCTRL_CLR (0x00000028) +#define HW_GPMI_ECCCTRL_TOG (0x0000002c) + +#define BP_GPMI_ECCCTRL_HANDLE 16 +#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000 +#define BF_GPMI_ECCCTRL_HANDLE(v) \ + (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE) +#define BM_GPMI_ECCCTRL_RSVD2 0x00008000 +#define BP_GPMI_ECCCTRL_ECC_CMD 13 +#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 +#define BF_GPMI_ECCCTRL_ECC_CMD(v) \ + (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD) +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE 0x1 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3 +#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 +#define BP_GPMI_ECCCTRL_RSVD1 9 +#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00 +#define BF_GPMI_ECCCTRL_RSVD1(v) \ + (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1) +#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 +#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF +#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \ + (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK) +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF + +#define HW_GPMI_ECCCOUNT (0x00000030) + +#define BP_GPMI_ECCCOUNT_RSVD2 16 +#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000 +#define BF_GPMI_ECCCOUNT_RSVD2(v) \ + (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2) +#define BP_GPMI_ECCCOUNT_COUNT 0 +#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF +#define BF_GPMI_ECCCOUNT_COUNT(v) \ + (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT) + +#define HW_GPMI_PAYLOAD (0x00000040) + +#define BP_GPMI_PAYLOAD_ADDRESS 2 +#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC +#define BF_GPMI_PAYLOAD_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) +#define BP_GPMI_PAYLOAD_RSVD0 0 +#define BM_GPMI_PAYLOAD_RSVD0 0x00000003 +#define BF_GPMI_PAYLOAD_RSVD0(v) \ + (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0) + +#define HW_GPMI_AUXILIARY (0x00000050) + +#define BP_GPMI_AUXILIARY_ADDRESS 2 +#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC +#define BF_GPMI_AUXILIARY_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) +#define BP_GPMI_AUXILIARY_RSVD0 0 +#define BM_GPMI_AUXILIARY_RSVD0 0x00000003 +#define BF_GPMI_AUXILIARY_RSVD0(v) \ + (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0) + +#define HW_GPMI_CTRL1 (0x00000060) +#define HW_GPMI_CTRL1_SET (0x00000064) +#define HW_GPMI_CTRL1_CLR (0x00000068) +#define HW_GPMI_CTRL1_TOG (0x0000006c) + +#define BM_GPMI_CTRL1_DEV_CLK_STOP 0x80000000 +#define BM_GPMI_CTRL1_SSYNC_CLK_STOP 0x40000000 +#define BM_GPMI_CTRL1_WRITE_CLK_STOP 0x20000000 +#define BM_GPMI_CTRL1_TOGGLE_MODE 0x10000000 +#define BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN 0x08000000 +#define BM_GPMI_CTRL1_UPDATE_CS 0x04000000 +#define BM_GPMI_CTRL1_SSYNCMODE 0x02000000 +#define BV_GPMI_CTRL1_SSYNCMODE__ASYNC 0x0 +#define BV_GPMI_CTRL1_SSYNCMODE__SSYNC 0x1 +#define BM_GPMI_CTRL1_DECOUPLE_CS 0x01000000 +#define BP_GPMI_CTRL1_WRN_DLY_SEL 22 +#define BM_GPMI_CTRL1_WRN_DLY_SEL 0x00C00000 +#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \ + (((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL) +#define BM_GPMI_CTRL1_RSVD1 0x00200000 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN 0x00100000 +#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000 +#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 +#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000 +#define BP_GPMI_CTRL1_HALF_PERIOD 16 +#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000 +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 +#define BF_GPMI_CTRL1_RDN_DELAY(v) \ + (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY) +#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800 +#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 +#define BM_GPMI_CTRL1_BURST_EN 0x00000100 +#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST 0x00000080 +#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 4 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 0x00000070 +#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) \ + (((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL) +#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 +#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 +#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 +#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002 +#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 +#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 +#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 + +#define HW_GPMI_TIMING0 (0x00000070) + +#define BP_GPMI_TIMING0_RSVD1 24 +#define BM_GPMI_TIMING0_RSVD1 0xFF000000 +#define BF_GPMI_TIMING0_RSVD1(v) \ + (((v) << 24) & BM_GPMI_TIMING0_RSVD1) +#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 +#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 +#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \ + (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP) +#define BP_GPMI_TIMING0_DATA_HOLD 8 +#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING0_DATA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD) +#define BP_GPMI_TIMING0_DATA_SETUP 0 +#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF +#define BF_GPMI_TIMING0_DATA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP) + +#define HW_GPMI_TIMING1 (0x00000080) + +#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 +#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) +#define BP_GPMI_TIMING1_RSVD1 0 +#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF +#define BF_GPMI_TIMING1_RSVD1(v) \ + (((v) << 0) & BM_GPMI_TIMING1_RSVD1) + +#define HW_GPMI_TIMING2 (0x00000090) + +#define BP_GPMI_TIMING2_RSVD1 27 +#define BM_GPMI_TIMING2_RSVD1 0xF8000000 +#define BF_GPMI_TIMING2_RSVD1(v) \ + (((v) << 27) & BM_GPMI_TIMING2_RSVD1) +#define BP_GPMI_TIMING2_READ_LATENCY 24 +#define BM_GPMI_TIMING2_READ_LATENCY 0x07000000 +#define BF_GPMI_TIMING2_READ_LATENCY(v) \ + (((v) << 24) & BM_GPMI_TIMING2_READ_LATENCY) +#define BP_GPMI_TIMING2_RSVD0 21 +#define BM_GPMI_TIMING2_RSVD0 0x00E00000 +#define BF_GPMI_TIMING2_RSVD0(v) \ + (((v) << 21) & BM_GPMI_TIMING2_RSVD0) +#define BP_GPMI_TIMING2_CE_DELAY 16 +#define BM_GPMI_TIMING2_CE_DELAY 0x001F0000 +#define BF_GPMI_TIMING2_CE_DELAY(v) \ + (((v) << 16) & BM_GPMI_TIMING2_CE_DELAY) +#define BP_GPMI_TIMING2_PREAMBLE_DELAY 12 +#define BM_GPMI_TIMING2_PREAMBLE_DELAY 0x0000F000 +#define BF_GPMI_TIMING2_PREAMBLE_DELAY(v) \ + (((v) << 12) & BM_GPMI_TIMING2_PREAMBLE_DELAY) +#define BP_GPMI_TIMING2_POSTAMBLE_DELAY 8 +#define BM_GPMI_TIMING2_POSTAMBLE_DELAY 0x00000F00 +#define BF_GPMI_TIMING2_POSTAMBLE_DELAY(v) \ + (((v) << 8) & BM_GPMI_TIMING2_POSTAMBLE_DELAY) +#define BP_GPMI_TIMING2_CMDADD_PAUSE 4 +#define BM_GPMI_TIMING2_CMDADD_PAUSE 0x000000F0 +#define BF_GPMI_TIMING2_CMDADD_PAUSE(v) \ + (((v) << 4) & BM_GPMI_TIMING2_CMDADD_PAUSE) +#define BP_GPMI_TIMING2_DATA_PAUSE 0 +#define BM_GPMI_TIMING2_DATA_PAUSE 0x0000000F +#define BF_GPMI_TIMING2_DATA_PAUSE(v) \ + (((v) << 0) & BM_GPMI_TIMING2_DATA_PAUSE) + +#define HW_GPMI_DATA (0x000000a0) + +#define BP_GPMI_DATA_DATA 0 +#define BM_GPMI_DATA_DATA 0xFFFFFFFF +#define BF_GPMI_DATA_DATA(v) (v) + +#define HW_GPMI_STAT (0x000000b0) + +#define BP_GPMI_STAT_READY_BUSY 24 +#define BM_GPMI_STAT_READY_BUSY 0xFF000000 +#define BF_GPMI_STAT_READY_BUSY(v) \ + (((v) << 24) & BM_GPMI_STAT_READY_BUSY) +#define BP_GPMI_STAT_RDY_TIMEOUT 16 +#define BM_GPMI_STAT_RDY_TIMEOUT 0x00FF0000 +#define BF_GPMI_STAT_RDY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT) +#define BM_GPMI_STAT_DEV7_ERROR 0x00008000 +#define BM_GPMI_STAT_DEV6_ERROR 0x00004000 +#define BM_GPMI_STAT_DEV5_ERROR 0x00002000 +#define BM_GPMI_STAT_DEV4_ERROR 0x00001000 +#define BM_GPMI_STAT_DEV3_ERROR 0x00000800 +#define BM_GPMI_STAT_DEV2_ERROR 0x00000400 +#define BM_GPMI_STAT_DEV1_ERROR 0x00000200 +#define BM_GPMI_STAT_DEV0_ERROR 0x00000100 +#define BP_GPMI_STAT_RSVD1 5 +#define BM_GPMI_STAT_RSVD1 0x000000E0 +#define BF_GPMI_STAT_RSVD1(v) \ + (((v) << 5) & BM_GPMI_STAT_RSVD1) +#define BM_GPMI_STAT_ATA_IRQ 0x00000010 +#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000008 +#define BM_GPMI_STAT_FIFO_EMPTY 0x00000004 +#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 +#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 +#define BM_GPMI_STAT_FIFO_FULL 0x00000002 +#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 +#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 +#define BM_GPMI_STAT_PRESENT 0x00000001 +#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 + +#define HW_GPMI_DEBUG (0x000000c0) + +#define BP_GPMI_DEBUG_WAIT_FOR_READY_END 24 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END 0xFF000000 +#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \ + (((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END) +#define BP_GPMI_DEBUG_DMA_SENSE 16 +#define BM_GPMI_DEBUG_DMA_SENSE 0x00FF0000 +#define BF_GPMI_DEBUG_DMA_SENSE(v) \ + (((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE) +#define BP_GPMI_DEBUG_DMAREQ 8 +#define BM_GPMI_DEBUG_DMAREQ 0x0000FF00 +#define BF_GPMI_DEBUG_DMAREQ(v) \ + (((v) << 8) & BM_GPMI_DEBUG_DMAREQ) +#define BP_GPMI_DEBUG_CMD_END 0 +#define BM_GPMI_DEBUG_CMD_END 0x000000FF +#define BF_GPMI_DEBUG_CMD_END(v) \ + (((v) << 0) & BM_GPMI_DEBUG_CMD_END) + +#define HW_GPMI_VERSION (0x000000d0) + +#define BP_GPMI_VERSION_MAJOR 24 +#define BM_GPMI_VERSION_MAJOR 0xFF000000 +#define BF_GPMI_VERSION_MAJOR(v) \ + (((v) << 24) & BM_GPMI_VERSION_MAJOR) +#define BP_GPMI_VERSION_MINOR 16 +#define BM_GPMI_VERSION_MINOR 0x00FF0000 +#define BF_GPMI_VERSION_MINOR(v) \ + (((v) << 16) & BM_GPMI_VERSION_MINOR) +#define BP_GPMI_VERSION_STEP 0 +#define BM_GPMI_VERSION_STEP 0x0000FFFF +#define BF_GPMI_VERSION_STEP(v) \ + (((v) << 0) & BM_GPMI_VERSION_STEP) + +#define HW_GPMI_DEBUG2 (0x000000e0) + +#define BP_GPMI_DEBUG2_RSVD1 28 +#define BM_GPMI_DEBUG2_RSVD1 0xF0000000 +#define BF_GPMI_DEBUG2_RSVD1(v) \ + (((v) << 28) & BM_GPMI_DEBUG2_RSVD1) +#define BP_GPMI_DEBUG2_UDMA_STATE 24 +#define BM_GPMI_DEBUG2_UDMA_STATE 0x0F000000 +#define BF_GPMI_DEBUG2_UDMA_STATE(v) \ + (((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE) +#define BM_GPMI_DEBUG2_BUSY 0x00800000 +#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0 +#define BV_GPMI_DEBUG2_BUSY__ENABLED 0x1 +#define BP_GPMI_DEBUG2_PIN_STATE 20 +#define BM_GPMI_DEBUG2_PIN_STATE 0x00700000 +#define BF_GPMI_DEBUG2_PIN_STATE(v) \ + (((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE) +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR 0x2 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL 0x3 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD 0x6 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE 0x7 +#define BP_GPMI_DEBUG2_MAIN_STATE 16 +#define BM_GPMI_DEBUG2_MAIN_STATE 0x000F0000 +#define BF_GPMI_DEBUG2_MAIN_STATE(v) \ + (((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE) +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP 0x9 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE 0xA +#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 +#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000 +#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \ + (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE) +#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800 +#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400 +#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200 +#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100 +#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080 +#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040 +#define BP_GPMI_DEBUG2_RDN_TAP 0 +#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F +#define BF_GPMI_DEBUG2_RDN_TAP(v) \ + (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP) + +#define HW_GPMI_DEBUG3 (0x000000f0) + +#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 +#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000 +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \ + (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 +#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF +#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \ + (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR) + +#define HW_GPMI_READ_DDR_DLL_CTRL (0x00000100) + +#define BP_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000 +#define BF_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(v) \ + (((v) << 28) & BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT) +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(v) \ + (((v) << 20) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT) +#define BP_GPMI_READ_DDR_DLL_CTRL_RSVD1 18 +#define BM_GPMI_READ_DDR_DLL_CTRL_RSVD1 0x000C0000 +#define BF_GPMI_READ_DDR_DLL_CTRL_RSVD1(v) \ + (((v) << 18) & BM_GPMI_READ_DDR_DLL_CTRL_RSVD1) +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00 +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) \ + (((v) << 10) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL) +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200 +#define BM_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON 0x00000100 +#define BM_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE 0x00000080 +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078 +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(v) \ + (((v) << 3) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET) +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004 +#define BM_GPMI_READ_DDR_DLL_CTRL_RESET 0x00000002 +#define BM_GPMI_READ_DDR_DLL_CTRL_ENABLE 0x00000001 + +#define HW_GPMI_WRITE_DDR_DLL_CTRL (0x00000110) + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000 +#define BF_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(v) \ + (((v) << 28) & BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT) +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(v) \ + (((v) << 20) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT) +#define BP_GPMI_WRITE_DDR_DLL_CTRL_RSVD1 18 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1 0x000C0000 +#define BF_GPMI_WRITE_DDR_DLL_CTRL_RSVD1(v) \ + (((v) << 18) & BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1) +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00 +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) \ + (((v) << 10) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL) +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON 0x00000100 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE 0x00000080 +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078 +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(v) \ + (((v) << 3) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET) +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_RESET 0x00000002 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_ENABLE 0x00000001 + +#define HW_GPMI_READ_DDR_DLL_STS (0x00000120) + +#define BP_GPMI_READ_DDR_DLL_STS_RSVD1 25 +#define BM_GPMI_READ_DDR_DLL_STS_RSVD1 0xFE000000 +#define BF_GPMI_READ_DDR_DLL_STS_RSVD1(v) \ + (((v) << 25) & BM_GPMI_READ_DDR_DLL_STS_RSVD1) +#define BP_GPMI_READ_DDR_DLL_STS_REF_SEL 17 +#define BM_GPMI_READ_DDR_DLL_STS_REF_SEL 0x01FE0000 +#define BF_GPMI_READ_DDR_DLL_STS_REF_SEL(v) \ + (((v) << 17) & BM_GPMI_READ_DDR_DLL_STS_REF_SEL) +#define BM_GPMI_READ_DDR_DLL_STS_REF_LOCK 0x00010000 +#define BP_GPMI_READ_DDR_DLL_STS_RSVD0 9 +#define BM_GPMI_READ_DDR_DLL_STS_RSVD0 0x0000FE00 +#define BF_GPMI_READ_DDR_DLL_STS_RSVD0(v) \ + (((v) << 9) & BM_GPMI_READ_DDR_DLL_STS_RSVD0) +#define BP_GPMI_READ_DDR_DLL_STS_SLV_SEL 1 +#define BM_GPMI_READ_DDR_DLL_STS_SLV_SEL 0x000001FE +#define BF_GPMI_READ_DDR_DLL_STS_SLV_SEL(v) \ + (((v) << 1) & BM_GPMI_READ_DDR_DLL_STS_SLV_SEL) +#define BM_GPMI_READ_DDR_DLL_STS_SLV_LOCK 0x00000001 + +#define HW_GPMI_WRITE_DDR_DLL_STS (0x00000130) + +#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD1 25 +#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD1 0xFE000000 +#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD1(v) \ + (((v) << 25) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD1) +#define BP_GPMI_WRITE_DDR_DLL_STS_REF_SEL 17 +#define BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL 0x01FE0000 +#define BF_GPMI_WRITE_DDR_DLL_STS_REF_SEL(v) \ + (((v) << 17) & BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL) +#define BM_GPMI_WRITE_DDR_DLL_STS_REF_LOCK 0x00010000 +#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD0 9 +#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD0 0x0000FE00 +#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD0(v) \ + (((v) << 9) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD0) +#define BP_GPMI_WRITE_DDR_DLL_STS_SLV_SEL 1 +#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL 0x000001FE +#define BF_GPMI_WRITE_DDR_DLL_STS_SLV_SEL(v) \ + (((v) << 1) & BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL) +#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK 0x00000001 +#endif /* __ARCH_ARM___GPMI_H */ diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c new file mode 100644 index 000000000000..b38d653a21fd --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c @@ -0,0 +1,1037 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +/** + * gpmi_nfc_bch_isr - BCH interrupt service routine. + * + * @interrupt_number: The interrupt number. + * @cookie: A cookie that contains a pointer to the owning device + * data structure. + */ +irqreturn_t gpmi_nfc_bch_isr(int irq, void *cookie) +{ + struct gpmi_nfc_data *this = cookie; + struct nfc_hal *nfc = this->nfc; + + gpmi_nfc_add_event("> gpmi_nfc_bch_isr", 1); + + /* Clear the interrupt. */ + + nfc->clear_bch(this); + + /* Release the base level. */ + + complete(&(nfc->bch_done)); + + /* Return success. */ + + gpmi_nfc_add_event("< gpmi_nfc_bch_isr", -1); + + return IRQ_HANDLED; + +} + +/** + * gpmi_nfc_dma_isr - DMA interrupt service routine. + * + * @interrupt_number: The interrupt number. + * @cookie: A cookie that contains a pointer to the owning device + * data structure. + */ +irqreturn_t gpmi_nfc_dma_isr(int irq, void *cookie) +{ + struct gpmi_nfc_data *this = cookie; + struct nfc_hal *nfc = this->nfc; + + gpmi_nfc_add_event("> gpmi_nfc_dma_isr", 1); + + /* Acknowledge the DMA channel's interrupt. */ + + mxs_dma_ack_irq(nfc->isr_dma_channel); + + /* Release the base level. */ + + complete(&(nfc->dma_done)); + + /* Return success. */ + + gpmi_nfc_add_event("< gpmi_nfc_dma_isr", -1); + + return IRQ_HANDLED; + +} + +/** + * gpmi_nfc_dma_init() - Initializes DMA. + * + * @this: Per-device data. + */ +int gpmi_nfc_dma_init(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct nfc_hal *nfc = this->nfc; + int i; + int error; + + /* Allocate the DMA descriptors. */ + + for (i = 0; i < NFC_DMA_DESCRIPTOR_COUNT; i++) { + nfc->dma_descriptors[i] = mxs_dma_alloc_desc(); + if (!nfc->dma_descriptors[i]) { + dev_err(dev, "Cannot allocate all DMA descriptors.\n"); + error = -ENOMEM; + goto exit_descriptor_allocation; + } + } + + /* If control arrives here, all is well. */ + + return 0; + + /* Control arrives here when something has gone wrong. */ + +exit_descriptor_allocation: + while (--i >= 0) + mxs_dma_free_desc(this->nfc->dma_descriptors[i]); + + return error; + +} + +/** + * gpmi_nfc_dma_exit() - Shuts down DMA. + * + * @this: Per-device data. + */ +void gpmi_nfc_dma_exit(struct gpmi_nfc_data *this) +{ + struct nfc_hal *nfc = this->nfc; + int i; + + /* Free the DMA descriptors. */ + + for (i = 0; i < NFC_DMA_DESCRIPTOR_COUNT; i++) + mxs_dma_free_desc(nfc->dma_descriptors[i]); + +} + +/** + * gpmi_nfc_set_geometry() - Shared NFC geometry configuration. + * + * In principle, computing the NFC geometry is version-specific. However, at + * this writing all, versions share the same page model, so this code can also + * be shared. + * + * @this: Per-device data. + */ +int gpmi_nfc_set_geometry(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct physical_geometry *physical = &this->physical_geometry; + struct nfc_geometry *geometry = &this->nfc_geometry; + struct boot_rom_helper *rom = this->rom; + unsigned int metadata_size; + unsigned int status_size; + unsigned int chunk_data_size_in_bits; + unsigned int chunk_ecc_size_in_bits; + unsigned int chunk_total_size_in_bits; + unsigned int block_mark_chunk_number; + unsigned int block_mark_chunk_bit_offset; + unsigned int block_mark_bit_offset; + + /* At this writing, we support only BCH. */ + + geometry->ecc_algorithm = "BCH"; + + /* + * We always choose a metadata size of 10. Don't try to make sense of + * it -- this is really only for historical compatibility. + */ + + geometry->metadata_size_in_bytes = 10; + + /* + * At this writing, we always use 512-byte ECC chunks. Later hardware + * will be able to support larger chunks, which will cause this + * decision to move into version-specific code. + */ + + geometry->ecc_chunk_size_in_bytes = 512; + + /* Compute the page size based on the physical geometry. */ + + geometry->page_size_in_bytes = + physical->page_data_size_in_bytes + + physical->page_oob_size_in_bytes ; + + /* + * Compute the total number of ECC chunks in a page. This includes the + * slightly larger chunk at the beginning of the page, which contains + * both data and metadata. + */ + + geometry->ecc_chunk_count = + physical->page_data_size_in_bytes / + /*---------------------------------*/ + geometry->ecc_chunk_size_in_bytes; + + /* + * We use the same ECC strength for all chunks, including the first one. + * At this writing, we base our ECC strength choice entirely on the + * the physical page geometry. In the future, this should be changed to + * pay attention to the detailed device information we gathered earlier. + */ + + geometry->ecc_strength = 0; + + switch (physical->page_data_size_in_bytes) { + case 2048: + geometry->ecc_strength = 8; + break; + case 4096: + switch (physical->page_oob_size_in_bytes) { + case 128: + geometry->ecc_strength = 8; + break; + case 218: + geometry->ecc_strength = 16; + break; + } + break; + } + + /* Check if we were able to figure out the ECC strength. */ + + if (!geometry->ecc_strength) { + dev_err(dev, "Unsupported page geometry: %u:%u\n", + physical->page_data_size_in_bytes, + physical->page_oob_size_in_bytes); + return !0; + } + + /* + * The payload buffer contains the data area of a page. The ECC engine + * only needs what's required to hold the data. + */ + + geometry->payload_size_in_bytes = physical->page_data_size_in_bytes; + + /* + * In principle, computing the auxiliary buffer geometry is NFC + * version-specific. However, at this writing, all versions share the + * same model, so this code can also be shared. + * + * The auxiliary buffer contains the metadata and the ECC status. The + * metadata is padded to the nearest 32-bit boundary. The ECC status + * contains one byte for every ECC chunk, and is also padded to the + * nearest 32-bit boundary. + */ + + metadata_size = (geometry->metadata_size_in_bytes + 0x3) & ~0x3; + status_size = (geometry->ecc_chunk_count + 0x3) & ~0x3; + + geometry->auxiliary_size_in_bytes = metadata_size + status_size; + geometry->auxiliary_status_offset = metadata_size; + + /* Check if we're going to do block mark swapping. */ + + if (!rom->swap_block_mark) + return 0; + + /* + * If control arrives here, we're doing block mark swapping, so we need + * to compute the byte and bit offsets of the physical block mark within + * the ECC-based view of the page data. In principle, this isn't a + * difficult computation -- but it's very important and it's easy to get + * it wrong, so we do it carefully. + * + * Note that this calculation is simpler because we use the same ECC + * strength for all chunks, including the zero'th one, which contains + * the metadata. The calculation would be slightly more complicated + * otherwise. + * + * We start by computing the physical bit offset of the block mark. We + * then subtract the number of metadata and ECC bits appearing before + * the mark to arrive at its bit offset within the data alone. + */ + + /* Compute some important facts about chunk geometry. */ + + chunk_data_size_in_bits = geometry->ecc_chunk_size_in_bytes * 8; + chunk_ecc_size_in_bits = geometry->ecc_strength * 13; + + chunk_total_size_in_bits = + chunk_data_size_in_bits + chunk_ecc_size_in_bits; + + /* Compute the bit offset of the block mark within the physical page. */ + + block_mark_bit_offset = physical->page_data_size_in_bytes * 8; + + /* Subtract the metadata bits. */ + + block_mark_bit_offset -= geometry->metadata_size_in_bytes * 8; + + /* + * Compute the chunk number (starting at zero) in which the block mark + * appears. + */ + + block_mark_chunk_number = + block_mark_bit_offset / chunk_total_size_in_bits; + + /* + * Compute the bit offset of the block mark within its chunk, and + * validate it. + */ + + block_mark_chunk_bit_offset = + block_mark_bit_offset - + (block_mark_chunk_number * chunk_total_size_in_bits); + + if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) { + + /* + * If control arrives here, the block mark actually appears in + * the ECC bits of this chunk. This wont' work. + */ + + dev_err(dev, "Unsupported page geometry " + "(block mark in ECC): %u:%u\n", + physical->page_data_size_in_bytes, + physical->page_oob_size_in_bytes); + return !0; + + } + + /* + * Now that we know the chunk number in which the block mark appears, + * we can subtract all the ECC bits that appear before it. + */ + + block_mark_bit_offset -= + block_mark_chunk_number * chunk_ecc_size_in_bits; + + /* + * We now know the absolute bit offset of the block mark within the + * ECC-based data. We can now compute the byte offset and the bit + * offset within the byte. + */ + + geometry->block_mark_byte_offset = block_mark_bit_offset / 8; + geometry->block_mark_bit_offset = block_mark_bit_offset % 8; + + /* Return success. */ + + return 0; + +} + +/* + * This code is useful for debugging. + */ + +/*#define DUMP_DMA_CONTEXT*/ + +#if (defined DUMP_DMA_CONTEXT) + +int dump_dma_context_flag; + +void dump_dma_context(struct gpmi_nfc_data *this, char *title) +{ + + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + void *q; + uint32_t *p; + unsigned int i; + unsigned int j; + + if (!dump_dma_context_flag) + return; + + pr_info("%s\n", title); + pr_info("======\n"); + pr_info("\n"); + + /*--------------------------------------------------------------------*/ + + pr_info(" Descriptors\n"); + pr_info(" -----------\n"); + { + + for (i = 0; i < NFC_DMA_DESCRIPTOR_COUNT; i++, d++) { + pr_info(" #%u\n", i); + pr_info(" --\n"); + pr_info(" Physical Address: 0x%08x\n" , (*d)->address); + pr_info(" Next : 0x%08lx\n", (*d)->cmd.next); + pr_info(" Command : 0x%08lx\n", (*d)->cmd.cmd.data); + pr_info(" Buffer : 0x%08x\n" , (*d)->cmd.address); + for (j = 0; j < 6; j++) + pr_info(" PIO[%u] : 0x%08lx\n", + j, (*d)->cmd.pio_words[j]); + } + + } + pr_info("\n"); + + /*--------------------------------------------------------------------*/ + + pr_info(" DMA\n"); + pr_info(" ---\n"); + { + void *DMA = IO_ADDRESS(APBH_DMA_PHYS_ADDR); + + p = q = DMA + 0x200; + + for (i = 0; i < 7; i++) { + pr_info(" [0x%03x] 0x%08x\n", q - DMA, *p); + q += 0x10; + p = q; + } + + } + pr_info("\n"); + + /*--------------------------------------------------------------------*/ + + pr_info(" GPMI\n"); + pr_info(" ----\n"); + { + void *GPMI = resources->gpmi_regs; + + p = q = GPMI; + + for (i = 0; i < 33; i++) { + pr_info(" [0x%03x] 0x%08x\n", q - GPMI, *p); + q += 0x10; + p = q; + } + + } + pr_info("\n"); + + /*--------------------------------------------------------------------*/ + + pr_info(" BCH\n"); + pr_info(" ---\n"); + { + void *BCH = resources->bch_regs; + + p = q = BCH; + + for (i = 0; i < 22; i++) { + pr_info(" [0x%03x] 0x%08x\n", q - BCH, *p); + q += 0x10; + p = q; + } + + } + pr_info("\n"); + +} + +#endif + +/** + * gpmi_nfc_dma_go - Run a DMA channel. + * + * @this: Per-device data structure. + * @dma_channel: The DMA channel we're going to use. + */ +int gpmi_nfc_dma_go(struct gpmi_nfc_data *this, int dma_channel) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + unsigned long timeout; + int error; + LIST_HEAD(tmp_desc_list); + + gpmi_nfc_add_event("> gpmi_nfc_dma_go", 1); + + /* Get ready... */ + + nfc->isr_dma_channel = dma_channel; + init_completion(&nfc->dma_done); + mxs_dma_enable_irq(dma_channel, 1); + + /* Go! */ + + #if defined(DUMP_DMA_CONTEXT) + dump_dma_context(this, "BEFORE"); + #endif + + mxs_dma_enable(dma_channel); + + /* Wait for it to finish. */ + + timeout = wait_for_completion_timeout(&nfc->dma_done, + msecs_to_jiffies(1000)); + + #if defined(DUMP_DMA_CONTEXT) + dump_dma_context(this, "AFTER"); + #endif + + error = (!timeout) ? -ETIMEDOUT : 0; + + if (error) { + dev_err(dev, "[%s] Chip: %u, DMA Channel: %d, Error %d\n", + __func__, dma_channel - resources->dma_low_channel, + dma_channel, error); + gpmi_nfc_add_event("...DMA timed out", 0); + } else + gpmi_nfc_add_event("...Finished DMA successfully", 0); + + /* Clear out the descriptors we just ran. */ + + mxs_dma_cooked(dma_channel, &tmp_desc_list); + + /* Shut the DMA channel down. */ + + mxs_dma_reset(dma_channel); + mxs_dma_enable_irq(dma_channel, 0); + mxs_dma_disable(dma_channel); + + /* Return. */ + + gpmi_nfc_add_event("< gpmi_nfc_dma_go", -1); + + return error; + +} + +/** + * ns_to_cycles - Converts time in nanoseconds to cycles. + * + * @ntime: The time, in nanoseconds. + * @period: The cycle period, in nanoseconds. + * @min: The minimum allowable number of cycles. + */ +static unsigned int ns_to_cycles(unsigned int time, + unsigned int period, unsigned int min) +{ + unsigned int k; + + /* + * Compute the minimum number of cycles that entirely contain the + * given time. + */ + + k = (time + period - 1) / period; + + return max(k, min); + +} + +/** + * gpmi_compute_hardware_timing - Apply timing to current hardware conditions. + * + * @this: Per-device data. + * @hardware_timing: A pointer to a hardware timing structure that will receive + * the results of our calculations. + */ +int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this, + struct gpmi_nfc_hardware_timing *hw) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct physical_geometry *physical = &this->physical_geometry; + struct nfc_hal *nfc = this->nfc; + struct gpmi_nfc_timing target = nfc->timing; + bool improved_timing_is_available; + unsigned long clock_frequency_in_hz; + unsigned int clock_period_in_ns; + bool dll_use_half_periods; + unsigned int dll_delay_shift; + unsigned int max_sample_delay_in_ns; + unsigned int address_setup_in_cycles; + unsigned int data_setup_in_ns; + unsigned int data_setup_in_cycles; + unsigned int data_hold_in_cycles; + int ideal_sample_delay_in_ns; + unsigned int sample_delay_factor; + int tEYE; + unsigned int min_prop_delay_in_ns = pdata->min_prop_delay_in_ns; + unsigned int max_prop_delay_in_ns = pdata->max_prop_delay_in_ns; + + /* + * If there are multiple chips, we need to relax the timings to allow + * for signal distortion due to higher capacitance. + */ + + if (physical->chip_count > 2) { + target.data_setup_in_ns += 10; + target.data_hold_in_ns += 10; + target.address_setup_in_ns += 10; + } else if (physical->chip_count > 1) { + target.data_setup_in_ns += 5; + target.data_hold_in_ns += 5; + target.address_setup_in_ns += 5; + } + + /* Check if improved timing information is available. */ + + improved_timing_is_available = + (target.tREA_in_ns >= 0) && + (target.tRLOH_in_ns >= 0) && + (target.tRHOH_in_ns >= 0) ; + + /* Inspect the clock. */ + + clock_frequency_in_hz = nfc->clock_frequency_in_hz; + clock_period_in_ns = 1000000000 / clock_frequency_in_hz; + + /* + * The NFC quantizes setup and hold parameters in terms of clock cycles. + * Here, we quantize the setup and hold timing parameters to the + * next-highest clock period to make sure we apply at least the + * specified times. + * + * For data setup and data hold, the hardware interprets a value of zero + * as the largest possible delay. This is not what's intended by a zero + * in the input parameter, so we impose a minimum of one cycle. + */ + + data_setup_in_cycles = ns_to_cycles(target.data_setup_in_ns, + clock_period_in_ns, 1); + data_hold_in_cycles = ns_to_cycles(target.data_hold_in_ns, + clock_period_in_ns, 1); + address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns, + clock_period_in_ns, 0); + + /* + * The clock's period affects the sample delay in a number of ways: + * + * (1) The NFC HAL tells us the maximum clock period the sample delay + * DLL can tolerate. If the clock period is greater than half that + * maximum, we must configure the DLL to be driven by half periods. + * + * (2) We need to convert from an ideal sample delay, in ns, to a + * "sample delay factor," which the NFC uses. This factor depends on + * whether we're driving the DLL with full or half periods. + * Paraphrasing the reference manual: + * + * AD = SDF x 0.125 x RP + * + * where: + * + * AD is the applied delay, in ns. + * SDF is the sample delay factor, which is dimensionless. + * RP is the reference period, in ns, which is a full clock period + * if the DLL is being driven by full periods, or half that if + * the DLL is being driven by half periods. + * + * Let's re-arrange this in a way that's more useful to us: + * + * 8 + * SDF = AD x ---- + * RP + * + * The reference period is either the clock period or half that, so this + * is: + * + * 8 AD x DDF + * SDF = AD x ----- = -------- + * f x P P + * + * where: + * + * f is 1 or 1/2, depending on how we're driving the DLL. + * P is the clock period. + * DDF is the DLL Delay Factor, a dimensionless value that + * incorporates all the constants in the conversion. + * + * DDF will be either 8 or 16, both of which are powers of two. We can + * reduce the cost of this conversion by using bit shifts instead of + * multiplication or division. Thus: + * + * AD << DDS + * SDF = --------- + * P + * + * or + * + * AD = (SDF >> DDS) x P + * + * where: + * + * DDS is the DLL Delay Shift, the logarithm to base 2 of the DDF. + */ + + if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) { + dll_use_half_periods = true; + dll_delay_shift = 3 + 1; + } else { + dll_use_half_periods = false; + dll_delay_shift = 3; + } + + /* + * Compute the maximum sample delay the NFC allows, under current + * conditions. If the clock is running too slowly, no sample delay is + * possible. + */ + + if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns) + max_sample_delay_in_ns = 0; + else { + + /* + * Compute the delay implied by the largest sample delay factor + * the NFC allows. + */ + + max_sample_delay_in_ns = + (nfc->max_sample_delay_factor * clock_period_in_ns) >> + dll_delay_shift; + + /* + * Check if the implied sample delay larger than the NFC + * actually allows. + */ + + if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns) + max_sample_delay_in_ns = nfc->max_dll_delay_in_ns; + + } + + /* + * Check if improved timing information is available. If not, we have to + * use a less-sophisticated algorithm. + */ + + if (!improved_timing_is_available) { + + /* + * Fold the read setup time required by the NFC into the ideal + * sample delay. + */ + + ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns + + nfc->internal_data_setup_in_ns; + + /* + * The ideal sample delay may be greater than the maximum + * allowed by the NFC. If so, we can trade off sample delay time + * for more data setup time. + * + * In each iteration of the following loop, we add a cycle to + * the data setup time and subtract a corresponding amount from + * the sample delay until we've satisified the constraints or + * can't do any better. + */ + + while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) && + (data_setup_in_cycles < nfc->max_data_setup_cycles)) { + + data_setup_in_cycles++; + ideal_sample_delay_in_ns -= clock_period_in_ns; + + if (ideal_sample_delay_in_ns < 0) + ideal_sample_delay_in_ns = 0; + + } + + /* + * Compute the sample delay factor that corresponds most closely + * to the ideal sample delay. If the result is too large for the + * NFC, use the maximum value. + * + * Notice that we use the ns_to_cycles function to compute the + * sample delay factor. We do this because the form of the + * computation is the same as that for calculating cycles. + */ + + sample_delay_factor = + ns_to_cycles( + ideal_sample_delay_in_ns << dll_delay_shift, + clock_period_in_ns, 0); + + if (sample_delay_factor > nfc->max_sample_delay_factor) + sample_delay_factor = nfc->max_sample_delay_factor; + + /* Skip to the part where we return our results. */ + + goto return_results; + + } + + /* + * If control arrives here, we have more detailed timing information, + * so we can use a better algorithm. + */ + + /* + * Fold the read setup time required by the NFC into the maximum + * propagation delay. + */ + + max_prop_delay_in_ns += nfc->internal_data_setup_in_ns; + + /* + * Earlier, we computed the number of clock cycles required to satisfy + * the data setup time. Now, we need to know the actual nanoseconds. + */ + + data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles; + + /* + * Compute tEYE, the width of the data eye when reading from the NAND + * Flash. The eye width is fundamentally determined by the data setup + * time, perturbed by propagation delays and some characteristics of the + * NAND Flash device. + * + * start of the eye = max_prop_delay + tREA + * end of the eye = min_prop_delay + tRHOH + data_setup + */ + + tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns + + (int)data_setup_in_ns; + + tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns; + + /* + * The eye must be open. If it's not, we can try to open it by + * increasing its main forcer, the data setup time. + * + * In each iteration of the following loop, we increase the data setup + * time by a single clock cycle. We do this until either the eye is + * open or we run into NFC limits. + */ + + while ((tEYE <= 0) && + (data_setup_in_cycles < nfc->max_data_setup_cycles)) { + /* Give a cycle to data setup. */ + data_setup_in_cycles++; + /* Synchronize the data setup time with the cycles. */ + data_setup_in_ns += clock_period_in_ns; + /* Adjust tEYE accordingly. */ + tEYE += clock_period_in_ns; + } + + /* + * When control arrives here, the eye is open. The ideal time to sample + * the data is in the center of the eye: + * + * end of the eye + start of the eye + * --------------------------------- - data_setup + * 2 + * + * After some algebra, this simplifies to the code immediately below. + */ + + ideal_sample_delay_in_ns = + ((int)max_prop_delay_in_ns + + (int)target.tREA_in_ns + + (int)min_prop_delay_in_ns + + (int)target.tRHOH_in_ns - + (int)data_setup_in_ns) >> 1; + + /* + * The following figure illustrates some aspects of a NAND Flash read: + * + * + * __ _____________________________________ + * RDN \_________________/ + * + * <---- tEYE -----> + * /-----------------\ + * Read Data ----------------------------< >--------- + * \-----------------/ + * ^ ^ ^ ^ + * | | | | + * |<--Data Setup -->|<--Delay Time -->| | + * | | | | + * | | | + * | |<-- Quantized Delay Time -->| + * | | | + * + * + * We have some issues we must now address: + * + * (1) The *ideal* sample delay time must not be negative. If it is, we + * jam it to zero. + * + * (2) The *ideal* sample delay time must not be greater than that + * allowed by the NFC. If it is, we can increase the data setup + * time, which will reduce the delay between the end of the data + * setup and the center of the eye. It will also make the eye + * larger, which might help with the next issue... + * + * (3) The *quantized* sample delay time must not fall either before the + * eye opens or after it closes (the latter is the problem + * illustrated in the above figure). + */ + + /* Jam a negative ideal sample delay to zero. */ + + if (ideal_sample_delay_in_ns < 0) + ideal_sample_delay_in_ns = 0; + + /* + * Extend the data setup as needed to reduce the ideal sample delay + * below the maximum permitted by the NFC. + */ + + while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) && + (data_setup_in_cycles < nfc->max_data_setup_cycles)) { + + /* Give a cycle to data setup. */ + data_setup_in_cycles++; + /* Synchronize the data setup time with the cycles. */ + data_setup_in_ns += clock_period_in_ns; + /* Adjust tEYE accordingly. */ + tEYE += clock_period_in_ns; + + /* + * Decrease the ideal sample delay by one half cycle, to keep it + * in the middle of the eye. + */ + ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1); + + /* Jam a negative ideal sample delay to zero. */ + if (ideal_sample_delay_in_ns < 0) + ideal_sample_delay_in_ns = 0; + + } + + /* + * Compute the sample delay factor that corresponds to the ideal sample + * delay. If the result is too large, then use the maximum allowed + * value. + * + * Notice that we use the ns_to_cycles function to compute the sample + * delay factor. We do this because the form of the computation is the + * same as that for calculating cycles. + */ + + sample_delay_factor = + ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift, + clock_period_in_ns, 0); + + if (sample_delay_factor > nfc->max_sample_delay_factor) + sample_delay_factor = nfc->max_sample_delay_factor; + + /* + * These macros conveniently encapsulate a computation we'll use to + * continuously evaluate whether or not the data sample delay is inside + * the eye. + */ + + #define IDEAL_DELAY ((int) ideal_sample_delay_in_ns) + + #define QUANTIZED_DELAY \ + ((int) ((sample_delay_factor * clock_period_in_ns) >> \ + dll_delay_shift)) + + #define DELAY_ERROR (abs(QUANTIZED_DELAY - IDEAL_DELAY)) + + #define SAMPLE_IS_NOT_WITHIN_THE_EYE (DELAY_ERROR > (tEYE >> 1)) + + /* + * While the quantized sample time falls outside the eye, reduce the + * sample delay or extend the data setup to move the sampling point back + * toward the eye. Do not allow the number of data setup cycles to + * exceed the maximum allowed by the NFC. + */ + + while (SAMPLE_IS_NOT_WITHIN_THE_EYE && + (data_setup_in_cycles < nfc->max_data_setup_cycles)) { + + /* + * If control arrives here, the quantized sample delay falls + * outside the eye. Check if it's before the eye opens, or after + * the eye closes. + */ + + if (QUANTIZED_DELAY > IDEAL_DELAY) { + + /* + * If control arrives here, the quantized sample delay + * falls after the eye closes. Decrease the quantized + * delay time and then go back to re-evaluate. + */ + + if (sample_delay_factor != 0) + sample_delay_factor--; + + continue; + + } + + /* + * If control arrives here, the quantized sample delay falls + * before the eye opens. Shift the sample point by increasing + * data setup time. This will also make the eye larger. + */ + + /* Give a cycle to data setup. */ + data_setup_in_cycles++; + /* Synchronize the data setup time with the cycles. */ + data_setup_in_ns += clock_period_in_ns; + /* Adjust tEYE accordingly. */ + tEYE += clock_period_in_ns; + + /* + * Decrease the ideal sample delay by one half cycle, to keep it + * in the middle of the eye. + */ + ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1); + + /* ...and one less period for the delay time. */ + ideal_sample_delay_in_ns -= clock_period_in_ns; + + /* Jam a negative ideal sample delay to zero. */ + if (ideal_sample_delay_in_ns < 0) + ideal_sample_delay_in_ns = 0; + + /* + * We have a new ideal sample delay, so re-compute the quantized + * delay. + */ + + sample_delay_factor = + ns_to_cycles( + ideal_sample_delay_in_ns << dll_delay_shift, + clock_period_in_ns, 0); + + if (sample_delay_factor > nfc->max_sample_delay_factor) + sample_delay_factor = nfc->max_sample_delay_factor; + + } + + /* Control arrives here when we're ready to return our results. */ + +return_results: + + hw->data_setup_in_cycles = data_setup_in_cycles; + hw->data_hold_in_cycles = data_hold_in_cycles; + hw->address_setup_in_cycles = address_setup_in_cycles; + hw->use_half_periods = dll_use_half_periods; + hw->sample_delay_factor = sample_delay_factor; + + /* Return success. */ + + return 0; + +} diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c new file mode 100644 index 000000000000..294bb9409581 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c @@ -0,0 +1,924 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +#include "gpmi-nfc-gpmi-regs-v0.h" +#include "gpmi-nfc-bch-regs-v0.h" + +/** + * init() - Initializes the NFC hardware. + * + * @this: Per-device data. + */ +static int init(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + int error; + + /* Initialize DMA. */ + + error = gpmi_nfc_dma_init(this); + + if (error) + return error; + + /* Enable the clock. It will stay on until the end of set_geometry(). */ + + clk_enable(resources->clock); + + /* Reset the GPMI block. */ + + mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true); + + /* Choose NAND mode. */ + __raw_writel(BM_GPMI_CTRL1_GPMI_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_CLR); + + /* Set the IRQ polarity. */ + __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable write protection. */ + __raw_writel(BM_GPMI_CTRL1_DEV_RESET, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Select BCH ECC. */ + __raw_writel(BM_GPMI_CTRL1_BCH_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable the clock. */ + + clk_disable(resources->clock); + + /* If control arrives here, all is well. */ + + return 0; + +} + +/** + * set_geometry() - Configures the NFC geometry. + * + * @this: Per-device data. + */ +static int set_geometry(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_geometry *nfc = &this->nfc_geometry; + unsigned int block_count; + unsigned int block_size; + unsigned int metadata_size; + unsigned int ecc_strength; + unsigned int page_size; + + /* We make the abstract choices in a common function. */ + + if (gpmi_nfc_set_geometry(this)) + return !0; + + /* Translate the abstract choices into register fields. */ + + block_count = nfc->ecc_chunk_count - 1; + block_size = nfc->ecc_chunk_size_in_bytes; + metadata_size = nfc->metadata_size_in_bytes; + ecc_strength = nfc->ecc_strength >> 1; + page_size = nfc->page_size_in_bytes; + + /* Enable the clock. */ + + clk_enable(resources->clock); + + /* + * Reset the BCH block. Notice that we pass in true for the just_enable + * flag. This is because the soft reset for the version 0 BCH block + * doesn't work. If you try to soft reset the BCH block, it becomes + * unusable until the next hard reset. + */ + + mxs_reset_block(resources->bch_regs, true); + + /* Configure layout 0. */ + + __raw_writel( + BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) | + BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) | + BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) | + BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size) , + resources->bch_regs + HW_BCH_FLASH0LAYOUT0); + + __raw_writel( + BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) | + BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) | + BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) , + resources->bch_regs + HW_BCH_FLASH0LAYOUT1); + + /* Set *all* chip selects to use layout 0. */ + + __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT); + + /* Enable interrupts. */ + + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN, + resources->bch_regs + HW_BCH_CTRL_SET); + + /* Disable the clock. */ + + clk_disable(resources->clock); + + /* Return success. */ + + return 0; + +} + +/** + * set_timing() - Configures the NFC timing. + * + * @this: Per-device data. + * @timing: The timing of interest. + */ +static int set_timing(struct gpmi_nfc_data *this, + const struct gpmi_nfc_timing *timing) +{ + struct nfc_hal *nfc = this->nfc; + + /* Accept the new timing. */ + + nfc->timing = *timing; + + /* Return success. */ + + return 0; + +} + +/** + * get_timing() - Retrieves the NFC hardware timing. + * + * @this: Per-device data. + * @clock_frequency_in_hz: The clock frequency, in Hz, during the current + * I/O transaction. If no I/O transaction is in + * progress, this is the clock frequency during the + * most recent I/O transaction. + * @hardware_timing: The hardware timing configuration in effect during + * the current I/O transaction. If no I/O transaction + * is in progress, this is the hardware timing + * configuration during the most recent I/O + * transaction. + */ +static void get_timing(struct gpmi_nfc_data *this, + unsigned long *clock_frequency_in_hz, + struct gpmi_nfc_hardware_timing *hardware_timing) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + unsigned char *gpmi_regs = resources->gpmi_regs; + uint32_t register_image; + + /* Return the clock frequency. */ + + *clock_frequency_in_hz = nfc->clock_frequency_in_hz; + + /* We'll be reading the hardware, so let's enable the clock. */ + + clk_enable(resources->clock); + + /* Retrieve the hardware timing. */ + + register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0); + + hardware_timing->data_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_SETUP) >> + BP_GPMI_TIMING0_DATA_SETUP; + + hardware_timing->data_hold_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_HOLD) >> + BP_GPMI_TIMING0_DATA_HOLD; + + hardware_timing->address_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >> + BP_GPMI_TIMING0_ADDRESS_SETUP; + + register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1); + + hardware_timing->use_half_periods = + (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >> + BP_GPMI_CTRL1_HALF_PERIOD; + + hardware_timing->sample_delay_factor = + (register_image & BM_GPMI_CTRL1_RDN_DELAY) >> + BP_GPMI_CTRL1_RDN_DELAY; + + /* We're done reading the hardware, so disable the clock. */ + + clk_disable(resources->clock); + +} + +/** + * exit() - Shuts down the NFC hardware. + * + * @this: Per-device data. + */ +static void exit(struct gpmi_nfc_data *this) +{ + gpmi_nfc_dma_exit(this); +} + +/** + * begin() - Begin NFC I/O. + * + * @this: Per-device data. + */ +static void begin(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct gpmi_nfc_hardware_timing hw; + unsigned char *gpmi_regs = resources->gpmi_regs; + unsigned int clock_period_in_ns; + uint32_t register_image; + unsigned int dll_wait_time_in_us; + + /* Enable the clock. */ + + clk_enable(resources->clock); + + /* Get the timing information we need. */ + + nfc->clock_frequency_in_hz = clk_get_rate(resources->clock); + clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz; + + gpmi_nfc_compute_hardware_timing(this, &hw); + + /* Set up all the simple timing parameters. */ + + register_image = + BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) | + BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) | + BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ; + + __raw_writel(register_image, gpmi_regs + HW_GPMI_TIMING0); + + /* + * HEY - PAY ATTENTION! + * + * DLL_ENABLE must be set to zero when setting RDN_DELAY or HALF_PERIOD. + */ + + __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR); + + /* Clear out the DLL control fields. */ + + __raw_writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR); + __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR); + + /* If no sample delay is called for, return immediately. */ + + if (!hw.sample_delay_factor) + return; + + /* Configure the HALF_PERIOD flag. */ + + if (hw.use_half_periods) + __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD, + gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Set the delay factor. */ + + __raw_writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor), + gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Enable the DLL. */ + + __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET); + + /* + * After we enable the GPMI DLL, we have to wait 64 clock cycles before + * we can use the GPMI. + * + * Calculate the amount of time we need to wait, in microseconds. + */ + + dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000; + + if (!dll_wait_time_in_us) + dll_wait_time_in_us = 1; + + /* Wait for the DLL to settle. */ + + udelay(dll_wait_time_in_us); + +} + +/** + * end() - End NFC I/O. + * + * @this: Per-device data. + */ +static void end(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + /* Disable the clock. */ + + clk_disable(resources->clock); + +} + +/** + * clear_bch() - Clears a BCH interrupt. + * + * @this: Per-device data. + */ +static void clear_bch(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, + resources->bch_regs + HW_BCH_CTRL_CLR); + +} + +/** + * is_ready() - Returns the ready/busy status of the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + */ +static int is_ready(struct gpmi_nfc_data *this, unsigned chip) +{ + struct resources *resources = &this->resources; + uint32_t mask; + uint32_t register_image; + + /* Extract and return the status. */ + + mask = BM_GPMI_DEBUG_READY0 << chip; + + register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_DEBUG); + + return !!(register_image & mask); + +} + +/** + * send_command() - Sends a command and associated addresses. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the command bytes. + * @length: The number of bytes in the buffer. + */ +static int send_command(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error; + uint32_t command_mode; + uint32_t address; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that sends out the command. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_CLE; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = DMA_READ; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 3; + (*d)->cmd.cmd.bits.bytes = length; + + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BM_GPMI_CTRL0_ADDRESS_INCREMENT | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Return success. */ + + return error; + +} + +/** + * send_data() - Sends data to the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the data. + * @length: The number of bytes in the buffer. + */ +static int send_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that writes a buffer out. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = DMA_READ; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 4; + (*d)->cmd.cmd.bits.bytes = length; + + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + (*d)->cmd.pio_words[3] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Return success. */ + + return error; + +} + +/** + * read_data() - Receives data from the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that will receive the data. + * @length: The number of bytes to read. + */ +static int read_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that reads the data. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = DMA_WRITE; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 0; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 1; + (*d)->cmd.cmd.bits.bytes = length; + + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* + * A DMA descriptor that waits for the command to end and the chip to + * become ready. + * + * I think we actually should *not* be waiting for the chip to become + * ready because, after all, we don't care. I think the original code + * did that and no one has re-thought it yet. + */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 1; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 4; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + (*d)->cmd.pio_words[3] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Return success. */ + + return error; + +} + +/** + * send_page() - Sends a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int send_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that does an ECC page read. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 6; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + + (*d)->cmd.pio_words[1] = 0; + + (*d)->cmd.pio_words[2] = + BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ; + + (*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Prepare to receive an interrupt from the BCH block. */ + + init_completion(&nfc->bch_done); + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Wait for the interrupt from the BCH block. */ + + wait_for_completion(&nfc->bch_done); + + /* Return success. */ + + return error; + +} + +/** + * read_page() - Reads a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int read_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* Wait for the chip to report ready. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 0; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 1; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 1; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Enable the BCH block and read. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 0; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 6; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = + BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ; + (*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Disable the BCH block */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 0; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 1; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 3; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Deassert the NAND lock and interrupt. */ + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 0; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 0; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Prepare to receive an interrupt from the BCH block. */ + + init_completion(&nfc->bch_done); + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Wait for the interrupt from the BCH block. */ + + wait_for_completion(&nfc->bch_done); + + /* Return success. */ + + return error; + +} + +/* This structure represents the NFC HAL for this version of the hardware. */ + +struct nfc_hal gpmi_nfc_hal_v0 = { + .version = 0, + .description = "4-chip GPMI and BCH", + .max_chip_count = 4, + .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >> + BP_GPMI_TIMING0_DATA_SETUP), + .internal_data_setup_in_ns = 0, + .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >> + BP_GPMI_CTRL1_RDN_DELAY), + .max_dll_clock_period_in_ns = 32, + .max_dll_delay_in_ns = 16, + .init = init, + .set_geometry = set_geometry, + .set_timing = set_timing, + .get_timing = get_timing, + .exit = exit, + .begin = begin, + .end = end, + .clear_bch = clear_bch, + .is_ready = is_ready, + .send_command = send_command, + .send_data = send_data, + .read_data = read_data, + .send_page = send_page, + .read_page = read_page, +}; diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c new file mode 100644 index 000000000000..962efe686853 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c @@ -0,0 +1,866 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +#include "gpmi-nfc-gpmi-regs-v1.h" +#include "gpmi-nfc-bch-regs-v1.h" + +/** + * init() - Initializes the NFC hardware. + * + * @this: Per-device data. + */ +static int init(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + int error; + + /* Initialize DMA. */ + + error = gpmi_nfc_dma_init(this); + + if (error) + return error; + + /* Enable the clock. */ + + clk_enable(resources->clock); + + /* Reset the GPMI block. */ + + mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true); + + /* Choose NAND mode. */ + __raw_writel(BM_GPMI_CTRL1_GPMI_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_CLR); + + /* Set the IRQ polarity. */ + __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable write protection. */ + __raw_writel(BM_GPMI_CTRL1_DEV_RESET, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Select BCH ECC. */ + __raw_writel(BM_GPMI_CTRL1_BCH_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable the clock. */ + + clk_disable(resources->clock); + + /* If control arrives here, all is well. */ + + return 0; + +} + +/** + * set_geometry() - Configures the NFC geometry. + * + * @this: Per-device data. + */ +static int set_geometry(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_geometry *nfc = &this->nfc_geometry; + unsigned int block_count; + unsigned int block_size; + unsigned int metadata_size; + unsigned int ecc_strength; + unsigned int page_size; + + /* We make the abstract choices in a common function. */ + + if (gpmi_nfc_set_geometry(this)) + return !0; + + /* Translate the abstract choices into register fields. */ + + block_count = nfc->ecc_chunk_count - 1; + block_size = nfc->ecc_chunk_size_in_bytes; + metadata_size = nfc->metadata_size_in_bytes; + ecc_strength = nfc->ecc_strength >> 1; + page_size = nfc->page_size_in_bytes; + + /* Enable the clock. */ + + clk_enable(resources->clock); + + /* + * Reset the BCH block. Notice that we pass in true for the just_enable + * flag. This is because the soft reset for the version 0 BCH block + * doesn't work and the version 1 BCH block is similar enough that we + * suspect the same (though this has not been officially tested). If you + * try to soft reset a version 0 BCH block, it becomes unusable until + * the next hard reset. + */ + + mxs_reset_block(resources->bch_regs, true); + + /* Configure layout 0. */ + + __raw_writel( + BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) | + BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) | + BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) | + BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size) , + resources->bch_regs + HW_BCH_FLASH0LAYOUT0); + + __raw_writel( + BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) | + BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) | + BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) , + resources->bch_regs + HW_BCH_FLASH0LAYOUT1); + + /* Set *all* chip selects to use layout 0. */ + + __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT); + + /* Enable interrupts. */ + + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN, + resources->bch_regs + HW_BCH_CTRL_SET); + + /* Disable the clock. */ + + clk_disable(resources->clock); + + /* Return success. */ + + return 0; + +} + +/** + * set_timing() - Configures the NFC timing. + * + * @this: Per-device data. + * @timing: The timing of interest. + */ +static int set_timing(struct gpmi_nfc_data *this, + const struct gpmi_nfc_timing *timing) +{ + struct nfc_hal *nfc = this->nfc; + + /* Accept the new timing. */ + + nfc->timing = *timing; + + /* Return success. */ + + return 0; + +} + +/** + * get_timing() - Retrieves the NFC hardware timing. + * + * @this: Per-device data. + * @clock_frequency_in_hz: The clock frequency, in Hz, during the current + * I/O transaction. If no I/O transaction is in + * progress, this is the clock frequency during the + * most recent I/O transaction. + * @hardware_timing: The hardware timing configuration in effect during + * the current I/O transaction. If no I/O transaction + * is in progress, this is the hardware timing + * configuration during the most recent I/O + * transaction. + */ +static void get_timing(struct gpmi_nfc_data *this, + unsigned long *clock_frequency_in_hz, + struct gpmi_nfc_hardware_timing *hardware_timing) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + unsigned char *gpmi_regs = resources->gpmi_regs; + uint32_t register_image; + + /* Return the clock frequency. */ + + *clock_frequency_in_hz = nfc->clock_frequency_in_hz; + + /* We'll be reading the hardware, so let's enable the clock. */ + + clk_enable(resources->clock); + + /* Retrieve the hardware timing. */ + + register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0); + + hardware_timing->data_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_SETUP) >> + BP_GPMI_TIMING0_DATA_SETUP; + + hardware_timing->data_hold_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_HOLD) >> + BP_GPMI_TIMING0_DATA_HOLD; + + hardware_timing->address_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >> + BP_GPMI_TIMING0_ADDRESS_SETUP; + + register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1); + + hardware_timing->use_half_periods = + (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >> + BP_GPMI_CTRL1_HALF_PERIOD; + + hardware_timing->sample_delay_factor = + (register_image & BM_GPMI_CTRL1_RDN_DELAY) >> + BP_GPMI_CTRL1_RDN_DELAY; + + /* We're done reading the hardware, so disable the clock. */ + + clk_disable(resources->clock); + +} + +/** + * exit() - Shuts down the NFC hardware. + * + * @this: Per-device data. + */ +static void exit(struct gpmi_nfc_data *this) +{ + gpmi_nfc_dma_exit(this); +} + +/** + * begin() - Begin NFC I/O. + * + * @this: Per-device data. + */ +static void begin(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct gpmi_nfc_hardware_timing hw; + + /* Enable the clock. */ + + clk_enable(resources->clock); + + /* Get the timing information we need. */ + + nfc->clock_frequency_in_hz = clk_get_rate(resources->clock); + gpmi_nfc_compute_hardware_timing(this, &hw); + + /* Apply the hardware timing. */ + + /* Coming soon - the clock handling code isn't ready yet. */ + +} + +/** + * end() - End NFC I/O. + * + * @this: Per-device data. + */ +static void end(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + /* Disable the clock. */ + + clk_disable(resources->clock); + +} + +/** + * clear_bch() - Clears a BCH interrupt. + * + * @this: Per-device data. + */ +static void clear_bch(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, + resources->bch_regs + HW_BCH_CTRL_CLR); + +} + +/** + * is_ready() - Returns the ready/busy status of the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + */ +static int is_ready(struct gpmi_nfc_data *this, unsigned chip) +{ + struct resources *resources = &this->resources; + uint32_t mask; + uint32_t register_image; + + /* Extract and return the status. */ + + mask = BF_GPMI_STAT_READY_BUSY(1 << chip); + + register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT); + + return !!(register_image & mask); + +} + +/** + * send_command() - Sends a command and associated addresses. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the command bytes. + * @length: The number of bytes in the buffer. + */ +static int send_command(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error; + uint32_t command_mode; + uint32_t address; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that sends out the command. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_CLE; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = DMA_READ; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 3; + (*d)->cmd.cmd.bits.bytes = length; + + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BM_GPMI_CTRL0_ADDRESS_INCREMENT | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Return success. */ + + return error; + +} + +/** + * send_data() - Sends data to the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the data. + * @length: The number of bytes in the buffer. + */ +static int send_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that writes a buffer out. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = DMA_READ; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 4; + (*d)->cmd.cmd.bits.bytes = length; + + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + (*d)->cmd.pio_words[3] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Return success. */ + + return error; + +} + +/** + * read_data() - Receives data from the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that will receive the data. + * @length: The number of bytes to read. + */ +static int read_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that reads the data. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = DMA_WRITE; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 0; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 1; + (*d)->cmd.cmd.bits.bytes = length; + + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* + * A DMA descriptor that waits for the command to end and the chip to + * become ready. + * + * I think we actually should *not* be waiting for the chip to become + * ready because, after all, we don't care. I think the original code + * did that and no one has re-thought it yet. + */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 1; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 4; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + (*d)->cmd.pio_words[3] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Return success. */ + + return error; + +} + +/** + * send_page() - Sends a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int send_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that does an ECC page read. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 6; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + + (*d)->cmd.pio_words[1] = 0; + + (*d)->cmd.pio_words[2] = + BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ; + + (*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Prepare to receive an interrupt from the BCH block. */ + + init_completion(&nfc->bch_done); + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Wait for the interrupt from the BCH block. */ + + wait_for_completion(&nfc->bch_done); + + /* Return success. */ + + return error; + +} + +/** + * read_page() - Reads a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int read_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* Wait for the chip to report ready. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 0; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 1; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 1; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Enable the BCH block and read. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__DECODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 0; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 6; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = + BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ; + (*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Disable the BCH block */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 0; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 1; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 3; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Deassert the NAND lock and interrupt. */ + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 0; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 0; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Prepare to receive an interrupt from the BCH block. */ + + init_completion(&nfc->bch_done); + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Wait for the interrupt from the BCH block. */ + + wait_for_completion(&nfc->bch_done); + + /* Return success. */ + + return error; + +} + +/* This structure represents the NFC HAL for this version of the hardware. */ + +struct nfc_hal gpmi_nfc_hal_v1 = { + .version = 1, + .description = "8-chip GPMI and BCH", + .max_chip_count = 8, + .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >> + BP_GPMI_TIMING0_DATA_SETUP), + .internal_data_setup_in_ns = 0, + .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >> + BP_GPMI_CTRL1_RDN_DELAY), + .max_dll_clock_period_in_ns = 32, + .max_dll_delay_in_ns = 16, + .init = init, + .set_geometry = set_geometry, + .set_timing = set_timing, + .get_timing = get_timing, + .exit = exit, + .begin = begin, + .end = end, + .clear_bch = clear_bch, + .is_ready = is_ready, + .send_command = send_command, + .send_data = send_data, + .read_data = read_data, + .send_page = send_page, + .read_page = read_page, +}; diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c new file mode 100644 index 000000000000..eee49ae58dea --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c @@ -0,0 +1,839 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +#include "gpmi-nfc-gpmi-regs-v2.h" +#include "gpmi-nfc-bch-regs-v2.h" + +/** + * init() - Initializes the NFC hardware. + * + * @this: Per-device data. + */ +static int init(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + int error; + + /* Initialize DMA. */ + + error = gpmi_nfc_dma_init(this); + + if (error) + return error; + + /* Enable the clock. */ + + clk_enable(resources->clock); + + /* Reset the GPMI block. */ + + mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true); + + /* Choose NAND mode. */ + __raw_writel(BM_GPMI_CTRL1_GPMI_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_CLR); + + /* Set the IRQ polarity. */ + __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable write protection. */ + __raw_writel(BM_GPMI_CTRL1_DEV_RESET, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Select BCH ECC. */ + __raw_writel(BM_GPMI_CTRL1_BCH_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable the clock. */ + + clk_disable(resources->clock); + + /* If control arrives here, all is well. */ + + return 0; + +} + +/** + * set_geometry() - Configures the NFC geometry. + * + * @this: Per-device data. + */ +static int set_geometry(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_geometry *nfc = &this->nfc_geometry; + unsigned int block_count; + unsigned int block_size; + unsigned int metadata_size; + unsigned int ecc_strength; + unsigned int page_size; + + /* We make the abstract choices in a common function. */ + + if (gpmi_nfc_set_geometry(this)) + return !0; + + /* Translate the abstract choices into register fields. */ + + block_count = nfc->ecc_chunk_count - 1; + block_size = nfc->ecc_chunk_size_in_bytes >> 2; + metadata_size = nfc->metadata_size_in_bytes; + ecc_strength = nfc->ecc_strength >> 1; + page_size = nfc->page_size_in_bytes; + + /* Enable the clock. */ + + clk_enable(resources->clock); + + /* + * Reset the BCH block. Notice that we pass in true for the just_enable + * flag. This is because the soft reset for the version 0 BCH block + * doesn't work and the version 1 BCH block is similar enough that we + * suspect the same (though this has not been officially tested). If you + * try to soft reset a version 0 BCH block, it becomes unusable until + * the next hard reset. + */ + + mxs_reset_block(resources->bch_regs, false); + + /* Configure layout 0. */ + + __raw_writel( + BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) | + BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) | + BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) | + BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size) , + resources->bch_regs + HW_BCH_FLASH0LAYOUT0); + + __raw_writel( + BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) | + BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) | + BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) , + resources->bch_regs + HW_BCH_FLASH0LAYOUT1); + + /* Set *all* chip selects to use layout 0. */ + + __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT); + + /* Enable interrupts. */ + + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN, + resources->bch_regs + HW_BCH_CTRL_SET); + + /* Disable the clock. */ + + clk_disable(resources->clock); + + /* Return success. */ + + return 0; + +} + +/** + * set_timing() - Configures the NFC timing. + * + * @this: Per-device data. + * @timing: The timing of interest. + */ +static int set_timing(struct gpmi_nfc_data *this, + const struct gpmi_nfc_timing *timing) +{ + struct nfc_hal *nfc = this->nfc; + + /* Accept the new timing. */ + + nfc->timing = *timing; + + /* Return success. */ + + return 0; + +} + +/** + * get_timing() - Retrieves the NFC hardware timing. + * + * @this: Per-device data. + * @clock_frequency_in_hz: The clock frequency, in Hz, during the current + * I/O transaction. If no I/O transaction is in + * progress, this is the clock frequency during the + * most recent I/O transaction. + * @hardware_timing: The hardware timing configuration in effect during + * the current I/O transaction. If no I/O transaction + * is in progress, this is the hardware timing + * configuration during the most recent I/O + * transaction. + */ +static void get_timing(struct gpmi_nfc_data *this, + unsigned long *clock_frequency_in_hz, + struct gpmi_nfc_hardware_timing *hardware_timing) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + unsigned char *gpmi_regs = resources->gpmi_regs; + uint32_t register_image; + + /* Return the clock frequency. */ + + *clock_frequency_in_hz = nfc->clock_frequency_in_hz; + + /* We'll be reading the hardware, so let's enable the clock. */ + + clk_enable(resources->clock); + + /* Retrieve the hardware timing. */ + + register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0); + + hardware_timing->data_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_SETUP) >> + BP_GPMI_TIMING0_DATA_SETUP; + + hardware_timing->data_hold_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_HOLD) >> + BP_GPMI_TIMING0_DATA_HOLD; + + hardware_timing->address_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >> + BP_GPMI_TIMING0_ADDRESS_SETUP; + + register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1); + + hardware_timing->use_half_periods = + (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >> + BP_GPMI_CTRL1_HALF_PERIOD; + + hardware_timing->sample_delay_factor = + (register_image & BM_GPMI_CTRL1_RDN_DELAY) >> + BP_GPMI_CTRL1_RDN_DELAY; + + /* We're done reading the hardware, so disable the clock. */ + + clk_disable(resources->clock); + +} + +/** + * exit() - Shuts down the NFC hardware. + * + * @this: Per-device data. + */ +static void exit(struct gpmi_nfc_data *this) +{ + gpmi_nfc_dma_exit(this); +} + +/** + * begin() - Begin NFC I/O. + * + * @this: Per-device data. + */ +static void begin(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct gpmi_nfc_hardware_timing hw; + + /* Enable the clock. */ + + clk_enable(resources->clock); + + /* Get the timing information we need. */ + + nfc->clock_frequency_in_hz = clk_get_rate(resources->clock); + gpmi_nfc_compute_hardware_timing(this, &hw); + + /* Apply the hardware timing. */ + + /* Coming soon - the clock handling code isn't ready yet. */ + +} + +/** + * end() - End NFC I/O. + * + * @this: Per-device data. + */ +static void end(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + /* Disable the clock. */ + + clk_disable(resources->clock); + +} + +/** + * clear_bch() - Clears a BCH interrupt. + * + * @this: Per-device data. + */ +static void clear_bch(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, + resources->bch_regs + HW_BCH_CTRL_CLR); + +} + +/** + * is_ready() - Returns the ready/busy status of the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + */ +static int is_ready(struct gpmi_nfc_data *this, unsigned chip) +{ + struct resources *resources = &this->resources; + uint32_t mask; + uint32_t register_image; + + /* Extract and return the status. */ + + mask = BF_GPMI_STAT_READY_BUSY(1 << 0); + + register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT); + + return !!(register_image & mask); + +} + +/** + * send_command() - Sends a command and associated addresses. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the command bytes. + * @length: The number of bytes in the buffer. + */ +static int send_command(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error; + uint32_t command_mode; + uint32_t address; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that sends out the command. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_CLE; + + /* reset the cmd bits fieled */ + (*d)->cmd.cmd.data = 0; + + (*d)->cmd.cmd.bits.command = DMA_READ; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 1; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 3; + (*d)->cmd.cmd.bits.bytes = length; + + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BM_GPMI_CTRL0_ADDRESS_INCREMENT | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Return success. */ + + return error; + +} + +/** + * send_data() - Sends data to the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the data. + * @length: The number of bytes in the buffer. + */ +static int send_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that writes a buffer out. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = DMA_READ; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 4; + (*d)->cmd.cmd.bits.bytes = length; + + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + (*d)->cmd.pio_words[3] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Return success. */ + + return error; + +} + +/** + * read_data() - Receives data from the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that will receive the data. + * @length: The number of bytes to read. + */ +static int read_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that reads the data. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = DMA_WRITE; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 1; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 1; + (*d)->cmd.cmd.bits.bytes = length; + + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + /* Return success. */ + + return error; + +} + +/** + * send_page() - Sends a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int send_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that does an ECC page read. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 6; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + + (*d)->cmd.pio_words[1] = 0; + + (*d)->cmd.pio_words[2] = + BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ; + + (*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Prepare to receive an interrupt from the BCH block. */ + + init_completion(&nfc->bch_done); + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Wait for the interrupt from the BCH block. */ + + error = wait_for_completion_timeout(&nfc->bch_done, + msecs_to_jiffies(1000)); + + error = (!error) ? -ETIMEDOUT : 0; + + if (error) + dev_err(dev, "[%s] bch timeout!!! \n", __func__); + + /* Return success. */ + + return error; + +} + +/** + * read_page() - Reads a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int read_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + int error = 0; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* Wait for the chip to report ready. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 0; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 1; + (*d)->cmd.cmd.bits.dec_sem = 0; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 1; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Enable the BCH block and read. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__DECODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 0; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 0; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 6; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = + BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ; + (*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Disable the BCH block */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 1; + (*d)->cmd.cmd.bits.irq = 0; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 1; + (*d)->cmd.cmd.bits.dec_sem = 0; + (*d)->cmd.cmd.bits.wait4end = 1; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 3; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Deassert the NAND lock and interrupt. */ + + (*d)->cmd.cmd.data = 0; + (*d)->cmd.cmd.bits.command = NO_DMA_XFER; + (*d)->cmd.cmd.bits.chain = 0; + (*d)->cmd.cmd.bits.irq = 1; + (*d)->cmd.cmd.bits.nand_lock = 0; + (*d)->cmd.cmd.bits.nand_wait_4_ready = 0; + (*d)->cmd.cmd.bits.dec_sem = 1; + (*d)->cmd.cmd.bits.wait4end = 0; + (*d)->cmd.cmd.bits.halt_on_terminate = 0; + (*d)->cmd.cmd.bits.terminate_flush = 0; + (*d)->cmd.cmd.bits.pio_words = 0; + (*d)->cmd.cmd.bits.bytes = 0; + + (*d)->cmd.address = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Prepare to receive an interrupt from the BCH block. */ + + init_completion(&nfc->bch_done); + + /* Go! */ + + error = gpmi_nfc_dma_go(this, dma_channel); + + if (error) + dev_err(dev, "[%s] DMA error\n", __func__); + + /* Wait for the interrupt from the BCH block. */ + + error = wait_for_completion_timeout(&nfc->bch_done, + msecs_to_jiffies(1000)); + + error = (!error) ? -ETIMEDOUT : 0; + + if (error) + dev_err(dev, "[%s] bch timeout!!! \n", __func__); + + /* Return success. */ + + return error; + +} + +/* This structure represents the NFC HAL for this version of the hardware. */ + +struct nfc_hal gpmi_nfc_hal_v2 = { + .version = 2, + .description = "8-chip GPMI and BCH", + .max_chip_count = 8, + .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >> + BP_GPMI_TIMING0_DATA_SETUP), + .internal_data_setup_in_ns = 0, + .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >> + BP_GPMI_CTRL1_RDN_DELAY), + .max_dll_clock_period_in_ns = 32, + .max_dll_delay_in_ns = 16, + .init = init, + .set_geometry = set_geometry, + .set_timing = set_timing, + .get_timing = get_timing, + .exit = exit, + .begin = begin, + .end = end, + .clear_bch = clear_bch, + .is_ready = is_ready, + .send_command = send_command, + .send_data = send_data, + .read_data = read_data, + .send_page = send_page, + .read_page = read_page, +}; diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c new file mode 100644 index 000000000000..54df1f084509 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c @@ -0,0 +1,1908 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +/* + * This structure contains the "safe" GPMI timing that should succeed with any + * NAND Flash device (although, with less-than-optimal performance). + */ + +static struct gpmi_nfc_timing safe_timing = { + .data_setup_in_ns = 80, + .data_hold_in_ns = 60, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, +}; + +/* + * This array has a pointer to every NFC HAL structure. The probing process will + * find and install the one that matches the version given by the platform. + */ + +static struct nfc_hal *(nfc_hals[]) = { + /* i.mx23 */ + &gpmi_nfc_hal_v0, + /* i.mx28 */ + &gpmi_nfc_hal_v1, + /* i.mx50 */ + &gpmi_nfc_hal_v2, +}; + +/* + * This array has a pointer to every Boot ROM Helper structure. The probing + * process will find and install the one that matches the version given by the + * platform. + */ + +static struct boot_rom_helper *(boot_rom_helpers[]) = { + &gpmi_nfc_boot_rom_helper_v0, + &gpmi_nfc_boot_rom_helper_v1, +}; + +/** + * show_device_report() - Contains a shell script that creates a handy report. + * + * @d: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_report(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + static const char *script = + "GPMISysDirectory=/sys/bus/platform/devices/gpmi-nfc.0\n" + "\n" + "NodeList='\n" + "physical_geometry\n" + "nfc_info\n" + "nfc_geometry\n" + "timing\n" + "timing_diagram\n" + "rom_geometry\n" + "mtd_nand_info\n" + "mtd_info\n" + "'\n" + "\n" + "cd ${GPMISysDirectory}\n" + "\n" + "printf '\\n'\n" + "\n" + "for NodeName in ${NodeList}\n" + "do\n" + "\n" + " printf '--------------------------------------------\\n'\n" + " printf '%s\\n' ${NodeName}\n" + " printf '--------------------------------------------\\n'\n" + " printf '\\n'\n" + "\n" + " cat ${NodeName}\n" + "\n" + " printf '\\n'\n" + "\n" + "done\n" + ; + + return sprintf(buf, "%s", script); + +} + +/** + * show_device_numchips() - Shows the number of physical chips. + * + * This node is made obsolete by the physical_geometry node, but we keep it for + * backward compatibility (especially for kobs). + * + * @d: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_numchips(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct physical_geometry *physical = &this->physical_geometry; + + return sprintf(buf, "%d\n", physical->chip_count); + +} + +/** + * show_device_physical_geometry() - Shows the physical Flash device geometry. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_physical_geometry(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct nand_device_info *info = &this->device_info; + struct physical_geometry *physical = &this->physical_geometry; + + return sprintf(buf, + "Description : %s\n" + "Chip Count : %u\n" + "Chip Size in Bytes : %llu\n" + "Block Size in Bytes : %u\n" + "Page Data Size in Bytes: %u\n" + "Page OOB Size in Bytes : %u\n" + , + info->description, + physical->chip_count, + physical->chip_size_in_bytes, + physical->block_size_in_bytes, + physical->page_data_size_in_bytes, + physical->page_oob_size_in_bytes + ); + +} + +/** + * show_device_nfc_info() - Shows the NFC-specific information. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_nfc_info(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct nfc_hal *nfc = this->nfc; + + return sprintf(buf, + "Version : %u\n" + "Description : %s\n" + "Max Chip Count : %u\n" + "Max Data Setup Cycles : 0x%x\n" + "Internal Data Setup in ns : %u\n" + "Max Sample Delay Factor : 0x%x\n" + "Max DLL Clock Period in ns: %u\n" + "Max DLL Delay in ns : %u\n" + , + nfc->version, + nfc->description, + nfc->max_chip_count, + nfc->max_data_setup_cycles, + nfc->internal_data_setup_in_ns, + nfc->max_sample_delay_factor, + nfc->max_dll_clock_period_in_ns, + nfc->max_dll_delay_in_ns + ); + +} + +/** + * show_device_nfc_geometry() - Shows the NFC view of the device geometry. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_nfc_geometry(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct nfc_geometry *nfc = &this->nfc_geometry; + + return sprintf(buf, + "ECC Algorithm : %s\n" + "ECC Strength : %u\n" + "Page Size in Bytes : %u\n" + "Metadata Size in Bytes : %u\n" + "ECC Chunk Size in Bytes: %u\n" + "ECC Chunk Count : %u\n" + "Payload Size in Bytes : %u\n" + "Auxiliary Size in Bytes: %u\n" + "Auxiliary Status Offset: %u\n" + "Block Mark Byte Offset : %u\n" + "Block Mark Bit Offset : %u\n" + , + nfc->ecc_algorithm, + nfc->ecc_strength, + nfc->page_size_in_bytes, + nfc->metadata_size_in_bytes, + nfc->ecc_chunk_size_in_bytes, + nfc->ecc_chunk_count, + nfc->payload_size_in_bytes, + nfc->auxiliary_size_in_bytes, + nfc->auxiliary_status_offset, + nfc->block_mark_byte_offset, + nfc->block_mark_bit_offset + ); + +} + +/** + * show_device_rom_geometry() - Shows the Boot ROM Helper's geometry. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_rom_geometry(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct boot_rom_geometry *rom = &this->rom_geometry; + + return sprintf(buf, + "Boot Area Count : %u\n" + "Boot Area Size in Bytes : %u\n" + "Stride Size in Pages : %u\n" + "Seach Area Stride Exponent: %u\n" + , + rom->boot_area_count, + rom->boot_area_size_in_bytes, + rom->stride_size_in_pages, + rom->search_area_stride_exponent + ); + +} + +/** + * show_device_mtd_nand_info() - Shows the device's MTD NAND-specific info. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_mtd_nand_info(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int o = 0; + unsigned int i; + unsigned int j; + static const unsigned int columns = 8; + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + struct nand_chip *nand = &mil->nand; + + o += sprintf(buf + o, + "Options : 0x%08x\n" + "Chip Count : %u\n" + "Chip Size in Bytes : %llu\n" + "Minimum Writable Size in Bytes: %u\n" + "Page Shift : %u\n" + "Page Mask : 0x%x\n" + "Block Shift : %u\n" + "BBT Block Shift : %u\n" + "Chip Shift : %u\n" + "Block Mark Offset : %u\n" + "Cached Page Number : %d\n" + , + nand->options, + nand->numchips, + nand->chipsize, + nand->subpagesize, + nand->page_shift, + nand->pagemask, + nand->phys_erase_shift, + nand->bbt_erase_shift, + nand->chip_shift, + nand->badblockpos, + nand->pagebuf + ); + + o += sprintf(buf + o, + "ECC Byte Count : %u\n" + , + nand->ecc.layout->eccbytes + ); + + /* Loop over rows. */ + + for (i = 0; (i * columns) < nand->ecc.layout->eccbytes; i++) { + + /* Loop over columns within rows. */ + + for (j = 0; j < columns; j++) { + + if (((i * columns) + j) >= nand->ecc.layout->eccbytes) + break; + + o += sprintf(buf + o, " %3u", + nand->ecc.layout->eccpos[(i * columns) + j]); + + } + + o += sprintf(buf + o, "\n"); + + } + + o += sprintf(buf + o, + "OOB Available Bytes : %u\n" + , + nand->ecc.layout->oobavail + ); + + j = 0; + + for (i = 0; j < nand->ecc.layout->oobavail; i++) { + + j += nand->ecc.layout->oobfree[i].length; + + o += sprintf(buf + o, + " [%3u, %2u]\n" + , + nand->ecc.layout->oobfree[i].offset, + nand->ecc.layout->oobfree[i].length + ); + + } + + return o; + +} + +/** + * show_device_mtd_info() - Shows the device's MTD-specific information. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_mtd_info(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int o = 0; + unsigned int i; + unsigned int j; + static const unsigned int columns = 8; + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + + o += sprintf(buf + o, + "Name : %s\n" + "Type : %u\n" + "Flags : 0x%08x\n" + "Size in Bytes : %llu\n" + "Erase Region Count : %d\n" + "Erase Size in Bytes: %u\n" + "Write Size in Bytes: %u\n" + "OOB Size in Bytes : %u\n" + "Errors Corrected : %u\n" + "Failed Reads : %u\n" + "Bad Block Count : %u\n" + "BBT Block Count : %u\n" + , + mtd->name, + mtd->type, + mtd->flags, + mtd->size, + mtd->numeraseregions, + mtd->erasesize, + mtd->writesize, + mtd->oobsize, + mtd->ecc_stats.corrected, + mtd->ecc_stats.failed, + mtd->ecc_stats.badblocks, + mtd->ecc_stats.bbtblocks + ); + + o += sprintf(buf + o, + "ECC Byte Count : %u\n" + , + mtd->ecclayout->eccbytes + ); + + /* Loop over rows. */ + + for (i = 0; (i * columns) < mtd->ecclayout->eccbytes; i++) { + + /* Loop over columns within rows. */ + + for (j = 0; j < columns; j++) { + + if (((i * columns) + j) >= mtd->ecclayout->eccbytes) + break; + + o += sprintf(buf + o, " %3u", + mtd->ecclayout->eccpos[(i * columns) + j]); + + } + + o += sprintf(buf + o, "\n"); + + } + + o += sprintf(buf + o, + "OOB Available Bytes: %u\n" + , + mtd->ecclayout->oobavail + ); + + j = 0; + + for (i = 0; j < mtd->ecclayout->oobavail; i++) { + + j += mtd->ecclayout->oobfree[i].length; + + o += sprintf(buf + o, + " [%3u, %2u]\n" + , + mtd->ecclayout->oobfree[i].offset, + mtd->ecclayout->oobfree[i].length + ); + + } + + return o; + +} + +/** + * show_device_timing_diagram() - Shows a timing diagram. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_timing_diagram(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct nfc_hal *nfc = this->nfc; + struct gpmi_nfc_timing timing = nfc->timing; + struct gpmi_nfc_hardware_timing hardware_timing; + unsigned long clock_frequency_in_hz; + unsigned long clock_period_in_ns; + unsigned int data_setup_in_ns; + unsigned int dll_delay_shift; + unsigned int sample_delay_in_ns; + unsigned int tDS_in_ns; + unsigned int tOPEN_in_ns; + unsigned int tCLOSE_in_ns; + unsigned int tEYE_in_ns; + unsigned int tDELAY_in_ns; + unsigned int tDS; + unsigned int tOPEN; + unsigned int tCLOSE; + unsigned int tEYE; + unsigned int tDELAY; + const unsigned int diagram_width_in_chars = 55; + unsigned int diagram_width_in_ns; + int o = 0; + unsigned int i; + + /* + * If there are any timing characteristics we need, but don't know, we + * pretend they're zero. + */ + + if (timing.tREA_in_ns < 0) + timing.tREA_in_ns = 0; + + if (timing.tRHOH_in_ns < 0) + timing.tRHOH_in_ns = 0; + + /* Get information about the current/last I/O transaction. */ + + nfc->get_timing(this, &clock_frequency_in_hz, &hardware_timing); + + clock_period_in_ns = 1000000000 / clock_frequency_in_hz; + + /* Compute basic timing facts. */ + + data_setup_in_ns = + hardware_timing.data_setup_in_cycles * clock_period_in_ns; + + /* Compute data sample delay facts. */ + + dll_delay_shift = 3; + + if (hardware_timing.use_half_periods) + dll_delay_shift++; + + sample_delay_in_ns = + (hardware_timing.sample_delay_factor * clock_period_in_ns) >> + dll_delay_shift; + + /* Compute the basic metrics in the diagram, in nanoseconds. */ + + tDS_in_ns = data_setup_in_ns; + tOPEN_in_ns = pdata->max_prop_delay_in_ns + timing.tREA_in_ns; + tCLOSE_in_ns = pdata->min_prop_delay_in_ns + timing.tRHOH_in_ns; + tEYE_in_ns = tDS_in_ns + tCLOSE_in_ns - tOPEN_in_ns; + tDELAY_in_ns = sample_delay_in_ns; + + /* + * We need to translate nanosecond timings into character widths in the + * diagram. The first step is to discover how "wide" the diagram is in + * nanoseconds. That depends on which happens latest: the sample point + * or the close of the eye. + */ + + if (tCLOSE_in_ns >= tDELAY_in_ns) + diagram_width_in_ns = tDS_in_ns + tCLOSE_in_ns; + else + diagram_width_in_ns = tDS_in_ns + tDELAY_in_ns; + + /* Convert the metrics that appear in the diagram. */ + + tDS = (tDS_in_ns * diagram_width_in_chars) / diagram_width_in_ns; + tOPEN = (tOPEN_in_ns * diagram_width_in_chars) / diagram_width_in_ns; + tCLOSE = (tCLOSE_in_ns * diagram_width_in_chars) / diagram_width_in_ns; + tEYE = (tEYE_in_ns * diagram_width_in_chars) / diagram_width_in_ns; + tDELAY = (tDELAY_in_ns * diagram_width_in_chars) / diagram_width_in_ns; + + /* + * Show the results. + * + * This code is really ugly, but it draws a pretty picture :) + */ + + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, "Sample ______"); + for (i = 0; i < tDS; i++) + o += sprintf(buf + o, "_"); + if (tDELAY > 0) + for (i = 0; i < (tDELAY - 1); i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "|"); + for (i = 0; i < (diagram_width_in_chars - (tDS + tDELAY)); i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, "Strobe "); + for (i = 0; i < tDS; i++) + o += sprintf(buf + o, " "); + o += sprintf(buf + o, "|"); + if (tDELAY > 1) { + for (i = 2; i < tDELAY; i++) + o += sprintf(buf + o, "-"); + o += sprintf(buf + o, "|"); + } + o += sprintf(buf + o, " tDELAY\n"); + + + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " tDS "); + o += sprintf(buf + o, "|"); + if (tDS > 1) { + for (i = 2; i < tDS; i++) + o += sprintf(buf + o, "-"); + o += sprintf(buf + o, "|"); + } + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " ______"); + for (i = 0; i < tDS; i++) + o += sprintf(buf + o, " "); + for (i = 0; i < (diagram_width_in_chars - tDS); i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, "RDN "); + if (tDS > 0) { + if (tDS == 1) + o += sprintf(buf + o, "V"); + else { + o += sprintf(buf + o, "\\"); + for (i = 2; i < tDS; i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "/"); + } + } + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " tOPEN "); + o += sprintf(buf + o, "|"); + if (tOPEN > 1) { + for (i = 2; i < tOPEN; i++) + o += sprintf(buf + o, "-"); + o += sprintf(buf + o, "|"); + } + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " "); + for (i = 0; i < tDS; i++) + o += sprintf(buf + o, " "); + o += sprintf(buf + o, "|"); + if (tCLOSE > 1) { + for (i = 2; i < tCLOSE; i++) + o += sprintf(buf + o, "-"); + o += sprintf(buf + o, "|"); + } + o += sprintf(buf + o, " tCLOSE\n"); + + + o += sprintf(buf + o, " "); + for (i = 0; i < tOPEN; i++) + o += sprintf(buf + o, " "); + if (tEYE > 2) { + o += sprintf(buf + o, " "); + for (i = 2; i < tEYE; i++) + o += sprintf(buf + o, "_"); + } + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, "Data ______"); + for (i = 0; i < tOPEN; i++) + o += sprintf(buf + o, "_"); + if (tEYE > 0) { + if (tEYE == 1) + o += sprintf(buf + o, "|"); + else { + o += sprintf(buf + o, "/"); + for (i = 2; i < tEYE; i++) + o += sprintf(buf + o, " "); + o += sprintf(buf + o, "\\"); + } + } + for (i = 0; i < (diagram_width_in_chars - (tOPEN + tEYE)); i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " "); + for (i = 0; i < tOPEN; i++) + o += sprintf(buf + o, " "); + if (tEYE > 0) { + if (tEYE == 1) + o += sprintf(buf + o, "|"); + else { + o += sprintf(buf + o, "\\"); + for (i = 2; i < tEYE; i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "/"); + } + } + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " "); + for (i = 0; i < tOPEN; i++) + o += sprintf(buf + o, " "); + o += sprintf(buf + o, "|"); + if (tEYE > 1) { + for (i = 2; i < tEYE; i++) + o += sprintf(buf + o, "-"); + o += sprintf(buf + o, "|"); + } + o += sprintf(buf + o, " tEYE\n"); + + + o += sprintf(buf + o, "\n"); + o += sprintf(buf + o, "tDS : %u ns\n", tDS_in_ns); + o += sprintf(buf + o, "tOPEN : %u ns\n", tOPEN_in_ns); + o += sprintf(buf + o, "tCLOSE: %u ns\n", tCLOSE_in_ns); + o += sprintf(buf + o, "tEYE : %u ns\n", tEYE_in_ns); + o += sprintf(buf + o, "tDELAY: %u ns\n", tDELAY_in_ns); + o += sprintf(buf + o, "\n"); + + + return o; + +} + +/** + * store_device_invalidate_page_cache() - Invalidates the device's page cache. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_invalidate_page_cache(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + + /* Invalidate the page cache. */ + + this->mil.nand.pagebuf = -1; + + /* Return success. */ + + return size; + +} + +/** + * store_device_mark_block_bad() - Marks a block as bad. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_mark_block_bad(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + struct nand_chip *nand = &mil->nand; + unsigned long block_number; + loff_t byte_address; + int error; + + /* Look for nonsense. */ + + if (!size) + return -EINVAL; + + /* Try to understand the block number. */ + + if (strict_strtoul(buf, 0, &block_number)) + return -EINVAL; + + /* Compute the byte address of this block. */ + + byte_address = block_number << nand->phys_erase_shift; + + /* Attempt to mark the block bad. */ + + error = mtd->block_markbad(mtd, byte_address); + + if (error) + return error; + + /* Return success. */ + + return size; + +} + +/** + * show_device_ignorebad() - Shows the value of the 'ignorebad' flag. + * + * @d: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_ignorebad(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + + return sprintf(buf, "%d\n", mil->ignore_bad_block_marks); +} + +/** + * store_device_ignorebad() - Sets the value of the 'ignorebad' flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_ignorebad(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + const char *p = buf; + unsigned long v; + + /* Try to make sense of what arrived from user space. */ + + if (strict_strtoul(p, 0, &v) < 0) + return size; + + if (v > 0) + v = 1; + + /* Only do something if the value is changing. */ + + if (v != mil->ignore_bad_block_marks) { + + if (v) { + + /* + * If control arrives here, we want to begin ignoring + * bad block marks. Reach into the NAND Flash MTD data + * structures and set the in-memory BBT pointer to NULL. + * This will cause the NAND Flash MTD code to believe + * that it never created a BBT and force it to call our + * block_bad function. + * + * See mil_block_bad for more details. + */ + + mil->saved_bbt = mil->nand.bbt; + mil->nand.bbt = 0; + + } else { + + /* + * If control arrives here, we want to stop ignoring + * bad block marks. Restore the NAND Flash MTD's pointer + * to its in-memory BBT. + */ + + mil->nand.bbt = mil->saved_bbt; + + } + + mil->ignore_bad_block_marks = v; + + } + + return size; + +} + +/** + * show_device_inject_ecc_error() - Shows the device's error injection flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_inject_ecc_error(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + + return sprintf(buf, "%d\n", mil->inject_ecc_error); + +} + +/** + * store_device_inject_ecc_error() - Sets the device's error injection flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_inject_ecc_error(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + long new_inject_ecc_error; + + /* Look for nonsense. */ + + if (!size) + return -EINVAL; + + /* Try to understand the ECC error count. */ + + if (strict_strtol(buf, 0, &new_inject_ecc_error)) + return -EINVAL; + + /* Store the value. */ + + mil->inject_ecc_error = new_inject_ecc_error; + + /* Return success. */ + + return size; + +} + +/** + * show_device_timing_help() - Show help for setting timing. + * + * @d: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_timing_help(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + static const char *help = + ",,
,," + ",,\n"; + + return sprintf(buf, "%s", help); + +} + +/** + * show_device_timing() - Shows the current timing. + * + * @d: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_timing(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct nfc_hal *nfc = this->nfc; + struct gpmi_nfc_timing *recorded = &nfc->timing; + unsigned long clock_frequency_in_hz; + unsigned long clock_period_in_ns; + struct gpmi_nfc_hardware_timing hardware; + unsigned int effective_data_setup_in_ns; + unsigned int effective_data_hold_in_ns; + unsigned int effective_address_setup_in_ns; + unsigned int dll_delay_shift; + unsigned int effective_sample_delay_in_ns; + + /* Get information about the current/last I/O transaction. */ + + nfc->get_timing(this, &clock_frequency_in_hz, &hardware); + + clock_period_in_ns = 1000000000 / clock_frequency_in_hz; + + /* Compute basic timing facts. */ + + effective_data_setup_in_ns = + hardware.data_setup_in_cycles * clock_period_in_ns; + effective_data_hold_in_ns = + hardware.data_hold_in_cycles * clock_period_in_ns; + effective_address_setup_in_ns = + hardware.address_setup_in_cycles * clock_period_in_ns; + + /* Compute data sample delay facts. */ + + dll_delay_shift = 3; + + if (hardware.use_half_periods) + dll_delay_shift++; + + effective_sample_delay_in_ns = + (hardware.sample_delay_factor * clock_period_in_ns) >> + dll_delay_shift; + + /* Show the results. */ + + return sprintf(buf, + "Minimum Propagation Delay in ns : %u\n" + "Maximum Propagation Delay in ns : %u\n" + "Clock Frequency in Hz : %lu\n" + "Clock Period in ns : %lu\n" + "Recorded Data Setup in ns : %d\n" + "Hardware Data Setup in cycles : %u\n" + "Effective Data Setup in ns : %u\n" + "Recorded Data Hold in ns : %d\n" + "Hardware Data Hold in cycles : %u\n" + "Effective Data Hold in ns : %u\n" + "Recorded Address Setup in ns : %d\n" + "Hardware Address Setup in cycles: %u\n" + "Effective Address Setup in ns : %u\n" + "Using Half Period : %s\n" + "Recorded Sample Delay in ns : %d\n" + "Hardware Sample Delay Factor : %u\n" + "Effective Sample Delay in ns : %u\n" + "Recorded tREA in ns : %d\n" + "Recorded tRLOH in ns : %d\n" + "Recorded tRHOH in ns : %d\n" + , + pdata->min_prop_delay_in_ns, + pdata->max_prop_delay_in_ns, + clock_frequency_in_hz, + clock_period_in_ns, + recorded->data_setup_in_ns, + hardware .data_setup_in_cycles, + effective_data_setup_in_ns, + recorded->data_hold_in_ns, + hardware .data_hold_in_cycles, + effective_data_hold_in_ns, + recorded->address_setup_in_ns, + hardware .address_setup_in_cycles, + effective_address_setup_in_ns, + hardware .use_half_periods ? "Yes" : "No", + recorded->gpmi_sample_delay_in_ns, + hardware .sample_delay_factor, + effective_sample_delay_in_ns, + recorded->tREA_in_ns, + recorded->tRLOH_in_ns, + recorded->tRHOH_in_ns); + +} + +/** + * store_device_timing() - Sets the current timing. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_timing(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct nfc_hal *nfc = this->nfc; + const char *p = buf; + const char *q; + char tmps[20]; + long t; + struct gpmi_nfc_timing new; + + int8_t *field_pointers[] = { + &new.data_setup_in_ns, + &new.data_hold_in_ns, + &new.address_setup_in_ns, + &new.gpmi_sample_delay_in_ns, + &new.tREA_in_ns, + &new.tRLOH_in_ns, + &new.tRHOH_in_ns, + NULL, + }; + + int8_t **field_pointer = field_pointers; + + /* + * Loop over comma-separated timing values in the incoming buffer, + * assigning them to fields in the timing structure as we go along. + */ + + while (*field_pointer != NULL) { + + /* Clear out the temporary buffer. */ + + memset(tmps, 0, sizeof(tmps)); + + /* Copy the timing value into the temporary buffer. */ + + q = strchr(p, ','); + if (q) + strncpy(tmps, p, min_t(int, sizeof(tmps) - 1, q - p)); + else + strncpy(tmps, p, sizeof(tmps) - 1); + + /* Attempt to convert the current timing value. */ + + if (strict_strtol(tmps, 0, &t) < 0) + return -EINVAL; + + if ((t > 127) || (t < -128)) + return -EINVAL; + + /* Assign this value to the current field. */ + + **field_pointer = (int8_t) t; + field_pointer++; + + /* Check if we ran out of input too soon. */ + + if (!q && *field_pointer) + return -EINVAL; + + /* Move past the comma to the next timing value. */ + + p = q + 1; + + } + + /* Hand over the timing to the NFC. */ + + nfc->set_timing(this, &new); + + /* Return success. */ + + return size; + +} + +/* Device attributes that appear in sysfs. */ + +static DEVICE_ATTR(report , 0555, show_device_report , 0); +static DEVICE_ATTR(numchips , 0444, show_device_numchips , 0); +static DEVICE_ATTR(physical_geometry, 0444, show_device_physical_geometry, 0); +static DEVICE_ATTR(nfc_info , 0444, show_device_nfc_info , 0); +static DEVICE_ATTR(nfc_geometry , 0444, show_device_nfc_geometry , 0); +static DEVICE_ATTR(rom_geometry , 0444, show_device_rom_geometry , 0); +static DEVICE_ATTR(mtd_nand_info , 0444, show_device_mtd_nand_info , 0); +static DEVICE_ATTR(mtd_info , 0444, show_device_mtd_info , 0); +static DEVICE_ATTR(timing_diagram , 0444, show_device_timing_diagram , 0); +static DEVICE_ATTR(timing_help , 0444, show_device_timing_help , 0); + +static DEVICE_ATTR(invalidate_page_cache, 0644, + 0, store_device_invalidate_page_cache); + +static DEVICE_ATTR(mark_block_bad, 0200, + 0, store_device_mark_block_bad); + +static DEVICE_ATTR(ignorebad, 0644, + show_device_ignorebad, store_device_ignorebad); + +static DEVICE_ATTR(inject_ecc_error, 0644, + show_device_inject_ecc_error, store_device_inject_ecc_error); + +static DEVICE_ATTR(timing, 0644, + show_device_timing, store_device_timing); + +static struct device_attribute *device_attributes[] = { + &dev_attr_report, + &dev_attr_numchips, + &dev_attr_physical_geometry, + &dev_attr_nfc_info, + &dev_attr_nfc_geometry, + &dev_attr_rom_geometry, + &dev_attr_mtd_nand_info, + &dev_attr_mtd_info, + &dev_attr_invalidate_page_cache, + &dev_attr_mark_block_bad, + &dev_attr_ignorebad, + &dev_attr_inject_ecc_error, + &dev_attr_timing, + &dev_attr_timing_help, + &dev_attr_timing_diagram, +}; + +/** + * validate_the_platform() - Validates information about the platform. + * + * @pdev: A pointer to the platform device data structure. + */ +static int validate_the_platform(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct gpmi_nfc_platform_data *pdata = pdev->dev.platform_data; + + /* Validate the clock name. */ + + if (!pdata->clock_name) { + dev_err(dev, "No clock name\n"); + return -ENXIO; + } + + /* Validate the partitions. */ + + if ((pdata->partitions && (!pdata->partition_count)) || + (!pdata->partitions && (pdata->partition_count))) { + dev_err(dev, "Bad partition data\n"); + return -ENXIO; + } + + /* Return success */ + + return 0; + +} + +/** + * acquire_register_block() - Tries to acquire and map a register block. + * + * @this: Per-device data. + * @resource_name: The name of the resource. + * @reg_block_base: A pointer to a variable that will receive the address of + * the mapped register block. + */ +static int acquire_register_block(struct gpmi_nfc_data *this, + const char *resource_name, void **reg_block_base) +{ + struct platform_device *pdev = this->pdev; + struct device *dev = this->dev; + void *p; + struct resource *r; + + /* Attempt to get information about the given resource. */ + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, resource_name); + + if (!r) { + dev_err(dev, "Can't get resource information for '%s'\n", + resource_name); + return -ENXIO; + } + + /* Attempt to remap the register block. */ + + p = ioremap(r->start, r->end - r->start + 1); + + if (!p) { + dev_err(dev, "Can't remap %s\n", resource_name); + return -EIO; + } + + /* If control arrives here, everything went fine. */ + + *reg_block_base = p; + + return 0; + +} + +/** + * release_register_block() - Releases a register block. + * + * @this: Per-device data. + * @reg_block_base: A pointer to the mapped register block. + */ +static void release_register_block(struct gpmi_nfc_data *this, + void *reg_block_base) +{ + iounmap(reg_block_base); +} + +/** + * acquire_interrupt() - Tries to acquire an interrupt. + * + * @this: Per-device data. + * @resource_name: The name of the resource. + * @interrupt_handler: A pointer to the function that will handle interrupts + * from this interrupt number. + * @lno: A pointer to a variable that will receive the acquired + * interrupt number(low part). + * @hno: A pointer to a variable that will receive the acquired + * interrupt number(high part). + */ +static int acquire_interrupt( + struct gpmi_nfc_data *this, const char *resource_name, + irq_handler_t interrupt_handler, int *lno, int *hno) +{ + struct platform_device *pdev = this->pdev; + struct device *dev = this->dev; + int error = 0; + struct resource *r; + int i; + + /* Attempt to get information about the given resource. */ + + r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, resource_name); + + if (!r) { + dev_err(dev, "Can't get resource information for '%s'\n", + resource_name); + return -ENXIO; + } + + /* Attempt to own the interrupt. */ + for (i = r->start; i <= r->end; i++) { + error = request_irq(i, interrupt_handler, 0, + resource_name, this); + + if (error) { + dev_err(dev, "Can't own %s\n", resource_name); + + /* Free all the irq's we've already acquired. */ + + while ((i - r->start) >= 0) { + free_irq(i, this); + i--; + } + + return -EIO; + } + } + + /* If control arrives here, everything went fine. */ + + *lno = r->start; + *hno = r->end; + + return 0; + +} + +/** + * release_interrupt() - Releases an interrupt. + * + * @this: Per-device data. + * @interrupt_number: The interrupt number. + */ +static void release_interrupt(struct gpmi_nfc_data *this, + int low_interrupt_number, int high_interrupt_number) +{ + int i; + for (i = low_interrupt_number; i <= high_interrupt_number; i++) + free_irq(i, this); +} + +/** + * acquire_dma_channels() - Tries to acquire DMA channels. + * + * @this: Per-device data. + * @resource_name: The name of the resource. + * @low_channel: A pointer to a variable that will receive the acquired + * low DMA channel number. + * @high_channel: A pointer to a variable that will receive the acquired + * high DMA channel number. + */ +static int acquire_dma_channels( + struct gpmi_nfc_data *this, const char *resource_name, + unsigned *low_channel, unsigned *high_channel) +{ + struct platform_device *pdev = this->pdev; + struct device *dev = this->dev; + int error = 0; + struct resource *r; + unsigned int dma_channel; + + /* Attempt to get information about the given resource. */ + + r = platform_get_resource_byname(pdev, IORESOURCE_DMA, resource_name); + + if (!r) { + dev_err(dev, "Can't get resource information for '%s'\n", + resource_name); + return -ENXIO; + } + + /* Loop over DMA channels, attempting to own them. */ + + for (dma_channel = r->start; dma_channel <= r->end; dma_channel++) { + + /* Attempt to own the current channel. */ + + error = mxs_dma_request(dma_channel, dev, resource_name); + + /* Check if we successfully acquired the current channel. */ + + if (error) { + + dev_err(dev, "Can't acquire DMA channel %u\n", + dma_channel); + + /* Free all the channels we've already acquired. */ + + while (--dma_channel >= 0) + mxs_dma_release(dma_channel, dev); + + return error; + + } + + /* + * If control arrives here, we successfully acquired the + * current channel. Continue initializing it. + */ + + mxs_dma_reset(dma_channel); + mxs_dma_ack_irq(dma_channel); + + } + + /* If control arrives here, all went well. */ + + *low_channel = r->start; + *high_channel = r->end; + + return 0; + +} + +/** + * release_dma_channels() - Releases DMA channels. + * + * @this: Per-device data. + * @low_channel: The low DMA channel number. + * @high_channel: The high DMA channel number. + */ +static void release_dma_channels(struct gpmi_nfc_data *this, + unsigned low_channel, unsigned high_channel) +{ + struct device *dev = this->dev; + unsigned int i; + + for (i = low_channel; i <= high_channel; i++) + mxs_dma_release(i, dev); +} + +/** + * acquire_clock() - Tries to acquire a clock. + * + * @this: Per-device data. + * @resource_name: The name of the clock. + * @high_channel: A pointer to a variable that will receive the acquired + * clock address. + */ +static int acquire_clock(struct gpmi_nfc_data *this, + const char *clock_name, struct clk **clock) +{ + struct device *dev = this->dev; + int error = 0; + struct clk *c; + + /* Try to get the clock. */ + + c = clk_get(dev, clock_name); + + if (IS_ERR(c)) { + error = PTR_ERR(c); + dev_err(dev, "Can't own clock %s\n", clock_name); + return error; + } + + /* If control arrives here, everything went fine. */ + + *clock = c; + + return 0; + +} + +/** + * release_clock() - Releases a clock. + * + * @this: Per-device data. + * @clock: A pointer to the clock structure. + */ +static void release_clock(struct gpmi_nfc_data *this, struct clk *clock) +{ + clk_disable(clock); + clk_put(clock); +} + +/** + * acquire_resources() - Tries to acquire resources. + * + * @this: Per-device data. + */ +static int acquire_resources(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct resources *resources = &this->resources; + int error = 0; + + /* Attempt to acquire the GPMI register block. */ + + error = acquire_register_block(this, + GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, &(resources->gpmi_regs)); + + if (error) + goto exit_gpmi_regs; + + /* Attempt to acquire the BCH register block. */ + + error = acquire_register_block(this, + GPMI_NFC_BCH_REGS_ADDR_RES_NAME, &(resources->bch_regs)); + + if (error) + goto exit_bch_regs; + + /* Attempt to acquire the BCH interrupt. */ + + error = acquire_interrupt(this, + GPMI_NFC_BCH_INTERRUPT_RES_NAME, + gpmi_nfc_bch_isr, + &(resources->bch_low_interrupt), + &(resources->bch_high_interrupt)); + + if (error) + goto exit_bch_interrupt; + + /* Attempt to acquire the DMA channels. */ + + error = acquire_dma_channels(this, + GPMI_NFC_DMA_CHANNELS_RES_NAME, + &(resources->dma_low_channel), &(resources->dma_high_channel)); + + if (error) + goto exit_dma_channels; + + /* Attempt to acquire the DMA interrupt. */ + + error = acquire_interrupt(this, + GPMI_NFC_DMA_INTERRUPT_RES_NAME, + gpmi_nfc_dma_isr, + &(resources->dma_low_interrupt), + &(resources->dma_high_interrupt)); + + if (error) + goto exit_dma_interrupt; + + /* Attempt to acquire our clock. */ + + error = acquire_clock(this, pdata->clock_name, &(resources->clock)); + + if (error) + goto exit_clock; + + /* If control arrives here, all went well. */ + + return 0; + + /* Control arrives here if something went wrong. */ + +exit_clock: + release_interrupt(this, + resources->dma_low_interrupt, resources->dma_high_interrupt); +exit_dma_interrupt: + release_dma_channels(this, + resources->dma_low_channel, resources->dma_high_channel); +exit_dma_channels: + release_interrupt(this, + resources->bch_low_interrupt, resources->bch_high_interrupt); +exit_bch_interrupt: + release_register_block(this, resources->bch_regs); +exit_bch_regs: + release_register_block(this, resources->gpmi_regs); +exit_gpmi_regs: + + return error; + +} + +/** + * release_resources() - Releases resources. + * + * @this: Per-device data. + */ +static void release_resources(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + release_clock(this, resources->clock); + release_register_block(this, resources->gpmi_regs); + release_register_block(this, resources->bch_regs); + release_interrupt(this, + resources->bch_low_interrupt, resources->bch_low_interrupt); + release_dma_channels(this, + resources->dma_low_channel, resources->dma_high_channel); + release_interrupt(this, + resources->dma_low_interrupt, resources->dma_high_interrupt); +} + +/** + * set_up_nfc_hal() - Sets up the NFC HAL. + * + * @this: Per-device data. + */ +static int set_up_nfc_hal(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct device *dev = this->dev; + struct nfc_hal *nfc; + int error = 0; + unsigned int i; + + /* Attempt to find an NFC HAL that matches the given version. */ + + for (i = 0; i < ARRAY_SIZE(nfc_hals); i++) { + + nfc = nfc_hals[i]; + + if (nfc->version == pdata->nfc_version) { + this->nfc = nfc; + break; + } + + } + + /* Check if we found a HAL. */ + + if (i >= ARRAY_SIZE(nfc_hals)) { + dev_err(dev, "Unkown NFC version %u\n", pdata->nfc_version); + return -ENXIO; + } + + pr_info("NFC: Version %u, %s\n", nfc->version, nfc->description); + + /* + * Check if we can handle the number of chips called for by the platform + * data. + */ + + if (pdata->max_chip_count > nfc->max_chip_count) { + dev_err(dev, "Platform data calls for %u chips " + "but NFC supports a max of %u.\n", + pdata->max_chip_count, nfc->max_chip_count); + return -ENXIO; + } + + /* Initialize the NFC HAL. */ + + error = nfc->init(this); + + if (error) + return error; + + /* Set up safe timing. */ + + nfc->set_timing(this, &safe_timing); + + /* + * If control arrives here, all is well. + */ + + return 0; + +} + +/** + * set_up_boot_rom_helper() - Sets up the Boot ROM Helper. + * + * @this: Per-device data. + */ +static int set_up_boot_rom_helper(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct device *dev = this->dev; + unsigned int i; + struct boot_rom_helper *rom; + + /* Attempt to find a Boot ROM Helper that matches the given version. */ + + for (i = 0; i < ARRAY_SIZE(boot_rom_helpers); i++) { + + rom = boot_rom_helpers[i]; + + if (rom->version == pdata->boot_rom_version) { + this->rom = rom; + break; + } + + } + + /* Check if we found a Boot ROM Helper. */ + + if (i >= ARRAY_SIZE(boot_rom_helpers)) { + dev_err(dev, "Unkown Boot ROM version %u\n", + pdata->boot_rom_version); + return -ENXIO; + } + + pr_info("Boot ROM: Version %u, %s\n", rom->version, rom->description); + + /* + * If control arrives here, all is well. + */ + + return 0; + +} + +/** + * manage_sysfs_files() - Creates/removes sysfs files for this device. + * + * @this: Per-device data. + */ +static void manage_sysfs_files(struct gpmi_nfc_data *this, int create) +{ + struct device *dev = this->dev; + int error; + unsigned int i; + struct device_attribute **attr; + + for (i = 0, attr = device_attributes; + i < ARRAY_SIZE(device_attributes); i++, attr++) { + + if (create) { + error = device_create_file(dev, *attr); + if (error) { + while (--attr >= device_attributes) + device_remove_file(dev, *attr); + return; + } + } else { + device_remove_file(dev, *attr); + } + + } + +} + +/** + * gpmi_nfc_probe() - Probes for a device and, if possible, takes ownership. + * + * @pdev: A pointer to the platform device data structure. + */ +static int gpmi_nfc_probe(struct platform_device *pdev) +{ + int error = 0; + struct device *dev = &pdev->dev; + struct gpmi_nfc_platform_data *pdata = pdev->dev.platform_data; + struct gpmi_nfc_data *this = 0; + + /* Validate the platform device data. */ + + error = validate_the_platform(pdev); + + if (error) + goto exit_validate_platform; + + /* Allocate memory for the per-device data. */ + + this = kzalloc(sizeof(*this), GFP_KERNEL); + + if (!this) { + dev_err(dev, "Failed to allocate per-device memory\n"); + error = -ENOMEM; + goto exit_allocate_this; + } + + /* Set up our data structures. */ + + platform_set_drvdata(pdev, this); + + this->pdev = pdev; + this->dev = &pdev->dev; + this->pdata = pdata; + + /* Acquire the resources we need. */ + + error = acquire_resources(this); + + if (error) + goto exit_acquire_resources; + + /* Set up the NFC. */ + + error = set_up_nfc_hal(this); + + if (error) + goto exit_nfc_init; + + /* Set up the platform. */ + + if (pdata->platform_init) + error = pdata->platform_init(pdata->max_chip_count); + + if (error) + goto exit_platform_init; + + /* Set up the Boot ROM Helper. */ + + error = set_up_boot_rom_helper(this); + + if (error) + goto exit_boot_rom_helper_init; + + /* Initialize the MTD Interface Layer. */ + + error = gpmi_nfc_mil_init(this); + + if (error) + goto exit_mil_init; + + /* Create sysfs entries for this device. */ + + manage_sysfs_files(this, true); + + /* Return success. */ + + return 0; + + /* Error return paths begin here. */ + +exit_mil_init: +exit_boot_rom_helper_init: + if (pdata->platform_exit) + pdata->platform_exit(pdata->max_chip_count); +exit_platform_init: + this->nfc->exit(this); +exit_nfc_init: + release_resources(this); +exit_acquire_resources: + platform_set_drvdata(pdev, NULL); + kfree(this); +exit_allocate_this: +exit_validate_platform: + return error; + +} + +/** + * gpmi_nfc_remove() - Dissociates this driver from the given device. + * + * @pdev: A pointer to the platform device data structure. + */ +static int __exit gpmi_nfc_remove(struct platform_device *pdev) +{ + struct gpmi_nfc_data *this = platform_get_drvdata(pdev); + struct gpmi_nfc_platform_data *pdata = this->pdata; + + manage_sysfs_files(this, false); + gpmi_nfc_mil_exit(this); + if (pdata->platform_exit) + pdata->platform_exit(pdata->max_chip_count); + this->nfc->exit(this); + release_resources(this); + platform_set_drvdata(pdev, NULL); + kfree(this); + + return 0; +} + +#ifdef CONFIG_PM + +/** + * gpmi_nfc_suspend() - Puts the NFC into a low power state. + * + * @pdev: A pointer to the platform device data structure. + * @state: The new power state. + */ +static int gpmi_nfc_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +/** + * gpmi_nfc_resume() - Brings the NFC back from a low power state. + * + * @pdev: A pointer to the platform device data structure. + */ +static int gpmi_nfc_resume(struct platform_device *pdev) +{ + return 0; +} + +#else + +#define suspend NULL +#define resume NULL + +#endif /* CONFIG_PM */ + +/* + * This structure represents this driver to the platform management system. + */ +static struct platform_driver gpmi_nfc_driver = { + .driver = { + .name = GPMI_NFC_DRIVER_NAME, + }, + .probe = gpmi_nfc_probe, + .remove = __exit_p(gpmi_nfc_remove), + .suspend = gpmi_nfc_suspend, + .resume = gpmi_nfc_resume, +}; + +/** + * gpmi_nfc_init() - Initializes this module. + */ +static int __init gpmi_nfc_init(void) +{ + + pr_info("i.MX GPMI NFC\n"); + + /* Register this driver with the platform management system. */ + + if (platform_driver_register(&gpmi_nfc_driver) != 0) { + pr_err("i.MX GPMI NFC driver registration failed\n"); + return -ENODEV; + } + + /* Return success. */ + + return 0; + +} + +/** + * gpmi_nfc_exit() - Deactivates this module. + */ +static void __exit gpmi_nfc_exit(void) +{ + platform_driver_unregister(&gpmi_nfc_driver); +} + +module_init(gpmi_nfc_init); +module_exit(gpmi_nfc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c new file mode 100644 index 000000000000..50ba771853a4 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c @@ -0,0 +1,2630 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +/* + * Indicates the driver should register the MTD that represents the entire + * medium, thus making it visible. + */ + +static int register_main_mtd; +module_param(register_main_mtd, int, 0400); + +/* + * Indicates the driver should attempt to perform DMA directly to/from buffers + * passed into this driver. This is true by default. If false, the driver will + * *always* copy incoming/outgoing data to/from its own DMA buffers. + */ + +static int map_io_buffers = true; +module_param(map_io_buffers, int, 0600); + +/** + * mil_outgoing_buffer_dma_begin() - Begins DMA on an outgoing buffer. + * + * @this: Per-device data. + * @source: The source buffer. + * @length: The length of the data in the source buffer. + * @alt_virt: The virtual address of an alternate buffer which is ready to be + * used for DMA. + * @alt_phys: The physical address of an alternate buffer which is ready to be + * used for DMA. + * @alt_size: The size of the alternate buffer. + * @use_virt: A pointer to a variable that will receive the virtual address to + * use. + * @use_phys: A pointer to a variable that will receive the physical address to + * use. + */ +static int mil_outgoing_buffer_dma_begin(struct gpmi_nfc_data *this, + const void *source, unsigned length, + void *alt_virt, dma_addr_t alt_phys, unsigned alt_size, + const void **use_virt, dma_addr_t *use_phys) +{ + struct device *dev = this->dev; + dma_addr_t source_phys = ~0; + + /* + * If we can, we want to use the caller's buffer directly for DMA. Check + * if the system will let us map them. + */ + + if (map_io_buffers && virt_addr_valid(source)) + source_phys = + dma_map_single(dev, + (void *) source, length, DMA_TO_DEVICE); + + if (dma_mapping_error(dev, source_phys)) { + + /* + * If control arrives here, we're not mapping the source buffer. + * Make sure the alternate is large enough. + */ + + if (alt_size < length) { + dev_err(dev, "Alternate buffer is too small " + "for outgoing I/O\n"); + return -ENOMEM; + } + + /* + * Copy the contents of the source buffer into the alternate + * buffer and set up the return values accordingly. + */ + + memcpy(alt_virt, source, length); + + *use_virt = alt_virt; + *use_phys = alt_phys; + + } else { + + /* + * If control arrives here, we're mapping the source buffer. Set + * up the return values accordingly. + */ + + *use_virt = source; + *use_phys = source_phys; + + } + + /* If control arrives here, all is well. */ + + return 0; + +} + +/** + * mil_outgoing_buffer_dma_end() - Ends DMA on an outgoing buffer. + * + * @this: Per-device data. + * @source: The source buffer. + * @length: The length of the data in the source buffer. + * @alt_virt: The virtual address of an alternate buffer which was ready to be + * used for DMA. + * @alt_phys: The physical address of an alternate buffer which was ready to + * be used for DMA. + * @alt_size: The size of the alternate buffer. + * @used_virt: The virtual address that was used. + * @used_phys: The physical address that was used. + */ +static void mil_outgoing_buffer_dma_end(struct gpmi_nfc_data *this, + const void *source, unsigned length, + void *alt_virt, dma_addr_t alt_phys, unsigned alt_size, + const void *used_virt, dma_addr_t used_phys) +{ + struct device *dev = this->dev; + + /* + * Check if we used the source buffer, and it's not one of our own DMA + * buffers. If so, we need to unmap it. + */ + + if (used_virt == source) + dma_unmap_single(dev, used_phys, length, DMA_TO_DEVICE); + +} + +/** + * mil_incoming_buffer_dma_begin() - Begins DMA on an incoming buffer. + * + * @this: Per-device data. + * @destination: The destination buffer. + * @length: The length of the data that will arrive. + * @alt_virt: The virtual address of an alternate buffer which is ready + * to be used for DMA. + * @alt_phys: The physical address of an alternate buffer which is ready + * to be used for DMA. + * @alt_size: The size of the alternate buffer. + * @use_virt: A pointer to a variable that will receive the virtual address + * to use. + * @use_phys: A pointer to a variable that will receive the physical address + * to use. + */ +static int mil_incoming_buffer_dma_begin(struct gpmi_nfc_data *this, + void *destination, unsigned length, + void *alt_virt, dma_addr_t alt_phys, unsigned alt_size, + void **use_virt, dma_addr_t *use_phys) +{ + struct device *dev = this->dev; + dma_addr_t destination_phys = ~0; + + /* + * If we can, we want to use the caller's buffer directly for DMA. Check + * if the system will let us map them. + */ + if (map_io_buffers && virt_addr_valid(destination) && + !((int)destination & 0x3) && 0) + destination_phys = + dma_map_single(dev, + (void *) destination, length, DMA_FROM_DEVICE); + + if (dma_mapping_error(dev, destination_phys)) { + + /* + * If control arrives here, we're not mapping the destination + * buffer. Make sure the alternate is large enough. + */ + + if (alt_size < length) { + dev_err(dev, "Alternate buffer is too small " + "for incoming I/O\n"); + return -ENOMEM; + } + + /* Set up the return values to use the alternate. */ + + *use_virt = alt_virt; + *use_phys = alt_phys; + + } else { + + /* + * If control arrives here, we're mapping the destination + * buffer. Set up the return values accordingly. + */ + + *use_virt = destination; + *use_phys = destination_phys; + + } + + /* If control arrives here, all is well. */ + + return 0; + +} + +/** + * mil_incoming_buffer_dma_end() - Ends DMA on an incoming buffer. + * + * @this: Per-device data. + * @destination: The destination buffer. + * @length: The length of the data that arrived. + * @alt_virt: The virtual address of an alternate buffer which was ready to + * be used for DMA. + * @alt_phys: The physical address of an alternate buffer which was ready to + * be used for DMA. + * @alt_size: The size of the alternate buffer. + * @used_virt: The virtual address that was used. + * @used_phys: The physical address that was used. + */ +static void mil_incoming_buffer_dma_end(struct gpmi_nfc_data *this, + void *destination, unsigned length, + void *alt_virt, dma_addr_t alt_phys, unsigned alt_size, + void *used_virt, dma_addr_t used_phys) +{ + struct device *dev = this->dev; + + /* + * Check if we used the destination buffer, and it's not one of our own + * DMA buffers. If so, we need to unmap it. + */ + + if (used_virt == destination) + dma_unmap_single(dev, used_phys, length, DMA_FROM_DEVICE); + else + memcpy(destination, alt_virt, length); + +} + +/** + * mil_cmd_ctrl - MTD Interface cmd_ctrl() + * + * This is the function that we install in the cmd_ctrl function pointer of the + * owning struct nand_chip. The only functions in the reference implementation + * that use these functions pointers are cmdfunc and select_chip. + * + * In this driver, we implement our own select_chip, so this function will only + * be called by the reference implementation's cmdfunc. For this reason, we can + * ignore the chip enable bit and concentrate only on sending bytes to the + * NAND Flash. + * + * @mtd: The owning MTD. + * @data: The value to push onto the data signals. + * @ctrl: The values to push onto the control signals. + */ +static void mil_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct mil *mil = &this->mil; + struct nfc_hal *nfc = this->nfc; + int error; +#if defined(CONFIG_MTD_DEBUG) + unsigned int i; + char display[MIL_COMMAND_BUFFER_SIZE * 5]; +#endif + + /* + * Every operation begins with a command byte and a series of zero or + * more address bytes. These are distinguished by either the Address + * Latch Enable (ALE) or Command Latch Enable (CLE) signals being + * asserted. When MTD is ready to execute the command, it will deassert + * both latch enables. + * + * Rather than run a separate DMA operation for every single byte, we + * queue them up and run a single DMA operation for the entire series + * of command and data bytes. + */ + + if ((ctrl & (NAND_ALE | NAND_CLE))) { + if (data != NAND_CMD_NONE) + mil->cmd_virt[mil->command_length++] = data; + return; + } + + /* + * If control arrives here, MTD has deasserted both the ALE and CLE, + * which means it's ready to run an operation. Check if we have any + * bytes to send. + */ + + if (!mil->command_length) + return; + + /* Hand the command over to the NFC. */ + + gpmi_nfc_add_event("mil_cmd_ctrl sending command...", 1); + +#if defined(CONFIG_MTD_DEBUG) + display[0] = 0; + for (i = 0; i < mil->command_length; i++) + sprintf(display + strlen(display), " 0x%02x", + mil->cmd_virt[i] & 0xff); + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc cmd_ctrl] command: %s\n", display); +#endif + + error = nfc->send_command(this, + mil->current_chip, mil->cmd_phys, mil->command_length); + + if (error) { + dev_err(dev, "[%s] Chip: %u, Error %d\n", + __func__, mil->current_chip, error); + print_hex_dump(KERN_ERR, + " Command Bytes: ", DUMP_PREFIX_NONE, 16, 1, + mil->cmd_virt, mil->command_length, 0); + } + + gpmi_nfc_add_event("...Finished", -1); + + /* Reset. */ + + mil->command_length = 0; + +} + +/** + * mil_dev_ready() - MTD Interface dev_ready() + * + * @mtd: A pointer to the owning MTD. + */ +static int mil_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + struct nfc_hal *nfc = this->nfc; + struct mil *mil = &this->mil; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc dev_ready]\n"); + + gpmi_nfc_add_event("> mil_dev_ready", 1); + + if (nfc->is_ready(this, mil->current_chip)) { + gpmi_nfc_add_event("< mil_dev_ready - Returning ready", -1); + return !0; + } else { + gpmi_nfc_add_event("< mil_dev_ready - Returning busy", -1); + return 0; + } + +} + +/** + * mil_select_chip() - MTD Interface select_chip() + * + * @mtd: A pointer to the owning MTD. + * @chip: The chip number to select, or -1 to select no chip. + */ +static void mil_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + struct mil *mil = &this->mil; + struct nfc_hal *nfc = this->nfc; + struct clk *clock = this->resources.clock; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc select_chip] chip: %d\n", chip); + + /* Figure out what kind of transition this is. */ + + if ((mil->current_chip < 0) && (chip >= 0)) { + gpmi_nfc_start_event_trace("> mil_select_chip"); + clk_enable(clock); + nfc->begin(this); + gpmi_nfc_add_event("< mil_select_chip", -1); + } else if ((mil->current_chip >= 0) && (chip < 0)) { + gpmi_nfc_add_event("> mil_select_chip", 1); + gpmi_nfc_add_event("> not disable clk", 1); + clk_disable(clock); + nfc->end(this); + gpmi_nfc_stop_event_trace("< mil_select_chip"); + } else { + gpmi_nfc_add_event("> mil_select_chip", 1); + gpmi_nfc_add_event("< mil_select_chip", -1); + } + + mil->current_chip = chip; + +} + +/** + * mil_read_buf() - MTD Interface read_buf(). + * + * @mtd: A pointer to the owning MTD. + * @buf: The destination buffer. + * @len: The number of bytes to read. + */ +static void mil_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mil *mil = &this->mil; + void *use_virt = 0; + dma_addr_t use_phys = ~0; + int error; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc readbuf] len: %d\n", len); + + gpmi_nfc_add_event("> mil_read_buf", 1); + + /* Set up DMA. */ + error = mil_incoming_buffer_dma_begin(this, buf, len, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + &use_virt, &use_phys); + + if (error) { + dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__); + goto exit; + } + + /* Ask the NFC. */ + + nfc->read_data(this, mil->current_chip, use_phys, len); + + /* Finish with DMA. */ + + mil_incoming_buffer_dma_end(this, buf, len, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + use_virt, use_phys); + + /* Return. */ + +exit: + + gpmi_nfc_add_event("< mil_read_buf", -1); + +} + +/** + * mil_write_buf() - MTD Interface write_buf(). + * + * @mtd: A pointer to the owning MTD. + * @buf: The source buffer. + * @len: The number of bytes to read. + */ +static void mil_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mil *mil = &this->mil; + const void *use_virt = 0; + dma_addr_t use_phys = ~0; + int error; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc writebuf] len: %d\n", len); + + gpmi_nfc_add_event("> mil_write_buf", 1); + + /* Set up DMA. */ + + error = mil_outgoing_buffer_dma_begin(this, buf, len, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + &use_virt, &use_phys); + + if (error) { + dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__); + goto exit; + } + + /* Ask the NFC. */ + + nfc->send_data(this, mil->current_chip, use_phys, len); + + /* Finish with DMA. */ + + mil_outgoing_buffer_dma_end(this, buf, len, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + use_virt, use_phys); + + /* Return. */ + +exit: + + gpmi_nfc_add_event("< mil_write_buf", -1); + +} + +/** + * mil_read_byte() - MTD Interface read_byte(). + * + * @mtd: A pointer to the owning MTD. + */ +static uint8_t mil_read_byte(struct mtd_info *mtd) +{ + uint8_t byte; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc read_byte]\n"); + + gpmi_nfc_add_event("> mil_read_byte", 1); + + mil_read_buf(mtd, (uint8_t *) &byte, 1); + + gpmi_nfc_add_event("< mil_read_byte", -1); + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc read_byte]: 0x%02x\n", byte); + + return byte; + +} + +/** + * mil_handle_block_mark_swapping() - Handles block mark swapping. + * + * Note that, when this function is called, it doesn't know whether it's + * swapping the block mark, or swapping it *back* -- but it doesn't matter + * because the the operation is the same. + * + * @this: Per-device data. + * @payload: A pointer to the payload buffer. + * @auxiliary: A pointer to the auxiliary buffer. + */ +static void mil_handle_block_mark_swapping(struct gpmi_nfc_data *this, + void *payload, void *auxiliary) +{ + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct boot_rom_helper *rom = this->rom; + unsigned char *p; + unsigned char *a; + unsigned int bit; + unsigned char mask; + unsigned char from_data; + unsigned char from_oob; + + /* Check if we're doing block mark swapping. */ + + if (!rom->swap_block_mark) + return; + + /* + * If control arrives here, we're swapping. Make some convenience + * variables. + */ + + bit = nfc_geo->block_mark_bit_offset; + p = ((unsigned char *) payload) + nfc_geo->block_mark_byte_offset; + a = auxiliary; + + /* + * Get the byte from the data area that overlays the block mark. Since + * the ECC engine applies its own view to the bits in the page, the + * physical block mark won't (in general) appear on a byte boundary in + * the data. + */ + + from_data = (p[0] >> bit) | (p[1] << (8 - bit)); + + /* Get the byte from the OOB. */ + + from_oob = a[0]; + + /* Swap them. */ + + a[0] = from_data; + + mask = (0x1 << bit) - 1; + p[0] = (p[0] & mask) | (from_oob << bit); + + mask = ~0 << bit; + p[1] = (p[1] & mask) | (from_oob >> (8 - bit)); + +} + +/** + * mil_ecc_read_page() - MTD Interface ecc.read_page(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @buf: A pointer to the destination buffer. + */ +static int mil_ecc_read_page(struct mtd_info *mtd, + struct nand_chip *nand, uint8_t *buf) +{ + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mil *mil = &this->mil; + void *payload_virt = 0; + dma_addr_t payload_phys = ~0; + void *auxiliary_virt = 0; + dma_addr_t auxiliary_phys = ~0; + unsigned int i; + unsigned char *status; + unsigned int failed; + unsigned int corrected; + int error = 0; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_read_page]\n"); + + gpmi_nfc_add_event("> mil_ecc_read_page", 1); + + /* + * Set up DMA. + * + * Notice that we don't try to use the caller's buffer as the auxiliary. + * We need to do a lot of fiddling to deliver the OOB, so there's no + * point. + */ + + error = mil_incoming_buffer_dma_begin(this, buf, mtd->writesize, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + &payload_virt, &payload_phys); + + if (error) { + dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__); + error = -ENOMEM; + goto exit_payload; + } + + auxiliary_virt = mil->auxiliary_virt; + auxiliary_phys = mil->auxiliary_phys; + + /* Ask the NFC. */ + + error = nfc->read_page(this, mil->current_chip, + payload_phys, auxiliary_phys); + + if (error) { + dev_err(dev, "[%s] Error in ECC-based read: %d\n", + __func__, error); + goto exit_nfc; + } + + /* Handle block mark swapping. */ + + mil_handle_block_mark_swapping(this, payload_virt, auxiliary_virt); + + /* Loop over status bytes, accumulating ECC status. */ + + failed = 0; + corrected = 0; + + status = ((unsigned char *) auxiliary_virt) + + nfc_geo->auxiliary_status_offset; + + for (i = 0; i < nfc_geo->ecc_chunk_count; i++, status++) { + + if ((*status == 0x00) || (*status == 0xff)) + continue; + + if (*status == 0xfe) { + failed++; + continue; + } + + corrected += *status; + + } + + /* Propagate ECC status to the owning MTD. */ + + mtd->ecc_stats.failed += failed; + mtd->ecc_stats.corrected += corrected; + + /* + * It's time to deliver the OOB bytes. See mil_ecc_read_oob() for + * details about our policy for delivering the OOB. + * + * We fill the caller's buffer with set bits, and then copy the block + * mark to th caller's buffer. Note that, if block mark swapping was + * necessary, it has already been done, so we can rely on the first + * byte of the auxiliary buffer to contain the block mark. + */ + + memset(nand->oob_poi, ~0, mtd->oobsize); + + nand->oob_poi[0] = ((uint8_t *) auxiliary_virt)[0]; + + /* Return. */ + +exit_nfc: + mil_incoming_buffer_dma_end(this, buf, mtd->writesize, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + payload_virt, payload_phys); +exit_payload: + + gpmi_nfc_add_event("< mil_ecc_read_page", -1); + + return error; + +} + +/** + * mil_ecc_write_page() - MTD Interface ecc.write_page(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @buf: A pointer to the source buffer. + */ +static void mil_ecc_write_page(struct mtd_info *mtd, + struct nand_chip *nand, const uint8_t *buf) +{ + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct boot_rom_helper *rom = this->rom; + struct mil *mil = &this->mil; + const void *payload_virt = 0; + dma_addr_t payload_phys = ~0; + const void *auxiliary_virt = 0; + dma_addr_t auxiliary_phys = ~0; + int error; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_write_page]\n"); + + gpmi_nfc_add_event("> mil_ecc_write_page", 1); + + /* Set up DMA. */ + + if (rom->swap_block_mark) { + + /* + * If control arrives here, we're doing block mark swapping. + * Since we can't modify the caller's buffers, we must copy them + * into our own. + */ + + memcpy(mil->payload_virt, buf, mtd->writesize); + payload_virt = mil->payload_virt; + payload_phys = mil->payload_phys; + + memcpy(mil->auxiliary_virt, nand->oob_poi, mtd->oobsize); + auxiliary_virt = mil->auxiliary_virt; + auxiliary_phys = mil->auxiliary_phys; + + /* Handle block mark swapping. */ + + mil_handle_block_mark_swapping(this, + (void *) payload_virt, (void *) auxiliary_virt); + + } else { + + /* + * If control arrives here, we're not doing block mark swapping, + * so we can to try and use the caller's buffers. + */ + + error = mil_outgoing_buffer_dma_begin(this, + buf, mtd->writesize, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + &payload_virt, &payload_phys); + + if (error) { + dev_err(dev, "[%s] Inadequate payload DMA buffer\n", + __func__); + goto exit_payload; + } + + error = mil_outgoing_buffer_dma_begin(this, + nand->oob_poi, mtd->oobsize, + mil->auxiliary_virt, mil->auxiliary_phys, + nfc_geo->auxiliary_size_in_bytes, + &auxiliary_virt, &auxiliary_phys); + + if (error) { + dev_err(dev, "[%s] Inadequate auxiliary DMA buffer\n", + __func__); + goto exit_auxiliary; + } + + } + + /* Ask the NFC. */ + + error = nfc->send_page(this, mil->current_chip, + payload_phys, auxiliary_phys); + + if (error) + dev_err(dev, "[%s] Error in ECC-based write: %d\n", + __func__, error); + + /* Return. */ + + if (!rom->swap_block_mark) + mil_outgoing_buffer_dma_end(this, nand->oob_poi, mtd->oobsize, + mil->auxiliary_virt, mil->auxiliary_phys, + nfc_geo->auxiliary_size_in_bytes, + auxiliary_virt, auxiliary_phys); +exit_auxiliary: + if (!rom->swap_block_mark) + mil_outgoing_buffer_dma_end(this, buf, mtd->writesize, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + payload_virt, payload_phys); +exit_payload: + + gpmi_nfc_add_event("< mil_ecc_write_page", -1); + +} + +/** + * mil_hook_read_oob() - Hooked MTD Interface read_oob(). + * + * This function is a veneer that replaces the function originally installed by + * the NAND Flash MTD code. See the description of the raw_oob_mode field in + * struct mil for more information about this. + * + * @mtd: A pointer to the MTD. + * @from: The starting address to read. + * @ops: Describes the operation. + */ +static int mil_hook_read_oob(struct mtd_info *mtd, + loff_t from, struct mtd_oob_ops *ops) +{ + register struct nand_chip *chip = mtd->priv; + struct gpmi_nfc_data *this = chip->priv; + struct mil *mil = &this->mil; + int ret; + + mil->raw_oob_mode = ops->mode == MTD_OOB_RAW; + ret = mil->hooked_read_oob(mtd, from, ops); + mil->raw_oob_mode = false; + return ret; +} + +/** + * mil_hook_write_oob() - Hooked MTD Interface write_oob(). + * + * This function is a veneer that replaces the function originally installed by + * the NAND Flash MTD code. See the description of the raw_oob_mode field in + * struct mil for more information about this. + * + * @mtd: A pointer to the MTD. + * @to: The starting address to write. + * @ops: Describes the operation. + */ +static int mil_hook_write_oob(struct mtd_info *mtd, + loff_t to, struct mtd_oob_ops *ops) +{ + register struct nand_chip *chip = mtd->priv; + struct gpmi_nfc_data *this = chip->priv; + struct mil *mil = &this->mil; + int ret; + + mil->raw_oob_mode = ops->mode == MTD_OOB_RAW; + ret = mil->hooked_write_oob(mtd, to, ops); + mil->raw_oob_mode = false; + return ret; +} + +/** + * mil_hook_block_markbad() - Hooked MTD Interface block_markbad(). + * + * This function is a veneer that replaces the function originally installed by + * the NAND Flash MTD code. See the description of the marking_a_bad_block field + * in struct mil for more information about this. + * + * @mtd: A pointer to the MTD. + * @ofs: Byte address of the block to mark. + */ +static int mil_hook_block_markbad(struct mtd_info *mtd, loff_t ofs) +{ + register struct nand_chip *chip = mtd->priv; + struct gpmi_nfc_data *this = chip->priv; + struct mil *mil = &this->mil; + int ret; + + mil->marking_a_bad_block = true; + ret = mil->hooked_block_markbad(mtd, ofs); + mil->marking_a_bad_block = false; + return ret; +} + +/** + * mil_ecc_read_oob() - MTD Interface ecc.read_oob(). + * + * There are several places in this driver where we have to handle the OOB and + * block marks. This is the function where things are the most complicated, so + * this is where we try to explain it all. All the other places refer back to + * here. + * + * These are the rules, in order of decreasing importance: + * + * 1) Nothing the caller does can be allowed to imperil the block mark, so all + * write operations take measures to protect it. + * + * 2) In read operations, the first byte of the OOB we return must reflect the + * true state of the block mark, no matter where that block mark appears in + * the physical page. + * + * 3) ECC-based read operations return an OOB full of set bits (since we never + * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads + * return). + * + * 4) "Raw" read operations return a direct view of the physical bytes in the + * page, using the conventional definition of which bytes are data and which + * are OOB. This gives the caller a way to see the actual, physical bytes + * in the page, without the distortions applied by our ECC engine. + * + * + * What we do for this specific read operation depends on two questions: + * + * 1) Are we doing a "raw" read, or an ECC-based read? + * + * 2) Are we using block mark swapping or transcription? + * + * There are four cases, illustrated by the following Karnaugh map: + * + * | Raw | ECC-based | + * -------------+-------------------------+-------------------------+ + * | Read the conventional | | + * | OOB at the end of the | | + * Swapping | page and return it. It | | + * | contains exactly what | | + * | we want. | Read the block mark and | + * -------------+-------------------------+ return it in a buffer | + * | Read the conventional | full of set bits. | + * | OOB at the end of the | | + * | page and also the block | | + * Transcribing | mark in the metadata. | | + * | Copy the block mark | | + * | into the first byte of | | + * | the OOB. | | + * -------------+-------------------------+-------------------------+ + * + * Note that we break rule #4 in the Transcribing/Raw case because we're not + * giving an accurate view of the actual, physical bytes in the page (we're + * overwriting the block mark). That's OK because it's more important to follow + * rule #2. + * + * It turns out that knowing whether we want an "ECC-based" or "raw" read is not + * easy. When reading a page, for example, the NAND Flash MTD code calls our + * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an + * ECC-based or raw view of the page is implicit in which function it calls + * (there is a similar pair of ECC-based/raw functions for writing). + * + * Since MTD assumes the OOB is not covered by ECC, there is no pair of + * ECC-based/raw functions for reading or or writing the OOB. The fact that the + * caller wants an ECC-based or raw view of the page is not propagated down to + * this driver. + * + * Since our OOB *is* covered by ECC, we need this information. So, we hook the + * ecc.read_oob and ecc.write_oob function pointers in the owning + * struct mtd_info with our own functions. These hook functions set the + * raw_oob_mode field so that, when control finally arrives here, we'll know + * what to do. + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @page: The page number to read. + * @sndcmd: Indicates this function should send a command to the chip before + * reading the out-of-band bytes. This is only false for small page + * chips that support auto-increment. + */ +static int mil_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand, + int page, int sndcmd) +{ + struct gpmi_nfc_data *this = nand->priv; + struct physical_geometry *physical = &this->physical_geometry; + struct mil *mil = &this->mil; + struct boot_rom_helper *rom = this->rom; + int block_mark_column; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_read_oob] " + "page: 0x%06x, sndcmd: %s\n", page, sndcmd ? "Yes" : "No"); + + gpmi_nfc_add_event("> mil_ecc_read_oob", 1); + + /* + * First, fill in the OOB buffer. If we're doing a raw read, we need to + * get the bytes from the physical page. If we're not doing a raw read, + * we need to fill the buffer with set bits. + */ + + if (mil->raw_oob_mode) { + + /* + * If control arrives here, we're doing a "raw" read. Send the + * command to read the conventional OOB. + */ + + nand->cmdfunc(mtd, NAND_CMD_READ0, + physical->page_data_size_in_bytes, page); + + /* Read out the conventional OOB. */ + + nand->read_buf(mtd, nand->oob_poi, mtd->oobsize); + + } else { + + /* + * If control arrives here, we're not doing a "raw" read. Fill + * the OOB buffer with set bits. + */ + + memset(nand->oob_poi, ~0, mtd->oobsize); + + } + + /* + * Now, we want to make sure the block mark is correct. In the + * Swapping/Raw case, we already have it. Otherwise, we need to + * explicitly read it. + */ + + if (!(rom->swap_block_mark && mil->raw_oob_mode)) { + + /* First, figure out where the block mark is. */ + + if (rom->swap_block_mark) + block_mark_column = physical->page_data_size_in_bytes; + else + block_mark_column = 0; + + /* Send the command to read the block mark. */ + + nand->cmdfunc(mtd, NAND_CMD_READ0, block_mark_column, page); + + /* Read the block mark into the first byte of the OOB buffer. */ + + nand->oob_poi[0] = nand->read_byte(mtd); + + } + + /* + * Return true, indicating that the next call to this function must send + * a command. + */ + + gpmi_nfc_add_event("< mil_ecc_read_oob", -1); + + return true; + +} + +/** + * mil_ecc_write_oob() - MTD Interface ecc.write_oob(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @page: The page number to write. + */ +static int mil_ecc_write_oob(struct mtd_info *mtd, + struct nand_chip *nand, int page) +{ + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct physical_geometry *physical = &this->physical_geometry; + struct mil *mil = &this->mil; + struct boot_rom_helper *rom = this->rom; + uint8_t block_mark = 0; + int block_mark_column; + int status; + int error = 0; + + DEBUG(MTD_DEBUG_LEVEL2, + "[gpmi_nfc ecc_write_oob] page: 0x%06x\n", page); + + gpmi_nfc_add_event("> mil_ecc_write_oob", -1); + + /* + * There are fundamental incompatibilities between the i.MX GPMI NFC and + * the NAND Flash MTD model that make it essentially impossible to write + * the out-of-band bytes. + * + * We permit *ONE* exception. If the *intent* of writing the OOB is to + * mark a block bad, we can do that. + */ + + if (!mil->marking_a_bad_block) { + dev_emerg(dev, "This driver doesn't support writing the OOB\n"); + WARN_ON(1); + error = -EIO; + goto exit; + } + + /* + * If control arrives here, we're marking a block bad. First, figure out + * where the block mark is. + * + * If we're using swapping, the block mark is in the conventional + * location. Otherwise, we're using transcription, and the block mark + * appears in the first byte of the page. + */ + + if (rom->swap_block_mark) + block_mark_column = physical->page_data_size_in_bytes; + else + block_mark_column = 0; + + /* Write the block mark. */ + + nand->cmdfunc(mtd, NAND_CMD_SEQIN, block_mark_column, page); + nand->write_buf(mtd, &block_mark, 1); + nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + + status = nand->waitfunc(mtd, nand); + + /* Check if it worked. */ + + if (status & NAND_STATUS_FAIL) + error = -EIO; + + /* Return. */ + +exit: + + gpmi_nfc_add_event("< mil_ecc_write_oob", -1); + + return error; + +} + +/** + * mil_block_bad - Claims all blocks are good. + * + * In principle, this function is *only* called when the NAND Flash MTD system + * isn't allowed to keep an in-memory bad block table, so it is forced to ask + * the driver for bad block information. + * + * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so + * this function is *only* called when we take it away. + * + * We take away the in-memory BBT when the user sets the "ignorebad" parameter, + * which indicates that all blocks should be reported good. + * + * Thus, this function is only called when we want *all* blocks to look good, + * so it *always* return success. + * + * @mtd: Ignored. + * @ofs: Ignored. + * @getchip: Ignored. + */ +static int mil_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + return 0; +} + +/** + * mil_set_physical_geometry() - Set up the physical medium geometry. + * + * This function retrieves the physical geometry information discovered by + * nand_scan(), corrects it, and records it in the per-device data structure. + * + * @this: Per-device data. + */ +static int mil_set_physical_geometry(struct gpmi_nfc_data *this) +{ + struct mil *mil = &this->mil; + struct physical_geometry *physical = &this->physical_geometry; + struct nand_chip *nand = &mil->nand; + struct nand_device_info *info = &this->device_info; + unsigned int block_size_in_pages; + unsigned int chip_size_in_blocks; + unsigned int chip_size_in_pages; + uint64_t medium_size_in_bytes; + + /* + * Record the number of physical chips that MTD found. + */ + + physical->chip_count = nand->numchips; + + /* + * We know the total size of a page. We need to break that down into the + * data size and OOB size. The data size is the largest power of two + * that will fit in the given page size. The OOB size is what's left + * over. + */ + + physical->page_data_size_in_bytes = + 1 << (fls(info->page_total_size_in_bytes) - 1); + + physical->page_oob_size_in_bytes = + info->page_total_size_in_bytes - + physical->page_data_size_in_bytes; + + /* + * Now that we know the page data size, we can multiply this by the + * number of pages in a block to compute the block size. + */ + + physical->block_size_in_bytes = + physical->page_data_size_in_bytes * info->block_size_in_pages; + + /* Get the chip size. */ + + physical->chip_size_in_bytes = info->chip_size_in_bytes; + + /* Compute some interesting facts. */ + + block_size_in_pages = + physical->block_size_in_bytes >> + (fls(physical->page_data_size_in_bytes) - 1); + chip_size_in_pages = + physical->chip_size_in_bytes >> + (fls(physical->page_data_size_in_bytes) - 1); + chip_size_in_blocks = + physical->chip_size_in_bytes >> + (fls(physical->block_size_in_bytes) - 1); + medium_size_in_bytes = + physical->chip_size_in_bytes * physical->chip_count; + + /* Report. */ + + #if defined(DETAILED_INFO) + + pr_info("-----------------\n"); + pr_info("Physical Geometry\n"); + pr_info("-----------------\n"); + pr_info("Chip Count : %d\n", physical->chip_count); + pr_info("Page Data Size in Bytes: %u (0x%x)\n", + physical->page_data_size_in_bytes, + physical->page_data_size_in_bytes); + pr_info("Page OOB Size in Bytes : %u\n", + physical->page_oob_size_in_bytes); + pr_info("Block Size in Bytes : %u (0x%x)\n", + physical->block_size_in_bytes, + physical->block_size_in_bytes); + pr_info("Block Size in Pages : %u (0x%x)\n", + block_size_in_pages, + block_size_in_pages); + pr_info("Chip Size in Bytes : %llu (0x%llx)\n", + physical->chip_size_in_bytes, + physical->chip_size_in_bytes); + pr_info("Chip Size in Pages : %u (0x%x)\n", + chip_size_in_pages, chip_size_in_pages); + pr_info("Chip Size in Blocks : %u (0x%x)\n", + chip_size_in_blocks, chip_size_in_blocks); + pr_info("Medium Size in Bytes : %llu (0x%llx)\n", + medium_size_in_bytes, medium_size_in_bytes); + + #endif + + /* Return success. */ + + return 0; + +} + +/** + * mil_set_nfc_geometry() - Set up the NFC geometry. + * + * This function calls the NFC HAL to select an NFC geometry that is compatible + * with the medium's physical geometry. + * + * @this: Per-device data. + */ +static int mil_set_nfc_geometry(struct gpmi_nfc_data *this) +{ + struct nfc_hal *nfc = this->nfc; +#if defined(DETAILED_INFO) + struct nfc_geometry *geo = &this->nfc_geometry; +#endif + /* Set the NFC geometry. */ + + if (nfc->set_geometry(this)) + return !0; + + /* Report. */ + + #if defined(DETAILED_INFO) + + pr_info("------------\n"); + pr_info("NFC Geometry\n"); + pr_info("------------\n"); + pr_info("ECC Algorithm : %s\n", geo->ecc_algorithm); + pr_info("ECC Strength : %u\n", geo->ecc_strength); + pr_info("Page Size in Bytes : %u\n", geo->page_size_in_bytes); + pr_info("Metadata Size in Bytes : %u\n", geo->metadata_size_in_bytes); + pr_info("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size_in_bytes); + pr_info("ECC Chunk Count : %u\n", geo->ecc_chunk_count); + pr_info("Payload Size in Bytes : %u\n", geo->payload_size_in_bytes); + pr_info("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size_in_bytes); + pr_info("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset); + pr_info("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset); + pr_info("Block Mark Bit Offset : %u\n", geo->block_mark_bit_offset); + + #endif + + /* Return success. */ + + return 0; + +} + +/** + * mil_set_boot_rom_helper_geometry() - Set up the Boot ROM Helper geometry. + * + * @this: Per-device data. + */ +static int mil_set_boot_rom_helper_geometry(struct gpmi_nfc_data *this) +{ + struct boot_rom_helper *rom = this->rom; +#if defined(DETAILED_INFO) + struct boot_rom_geometry *geo = &this->rom_geometry; +#endif + + /* Set the Boot ROM Helper geometry. */ + + if (rom->set_geometry(this)) + return !0; + + /* Report. */ + + #if defined(DETAILED_INFO) + + pr_info("-----------------\n"); + pr_info("Boot ROM Geometry\n"); + pr_info("-----------------\n"); + pr_info("Boot Area Count : %u\n", geo->boot_area_count); + pr_info("Boot Area Size in Bytes : %u (0x%x)\n", + geo->boot_area_size_in_bytes, geo->boot_area_size_in_bytes); + pr_info("Stride Size in Pages : %u\n", geo->stride_size_in_pages); + pr_info("Search Area Stride Exponent: %u\n", + geo->search_area_stride_exponent); + + #endif + + /* Return success. */ + + return 0; + +} + +/** + * mil_set_mtd_geometry() - Set up the MTD geometry. + * + * This function adjusts the owning MTD data structures to match the logical + * geometry we've chosen. + * + * @this: Per-device data. + */ +static int mil_set_mtd_geometry(struct gpmi_nfc_data *this) +{ + struct physical_geometry *physical = &this->physical_geometry; + struct mil *mil = &this->mil; + struct nand_ecclayout *layout = &mil->oob_layout; + struct nand_chip *nand = &mil->nand; + struct mtd_info *mtd = &mil->mtd; + + /* Configure the struct nand_ecclayout. */ + + layout->eccbytes = 0; + layout->oobavail = physical->page_oob_size_in_bytes; + layout->oobfree[0].offset = 0; + layout->oobfree[0].length = physical->page_oob_size_in_bytes; + + /* Configure the struct mtd_info. */ + + mtd->size = nand->numchips * physical->chip_size_in_bytes; + mtd->erasesize = physical->block_size_in_bytes; + mtd->writesize = physical->page_data_size_in_bytes; + mtd->ecclayout = layout; + mtd->oobavail = mtd->ecclayout->oobavail; + mtd->oobsize = mtd->ecclayout->oobavail + mtd->ecclayout->eccbytes; + mtd->subpage_sft = 0; /* We don't support sub-page writing. */ + + /* Configure the struct nand_chip. */ + + nand->chipsize = physical->chip_size_in_bytes; + nand->page_shift = ffs(mtd->writesize) - 1; + nand->pagemask = (nand->chipsize >> nand->page_shift) - 1; + nand->subpagesize = mtd->writesize >> mtd->subpage_sft; + nand->phys_erase_shift = ffs(mtd->erasesize) - 1; + nand->bbt_erase_shift = nand->phys_erase_shift; + nand->oob_poi = nand->buffers->databuf + mtd->writesize; + nand->ecc.layout = layout; + if (nand->chipsize & 0xffffffff) + nand->chip_shift = ffs((unsigned) nand->chipsize) - 1; + else + nand->chip_shift = + ffs((unsigned) (nand->chipsize >> 32)) + 32 - 1; + + /* Return success. */ + + return 0; + +} + +/** + * mil_set_geometry() - Set up the medium geometry. + * + * @this: Per-device data. + */ +static int mil_set_geometry(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mil *mil = &this->mil; + + + /* Free the memory for read ID case */ + if (mil->page_buffer_virt && virt_addr_valid(mil->page_buffer_virt)) + dma_free_coherent(dev, nfc_geo->payload_size_in_bytes, + mil->page_buffer_virt, mil->page_buffer_phys); + + /* Set up the various layers of geometry, in this specific order. */ + + if (mil_set_physical_geometry(this)) + return -ENXIO; + + if (mil_set_nfc_geometry(this)) + return -ENXIO; + + if (mil_set_boot_rom_helper_geometry(this)) + return -ENXIO; + + if (mil_set_mtd_geometry(this)) + return -ENXIO; + + /* + * Allocate the page buffer. + * + * Both the payload buffer and the auxiliary buffer must appear on + * 32-bit boundaries. We presume the size of the payload buffer is a + * power of two and is much larger than four, which guarantees the + * auxiliary buffer will appear on a 32-bit boundary. + */ + + mil->page_buffer_size = nfc_geo->payload_size_in_bytes + + nfc_geo->auxiliary_size_in_bytes; + + mil->page_buffer_virt = + dma_alloc_coherent(dev, mil->page_buffer_size, + &mil->page_buffer_phys, GFP_DMA); + + if (!mil->page_buffer_virt) + return -ENOMEM; + + /* Slice up the page buffer. */ + + mil->payload_virt = mil->page_buffer_virt; + mil->payload_phys = mil->page_buffer_phys; + + mil->auxiliary_virt = ((char *) mil->payload_virt) + + nfc_geo->payload_size_in_bytes; + mil->auxiliary_phys = mil->payload_phys + + nfc_geo->payload_size_in_bytes; + + /* Return success. */ + + return 0; + +} + +/** + * mil_pre_bbt_scan() - Prepare for the BBT scan. + * + * @this: Per-device data. + */ +static int mil_pre_bbt_scan(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct physical_geometry *physical = &this->physical_geometry; + struct boot_rom_helper *rom = this->rom; + struct mil *mil = &this->mil; + struct nand_chip *nand = &mil->nand; + struct mtd_info *mtd = &mil->mtd; + unsigned int block_count; + unsigned int block; + int chip; + int page; + loff_t byte; + uint8_t block_mark; + int error; + + /* + * Check if we can use block mark swapping, which enables us to leave + * the block marks where they are. If so, we don't need to do anything + * at all. + */ + + if (rom->swap_block_mark) + return 0; + + /* + * If control arrives here, we can't use block mark swapping, which + * means we're forced to use transcription. First, scan for the + * transcription stamp. If we find it, then we don't have to do + * anything -- the block marks are already transcribed. + */ + + if (rom->check_transcription_stamp(this)) + return 0; + + /* + * If control arrives here, we couldn't find a transcription stamp, so + * so we presume the block marks are in the conventional location. + */ + + pr_info("Transcribing bad block marks...\n"); + + /* Compute the number of blocks in the entire medium. */ + + block_count = + physical->chip_size_in_bytes >> nand->phys_erase_shift; + + /* + * Loop over all the blocks in the medium, transcribing block marks as + * we go. + */ + + for (block = 0; block < block_count; block++) { + + /* + * Compute the chip, page and byte addresses for this block's + * conventional mark. + */ + + chip = block >> (nand->chip_shift - nand->phys_erase_shift); + page = block << (nand->phys_erase_shift - nand->page_shift); + byte = block << nand->phys_erase_shift; + + /* Select the chip. */ + + nand->select_chip(mtd, chip); + + /* Send the command to read the conventional block mark. */ + + nand->cmdfunc(mtd, NAND_CMD_READ0, + physical->page_data_size_in_bytes, page); + + /* Read the conventional block mark. */ + + block_mark = nand->read_byte(mtd); + + /* + * Check if the block is marked bad. If so, we need to mark it + * again, but this time the result will be a mark in the + * location where we transcribe block marks. + * + * Notice that we have to explicitly set the marking_a_bad_block + * member before we call through the block_markbad function + * pointer in the owning struct nand_chip. If we could call + * though the block_markbad function pointer in the owning + * struct mtd_info, which we have hooked, then this would be + * taken care of for us. Unfortunately, we can't because that + * higher-level code path will do things like consulting the + * in-memory bad block table -- which doesn't even exist yet! + * So, we have to call at a lower level and handle some details + * ourselves. + */ + + if (block_mark != 0xff) { + pr_info("Transcribing mark in block %u\n", block); + mil->marking_a_bad_block = true; + error = nand->block_markbad(mtd, byte); + mil->marking_a_bad_block = false; + if (error) + dev_err(dev, "Failed to mark block bad with " + "error %d\n", error); + } + + /* Deselect the chip. */ + + nand->select_chip(mtd, -1); + + } + + /* Write the stamp that indicates we've transcribed the block marks. */ + + rom->write_transcription_stamp(this); + + /* Return success. */ + + return 0; + +} + +/** + * mil_scan_bbt() - MTD Interface scan_bbt(). + * + * The HIL calls this function once, when it initializes the NAND Flash MTD. + * + * Nominally, the purpose of this function is to look for or create the bad + * block table. In fact, since the HIL calls this function at the very end of + * the initialization process started by nand_scan(), and the HIL doesn't have a + * more formal mechanism, everyone "hooks" this function to continue the + * initialization process. + * + * At this point, the physical NAND Flash chips have been identified and + * counted, so we know the physical geometry. This enables us to make some + * important configuration decisions. + * + * The return value of this function propogates directly back to this driver's + * call to nand_scan(). Anything other than zero will cause this driver to + * tear everything down and declare failure. + * + * @mtd: A pointer to the owning MTD. + */ +static int mil_scan_bbt(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + struct nfc_hal *nfc = this->nfc; + struct mil *mil = &this->mil; + int saved_chip_number; + uint8_t id_bytes[NAND_DEVICE_ID_BYTE_COUNT]; + struct nand_device_info *info; + struct gpmi_nfc_timing timing; + int error; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc scan_bbt] \n"); + + /* + * Tell MTD users that the out-of-band area can't be written. + * + * This flag is not part of the standard kernel source tree. It comes + * from a patch that touches both MTD and JFFS2. + * + * The problem is that, without this patch, JFFS2 believes it can write + * the data area and the out-of-band area separately. This is wrong for + * two reasons: + * + * 1) Our NFC distributes out-of-band bytes throughout the page, + * intermingled with the data, and covered by the same ECC. + * Thus, it's not possible to write the out-of-band bytes and + * data bytes separately. + * + * 2) Large page (MLC) Flash chips don't support partial page + * writes. You must write the entire page at a time. Thus, even + * if our NFC didn't force you to write out-of-band and data + * bytes together, it would *still* be a bad idea to do + * otherwise. + */ + + mtd->flags &= ~MTD_OOB_WRITEABLE; + + /* + * MTD identified the attached NAND Flash devices, but we have a much + * better database that we want to consult. First, we need to gather all + * the ID bytes from the first chip (MTD only read the first two). + */ + + saved_chip_number = mil->current_chip; + nand->select_chip(mtd, 0); + + nand->cmdfunc(mtd, NAND_CMD_READID, 0, -1); + nand->read_buf(mtd, id_bytes, NAND_DEVICE_ID_BYTE_COUNT); + + nand->select_chip(mtd, saved_chip_number); + + /* Look up this device in our database. */ + + info = nand_device_get_info(id_bytes); + + /* Check if we understand this device. */ + + if (!info) { + pr_err("Unrecognized NAND Flash device.\n"); + return !0; + } + + /* Display the information we discovered. */ + + #if defined(DETAILED_INFO) + pr_info("-----------------------------\n"); + pr_info("NAND Flash Device Information\n"); + pr_info("-----------------------------\n"); + nand_device_print_info(info); + #endif + + /* + * Copy the device info into the per-device data. We can't just keep + * the pointer because that storage is reclaimed after initialization. + */ + + this->device_info = *info; + this->device_info.description = kstrdup(info->description, GFP_KERNEL); + + /* Set up geometry. */ + + error = mil_set_geometry(this); + + if (error) + return error; + + /* Set up timing. */ + + timing.data_setup_in_ns = info->data_setup_in_ns; + timing.data_hold_in_ns = info->data_hold_in_ns; + timing.address_setup_in_ns = info->address_setup_in_ns; + timing.gpmi_sample_delay_in_ns = info->gpmi_sample_delay_in_ns; + timing.tREA_in_ns = info->tREA_in_ns; + timing.tRLOH_in_ns = info->tRLOH_in_ns; + timing.tRHOH_in_ns = info->tRHOH_in_ns; + + error = nfc->set_timing(this, &timing); + + if (error) + return error; + + /* Prepare for the BBT scan. */ + + error = mil_pre_bbt_scan(this); + + if (error) + return error; + + /* We use the reference implementation for bad block management. */ + + error = nand_default_bbt(mtd); + + if (error) + return error; + + /* Return success. */ + + return 0; + +} + +/** + * mil_boot_areas_init() - Initializes boot areas. + * + * @this: Per-device data. + */ +static int mil_boot_areas_init(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct physical_geometry *physical = &this->physical_geometry; + struct boot_rom_geometry *rom = &this->rom_geometry; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + struct nand_chip *nand = &mil->nand; + int mtd_support_is_adequate; + unsigned int i; + struct mtd_partition partitions[4]; + struct mtd_info *search_mtd; + struct mtd_info *chip_0_remainder_mtd = 0; + struct mtd_info *medium_remainder_mtd = 0; + struct mtd_info *concatenate[2]; + + /* + * Here we declare the static strings we use to name partitions. We use + * static strings because, as of 2.6.31, the partitioning code *always* + * registers the partition MTDs it creates and leaves behind *no* other + * trace of its work. So, once we've created a partition, we must search + * the master MTD table to find the MTDs we created. Since we're using + * static strings, we can simply search the master table for an MTD with + * a name field pointing to a known address. + */ + + static char *chip_0_boot_name = "gpmi-nfc-0-boot"; + static char *chip_0_remainder_name = "gpmi-nfc-0-remainder"; + static char *chip_1_boot_name = "gpmi-nfc-1-boot"; + static char *medium_remainder_name = "gpmi-nfc-remainder"; + static char *general_use_name = "gpmi-nfc-general-use"; + + /* Check if we're protecting the boot areas.*/ + + if (!rom->boot_area_count) { + + /* + * If control arrives here, we're not protecting the boot areas. + * In this case, there are not boot area partitons, and the main + * MTD is the general use MTD. + */ + + mil->general_use_mtd = &mil->mtd; + + return 0; + + } + + /* + * If control arrives here, we're protecting the boot areas. Check if we + * have the MTD support we need. + */ + + pr_info("Boot area protection is enabled.\n"); + + if (rom->boot_area_count > 1) { + + /* + * If the Boot ROM wants more than one boot area, then we'll + * need to create partitions *and* concatenate them. + */ + + #if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT) + mtd_support_is_adequate = true; + #else + mtd_support_is_adequate = false; + #endif + + } else if (rom->boot_area_count == 1) { + + /* + * If the Boot ROM wants only one boot area, then we only need + * to create partitions -- we don't need to concatenate them. + */ + + #if defined(CONFIG_MTD_PARTITIONS) + mtd_support_is_adequate = true; + #else + mtd_support_is_adequate = false; + #endif + + } else { + + /* + * If control arrives here, we're protecting the boot area, but + * somehow the boot area count was set to zero. This doesn't + * make any sense. + */ + + dev_err(dev, "Internal error: boot area count is " + "incorrectly set to zero."); + return -ENXIO; + + } + + if (!mtd_support_is_adequate) { + dev_err(dev, "Configured MTD support is inadequate to " + "protect the boot area(s)."); + return -ENXIO; + } + + /* + * If control arrives here, we're protecting boot areas and we have + * everything we need to do so. + * + * We have special code to handle the case for one boot area. + * + * The code that handles "more than one" boot area actually only handles + * two. We *could* write the general case, but that would take a lot of + * time to both write and test -- and, right now, we don't have a chip + * that cares. + */ + + /* Check if a boot area is larger than a single chip. */ + + if (rom->boot_area_size_in_bytes > physical->chip_size_in_bytes) { + dev_emerg(dev, "Boot area size is larger than a chip"); + return -ENXIO; + } + + if (rom->boot_area_count == 1) { + +#if defined(CONFIG_MTD_PARTITIONS) + + /* + * We partition the medium like so: + * + * +------+----------------------------------------------------+ + * | Boot | General Use | + * +------+----------------------------------------------------+ + */ + + /* Chip 0 Boot */ + + partitions[0].name = chip_0_boot_name; + partitions[0].offset = 0; + partitions[0].size = rom->boot_area_size_in_bytes; + partitions[0].mask_flags = 0; + + /* General Use */ + + partitions[1].name = general_use_name; + partitions[1].offset = rom->boot_area_size_in_bytes; + partitions[1].size = MTDPART_SIZ_FULL; + partitions[1].mask_flags = 0; + + /* Construct and register the partitions. */ + + add_mtd_partitions(mtd, partitions, 2); + + /* Find the general use MTD. */ + + for (i = 0; i < MAX_MTD_DEVICES; i++) { + + /* Get the current MTD so we can examine it. */ + + search_mtd = get_mtd_device(0, i); + + /* Check if we got nonsense. */ + + if ((!search_mtd) || (search_mtd == ERR_PTR(-ENODEV))) + continue; + + /* Check if the current MTD is one of our remainders. */ + + if (search_mtd->name == general_use_name) + mil->general_use_mtd = search_mtd; + + /* Put the MTD back. We only wanted a quick look. */ + + put_mtd_device(search_mtd); + + } + + if (!mil->general_use_mtd) { + dev_emerg(dev, "Can't find general use MTD"); + BUG(); + } + +#endif + + } else if (rom->boot_area_count == 2) { + +#if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT) + + /* + * If control arrives here, there is more than one boot area. + * We partition the medium and concatenate the remainders like + * so: + * + * --- Chip 0 --- --- Chip 1 --- ... ------- Chip N ------- + * / \ / \ + * +----+----------+----+--------------- ... ------------------+ + * |Boot|Remainder |Boot| Remainder | + * +----+----------+----+--------------- ... ------------------+ + * | | / / + * | | / / + * | | / / + * | |/ / + * +----------+----------- ... ----------------------+ + * | General Use | + * +---------------------- ... ----------------------+ + * + * Notice that the results we leave in the master MTD table + * look like this: + * + * * Chip 0 Boot Area + * * Chip 1 Boot Area + * * General Use + * + * Some user space programs expect the boot partitions to + * appear first. This is naive, but let's try not to cause + * any trouble, where we can avoid it. + */ + + /* Chip 0 Boot */ + + partitions[0].name = chip_0_boot_name; + partitions[0].offset = 0; + partitions[0].size = rom->boot_area_size_in_bytes; + partitions[0].mask_flags = 0; + + /* Chip 1 Boot */ + + partitions[1].name = chip_1_boot_name; + partitions[1].offset = nand->chipsize; + partitions[1].size = rom->boot_area_size_in_bytes; + partitions[1].mask_flags = 0; + + /* Chip 0 Remainder */ + + partitions[2].name = chip_0_remainder_name; + partitions[2].offset = rom->boot_area_size_in_bytes; + partitions[2].size = nand->chipsize - + rom->boot_area_size_in_bytes; + partitions[2].mask_flags = 0; + + /* Medium Remainder */ + + partitions[3].name = medium_remainder_name; + partitions[3].offset = nand->chipsize + + rom->boot_area_size_in_bytes; + partitions[3].size = MTDPART_SIZ_FULL; + partitions[3].mask_flags = 0; + + /* Construct and register the partitions. */ + + add_mtd_partitions(mtd, partitions, 4); + + /* Find the remainder partitions. */ + + for (i = 0; i < MAX_MTD_DEVICES; i++) { + + /* Get the current MTD so we can examine it. */ + + search_mtd = get_mtd_device(0, i); + + /* Check if we got nonsense. */ + + if ((!search_mtd) || (search_mtd == ERR_PTR(-ENODEV))) + continue; + + /* Check if the current MTD is one of our remainders. */ + + if (search_mtd->name == chip_0_remainder_name) + chip_0_remainder_mtd = search_mtd; + + if (search_mtd->name == medium_remainder_name) + medium_remainder_mtd = search_mtd; + + /* Put the MTD back. We only wanted a quick look. */ + + put_mtd_device(search_mtd); + + } + + if (!chip_0_remainder_mtd || !medium_remainder_mtd) { + dev_emerg(dev, "Can't find remainder partitions"); + BUG(); + } + + /* + * Unregister the remainder MTDs. Note that we are *not* + * destroying these MTDs -- we're just removing from the + * globally-visible list. There's no need for anyone to see + * these. + */ + + del_mtd_device(chip_0_remainder_mtd); + del_mtd_device(medium_remainder_mtd); + + /* Concatenate the remainders and register the result. */ + + concatenate[0] = chip_0_remainder_mtd; + concatenate[1] = medium_remainder_mtd; + + mil->general_use_mtd = mtd_concat_create(concatenate, + 2, general_use_name); + + add_mtd_device(mil->general_use_mtd); + +#endif + + } else { + dev_err(dev, "Boot area count greater than two is " + "unimplemented.\n"); + return -ENXIO; + } + + /* Return success. */ + + return 0; + +} + +/** + * mil_boot_areas_exit() - Shuts down boot areas. + * + * @this: Per-device data. + */ +static void mil_boot_areas_exit(struct gpmi_nfc_data *this) +{ + struct boot_rom_geometry *rom = &this->rom_geometry; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + + /* Check if we're protecting the boot areas.*/ + + if (!rom->boot_area_count) { + + /* + * If control arrives here, we're not protecting the boot areas. + * That means we never created any boot area partitions, and the + * general use MTD is just the main MTD. + */ + + mil->general_use_mtd = 0; + + return; + + } + + /* + * If control arrives here, we're protecting the boot areas. + * + * Start by checking if there is more than one boot area. If so, then + * we both partitioned the medium and then concatenated some of the + * partitions to form the general use MTD. The first step is to get rid + * of the concatenation. + */ + + #if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT) + if (rom->boot_area_count > 1) { + del_mtd_device(mil->general_use_mtd); + mtd_concat_destroy(mil->general_use_mtd); + } + #endif + + /* + * At this point, we're left only with the partitions of the main MTD. + * Delete them. + */ + + #if defined(CONFIG_MTD_PARTITIONS) + del_mtd_partitions(mtd); + #endif + + /* The general use MTD no longer exists. */ + + mil->general_use_mtd = 0; + +} + +/** + * mil_construct_ubi_partitions() - Constructs partitions for UBI. + * + * MTD uses a 64-bit value to express the size of MTDs, but UBI is still using + * a 32-bit value. For this reason, UBI can't work on top of an MTD with size + * greater than 2GiB. In this function, we examine the general use MTD and, if + * it's larger than 2GiB, we construct a set of partitions for that MTD such + * that none are too large for UBI to comprehend. + * + * @this: Per-device data. + */ +static void mil_construct_ubi_partitions(struct gpmi_nfc_data *this) +{ +#if defined(CONFIG_MTD_PARTITIONS) + struct device *dev = this->dev; + struct mil *mil = &this->mil; + unsigned int partition_count; + struct mtd_partition *partitions; + unsigned int name_size; + char *names; + unsigned int memory_block_size; + unsigned int i; + + static const char *name_prefix = "gpmi-nfc-ubi-"; + + /* + * If the general use MTD isn't larger than 2GiB, we have nothing to do. + */ + + if (mil->general_use_mtd->size <= SZ_2G) + return; + + /* + * If control arrives here, the general use MTD is larger than 2GiB. We + * need to split it up into some number of partitions. Find out how many + * 2GiB partitions we'll be creating. + */ + + partition_count = mil->general_use_mtd->size >> 31; + + /* + * If the MTD size doesn't evenly divide by 2GiB, we'll need another + * partition to hold the extra. + */ + + if (mil->general_use_mtd->size & ((1 << 30) - 1)) + partition_count++; + + /* + * We're going to allocate a single memory block to contain all the + * partition structures and their names. Calculate how large it must be. + */ + + name_size = strlen(name_prefix) + 4; + + memory_block_size = (sizeof(*partitions) + name_size) * partition_count; + + /* + * Attempt to allocate the block. + */ + + partitions = kzalloc(memory_block_size, GFP_KERNEL); + + if (!partitions) { + dev_err(dev, "Could not allocate memory for UBI partitions.\n"); + return; + } + + names = (char *)(partitions + partition_count); + + /* Loop over partitions, filling in the details. */ + + for (i = 0; i < partition_count; i++) { + + partitions[i].name = names; + partitions[i].size = SZ_2G; + partitions[i].offset = MTDPART_OFS_NXTBLK; + + sprintf(names, "%s%u", name_prefix, i); + names += name_size; + + } + + /* Adjust the last partition to take up the remainder. */ + + partitions[i - 1].size = MTDPART_SIZ_FULL; + + /* Record everything in the device data structure. */ + + mil->partitions = partitions; + mil->partition_count = partition_count; + mil->ubi_partition_memory = partitions; + +#endif +} + +/** + * mil_partitions_init() - Initializes partitions. + * + * @this: Per-device data. + */ +static int mil_partitions_init(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + int error; + + /* + * Set up the boot areas. When this function returns, if there has been + * no error, the boot area partitions (if any) will have been created + * and registered. Also, the general_use_mtd field will point to an MTD + * we can use. + */ + + error = mil_boot_areas_init(this); + + if (error) + return error; + + /* + * If we've been told to, register the MTD that represents the entire + * medium. Normally, we don't register the main MTD because we only want + * to expose the medium through the boot area partitions and the general + * use partition. + * + * We do this *after* setting up the boot areas because, for historical + * reasons, we like the lowest-numbered MTDs to be the boot areas. + */ + + if (register_main_mtd) { + pr_info("Registering the main MTD.\n"); + add_mtd_device(mtd); + } + +#if defined(CONFIG_MTD_PARTITIONS) + + /* + * If control arrives here, partitioning is available. + * + * There are three possible sets of partitions we might apply, in order + * of decreasing priority: + * + * 1) Partitions dynamically discovered from sources defined by the + * platform. These can come from, for example, the command line or + * a partition table. + * + * 2) Partitions attached to the platform data. + * + * 3) Partitions we generate to deal with limitations in UBI. + * + * Recall that the pointer to the general use MTD *may* just point to + * the main MTD. + */ + + /* + * First, try to get partition information from the sources defined by + * the platform. + */ + + if (pdata->partition_source_types) + mil->partition_count = + parse_mtd_partitions(mil->general_use_mtd, + pdata->partition_source_types, + &mil->partitions, 0); + + /* + * Check if we got anything. If not, then accept whatever partitions are + * attached to the platform data. + */ + + if ((mil->partition_count <= 0) && (pdata->partitions)) { + mil->partition_count = mil->partition_count; + mil->partitions = mil->partitions; + } + + /* + * If we still don't have any partitions to apply, then we might want to + * apply some of our own, to account for UBI's limitations. + */ + + if (!mil->partition_count) + mil_construct_ubi_partitions(this); + + /* If we came up with any partitions, apply them. */ + + if (mil->partition_count) + add_mtd_partitions(mil->general_use_mtd, + mil->partitions, + mil->partition_count); + +#endif + + /* Return success. */ + + return 0; + +} + +/** + * mil_partitions_exit() - Shuts down partitions. + * + * @this: Per-device data. + */ +static void mil_partitions_exit(struct gpmi_nfc_data *this) +{ + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + + /* Check if we applied any partitions to the general use MTD. */ + + #if defined(CONFIG_MTD_PARTITIONS) + + if (mil->partition_count) + del_mtd_partitions(mil->general_use_mtd); + + kfree(mil->ubi_partition_memory); + + #endif + + /* + * If we were told to register the MTD that represents the entire + * medium, unregister it now. Note that this does *not* "destroy" the + * MTD - it merely unregisters it. That's important because all our + * other MTDs depend on this one. + */ + + if (register_main_mtd) + del_mtd_device(mtd); + + /* Tear down the boot areas. */ + + mil_boot_areas_exit(this); + +} + +/** + * gpmi_nfc_mil_init() - Initializes the MTD Interface Layer. + * + * @this: Per-device data. + */ +int gpmi_nfc_mil_init(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + struct nand_chip *nand = &mil->nand; + static struct nand_ecclayout fake_ecc_layout; + int error = 0; + + /* Initialize MIL data. */ + + mil->current_chip = -1; + mil->command_length = 0; + + mil->page_buffer_virt = 0; + mil->page_buffer_phys = ~0; + mil->page_buffer_size = 0; + + /* Initialize the MTD data structures. */ + + mtd->priv = nand; + mtd->name = "gpmi-nfc-main"; + mtd->owner = THIS_MODULE; + nand->priv = this; + + /* + * Signal Control + */ + + nand->cmd_ctrl = mil_cmd_ctrl; + + /* + * Chip Control + * + * We rely on the reference implementations of: + * - cmdfunc + * - waitfunc + */ + + nand->dev_ready = mil_dev_ready; + nand->select_chip = mil_select_chip; + + /* + * Low-level I/O + * + * We don't support a 16-bit NAND Flash bus, so we don't implement + * read_word. + * + * We rely on the reference implentation of verify_buf. + */ + + nand->read_byte = mil_read_byte; + nand->read_buf = mil_read_buf; + nand->write_buf = mil_write_buf; + + /* + * ECC Control + * + * None of these functions are necessary for us: + * - ecc.hwctl + * - ecc.calculate + * - ecc.correct + */ + + /* + * ECC-aware I/O + * + * We rely on the reference implementations of: + * - ecc.read_page_raw + * - ecc.write_page_raw + */ + + nand->ecc.read_page = mil_ecc_read_page; + nand->ecc.write_page = mil_ecc_write_page; + + /* + * High-level I/O + * + * We rely on the reference implementations of: + * - write_page + * - erase_cmd + */ + + nand->ecc.read_oob = mil_ecc_read_oob; + nand->ecc.write_oob = mil_ecc_write_oob; + + /* + * Bad Block Management + * + * We rely on the reference implementations of: + * - block_bad + * - block_markbad + */ + + nand->block_bad = mil_block_bad; + nand->scan_bbt = mil_scan_bbt; + + /* + * Error Recovery Functions + * + * We don't fill in the errstat function pointer because it's optional + * and we don't have a need for it. + */ + + /* + * Set up NAND Flash options. Specifically: + * + * - Disallow partial page writes. + */ + + nand->options |= NAND_NO_SUBPAGE_WRITE; + + /* + * Tell the NAND Flash MTD system that we'll be handling ECC with our + * own hardware. It turns out that we still have to fill in the ECC size + * because the MTD code will divide by it -- even though it doesn't + * actually care. + */ + + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = 1; + + /* + * Install a "fake" ECC layout. + * + * We'll be calling nand_scan() to do the final MTD setup. If we haven't + * already chosen an ECC layout, then nand_scan() will choose one based + * on the part geometry it discovers. Unfortunately, it doesn't make + * good choices. It would be best if we could install the correct ECC + * layout now, before we call nand_scan(). We can't do that because we + * don't know the medium geometry yet. Here, we install a "fake" ECC + * layout just to stop nand_scan() from trying to pick one for itself. + * Later, when we know the medium geometry, we'll install the correct + * one. + * + * Of course, this tactic depends critically on the MTD code not doing + * an I/O operation that depends on the ECC layout being sensible. This + * is in fact the case. + */ + + memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout)); + + nand->ecc.layout = &fake_ecc_layout; + + /* Allocate a command buffer. */ + + mil->cmd_virt = + dma_alloc_coherent(dev, + MIL_COMMAND_BUFFER_SIZE, &mil->cmd_phys, GFP_DMA); + + if (!mil->cmd_virt) { + error = -ENOMEM; + goto exit_cmd_allocation; + } + + + /* Allocate buf read ID case */ + this->nfc_geometry.payload_size_in_bytes = 1024; + mil->page_buffer_virt = + dma_alloc_coherent(dev, + this->nfc_geometry.payload_size_in_bytes, + &mil->page_buffer_phys, GFP_DMA); + + if (!mil->page_buffer_virt) { + error = -ENOMEM; + goto exit_buf_allocation; + } + + /* Slice up the page buffer. */ + mil->payload_virt = mil->page_buffer_virt; + mil->payload_phys = mil->page_buffer_phys; + + /* + * Ask the NAND Flash system to scan for chips. + * + * This will fill in reference implementations for all the members of + * the MTD structures that we didn't set, and will make the medium fully + * usable. + */ + + pr_info("Scanning for NAND Flash chips...\n"); + + error = nand_scan(mtd, pdata->max_chip_count); + + if (error) { + dev_err(dev, "Chip scan failed\n"); + goto exit_nand_scan; + } + + /* + * Hook some operations at the MTD level. See the descriptions of the + * saved function pointer fields for details about why we hook these. + */ + + mil->hooked_read_oob = mtd->read_oob; + mtd->read_oob = mil_hook_read_oob; + + mil->hooked_write_oob = mtd->write_oob; + mtd->write_oob = mil_hook_write_oob; + + mil->hooked_block_markbad = mtd->block_markbad; + mtd->block_markbad = mil_hook_block_markbad; + + /* Construct partitions as necessary. */ + + error = mil_partitions_init(this); + + if (error) + goto exit_partitions; + + /* Return success. */ + + return 0; + + /* Control arrives here if something went wrong. */ + +exit_partitions: + nand_release(&mil->mtd); +exit_nand_scan: + dma_free_coherent(dev, + this->nfc_geometry.payload_size_in_bytes, + mil->page_buffer_virt, mil->page_buffer_phys); + mil->page_buffer_virt = 0; + mil->page_buffer_phys = ~0; +exit_buf_allocation: + dma_free_coherent(dev, MIL_COMMAND_BUFFER_SIZE, + mil->cmd_virt, mil->cmd_phys); + mil->cmd_virt = 0; + mil->cmd_phys = ~0; +exit_cmd_allocation: + + return error; + +} + +/** + * gpmi_nfc_mil_exit() - Shuts down the MTD Interface Layer. + * + * @this: Per-device data. + */ +void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct mil *mil = &this->mil; + + /* Shut down partitions as necessary. */ + + mil_partitions_exit(this); + + /* Get MTD to let go of our MTD. */ + + nand_release(&mil->mtd); + + /* Free the page buffer, if it's been allocated. */ + + if (mil->page_buffer_virt) + dma_free_coherent(dev, mil->page_buffer_size, + mil->page_buffer_virt, mil->page_buffer_phys); + + mil->page_buffer_size = 0; + mil->page_buffer_virt = 0; + mil->page_buffer_phys = ~0; + + /* Free the command buffer, if it's been allocated. */ + + if (mil->cmd_virt) + dma_free_coherent(dev, MIL_COMMAND_BUFFER_SIZE, + mil->cmd_virt, mil->cmd_phys); + + mil->cmd_virt = 0; + mil->cmd_phys = ~0; + +} diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c new file mode 100644 index 000000000000..0cd0b39141fd --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c @@ -0,0 +1,59 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +/** + * gpmi_nfc_rom_helper_set_geometry() - Sets geometry for the Boot ROM Helper. + * + * @this: Per-device data. + */ +int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this) +{ + struct boot_rom_geometry *geometry = &this->rom_geometry; + + /* + * Set the boot block stride size. + * + * In principle, we should be reading this from the OTP bits, since + * that's where the ROM is going to get it. In fact, we don't have any + * way to read the OTP bits, so we go with the default and hope for the + * best. + */ + + geometry->stride_size_in_pages = 64; + + /* + * Set the search area stride exponent. + * + * In principle, we should be reading this from the OTP bits, since + * that's where the ROM is going to get it. In fact, we don't have any + * way to read the OTP bits, so we go with the default and hope for the + * best. + */ + + geometry->search_area_stride_exponent = 2; + + /* Return success. */ + + return 0; + +} diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c new file mode 100644 index 000000000000..35321cc25546 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c @@ -0,0 +1,297 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +/* + * Useful variables for Boot ROM Helper version 0. + */ + +static const char *fingerprint = "STMP"; + +/** + * set_geometry() - Sets geometry for the Boot ROM Helper. + * + * @this: Per-device data. + */ +static int set_geometry(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct physical_geometry *physical = &this->physical_geometry; + struct boot_rom_geometry *geometry = &this->rom_geometry; + int error; + + /* Version-independent geometry. */ + + error = gpmi_nfc_rom_helper_set_geometry(this); + + if (error) + return error; + + /* + * Check if the platform data indicates we are to protect the boot area. + */ + + if (!pdata->boot_area_size_in_bytes) { + geometry->boot_area_count = 0; + geometry->boot_area_size_in_bytes = 0; + return 0; + } + + /* + * If control arrives here, we are supposed to set up partitions to + * protect the boot areas. In this version of the ROM, the number of + * boot areas and their size depends on the number of chips. + */ + + if (physical->chip_count == 1) { + geometry->boot_area_count = 1; + geometry->boot_area_size_in_bytes = + pdata->boot_area_size_in_bytes * 2; + } else { + geometry->boot_area_count = 2; + geometry->boot_area_size_in_bytes = + pdata->boot_area_size_in_bytes; + } + + /* Return success. */ + + return 0; + +} + +/** + * check_transcription_stamp() - Checks for a transcription stamp. + * + * Returns 0 if a stamp is not found. + * + * @this: Per-device data. + */ +static int check_transcription_stamp(struct gpmi_nfc_data *this) +{ + struct physical_geometry *physical = &this->physical_geometry; + struct boot_rom_geometry *rom_geo = &this->rom_geometry; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + struct nand_chip *nand = &mil->nand; + unsigned int search_area_size_in_strides; + unsigned int stride; + unsigned int page; + loff_t byte; + uint8_t *buffer = nand->buffers->databuf; + int saved_chip_number; + int found_an_ncb_fingerprint = false; + + /* Compute the number of strides in a search area. */ + + search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent; + + /* Select chip 0. */ + + saved_chip_number = mil->current_chip; + nand->select_chip(mtd, 0); + + /* + * Loop through the first search area, looking for the NCB fingerprint. + */ + + pr_info("Scanning for an NCB fingerprint...\n"); + + for (stride = 0; stride < search_area_size_in_strides; stride++) { + + /* Compute the page and byte addresses. */ + + page = stride * rom_geo->stride_size_in_pages; + byte = page * physical->page_data_size_in_bytes; + + pr_info(" Looking for a fingerprint in page 0x%x\n", page); + + /* + * Read the NCB fingerprint. The fingerprint is four bytes long + * and starts in the 12th byte of the page. + */ + + nand->cmdfunc(mtd, NAND_CMD_READ0, 12, page); + nand->read_buf(mtd, buffer, strlen(fingerprint)); + + /* Look for the fingerprint. */ + + if (!memcmp(buffer, fingerprint, + strlen(fingerprint))) { + found_an_ncb_fingerprint = true; + break; + } + + } + + /* Deselect chip 0. */ + + nand->select_chip(mtd, saved_chip_number); + + /* Return. */ + + if (found_an_ncb_fingerprint) + pr_info(" Found a fingerprint\n"); + else + pr_info(" No fingerprint found\n"); + + return found_an_ncb_fingerprint; + +} + +/** + * write_transcription_stamp() - Writes a transcription stamp. + * + * @this: Per-device data. + */ +static int write_transcription_stamp(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct physical_geometry *physical = &this->physical_geometry; + struct boot_rom_geometry *rom_geo = &this->rom_geometry; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + struct nand_chip *nand = &mil->nand; + unsigned int block_size_in_pages; + unsigned int search_area_size_in_strides; + unsigned int search_area_size_in_pages; + unsigned int search_area_size_in_blocks; + unsigned int block; + unsigned int stride; + unsigned int page; + loff_t byte; + uint8_t *buffer = nand->buffers->databuf; + int saved_chip_number; + int status; + + /* Compute the search area geometry. */ + + block_size_in_pages = physical->block_size_in_bytes >> + (ffs(physical->page_data_size_in_bytes) - 1); + + search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent; + + search_area_size_in_pages = search_area_size_in_strides * + rom_geo->stride_size_in_pages; + + search_area_size_in_blocks = + (search_area_size_in_pages + (block_size_in_pages - 1)) / + /*-------------------------------------------------------*/ + block_size_in_pages; + + #if defined(DETAILED_INFO) + + pr_info("--------------------\n"); + pr_info("Search Area Geometry\n"); + pr_info("--------------------\n"); + pr_info("Search Area Size in Blocks : %u", search_area_size_in_blocks); + pr_info("Search Area Size in Strides: %u", search_area_size_in_strides); + pr_info("Search Area Size in Pages : %u", search_area_size_in_pages); + + #endif + + /* Select chip 0. */ + + saved_chip_number = mil->current_chip; + nand->select_chip(mtd, 0); + + /* Loop over blocks in the first search area, erasing them. */ + + pr_info("Erasing the search area...\n"); + + for (block = 0; block < search_area_size_in_blocks; block++) { + + /* Compute the page address. */ + + page = block * block_size_in_pages; + + /* Erase this block. */ + + pr_info(" Erasing block 0x%x\n", block); + + nand->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); + nand->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); + + /* Wait for the erase to finish. */ + + status = nand->waitfunc(mtd, nand); + + if (status & NAND_STATUS_FAIL) + dev_err(dev, "[%s] Erase failed.\n", __func__); + + } + + /* Write the NCB fingerprint into the page buffer. */ + + memset(buffer, ~0, mtd->writesize); + memset(nand->oob_poi, ~0, mtd->oobsize); + + memcpy(buffer + 12, fingerprint, strlen(fingerprint)); + + /* Loop through the first search area, writing NCB fingerprints. */ + + pr_info("Writing NCB fingerprints...\n"); + + for (stride = 0; stride < search_area_size_in_strides; stride++) { + + /* Compute the page and byte addresses. */ + + page = stride * rom_geo->stride_size_in_pages; + byte = page * physical->page_data_size_in_bytes; + + /* Write the first page of the current stride. */ + + pr_info(" Writing an NCB fingerprint in page 0x%x\n", page); + + nand->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); + nand->ecc.write_page_raw(mtd, nand, buffer); + nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + + /* Wait for the write to finish. */ + + status = nand->waitfunc(mtd, nand); + + if (status & NAND_STATUS_FAIL) + dev_err(dev, "[%s] Write failed.\n", __func__); + + } + + /* Deselect chip 0. */ + + nand->select_chip(mtd, saved_chip_number); + + /* Return success. */ + + return 0; + +} + +/* This structure represents the Boot ROM Helper for this version. */ + +struct boot_rom_helper gpmi_nfc_boot_rom_helper_v0 = { + .version = 0, + .description = "Single/dual-chip boot area, " + "no block mark swapping", + .swap_block_mark = false, + .set_geometry = set_geometry, + .check_transcription_stamp = check_transcription_stamp, + .write_transcription_stamp = write_transcription_stamp, +}; diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c new file mode 100644 index 000000000000..49cb329ccdd4 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c @@ -0,0 +1,82 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +/** + * set_geometry() - Sets geometry for the Boot ROM Helper. + * + * @this: Per-device data. + */ +static int set_geometry(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct boot_rom_geometry *geometry = &this->rom_geometry; + int error; + + /* Version-independent geometry. */ + + error = gpmi_nfc_rom_helper_set_geometry(this); + + if (error) + return error; + + /* + * Check if the platform data indicates we are to protect the boot area. + */ + + if (!pdata->boot_area_size_in_bytes) { + geometry->boot_area_count = 0; + geometry->boot_area_size_in_bytes = 0; + return 0; + } + + /* + * If control arrives here, we are supposed to set up partitions to + * protect the boot areas. In this version of the ROM, we support only + * one boot area. + */ + + geometry->boot_area_count = 1; + + /* + * Use the platform's boot area size. + */ + + geometry->boot_area_size_in_bytes = pdata->boot_area_size_in_bytes; + + /* Return success. */ + + return 0; + +} + +/* This structure represents the Boot ROM Helper for this version. */ + +struct boot_rom_helper gpmi_nfc_boot_rom_helper_v1 = { + .version = 1, + .description = "Single-chip boot area, " + "block mark swapping supported", + .swap_block_mark = true, + .set_geometry = set_geometry, + .check_transcription_stamp = 0, + .write_transcription_stamp = 0, +}; diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h new file mode 100644 index 000000000000..9b0074532917 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h @@ -0,0 +1,645 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __DRIVERS_MTD_NAND_GPMI_NFC_H +#define __DRIVERS_MTD_NAND_GPMI_NFC_H + +/* Linux header files. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Platform header files. */ + +#include +#include +#include + +/* Driver header files. */ + +#include "../nand_device_info.h" + +/* + *------------------------------------------------------------------------------ + * Fundamental Macros + *------------------------------------------------------------------------------ + */ + +/* Define this macro to enable detailed information messages. */ + +#define DETAILED_INFO + +/* Define this macro to enable event reporting. */ + +/*#define EVENT_REPORTING*/ + +/* + *------------------------------------------------------------------------------ + * Fundamental Data Structures + *------------------------------------------------------------------------------ + */ + +/** + * struct resources - The collection of resources the driver needs. + * + * @gpmi_regs: A pointer to the GPMI registers. + * @bch_regs: A pointer to the BCH registers. + * @bch_interrupt: The BCH interrupt number. + * @dma_low_channel: The low DMA channel. + * @dma_high_channel: The high DMA channel. + * @dma_interrupt: The DMA interrupt number. + * @clock: A pointer to the struct clk for the NFC's clock. + */ + +struct resources { + void *gpmi_regs; + void *bch_regs; + unsigned int bch_low_interrupt; + unsigned int bch_high_interrupt; + unsigned int dma_low_channel; + unsigned int dma_high_channel; + unsigned int dma_low_interrupt; + unsigned int dma_high_interrupt; + struct clk *clock; +}; + +/** + * struct mil - State for the MTD Interface Layer. + * + * @nand: The NAND Flash MTD data structure that represents + * the NAND Flash medium. + * @mtd: The MTD data structure that represents the NAND + * Flash medium. + * @oob_layout: A structure that describes how bytes are laid out + * in the OOB. + * @general_use_mtd: A pointer to an MTD we export for general use. + * This *may* simply be a pointer to the mtd field, if + * we've been instructed NOT to protect the boot + * areas. + * @partitions: A pointer to a set of partitions applied to the + * general use MTD. + * @partition_count: The number of partitions. + * @ubi_partition_memory: If not NULL, a block of memory used to create a set + * of partitions that help with the problem that UBI + * can't handle an MTD larger than 2GiB. + * @current_chip: The chip currently selected by the NAND Fash MTD + * code. A negative value indicates that no chip is + * selected. + * @command_length: The length of the command that appears in the + * command buffer (see cmd_virt, below). + * @inject_ecc_error: Indicates the driver should inject a "fake" ECC + * error into the next read operation that uses ECC. + * User space programs can set this value through the + * sysfs node of the same name. If this value is less + * than zero, the driver will inject an uncorrectable + * ECC error. If this value is greater than zero, the + * driver will inject that number of correctable + * errors, capped by the maximum possible number of + * errors that could appear in a single read. + * @ignore_bad_block_marks: Indicates we are ignoring bad block marks. + * @saved_bbt: A saved pointer to the in-memory NAND Flash MTD bad + * block table. See show_device_ignorebad() for more + * details. + * @raw_oob_mode: Indicates the OOB is to be read/written in "raw" + * mode. See mil_ecc_read_oob() for details. + * @hooked_read_oob: A pointer to the ecc.read_oob() function we + * "hooked." See mil_ecc_read_oob() for details. + * @hooked_write_oob: A pointer to the ecc.write_oob() function pointer + * we "hooked." See mil_ecc_read_oob() for details. + * @marking_a_bad_block: Indicates the caller is marking a bad block. See + * mil_ecc_write_oob() for details. + * @hooked_block_markbad: A pointer to the block_markbad() function we + * we "hooked." See mil_ecc_write_oob() for details. + * @cmd_virt: A pointer to a DMA-coherent buffer in which we + * accumulate command bytes before we give them to the + * NFC layer. See mil_cmd_ctrl() for more details. + * @cmd_phys: The physical address for the cmd_virt buffer. + * @page_buffer_virt: A pointer to a DMA-coherent buffer we use for + * reading and writing pages. This buffer includes + * space for both the payload data and the auxiliary + * data (including status bytes, but not syndrome + * bytes). + * @page_buffer_phys: The physical address for the page_buffer_virt + * buffer. + * @page_buffer_size: The size of the page buffer. + * @payload_virt: A pointer to a location in the page buffer used + * for payload bytes. The size of this buffer is + * determined by struct nfc_geometry. + * @payload_phys: The physical address for payload_virt. + * @payload_size: The size of the payload area in the page buffer. + * @auxiliary_virt: A pointer to a location in the page buffer used + * for auxiliary bytes. The size of this buffer is + * determined by struct nfc_geometry. + * @auxiliary_phys: The physical address for auxiliary_virt. + * @auxiliary_size: The size of the auxiliary area in the page buffer. + */ + +#define MIL_COMMAND_BUFFER_SIZE (10) + +struct mil { + + /* MTD Data Structures */ + + struct nand_chip nand; + struct mtd_info mtd; + struct nand_ecclayout oob_layout; + + /* Partitioning and Boot Area Protection */ + + struct mtd_info *general_use_mtd; + struct mtd_partition *partitions; + unsigned int partition_count; + void *ubi_partition_memory; + + /* General-use Variables */ + + int current_chip; + unsigned int command_length; + int inject_ecc_error; + int ignore_bad_block_marks; + void *saved_bbt; + + /* MTD Function Pointer Hooks */ + + int raw_oob_mode; + int (*hooked_read_oob)(struct mtd_info *mtd, + loff_t from, struct mtd_oob_ops *ops); + int (*hooked_write_oob)(struct mtd_info *mtd, + loff_t to, struct mtd_oob_ops *ops); + + int marking_a_bad_block; + int (*hooked_block_markbad)(struct mtd_info *mtd, + loff_t ofs); + + /* DMA Buffers */ + + char *cmd_virt; + dma_addr_t cmd_phys; + + void *page_buffer_virt; + dma_addr_t page_buffer_phys; + unsigned int page_buffer_size; + + void *payload_virt; + dma_addr_t payload_phys; + + void *auxiliary_virt; + dma_addr_t auxiliary_phys; + +}; + +/** + * struct physical_geometry - Physical geometry description. + * + * This structure describes the physical geometry of the medium. + * + * @chip_count: The number of chips in the medium. + * @chip_size_in_bytes: The size, in bytes, of a single chip + * (excluding the out-of-band bytes). + * @block_size_in_bytes: The size, in bytes, of a single block + * (excluding the out-of-band bytes). + * @page_data_size_in_bytes: The size, in bytes, of the data area in a + * page (excluding the out-of-band bytes). + * @page_oob_size_in_bytes: The size, in bytes, of the out-of-band area + * in a page. + */ + +struct physical_geometry { + unsigned int chip_count; + uint64_t chip_size_in_bytes; + unsigned int block_size_in_bytes; + unsigned int page_data_size_in_bytes; + unsigned int page_oob_size_in_bytes; +}; + +/** + * struct nfc_geometry - NFC geometry description. + * + * This structure describes the NFC's view of the medium geometry. + * + * @ecc_algorithm: The human-readable name of the ECC algorithm + * (e.g., "Reed-Solomon" or "BCH"). + * @ecc_strength: A number that describes the strength of the ECC + * algorithm. + * @page_size_in_bytes: The size, in bytes, of a physical page, including + * both data and OOB. + * @metadata_size_in_bytes: The size, in bytes, of the metadata. + * @ecc_chunk_size_in_bytes: The size, in bytes, of a single ECC chunk. Note + * the first chunk in the page includes both data and + * metadata, so it's a bit larger than this value. + * @ecc_chunk_count: The number of ECC chunks in the page, + * @payload_size_in_bytes: The size, in bytes, of the payload buffer. + * @auxiliary_size_in_bytes: The size, in bytes, of the auxiliary buffer. + * @auxiliary_status_offset: The offset into the auxiliary buffer at which + * the ECC status appears. + * @block_mark_byte_offset: The byte offset in the ECC-based page view at + * which the underlying physical block mark appears. + * @block_mark_bit_offset: The bit offset into the ECC-based page view at + * which the underlying physical block mark appears. + */ + +struct nfc_geometry { + char *ecc_algorithm; + unsigned int ecc_strength; + unsigned int page_size_in_bytes; + unsigned int metadata_size_in_bytes; + unsigned int ecc_chunk_size_in_bytes; + unsigned int ecc_chunk_count; + unsigned int payload_size_in_bytes; + unsigned int auxiliary_size_in_bytes; + unsigned int auxiliary_status_offset; + unsigned int block_mark_byte_offset; + unsigned int block_mark_bit_offset; +}; + +/** + * struct boot_rom_geometry - Boot ROM geometry description. + * + * This structure encapsulates decisions made by the Boot ROM Helper. + * + * @boot_area_count: The number of boot areas. The first boot area + * appears at the beginning of chip 0, the next + * at the beginning of chip 1, etc. + * @boot_area_size_in_bytes: The size, in bytes, of each boot area. + * @stride_size_in_pages: The size of a boot block stride, in pages. + * @search_area_stride_exponent: The logarithm to base 2 of the size of a + * search area in boot block strides. + */ + +struct boot_rom_geometry { + unsigned int boot_area_count; + unsigned int boot_area_size_in_bytes; + unsigned int stride_size_in_pages; + unsigned int search_area_stride_exponent; +}; + +/** + * struct gpmi_nfc_data - i.MX NFC per-device data. + * + * Note that the "device" managed by this driver represents the NAND Flash + * controller *and* the NAND Flash medium behind it. Thus, the per-device data + * structure has information about the controller, the chips to which it is + * connected, and properties of the medium as a whole. + * + * @dev: A pointer to the owning struct device. + * @pdev: A pointer to the owning struct platform_device. + * @pdata: A pointer to the device's platform data. + * @resources: Information about system resources used by this driver. + * @device_info: A structure that contains detailed information about + * the NAND Flash device. + * @physical_geometry: A description of the medium's physical geometry. + * @nfc: A pointer to a structure that represents the underlying + * NFC hardware. + * @nfc_geometry: A description of the medium geometry as viewed by the + * NFC. + * @rom: A pointer to a structure that represents the underlying + * Boot ROM. + * @rom_geometry: A description of the medium geometry as viewed by the + * Boot ROM. + * @mil: A collection of information used by the MTD Interface + * Layer. + */ + +struct gpmi_nfc_data { + + /* System Interface */ + struct device *dev; + struct platform_device *pdev; + struct gpmi_nfc_platform_data *pdata; + + /* Resources */ + struct resources resources; + + /* Flash Hardware */ + struct nand_device_info device_info; + struct physical_geometry physical_geometry; + + /* NFC HAL */ + struct nfc_hal *nfc; + struct nfc_geometry nfc_geometry; + + /* Boot ROM Helper */ + struct boot_rom_helper *rom; + struct boot_rom_geometry rom_geometry; + + /* MTD Interface Layer */ + struct mil mil; + +}; + +/** + * struct gpmi_nfc_timing - GPMI NFC timing parameters. + * + * This structure contains the fundamental timing attributes for the NAND Flash + * bus and the GPMI NFC hardware. + * + * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the + * maximum of tDS and tWP. A negative value + * indicates this characteristic isn't known. + * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the + * maximum of tDH, tWH and tREH. A negative value + * indicates this characteristic isn't known. + * @address_setup_in_ns: The address setup time, in nanoseconds. Usually + * the maximum of tCLS, tCS and tALS. A negative + * value indicates this characteristic isn't known. + * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative value + * indicates this characteristic isn't known. + * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic isn't + * known. + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic isn't + * known. + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic isn't + * known. + */ + +struct gpmi_nfc_timing { + int8_t data_setup_in_ns; + int8_t data_hold_in_ns; + int8_t address_setup_in_ns; + int8_t gpmi_sample_delay_in_ns; + int8_t tREA_in_ns; + int8_t tRLOH_in_ns; + int8_t tRHOH_in_ns; +}; + +/** + * struct gpmi_nfc_hardware_timing - GPMI NFC hardware timing parameters. + * + * This structure contains timing information expressed in a form directly + * usable by the GPMI NFC hardware. + * + * @data_setup_in_cycles: The data setup time, in cycles. + * @data_hold_in_cycles: The data hold time, in cycles. + * @address_setup_in_cycles: The address setup time, in cycles. + * @use_half_periods: Indicates the clock is running slowly, so the + * NFC DLL should use half-periods. + * @sample_delay_factor: The sample delay factor. + */ + +struct gpmi_nfc_hardware_timing { + uint8_t data_setup_in_cycles; + uint8_t data_hold_in_cycles; + uint8_t address_setup_in_cycles; + bool use_half_periods; + uint8_t sample_delay_factor; +}; + +/** + * struct nfc_hal - GPMI NFC HAL + * + * This structure embodies an abstract interface to the underlying NFC hardware. + * + * @version: The NFC hardware version. + * @description: A pointer to a human-readable description of + * the NFC hardware. + * @max_chip_count: The maximum number of chips the NFC can + * possibly support (this value is a constant for + * each NFC version). This may *not* be the actual + * number of chips connected. + * @max_data_setup_cycles: The maximum number of data setup cycles that + * can be expressed in the hardware. + * @internal_data_setup_in_ns: The time, in ns, that the NFC hardware requires + * for data read internal setup. In the Reference + * Manual, see the chapter "High-Speed NAND + * Timing" for more details. + * @max_sample_delay_factor: The maximum sample delay factor that can be + * expressed in the hardware. + * @max_dll_clock_period_in_ns: The maximum period of the GPMI clock that the + * sample delay DLL hardware can possibly work + * with (the DLL is unusable with longer periods). + * If the full-cycle period is greater than HALF + * this value, the DLL must be configured to use + * half-periods. + * @max_dll_delay_in_ns: The maximum amount of delay, in ns, that the + * DLL can implement. + * @dma_descriptors: A pool of DMA descriptors. + * @isr_dma_channel: The DMA channel with which the NFC HAL is + * working. We record this here so the ISR knows + * which DMA channel to acknowledge. + * @dma_done: The completion structure used for DMA + * interrupts. + * @bch_done: The completion structure used for BCH + * interrupts. + * @timing: The current timing configuration. + * @clock_frequency_in_hz: The clock frequency, in Hz, during the current + * I/O transaction. If no I/O transaction is in + * progress, this is the clock frequency during + * the most recent I/O transaction. + * @hardware_timing: The hardware timing configuration in effect + * during the current I/O transaction. If no I/O + * transaction is in progress, this is the + * hardware timing configuration during the most + * recent I/O transaction. + * @init: Initializes the NFC hardware and data + * structures. This function will be called after + * everything has been set up for communication + * with the NFC itself, but before the platform + * has set up off-chip communication. Thus, this + * function must not attempt to communicate with + * the NAND Flash hardware. + * @set_geometry: Configures the NFC hardware and data structures + * to match the physical NAND Flash geometry. + * @set_geometry: Configures the NFC hardware and data structures + * to match the physical NAND Flash geometry. + * @set_timing: Configures the NFC hardware and data structures + * to match the given NAND Flash bus timing. + * @get_timing: Returns the the clock frequency, in Hz, and + * the hardware timing configuration during the + * current I/O transaction. If no I/O transaction + * is in progress, this is the timing state during + * the most recent I/O transaction. + * @exit: Shuts down the NFC hardware and data + * structures. This function will be called after + * the platform has shut down off-chip + * communication but while communication with the + * NFC itself still works. + * @clear_bch: Clears a BCH interrupt (intended to be called + * by a more general interrupt handler to do + * device-specific clearing). + * @is_ready: Returns true if the given chip is ready. + * @begin: Begins an interaction with the NFC. This + * function must be called before *any* of the + * following functions so the NFC can prepare + * itself. + * @end: Ends interaction with the NFC. This function + * should be called to give the NFC a chance to, + * among other things, enter a lower-power state. + * @send_command: Sends the given buffer of command bytes. + * @send_data: Sends the given buffer of data bytes. + * @read_data: Reads data bytes into the given buffer. + * @send_page: Sends the given given data and OOB bytes, + * using the ECC engine. + * @read_page: Reads a page through the ECC engine and + * delivers the data and OOB bytes to the given + * buffers. + */ + +#define NFC_DMA_DESCRIPTOR_COUNT (4) + +struct nfc_hal { + + /* Hardware attributes. */ + + const unsigned int version; + const char *description; + const unsigned int max_chip_count; + const unsigned int max_data_setup_cycles; + const unsigned int internal_data_setup_in_ns; + const unsigned int max_sample_delay_factor; + const unsigned int max_dll_clock_period_in_ns; + const unsigned int max_dll_delay_in_ns; + + /* Working variables. */ + + struct mxs_dma_desc *dma_descriptors[NFC_DMA_DESCRIPTOR_COUNT]; + int isr_dma_channel; + struct completion dma_done; + struct completion bch_done; + struct gpmi_nfc_timing timing; + unsigned long clock_frequency_in_hz; + + /* Configuration functions. */ + + int (*init) (struct gpmi_nfc_data *); + int (*set_geometry)(struct gpmi_nfc_data *); + int (*set_timing) (struct gpmi_nfc_data *, + const struct gpmi_nfc_timing *); + void (*get_timing) (struct gpmi_nfc_data *, + unsigned long *clock_frequency_in_hz, + struct gpmi_nfc_hardware_timing *); + void (*exit) (struct gpmi_nfc_data *); + + /* Call these functions to begin and end I/O. */ + + void (*begin) (struct gpmi_nfc_data *); + void (*end) (struct gpmi_nfc_data *); + + /* Call these I/O functions only between begin() and end(). */ + + void (*clear_bch) (struct gpmi_nfc_data *); + int (*is_ready) (struct gpmi_nfc_data *, unsigned chip); + int (*send_command)(struct gpmi_nfc_data *, unsigned chip, + dma_addr_t buffer, unsigned length); + int (*send_data) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t buffer, unsigned length); + int (*read_data) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t buffer, unsigned length); + int (*send_page) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary); + int (*read_page) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary); +}; + +/** + * struct boot_rom_helper - Boot ROM Helper + * + * This structure embodies the interface to an object that assists the driver + * in making decisions that relate to the Boot ROM. + * + * @version: The Boot ROM version. + * @description: A pointer to a human-readable description of the + * Boot ROM. + * @swap_block_mark: Indicates that the Boot ROM will swap the block + * mark with the first byte of the OOB. + * @set_geometry: Configures the Boot ROM geometry. + * @check_transcription_stamp: Checks for a transcription stamp. This pointer + * is ignored if swap_block_mark is set. + * @write_transcription_stamp: Writes a transcription stamp. This pointer + * is ignored if swap_block_mark is set. + */ + +struct boot_rom_helper { + const unsigned int version; + const char *description; + const int swap_block_mark; + int (*set_geometry) (struct gpmi_nfc_data *); + int (*check_transcription_stamp)(struct gpmi_nfc_data *); + int (*write_transcription_stamp)(struct gpmi_nfc_data *); +}; + +/* + *------------------------------------------------------------------------------ + * External Symbols + *------------------------------------------------------------------------------ + */ + +/* Event Reporting */ + +#if defined(EVENT_REPORTING) + extern void gpmi_nfc_start_event_trace(char *description); + extern void gpmi_nfc_add_event(char *description, int delta); + extern void gpmi_nfc_stop_event_trace(char *description); + extern void gpmi_nfc_dump_event_trace(void); +#else + #define gpmi_nfc_start_event_trace(description) do {} while (0) + #define gpmi_nfc_add_event(description, delta) do {} while (0) + #define gpmi_nfc_stop_event_trace(description) do {} while (0) + #define gpmi_nfc_dump_event_trace() do {} while (0) +#endif + +/* NFC HAL Common Services */ + +extern irqreturn_t gpmi_nfc_bch_isr(int irq, void *cookie); +extern irqreturn_t gpmi_nfc_dma_isr(int irq, void *cookie); +extern int gpmi_nfc_dma_init(struct gpmi_nfc_data *this); +extern void gpmi_nfc_dma_exit(struct gpmi_nfc_data *this); +extern int gpmi_nfc_set_geometry(struct gpmi_nfc_data *this); +extern int gpmi_nfc_dma_go(struct gpmi_nfc_data *this, int dma_channel); +extern int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this, + struct gpmi_nfc_hardware_timing *hw); + +/* NFC HAL Structures */ + +extern struct nfc_hal gpmi_nfc_hal_v0; +extern struct nfc_hal gpmi_nfc_hal_v1; +extern struct nfc_hal gpmi_nfc_hal_v2; + +/* Boot ROM Helper Common Services */ + +extern int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this); + +/* Boot ROM Helper Structures */ + +extern struct boot_rom_helper gpmi_nfc_boot_rom_helper_v0; +extern struct boot_rom_helper gpmi_nfc_boot_rom_helper_v1; + +/* MTD Interface Layer */ + +extern int gpmi_nfc_mil_init(struct gpmi_nfc_data *this); +extern void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this); + +#endif diff --git a/drivers/mxc/amd-gpu/Kconfig b/drivers/mxc/amd-gpu/Kconfig new file mode 100644 index 000000000000..629d8cbbc989 --- /dev/null +++ b/drivers/mxc/amd-gpu/Kconfig @@ -0,0 +1,13 @@ +# +# Bluetooth configuration +# + +menu "MXC GPU support" + +config MXC_AMD_GPU + tristate "MXC GPU support" + depends on ARCH_MX35 || ARCH_MX51 || ARCH_MX53 || ARCH_MX50 + ---help--- + Say Y to get the GPU driver support. + +endmenu diff --git a/drivers/mxc/amd-gpu/Makefile b/drivers/mxc/amd-gpu/Makefile new file mode 100644 index 000000000000..84cf02e5b3a3 --- /dev/null +++ b/drivers/mxc/amd-gpu/Makefile @@ -0,0 +1,31 @@ +EXTRA_CFLAGS := \ + -D_LINUX \ + -I$(obj)/include \ + -I$(obj)/include/api \ + -I$(obj)/include/ucode \ + -I$(obj)/platform/hal/linux \ + -I$(obj)/os/include \ + -I$(obj)/os/kernel/include \ + -I$(obj)/os/user/include + +obj-$(CONFIG_MXC_AMD_GPU) += gpu.o +gpu-objs += common/gsl_cmdstream.o \ + common/gsl_cmdwindow.o \ + common/gsl_context.o \ + common/gsl_debug_pm4.o \ + common/gsl_device.o \ + common/gsl_drawctxt.o \ + common/gsl_driver.o \ + common/gsl_g12.o \ + common/gsl_intrmgr.o \ + common/gsl_memmgr.o \ + common/gsl_mmu.o \ + common/gsl_ringbuffer.o \ + common/gsl_sharedmem.o \ + common/gsl_yamato.o \ + platform/hal/linux/gsl_linux_map.o \ + platform/hal/linux/gsl_kmod.o \ + platform/hal/linux/gsl_hal.o \ + platform/hal/linux/gsl_kmod_cleanup.o \ + platform/hal/linux/misc.o \ + os/kernel/src/linux/kos_lib.o diff --git a/drivers/mxc/amd-gpu/common/gsl_cmdstream.c b/drivers/mxc/amd-gpu/common/gsl_cmdstream.c new file mode 100644 index 000000000000..338192c7ba32 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_cmdstream.c @@ -0,0 +1,239 @@ +/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#include "gsl_cmdstream.h" + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_cmdstream_init(gsl_device_t *device) +{ + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int +kgsl_cmdstream_close(gsl_device_t *device) +{ + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +gsl_timestamp_t +kgsl_cmdstream_readtimestamp0(gsl_deviceid_t device_id, gsl_timestamp_type_t type) +{ + gsl_timestamp_t timestamp = -1; + gsl_device_t* device = &gsl_driver.device[device_id-1]; + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> gsl_timestamp_t kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id=%d gsl_timestamp_type_t type=%d)\n", device_id, type ); +#if (defined(GSL_BLD_G12) && defined(IRQTHREAD_POLL)) + kos_event_signal(device->irqthread_event); +#endif + if (type == GSL_TIMESTAMP_CONSUMED) + { + // start-of-pipeline timestamp + GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, (unsigned int*)×tamp); + } + else if (type == GSL_TIMESTAMP_RETIRED) + { + // end-of-pipeline timestamp + GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (unsigned int*)×tamp); + } + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_readtimestamp. Return value %d\n", timestamp ); + return (timestamp); +} + +//---------------------------------------------------------------------------- + +KGSL_API gsl_timestamp_t +kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id, gsl_timestamp_type_t type) +{ + gsl_timestamp_t timestamp = -1; + GSL_API_MUTEX_LOCK(); + timestamp = kgsl_cmdstream_readtimestamp0(device_id, type); + GSL_API_MUTEX_UNLOCK(); + return timestamp; +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_cmdstream_issueibcmds(gsl_deviceid_t device_id, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags) +{ + gsl_device_t* device = &gsl_driver.device[device_id-1]; + int status = GSL_FAILURE; + GSL_API_MUTEX_LOCK(); + + kgsl_device_active(device); + + if (device->ftbl.cmdstream_issueibcmds) + { + status = device->ftbl.cmdstream_issueibcmds(device, drawctxt_index, ibaddr, sizedwords, timestamp, flags); + } + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_add_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t *timestamp) +{ + gsl_device_t* device = &gsl_driver.device[device_id-1]; + int status = GSL_FAILURE; + GSL_API_MUTEX_LOCK(); + if (device->ftbl.device_addtimestamp) + { + status = device->ftbl.device_addtimestamp(device, timestamp); + } + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +KGSL_API +int kgsl_cmdstream_waittimestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp, unsigned int timeout) +{ + gsl_device_t* device = &gsl_driver.device[device_id-1]; + int status = GSL_FAILURE; + if (device->ftbl.device_waittimestamp) + { + status = device->ftbl.device_waittimestamp(device, timestamp, timeout); + } + return status; +} + +//---------------------------------------------------------------------------- + +void +kgsl_cmdstream_memqueue_drain(gsl_device_t *device) +{ + gsl_memnode_t *memnode, *nextnode, *freehead; + gsl_timestamp_t timestamp, ts_processed; + gsl_memqueue_t *memqueue = &device->memqueue; + // check head + if (memqueue->head == NULL) + { + return; + } + // get current EOP timestamp + ts_processed = kgsl_cmdstream_readtimestamp0(device->id, GSL_TIMESTAMP_RETIRED); + timestamp = memqueue->head->timestamp; + // check head timestamp + if (!(((ts_processed - timestamp) >= 0) || ((ts_processed - timestamp) < -20000))) + { + return; + } + memnode = memqueue->head; + freehead = memqueue->head; + // get node list to free + for(;;) + { + nextnode = memnode->next; + if (nextnode == NULL) + { + // entire queue drained + memqueue->head = NULL; + memqueue->tail = NULL; + break; + } + timestamp = nextnode->timestamp; + if (!(((ts_processed - timestamp) >= 0) || ((ts_processed - timestamp) < -20000))) + { + // drained up to a point + memqueue->head = nextnode; + memnode->next = NULL; + break; + } + memnode = nextnode; + } + // free nodes + while (freehead) + { + memnode = freehead; + freehead = memnode->next; + kgsl_sharedmem_free0(&memnode->memdesc, memnode->pid); + kos_free(memnode); + } +} + +//---------------------------------------------------------------------------- + +int +kgsl_cmdstream_freememontimestamp(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type) +{ + gsl_memnode_t *memnode; + gsl_device_t *device = &gsl_driver.device[device_id-1]; + gsl_memqueue_t *memqueue; + (void)type; // unref. For now just use EOP timestamp + + GSL_API_MUTEX_LOCK(); + + memqueue = &device->memqueue; + + memnode = kos_malloc(sizeof(gsl_memnode_t)); + + if (!memnode) + { + // other solution is to idle and free which given that the upper level driver probably wont check, probably a better idea + GSL_API_MUTEX_UNLOCK(); + return (GSL_FAILURE); + } + + memnode->timestamp = timestamp; + memnode->pid = GSL_CALLER_PROCESSID_GET(); + memnode->next = NULL; + kos_memcpy(&memnode->memdesc, memdesc, sizeof(gsl_memdesc_t)); + + // add to end of queue + if (memqueue->tail != NULL) + { + memqueue->tail->next = memnode; + memqueue->tail = memnode; + } + else + { + KOS_ASSERT(memqueue->head == NULL); + memqueue->head = memnode; + memqueue->tail = memnode; + } + + GSL_API_MUTEX_UNLOCK(); + + return (GSL_SUCCESS); +} + +static int kgsl_cmdstream_timestamp_cmp(gsl_timestamp_t ts_new, gsl_timestamp_t ts_old) +{ + gsl_timestamp_t ts_diff = ts_new - ts_old; + return (ts_diff >= 0) || (ts_diff < -20000); +} + +int kgsl_cmdstream_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp) +{ + gsl_timestamp_t ts_processed; + ts_processed = kgsl_cmdstream_readtimestamp0(device_id, GSL_TIMESTAMP_RETIRED); + return kgsl_cmdstream_timestamp_cmp(ts_processed, timestamp); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c b/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c new file mode 100644 index 000000000000..4d70da5b25c8 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c @@ -0,0 +1,136 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + +#ifdef GSL_BLD_G12 + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_CMDWINDOW_TARGET_MASK 0x000000FF +#define GSL_CMDWINDOW_ADDR_MASK 0x00FFFF00 +#define GSL_CMDWINDOW_TARGET_SHIFT 0 +#define GSL_CMDWINDOW_ADDR_SHIFT 8 + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_cmdwindow_init(gsl_device_t *device) +{ + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_cmdwindow_close(gsl_device_t *device) +{ + return (GSL_SUCCESS); +} + +#endif // GSL_BLD_G12 + +//---------------------------------------------------------------------------- + +int +kgsl_cmdwindow_write0(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data) +{ +#ifdef GSL_BLD_G12 + gsl_device_t *device; + unsigned int cmdwinaddr; + unsigned int cmdstream; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_cmdwindow_write( gsl_device_id_t device_id=%d, gsl_cmdwindow_t target=%d, unsigned int addr=0x%08x, unsigned int data=0x%08x)\n", device_id, target, addr, data ); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + if (target < GSL_CMDWINDOW_MIN || target > GSL_CMDWINDOW_MAX) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid target.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + if ((!(device->flags & GSL_FLAGS_INITIALIZED) && target == GSL_CMDWINDOW_MMU) || + (!(device->flags & GSL_FLAGS_STARTED) && target != GSL_CMDWINDOW_MMU)) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device state to write to selected targer.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // set command stream + if (target == GSL_CMDWINDOW_MMU) + { +#ifdef GSL_NO_MMU + return (GSL_SUCCESS); +#endif + cmdstream = ADDR_VGC_MMUCOMMANDSTREAM; + } + else + { + cmdstream = ADDR_VGC_COMMANDSTREAM; + } + + + // set command window address + cmdwinaddr = ((target << GSL_CMDWINDOW_TARGET_SHIFT) & GSL_CMDWINDOW_TARGET_MASK); + cmdwinaddr |= ((addr << GSL_CMDWINDOW_ADDR_SHIFT) & GSL_CMDWINDOW_ADDR_MASK); + +#ifndef GSL_NO_MMU + // set mmu pagetable + kgsl_mmu_setpagetable(device, GSL_CALLER_PROCESSID_GET()); +#endif + + // write command window address + device->ftbl.device_regwrite(device, (cmdstream)>>2, cmdwinaddr); + + // write data + device->ftbl.device_regwrite(device, (cmdstream)>>2, data); + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +#else + // unreferenced formal parameter + (void) device_id; + (void) target; + (void) addr; + (void) data; + + return (GSL_FAILURE); +#endif // GSL_BLD_G12 +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_cmdwindow_write(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_cmdwindow_write0(device_id, target, addr, data); + GSL_API_MUTEX_UNLOCK(); + return status; +} diff --git a/drivers/mxc/amd-gpu/common/gsl_context.c b/drivers/mxc/amd-gpu/common/gsl_context.c new file mode 100644 index 000000000000..c999247b3afd --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_context.c @@ -0,0 +1,74 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#include "gsl_context.h" + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +KGSL_API int +kgsl_context_create(gsl_deviceid_t device_id, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags) +{ + gsl_device_t* device = &gsl_driver.device[device_id-1]; + int status; + + GSL_API_MUTEX_LOCK(); + + if (device->ftbl.context_create) + { + status = device->ftbl.context_create(device, type, drawctxt_id, flags); + } + else + { + status = GSL_FAILURE; + } + + GSL_API_MUTEX_UNLOCK(); + + return status; +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_context_destroy(gsl_deviceid_t device_id, unsigned int drawctxt_id) +{ + gsl_device_t* device = &gsl_driver.device[device_id-1]; + int status; + + GSL_API_MUTEX_LOCK(); + + if (device->ftbl.context_destroy) + { + status = device->ftbl.context_destroy(device, drawctxt_id); + } + else + { + status = GSL_FAILURE; + } + + GSL_API_MUTEX_UNLOCK(); + + return status; +} + +//---------------------------------------------------------------------------- + diff --git a/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c b/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c new file mode 100644 index 000000000000..847df8dbe386 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c @@ -0,0 +1,1015 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + +#if defined(_WIN32) && defined (GSL_BLD_YAMATO) + +#include +#include +#include + +//#define PM4_DEBUG_USE_MEMBUF + +#ifdef PM4_DEBUG_USE_MEMBUF + +#define MEMBUF_SIZE 100000 +#define BUFFER_END_MARGIN 1000 +char memBuf[MEMBUF_SIZE]; +static int writePtr = 0; +static unsigned int lineNumber = 0; +//#define fprintf(A,...); writePtr += sprintf( memBuf+writePtr, __VA_ARGS__ ); sprintf( memBuf+writePtr, "###" ); if( writePtr > MEMBUF_SIZE-BUFFER_END_MARGIN ) { memset(memBuf+writePtr, '#', MEMBUF_SIZE-writePtr); writePtr = 0; } +#define FILE char +#define fopen(X,Y) 0 +#define fclose(X) + +int printString( FILE *_File, const char * _Format, ...) +{ + int ret; + va_list ap; + (void)_File; + + va_start(ap, _Format); + if( writePtr > 0 && memBuf[writePtr-1] == '\n' ) + { + // Add line number if last written character was newline + writePtr += sprintf( memBuf+writePtr, "%d: ", lineNumber++ ); + } + ret = vsprintf(memBuf+writePtr, _Format, ap); + writePtr += ret; + sprintf( memBuf+writePtr, "###" ); + if( writePtr > MEMBUF_SIZE-BUFFER_END_MARGIN ) + { + memset(memBuf+writePtr, '#', MEMBUF_SIZE-writePtr); + writePtr = 0; + } + + va_end(ap); + + return ret; +} + +#else + +int printString( FILE *_File, const char * _Format, ...) +{ + int ret; + va_list ap; + va_start(ap, _Format); + ret = vfprintf(_File, _Format, ap); + va_end(ap); + fflush(_File); + return ret; +} + +#endif + +#ifndef _WIN32_WCE +#define PM4_DUMPFILE "pm4dump.txt" +#else +#define PM4_DUMPFILE "\\Release\\pm4dump.txt" +#endif + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define EXPAND_OPCODE(opcode) ((opcode << 8) | PM4_PKT_MASK) + +#define GetString_uint GetString_int +#define GetString_fixed12_4(val, szValue) GetString_fixed(val, 12, 4, szValue) +#define GetString_signedint15(val, szValue) GetString_signedint(val, 15, szValue) + +// Need a prototype for this function +void WritePM4Packet_Type3(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer); + +static int indirectionLevel = 0; + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +void WriteDWORD(FILE* pFile, unsigned int dwValue) +{ + printString(pFile, " 0x%08x", dwValue); +} + +void WriteDWORD2(FILE* pFile, unsigned int dwValue) +{ + printString(pFile, " 0x%08x\n", dwValue); +} + +//---------------------------------------------------------------------------- + +// Generate the GetString_## functions for enumerated types +#define START_ENUMTYPE(__type) \ +void GetString_##__type(unsigned int val, char* szValue) \ +{ \ + switch(val) \ + { + +#define GENERATE_ENUM(__enumname, __val) \ + case __val: \ + kos_strcpy(szValue, #__enumname); \ + break; + +#define END_ENUMTYPE(__type) \ + default: \ + sprintf(szValue, "Unknown: %d", val); \ + break; \ + } \ +} + +#include _YAMATO_GENENUM_H + +//---------------------------------------------------------------------------- + +void +GetString_hex(unsigned int val, char* szValue) +{ + sprintf(szValue, "0x%x", val); +} + +//---------------------------------------------------------------------------- + +void +GetString_float(unsigned int val, char* szValue) +{ + float fval = *((float*) &val); + sprintf(szValue, "%.4f", fval); +} + +//---------------------------------------------------------------------------- + +void +GetString_bool(unsigned int val, char* szValue) +{ + if (val) + { + kos_strcpy(szValue, "TRUE"); + } + else + { + kos_strcpy(szValue, "FALSE"); + } +} + +//---------------------------------------------------------------------------- + +void GetString_int(unsigned int val, char* szValue) +{ + sprintf(szValue, "%d", val); +} + +//---------------------------------------------------------------------------- + +void +GetString_intMinusOne(unsigned int val, char* szValue) +{ + sprintf(szValue, "%d+1", val); +} + +//---------------------------------------------------------------------------- + +void +GetString_signedint(unsigned int val, unsigned int dwNumBits, char* szValue) +{ + int nValue = val; + + if (val & (1<<(dwNumBits-1))) + { + nValue |= 0xffffffff << dwNumBits; + } + + sprintf(szValue, "%d", nValue); +} + +//---------------------------------------------------------------------------- + +void +GetString_fixed(unsigned int val, unsigned int dwNumInt, unsigned int dwNumFrac, char* szValue) +{ + + (void) dwNumInt; // unreferenced formal parameter + + if (val>>dwNumFrac == 0) + { + // Integer part is 0 - just print out the fractional part + sprintf(szValue, "%d/%d", + val&((1<>dwNumFrac, + val&((1<> 16) == 0x4)) + registerAddr = (*pBuffer) & 0xffff; + + // Write unsigned int + WriteDWORD(pFile, *pBuffer); + + // Starting at Ordinal 2 is actual register values + if((dwIndex > 0) && (registerAddr != 0xffffffff)) + { + // Write register string based on address + GetString_Register(registerAddr + 0x2000, *pBuffer, szRegister); + printString(pFile, " // %s\n", szRegister); + registerAddr++; + } + else + { + // Write out newline if we aren't augmenting with register fields + printString(pFile, "\n"); + } + + pBuffer++; + } + } + *ppBuffer = pBuffer; +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpInitParams(unsigned int dwEDRAMBase, unsigned int dwEDRAMSize) +{ + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "InitParams, edrambase=0x%x, edramsize=%d\n", + dwEDRAMBase, dwEDRAMSize); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpSwapBuffers(unsigned int dwAddress, unsigned int dwWidth, + unsigned int dwHeight, unsigned int dwPitch, unsigned int dwAlignedHeight, unsigned int dwBitsPerPixel) +{ + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "SwapBuffers, address=0x%08x, width=%d, height=%d, pitch=%d, alignedheight=%d, bpp=%d\n", + dwAddress, dwWidth, dwHeight, dwPitch, dwAlignedHeight, dwBitsPerPixel); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpRegSpace(gsl_device_t *device) +{ + int regsPerLine = 0x20; + unsigned int dwOffset; + unsigned int value; + + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "Start_RegisterSpace\n"); + + for (dwOffset = 0; dwOffset < device->regspace.sizebytes; dwOffset += 4) + { + if (dwOffset % regsPerLine == 0) + { + printString(pFile, " 0x%08x ", dwOffset); + } + + GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (dwOffset >> 2), &value); + + printString(pFile, " 0x%08x", value); + + if (((dwOffset + 4) % regsPerLine == 0) && ((dwOffset + 4) < device->regspace.sizebytes)) + { + printString(pFile, "\n"); + } + } + + printString(pFile, "\nEnd_RegisterSpace\n"); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpAllocateMemory(unsigned int dwSize, unsigned int dwFlags, unsigned int dwAddress, + unsigned int dwActualSize) +{ + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "AllocateMemory, size=%d, flags=0x%x, address=0x%x, actualSize=%d\n", + dwSize, dwFlags, dwAddress, dwActualSize); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpFreeMemory(unsigned int dwAddress) +{ + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "FreeMemory, address=0x%x\n", dwAddress); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpWriteMemory(unsigned int dwAddress, unsigned int dwSize, void* pData) +{ + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + unsigned int dwNumDWORDs; + unsigned int dwIndex; + unsigned int *pDataPtr; + + printString(pFile, "StartWriteMemory, address=0x%x, size=%d\n", dwAddress, dwSize); + + // Now write the data, in dwNumDWORDs + dwNumDWORDs = dwSize >> 2; + + // If there are spillover bytes into the next dword, increment the amount dumped out here. + // The reader needs to take care of not overwriting the nonvalid bytes + if((dwSize % 4) != 0) + dwNumDWORDs++; + + for (dwIndex = 0, pDataPtr = (unsigned int *)pData; dwIndex < dwNumDWORDs; dwIndex++, pDataPtr++) + { + WriteDWORD2(pFile, *pDataPtr); + } + + printString(pFile, "EndWriteMemory\n"); + + fclose(pFile); +} + +void +Yamato_DumpSetMemory(unsigned int dwAddress, unsigned int dwSize, unsigned int pData) +{ + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); +// unsigned int* pDataPtr; + + printString(pFile, "SetMemory, address=0x%x, size=%d, value=0x%x\n", + dwAddress, dwSize, pData); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- +void +Yamato_ConvertIBAddr(unsigned int dwHeader, unsigned int *pBuffer, int gpuToHost) +{ + unsigned int hostaddr; + unsigned int *ibend; + unsigned int *addr; + unsigned int *ib = pBuffer; + pm4_type3 header = *((pm4_type3*) &dwHeader); + + // convert ib1 base address + if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) || + (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD)) + { + if (gpuToHost) + { + // from gpu to host + *ib = kgsl_sharedmem_convertaddr(*ib, 0); + + hostaddr = *ib; + } + else + { + // from host to gpu + hostaddr = *ib; + *ib = kgsl_sharedmem_convertaddr(*ib, 1); + } + + // walk through ib1 and convert any ib2 base address + + ib = (unsigned int *) hostaddr; + ibend = (unsigned int *) (ib + *(++pBuffer)); + + while (ib < ibend) + { + dwHeader = *(ib); + header = *((pm4_type3*) (&dwHeader)); + + switch(dwHeader & PM4_PKT_MASK) + { + case PM4_TYPE0_PKT: + ib += header.count + 2; + break; + + case PM4_TYPE1_PKT: + break; + + case PM4_TYPE2_PKT: + ib++; + break; + + case PM4_TYPE3_PKT: + if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) || + (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD)) + { + addr = ib + 1; + if (gpuToHost) + { + // from gpu to host + *addr = kgsl_sharedmem_convertaddr(*addr, 0); + } + else + { + // from host to gpu + *addr = kgsl_sharedmem_convertaddr(*addr, 1); + } + } + ib += header.count + 2; + break; + } + } + } +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpPM4(unsigned int* pBuffer, unsigned int sizeDWords) +{ + unsigned int *pBufferEnd = pBuffer + sizeDWords; + unsigned int *tmp; + + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "Start_PM4Buffer\n");//, count=%d\n", sizeDWords); + + // So look at the first unsigned int - should be a header + while(pBuffer < pBufferEnd) + { + unsigned int dwHeader = *(pBuffer++); + + //printString(pFile, " Start_Packet\n"); + switch(dwHeader & PM4_PKT_MASK) + { + case PM4_TYPE0_PKT: + WritePM4Packet_Type0(pFile, dwHeader, &pBuffer); + break; + + case PM4_TYPE1_PKT: + break; + + case PM4_TYPE2_PKT: + WritePM4Packet_Type2(pFile, dwHeader, &pBuffer); + break; + + case PM4_TYPE3_PKT: + indirectionLevel = 0; + tmp = pBuffer; + Yamato_ConvertIBAddr(dwHeader, tmp, 1); + WritePM4Packet_Type3(pFile, dwHeader, &pBuffer); + Yamato_ConvertIBAddr(dwHeader, tmp, 0); + break; + } + //printString(pFile, " End_Packet\n"); + } + + printString(pFile, "End_PM4Buffer\n"); + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpRegisterWrite(unsigned int dwAddress, unsigned int value) +{ + FILE *pFile; + + // Build a Type-0 packet that maps to this register write + unsigned int pBuffer[100], *pBuf = &pBuffer[1]; + + // Don't dump CP_RB_WPTR (switch statement may be necessary here for future additions) + if(dwAddress == mmCP_RB_WPTR) + return; + + pFile = fopen(PM4_DUMPFILE, "a"); + + pBuffer[0] = dwAddress; + pBuffer[1] = value; + + printString(pFile, "StartRegisterWrite\n"); + WritePM4Packet_Type0(pFile, pBuffer[0], &pBuf); + printString(pFile, "EndRegisterWrite\n"); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpFbStart(gsl_device_t *device) +{ + FILE *pFile; + + static int firstCall = 0; + + // We only want to call this once + if(firstCall) + return; + + pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "FbStart, value=0x%x\n", device->mmu.mpu_base); + printString(pFile, "FbSize, value=0x%x\n", device->mmu.mpu_range); + + fclose(pFile); + + firstCall = 1; +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpWindow(unsigned int addr, unsigned int width, unsigned int height) +{ + FILE *pFile; + + pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "DumpWindow, addr=0x%x, width=0x%x, height=0x%x\n", addr, width, height); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- +#ifdef _DEBUG + +#define ADDRESS_STACK_SIZE 256 +#define GET_PM4_TYPE3_OPCODE(x) ((*(x) >> 8) & 0xFF) +#define IF_REGISTER_IN_RANGE(reg, base, count) \ + offset = (reg) - (base); \ + if(offset >= 0 && offset <= (count) - 2) +#define GET_CP_CONSTANT_DATA(x) (*((x) + offset + 2)) + +static const char format2bpp[] = +{ + 2, // COLORX_4_4_4_4 + 2, // COLORX_1_5_5_5 + 2, // COLORX_5_6_5 + 1, // COLORX_8 + 2, // COLORX_8_8 + 4, // COLORX_8_8_8_8 + 4, // COLORX_S8_8_8_8 + 2, // COLORX_16_FLOAT + 4, // COLORX_16_16_FLOAT + 8, // COLORX_16_16_16_16_FLOAT + 4, // COLORX_32_FLOAT + 8, // COLORX_32_32_FLOAT + 16, // COLORX_32_32_32_32_FLOAT , + 1, // COLORX_2_3_3 + 3, // COLORX_8_8_8 +}; + +static unsigned int kgsl_dumpx_addr_count = 0; //unique command buffer addresses encountered +static int kgsl_dumpx_handle_type3(unsigned int* hostaddr, int count) +{ + // For swap detection we need to find the below declared static values, and detect DI during EDRAM copy + static unsigned int width = 0, height = 0, format = 0, baseaddr = 0, iscopy = 0; + + static unsigned int addr_stack[ADDRESS_STACK_SIZE]; + static unsigned int size_stack[ADDRESS_STACK_SIZE]; + int swap = 0; // have we encountered a swap during recursion (return value) + + switch(GET_PM4_TYPE3_OPCODE(hostaddr)) + { + case PM4_INDIRECT_BUFFER_PFD: + case PM4_INDIRECT_BUFFER: + { + // traverse indirect buffers + unsigned int i; + unsigned int ibaddr = *(hostaddr+1); + unsigned int ibsize = *(hostaddr+2); + + // is this address already in encountered? + for(i = 0; i < kgsl_dumpx_addr_count && addr_stack[i] != ibaddr; i++); + + if(kgsl_dumpx_addr_count == i) + { + // yes it was, store the address so we don't dump this buffer twice + addr_stack[kgsl_dumpx_addr_count] = ibaddr; + // just for sanity checking + size_stack[kgsl_dumpx_addr_count++] = ibsize; + KOS_ASSERT(kgsl_dumpx_addr_count < ADDRESS_STACK_SIZE); + + // recursively follow the indirect link and update swap if indirect buffer had resolve + swap |= kgsl_dumpx_parse_ibs(ibaddr, ibsize); + } + else + { + KOS_ASSERT(size_stack[i] == ibsize); + } + } + break; + + case PM4_SET_CONSTANT: + if((*(hostaddr+1) >> 16) == 0x4) + { + // parse register writes, and figure out framebuffer configuration + + unsigned int regaddr = (*(hostaddr + 1) & 0xFFFF) + 0x2000; //dword address in register space + int offset; // used by the macros + + IF_REGISTER_IN_RANGE(mmPA_SC_WINDOW_SCISSOR_BR, regaddr, count) + { + // found write to PA_SC_WINDOW_SCISSOR_BR, we use this to detect current + // width and height of the framebuffer (TODO: find more reliable way of achieving this) + unsigned int data = GET_CP_CONSTANT_DATA(hostaddr); + width = data & 0xFFFF; + height = data >> 16; + } + + IF_REGISTER_IN_RANGE(mmRB_MODECONTROL, regaddr, count) + { + // found write to RB_MODECONTROL, we use this to find out if next DI is resolve + unsigned int data = GET_CP_CONSTANT_DATA(hostaddr); + iscopy = (data & RB_MODECONTROL__EDRAM_MODE_MASK) == (EDRAM_COPY << RB_MODECONTROL__EDRAM_MODE__SHIFT); + } + + IF_REGISTER_IN_RANGE(mmRB_COPY_DEST_BASE, regaddr, count) + { + // found write to RB_COPY_DEST_BASE, we use this to find out the framebuffer base address + unsigned int data = GET_CP_CONSTANT_DATA(hostaddr); + baseaddr = (data & RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK); + } + + IF_REGISTER_IN_RANGE(mmRB_COPY_DEST_INFO, regaddr, count) + { + // found write to RB_COPY_DEST_INFO, we use this to find out the framebuffer format + unsigned int data = GET_CP_CONSTANT_DATA(hostaddr); + format = (data & RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT; + } + } + break; + + case PM4_DRAW_INDX: + case PM4_DRAW_INDX_2: + { + // DI found + // check if it is resolve + if(iscopy && !swap) + { + // printf("resolve: %ix%i @ 0x%08x, format = 0x%08x\n", width, height, baseaddr, format); + KOS_ASSERT(format < 15); + + // yes it was and we need to update color buffer config because this is the first bin + // dumpx framebuffer base address, and dimensions + KGSL_DEBUG_DUMPX( BB_DUMP_CBUF_AWH, (unsigned int)baseaddr, width, height, " "); + + // find aligned width + width = (width + 31) & ~31; + + //dump bytes-per-pixel and aligned width + KGSL_DEBUG_DUMPX( BB_DUMP_CBUF_FS, format2bpp[format], width, 0, " "); + swap = 1; + } + + } + break; + + default: + break; + } + return swap; +} + +// Traverse IBs and dump them to test vector. Detect swap by inspecting register +// writes, keeping note of the current state, and dump framebuffer config to test vector +int kgsl_dumpx_parse_ibs(gpuaddr_t gpuaddr, int sizedwords) +{ + static unsigned int level = 0; //recursion level + + int swap = 0; // have we encountered a swap during recursion (return value) + unsigned int *hostaddr; + int dwords_left = sizedwords; //dwords left in the current command buffer + + level++; + + KOS_ASSERT(sizeof(unsigned int *) == sizeof(unsigned int)); + KOS_ASSERT(level <= 2); + hostaddr = (unsigned int *)kgsl_sharedmem_convertaddr(gpuaddr, 0); + + // dump the IB to test vector + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, gpuaddr, (unsigned int)hostaddr, sizedwords*4, "kgsl_dumpx_write_ibs")); + + while(dwords_left) + { + int count = 0; //dword count including packet header + + switch(*hostaddr >> 30) + { + case 0x0: // type-0 + count = (*hostaddr >> 16)+2; + break; + case 0x1: // type-1 + count = 2; + break; + case 0x3: // type-3 + count = ((*hostaddr >> 16) & 0x3fff) + 2; + swap |= kgsl_dumpx_handle_type3(hostaddr, count); + break; // type-3 + default: + KOS_ASSERT(!"unknown packet type"); + } + + // jump to next packet + dwords_left -= count; + hostaddr += count; + KOS_ASSERT(dwords_left >= 0 && "PM4 parsing error"); + } + + level--; + + // if this is the starting level of recursion, we are done. clean-up + if(level == 0) kgsl_dumpx_addr_count = 0; + + return swap; +} +#endif + +#endif // WIN32 + diff --git a/drivers/mxc/amd-gpu/common/gsl_device.c b/drivers/mxc/amd-gpu/common/gsl_device.c new file mode 100644 index 000000000000..537b277918c4 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_device.c @@ -0,0 +1,683 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#ifdef _LINUX +#include +#endif + +////////////////////////////////////////////////////////////////////////////// +// inline functions +////////////////////////////////////////////////////////////////////////////// +OSINLINE void +kgsl_device_getfunctable(gsl_deviceid_t device_id, gsl_functable_t *ftbl) +{ + switch (device_id) + { +#ifdef GSL_BLD_YAMATO + case GSL_DEVICE_YAMATO: + kgsl_yamato_getfunctable(ftbl); + break; +#endif // GSL_BLD_YAMATO +#ifdef GSL_BLD_G12 + case GSL_DEVICE_G12: + kgsl_g12_getfunctable(ftbl); + break; +#endif // GSL_BLD_G12 + default: + break; + } +} + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_device_init(gsl_device_t *device, gsl_deviceid_t device_id) +{ + int status = GSL_SUCCESS; + gsl_devconfig_t config; + gsl_hal_t *hal = (gsl_hal_t *)gsl_driver.hal; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_init(gsl_device_t *device=0x%08x, gsl_deviceid_t device_id=%D )\n", device, device_id ); + + if ((GSL_DEVICE_YAMATO == device_id) && !(hal->has_z430)) { + return GSL_FAILURE_NOTSUPPORTED; + } + + if ((GSL_DEVICE_G12 == device_id) && !(hal->has_z160)) { + return GSL_FAILURE_NOTSUPPORTED; + } + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_init. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + kos_memset(device, 0, sizeof(gsl_device_t)); + + // if device configuration is present + if (kgsl_hal_getdevconfig(device_id, &config) == GSL_SUCCESS) + { + kgsl_device_getfunctable(device_id, &device->ftbl); + + kos_memcpy(&device->regspace, &config.regspace, sizeof(gsl_memregion_t)); +#ifdef GSL_BLD_YAMATO + kos_memcpy(&device->gmemspace, &config.gmemspace, sizeof(gsl_memregion_t)); +#endif // GSL_BLD_YAMATO + + device->refcnt = 0; + device->id = device_id; + +#ifndef GSL_NO_MMU + device->mmu.config = config.mmu_config; + device->mmu.mpu_base = config.mpu_base; + device->mmu.mpu_range = config.mpu_range; + device->mmu.va_base = config.va_base; + device->mmu.va_range = config.va_range; +#endif + + if (device->ftbl.device_init) + { + status = device->ftbl.device_init(device); + } + else + { + status = GSL_FAILURE_NOTINITIALIZED; + } + + // allocate memory store + status = kgsl_sharedmem_alloc0(device->id, GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_CONPHYS, sizeof(gsl_devmemstore_t), &device->memstore); + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + // dumpx needs this to be in EMEM0 aperture + kgsl_sharedmem_free0(&device->memstore, GSL_CALLER_PROCESSID_GET()); + status = kgsl_sharedmem_alloc0(device->id, GSL_MEMFLAGS_ALIGNPAGE, sizeof(gsl_devmemstore_t), &device->memstore); + }); + + if (status != GSL_SUCCESS) + { + kgsl_device_stop(device->id); + return (status); + } + kgsl_sharedmem_set0(&device->memstore, 0, 0, device->memstore.size); + + // init memqueue + device->memqueue.head = NULL; + device->memqueue.tail = NULL; + + // init cmdstream + status = kgsl_cmdstream_init(device); + if (status != GSL_SUCCESS) + { + kgsl_device_stop(device->id); + return (status); + } + +#ifndef _LINUX + // Create timestamp event + device->timestamp_event = kos_event_create(0); + if( !device->timestamp_event ) + { + kgsl_device_stop(device->id); + return (status); + } +#else + // Create timestamp wait queue + init_waitqueue_head(&device->timestamp_waitq); +#endif + + // + // Read the chip ID after the device has been initialized. + // + device->chip_id = kgsl_hal_getchipid(device->id); + } + + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_init. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_device_close(gsl_device_t *device) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_close(gsl_device_t *device=0x%08x )\n", device ); + + if (!(device->flags & GSL_FLAGS_INITIALIZED)) { + return status; + } + + /* make sure the device is stopped before close + kgsl_device_close is only called for last running caller process + */ + while (device->refcnt > 0) { + GSL_API_MUTEX_UNLOCK(); + kgsl_device_stop(device->id); + GSL_API_MUTEX_LOCK(); + } + + // close cmdstream + status = kgsl_cmdstream_close(device); + if( status != GSL_SUCCESS ) return status; + + if (device->ftbl.device_close) { + status = device->ftbl.device_close(device); + } + + // DumpX allocates memstore from MMU aperture + if ((device->refcnt == 0) && device->memstore.hostptr + && !(gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX)) + { + kgsl_sharedmem_free0(&device->memstore, GSL_CALLER_PROCESSID_GET()); + } + +#ifndef _LINUX + // destroy timestamp event + if(device->timestamp_event) + { + kos_event_signal(device->timestamp_event); // wake up waiting threads before destroying the structure + kos_event_destroy( device->timestamp_event ); + device->timestamp_event = 0; + } +#else + wake_up_interruptible_all(&(device->timestamp_waitq)); +#endif + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_close. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_device_destroy(gsl_device_t *device) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_destroy(gsl_device_t *device=0x%08x )\n", device ); + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + if (device->ftbl.device_destroy) + { + status = device->ftbl.device_destroy(device); + } + } + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_destroy. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_device_attachcallback(gsl_device_t *device, unsigned int pid) +{ + int status = GSL_SUCCESS; + int pindex; + +#ifndef GSL_NO_MMU + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_device_attachcallback(gsl_device_t *device=0x%08x, unsigned int pid=0x%08x)\n", device, pid ); + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + if (kgsl_driver_getcallerprocessindex(pid, &pindex) == GSL_SUCCESS) + { + device->callerprocess[pindex] = pid; + + status = kgsl_mmu_attachcallback(&device->mmu, pid); + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_attachcallback. Return value: %B\n", status ); + +#else + (void)pid; + (void)device; +#endif + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_device_detachcallback(gsl_device_t *device, unsigned int pid) +{ + int status = GSL_SUCCESS; + int pindex; + +#ifndef GSL_NO_MMU + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_device_detachcallback(gsl_device_t *device=0x%08x, unsigned int pid=0x%08x)\n", device, pid ); + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + if (kgsl_driver_getcallerprocessindex(pid, &pindex) == GSL_SUCCESS) + { + status |= kgsl_mmu_detachcallback(&device->mmu, pid); + + device->callerprocess[pindex] = 0; + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_detachcallback. Return value: %B\n", status ); + +#else + (void)pid; + (void)device; +#endif + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_getproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_SUCCESS; + gsl_device_t *device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_getproperty(gsl_deviceid_t device_id=%D, gsl_property_type_t type=%d, void *value=0x08x, unsigned int sizebytes=%d)\n", device_id, type, value, sizebytes ); + + KOS_ASSERT(value); + +#ifndef _DEBUG + (void) sizebytes; // unreferenced formal parameter +#endif + + switch (type) + { + case GSL_PROP_SHMEM: + { + gsl_shmemprop_t *shem = (gsl_shmemprop_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_shmemprop_t)); + + shem->numapertures = gsl_driver.shmem.numapertures; + shem->aperture_mask = GSL_APERTURE_MASK; + shem->aperture_shift = GSL_APERTURE_SHIFT; + + break; + } + + case GSL_PROP_SHMEM_APERTURES: + { + int i; + gsl_apertureprop_t *aperture = (gsl_apertureprop_t *) value; + + KOS_ASSERT(sizebytes == (sizeof(gsl_apertureprop_t) * gsl_driver.shmem.numapertures)); + + for (i = 0; i < gsl_driver.shmem.numapertures; i++) + { + if (gsl_driver.shmem.apertures[i].memarena) + { + aperture->gpuaddr = GSL_APERTURE_GETGPUADDR(gsl_driver.shmem, i); + aperture->hostaddr = GSL_APERTURE_GETHOSTADDR(gsl_driver.shmem, i); + } + else + { + aperture->gpuaddr = 0x0; + aperture->hostaddr = 0x0; + } + aperture++; + } + + break; + } + + case GSL_PROP_DEVICE_SHADOW: + { + gsl_shadowprop_t *shadowprop = (gsl_shadowprop_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_shadowprop_t)); + + kos_memset(shadowprop, 0, sizeof(gsl_shadowprop_t)); + +#ifdef GSL_DEVICE_SHADOW_MEMSTORE_TO_USER + if (device->memstore.hostptr) + { + shadowprop->hostaddr = (unsigned int) device->memstore.hostptr; + shadowprop->size = device->memstore.size; + shadowprop->flags = GSL_FLAGS_INITIALIZED; + } +#endif // GSL_DEVICE_SHADOW_MEMSTORE_TO_USER + + break; + } + + default: + { + if (device->ftbl.device_getproperty) + { + status = device->ftbl.device_getproperty(device, type, value, sizebytes); + } + + break; + } + } + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_getproperty. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_setproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_SUCCESS; + gsl_device_t *device; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_setproperty(gsl_deviceid_t device_id=%D, gsl_property_type_t type=%d, void *value=0x08x, unsigned int sizebytes=%d)\n", device_id, type, value, sizebytes ); + + KOS_ASSERT(value); + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + if (device->ftbl.device_setproperty) + { + status = device->ftbl.device_setproperty(device, type, value, sizebytes); + } + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_setproperty. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_start(gsl_deviceid_t device_id, gsl_flags_t flags) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + gsl_hal_t *hal = (gsl_hal_t *)gsl_driver.hal; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_start(gsl_deviceid_t device_id=%D, gsl_flags_t flags=%d)\n", device_id, flags ); + + GSL_API_MUTEX_LOCK(); + + if ((GSL_DEVICE_G12 == device_id) && !(hal->has_z160)) { + GSL_API_MUTEX_UNLOCK(); + return GSL_FAILURE_NOTSUPPORTED; + } + + if ((GSL_DEVICE_YAMATO == device_id) && !(hal->has_z430)) { + GSL_API_MUTEX_UNLOCK(); + return GSL_FAILURE_NOTSUPPORTED; + } + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + kgsl_device_active(device); + + if (!(device->flags & GSL_FLAGS_INITIALIZED)) + { + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_ERROR, "ERROR: Trying to start uninitialized device.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + device->refcnt++; + + if (device->flags & GSL_FLAGS_STARTED) + { + GSL_API_MUTEX_UNLOCK(); + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + // start device in safe mode + if (flags & GSL_FLAGS_SAFEMODE) + { + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_INFO, "Running the device in safe mode.\n" ); + device->flags |= GSL_FLAGS_SAFEMODE; + } + + if (device->ftbl.device_start) + { + status = device->ftbl.device_start(device, flags); + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_stop(gsl_deviceid_t device_id) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_stop(gsl_deviceid_t device_id=%D)\n", device_id ); + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + if (device->flags & GSL_FLAGS_STARTED) + { + KOS_ASSERT(device->refcnt); + + device->refcnt--; + + if (device->refcnt == 0) + { + if (device->ftbl.device_stop) + { + status = device->ftbl.device_stop(device); + } + } + else + { + status = GSL_SUCCESS; + } + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_stop. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_idle(gsl_deviceid_t device_id, unsigned int timeout) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_idle(gsl_deviceid_t device_id=%D, unsigned int timeout=%d)\n", device_id, timeout ); + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + kgsl_device_active(device); + + if (device->ftbl.device_idle) + { + status = device->ftbl.device_idle(device, timeout); + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_idle. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_regread(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int *value) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + + +#ifdef GSL_LOG + if( offsetwords != mmRBBM_STATUS && offsetwords != mmCP_RB_RPTR ) // Would otherwise flood the log + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_regread(gsl_deviceid_t device_id=%D, unsigned int offsetwords=%R, unsigned int *value=0x%08x)\n", device_id, offsetwords, value ); +#endif + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + KOS_ASSERT(value); + KOS_ASSERT(offsetwords < device->regspace.sizebytes); + + if (device->ftbl.device_regread) + { + status = device->ftbl.device_regread(device, offsetwords, value); + } + + GSL_API_MUTEX_UNLOCK(); + +#ifdef GSL_LOG + if( offsetwords != mmRBBM_STATUS && offsetwords != mmCP_RB_RPTR ) + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_regread. Return value %B\n", status ); +#endif + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_regwrite(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int value) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_regwrite(gsl_deviceid_t device_id=%D, unsigned int offsetwords=%R, unsigned int value=0x%08x)\n", device_id, offsetwords, value ); + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + KOS_ASSERT(offsetwords < device->regspace.sizebytes); + + if (device->ftbl.device_regwrite) + { + status = device->ftbl.device_regwrite(device, offsetwords, value); + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_regwrite. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_waitirq(gsl_deviceid_t device_id, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_waitirq(gsl_deviceid_t device_id=%D, gsl_intrid_t intr_id=%d, unsigned int *count=0x%08x, unsigned int timout=0x%08x)\n", device_id, intr_id, count, timeout); + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + if (device->ftbl.device_waitirq) + { + status = device->ftbl.device_waitirq(device, intr_id, count, timeout); + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_waitirq. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_device_runpending(gsl_device_t *device) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_runpending(gsl_device_t *device=0x%08x )\n", device ); + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + if (device->ftbl.device_runpending) + { + status = device->ftbl.device_runpending(device); + } + } + + // free any pending freeontimestamps + kgsl_cmdstream_memqueue_drain(device); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_runpending. Return value %B\n", status ); + + return (status); +} + diff --git a/drivers/mxc/amd-gpu/common/gsl_drawctxt.c b/drivers/mxc/amd-gpu/common/gsl_drawctxt.c new file mode 100644 index 000000000000..afa44e618794 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_drawctxt.c @@ -0,0 +1,1796 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#ifdef _LINUX +#include +#endif + +#ifdef GSL_BLD_YAMATO + +//#define DISABLE_SHADOW_WRITES + +/* +////////////////////////////////////////////////////////////////////////////// +// +// Memory Map for Register, Constant & Instruction Shadow, and Command Buffers (34.5KB) +// +// +---------------------+------------+-------------+---+---------------------+ +// | ALU Constant Shadow | Reg Shadow | C&V Buffers |Tex| Shader Instr Shadow | +// +---------------------+------------+-------------+---+---------------------+ +// ________________________________/ \___________________ +// / \ +// +--------------+-----------+------+-----------+------------------------+ +// | Restore Regs | Save Regs | Quad | Gmem Save | Gmem Restore | unused | +// +--------------+-----------+------+-----------+------------------------+ +// +// 8K - ALU Constant Shadow (8K aligned) +// 4K - H/W Register Shadow (8K aligned) +// 9K - Command and Vertex Buffers +// - Indirect command buffer : Const/Reg restore +// - includes Loop & Bool const shadows +// - Indirect command buffer : Const/Reg save +// - Quad vertices & texture coordinates +// - Indirect command buffer : Gmem save +// - Indirect command buffer : Gmem restore +// - Unused (padding to 8KB boundary) +// <1K - Texture Constant Shadow (768 bytes) (8K aligned) +// 18K - Shader Instruction Shadow +// - 6K vertex (32 byte aligned) +// - 6K pixel (32 byte aligned) +// - 6K shared (32 byte aligned) +// +// Note: Reading constants into a shadow, one at a time using REG_TO_MEM, takes +// 3 DWORDS per DWORD transfered, plus 1 DWORD for the shadow, for a total of +// 16 bytes per constant. If the texture constants were transfered this way, +// the Command & Vertex Buffers section would extend past the 16K boundary. +// By moving the texture constant shadow area to start at 16KB boundary, we +// only require approximately 40 bytes more memory, but are able to use the +// LOAD_CONSTANT_CONTEXT shadowing feature for the textures, speeding up +// context switching. +// +// [Using LOAD_CONSTANT_CONTEXT shadowing feature for the Loop and/or Bool +// constants would require an additional 8KB each, for alignment.] +// +////////////////////////////////////////////////////////////////////////////// +*/ + +////////////////////////////////////////////////////////////////////////////// +// Constants +////////////////////////////////////////////////////////////////////////////// + + + + +#define ALU_CONSTANTS 2048 // DWORDS +#define NUM_REGISTERS 1024 // DWORDS +#ifdef DISABLE_SHADOW_WRITES + #define CMD_BUFFER_LEN 9216 // DWORDS +#else + #define CMD_BUFFER_LEN 3072 // DWORDS +#endif +#define TEX_CONSTANTS (32*6) // DWORDS +#define BOOL_CONSTANTS 8 // DWORDS +#define LOOP_CONSTANTS 56 // DWORDS +#define SHADER_INSTRUCT_LOG2 9U // 2^n == SHADER_INSTRUCTIONS + +#if defined(PM4_IM_STORE) +#define SHADER_INSTRUCT (1<=0x10000) { exp+=16; u>>=16; } + if(u>=0x100 ) { exp+=8; u>>=8; } + if(u>=0x10 ) { exp+=4; u>>=4; } + if(u>=0x4 ) { exp+=2; u>>=2; } + if(u>=0x2 ) { exp+=1; u>>=1; } + + // Calculate fraction + frac = ( uintval & ( ~( 1 << exp ) ) ) << ( 23 - exp ); + + // Exp is biased by 127 and shifted 23 bits + exp = ( exp + 127 ) << 23; + + return ( exp | frac ); +} + +////////////////////////////////////////////////////////////////////////////// +// Helper function to divide two unsigned ints and return the result as a floating point value +////////////////////////////////////////////////////////////////////////////// +unsigned int uintdivide(unsigned int a, unsigned int b) +{ +#ifdef _LINUX + uint64_t a_fixed = a << 16; + uint64_t b_fixed = b << 16; +#else + unsigned int a_fixed = a << 16; + unsigned int b_fixed = b << 16; +#endif + // Assume the result is 0.fraction + unsigned int fraction; + unsigned int exp = 126; + + if( b == 0 ) return 0; + +#ifdef _LINUX + a_fixed = a_fixed << 32; + do_div(a_fixed, b_fixed); + fraction = (unsigned int)a_fixed; +#else + fraction = ((unsigned int)((((__int64)a_fixed) << 32) / (__int64)b_fixed)); +#endif + + if( fraction == 0 ) return 0; + + // Normalize + while( !(fraction & (1<<31)) ) + { + fraction <<= 1; + exp--; + } + // Remove hidden bit + fraction <<= 1; + + // Round + if( ( fraction & 0x1ff ) > 256 ) + { + int rounded = 0; + int i = 9; + + // Do the bit addition + while( !rounded ) + { + if( fraction & (1<>= 9; + + return ( ( exp << 23 ) | fraction ); +} + + + +////////////////////////////////////////////////////////////////////////////// +// context save (gmem -> sys) +////////////////////////////////////////////////////////////////////////////// + + +////////////////////////////////////////////////////////////////////////////// +// pre-compiled vertex shader program +// +// attribute vec4 P; +// void main(void) +// { +// gl_Position = P; +// } +// +////////////////////////////////////////////////////////////////////////////// + +#define GMEM2SYS_VTX_PGM_LEN 0x12 + +static const unsigned int gmem2sys_vtx_pgm[GMEM2SYS_VTX_PGM_LEN] = { + 0x00011003, 0x00001000, 0xc2000000, + 0x00001004, 0x00001000, 0xc4000000, + 0x00001005, 0x00002000, 0x00000000, + 0x1cb81000, 0x00398a88, 0x00000003, + 0x140f803e, 0x00000000, 0xe2010100, + 0x14000000, 0x00000000, 0xe2000000 +}; + + +////////////////////////////////////////////////////////////////////////////// +// pre-compiled fragment shader program +// +// precision highp float; +// uniform vec4 clear_color; +// void main(void) +// { +// gl_FragColor = clear_color; +// } +// +////////////////////////////////////////////////////////////////////////////// + +#define GMEM2SYS_FRAG_PGM_LEN 0x0c + +static const unsigned int gmem2sys_frag_pgm[GMEM2SYS_FRAG_PGM_LEN] = { + 0x00000000, 0x1002c400, 0x10000000, + 0x00001003, 0x00002000, 0x00000000, + 0x140f8000, 0x00000000, 0x22000000, + 0x14000000, 0x00000000, 0xe2000000 +}; + + +////////////////////////////////////////////////////////////////////////////// +// context restore (sys -> gmem) +////////////////////////////////////////////////////////////////////////////// + + +////////////////////////////////////////////////////////////////////////////// +// pre-compiled vertex shader program +// +// attribute vec4 position; +// attribute vec4 texcoord; +// varying vec4 texcoord0; +// void main() +// { +// gl_Position = position; +// texcoord0 = texcoord; +// } +// +////////////////////////////////////////////////////////////////////////////// + +#define SYS2GMEM_VTX_PGM_LEN 0x18 + +static const unsigned int sys2gmem_vtx_pgm[SYS2GMEM_VTX_PGM_LEN] = { + 0x00052003, 0x00001000, 0xc2000000, 0x00001005, + 0x00001000, 0xc4000000, 0x00001006, 0x10071000, + 0x20000000, 0x18981000, 0x0039ba88, 0x00000003, + 0x12982000, 0x40257b08, 0x00000002, 0x140f803e, + 0x00000000, 0xe2010100, 0x140f8000, 0x00000000, + 0xe2020200, 0x14000000, 0x00000000, 0xe2000000 +}; + + +////////////////////////////////////////////////////////////////////////////// +// pre-compiled fragment shader program +// +// precision mediump float; +// uniform sampler2D tex0; +// varying vec4 texcoord0; +// void main() +// { +// gl_FragColor = texture2D(tex0, texcoord0.xy); +// } +// +////////////////////////////////////////////////////////////////////////////// + +#define SYS2GMEM_FRAG_PGM_LEN 0x0f + +static const unsigned int sys2gmem_frag_pgm[SYS2GMEM_FRAG_PGM_LEN] = { + 0x00011002, 0x00001000, 0xc4000000, 0x00001003, + 0x10041000, 0x20000000, 0x10000001, 0x1ffff688, + 0x00000002, 0x140f8000, 0x00000000, 0xe2000000, + 0x14000000, 0x00000000, 0xe2000000 +}; + + +////////////////////////////////////////////////////////////////////////////// +// shader texture constants (sysmem -> gmem) +////////////////////////////////////////////////////////////////////////////// + +#define SYS2GMEM_TEX_CONST_LEN 6 + +static unsigned int sys2gmem_tex_const[SYS2GMEM_TEX_CONST_LEN] = +{ + // Texture, FormatXYZW=Unsigned, ClampXYZ=Wrap/Repeat,RFMode=ZeroClamp-1,Dim=1:2d + 0x00000002, // Pitch = TBD + + // Format=6:8888_WZYX, EndianSwap=0:None, ReqSize=0:256bit, DimHi=0, NearestClamp=1:OGL Mode + 0x00000806, // Address[31:12] = TBD + + // Width, Height, EndianSwap=0:None + 0, // Width & Height = TBD + + // NumFormat=0:RF, DstSelXYZW=XYZW, ExpAdj=0, MagFilt=MinFilt=0:Point, Mip=2:BaseMap + 0 << 1 | 1 << 4 | 2 << 7 | 3 << 10 | 2 << 23, + + // VolMag=VolMin=0:Point, MinMipLvl=0, MaxMipLvl=1, LodBiasH=V=0, Dim3d=0 + 0, + + // BorderColor=0:ABGRBlack, ForceBC=0:diable, TriJuice=0, Aniso=0, Dim=1:2d, MipPacking=0 + 1 << 9 // Mip Address[31:12] = TBD +}; + + +////////////////////////////////////////////////////////////////////////////// +// quad for copying GMEM to context shadow +////////////////////////////////////////////////////////////////////////////// + +#define QUAD_LEN 12 + +static unsigned int gmem_copy_quad[QUAD_LEN] = { + 0x00000000, 0x00000000, 0x3f800000, + 0x00000000, 0x00000000, 0x3f800000, + 0x00000000, 0x00000000, 0x3f800000, + 0x00000000, 0x00000000, 0x3f800000 +}; + +#define TEXCOORD_LEN 8 + +static unsigned int gmem_copy_texcoord[TEXCOORD_LEN] = { + 0x00000000, 0x3f800000, + 0x3f800000, 0x3f800000, + 0x00000000, 0x00000000, + 0x3f800000, 0x00000000 +}; + + +////////////////////////////////////////////////////////////////////////////// +// shader linkage info +////////////////////////////////////////////////////////////////////////////// + +#define SHADER_CONST_ADDR (11 * 6 + 3) + + +////////////////////////////////////////////////////////////////////////////// +// gmem command buffer length +////////////////////////////////////////////////////////////////////////////// + +#define PM4_REG(reg) ((0x4 << 16) | (GSL_HAL_SUBBLOCK_OFFSET(reg))) + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +static void +config_gmemsize(gmem_shadow_t *shadow, int gmem_size) +{ + int w=64, h=64; // 16KB surface, minimum + + // convert from bytes to 32-bit words + gmem_size = (gmem_size + 3)/4; + + // find the right surface size, close to a square. + while (w * h < gmem_size) + if (w < h) + w *= 2; + else + h *= 2; + + shadow->width = w; + shadow->pitch = w; + shadow->height = h; + + shadow->size = shadow->pitch * shadow->height * 4; +} + + +////////////////////////////////////////////////////////////////////////////// + +static unsigned int +gpuaddr(unsigned int *cmd, gsl_memdesc_t *memdesc) +{ + return memdesc->gpuaddr + ((char *)cmd - (char *)memdesc->hostptr); +} + + +////////////////////////////////////////////////////////////////////////////// + +static void +create_ib1(gsl_drawctxt_t *drawctxt, unsigned int *cmd, unsigned int *start, unsigned int *end) +{ + cmd[0] = PM4_HDR_INDIRECT_BUFFER_PFD; + cmd[1] = gpuaddr(start, &drawctxt->gpustate); + cmd[2] = end - start; +} + + +////////////////////////////////////////////////////////////////////////////// + +static unsigned int * +program_shader(unsigned int *cmds, int vtxfrag, const unsigned int *shader_pgm, int dwords) +{ + // load the patched vertex shader stream + *cmds++ = pm4_type3_packet(PM4_IM_LOAD_IMMEDIATE, 2 + dwords); + *cmds++ = vtxfrag; // 0=vertex shader, 1=fragment shader + *cmds++ = ( (0 << 16) | dwords ); // instruction start & size (in 32-bit words) + + kos_memcpy(cmds, shader_pgm, dwords<<2); + cmds += dwords; + + return cmds; +} + + +////////////////////////////////////////////////////////////////////////////// + +static unsigned int * +reg_to_mem(unsigned int *cmds, gpuaddr_t dst, gpuaddr_t src, int dwords) +{ + while (dwords-- > 0) + { + *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmds++ = src++; + *cmds++ = dst; + dst += 4; + } + + return cmds; +} + + + +#ifdef DISABLE_SHADOW_WRITES + +static void build_reg_to_mem_range(unsigned int start, unsigned int end, unsigned int** cmd, /*ctx_t *ctx, unsigned int* offset) //*/gsl_drawctxt_t *drawctxt) +{ + unsigned int i = start; + + for(i=start; i<=end; i++) + { + *(*cmd)++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *(*cmd)++ = i | (1<<30); + *(*cmd)++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) + (i-0x2000)*4; + } +} + +#endif + +////////////////////////////////////////////////////////////////////////////// +// chicken restore +////////////////////////////////////////////////////////////////////////////// +static unsigned int* +build_chicken_restore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + unsigned int *start = ctx->cmd; + unsigned int *cmds = start; + + *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmds++ = 0; + + *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1); + ctx->chicken_restore = gpuaddr(cmds, &drawctxt->gpustate); + *cmds++ = 0x00000000; + + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->chicken_restore, start, cmds); + + return cmds; +} + + + +////////////////////////////////////////////////////////////////////////////// +// context save +////////////////////////////////////////////////////////////////////////////// + + +////////////////////////////////////////////////////////////////////////////// +// save h/w regs, alu constants, texture contants, etc. ... +// requires: bool_shadow_gpuaddr, loop_shadow_gpuaddr +////////////////////////////////////////////////////////////////////////////// + +static void +build_regsave_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + unsigned int *start = ctx->cmd; + unsigned int *cmd = start; + +#ifdef DISABLE_SHADOW_WRITES + // Write HW registers into shadow + build_reg_to_mem_range(mmRB_SURFACE_INFO, mmRB_DEPTH_INFO, &cmd, drawctxt); + build_reg_to_mem_range(mmCOHER_DEST_BASE_0, mmPA_SC_SCREEN_SCISSOR_BR, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SC_WINDOW_OFFSET, mmPA_SC_WINDOW_SCISSOR_BR, &cmd, drawctxt); + build_reg_to_mem_range(mmVGT_MAX_VTX_INDX, mmRB_FOG_COLOR, &cmd, drawctxt); + build_reg_to_mem_range(mmRB_STENCILREFMASK_BF, mmPA_CL_VPORT_ZOFFSET, &cmd, drawctxt); + build_reg_to_mem_range(mmSQ_PROGRAM_CNTL, mmSQ_WRAPPING_1, &cmd, drawctxt); + build_reg_to_mem_range(mmRB_DEPTHCONTROL, mmRB_MODECONTROL, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SU_POINT_SIZE, mmPA_SC_LINE_STIPPLE, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SC_VIZ_QUERY, mmPA_SC_VIZ_QUERY, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SC_LINE_CNTL, mmSQ_PS_CONST, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SC_AA_MASK, mmPA_SC_AA_MASK, &cmd, drawctxt); + build_reg_to_mem_range(mmVGT_VERTEX_REUSE_BLOCK_CNTL, mmRB_DEPTH_CLEAR, &cmd, drawctxt); + build_reg_to_mem_range(mmRB_SAMPLE_COUNT_CTL, mmRB_COLOR_DEST_MASK, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SU_POLY_OFFSET_FRONT_SCALE, mmPA_SU_POLY_OFFSET_BACK_OFFSET, &cmd, drawctxt); + + // Copy ALU constants + cmd = reg_to_mem(cmd, (drawctxt->gpustate.gpuaddr) & 0xFFFFE000, mmSQ_CONSTANT_0, ALU_CONSTANTS); + + // Copy Tex constants + cmd = reg_to_mem(cmd, (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000, mmSQ_FETCH_0, TEX_CONSTANTS); +#else + // H/w registers are already shadowed; just need to disable shadowing to prevent corruption. + *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); + *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000; + *cmd++ = 4 << 16; // regs, start=0 + *cmd++ = 0x0; // count = 0 + + // ALU constants are already shadowed; just need to disable shadowing to prevent corruption. + *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); + *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000; + *cmd++ = 0 << 16; // ALU, start=0 + *cmd++ = 0x0; // count = 0 + + // Tex constants are already shadowed; just need to disable shadowing to prevent corruption. + *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); + *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000; + *cmd++ = 1 << 16; // Tex, start=0 + *cmd++ = 0x0; // count = 0 +#endif + + + + + // Need to handle some of the registers separately + *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmd++ = mmSQ_GPR_MANAGEMENT; + *cmd++ = ctx->reg_values[0]; + *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmd++ = mmTP0_CHICKEN; + *cmd++ = ctx->reg_values[1]; + + // Copy Boolean constants + cmd = reg_to_mem(cmd, ctx->bool_shadow, mmSQ_CF_BOOLEANS, BOOL_CONSTANTS); + + // Copy Loop constants + cmd = reg_to_mem(cmd, ctx->loop_shadow, mmSQ_CF_LOOP, LOOP_CONSTANTS); + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->reg_save, start, cmd); + + ctx->cmd = cmd; +} + + +////////////////////////////////////////////////////////////////////////////// +// copy colour, depth, & stencil buffers from graphics memory to system memory +////////////////////////////////////////////////////////////////////////////// + +static unsigned int* +build_gmem2sys_cmds(gsl_drawctxt_t *drawctxt, ctx_t* ctx, gmem_shadow_t *shadow) +{ + unsigned int *cmds = shadow->gmem_save_commands; + unsigned int *start = cmds; + + // Store TP0_CHICKEN register + *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmds++ = mmTP0_CHICKEN; + if( ctx ) + *cmds++ = ctx->chicken_restore; + else + cmds++; + + *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmds++ = 0; + + // Set TP0_CHICKEN to zero + *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1); + *cmds++ = 0x00000000; + + // -------------- + // program shader + // -------------- + + // load shader vtx constants ... 5 dwords + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4); + *cmds++ = (0x1 << 16) | SHADER_CONST_ADDR; + *cmds++ = 0; + *cmds++ = shadow->quad_vertices.gpuaddr | 0x3; // valid(?) vtx constant flag & addr + *cmds++ = 0x00000030; // limit = 12 dwords + + // Invalidate L2 cache to make sure vertices are updated + *cmds++ = pm4_type0_packet(mmTC_CNTL_STATUS, 1); + *cmds++ = 0x1; + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4); + *cmds++ = PM4_REG(mmVGT_MAX_VTX_INDX); + *cmds++ = 0x00ffffff; //mmVGT_MAX_VTX_INDX + *cmds++ = 0x0; //mmVGT_MIN_VTX_INDX + *cmds++ = 0x00000000; //mmVGT_INDX_OFFSET + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SC_AA_MASK); + *cmds++ = 0x0000ffff; //mmPA_SC_AA_MASK + + + // load the patched vertex shader stream + cmds = program_shader(cmds, 0, gmem2sys_vtx_pgm, GMEM2SYS_VTX_PGM_LEN); + + // Load the patched fragment shader stream + cmds = program_shader(cmds, 1, gmem2sys_frag_pgm, GMEM2SYS_FRAG_PGM_LEN); + + // SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmSQ_PROGRAM_CNTL); + *cmds++ = 0x10010001; + *cmds++ = 0x00000008; + + + // -------------- + // resolve + // -------------- + + // PA_CL_VTE_CNTL + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_CL_VTE_CNTL); + *cmds++ = 0x00000b00; // disable X/Y/Z transforms, X/Y/Z are premultiplied by W + + // change colour buffer to RGBA8888, MSAA = 1, and matching pitch + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmRB_SURFACE_INFO); + *cmds++ = drawctxt->context_gmem_shadow.pitch; // GMEM pitch is equal to context GMEM shadow pitch + + // RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0, Base=gmem_base + if( ctx ) + { + KOS_ASSERT((ctx->gmem_base & 0xFFF) == 0); // gmem base assumed 4K aligned. + *cmds++ = (COLORX_8_8_8_8 << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx->gmem_base; + } + else + cmds++; + + // disable Z + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_DEPTHCONTROL); + *cmds++ = 0; + + // set mmPA_SU_SC_MODE_CNTL + // Front_ptype = draw triangles + // Back_ptype = draw triangles + // Provoking vertex = last + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SU_SC_MODE_CNTL); + *cmds++ = 0x00080240; + + // set the scissor to the extents of the draw surface + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_SC_SCREEN_SCISSOR_TL); + *cmds++ = (0 << 16) | 0; + *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width; + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_SC_WINDOW_SCISSOR_TL); + *cmds++ = (unsigned int) ((1U << 31) | (0 << 16) | 0); + *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width; + + // load the viewport so that z scale = clear depth and z offset = 0.0f + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_CL_VPORT_ZSCALE); + *cmds++ = 0xbf800000; // -1.0f + *cmds++ = 0x0; + + // load the COPY state + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 6); + *cmds++ = PM4_REG(mmRB_COPY_CONTROL); + *cmds++ = 0; // RB_COPY_CONTROL + + *cmds++ = (shadow->gmemshadow.gpuaddr+shadow->offset*4) & 0xfffff000; // RB_COPY_DEST_BASE + + *cmds++ = shadow->pitch >> 5; // RB_COPY_DEST_PITCH + *cmds++ = 0x0003c058; // Endian=none, Linear, Format=RGBA8888,Swap=0,!Dither,MaskWrite:R=G=B=A=1 + + { + // Calculate the new offset based on the adjusted base + unsigned int addr = (shadow->gmemshadow.gpuaddr+shadow->offset*4); + unsigned int offset = (addr-(addr&0xfffff000))/4; + + kos_assert( (offset & 0xfffff000) == 0 ); // Make sure we stay in offsetx field. + + *cmds++ = offset; + } + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_MODECONTROL); + *cmds++ = 0x6; // EDRAM copy + + // queue the draw packet + *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2); + *cmds++ = 0; // viz query info. + *cmds++ = 0x00030088; // PrimType=RectList, NumIndices=3, SrcSel=AutoIndex + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, shadow->gmem_save, start, cmds); + + return cmds; +} + + +////////////////////////////////////////////////////////////////////////////// +// context restore +////////////////////////////////////////////////////////////////////////////// + + +////////////////////////////////////////////////////////////////////////////// +// copy colour, depth, & stencil buffers from system memory to graphics memory +////////////////////////////////////////////////////////////////////////////// + +static unsigned int* +build_sys2gmem_cmds(gsl_drawctxt_t *drawctxt, ctx_t* ctx, gmem_shadow_t *shadow) +{ + unsigned int *cmds = shadow->gmem_restore_commands; + unsigned int *start = cmds; + + // Store TP0_CHICKEN register + *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmds++ = mmTP0_CHICKEN; + if( ctx ) + *cmds++ = ctx->chicken_restore; + else + cmds++; + + *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmds++ = 0; + + // Set TP0_CHICKEN to zero + *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1); + *cmds++ = 0x00000000; + + // ---------------- + // shader constants + // ---------------- + + // vertex buffer constants + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 7); + + *cmds++ = (0x1 << 16) | (9 * 6); + *cmds++ = shadow->quad_vertices.gpuaddr | 0x3; // valid(?) vtx constant flag & addr + *cmds++ = 0x00000030; // limit = 12 dwords + *cmds++ = shadow->quad_texcoords.gpuaddr | 0x3; // valid(?) vtx constant flag & addr + *cmds++ = 0x00000020; // limit = 8 dwords + *cmds++ = 0; + *cmds++ = 0; + + // Invalidate L2 cache to make sure vertices and texture coordinates are updated + *cmds++ = pm4_type0_packet(mmTC_CNTL_STATUS, 1); + *cmds++ = 0x1; + + // load the patched vertex shader stream + cmds = program_shader(cmds, 0, sys2gmem_vtx_pgm, SYS2GMEM_VTX_PGM_LEN); + + // Load the patched fragment shader stream + cmds = program_shader(cmds, 1, sys2gmem_frag_pgm, SYS2GMEM_FRAG_PGM_LEN); + + // SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmSQ_PROGRAM_CNTL); + *cmds++ = 0x10030002; + *cmds++ = 0x00000008; + + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SC_AA_MASK); + *cmds++ = 0x0000ffff; //mmPA_SC_AA_MASK + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SC_VIZ_QUERY); + *cmds++ = 0x0; //mmPA_SC_VIZ_QUERY + + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_COLORCONTROL); + *cmds++ = 0x00000c20; // RB_COLORCONTROL + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4); + *cmds++ = PM4_REG(mmVGT_MAX_VTX_INDX); + *cmds++ = 0x00ffffff; //mmVGT_MAX_VTX_INDX + *cmds++ = 0x0; //mmVGT_MIN_VTX_INDX + *cmds++ = 0x00000000; //mmVGT_INDX_OFFSET + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmVGT_VERTEX_REUSE_BLOCK_CNTL); + *cmds++ = 0x00000002; //mmVGT_VERTEX_REUSE_BLOCK_CNTL + *cmds++ = 0x00000002; //mmVGT_OUT_DEALLOC_CNTL + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmSQ_INTERPOLATOR_CNTL); + //*cmds++ = 0x0000ffff; //mmSQ_INTERPOLATOR_CNTL + *cmds++ = 0xffffffff; //mmSQ_INTERPOLATOR_CNTL + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SC_AA_CONFIG); + *cmds++ = 0x00000000; //mmPA_SC_AA_CONFIG + + + // set mmPA_SU_SC_MODE_CNTL + // Front_ptype = draw triangles + // Back_ptype = draw triangles + // Provoking vertex = last + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SU_SC_MODE_CNTL); + *cmds++ = 0x00080240; + + // texture constants + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, (SYS2GMEM_TEX_CONST_LEN + 1)); + *cmds++ = (0x1 << 16) | (0 * 6); + kos_memcpy(cmds, sys2gmem_tex_const, SYS2GMEM_TEX_CONST_LEN<<2); + cmds[0] |= (shadow->pitch >> 5) << 22; + cmds[1] |= shadow->gmemshadow.gpuaddr; + cmds[2] |= (shadow->width+shadow->offset_x-1) | (shadow->height+shadow->offset_y-1) << 13; + cmds += SYS2GMEM_TEX_CONST_LEN; + + // change colour buffer to RGBA8888, MSAA = 1, and matching pitch + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmRB_SURFACE_INFO); + *cmds++ = drawctxt->context_gmem_shadow.pitch; // GMEM pitch is equal to context GMEM shadow pitch + + + // RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0, Base=gmem_base + if( ctx ) + *cmds++ = (COLORX_8_8_8_8 << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx->gmem_base; + else + cmds++; + + // RB_DEPTHCONTROL + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_DEPTHCONTROL); + *cmds++ = 0; // disable Z + + + // set the scissor to the extents of the draw surface + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_SC_SCREEN_SCISSOR_TL); + *cmds++ = (0 << 16) | 0; + *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width; + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_SC_WINDOW_SCISSOR_TL); + *cmds++ = (unsigned int) ((1U << 31) | (shadow->gmem_offset_y << 16) | shadow->gmem_offset_x); + *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width; + + // PA_CL_VTE_CNTL + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_CL_VTE_CNTL); + *cmds++ = 0x00000b00; // disable X/Y/Z transforms, X/Y/Z are premultiplied by W + + // load the viewport so that z scale = clear depth and z offset = 0.0f + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_CL_VPORT_ZSCALE); + *cmds++ = 0xbf800000; + *cmds++ = 0x0; + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_COLOR_MASK); + *cmds++ = 0x0000000f; // R = G = B = 1:enabled + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_COLOR_DEST_MASK); + *cmds++ = 0xffffffff; + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmSQ_WRAPPING_0); + *cmds++ = 0x00000000; + *cmds++ = 0x00000000; + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_MODECONTROL); + *cmds++ = 0x4; // draw pixels with color and depth/stencil component + + // queue the draw packet + *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2); + *cmds++ = 0; // viz query info. + *cmds++ = 0x00030088; // PrimType=RectList, NumIndices=3, SrcSel=AutoIndex + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, shadow->gmem_restore, start, cmds); + + return cmds; +} + + +////////////////////////////////////////////////////////////////////////////// +// restore h/w regs, alu constants, texture constants, etc. ... +////////////////////////////////////////////////////////////////////////////// + +static unsigned * +reg_range(unsigned int *cmd, unsigned int start, unsigned int end) +{ + *cmd++ = PM4_REG(start); // h/w regs, start addr + *cmd++ = end - start + 1; // count + return cmd; +} + + +////////////////////////////////////////////////////////////////////////////// + +static void +build_regrestore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + unsigned int *start = ctx->cmd; + unsigned int *cmd = start; + + + //*cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + //*cmd++ = 0; + + // H/W Registers + cmd++; // deferred pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, ???); +#ifdef DISABLE_SHADOW_WRITES + *cmd++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) | 1; // Force mismatch +#else + *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000; +#endif + + cmd = reg_range(cmd, mmRB_SURFACE_INFO, mmPA_SC_SCREEN_SCISSOR_BR); + cmd = reg_range(cmd, mmPA_SC_WINDOW_OFFSET, mmPA_SC_WINDOW_SCISSOR_BR); + cmd = reg_range(cmd, mmVGT_MAX_VTX_INDX, mmPA_CL_VPORT_ZOFFSET); + cmd = reg_range(cmd, mmSQ_PROGRAM_CNTL, mmSQ_WRAPPING_1); + cmd = reg_range(cmd, mmRB_DEPTHCONTROL, mmRB_MODECONTROL); + cmd = reg_range(cmd, mmPA_SU_POINT_SIZE, mmPA_SC_VIZ_QUERY/*mmVGT_ENHANCE*/); + cmd = reg_range(cmd, mmPA_SC_LINE_CNTL, mmRB_COLOR_DEST_MASK); + cmd = reg_range(cmd, mmPA_SU_POLY_OFFSET_FRONT_SCALE, mmPA_SU_POLY_OFFSET_BACK_OFFSET); + + // Now we know how many register blocks we have, we can compute command length + start[0] = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, (cmd-start)-1); +#ifdef DISABLE_SHADOW_WRITES + start[2] |= (0<<24) | (4 << 16); // Disable shadowing. +#else + start[2] |= (1<<24) | (4 << 16); // Enable shadowing for the entire register block. +#endif + + // Need to handle some of the registers separately + *cmd++ = pm4_type0_packet(mmSQ_GPR_MANAGEMENT, 1); + ctx->reg_values[0] = gpuaddr(cmd, &drawctxt->gpustate); + *cmd++ = 0x00040400; + + *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmd++ = 0; + *cmd++ = pm4_type0_packet(mmTP0_CHICKEN, 1); + ctx->reg_values[1] = gpuaddr(cmd, &drawctxt->gpustate); + *cmd++ = 0x00000000; + + // ALU Constants + *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); + *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000; +#ifdef DISABLE_SHADOW_WRITES + *cmd++ = (0<<24) | (0<<16) | 0; // Disable shadowing +#else + *cmd++ = (1<<24) | (0<<16) | 0; +#endif + *cmd++ = ALU_CONSTANTS; + + + // Texture Constants + *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); + *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000; +#ifdef DISABLE_SHADOW_WRITES + *cmd++ = (0<<24) | (1<<16) | 0; // Disable shadowing +#else + *cmd++ = (1<<24) | (1<<16) | 0; +#endif + *cmd++ = TEX_CONSTANTS; + + + // Boolean Constants + *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + BOOL_CONSTANTS); + *cmd++ = (2<<16) | 0; + + // the next BOOL_CONSTANT dwords is the shadow area for boolean constants. + ctx->bool_shadow = gpuaddr(cmd, &drawctxt->gpustate); + cmd += BOOL_CONSTANTS; + + + // Loop Constants + *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + LOOP_CONSTANTS); + *cmd++ = (3<<16) | 0; + + // the next LOOP_CONSTANTS dwords is the shadow area for loop constants. + ctx->loop_shadow = gpuaddr(cmd, &drawctxt->gpustate); + cmd += LOOP_CONSTANTS; + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->reg_restore, start, cmd); + + ctx->cmd = cmd; +} + + +////////////////////////////////////////////////////////////////////////////// +// quad for saving/restoring gmem +////////////////////////////////////////////////////////////////////////////// + +static void set_gmem_copy_quad( gmem_shadow_t* shadow ) +{ + unsigned int tex_offset[2]; + + // set vertex buffer values + + gmem_copy_quad[1] = uint2float( shadow->height + shadow->gmem_offset_y ); + gmem_copy_quad[3] = uint2float( shadow->width + shadow->gmem_offset_x ); + gmem_copy_quad[4] = uint2float( shadow->height + shadow->gmem_offset_y ); + gmem_copy_quad[9] = uint2float( shadow->width + shadow->gmem_offset_x ); + + gmem_copy_quad[0] = uint2float( shadow->gmem_offset_x ); + gmem_copy_quad[6] = uint2float( shadow->gmem_offset_x ); + gmem_copy_quad[7] = uint2float( shadow->gmem_offset_y ); + gmem_copy_quad[10] = uint2float( shadow->gmem_offset_y ); + + tex_offset[0] = uintdivide( shadow->offset_x, (shadow->offset_x+shadow->width) ); + tex_offset[1] = uintdivide( shadow->offset_y, (shadow->offset_y+shadow->height) ); + + gmem_copy_texcoord[0] = gmem_copy_texcoord[4] = tex_offset[0]; + gmem_copy_texcoord[5] = gmem_copy_texcoord[7] = tex_offset[1]; + + // copy quad data to vertex buffer + kos_memcpy(shadow->quad_vertices.hostptr, gmem_copy_quad, QUAD_LEN << 2); + + // copy tex coord data to tex coord buffer + kos_memcpy(shadow->quad_texcoords.hostptr, gmem_copy_texcoord, TEXCOORD_LEN << 2); +} + + +static void +build_quad_vtxbuff(gsl_drawctxt_t *drawctxt, ctx_t *ctx, gmem_shadow_t* shadow) +{ + unsigned int *cmd = ctx->cmd; + + // quad vertex buffer location + shadow->quad_vertices.hostptr = cmd; + shadow->quad_vertices.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate); + cmd += QUAD_LEN; + + // tex coord buffer location (in GPU space) + shadow->quad_texcoords.hostptr = cmd; + shadow->quad_texcoords.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate); + + + cmd += TEXCOORD_LEN; + + set_gmem_copy_quad(shadow); + + + ctx->cmd = cmd; +} + + +////////////////////////////////////////////////////////////////////////////// + +static void +build_shader_save_restore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + unsigned int *cmd = ctx->cmd; + unsigned int *save, *restore, *fixup; +#if defined(PM4_IM_STORE) + unsigned int *startSizeVtx, *startSizePix, *startSizeShared; +#endif + unsigned int *partition1; + unsigned int *shaderBases, *partition2; + +#if defined(PM4_IM_STORE) + // compute vertex, pixel and shared instruction shadow GPU addresses + ctx->shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET; + ctx->shader_pixel = ctx->shader_vertex + SHADER_SHADOW_SIZE; + ctx->shader_shared = ctx->shader_pixel + SHADER_SHADOW_SIZE; +#endif + + + //------------------------------------------------------------------- + // restore shader partitioning and instructions + //------------------------------------------------------------------- + + restore = cmd; // start address + + // Invalidate Vertex & Pixel instruction code address and sizes + *cmd++ = pm4_type3_packet(PM4_INVALIDATE_STATE, 1); + *cmd++ = 0x00000300; // 0x100 = Vertex, 0x200 = Pixel + + // Restore previous shader vertex & pixel instruction bases. + *cmd++ = pm4_type3_packet(PM4_SET_SHADER_BASES, 1); + shaderBases = cmd++; // TBD #5: shader bases (from fixup) + + // write the shader partition information to a scratch register + *cmd++ = pm4_type0_packet(mmSQ_INST_STORE_MANAGMENT, 1); + partition1 = cmd++; // TBD #4a: partition info (from save) + +#if defined(PM4_IM_STORE) + // load vertex shader instructions from the shadow. + *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); + *cmd++ = ctx->shader_vertex + 0x0; // 0x0 = Vertex + startSizeVtx = cmd++; // TBD #1: start/size (from save) + + // load pixel shader instructions from the shadow. + *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); + *cmd++ = ctx->shader_pixel + 0x1; // 0x1 = Pixel + startSizePix = cmd++; // TBD #2: start/size (from save) + + // load shared shader instructions from the shadow. + *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); + *cmd++ = ctx->shader_shared + 0x2; // 0x2 = Shared + startSizeShared = cmd++; // TBD #3: start/size (from save) +#endif + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->shader_restore, restore, cmd); + + + //------------------------------------------------------------------- + // fixup SET_SHADER_BASES data + // + // since self-modifying PM4 code is being used here, a seperate + // command buffer is used for this fixup operation, to ensure the + // commands are not read by the PM4 engine before the data fields + // have been written. + //------------------------------------------------------------------- + + fixup = cmd; // start address + + // write the shader partition information to a scratch register + *cmd++ = pm4_type0_packet(mmSCRATCH_REG2, 1); + partition2 = cmd++; // TBD #4b: partition info (from save) + + // mask off unused bits, then OR with shader instruction memory size + *cmd++ = pm4_type3_packet(PM4_REG_RMW, 3); + *cmd++ = mmSCRATCH_REG2; + *cmd++ = 0x0FFF0FFF; // AND off invalid bits. + *cmd++ = (unsigned int)((SHADER_INSTRUCT_LOG2-5U) << 29); // OR in instruction memory size + + // write the computed value to the SET_SHADER_BASES data field + *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmd++ = mmSCRATCH_REG2; + *cmd++ = gpuaddr(shaderBases, &drawctxt->gpustate); // TBD #5: shader bases (to restore) + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->shader_fixup, fixup, cmd); + + + //------------------------------------------------------------------- + // save shader partitioning and instructions + //------------------------------------------------------------------- + + save = cmd; // start address + + *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmd++ = 0; + + // Fetch the SQ_INST_STORE_MANAGMENT register value, + // Store the value in the data fields of the SET_CONSTANT commands above. + *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmd++ = mmSQ_INST_STORE_MANAGMENT; + *cmd++ = gpuaddr(partition1, &drawctxt->gpustate); // TBD #4a: partition info (to restore) + *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmd++ = mmSQ_INST_STORE_MANAGMENT; + *cmd++ = gpuaddr(partition2, &drawctxt->gpustate); // TBD #4b: partition info (to fixup) + +#if defined(PM4_IM_STORE) + // Store the vertex shader instructions + *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); + *cmd++ = ctx->shader_vertex + 0x0; // 0x0 = Vertex + *cmd++ = gpuaddr(startSizeVtx, &drawctxt->gpustate); // TBD #1: start/size (to restore) + + // store the pixel shader instructions + *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); + *cmd++ = ctx->shader_pixel + 0x1; // 0x1 = Pixel + *cmd++ = gpuaddr(startSizePix, &drawctxt->gpustate); // TBD #2: start/size (to restore) + + // Store the shared shader instructions + *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); + *cmd++ = ctx->shader_shared + 0x2; // 0x2 = Shared + *cmd++ = gpuaddr(startSizeShared, &drawctxt->gpustate); // TBD #3: start/size (to restore) +#endif + + *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmd++ = 0; + + + + // Create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->shader_save, save, cmd); + + + ctx->cmd = cmd; +} + + + +////////////////////////////////////////////////////////////////////////////// +// create buffers for saving/restoring registers and constants +////////////////////////////////////////////////////////////////////////////// + +static int +create_gpustate_shadow(gsl_device_t *device, gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + gsl_flags_t flags; + + flags = (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGN8K); + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = (GSL_MEMFLAGS_EMEM | GSL_MEMFLAGS_ALIGN8K)); + + // allocate memory to allow HW to save sub-blocks for efficient context save/restore + if (kgsl_sharedmem_alloc0(device->id, flags, CONTEXT_SIZE, &drawctxt->gpustate) != GSL_SUCCESS) + return GSL_FAILURE; + + drawctxt->flags |= CTXT_FLAGS_STATE_SHADOW; + + // Blank out h/w register, constant, and command buffer shadows. + kgsl_sharedmem_set0(&drawctxt->gpustate, 0, 0, CONTEXT_SIZE); + + // set-up command and vertex buffer pointers + ctx->cmd = ctx->start = (unsigned int *) ((char *)drawctxt->gpustate.hostptr + CMD_OFFSET); + + // build indirect command buffers to save & restore regs/constants + build_regrestore_cmds(drawctxt, ctx); + build_regsave_cmds(drawctxt, ctx); + + build_shader_save_restore_cmds(drawctxt, ctx); + + return GSL_SUCCESS; +} + + +////////////////////////////////////////////////////////////////////////////// +// Allocate GMEM shadow buffer +////////////////////////////////////////////////////////////////////////////// +static int +allocate_gmem_shadow_buffer(gsl_device_t *device, gsl_drawctxt_t *drawctxt) +{ + // allocate memory for GMEM shadow + if (kgsl_sharedmem_alloc0(device->id, (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGN8K), + drawctxt->context_gmem_shadow.size, &drawctxt->context_gmem_shadow.gmemshadow) != GSL_SUCCESS) + return GSL_FAILURE; + + // blank out gmem shadow. + kgsl_sharedmem_set0(&drawctxt->context_gmem_shadow.gmemshadow, 0, 0, drawctxt->context_gmem_shadow.size); + + return GSL_SUCCESS; +} + + +////////////////////////////////////////////////////////////////////////////// +// create GMEM save/restore specific stuff +////////////////////////////////////////////////////////////////////////////// + +static int +create_gmem_shadow(gsl_device_t *device, gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + unsigned int i; + config_gmemsize(&drawctxt->context_gmem_shadow, device->gmemspace.sizebytes); + ctx->gmem_base = device->gmemspace.gpu_base; + + if( drawctxt->flags & CTXT_FLAGS_GMEM_SHADOW ) + { + if( allocate_gmem_shadow_buffer(device, drawctxt) != GSL_SUCCESS ) + return GSL_FAILURE; + } + else + { + kos_memset( &drawctxt->context_gmem_shadow.gmemshadow, 0, sizeof( gsl_memdesc_t ) ); + } + + // build quad vertex buffer + build_quad_vtxbuff(drawctxt, ctx, &drawctxt->context_gmem_shadow); + + // build TP0_CHICKEN register restore command buffer + ctx->cmd = build_chicken_restore_cmds(drawctxt, ctx); + + // build indirect command buffers to save & restore gmem + drawctxt->context_gmem_shadow.gmem_save_commands = ctx->cmd; + ctx->cmd = build_gmem2sys_cmds(drawctxt, ctx, &drawctxt->context_gmem_shadow); + drawctxt->context_gmem_shadow.gmem_restore_commands = ctx->cmd; + ctx->cmd = build_sys2gmem_cmds(drawctxt, ctx, &drawctxt->context_gmem_shadow); + + for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ ) + { + // build quad vertex buffer + build_quad_vtxbuff(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]); + + // build indirect command buffers to save & restore gmem + drawctxt->user_gmem_shadow[i].gmem_save_commands = ctx->cmd; + ctx->cmd = build_gmem2sys_cmds(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]); + + drawctxt->user_gmem_shadow[i].gmem_restore_commands = ctx->cmd; + ctx->cmd = build_sys2gmem_cmds(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]); + } + + return GSL_SUCCESS; +} + + +////////////////////////////////////////////////////////////////////////////// +// init draw context +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_drawctxt_init(gsl_device_t *device) +{ + return (GSL_SUCCESS); +} + + +////////////////////////////////////////////////////////////////////////////// +// close draw context +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_drawctxt_close(gsl_device_t *device) +{ + return (GSL_SUCCESS); +} + + +////////////////////////////////////////////////////////////////////////////// +// create a new drawing context +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_drawctxt_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags) +{ + gsl_drawctxt_t *drawctxt; + int index; + ctx_t ctx; + + kgsl_device_active(device); + + if (device->drawctxt_count >= GSL_CONTEXT_MAX) + { + return (GSL_FAILURE); + } + + // find a free context slot + index = 0; + while (index < GSL_CONTEXT_MAX) + { + if (device->drawctxt[index].flags == CTXT_FLAGS_NOT_IN_USE) + break; + + index++; + } + + if (index >= GSL_CONTEXT_MAX) + { + return (GSL_FAILURE); + } + + drawctxt = &device->drawctxt[index]; + + kos_memset( &drawctxt->context_gmem_shadow, 0, sizeof( gmem_shadow_t ) ); + + drawctxt->pid = GSL_CALLER_PROCESSID_GET(); + drawctxt->flags = CTXT_FLAGS_IN_USE; + drawctxt->type = type; + + device->drawctxt_count++; + + // create context shadows, when not running in safe mode + if (!(device->flags & GSL_FLAGS_SAFEMODE)) + { + if (create_gpustate_shadow(device, drawctxt, &ctx) != GSL_SUCCESS) + { + kgsl_drawctxt_destroy(device, index); + return (GSL_FAILURE); + } + + // Save the shader instruction memory on context switching + drawctxt->flags |= CTXT_FLAGS_SHADER_SAVE; + + if(!(flags & GSL_CONTEXT_NO_GMEM_ALLOC)) + drawctxt->flags |= CTXT_FLAGS_GMEM_SHADOW; + + // Clear out user defined GMEM shadow buffer structs + kos_memset( drawctxt->user_gmem_shadow, 0, sizeof(gmem_shadow_t)*GSL_MAX_GMEM_SHADOW_BUFFERS ); + + // create gmem shadow + if (create_gmem_shadow(device, drawctxt, &ctx) != GSL_SUCCESS) + { + kgsl_drawctxt_destroy(device, index); + return (GSL_FAILURE); + } + + + KOS_ASSERT(ctx.cmd - ctx.start <= CMD_BUFFER_LEN); + } + + *drawctxt_id = index; + + return (GSL_SUCCESS); +} + + +////////////////////////////////////////////////////////////////////////////// +// destroy a drawing context +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_drawctxt_destroy(gsl_device_t* device, unsigned int drawctxt_id) +{ + gsl_drawctxt_t *drawctxt; + + drawctxt = &device->drawctxt[drawctxt_id]; + + if (drawctxt->flags != CTXT_FLAGS_NOT_IN_USE) + { + // deactivate context + if (device->drawctxt_active == drawctxt) + { + // no need to save GMEM or shader, the context is being destroyed. + drawctxt->flags &= ~(CTXT_FLAGS_GMEM_SAVE | CTXT_FLAGS_SHADER_SAVE); + + kgsl_drawctxt_switch(device, GSL_CONTEXT_NONE, 0); + } + + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + + // destroy state shadow, if allocated + if (drawctxt->flags & CTXT_FLAGS_STATE_SHADOW) + kgsl_sharedmem_free0(&drawctxt->gpustate, GSL_CALLER_PROCESSID_GET()); + + + // destroy gmem shadow, if allocated + if (drawctxt->context_gmem_shadow.gmemshadow.size > 0) + { + kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET()); + drawctxt->context_gmem_shadow.gmemshadow.size = 0; + } + + drawctxt->flags = CTXT_FLAGS_NOT_IN_USE; + drawctxt->pid = 0; + + device->drawctxt_count--; + KOS_ASSERT(device->drawctxt_count >= 0); + } + + return (GSL_SUCCESS); +} + +////////////////////////////////////////////////////////////////////////////// +// Binds a user specified buffer as GMEM shadow area +// +// gmem_rect: defines the rectangle that is copied from GMEM. X and Y +// coordinates need to be multiples of 8 after conversion to 32bpp. +// X, Y, width, and height need to be at 32-bit boundary to avoid +// rounding. +// +// shadow_x & shadow_y: Position in GMEM shadow buffer where the contents of +// gmem_rect is copied. Both must be multiples of 8 after +// conversion to 32bpp. They also need to be at 32-bit +// boundary to avoid rounding. +// +// shadow_buffer: Description of the GMEM shadow buffer. BPP needs to be +// 8, 16, 32, 64, or 128. Enabled tells if the buffer is +// used or not (values 0 and 1). All the other buffer +// parameters are ignored when enabled=0. +// +// buffer_id: Two different buffers can be defined. Use buffer IDs 0 and 1. +// +// +////////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id) +{ + gsl_device_t *device; + gsl_drawctxt_t *drawctxt; + gmem_shadow_t *shadow; // Shadow struct being modified + unsigned int i; + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + drawctxt = &device->drawctxt[drawctxt_id]; + + shadow = &drawctxt->user_gmem_shadow[buffer_id]; + + if( !shadow_buffer->enabled ) + { + // Disable shadow + shadow->gmemshadow.size = 0; + } + else + { + // Binding to a buffer + unsigned int width, height, gmem_x, gmem_y, gmem_width, gmem_height, pixel_ratio; + + KOS_ASSERT(shadow_buffer->stride_bytes%4 == 0); + + // Convert to 32bpp pixel units + if( shadow_buffer->bpp <= 32 ) + { + KOS_ASSERT(32%shadow_buffer->bpp==0); + pixel_ratio = 32/shadow_buffer->bpp; + KOS_ASSERT(gmem_rect->x%pixel_ratio==0); // Needs to be at 32bit boundary + gmem_x = gmem_rect->x/pixel_ratio; + KOS_ASSERT(gmem_x%8==0); // Needs to be a multiple of 8 + KOS_ASSERT(gmem_rect->y%pixel_ratio==0); // Needs to be at 32bit boundary + gmem_y = gmem_rect->y/pixel_ratio; + KOS_ASSERT(gmem_y%8==0); // Needs to be a multiple of 8 + KOS_ASSERT(gmem_rect->width%pixel_ratio==0); // Needs to be at 32bit boundary + gmem_width = gmem_rect->width/pixel_ratio; + KOS_ASSERT(gmem_rect->height%pixel_ratio==0); // Needs to be at 32bit boundary + gmem_height = gmem_rect->height/pixel_ratio; + KOS_ASSERT(shadow_x%pixel_ratio==0); // Needs to be at 32bit boundary + shadow_x = shadow_x/pixel_ratio; + KOS_ASSERT(shadow_x%8==0); // Needs to be a multiple of 8 + KOS_ASSERT(shadow_y%pixel_ratio==0); // Needs to be at 32bit boundary + shadow_y = shadow_y/pixel_ratio; + KOS_ASSERT(shadow_y%8==0); // Needs to be a multiple of 8 + } + else + { + KOS_ASSERT(shadow_buffer->bpp==64 || shadow_buffer->bpp==128); + pixel_ratio = shadow_buffer->bpp/32; + gmem_x = gmem_rect->x*pixel_ratio; + KOS_ASSERT(gmem_x%8==0); // Needs to be a multiple of 8 + gmem_y = gmem_rect->y*pixel_ratio; + KOS_ASSERT(gmem_y%8==0); // Needs to be a multiple of 8 + gmem_width = gmem_rect->width*pixel_ratio; + gmem_height = gmem_rect->height*pixel_ratio; + shadow_x = shadow_x*pixel_ratio; + KOS_ASSERT(shadow_x%8==0); // Needs to be a multiple of 8 + shadow_y = shadow_y*pixel_ratio; + KOS_ASSERT(shadow_y%8==0); // Needs to be a multiple of 8 + } + + KOS_ASSERT( buffer_id >= 0 && buffer_id < GSL_MAX_GMEM_SHADOW_BUFFERS ); + + width = gmem_width < drawctxt->context_gmem_shadow.width ? gmem_width : drawctxt->context_gmem_shadow.width; + height = gmem_height < drawctxt->context_gmem_shadow.height ? gmem_height : drawctxt->context_gmem_shadow.height; + + drawctxt->user_gmem_shadow[buffer_id].width = width; + drawctxt->user_gmem_shadow[buffer_id].height = height; + drawctxt->user_gmem_shadow[buffer_id].pitch = shadow_buffer->stride_bytes/4; + + kos_memcpy( &drawctxt->user_gmem_shadow[buffer_id].gmemshadow, &shadow_buffer->data, sizeof( gsl_memdesc_t ) ); + // Calculate offset + drawctxt->user_gmem_shadow[buffer_id].offset = (int)shadow_buffer->stride_bytes/4*((int)shadow_y-(int)gmem_y)+(int)shadow_x-(int)gmem_x; + + drawctxt->user_gmem_shadow[buffer_id].offset_x = shadow_x; + drawctxt->user_gmem_shadow[buffer_id].offset_y = shadow_y; + drawctxt->user_gmem_shadow[buffer_id].gmem_offset_x = gmem_x; + drawctxt->user_gmem_shadow[buffer_id].gmem_offset_y = gmem_y; + + drawctxt->user_gmem_shadow[buffer_id].size = drawctxt->user_gmem_shadow[buffer_id].gmemshadow.size; + + // Modify quad vertices + set_gmem_copy_quad(shadow); + + // Modify commands + build_gmem2sys_cmds(drawctxt, NULL, shadow); + build_sys2gmem_cmds(drawctxt, NULL, shadow); + + // Release context GMEM shadow if found + if (drawctxt->context_gmem_shadow.gmemshadow.size > 0) + { + kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET()); + drawctxt->context_gmem_shadow.gmemshadow.size = 0; + } + } + + // Enable GMEM shadowing if we have any of the user buffers enabled + drawctxt->flags &= ~CTXT_FLAGS_GMEM_SHADOW; + for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ ) + { + if( drawctxt->user_gmem_shadow[i].gmemshadow.size > 0 ) + { + drawctxt->flags |= CTXT_FLAGS_GMEM_SHADOW; + } + } + + GSL_API_MUTEX_UNLOCK(); + + return (GSL_SUCCESS); +} + + + +////////////////////////////////////////////////////////////////////////////// +// switch drawing contexts +////////////////////////////////////////////////////////////////////////////// + +void +kgsl_drawctxt_switch(gsl_device_t *device, gsl_drawctxt_t *drawctxt, gsl_flags_t flags) +{ + gsl_drawctxt_t *active_ctxt = device->drawctxt_active; + + if (drawctxt != GSL_CONTEXT_NONE) + { + if(0) // flags & GSL_CONTEXT_SAVE_GMEM ) + { + // Set the flag in context so that the save is done when this context is switched out. + drawctxt->flags |= CTXT_FLAGS_GMEM_SAVE; + } + else + { + // Remove GMEM saving flag from the context + drawctxt->flags &= ~CTXT_FLAGS_GMEM_SAVE; + } + } + + // already current? + if (active_ctxt == drawctxt) + { + return; + } + + // save old context, when not running in safe mode + if (active_ctxt != GSL_CONTEXT_NONE && !(device->flags & GSL_FLAGS_SAFEMODE)) + { + // save registers and constants. + kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->reg_save, 3, active_ctxt->pid); + + if (active_ctxt->flags & CTXT_FLAGS_SHADER_SAVE) + { + // save shader partitioning and instructions. + kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->shader_save, 3, active_ctxt->pid); + + // fixup shader partitioning parameter for SET_SHADER_BASES. + kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->shader_fixup, 3, active_ctxt->pid); + + active_ctxt->flags |= CTXT_FLAGS_SHADER_RESTORE; + } + + if (active_ctxt->flags & CTXT_FLAGS_GMEM_SHADOW && active_ctxt->flags & CTXT_FLAGS_GMEM_SAVE ) + { + // save gmem. (note: changes shader. shader must already be saved.) + + unsigned int i, numbuffers = 0; + + for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ ) + { + if( active_ctxt->user_gmem_shadow[i].gmemshadow.size > 0 ) + { + kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->user_gmem_shadow[i].gmem_save, 3, active_ctxt->pid); + + // Restore TP0_CHICKEN + kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->chicken_restore, 3, active_ctxt->pid); + numbuffers++; + } + } + if( numbuffers == 0 ) + { + // No user defined buffers -> use context default + kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->context_gmem_shadow.gmem_save, 3, active_ctxt->pid); + // Restore TP0_CHICKEN + kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->chicken_restore, 3, active_ctxt->pid); + } + + active_ctxt->flags |= CTXT_FLAGS_GMEM_RESTORE; + } + } + + device->drawctxt_active = drawctxt; + + // restore new context, when not running in safe mode + if (drawctxt != GSL_CONTEXT_NONE && !(device->flags & GSL_FLAGS_SAFEMODE)) + { + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, drawctxt->gpustate.gpuaddr, (unsigned int)drawctxt->gpustate.hostptr, LCC_SHADOW_SIZE + REG_SHADOW_SIZE + CMD_BUFFER_SIZE + TEX_SHADOW_SIZE , "kgsl_drawctxt_switch")); + + // restore gmem. (note: changes shader. shader must not already be restored.) + if (drawctxt->flags & CTXT_FLAGS_GMEM_RESTORE) + { + unsigned int i, numbuffers = 0; + + for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ ) + { + if( drawctxt->user_gmem_shadow[i].gmemshadow.size > 0 ) + { + kgsl_ringbuffer_issuecmds(device, 1, drawctxt->user_gmem_shadow[i].gmem_restore, 3, drawctxt->pid); + + // Restore TP0_CHICKEN + kgsl_ringbuffer_issuecmds(device, 0, drawctxt->chicken_restore, 3, drawctxt->pid); + numbuffers++; + } + } + if( numbuffers == 0 ) + { + // No user defined buffers -> use context default + kgsl_ringbuffer_issuecmds(device, 1, drawctxt->context_gmem_shadow.gmem_restore, 3, drawctxt->pid); + // Restore TP0_CHICKEN + kgsl_ringbuffer_issuecmds(device, 0, drawctxt->chicken_restore, 3, drawctxt->pid); + } + + drawctxt->flags &= ~CTXT_FLAGS_GMEM_RESTORE; + } + + // restore registers and constants. + kgsl_ringbuffer_issuecmds(device, 0, drawctxt->reg_restore, 3, drawctxt->pid); + + // restore shader instructions & partitioning. + if (drawctxt->flags & CTXT_FLAGS_SHADER_RESTORE) + { + kgsl_ringbuffer_issuecmds(device, 0, drawctxt->shader_restore, 3, drawctxt->pid); + } + } +} + + +////////////////////////////////////////////////////////////////////////////// +// destroy all drawing contexts +////////////////////////////////////////////////////////////////////////////// +int +kgsl_drawctxt_destroyall(gsl_device_t *device) +{ + int i; + gsl_drawctxt_t *drawctxt; + + for (i = 0; i < GSL_CONTEXT_MAX; i++) + { + drawctxt = &device->drawctxt[i]; + + if (drawctxt->flags != CTXT_FLAGS_NOT_IN_USE) + { + // destroy state shadow, if allocated + if (drawctxt->flags & CTXT_FLAGS_STATE_SHADOW) + kgsl_sharedmem_free0(&drawctxt->gpustate, GSL_CALLER_PROCESSID_GET()); + + // destroy gmem shadow, if allocated + if (drawctxt->context_gmem_shadow.gmemshadow.size > 0) + { + kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET()); + drawctxt->context_gmem_shadow.gmemshadow.size = 0; + } + + drawctxt->flags = CTXT_FLAGS_NOT_IN_USE; + + device->drawctxt_count--; + KOS_ASSERT(device->drawctxt_count >= 0); + } + } + + return (GSL_SUCCESS); +} + +#endif diff --git a/drivers/mxc/amd-gpu/common/gsl_driver.c b/drivers/mxc/amd-gpu/common/gsl_driver.c new file mode 100644 index 000000000000..b8c5170a1425 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_driver.c @@ -0,0 +1,329 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_PROCESSID_NONE 0x00000000 + +#define GSL_DRVFLAGS_EXTERNAL 0x10000000 +#define GSL_DRVFLAGS_INTERNAL 0x20000000 + + +////////////////////////////////////////////////////////////////////////////// +// globals +////////////////////////////////////////////////////////////////////////////// +#ifndef KGSL_USER_MODE +static gsl_flags_t gsl_driver_initialized = 0; +gsl_driver_t gsl_driver; +#else +extern gsl_flags_t gsl_driver_initialized; +extern gsl_driver_t gsl_driver; +#endif + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_driver_init0(gsl_flags_t flags, gsl_flags_t flags_debug) +{ + int status = GSL_SUCCESS; + + if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED0)) + { +#ifdef GSL_LOG + // Uncomment these to enable logging. + //kgsl_log_init(); + //kgsl_log_open_stdout( KGSL_LOG_GROUP_ALL | KGSL_LOG_LEVEL_ALL | KGSL_LOG_TIMESTAMP + // | KGSL_LOG_THREAD_ID | KGSL_LOG_PROCESS_ID ); + //kgsl_log_open_file( "c:\\kgsl_log.txt", KGSL_LOG_GROUP_ALL | KGSL_LOG_LEVEL_ALL | KGSL_LOG_TIMESTAMP + // | KGSL_LOG_THREAD_ID | KGSL_LOG_PROCESS_ID ); +#endif + kos_memset(&gsl_driver, 0, sizeof(gsl_driver_t)); + + GSL_API_MUTEX_CREATE(); + } + +#ifdef _DEBUG + // set debug flags on every entry, and prior to hal initialization + gsl_driver.flags_debug |= flags_debug; +#else + (void) flags_debug; // unref formal parameter +#endif // _DEBUG + + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + KGSL_DEBUG_DUMPX_OPEN("dumpx.tb", 0); + KGSL_DEBUG_DUMPX( BB_DUMP_ENABLE, 0, 0, 0, " "); + }); + + KGSL_DEBUG_TBDUMP_OPEN("tbdump.txt"); + + if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED0)) + { + GSL_API_MUTEX_LOCK(); + + // init hal + status = kgsl_hal_init(); + + if (status == GSL_SUCCESS) + { + gsl_driver_initialized |= flags; + gsl_driver_initialized |= GSL_FLAGS_INITIALIZED0; + } + + GSL_API_MUTEX_UNLOCK(); + } + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_driver_close0(gsl_flags_t flags) +{ + int status = GSL_SUCCESS; + + if ((gsl_driver_initialized & GSL_FLAGS_INITIALIZED0) && (gsl_driver_initialized & flags)) + { + GSL_API_MUTEX_LOCK(); + + // close hall + status = kgsl_hal_close(); + + GSL_API_MUTEX_UNLOCK(); + + GSL_API_MUTEX_FREE(); + +#ifdef GSL_LOG + kgsl_log_close(); +#endif + + gsl_driver_initialized &= ~flags; + gsl_driver_initialized &= ~GSL_FLAGS_INITIALIZED0; + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + KGSL_DEBUG_DUMPX_CLOSE(); + }); + + KGSL_DEBUG_TBDUMP_CLOSE(); + } + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_driver_init() +{ + // only an external (platform specific device driver) component should call this + + return(kgsl_driver_init0(GSL_DRVFLAGS_EXTERNAL, 0)); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_driver_close() +{ + // only an external (platform specific device driver) component should call this + + return(kgsl_driver_close0(GSL_DRVFLAGS_EXTERNAL)); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_driver_entry(gsl_flags_t flags) +{ + int status = GSL_FAILURE; + int index, i; + unsigned int pid; + + if (kgsl_driver_init0(GSL_DRVFLAGS_INTERNAL, flags) != GSL_SUCCESS) + { + return (GSL_FAILURE); + } + + kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_driver_entry( gsl_flags_t flags=%d )\n", flags ); + + GSL_API_MUTEX_LOCK(); + + pid = GSL_CALLER_PROCESSID_GET(); + + // if caller process has not already opened access + status = kgsl_driver_getcallerprocessindex(pid, &index); + if (status != GSL_SUCCESS) + { + // then, add caller pid to process table + status = kgsl_driver_getcallerprocessindex(GSL_PROCESSID_NONE, &index); + if (status == GSL_SUCCESS) + { + gsl_driver.callerprocess[index] = pid; + gsl_driver.refcnt++; + } + } + + if (status == GSL_SUCCESS) + { + if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED)) + { + // init memory apertures + status = kgsl_sharedmem_init(&gsl_driver.shmem); + if (status == GSL_SUCCESS) + { + // init devices + status = GSL_FAILURE; + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + if (kgsl_device_init(&gsl_driver.device[i], (gsl_deviceid_t)(i + 1)) == GSL_SUCCESS) { + status = GSL_SUCCESS; + } + } + } + + if (status == GSL_SUCCESS) + { + gsl_driver_initialized |= GSL_FLAGS_INITIALIZED; + } + } + + // walk through process attach callbacks + if (status == GSL_SUCCESS) + { + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + status = kgsl_device_attachcallback(&gsl_driver.device[i], pid); + if (status != GSL_SUCCESS) + { + break; + } + } + } + + // if something went wrong + if (status != GSL_SUCCESS) + { + // then, remove caller pid from process table + if (kgsl_driver_getcallerprocessindex(pid, &index) == GSL_SUCCESS) + { + gsl_driver.callerprocess[index] = GSL_PROCESSID_NONE; + gsl_driver.refcnt--; + } + } + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_driver_entry. Return value: %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_driver_exit0(unsigned int pid) +{ + int status = GSL_SUCCESS; + int index, i; + + GSL_API_MUTEX_LOCK(); + + if (gsl_driver_initialized & GSL_FLAGS_INITIALIZED) + { + if (kgsl_driver_getcallerprocessindex(pid, &index) == GSL_SUCCESS) + { + // walk through process detach callbacks + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + // Empty the freememqueue of this device + kgsl_cmdstream_memqueue_drain(&gsl_driver.device[i]); + + // Detach callback + status = kgsl_device_detachcallback(&gsl_driver.device[i], pid); + if (status != GSL_SUCCESS) + { + break; + } + } + + // last running caller process + if (gsl_driver.refcnt - 1 == 0) + { + // close devices + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + kgsl_device_close(&gsl_driver.device[i]); + } + + // shutdown memory apertures + kgsl_sharedmem_close(&gsl_driver.shmem); + + gsl_driver_initialized &= ~GSL_FLAGS_INITIALIZED; + } + + // remove caller pid from process table + gsl_driver.callerprocess[index] = GSL_PROCESSID_NONE; + gsl_driver.refcnt--; + } + } + + GSL_API_MUTEX_UNLOCK(); + + if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED)) + { + kgsl_driver_close0(GSL_DRVFLAGS_INTERNAL); + } + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_driver_exit(void) +{ + int status; + + kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_driver_exit()\n" ); + + status = kgsl_driver_exit0(GSL_CALLER_PROCESSID_GET()); + + kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_driver_exit(). Return value: %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_driver_destroy(unsigned int pid) +{ + return (kgsl_driver_exit0(pid)); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_g12.c b/drivers/mxc/amd-gpu/common/gsl_g12.c new file mode 100644 index 000000000000..14cfdb61b6a1 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_g12.c @@ -0,0 +1,993 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#include "kos_libapi.h" +#include "gsl_cmdstream.h" +#ifdef _LINUX +#include +#endif + +#ifdef GSL_BLD_G12 +#define GSL_TIMESTAMP_EPSILON 20000 +#define GSL_IRQ_TIMEOUT 200 + + +//---------------------------------------------------------------------------- + +#define GSL_HAL_NUMCMDBUFFERS 5 +#define GSL_HAL_CMDBUFFERSIZE (1024 + 13) * sizeof(unsigned int) + +#define ALIGN_IN_BYTES( dim, alignment ) ( ( (dim) + (alignment-1) ) & ~(alignment-1) ) + + +#ifdef _Z180 +#define NUMTEXUNITS 4 +#define TEXUNITREGCOUNT 25 +#define VG_REGCOUNT 0x39 +#define GSL_HAL_EDGE0BUFSIZE 0x3E8+64 +#define GSL_HAL_EDGE1BUFSIZE 0x8000+64 +#define GSL_HAL_EDGE2BUFSIZE 0x80020+64 +#define GSL_HAL_EDGE0REG ADDR_VGV1_CBUF +#define GSL_HAL_EDGE1REG ADDR_VGV1_BBUF +#define GSL_HAL_EDGE2REG ADDR_VGV1_EBUF +#else +#define NUMTEXUNITS 2 +#define TEXUNITREGCOUNT 24 +#define VG_REGCOUNT 0x3A +#define L1TILESIZE 64 +#define GSL_HAL_EDGE0BUFSIZE L1TILESIZE*L1TILESIZE*4+64 +#define GSL_HAL_EDGE1BUFSIZE L1TILESIZE*L1TILESIZE*16+64 +#define GSL_HAL_EDGE0REG ADDR_VGV1_CBASE1 +#define GSL_HAL_EDGE1REG ADDR_VGV1_UBASE2 +#endif + +#define PACKETSIZE_BEGIN 3 +#define PACKETSIZE_G2DCOLOR 2 +#define PACKETSIZE_TEXUNIT (TEXUNITREGCOUNT*2) +#define PACKETSIZE_REG (VG_REGCOUNT*2) +#define PACKETSIZE_STATE (PACKETSIZE_TEXUNIT*NUMTEXUNITS + PACKETSIZE_REG + PACKETSIZE_BEGIN + PACKETSIZE_G2DCOLOR) +#define PACKETSIZE_STATESTREAM ALIGN_IN_BYTES((PACKETSIZE_STATE*sizeof(unsigned int)), 32) / sizeof(unsigned int) + +//---------------------------------------------------------------------------- + +typedef struct +{ + unsigned int id; + // unsigned int regs[]; +}gsl_hal_z1xxdrawctx_t; + +typedef struct +{ + unsigned int offs; + unsigned int curr; + unsigned int prevctx; + + gsl_memdesc_t e0; + gsl_memdesc_t e1; + gsl_memdesc_t e2; + unsigned int* cmdbuf[GSL_HAL_NUMCMDBUFFERS]; + gsl_memdesc_t cmdbufdesc[GSL_HAL_NUMCMDBUFFERS]; + gsl_timestamp_t timestamp[GSL_HAL_NUMCMDBUFFERS]; + + unsigned int numcontext; +}gsl_z1xx_t; + +static gsl_z1xx_t g_z1xx = {0}; + +extern int z160_version; + +//---------------------------------------------------------------------------- + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +static int kgsl_g12_addtimestamp(gsl_device_t* device, gsl_timestamp_t *timestamp); +static int kgsl_g12_issueibcmds(gsl_device_t* device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags); +static int kgsl_g12_context_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags); +static int kgsl_g12_context_destroy(gsl_device_t* device, unsigned int drawctxt_id); +static unsigned int drawctx_id = 0; +static int kgsl_g12_idle(gsl_device_t *device, unsigned int timeout); +#ifndef _LINUX +static void irq_thread(void); +#endif + +//---------------------------------------------------------------------------- + +void +kgsl_g12_intrcallback(gsl_intrid_t id, void *cookie) +{ + gsl_device_t *device = (gsl_device_t *) cookie; + + switch(id) + { + // non-error condition interrupt + case GSL_INTR_G12_G2D: +#ifdef _LINUX + queue_work(device->irq_workq, &(device->irq_work)); + break; +#endif +#ifndef _Z180 + case GSL_INTR_G12_FBC: +#endif //_Z180 + // signal intr completion event + kos_event_signal(device->intr.evnt[id]); + break; + + // error condition interrupt + case GSL_INTR_G12_FIFO: + device->ftbl.device_destroy(device); + break; + + case GSL_INTR_G12_MH: + // don't do anything. this is handled by the MMU manager + break; + + default: + break; + } +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_isr(gsl_device_t *device) +{ + unsigned int status; +#ifdef _DEBUG + REG_MH_MMU_PAGE_FAULT page_fault = {0}; + REG_MH_AXI_ERROR axi_error = {0}; +#endif // DEBUG + + // determine if G12 is interrupting + device->ftbl.device_regread(device, (ADDR_VGC_IRQSTATUS >> 2), &status); + + if (status) + { + // if G12 MH is interrupting, clear MH block interrupt first, then master G12 MH interrupt + if (status & (1 << VGC_IRQSTATUS_MH_FSHIFT)) + { +#ifdef _DEBUG + // obtain mh error information + device->ftbl.device_regread(device, ADDR_MH_MMU_PAGE_FAULT, (unsigned int *)&page_fault); + device->ftbl.device_regread(device, ADDR_MH_AXI_ERROR, (unsigned int *)&axi_error); +#endif // DEBUG + + kgsl_intr_decode(device, GSL_INTR_BLOCK_G12_MH); + } + + kgsl_intr_decode(device, GSL_INTR_BLOCK_G12); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_tlbinvalidate(gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid) +{ +#ifndef GSL_NO_MMU + REG_MH_MMU_INVALIDATE mh_mmu_invalidate = {0}; + + // unreferenced formal parameter + (void) pid; + + mh_mmu_invalidate.INVALIDATE_ALL = 1; + mh_mmu_invalidate.INVALIDATE_TC = 1; + + device->ftbl.device_regwrite(device, reg_invalidate, *(unsigned int *) &mh_mmu_invalidate); +#else + (void)device; + (void)reg_invalidate; +#endif + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_setpagetable(gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid) +{ + // unreferenced formal parameter + (void) pid; +#ifndef GSL_NO_MMU + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + device->ftbl.device_regwrite(device, reg_ptbase, ptbase); +#else + (void)device; + (void)reg_ptbase; + (void)reg_varange; +#endif + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +#ifdef _LINUX +static void kgsl_g12_updatetimestamp(gsl_device_t *device) +{ + unsigned int count = 0; + device->ftbl.device_regread(device, (ADDR_VGC_IRQ_ACTIVE_CNT >> 2), &count); + count >>= 8; + count &= 255; + device->timestamp += count; + kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), &device->timestamp, 4, 0); +} + +//---------------------------------------------------------------------------- + +static void kgsl_g12_irqtask(struct work_struct *work) +{ + gsl_device_t *device = &gsl_driver.device[GSL_DEVICE_G12-1]; + kgsl_g12_updatetimestamp(device); + wake_up_interruptible_all(&device->timestamp_waitq); +} +#endif + +//---------------------------------------------------------------------------- + +int +kgsl_g12_init(gsl_device_t *device) +{ + int status = GSL_FAILURE; + + device->flags |= GSL_FLAGS_INITIALIZED; + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_ON, 100); + + // setup MH arbiter - MH offsets are considered to be dword based, therefore no down shift + device->ftbl.device_regwrite(device, ADDR_MH_ARBITER_CONFIG, *(unsigned int *) &gsl_cfg_g12_mharb); + + // init interrupt + status = kgsl_intr_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + // enable irq + device->ftbl.device_regwrite(device, (ADDR_VGC_IRQENABLE >> 2), 0x3); + +#ifndef GSL_NO_MMU + // enable master interrupt for G12 MH + kgsl_intr_attach(&device->intr, GSL_INTR_G12_MH, kgsl_g12_intrcallback, (void *) device); + kgsl_intr_enable(&device->intr, GSL_INTR_G12_MH); + + // init mmu + status = kgsl_mmu_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } +#endif + +#ifdef IRQTHREAD_POLL + // Create event to trigger IRQ polling thread + device->irqthread_event = kos_event_create(0); +#endif + + // enable interrupts + kgsl_intr_attach(&device->intr, GSL_INTR_G12_G2D, kgsl_g12_intrcallback, (void *) device); + kgsl_intr_attach(&device->intr, GSL_INTR_G12_FIFO, kgsl_g12_intrcallback, (void *) device); + kgsl_intr_enable(&device->intr, GSL_INTR_G12_G2D); + kgsl_intr_enable(&device->intr, GSL_INTR_G12_FIFO); + +#ifndef _Z180 + kgsl_intr_attach(&device->intr, GSL_INTR_G12_FBC, kgsl_g12_intrcallback, (void *) device); + //kgsl_intr_enable(&device->intr, GSL_INTR_G12_FBC); +#endif //_Z180 + + // create thread for IRQ handling +#if defined(__SYMBIAN32__) + kos_thread_create( (oshandle_t)irq_thread, &(device->irq_thread) ); +#elif defined(_LINUX) + device->irq_workq = create_singlethread_workqueue("z1xx_workq"); + INIT_WORK(&device->irq_work, kgsl_g12_irqtask); +#else + #pragma warning(disable:4152) + device->irq_thread_handle = kos_thread_create( (oshandle_t)irq_thread, &(device->irq_thread) ); +#endif + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_close(gsl_device_t *device) +{ + int status = GSL_FAILURE; + + if (device->refcnt == 0) + { + // wait pending interrupts before shutting down G12 intr thread to + // empty irq counters. Otherwise there's a possibility to have them in + // registers next time systems starts up and this results in a hang. + status = device->ftbl.device_idle(device, 1000); + KOS_ASSERT(status == GSL_SUCCESS); + +#ifndef _LINUX + kos_thread_destroy(device->irq_thread_handle); +#else + destroy_workqueue(device->irq_workq); +#endif + + // shutdown command window + kgsl_cmdwindow_close(device); + +#ifndef GSL_NO_MMU + // shutdown mmu + kgsl_mmu_close(device); +#endif + // disable interrupts + kgsl_intr_detach(&device->intr, GSL_INTR_G12_MH); + kgsl_intr_detach(&device->intr, GSL_INTR_G12_G2D); + kgsl_intr_detach(&device->intr, GSL_INTR_G12_FIFO); +#ifndef _Z180 + kgsl_intr_detach(&device->intr, GSL_INTR_G12_FBC); +#endif //_Z180 + + // shutdown interrupt + kgsl_intr_close(device); + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_OFF, 0); + + device->ftbl.device_idle(device, GSL_TIMEOUT_NONE); + device->flags &= ~GSL_FLAGS_INITIALIZED; + +#if defined(__SYMBIAN32__) + while(device->irq_thread) + { + kos_sleep(20); + } +#endif + drawctx_id = 0; + + KOS_ASSERT(g_z1xx.numcontext == 0); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_destroy(gsl_device_t *device) +{ + int i; + unsigned int pid; + +#ifdef _DEBUG + // for now, signal catastrophic failure in a brute force way + KOS_ASSERT(0); +#endif // _DEBUG + + //todo: hard reset core? + + for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++) + { + pid = device->callerprocess[i]; + if (pid) + { + device->ftbl.device_stop(device); + kgsl_driver_destroy(pid); + + // todo: terminate client process? + } + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_start(gsl_device_t *device, gsl_flags_t flags) +{ + int status = GSL_SUCCESS; + + (void) flags; // unreferenced formal parameter + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_ON, 100); + + // init command window + status = kgsl_cmdwindow_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + KOS_ASSERT(g_z1xx.numcontext == 0); + + device->flags |= GSL_FLAGS_STARTED; + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_stop(gsl_device_t *device) +{ + int status; + + KOS_ASSERT(device->refcnt == 0); + + /* wait for device to idle before setting it's clock off */ + status = device->ftbl.device_idle(device, 1000); + KOS_ASSERT(status == GSL_SUCCESS); + + status = kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_OFF, 0); + device->flags &= ~GSL_FLAGS_STARTED; + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_getproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_FAILURE; + // unreferenced formal parameter + (void) sizebytes; + + if (type == GSL_PROP_DEVICE_INFO) + { + gsl_devinfo_t *devinfo = (gsl_devinfo_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_devinfo_t)); + + devinfo->device_id = device->id; + devinfo->chip_id = (gsl_chipid_t)device->chip_id; +#ifndef GSL_NO_MMU + devinfo->mmu_enabled = kgsl_mmu_isenabled(&device->mmu); +#endif + if (z160_version == 1) + devinfo->high_precision = 1; + else + devinfo->high_precision = 0; + + status = GSL_SUCCESS; + } + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_setproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_FAILURE; + + // unreferenced formal parameters + (void) device; + + if (type == GSL_PROP_DEVICE_POWER) + { + gsl_powerprop_t *power = (gsl_powerprop_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_powerprop_t)); + + if (!(device->flags & GSL_FLAGS_SAFEMODE)) + { + kgsl_hal_setpowerstate(device->id, power->flags, power->value); + } + + status = GSL_SUCCESS; + } + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_idle(gsl_device_t *device, unsigned int timeout) +{ + if ( device->flags & GSL_FLAGS_STARTED ) + { + for ( ; ; ) + { + gsl_timestamp_t retired = kgsl_cmdstream_readtimestamp0( device->id, GSL_TIMESTAMP_RETIRED ); + gsl_timestamp_t ts_diff = retired - device->current_timestamp; + if ( ts_diff >= 0 || ts_diff < -GSL_TIMESTAMP_EPSILON ) + break; + kos_sleep(10); + } + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_regread(gsl_device_t *device, unsigned int offsetwords, unsigned int *value) +{ + // G12 MH register values can only be retrieved via dedicated read registers + if ((offsetwords >= ADDR_MH_ARBITER_CONFIG && offsetwords <= ADDR_MH_AXI_HALT_CONTROL) || + (offsetwords >= ADDR_MH_MMU_CONFIG && offsetwords <= ADDR_MH_MMU_MPU_END)) + { +#ifdef _Z180 + device->ftbl.device_regwrite(device, (ADDR_VGC_MH_READ_ADDR >> 2), offsetwords); + GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (ADDR_VGC_MH_READ_ADDR >> 2), value); +#else + device->ftbl.device_regwrite(device, (ADDR_MMU_READ_ADDR >> 2), offsetwords); + GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (ADDR_MMU_READ_DATA >> 2), value); +#endif + } + else + { + GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_regwrite(gsl_device_t *device, unsigned int offsetwords, unsigned int value) +{ + // G12 MH registers can only be written via the command window + if ((offsetwords >= ADDR_MH_ARBITER_CONFIG && offsetwords <= ADDR_MH_AXI_HALT_CONTROL) || + (offsetwords >= ADDR_MH_MMU_CONFIG && offsetwords <= ADDR_MH_MMU_MPU_END)) + { + kgsl_cmdwindow_write0(device->id, GSL_CMDWINDOW_MMU, offsetwords, value); + } + else + { + GSL_HAL_REG_WRITE(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value); + } + + // idle device when running in safe mode + if (device->flags & GSL_FLAGS_SAFEMODE) + { + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_waitirq(gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout) +{ + int status = GSL_FAILURE_NOTSUPPORTED; +#ifdef VG_HDK + (void)timeout; +#endif + +#ifndef _Z180 + if (intr_id == GSL_INTR_G12_G2D || intr_id == GSL_INTR_G12_FBC) +#else + if (intr_id == GSL_INTR_G12_G2D) +#endif //_Z180 + { +#ifndef VG_HDK + if (kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS) +#endif + { + // wait until intr completion event is received and check that + // the interrupt is still enabled. If event is received, but + // interrupt is not enabled any more, the driver is shutting + // down and event structure is not valid anymore. +#ifndef VG_HDK + if (kos_event_wait(device->intr.evnt[intr_id], timeout) == OS_SUCCESS && kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS) +#endif + { + unsigned int cntrs; + int i; + kgsl_device_active(device); +#ifndef VG_HDK + kos_event_reset(device->intr.evnt[intr_id]); + device->ftbl.device_regread(device, (ADDR_VGC_IRQ_ACTIVE_CNT >> 2), &cntrs); +#else + device->ftbl.device_regread(device, (0x38 >> 2), &cntrs); +#endif + + for (i = 0; i < GSL_G12_INTR_COUNT; i++) + { + int intrcnt = cntrs >> ((8 * i)) & 255; + + // maximum allowed counter value is 254. if set to 255 then something has gone wrong + if (intrcnt && (intrcnt < 0xFF)) + { + device->intrcnt[i] += intrcnt; + } + } + + *count = device->intrcnt[intr_id - GSL_INTR_G12_MH]; + device->intrcnt[intr_id - GSL_INTR_G12_MH] = 0; + status = GSL_SUCCESS; + } +#ifndef VG_HDK + else + { + status = GSL_FAILURE_TIMEOUT; + } +#endif + } + } + else if(intr_id == GSL_INTR_FOOBAR) + { + if (kgsl_intr_isenabled(&device->intr, GSL_INTR_G12_G2D) == GSL_SUCCESS) + { + kos_event_signal(device->intr.evnt[GSL_INTR_G12_G2D]); + } + } + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_waittimestamp(gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout) +{ +#ifndef _LINUX + return kos_event_wait( device->timestamp_event, timeout ); +#else + int status = wait_event_interruptible_timeout(device->timestamp_waitq, + kgsl_cmdstream_check_timestamp(device->id, timestamp), + msecs_to_jiffies(timeout)); + if (status > 0) + return GSL_SUCCESS; + else + return GSL_FAILURE; +#endif +} + +int +kgsl_g12_getfunctable(gsl_functable_t *ftbl) +{ + ftbl->device_init = kgsl_g12_init; + ftbl->device_close = kgsl_g12_close; + ftbl->device_destroy = kgsl_g12_destroy; + ftbl->device_start = kgsl_g12_start; + ftbl->device_stop = kgsl_g12_stop; + ftbl->device_getproperty = kgsl_g12_getproperty; + ftbl->device_setproperty = kgsl_g12_setproperty; + ftbl->device_idle = kgsl_g12_idle; + ftbl->device_regread = kgsl_g12_regread; + ftbl->device_regwrite = kgsl_g12_regwrite; + ftbl->device_waitirq = kgsl_g12_waitirq; + ftbl->device_waittimestamp = kgsl_g12_waittimestamp; + ftbl->device_runpending = NULL; + ftbl->device_addtimestamp = kgsl_g12_addtimestamp; + ftbl->intr_isr = kgsl_g12_isr; + ftbl->mmu_tlbinvalidate = kgsl_g12_tlbinvalidate; + ftbl->mmu_setpagetable = kgsl_g12_setpagetable; + ftbl->cmdstream_issueibcmds = kgsl_g12_issueibcmds; + ftbl->context_create = kgsl_g12_context_create; + ftbl->context_destroy = kgsl_g12_context_destroy; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +static void addmarker(gsl_z1xx_t* z1xx) +{ + KOS_ASSERT(z1xx); + { + unsigned int *p = z1xx->cmdbuf[z1xx->curr]; + /* todo: use symbolic values */ + p[z1xx->offs++] = 0x7C000176; + p[z1xx->offs++] = (0x8000|5); + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = 0x7C000176; + p[z1xx->offs++] = 5; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + } +} + +//---------------------------------------------------------------------------- +static void beginpacket(gsl_z1xx_t* z1xx, gpuaddr_t cmd, unsigned int nextcnt) +{ + unsigned int *p = z1xx->cmdbuf[z1xx->curr]; + + p[z1xx->offs++] = 0x7C000176; + p[z1xx->offs++] = 5; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = 0x7C000275; + p[z1xx->offs++] = cmd; + p[z1xx->offs++] = 0x1000|nextcnt; // nextcount + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; +} + +//---------------------------------------------------------------------------- + +static int +kgsl_g12_issueibcmds(gsl_device_t* device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags) +{ + unsigned int ofs = PACKETSIZE_STATESTREAM*sizeof(unsigned int); + unsigned int cnt = 5; + unsigned int cmd = ibaddr; + unsigned int nextbuf = (g_z1xx.curr+1)%GSL_HAL_NUMCMDBUFFERS; + unsigned int nextaddr = g_z1xx.cmdbufdesc[nextbuf].gpuaddr; + unsigned int nextcnt = 0x9000|5; + gsl_memdesc_t tmp = {0}; + gsl_timestamp_t processed_timestamp; + + (void) flags; + + // read what is the latest timestamp device have processed + GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&processed_timestamp); + + /* wait for the next buffer's timestamp to occur */ + while(processed_timestamp < g_z1xx.timestamp[nextbuf]) + { +#ifndef _LINUX + kos_event_wait(device->timestamp_event, 1000); + kos_event_reset(device->timestamp_event); +#else + kgsl_cmdstream_waittimestamp(device->id, g_z1xx.timestamp[nextbuf], 1000); +#endif + GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&processed_timestamp); + } + + *timestamp = g_z1xx.timestamp[nextbuf] = device->current_timestamp + 1; + + /* context switch */ + if (drawctxt_index != (int)g_z1xx.prevctx) + { + cnt = PACKETSIZE_STATESTREAM; + ofs = 0; + } + g_z1xx.prevctx = drawctxt_index; + + g_z1xx.offs = 10; + beginpacket(&g_z1xx, cmd+ofs, cnt); + + tmp.gpuaddr=ibaddr+(sizedwords*sizeof(unsigned int)); + kgsl_sharedmem_write0(&tmp, 4, &nextaddr, 4, false); + kgsl_sharedmem_write0(&tmp, 8, &nextcnt, 4, false); + + /* sync mem */ + kgsl_sharedmem_write0((const gsl_memdesc_t *)&g_z1xx.cmdbufdesc[g_z1xx.curr], 0, g_z1xx.cmdbuf[g_z1xx.curr], (512 + 13) * sizeof(unsigned int), false); + + g_z1xx.offs = 0; + g_z1xx.curr = nextbuf; + + /* increment mark counter */ + kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, flags); + kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0); + + /* increment consumed timestamp */ + device->current_timestamp++; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +static int +kgsl_g12_context_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags) +{ + int status = 0; + int i; + int cmd; + gsl_flags_t gslflags = (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGNPAGE); + + // unreferenced formal parameters + (void) device; + (void) type; + //(void) drawctxt_id; + (void) flags; + + kgsl_device_active(device); + + if (g_z1xx.numcontext==0) + { + /* todo: move this to device create or start. Error checking!! */ + for (i=0;iirqthread_event, GSL_IRQ_TIMEOUT)==GSL_SUCCESS) + { + kgsl_g12_waitirq(device, GSL_INTR_G12_G2D, &irq_count, GSL_IRQ_TIMEOUT); +#else + + if( kgsl_g12_waitirq(device, GSL_INTR_G12_G2D, &irq_count, GSL_IRQ_TIMEOUT) == GSL_SUCCESS ) + { +#endif + /* Read a timestamp value */ +#ifdef VG_HDK + timestamp = device->timestamp; +#else + GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)×tamp); +#endif + /* Increase the timestamp value */ + timestamp += irq_count; + + KOS_ASSERT( timestamp <= device->current_timestamp ); + /* Write the new timestamp value */ +#ifdef VG_HDK + device->timestamp = timestamp; +#else + kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), ×tamp, 4, false); +#endif + + /* Notify timestamp event */ +#ifndef _LINUX + kos_event_signal( device->timestamp_event ); +#else + wake_up_interruptible_all(&(device->timestamp_waitq)); +#endif + } + else + { + /* Timeout */ + + + if(!(device->flags&GSL_FLAGS_INITIALIZED)) + { + /* if device is closed -> thread exit */ +#if defined(__SYMBIAN32__) + device->irq_thread = 0; +#endif + return; + } + } + } +} +#endif + +//---------------------------------------------------------------------------- + +static int +kgsl_g12_addtimestamp(gsl_device_t* device, gsl_timestamp_t *timestamp) +{ + device->current_timestamp++; + *timestamp = device->current_timestamp; + + return (GSL_SUCCESS); +} +#endif diff --git a/drivers/mxc/amd-gpu/common/gsl_intrmgr.c b/drivers/mxc/amd-gpu/common/gsl_intrmgr.c new file mode 100644 index 000000000000..2c8b278dfe7a --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_intrmgr.c @@ -0,0 +1,305 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define GSL_INTRID_VALIDATE(id) (((id) < 0) || ((id) >= GSL_INTR_COUNT)) + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +static const gsl_intrblock_reg_t * +kgsl_intr_id2block(gsl_intrid_t id) +{ + const gsl_intrblock_reg_t *block; + int i; + + // interrupt id to hw block + for (i = 0; i < GSL_INTR_BLOCK_COUNT; i++) + { + block = &gsl_cfg_intrblock_reg[i]; + + if (block->first_id <= id && id <= block->last_id) + { + return (block); + } + } + + return (NULL); +} + +//---------------------------------------------------------------------------- + +void +kgsl_intr_decode(gsl_device_t *device, gsl_intrblock_t block_id) +{ + const gsl_intrblock_reg_t *block = &gsl_cfg_intrblock_reg[block_id]; + gsl_intrid_t id; + unsigned int status; + + // read the block's interrupt status bits + device->ftbl.device_regread(device, block->status_reg, &status); + + // mask off any interrupts which are disabled + status &= device->intr.enabled[block->id]; + + // acknowledge the block's interrupts + device->ftbl.device_regwrite(device, block->clear_reg, status); + + // loop through the block's masks, determine which interrupt bits are active, and call callback (or TODO queue DPC) + for (id = block->first_id; id <= block->last_id; id++) + { + if (status & gsl_cfg_intr_mask[id]) + { + device->intr.handler[id].callback(id, device->intr.handler[id].cookie); + } + } +} + +//---------------------------------------------------------------------------- + +KGSL_API void +kgsl_intr_isr() +{ + gsl_deviceid_t device_id; + gsl_device_t *device; + + // loop through the devices, and call device specific isr + for (device_id = (gsl_deviceid_t)(GSL_DEVICE_ANY + 1); device_id <= GSL_DEVICE_MAX; device_id++) + { + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + if (device->intr.flags & GSL_FLAGS_INITIALIZED) + { + kgsl_device_active(device); + device->ftbl.intr_isr(device); + } + } +} + +//---------------------------------------------------------------------------- + +int kgsl_intr_init(gsl_device_t *device) +{ + if (device->ftbl.intr_isr == NULL) + { + return (GSL_FAILURE_BADPARAM); + } + + if (device->intr.flags & GSL_FLAGS_INITIALIZED) + { + return (GSL_SUCCESS); + } + + device->intr.device = device; + device->intr.flags |= GSL_FLAGS_INITIALIZED; + + // os_interrupt_setcallback(YAMATO_INTR, kgsl_intr_isr); + // os_interrupt_enable(YAMATO_INTR); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int kgsl_intr_close(gsl_device_t *device) +{ + const gsl_intrblock_reg_t *block; + int i, id; + + if (device->intr.flags & GSL_FLAGS_INITIALIZED) + { + // check if there are any enabled interrupts lingering around + for (i = 0; i < GSL_INTR_BLOCK_COUNT; i++) + { + if (device->intr.enabled[i]) + { + block = &gsl_cfg_intrblock_reg[i]; + + // loop through the block's masks, disable interrupts which active + for (id = block->first_id; id <= block->last_id; id++) + { + if (device->intr.enabled[i] & gsl_cfg_intr_mask[id]) + { + kgsl_intr_disable(&device->intr, (gsl_intrid_t)id); + } + } + } + } + + kos_memset(&device->intr, 0, sizeof(gsl_intr_t)); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int kgsl_intr_enable(gsl_intr_t *intr, gsl_intrid_t id) +{ + const gsl_intrblock_reg_t *block; + unsigned int mask; + unsigned int enabled; + + if (GSL_INTRID_VALIDATE(id)) + { + return (GSL_FAILURE_BADPARAM); + } + + if (intr->handler[id].callback == NULL) + { + return (GSL_FAILURE_NOTINITIALIZED); + } + + block = kgsl_intr_id2block(id); + if (block == NULL) + { + return (GSL_FAILURE_SYSTEMERROR); + } + + mask = gsl_cfg_intr_mask[id]; + enabled = intr->enabled[block->id]; + + if (mask && !(enabled & mask)) + { + intr->evnt[id] = kos_event_create(0); + + enabled |= mask; + intr->enabled[block->id] = enabled; + intr->device->ftbl.device_regwrite(intr->device, block->mask_reg, enabled); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int kgsl_intr_disable(gsl_intr_t *intr, gsl_intrid_t id) +{ + const gsl_intrblock_reg_t *block; + unsigned int mask; + unsigned int enabled; + + if (GSL_INTRID_VALIDATE(id)) + { + return (GSL_FAILURE_BADPARAM); + } + + if (intr->handler[id].callback == NULL) + { + return (GSL_FAILURE_NOTINITIALIZED); + } + + block = kgsl_intr_id2block(id); + if (block == NULL) + { + return (GSL_FAILURE_SYSTEMERROR); + } + + mask = gsl_cfg_intr_mask[id]; + enabled = intr->enabled[block->id]; + + if (enabled & mask) + { + enabled &= ~mask; + intr->enabled[block->id] = enabled; + intr->device->ftbl.device_regwrite(intr->device, block->mask_reg, enabled); + + kos_event_signal(intr->evnt[id]); // wake up waiting threads before destroying the event + kos_event_destroy(intr->evnt[id]); + intr->evnt[id] = 0; + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_intr_attach(gsl_intr_t *intr, gsl_intrid_t id, gsl_intr_callback_t callback, void *cookie) +{ + if (GSL_INTRID_VALIDATE(id) || callback == NULL) + { + return (GSL_FAILURE_BADPARAM); + } + + if (intr->handler[id].callback != NULL) + { + if (intr->handler[id].callback == callback && intr->handler[id].cookie == cookie) + { + return (GSL_FAILURE_ALREADYINITIALIZED); + } + else + { + return (GSL_FAILURE_NOMOREAVAILABLE); + } + } + + intr->handler[id].callback = callback; + intr->handler[id].cookie = cookie; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_intr_detach(gsl_intr_t *intr, gsl_intrid_t id) +{ + if (GSL_INTRID_VALIDATE(id)) + { + return (GSL_FAILURE_BADPARAM); + } + + if (intr->handler[id].callback == NULL) + { + return (GSL_FAILURE_NOTINITIALIZED); + } + + kgsl_intr_disable(intr, id); + + intr->handler[id].callback = NULL; + intr->handler[id].cookie = NULL; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_intr_isenabled(gsl_intr_t *intr, gsl_intrid_t id) +{ + int status = GSL_FAILURE; + const gsl_intrblock_reg_t *block = kgsl_intr_id2block(id); + + if (block != NULL) + { + // check if interrupt is enabled + if (intr->enabled[block->id] & gsl_cfg_intr_mask[id]) + { + status = GSL_SUCCESS; + } + } + + return (status); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_log.c b/drivers/mxc/amd-gpu/common/gsl_log.c new file mode 100644 index 000000000000..79a14a5f4b21 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_log.c @@ -0,0 +1,591 @@ +/* Copyright (c) 2002,2008-2009, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifdef GSL_LOG + +#define _CRT_SECURE_NO_WARNINGS + +#include +#include +#include +#include "gsl.h" + +#define KGSL_OUTPUT_TYPE_MEMBUF 0 +#define KGSL_OUTPUT_TYPE_STDOUT 1 +#define KGSL_OUTPUT_TYPE_FILE 2 + +#define REG_OUTPUT( X ) case X: b += sprintf( b, "%s", #X ); break; +#define INTRID_OUTPUT( X ) case X: b += sprintf( b, "%s", #X ); break; + +typedef struct log_output +{ + unsigned char type; + unsigned int flags; + oshandle_t file; + + struct log_output* next; +} log_output_t; + +static log_output_t* outputs = NULL; + +static oshandle_t log_mutex = NULL; +static char buffer[256]; +static char buffer2[256]; +static int log_initialized = 0; + +//---------------------------------------------------------------------------- + +int kgsl_log_init() +{ + log_mutex = kos_mutex_create( "log_mutex" ); + + log_initialized = 1; + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int kgsl_log_close() +{ + if( !log_initialized ) return GSL_SUCCESS; + + // Go throught output list and free every node + while( outputs != NULL ) + { + log_output_t* temp = outputs->next; + + switch( outputs->type ) + { + case KGSL_OUTPUT_TYPE_FILE: + kos_fclose( outputs->file ); + break; + } + + kos_free( outputs ); + outputs = temp; + } + + kos_mutex_free( log_mutex ); + + log_initialized = 0; + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int kgsl_log_open_stdout( unsigned int log_flags ) +{ + log_output_t* output; + + if( !log_initialized ) return GSL_SUCCESS; + + output = kos_malloc( sizeof( log_output_t ) ); + output->type = KGSL_OUTPUT_TYPE_STDOUT; + output->flags = log_flags; + + // Add to the list + if( outputs == NULL ) + { + // First node in the list. + outputs = output; + output->next = NULL; + } + else + { + // Add to the start of the list + output->next = outputs; + outputs = output; + } + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags ) +{ + // TODO + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int kgsl_log_open_file( char* filename, unsigned int log_flags ) +{ + log_output_t* output; + + if( !log_initialized ) return GSL_SUCCESS; + + output = kos_malloc( sizeof( log_output_t ) ); + output->type = KGSL_OUTPUT_TYPE_FILE; + output->flags = log_flags; + output->file = kos_fopen( filename, "w" ); + + // Add to the list + if( outputs == NULL ) + { + // First node in the list. + outputs = output; + output->next = NULL; + } + else + { + // Add to the start of the list + output->next = outputs; + outputs = output; + } + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int kgsl_log_flush_membuf( char* filename, int memBufId ) +{ + // TODO + + return GSL_SUCCESS; +} +//---------------------------------------------------------------------------- + +int kgsl_log_write( unsigned int log_flags, char* format, ... ) +{ + char *c = format; + char *b = buffer; + char *p1, *p2; + log_output_t* output; + va_list arguments; + + if( !log_initialized ) return GSL_SUCCESS; + + // Acquire mutex lock as we are using shared buffer for the string parsing + kos_mutex_lock( log_mutex ); + + // Add separator + *(b++) = '|'; *(b++) = ' '; + + va_start( arguments, format ); + + while( 1 ) + { + // Find the first occurence of % + p1 = strchr( c, '%' ); + if( !p1 ) + { + // No more % characters -> copy rest of the string + strcpy( b, c ); + + break; + } + + // Find the second occurence of % and handle the string until that point + p2 = strchr( p1+1, '%' ); + + // If not found, just use the end of the buffer + if( !p2 ) p2 = strchr( p1+1, '\0' ); + + // Break the string to this point + kos_memcpy( buffer2, c, p2-c ); + *(buffer2+(unsigned int)(p2-c)) = '\0'; + + switch( *(p1+1) ) + { + // gsl_memdesc_t + case 'M': + { + gsl_memdesc_t val = va_arg( arguments, gsl_memdesc_t ); + // Handle string before %M + kos_memcpy( b, c, p1-c ); + b += (unsigned int)p1-(unsigned int)c; + // Replace %M + b += sprintf( b, "[hostptr=0x%08x, gpuaddr=0x%08x]", val.hostptr, val.gpuaddr ); + // Handle string after %M + kos_memcpy( b, p1+2, p2-(p1+2) ); + b += (unsigned int)p2-(unsigned int)(p1+2); + *b = '\0'; + } + break; + + // GSL_SUCCESS/GSL_FAILURE + case 'B': + { + int val = va_arg( arguments, int ); + // Handle string before %B + kos_memcpy( b, c, p1-c ); + b += (unsigned int)p1-(unsigned int)c; + // Replace %B + if( val == GSL_SUCCESS ) + b += sprintf( b, "%s", "GSL_SUCCESS" ); + else + b += sprintf( b, "%s", "GSL_FAILURE" ); + // Handle string after %B + kos_memcpy( b, p1+2, p2-(p1+2) ); + b += (unsigned int)p2-(unsigned int)(p1+2); + *b = '\0'; + } + break; + + // gsl_deviceid_t + case 'D': + { + gsl_deviceid_t val = va_arg( arguments, gsl_deviceid_t ); + // Handle string before %D + kos_memcpy( b, c, p1-c ); + b += (unsigned int)p1-(unsigned int)c; + // Replace %D + switch( val ) + { + case GSL_DEVICE_ANY: + b += sprintf( b, "%s", "GSL_DEVICE_ANY" ); + break; + case GSL_DEVICE_YAMATO: + b += sprintf( b, "%s", "GSL_DEVICE_YAMATO" ); + break; + case GSL_DEVICE_G12: + b += sprintf( b, "%s", "GSL_DEVICE_G12" ); + break; + default: + b += sprintf( b, "%s", "UNKNOWN DEVICE" ); + break; + } + // Handle string after %D + kos_memcpy( b, p1+2, p2-(p1+2) ); + b += (unsigned int)p2-(unsigned int)(p1+2); + *b = '\0'; + } + break; + + // gsl_intrid_t + case 'I': + { + unsigned int val = va_arg( arguments, unsigned int ); + // Handle string before %I + kos_memcpy( b, c, p1-c ); + b += (unsigned int)p1-(unsigned int)c; + // Replace %I + switch( val ) + { + INTRID_OUTPUT( GSL_INTR_YDX_MH_AXI_READ_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_MH_AXI_WRITE_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_MH_MMU_PAGE_FAULT ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_SW_INT ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_T0_PACKET_IN_IB ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_OPCODE_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_RESERVED_BIT_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_IB_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_IB2_INT ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_IB1_INT ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_RING_BUFFER ); + INTRID_OUTPUT( GSL_INTR_YDX_RBBM_READ_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_RBBM_DISPLAY_UPDATE ); + INTRID_OUTPUT( GSL_INTR_YDX_RBBM_GUI_IDLE ); + INTRID_OUTPUT( GSL_INTR_YDX_SQ_PS_WATCHDOG ); + INTRID_OUTPUT( GSL_INTR_YDX_SQ_VS_WATCHDOG ); + INTRID_OUTPUT( GSL_INTR_G12_MH ); + INTRID_OUTPUT( GSL_INTR_G12_G2D ); + INTRID_OUTPUT( GSL_INTR_G12_FIFO ); +#ifndef _Z180 + INTRID_OUTPUT( GSL_INTR_G12_FBC ); +#endif // _Z180 + INTRID_OUTPUT( GSL_INTR_G12_MH_AXI_READ_ERROR ); + INTRID_OUTPUT( GSL_INTR_G12_MH_AXI_WRITE_ERROR ); + INTRID_OUTPUT( GSL_INTR_G12_MH_MMU_PAGE_FAULT ); + INTRID_OUTPUT( GSL_INTR_COUNT ); + INTRID_OUTPUT( GSL_INTR_FOOBAR ); + + default: + b += sprintf( b, "%s", "UNKNOWN INTERRUPT ID" ); + break; + } + // Handle string after %I + kos_memcpy( b, p1+2, p2-(p1+2) ); + b += (unsigned int)p2-(unsigned int)(p1+2); + *b = '\0'; + } + break; + + // Register offset + case 'R': + { + unsigned int val = va_arg( arguments, unsigned int ); + + // Handle string before %R + kos_memcpy( b, c, p1-c ); + b += (unsigned int)p1-(unsigned int)c; + // Replace %R + switch( val ) + { + REG_OUTPUT( mmPA_CL_VPORT_XSCALE ); REG_OUTPUT( mmPA_CL_VPORT_XOFFSET ); REG_OUTPUT( mmPA_CL_VPORT_YSCALE ); + REG_OUTPUT( mmPA_CL_VPORT_YOFFSET ); REG_OUTPUT( mmPA_CL_VPORT_ZSCALE ); REG_OUTPUT( mmPA_CL_VPORT_ZOFFSET ); + REG_OUTPUT( mmPA_CL_VTE_CNTL ); REG_OUTPUT( mmPA_CL_CLIP_CNTL ); REG_OUTPUT( mmPA_CL_GB_VERT_CLIP_ADJ ); + REG_OUTPUT( mmPA_CL_GB_VERT_DISC_ADJ ); REG_OUTPUT( mmPA_CL_GB_HORZ_CLIP_ADJ ); REG_OUTPUT( mmPA_CL_GB_HORZ_DISC_ADJ ); + REG_OUTPUT( mmPA_CL_ENHANCE ); REG_OUTPUT( mmPA_SC_ENHANCE ); REG_OUTPUT( mmPA_SU_VTX_CNTL ); + REG_OUTPUT( mmPA_SU_POINT_SIZE ); REG_OUTPUT( mmPA_SU_POINT_MINMAX ); REG_OUTPUT( mmPA_SU_LINE_CNTL ); + REG_OUTPUT( mmPA_SU_FACE_DATA ); REG_OUTPUT( mmPA_SU_SC_MODE_CNTL ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_FRONT_SCALE ); + REG_OUTPUT( mmPA_SU_POLY_OFFSET_FRONT_OFFSET ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_BACK_SCALE ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_BACK_OFFSET ); + REG_OUTPUT( mmPA_SU_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER2_SELECT ); + REG_OUTPUT( mmPA_SU_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER0_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER0_HI ); + REG_OUTPUT( mmPA_SU_PERFCOUNTER1_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER1_HI ); REG_OUTPUT( mmPA_SU_PERFCOUNTER2_LOW ); + REG_OUTPUT( mmPA_SU_PERFCOUNTER2_HI ); REG_OUTPUT( mmPA_SU_PERFCOUNTER3_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER3_HI ); + REG_OUTPUT( mmPA_SC_WINDOW_OFFSET ); REG_OUTPUT( mmPA_SC_AA_CONFIG ); REG_OUTPUT( mmPA_SC_AA_MASK ); + REG_OUTPUT( mmPA_SC_LINE_STIPPLE ); REG_OUTPUT( mmPA_SC_LINE_CNTL ); REG_OUTPUT( mmPA_SC_WINDOW_SCISSOR_TL ); + REG_OUTPUT( mmPA_SC_WINDOW_SCISSOR_BR ); REG_OUTPUT( mmPA_SC_SCREEN_SCISSOR_TL ); REG_OUTPUT( mmPA_SC_SCREEN_SCISSOR_BR ); + REG_OUTPUT( mmPA_SC_VIZ_QUERY ); REG_OUTPUT( mmPA_SC_VIZ_QUERY_STATUS ); REG_OUTPUT( mmPA_SC_LINE_STIPPLE_STATE ); + REG_OUTPUT( mmPA_SC_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmPA_SC_PERFCOUNTER0_LOW ); REG_OUTPUT( mmPA_SC_PERFCOUNTER0_HI ); + REG_OUTPUT( mmPA_CL_CNTL_STATUS ); REG_OUTPUT( mmPA_SU_CNTL_STATUS ); REG_OUTPUT( mmPA_SC_CNTL_STATUS ); + REG_OUTPUT( mmPA_SU_DEBUG_CNTL ); REG_OUTPUT( mmPA_SU_DEBUG_DATA ); REG_OUTPUT( mmPA_SC_DEBUG_CNTL ); + REG_OUTPUT( mmPA_SC_DEBUG_DATA ); REG_OUTPUT( mmGFX_COPY_STATE ); REG_OUTPUT( mmVGT_DRAW_INITIATOR ); + REG_OUTPUT( mmVGT_EVENT_INITIATOR ); REG_OUTPUT( mmVGT_DMA_BASE ); REG_OUTPUT( mmVGT_DMA_SIZE ); + REG_OUTPUT( mmVGT_BIN_BASE ); REG_OUTPUT( mmVGT_BIN_SIZE ); REG_OUTPUT( mmVGT_CURRENT_BIN_ID_MIN ); + REG_OUTPUT( mmVGT_CURRENT_BIN_ID_MAX ); REG_OUTPUT( mmVGT_IMMED_DATA ); REG_OUTPUT( mmVGT_MAX_VTX_INDX ); + REG_OUTPUT( mmVGT_MIN_VTX_INDX ); REG_OUTPUT( mmVGT_INDX_OFFSET ); REG_OUTPUT( mmVGT_VERTEX_REUSE_BLOCK_CNTL ); + REG_OUTPUT( mmVGT_OUT_DEALLOC_CNTL ); REG_OUTPUT( mmVGT_MULTI_PRIM_IB_RESET_INDX ); REG_OUTPUT( mmVGT_ENHANCE ); + REG_OUTPUT( mmVGT_VTX_VECT_EJECT_REG ); REG_OUTPUT( mmVGT_LAST_COPY_STATE ); REG_OUTPUT( mmVGT_DEBUG_CNTL ); + REG_OUTPUT( mmVGT_DEBUG_DATA ); REG_OUTPUT( mmVGT_CNTL_STATUS ); REG_OUTPUT( mmVGT_CRC_SQ_DATA ); + REG_OUTPUT( mmVGT_CRC_SQ_CTRL ); REG_OUTPUT( mmVGT_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER1_SELECT ); + REG_OUTPUT( mmVGT_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER0_LOW ); + REG_OUTPUT( mmVGT_PERFCOUNTER1_LOW ); REG_OUTPUT( mmVGT_PERFCOUNTER2_LOW ); REG_OUTPUT( mmVGT_PERFCOUNTER3_LOW ); + REG_OUTPUT( mmVGT_PERFCOUNTER0_HI ); REG_OUTPUT( mmVGT_PERFCOUNTER1_HI ); REG_OUTPUT( mmVGT_PERFCOUNTER2_HI ); + REG_OUTPUT( mmVGT_PERFCOUNTER3_HI ); REG_OUTPUT( mmTC_CNTL_STATUS ); REG_OUTPUT( mmTCR_CHICKEN ); + REG_OUTPUT( mmTCF_CHICKEN ); REG_OUTPUT( mmTCM_CHICKEN ); REG_OUTPUT( mmTCR_PERFCOUNTER0_SELECT ); + REG_OUTPUT( mmTCR_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmTCR_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCR_PERFCOUNTER1_HI ); + REG_OUTPUT( mmTCR_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTCR_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTP_TC_CLKGATE_CNTL ); + REG_OUTPUT( mmTPC_CNTL_STATUS ); REG_OUTPUT( mmTPC_DEBUG0 ); REG_OUTPUT( mmTPC_DEBUG1 ); + REG_OUTPUT( mmTPC_CHICKEN ); REG_OUTPUT( mmTP0_CNTL_STATUS ); REG_OUTPUT( mmTP0_DEBUG ); + REG_OUTPUT( mmTP0_CHICKEN ); REG_OUTPUT( mmTP0_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTP0_PERFCOUNTER0_HI ); + REG_OUTPUT( mmTP0_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTP0_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmTP0_PERFCOUNTER1_HI ); + REG_OUTPUT( mmTP0_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTCM_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTCM_PERFCOUNTER1_SELECT ); + REG_OUTPUT( mmTCM_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCM_PERFCOUNTER1_HI ); REG_OUTPUT( mmTCM_PERFCOUNTER0_LOW ); + REG_OUTPUT( mmTCM_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER1_SELECT ); + REG_OUTPUT( mmTCF_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER4_SELECT ); + REG_OUTPUT( mmTCF_PERFCOUNTER5_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER6_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER7_SELECT ); + REG_OUTPUT( mmTCF_PERFCOUNTER8_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER9_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER10_SELECT ); + REG_OUTPUT( mmTCF_PERFCOUNTER11_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER1_HI ); + REG_OUTPUT( mmTCF_PERFCOUNTER2_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER3_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER4_HI ); + REG_OUTPUT( mmTCF_PERFCOUNTER5_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER6_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER7_HI ); + REG_OUTPUT( mmTCF_PERFCOUNTER8_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER9_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER10_HI ); + REG_OUTPUT( mmTCF_PERFCOUNTER11_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER1_LOW ); + REG_OUTPUT( mmTCF_PERFCOUNTER2_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER3_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER4_LOW ); + REG_OUTPUT( mmTCF_PERFCOUNTER5_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER6_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER7_LOW ); + REG_OUTPUT( mmTCF_PERFCOUNTER8_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER9_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER10_LOW ); + REG_OUTPUT( mmTCF_PERFCOUNTER11_LOW ); REG_OUTPUT( mmTCF_DEBUG ); REG_OUTPUT( mmTCA_FIFO_DEBUG ); + REG_OUTPUT( mmTCA_PROBE_DEBUG ); REG_OUTPUT( mmTCA_TPC_DEBUG ); REG_OUTPUT( mmTCB_CORE_DEBUG ); + REG_OUTPUT( mmTCB_TAG0_DEBUG ); REG_OUTPUT( mmTCB_TAG1_DEBUG ); REG_OUTPUT( mmTCB_TAG2_DEBUG ); + REG_OUTPUT( mmTCB_TAG3_DEBUG ); REG_OUTPUT( mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG ); REG_OUTPUT( mmTCB_FETCH_GEN_WALKER_DEBUG ); + REG_OUTPUT( mmTCB_FETCH_GEN_PIPE0_DEBUG ); REG_OUTPUT( mmTCD_INPUT0_DEBUG ); REG_OUTPUT( mmTCD_DEGAMMA_DEBUG ); + REG_OUTPUT( mmTCD_DXTMUX_SCTARB_DEBUG ); REG_OUTPUT( mmTCD_DXTC_ARB_DEBUG ); REG_OUTPUT( mmTCD_STALLS_DEBUG ); + REG_OUTPUT( mmTCO_STALLS_DEBUG ); REG_OUTPUT( mmTCO_QUAD0_DEBUG0 ); REG_OUTPUT( mmTCO_QUAD0_DEBUG1 ); + REG_OUTPUT( mmSQ_GPR_MANAGEMENT ); REG_OUTPUT( mmSQ_FLOW_CONTROL ); REG_OUTPUT( mmSQ_INST_STORE_MANAGMENT ); + REG_OUTPUT( mmSQ_RESOURCE_MANAGMENT ); REG_OUTPUT( mmSQ_EO_RT ); REG_OUTPUT( mmSQ_DEBUG_MISC ); + REG_OUTPUT( mmSQ_ACTIVITY_METER_CNTL ); REG_OUTPUT( mmSQ_ACTIVITY_METER_STATUS ); REG_OUTPUT( mmSQ_INPUT_ARB_PRIORITY ); + REG_OUTPUT( mmSQ_THREAD_ARB_PRIORITY ); REG_OUTPUT( mmSQ_VS_WATCHDOG_TIMER ); REG_OUTPUT( mmSQ_PS_WATCHDOG_TIMER ); + REG_OUTPUT( mmSQ_INT_CNTL ); REG_OUTPUT( mmSQ_INT_STATUS ); REG_OUTPUT( mmSQ_INT_ACK ); + REG_OUTPUT( mmSQ_DEBUG_INPUT_FSM ); REG_OUTPUT( mmSQ_DEBUG_CONST_MGR_FSM ); REG_OUTPUT( mmSQ_DEBUG_TP_FSM ); + REG_OUTPUT( mmSQ_DEBUG_FSM_ALU_0 ); REG_OUTPUT( mmSQ_DEBUG_FSM_ALU_1 ); REG_OUTPUT( mmSQ_DEBUG_EXP_ALLOC ); + REG_OUTPUT( mmSQ_DEBUG_PTR_BUFF ); REG_OUTPUT( mmSQ_DEBUG_GPR_VTX ); REG_OUTPUT( mmSQ_DEBUG_GPR_PIX ); + REG_OUTPUT( mmSQ_DEBUG_TB_STATUS_SEL ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_0 ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_1 ); + REG_OUTPUT( mmSQ_DEBUG_VTX_TB_STATUS_REG ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_STATE_MEM ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_0 ); + REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_0 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_1 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_2 ); + REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_3 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATE_MEM ); REG_OUTPUT( mmSQ_PERFCOUNTER0_SELECT ); + REG_OUTPUT( mmSQ_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmSQ_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmSQ_PERFCOUNTER3_SELECT ); + REG_OUTPUT( mmSQ_PERFCOUNTER0_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER0_HI ); REG_OUTPUT( mmSQ_PERFCOUNTER1_LOW ); + REG_OUTPUT( mmSQ_PERFCOUNTER1_HI ); REG_OUTPUT( mmSQ_PERFCOUNTER2_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER2_HI ); + REG_OUTPUT( mmSQ_PERFCOUNTER3_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER3_HI ); REG_OUTPUT( mmSX_PERFCOUNTER0_SELECT ); + REG_OUTPUT( mmSX_PERFCOUNTER0_LOW ); REG_OUTPUT( mmSX_PERFCOUNTER0_HI ); REG_OUTPUT( mmSQ_INSTRUCTION_ALU_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_ALU_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_ALU_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_2 ); REG_OUTPUT( mmSQ_CONSTANT_0 ); + REG_OUTPUT( mmSQ_CONSTANT_1 ); REG_OUTPUT( mmSQ_CONSTANT_2 ); REG_OUTPUT( mmSQ_CONSTANT_3 ); + REG_OUTPUT( mmSQ_FETCH_0 ); REG_OUTPUT( mmSQ_FETCH_1 ); REG_OUTPUT( mmSQ_FETCH_2 ); + REG_OUTPUT( mmSQ_FETCH_3 ); REG_OUTPUT( mmSQ_FETCH_4 ); REG_OUTPUT( mmSQ_FETCH_5 ); + REG_OUTPUT( mmSQ_CONSTANT_VFETCH_0 ); REG_OUTPUT( mmSQ_CONSTANT_VFETCH_1 ); REG_OUTPUT( mmSQ_CONSTANT_T2 ); + REG_OUTPUT( mmSQ_CONSTANT_T3 ); REG_OUTPUT( mmSQ_CF_BOOLEANS ); REG_OUTPUT( mmSQ_CF_LOOP ); + REG_OUTPUT( mmSQ_CONSTANT_RT_0 ); REG_OUTPUT( mmSQ_CONSTANT_RT_1 ); REG_OUTPUT( mmSQ_CONSTANT_RT_2 ); + REG_OUTPUT( mmSQ_CONSTANT_RT_3 ); REG_OUTPUT( mmSQ_FETCH_RT_0 ); REG_OUTPUT( mmSQ_FETCH_RT_1 ); + REG_OUTPUT( mmSQ_FETCH_RT_2 ); REG_OUTPUT( mmSQ_FETCH_RT_3 ); REG_OUTPUT( mmSQ_FETCH_RT_4 ); + REG_OUTPUT( mmSQ_FETCH_RT_5 ); REG_OUTPUT( mmSQ_CF_RT_BOOLEANS ); REG_OUTPUT( mmSQ_CF_RT_LOOP ); + REG_OUTPUT( mmSQ_VS_PROGRAM ); REG_OUTPUT( mmSQ_PS_PROGRAM ); REG_OUTPUT( mmSQ_CF_PROGRAM_SIZE ); + REG_OUTPUT( mmSQ_INTERPOLATOR_CNTL ); REG_OUTPUT( mmSQ_PROGRAM_CNTL ); REG_OUTPUT( mmSQ_WRAPPING_0 ); + REG_OUTPUT( mmSQ_WRAPPING_1 ); REG_OUTPUT( mmSQ_VS_CONST ); REG_OUTPUT( mmSQ_PS_CONST ); + REG_OUTPUT( mmSQ_CONTEXT_MISC ); REG_OUTPUT( mmSQ_CF_RD_BASE ); REG_OUTPUT( mmSQ_DEBUG_MISC_0 ); + REG_OUTPUT( mmSQ_DEBUG_MISC_1 ); REG_OUTPUT( mmMH_ARBITER_CONFIG ); REG_OUTPUT( mmMH_CLNT_AXI_ID_REUSE ); + REG_OUTPUT( mmMH_INTERRUPT_MASK ); REG_OUTPUT( mmMH_INTERRUPT_STATUS ); REG_OUTPUT( mmMH_INTERRUPT_CLEAR ); + REG_OUTPUT( mmMH_AXI_ERROR ); REG_OUTPUT( mmMH_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmMH_PERFCOUNTER1_SELECT ); + REG_OUTPUT( mmMH_PERFCOUNTER0_CONFIG ); REG_OUTPUT( mmMH_PERFCOUNTER1_CONFIG ); REG_OUTPUT( mmMH_PERFCOUNTER0_LOW ); + REG_OUTPUT( mmMH_PERFCOUNTER1_LOW ); REG_OUTPUT( mmMH_PERFCOUNTER0_HI ); REG_OUTPUT( mmMH_PERFCOUNTER1_HI ); + REG_OUTPUT( mmMH_DEBUG_CTRL ); REG_OUTPUT( mmMH_DEBUG_DATA ); REG_OUTPUT( mmMH_AXI_HALT_CONTROL ); + REG_OUTPUT( mmMH_MMU_CONFIG ); REG_OUTPUT( mmMH_MMU_VA_RANGE ); REG_OUTPUT( mmMH_MMU_PT_BASE ); + REG_OUTPUT( mmMH_MMU_PAGE_FAULT ); REG_OUTPUT( mmMH_MMU_TRAN_ERROR ); REG_OUTPUT( mmMH_MMU_INVALIDATE ); + REG_OUTPUT( mmMH_MMU_MPU_BASE ); REG_OUTPUT( mmMH_MMU_MPU_END ); REG_OUTPUT( mmWAIT_UNTIL ); + REG_OUTPUT( mmRBBM_ISYNC_CNTL ); REG_OUTPUT( mmRBBM_STATUS ); REG_OUTPUT( mmRBBM_DSPLY ); + REG_OUTPUT( mmRBBM_RENDER_LATEST ); REG_OUTPUT( mmRBBM_RTL_RELEASE ); REG_OUTPUT( mmRBBM_PATCH_RELEASE ); + REG_OUTPUT( mmRBBM_AUXILIARY_CONFIG ); REG_OUTPUT( mmRBBM_PERIPHID0 ); REG_OUTPUT( mmRBBM_PERIPHID1 ); + REG_OUTPUT( mmRBBM_PERIPHID2 ); REG_OUTPUT( mmRBBM_PERIPHID3 ); REG_OUTPUT( mmRBBM_CNTL ); + REG_OUTPUT( mmRBBM_SKEW_CNTL ); REG_OUTPUT( mmRBBM_SOFT_RESET ); REG_OUTPUT( mmRBBM_PM_OVERRIDE1 ); + REG_OUTPUT( mmRBBM_PM_OVERRIDE2 ); REG_OUTPUT( mmGC_SYS_IDLE ); REG_OUTPUT( mmNQWAIT_UNTIL ); + REG_OUTPUT( mmRBBM_DEBUG_OUT ); REG_OUTPUT( mmRBBM_DEBUG_CNTL ); REG_OUTPUT( mmRBBM_DEBUG ); + REG_OUTPUT( mmRBBM_READ_ERROR ); REG_OUTPUT( mmRBBM_WAIT_IDLE_CLOCKS ); REG_OUTPUT( mmRBBM_INT_CNTL ); + REG_OUTPUT( mmRBBM_INT_STATUS ); REG_OUTPUT( mmRBBM_INT_ACK ); REG_OUTPUT( mmMASTER_INT_SIGNAL ); + REG_OUTPUT( mmRBBM_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmRBBM_PERFCOUNTER1_LO ); REG_OUTPUT( mmRBBM_PERFCOUNTER1_HI ); + REG_OUTPUT( mmCP_RB_BASE ); REG_OUTPUT( mmCP_RB_CNTL ); REG_OUTPUT( mmCP_RB_RPTR_ADDR ); + REG_OUTPUT( mmCP_RB_RPTR ); REG_OUTPUT( mmCP_RB_RPTR_WR ); REG_OUTPUT( mmCP_RB_WPTR ); + REG_OUTPUT( mmCP_RB_WPTR_DELAY ); REG_OUTPUT( mmCP_RB_WPTR_BASE ); REG_OUTPUT( mmCP_IB1_BASE ); + REG_OUTPUT( mmCP_IB1_BUFSZ ); REG_OUTPUT( mmCP_IB2_BASE ); REG_OUTPUT( mmCP_IB2_BUFSZ ); + REG_OUTPUT( mmCP_ST_BASE ); REG_OUTPUT( mmCP_ST_BUFSZ ); REG_OUTPUT( mmCP_QUEUE_THRESHOLDS ); + REG_OUTPUT( mmCP_MEQ_THRESHOLDS ); REG_OUTPUT( mmCP_CSQ_AVAIL ); REG_OUTPUT( mmCP_STQ_AVAIL ); + REG_OUTPUT( mmCP_MEQ_AVAIL ); REG_OUTPUT( mmCP_CSQ_RB_STAT ); REG_OUTPUT( mmCP_CSQ_IB1_STAT ); + REG_OUTPUT( mmCP_CSQ_IB2_STAT ); REG_OUTPUT( mmCP_NON_PREFETCH_CNTRS ); REG_OUTPUT( mmCP_STQ_ST_STAT ); + REG_OUTPUT( mmCP_MEQ_STAT ); REG_OUTPUT( mmCP_MIU_TAG_STAT ); REG_OUTPUT( mmCP_CMD_INDEX ); + REG_OUTPUT( mmCP_CMD_DATA ); REG_OUTPUT( mmCP_ME_CNTL ); REG_OUTPUT( mmCP_ME_STATUS ); + REG_OUTPUT( mmCP_ME_RAM_WADDR ); REG_OUTPUT( mmCP_ME_RAM_RADDR ); REG_OUTPUT( mmCP_ME_RAM_DATA ); + REG_OUTPUT( mmCP_ME_RDADDR ); REG_OUTPUT( mmCP_DEBUG ); REG_OUTPUT( mmSCRATCH_REG0 ); + REG_OUTPUT( mmSCRATCH_REG1 ); REG_OUTPUT( mmSCRATCH_REG2 ); REG_OUTPUT( mmSCRATCH_REG3 ); + REG_OUTPUT( mmSCRATCH_REG4 ); REG_OUTPUT( mmSCRATCH_REG5 ); REG_OUTPUT( mmSCRATCH_REG6 ); + REG_OUTPUT( mmSCRATCH_REG7 ); + REG_OUTPUT( mmSCRATCH_UMSK ); REG_OUTPUT( mmSCRATCH_ADDR ); REG_OUTPUT( mmCP_ME_VS_EVENT_SRC ); + REG_OUTPUT( mmCP_ME_VS_EVENT_ADDR ); REG_OUTPUT( mmCP_ME_VS_EVENT_DATA ); REG_OUTPUT( mmCP_ME_VS_EVENT_ADDR_SWM ); + REG_OUTPUT( mmCP_ME_VS_EVENT_DATA_SWM ); REG_OUTPUT( mmCP_ME_PS_EVENT_SRC ); REG_OUTPUT( mmCP_ME_PS_EVENT_ADDR ); + REG_OUTPUT( mmCP_ME_PS_EVENT_DATA ); REG_OUTPUT( mmCP_ME_PS_EVENT_ADDR_SWM ); REG_OUTPUT( mmCP_ME_PS_EVENT_DATA_SWM ); + REG_OUTPUT( mmCP_ME_CF_EVENT_SRC ); REG_OUTPUT( mmCP_ME_CF_EVENT_ADDR ); REG_OUTPUT( mmCP_ME_CF_EVENT_DATA ); + REG_OUTPUT( mmCP_ME_NRT_ADDR ); REG_OUTPUT( mmCP_ME_NRT_DATA ); REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_SRC ); + REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_ADDR ); REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_DATA ); REG_OUTPUT( mmCP_INT_CNTL ); + REG_OUTPUT( mmCP_INT_STATUS ); REG_OUTPUT( mmCP_INT_ACK ); REG_OUTPUT( mmCP_PFP_UCODE_ADDR ); + REG_OUTPUT( mmCP_PFP_UCODE_DATA ); REG_OUTPUT( mmCP_PERFMON_CNTL ); REG_OUTPUT( mmCP_PERFCOUNTER_SELECT ); + REG_OUTPUT( mmCP_PERFCOUNTER_LO ); REG_OUTPUT( mmCP_PERFCOUNTER_HI ); REG_OUTPUT( mmCP_BIN_MASK_LO ); + REG_OUTPUT( mmCP_BIN_MASK_HI ); REG_OUTPUT( mmCP_BIN_SELECT_LO ); REG_OUTPUT( mmCP_BIN_SELECT_HI ); + REG_OUTPUT( mmCP_NV_FLAGS_0 ); REG_OUTPUT( mmCP_NV_FLAGS_1 ); REG_OUTPUT( mmCP_NV_FLAGS_2 ); + REG_OUTPUT( mmCP_NV_FLAGS_3 ); REG_OUTPUT( mmCP_STATE_DEBUG_INDEX ); REG_OUTPUT( mmCP_STATE_DEBUG_DATA ); + REG_OUTPUT( mmCP_PROG_COUNTER ); REG_OUTPUT( mmCP_STAT ); REG_OUTPUT( mmBIOS_0_SCRATCH ); + REG_OUTPUT( mmBIOS_1_SCRATCH ); REG_OUTPUT( mmBIOS_2_SCRATCH ); REG_OUTPUT( mmBIOS_3_SCRATCH ); + REG_OUTPUT( mmBIOS_4_SCRATCH ); REG_OUTPUT( mmBIOS_5_SCRATCH ); REG_OUTPUT( mmBIOS_6_SCRATCH ); + REG_OUTPUT( mmBIOS_7_SCRATCH ); REG_OUTPUT( mmBIOS_8_SCRATCH ); REG_OUTPUT( mmBIOS_9_SCRATCH ); + REG_OUTPUT( mmBIOS_10_SCRATCH ); REG_OUTPUT( mmBIOS_11_SCRATCH ); REG_OUTPUT( mmBIOS_12_SCRATCH ); + REG_OUTPUT( mmBIOS_13_SCRATCH ); REG_OUTPUT( mmBIOS_14_SCRATCH ); REG_OUTPUT( mmBIOS_15_SCRATCH ); + REG_OUTPUT( mmCOHER_SIZE_PM4 ); REG_OUTPUT( mmCOHER_BASE_PM4 ); REG_OUTPUT( mmCOHER_STATUS_PM4 ); + REG_OUTPUT( mmCOHER_SIZE_HOST ); REG_OUTPUT( mmCOHER_BASE_HOST ); REG_OUTPUT( mmCOHER_STATUS_HOST ); + REG_OUTPUT( mmCOHER_DEST_BASE_0 ); REG_OUTPUT( mmCOHER_DEST_BASE_1 ); REG_OUTPUT( mmCOHER_DEST_BASE_2 ); + REG_OUTPUT( mmCOHER_DEST_BASE_3 ); REG_OUTPUT( mmCOHER_DEST_BASE_4 ); REG_OUTPUT( mmCOHER_DEST_BASE_5 ); + REG_OUTPUT( mmCOHER_DEST_BASE_6 ); REG_OUTPUT( mmCOHER_DEST_BASE_7 ); REG_OUTPUT( mmRB_SURFACE_INFO ); + REG_OUTPUT( mmRB_COLOR_INFO ); REG_OUTPUT( mmRB_DEPTH_INFO ); REG_OUTPUT( mmRB_STENCILREFMASK ); + REG_OUTPUT( mmRB_ALPHA_REF ); REG_OUTPUT( mmRB_COLOR_MASK ); REG_OUTPUT( mmRB_BLEND_RED ); + REG_OUTPUT( mmRB_BLEND_GREEN ); REG_OUTPUT( mmRB_BLEND_BLUE ); REG_OUTPUT( mmRB_BLEND_ALPHA ); + REG_OUTPUT( mmRB_FOG_COLOR ); REG_OUTPUT( mmRB_STENCILREFMASK_BF ); REG_OUTPUT( mmRB_DEPTHCONTROL ); + REG_OUTPUT( mmRB_BLENDCONTROL ); REG_OUTPUT( mmRB_COLORCONTROL ); REG_OUTPUT( mmRB_MODECONTROL ); + REG_OUTPUT( mmRB_COLOR_DEST_MASK ); REG_OUTPUT( mmRB_COPY_CONTROL ); REG_OUTPUT( mmRB_COPY_DEST_BASE ); + REG_OUTPUT( mmRB_COPY_DEST_PITCH ); REG_OUTPUT( mmRB_COPY_DEST_INFO ); REG_OUTPUT( mmRB_COPY_DEST_PIXEL_OFFSET ); + REG_OUTPUT( mmRB_DEPTH_CLEAR ); REG_OUTPUT( mmRB_SAMPLE_COUNT_CTL ); REG_OUTPUT( mmRB_SAMPLE_COUNT_ADDR ); + REG_OUTPUT( mmRB_BC_CONTROL ); REG_OUTPUT( mmRB_EDRAM_INFO ); REG_OUTPUT( mmRB_CRC_RD_PORT ); + REG_OUTPUT( mmRB_CRC_CONTROL ); REG_OUTPUT( mmRB_CRC_MASK ); REG_OUTPUT( mmRB_PERFCOUNTER0_SELECT ); + REG_OUTPUT( mmRB_PERFCOUNTER0_LOW ); REG_OUTPUT( mmRB_PERFCOUNTER0_HI ); REG_OUTPUT( mmRB_TOTAL_SAMPLES ); + REG_OUTPUT( mmRB_ZPASS_SAMPLES ); REG_OUTPUT( mmRB_ZFAIL_SAMPLES ); REG_OUTPUT( mmRB_SFAIL_SAMPLES ); + REG_OUTPUT( mmRB_DEBUG_0 ); REG_OUTPUT( mmRB_DEBUG_1 ); REG_OUTPUT( mmRB_DEBUG_2 ); + REG_OUTPUT( mmRB_DEBUG_3 ); REG_OUTPUT( mmRB_DEBUG_4 ); REG_OUTPUT( mmRB_FLAG_CONTROL ); + REG_OUTPUT( mmRB_BC_SPARES ); REG_OUTPUT( mmBC_DUMMY_CRAYRB_ENUMS ); REG_OUTPUT( mmBC_DUMMY_CRAYRB_MOREENUMS ); + + default: + b += sprintf( b, "%s", "UNKNOWN REGISTER OFFSET" ); + break; + } + // Handle string after %R + kos_memcpy( b, p1+2, p2-(p1+2) ); + b += (unsigned int)p2-(unsigned int)(p1+2); + *b = '\0'; + } + break; + + + default: + { + int val = va_arg( arguments, int ); + // Standard format. Use vsprintf. + b += sprintf( b, buffer2, val ); + } + break; + } + + + c = p2; + } + + // Add this string to all outputs + output = outputs; + + while( output != NULL ) + { + // Filter according to the flags + if( ( output->flags & log_flags ) == log_flags ) + { + // Passed the filter. Now commit this message. + switch( output->type ) + { + case KGSL_OUTPUT_TYPE_MEMBUF: + // TODO + break; + + case KGSL_OUTPUT_TYPE_STDOUT: + // Write timestamp if enabled + if( output->flags & KGSL_LOG_TIMESTAMP ) + printf( "[Timestamp: %d] ", kos_timestamp() ); + // Write process id if enabled + if( output->flags & KGSL_LOG_PROCESS_ID ) + printf( "[Process ID: %d] ", kos_process_getid() ); + // Write thread id if enabled + if( output->flags & KGSL_LOG_THREAD_ID ) + printf( "[Thread ID: %d] ", kos_thread_getid() ); + + // Write the message + printf( buffer ); + break; + + case KGSL_OUTPUT_TYPE_FILE: + // Write timestamp if enabled + if( output->flags & KGSL_LOG_TIMESTAMP ) + kos_fprintf( output->file, "[Timestamp: %d] ", kos_timestamp() ); + // Write process id if enabled + if( output->flags & KGSL_LOG_PROCESS_ID ) + kos_fprintf( output->file, "[Process ID: %d] ", kos_process_getid() ); + // Write thread id if enabled + if( output->flags & KGSL_LOG_THREAD_ID ) + kos_fprintf( output->file, "[Thread ID: %d] ", kos_thread_getid() ); + + // Write the message + kos_fprintf( output->file, buffer ); + break; + } + } + + output = output->next; + } + + va_end( arguments ); + + kos_mutex_unlock( log_mutex ); + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- +#endif diff --git a/drivers/mxc/amd-gpu/common/gsl_memmgr.c b/drivers/mxc/amd-gpu/common/gsl_memmgr.c new file mode 100644 index 000000000000..75f250ae59b1 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_memmgr.c @@ -0,0 +1,949 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_MEMARENAPRIV_SIGNATURE_MASK 0x0000FFFF +#define GSL_MEMARENAPRIV_APERTUREID_MASK 0xF0000000 +#define GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK 0x0F000000 + +#define GSL_MEMARENAPRIV_SIGNATURE_SHIFT 0 +#define GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT 24 +#define GSL_MEMARENAPRIV_APERTUREID_SHIFT 28 + +#define GSL_MEMARENA_INSTANCE_SIGNATURE 0x0000CAFE + +#ifdef GSL_STATS_MEM +#define GSL_MEMARENA_STATS(x) x +#else +#define GSL_MEMARENA_STATS(x) +#endif // GSL_STATS_MEM + + +///////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define GSL_MEMARENA_LOCK() kos_mutex_lock(memarena->mutex) +#define GSL_MEMARENA_UNLOCK() kos_mutex_unlock(memarena->mutex) + +#define GSL_MEMARENA_SET_SIGNATURE (memarena->priv |= ((GSL_MEMARENA_INSTANCE_SIGNATURE << GSL_MEMARENAPRIV_SIGNATURE_SHIFT) & GSL_MEMARENAPRIV_SIGNATURE_MASK)) +#define GSL_MEMARENA_SET_MMU_VIRTUALIZED (memarena->priv |= ((mmu_virtualized << GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT) & GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK)) +#define GSL_MEMARENA_SET_ID (memarena->priv |= ((aperture_id << GSL_MEMARENAPRIV_APERTUREID_SHIFT) & GSL_MEMARENAPRIV_APERTUREID_MASK)) + +#define GSL_MEMARENA_GET_SIGNATURE ((memarena->priv & GSL_MEMARENAPRIV_SIGNATURE_MASK) >> GSL_MEMARENAPRIV_SIGNATURE_SHIFT) +#define GSL_MEMARENA_IS_MMU_VIRTUALIZED ((memarena->priv & GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK) >> GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT) +#define GSL_MEMARENA_GET_ID ((memarena->priv & GSL_MEMARENAPRIV_APERTUREID_MASK) >> GSL_MEMARENAPRIV_APERTUREID_SHIFT) + + +////////////////////////////////////////////////////////////////////////////// +// validate +////////////////////////////////////////////////////////////////////////////// +#define GSL_MEMARENA_VALIDATE(memarena) \ + KOS_ASSERT(memarena); \ + if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) \ + { \ + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, \ + "ERROR: Memarena validation failed.\n" ); \ + return (GSL_FAILURE); \ + } + +////////////////////////////////////////////////////////////////////////////// +// block alignment shift count +////////////////////////////////////////////////////////////////////////////// +OSINLINE unsigned int +gsl_memarena_alignmentshift(gsl_flags_t flags) +{ + int alignshift = ((flags & GSL_MEMFLAGS_ALIGN_MASK) >> GSL_MEMFLAGS_ALIGN_SHIFT); + if (alignshift == 0) + alignshift = 5; // 32 bytes is the minimum alignment boundary + return (alignshift); +} + +////////////////////////////////////////////////////////////////////////////// +// address alignment +////////////////////////////////////////////////////////////////////////////// +OSINLINE unsigned int +gsl_memarena_alignaddr(unsigned int address, int shift) +{ + // + // the value of the returned address is guaranteed to be an even multiple + // of the block alignment shift specified. + // + unsigned int alignedbaseaddr = ((address) >> shift) << shift; + if (alignedbaseaddr < address) + { + alignedbaseaddr += (1 << shift); + } + return (alignedbaseaddr); +} + + +////////////////////////////////////////////////////////////////////////////// +// memory management API +////////////////////////////////////////////////////////////////////////////// + +OSINLINE memblk_t* +kgsl_memarena_getmemblknode(gsl_memarena_t *memarena) +{ +#ifdef GSL_MEMARENA_NODE_POOL_ENABLED + gsl_nodepool_t *nodepool = memarena->nodepool; + memblk_t *memblk = NULL; + int allocnewpool = 1; + int i; + + if (nodepool) + { + // walk through list of existing pools + for ( ; ; ) + { + // if there is a pool with a free memblk node + if (nodepool->priv != (1 << GSL_MEMARENA_NODE_POOL_MAX)-1) + { + // get index of the first free memblk node + for (i = 0; i < GSL_MEMARENA_NODE_POOL_MAX; i++) + { + if (((nodepool->priv >> i) & 0x1) == 0) + { + break; + } + } + + // mark memblk node as used + nodepool->priv |= 1 << i; + + memblk = &nodepool->memblk[i]; + memblk->nodepoolindex = i; + memblk->blkaddr = 0; + memblk->blksize = 0; + + allocnewpool = 0; + + break; + } + else + { + nodepool = nodepool->next; + + if (nodepool == memarena->nodepool) + { + // no free memblk node found + break; + } + } + } + } + + // if no existing pool has a free memblk node + if (allocnewpool) + { + // alloc new pool of memblk nodes + nodepool = ((gsl_nodepool_t *)kos_malloc(sizeof(gsl_nodepool_t))); + if (nodepool) + { + kos_memset(nodepool, 0, sizeof(gsl_nodepool_t)); + + if (memarena->nodepool) + { + nodepool->next = memarena->nodepool->next; + nodepool->prev = memarena->nodepool; + memarena->nodepool->next->prev = nodepool; + memarena->nodepool->next = nodepool; + } + else + { + nodepool->next = nodepool; + nodepool->prev = nodepool; + } + + // reposition pool head + memarena->nodepool = nodepool; + + // mark memblk node as used + nodepool->priv |= 0x1; + + memblk = &nodepool->memblk[0]; + memblk->nodepoolindex = 0; + } + } + + KOS_ASSERT(memblk); + + return (memblk); +#else + // unreferenced formal parameter + (void) memarena; + + return ((memblk_t *)kos_malloc(sizeof(memblk_t))); +#endif // GSL_MEMARENA_NODE_POOL_ENABLED +} + +//---------------------------------------------------------------------------- + +OSINLINE void +kgsl_memarena_releasememblknode(gsl_memarena_t *memarena, memblk_t *memblk) +{ +#ifdef GSL_MEMARENA_NODE_POOL_ENABLED + gsl_nodepool_t *nodepool = memarena->nodepool; + + KOS_ASSERT(memblk); + KOS_ASSERT(nodepool); + + // locate pool to which this memblk node belongs + while (((unsigned int) memblk) < ((unsigned int) nodepool) || + ((unsigned int) memblk) > ((unsigned int) nodepool) + sizeof(gsl_nodepool_t)) + { + nodepool = nodepool->prev; + + KOS_ASSERT(nodepool != memarena->nodepool); + } + + // mark memblk node as unused + nodepool->priv &= ~(1 << memblk->nodepoolindex); + + // free pool when all its memblk nodes are unused + if (nodepool->priv == 0) + { + if (nodepool != nodepool->prev) + { + // reposition pool head + if (nodepool == memarena->nodepool) + { + memarena->nodepool = nodepool->prev; + } + + nodepool->prev->next = nodepool->next; + nodepool->next->prev = nodepool->prev; + } + else + { + memarena->nodepool = NULL; + } + + kos_free((void *)nodepool); + } + else + { + // leave pool head in last pool a memblk node was released + memarena->nodepool = nodepool; + } +#else + // unreferenced formal parameter + (void) memarena; + + kos_free((void *)memblk); +#endif // GSL_MEMARENA_NODE_POOL_ENABLED +} + +//---------------------------------------------------------------------------- + +gsl_memarena_t* +kgsl_memarena_create(int aperture_id, int mmu_virtualized, unsigned int hostbaseaddr, gpuaddr_t gpubaseaddr, int sizebytes) +{ + static int count = 0; + char name[100], id_str[2]; + int len; + gsl_memarena_t *memarena; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> gsl_memarena_t* kgsl_memarena_create(int aperture_id=%d, gpuaddr_t gpubaseaddr=0x%08x, int sizebytes=%d)\n", aperture_id, gpubaseaddr, sizebytes ); + + memarena = (gsl_memarena_t *)kos_malloc(sizeof(gsl_memarena_t)); + + if (!memarena) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, + "ERROR: Memarena allocation failed.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "<-- kgsl_memarena_create. Return value: 0x%08x\n", NULL ); + return (NULL); + } + + kos_memset(memarena, 0, sizeof(gsl_memarena_t)); + + GSL_MEMARENA_SET_SIGNATURE; + GSL_MEMARENA_SET_MMU_VIRTUALIZED; + GSL_MEMARENA_SET_ID; + + // define unique mutex for each memory arena instance + id_str[0] = (char) (count + '0'); + id_str[1] = '\0'; + kos_strcpy(name, "GSL_memory_arena_"); + len = kos_strlen(name); + kos_strcpy(&name[len], id_str); + + memarena->mutex = kos_mutex_create(name); + + // set up the memory arena + memarena->hostbaseaddr = hostbaseaddr; + memarena->gpubaseaddr = gpubaseaddr; + memarena->sizebytes = sizebytes; + + // allocate a memory block in free list which represents all memory in arena + memarena->freelist.head = kgsl_memarena_getmemblknode(memarena); + memarena->freelist.head->blkaddr = 0; + memarena->freelist.head->blksize = memarena->sizebytes; + memarena->freelist.head->next = memarena->freelist.head; + memarena->freelist.head->prev = memarena->freelist.head; + memarena->freelist.allocrover = memarena->freelist.head; + memarena->freelist.freerover = memarena->freelist.head; + + count++; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_create. Return value: 0x%08x\n", memarena ); + + return (memarena); +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_destroy(gsl_memarena_t *memarena) +{ + int status = GSL_SUCCESS; + memblk_t *p, *next; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_memarena_destroy(gsl_memarena_t *memarena=0x%08x)\n", memarena ); + + GSL_MEMARENA_VALIDATE(memarena); + + GSL_MEMARENA_LOCK(); + +#ifdef _DEBUG + // memory leak check + if (memarena->freelist.head->blksize != memarena->sizebytes) + { + if (GSL_MEMARENA_GET_ID == GSL_APERTURE_EMEM) + { + // external memory leak detected + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, + "ERROR: External memory leak detected.\n" ); + return (GSL_FAILURE); + } + } +#endif // _DEBUG + + p = memarena->freelist.head; + do + { + next = p->next; + kgsl_memarena_releasememblknode(memarena, p); + p = next; + } while (p != memarena->freelist.head); + + GSL_MEMARENA_UNLOCK(); + + if (memarena->mutex) + { + kos_mutex_free(memarena->mutex); + } + + kos_free((void *)memarena); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_destroy. Return value: %B\n", GSL_SUCCESS ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_isvirtualized(gsl_memarena_t *memarena) +{ + // mmu virtualization enabled + return (GSL_MEMARENA_IS_MMU_VIRTUALIZED); +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_checkconsistency(gsl_memarena_t *memarena) +{ + memblk_t *p; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_memarena_checkconsistency(gsl_memarena_t *memarena=0x%08x)\n", memarena ); + + // go through list of free blocks and make sure there are no detectable errors + + p = memarena->freelist.head; + do + { + if (p->next->blkaddr != memarena->freelist.head->blkaddr) + { + if (p->prev->next->blkaddr != p->blkaddr || + p->next->prev->blkaddr != p->blkaddr || + p->blkaddr + p->blksize >= p->next->blkaddr) + { + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkconsistency. Return value: %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + } + p = p->next; + + } while (p != memarena->freelist.head); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkconsistency. Return value: %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_querystats(gsl_memarena_t *memarena, gsl_memarena_stats_t *stats) +{ +#ifdef GSL_STATS_MEM + KOS_ASSERT(stats); + GSL_MEMARENA_VALIDATE(memarena); + + kos_memcpy(stats, &memarena->stats, sizeof(gsl_memarena_stats_t)); + + return (GSL_SUCCESS); +#else + // unreferenced formal parameters + (void) memarena; + (void) stats; + + return (GSL_FAILURE_NOTSUPPORTED); +#endif // GSL_STATS_MEM +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_checkfreeblock(gsl_memarena_t *memarena, int bytesneeded) +{ + memblk_t *p; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_memarena_checkfreeblock(gsl_memarena_t *memarena=0x%08x, int bytesneeded=%d)\n", memarena, bytesneeded ); + + GSL_MEMARENA_VALIDATE(memarena); + + if (bytesneeded < 1) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Illegal number of bytes needed.\n" ); + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + GSL_MEMARENA_LOCK(); + + p = memarena->freelist.head; + do + { + if (p->blksize >= (unsigned int)bytesneeded) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + p = p->next; + } while (p != memarena->freelist.head); + + GSL_MEMARENA_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_FAILURE ); + + return (GSL_FAILURE); +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_memdesc_t *memdesc) +{ + int result = GSL_FAILURE_OUTOFMEM; + memblk_t *ptrfree, *ptrlast, *p; + unsigned int blksize; + unsigned int baseaddr, alignedbaseaddr, alignfragment; + int freeblk, alignmentshift; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_memarena_alloc(gsl_memarena_t *memarena=0x%08x, gsl_flags_t flags=0x%08x, int size=%d, gsl_memdesc_t *memdesc=%M)\n", memarena, flags, size, memdesc ); + + GSL_MEMARENA_VALIDATE(memarena); + + if (size <= 0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid size for memory allocation.\n" ); + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_alloc. Return value: %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // + // go through the list of free blocks. check to find block which can satisfy the alloc request + // + // if no block can satisfy the alloc request this implies that the memory is too fragmented + // and the requestor needs to free up other memory blocks and re-request the allocation + // + // if we do find a block that can satisfy the alloc request then reduce the size of free block + // by blksize and return the address after allocating the memory. if the free block size becomes + // 0 then remove this node from the free list + // + // there would be no node on the free list if all available memory were to be allocated. + // handling an empty list would require executing error checking code in the main branch which + // is not desired. instead, the free list will have at least one node at all times. This node + // could have a block size of zero + // + // we use a next fit allocation mechanism that uses a roving pointer on a circular free block list. + // the pointer is advanced along the chain when searching for a fit. Thus each allocation begins + // looking where the previous one finished. + // + + // when allocating from external memory aperture, round up size of requested block to multiple of page size if needed + if (GSL_MEMARENA_GET_ID == GSL_APERTURE_EMEM) + { + if ((flags & GSL_MEMFLAGS_FORCEPAGESIZE) || GSL_MEMARENA_IS_MMU_VIRTUALIZED) + { + if (size & (GSL_PAGESIZE-1)) + { + size = ((size >> GSL_PAGESIZE_SHIFT) + 1) << GSL_PAGESIZE_SHIFT; + } + } + } + + // determine shift count for alignment requested + alignmentshift = gsl_memarena_alignmentshift(flags); + + // adjust size of requested block to include alignment + blksize = (unsigned int)((size + ((1 << alignmentshift) - 1)) >> alignmentshift) << alignmentshift; + + GSL_MEMARENA_LOCK(); + + // check consistency, debug only + KGSL_DEBUG(GSL_DBGFLAGS_MEMMGR, kgsl_memarena_checkconsistency(memarena)); + + ptrfree = memarena->freelist.allocrover; + ptrlast = memarena->freelist.head->prev; + freeblk = 0; + + do + { + // align base address + baseaddr = ptrfree->blkaddr + memarena->gpubaseaddr; + alignedbaseaddr = gsl_memarena_alignaddr(baseaddr, alignmentshift); + + alignfragment = alignedbaseaddr - baseaddr; + + if (ptrfree->blksize >= blksize + alignfragment) + { + result = GSL_SUCCESS; + freeblk = 1; + + memdesc->gpuaddr = alignedbaseaddr; + memdesc->hostptr = kgsl_memarena_gethostptr(memarena, memdesc->gpuaddr); + memdesc->size = blksize; + + if (alignfragment > 0) + { + // insert new node to handle newly created (small) fragment + p = kgsl_memarena_getmemblknode(memarena); + p->blkaddr = ptrfree->blkaddr; + p->blksize = alignfragment; + + p->next = ptrfree; + p->prev = ptrfree->prev; + ptrfree->prev->next = p; + ptrfree->prev = p; + + if (ptrfree == memarena->freelist.head) + { + memarena->freelist.head = p; + } + } + + ptrfree->blkaddr += alignfragment + blksize; + ptrfree->blksize -= alignfragment + blksize; + + memarena->freelist.allocrover = ptrfree; + + if (ptrfree->blksize == 0 && ptrfree != ptrlast) + { + ptrfree->prev->next = ptrfree->next; + ptrfree->next->prev = ptrfree->prev; + if (ptrfree == memarena->freelist.head) + { + memarena->freelist.head = ptrfree->next; + } + if (ptrfree == memarena->freelist.allocrover) + { + memarena->freelist.allocrover = ptrfree->next; + } + if (ptrfree == memarena->freelist.freerover) + { + memarena->freelist.freerover = ptrfree->prev; + } + p = ptrfree; + ptrfree = ptrfree->prev; + kgsl_memarena_releasememblknode(memarena, p); + } + } + + ptrfree = ptrfree->next; + + } while (!freeblk && ptrfree != memarena->freelist.allocrover); + + GSL_MEMARENA_UNLOCK(); + + if (result == GSL_SUCCESS) + { + GSL_MEMARENA_STATS( + { + int i = 0; + while (memdesc->size >> (GSL_PAGESIZE_SHIFT + i)) + { + i++; + } + i = i > (GSL_MEMARENA_PAGE_DIST_MAX-1) ? (GSL_MEMARENA_PAGE_DIST_MAX-1) : i; + memarena->stats.allocs_pagedistribution[i]++; + }); + + GSL_MEMARENA_STATS(memarena->stats.allocs_success++); + } + else + { + GSL_MEMARENA_STATS(memarena->stats.allocs_fail++); + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_alloc. Return value: %B\n", result ); + + return (result); +} + +//---------------------------------------------------------------------------- + +void +kgsl_memarena_free(gsl_memarena_t *memarena, gsl_memdesc_t *memdesc) +{ + // + // request to free a malloc'ed block from the memory arena + // add this block to the free list + // adding a block to the free list requires the following: + // going through the list of free blocks to decide where to add this free block (based on address) + // coalesce free blocks + // + memblk_t *ptrfree, *ptrend, *p; + int mallocfreeblk, clockwise; + unsigned int addrtofree; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> void kgsl_memarena_free(gsl_memarena_t *memarena=0x%08x, gsl_memdesc_t *memdesc=%M)\n", memarena, memdesc ); + + KOS_ASSERT(memarena); + if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" ); + return; + } + + // check size of malloc'ed block + if (memdesc->size <= 0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Illegal size for the memdesc.\n" ); + KOS_ASSERT(0); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" ); + return; + } + + // check address range + KOS_ASSERT( memarena->gpubaseaddr <= memdesc->gpuaddr); + KOS_ASSERT((memarena->gpubaseaddr + memarena->sizebytes) >= memdesc->gpuaddr + memdesc->size); + + GSL_MEMARENA_LOCK(); + + // check consistency of memory map, debug only + KGSL_DEBUG(GSL_DBGFLAGS_MEMMGR, kgsl_memarena_checkconsistency(memarena)); + + addrtofree = memdesc->gpuaddr - memarena->gpubaseaddr; + mallocfreeblk = 1; + + if (addrtofree < memarena->freelist.head->blkaddr) + { + // add node to head of free list + + if (addrtofree + memdesc->size == memarena->freelist.head->blkaddr) + { + memarena->freelist.head->blkaddr = addrtofree; + memarena->freelist.head->blksize += memdesc->size; + + mallocfreeblk = 0; + } + + ptrfree = memarena->freelist.head->prev; + } + else if (addrtofree >= memarena->freelist.head->prev->blkaddr) + { + // add node to tail of free list + + ptrfree = memarena->freelist.head->prev; + + if (ptrfree->blkaddr + ptrfree->blksize == addrtofree) + { + ptrfree->blksize += memdesc->size; + + mallocfreeblk = 0; + } + } + else + { + // determine range of free list nodes to traverse and orientation in which to traverse them + // keep this code segment unrolled for performance reasons! + if (addrtofree > memarena->freelist.freerover->blkaddr) + { + if (addrtofree - memarena->freelist.freerover->blkaddr < memarena->freelist.head->prev->blkaddr - addrtofree) + { + ptrfree = memarena->freelist.freerover; // rover + ptrend = memarena->freelist.head->prev; // tail + clockwise = 1; + } + else + { + ptrfree = memarena->freelist.head->prev->prev; // tail + ptrend = memarena->freelist.freerover->prev; // rover + clockwise = 0; + } + } + else + { + if (addrtofree - memarena->freelist.head->blkaddr < memarena->freelist.freerover->blkaddr - addrtofree) + { + ptrfree = memarena->freelist.head; // head + ptrend = memarena->freelist.freerover; // rover + clockwise = 1; + } + else + { + ptrfree = memarena->freelist.freerover->prev; // rover + ptrend = memarena->freelist.head->prev; // head + clockwise = 0; + } + } + + // traverse the nodes + do + { + if ((addrtofree >= ptrfree->blkaddr + ptrfree->blksize) && + (addrtofree + memdesc->size <= ptrfree->next->blkaddr)) + { + if (addrtofree == ptrfree->blkaddr + ptrfree->blksize) + { + memblk_t *next; + + ptrfree->blksize += memdesc->size; + next = ptrfree->next; + + if (ptrfree->blkaddr + ptrfree->blksize == next->blkaddr) + { + ptrfree->blksize += next->blksize; + ptrfree->next = next->next; + next->next->prev = ptrfree; + + if (next == memarena->freelist.allocrover) + { + memarena->freelist.allocrover = ptrfree; + } + + kgsl_memarena_releasememblknode(memarena, next); + } + + mallocfreeblk = 0; + } + else if (addrtofree + memdesc->size == ptrfree->next->blkaddr) + { + ptrfree->next->blkaddr = addrtofree; + ptrfree->next->blksize += memdesc->size; + + mallocfreeblk = 0; + } + + break; + } + + if (clockwise) + { + ptrfree = ptrfree->next; + } + else + { + ptrfree = ptrfree->prev; + } + + } while (ptrfree != ptrend); + } + + // this free block could not be coalesced, so create a new free block + // and add it to the free list in the memory arena + if (mallocfreeblk) + { + p = kgsl_memarena_getmemblknode(memarena); + p->blkaddr = addrtofree; + p->blksize = memdesc->size; + + p->next = ptrfree->next; + p->prev = ptrfree; + ptrfree->next->prev = p; + ptrfree->next = p; + + if (p->blkaddr < memarena->freelist.head->blkaddr) + { + memarena->freelist.head = p; + } + + memarena->freelist.freerover = p; + } + else + { + memarena->freelist.freerover = ptrfree; + } + + GSL_MEMARENA_UNLOCK(); + + GSL_MEMARENA_STATS( + { + int i = 0; + while (memdesc->size >> (GSL_PAGESIZE_SHIFT + i)) + { + i++; + } + i = i > (GSL_MEMARENA_PAGE_DIST_MAX-1) ? (GSL_MEMARENA_PAGE_DIST_MAX-1) : i; + memarena->stats.frees_pagedistribution[i]++; + }); + + GSL_MEMARENA_STATS(memarena->stats.frees++); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" ); +} + +//---------------------------------------------------------------------------- + +void * +kgsl_memarena_gethostptr(gsl_memarena_t *memarena, gpuaddr_t gpuaddr) +{ + // + // get the host mapped address for a hardware device address + // + + void *hostptr = NULL; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> void* kgsl_memarena_gethostptr(gsl_memarena_t *memarena=0x%08x, gpuaddr_t gpuaddr=0x%08x)\n", memarena, gpuaddr ); + + KOS_ASSERT(memarena); + if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_gethostptr. Return value: 0x%08x\n", NULL ); + return (NULL); + } + + // check address range + KOS_ASSERT(gpuaddr >= memarena->gpubaseaddr); + KOS_ASSERT(gpuaddr < memarena->gpubaseaddr + memarena->sizebytes); + + hostptr = (void *)((gpuaddr - memarena->gpubaseaddr) + memarena->hostbaseaddr); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_gethostptr. Return value: 0x%08x\n", hostptr ); + + return (hostptr); +} + +//---------------------------------------------------------------------------- + +gpuaddr_t +kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena, void *hostptr) +{ + // + // get the hardware device address for a host mapped address + // + + gpuaddr_t gpuaddr = 0; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena=0x%08x, void *hostptr=0x%08x)\n", memarena, hostptr ); + + KOS_ASSERT(memarena); + if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getgpuaddr. Return value: 0x%08x\n", 0 ); + return (0); + } + + // check address range + KOS_ASSERT(hostptr >= (void *)memarena->hostbaseaddr); + KOS_ASSERT(hostptr < (void *)(memarena->hostbaseaddr + memarena->sizebytes)); + + gpuaddr = ((unsigned int)hostptr - memarena->hostbaseaddr) + memarena->gpubaseaddr; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getgpuaddr. Return value: 0x%08x\n", gpuaddr ); + + return (gpuaddr); +} + +//---------------------------------------------------------------------------- + +unsigned int +kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena, gsl_flags_t flags) +{ + memblk_t *ptrfree; + unsigned int blocksize, largestblocksize = 0; + int alignmentshift; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> unsigned int kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena=0x%08x, gsl_flags_t flags=0x%08x)\n", memarena, flags ); + + KOS_ASSERT(memarena); + if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getlargestfreeblock. Return value: %d\n", 0 ); + return (0); + } + + // determine shift count for alignment requested + alignmentshift = gsl_memarena_alignmentshift(flags); + + GSL_MEMARENA_LOCK(); + + ptrfree = memarena->freelist.head; + + do + { + blocksize = ptrfree->blksize - (ptrfree->blkaddr - ((ptrfree->blkaddr >> alignmentshift) << alignmentshift)); + + if (blocksize > largestblocksize) + { + largestblocksize = blocksize; + } + + ptrfree = ptrfree->next; + + } while (ptrfree != memarena->freelist.head); + + GSL_MEMARENA_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getlargestfreeblock. Return value: %d\n", largestblocksize ); + + return (largestblocksize); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_mmu.c b/drivers/mxc/amd-gpu/common/gsl_mmu.c new file mode 100644 index 000000000000..310677d926f0 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_mmu.c @@ -0,0 +1,1036 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// --------- +// pte debug +// --------- + +typedef struct _gsl_pte_debug_t +{ + unsigned int write :1; + unsigned int read :1; + unsigned int reserved :10; + unsigned int phyaddr :20; +} gsl_pte_debug_t; + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_PT_ENTRY_SIZEBYTES 4 +#define GSL_PT_EXTRA_ENTRIES 16 + +#define GSL_PT_PAGE_WRITE 0x00000001 +#define GSL_PT_PAGE_READ 0x00000002 + +#define GSL_PT_PAGE_AP_MASK 0x00000003 +#define GSL_PT_PAGE_ADDR_MASK ~(GSL_PAGESIZE-1) + +#define GSL_MMUFLAGS_TLBFLUSH 0x80000000 + +#define GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS (sizeof(unsigned char) * 8) + + +////////////////////////////////////////////////////////////////////////////// +// constants +////////////////////////////////////////////////////////////////////////////// +const unsigned int GSL_PT_PAGE_AP[4] = {(GSL_PT_PAGE_READ | GSL_PT_PAGE_WRITE), GSL_PT_PAGE_READ, GSL_PT_PAGE_WRITE, 0}; + + +///////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// + +#define GSL_PT_ENTRY_GET(va) ((va - pagetable->va_base) >> GSL_PAGESIZE_SHIFT) +#define GSL_PT_VIRT_GET(pte) (pagetable->va_base + (pte * GSL_PAGESIZE)) + +#define GSL_PT_MAP_APDEFAULT GSL_PT_PAGE_AP[0] + +#define GSL_PT_MAP_GET(pte) *((unsigned int *)(((unsigned int)pagetable->base.hostptr) + ((pte) * GSL_PT_ENTRY_SIZEBYTES))) +#define GSL_PT_MAP_GETADDR(pte) (GSL_PT_MAP_GET(pte) & GSL_PT_PAGE_ADDR_MASK) + +#define GSL_PT_MAP_DEBUG(pte) ((gsl_pte_debug_t*) &GSL_PT_MAP_GET(pte)) + +#define GSL_PT_MAP_SETBITS(pte, bits) (GSL_PT_MAP_GET(pte) |= (((unsigned int) bits) & GSL_PT_PAGE_AP_MASK)) +#define GSL_PT_MAP_SETADDR(pte, pageaddr) (GSL_PT_MAP_GET(pte) = (GSL_PT_MAP_GET(pte) & ~GSL_PT_PAGE_ADDR_MASK) | (((unsigned int) pageaddr) & GSL_PT_PAGE_ADDR_MASK)) + +#define GSL_PT_MAP_RESET(pte) (GSL_PT_MAP_GET(pte) = 0) +#define GSL_PT_MAP_RESETBITS(pte, bits) (GSL_PT_MAP_GET(pte) &= ~(((unsigned int) bits) & GSL_PT_PAGE_AP_MASK)) + +#define GSL_MMU_VIRT_TO_PAGE(va) *((unsigned int *)(pagetable->base.gpuaddr + (GSL_PT_ENTRY_GET(va) * GSL_PT_ENTRY_SIZEBYTES))) +#define GSL_MMU_VIRT_TO_PHYS(va) ((GSL_MMU_VIRT_TO_PAGE(va) & GSL_PT_PAGE_ADDR_MASK) + (va & (GSL_PAGESIZE-1))) + +#define GSL_TLBFLUSH_FILTER_GET(superpte) *((unsigned char *)(((unsigned int)mmu->tlbflushfilter.base) + (superpte / GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS))) +#define GSL_TLBFLUSH_FILTER_SETDIRTY(superpte) (GSL_TLBFLUSH_FILTER_GET((superpte)) |= 1 << (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS)) +#define GSL_TLBFLUSH_FILTER_ISDIRTY(superpte) (GSL_TLBFLUSH_FILTER_GET((superpte)) & (1 << (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS))) +#define GSL_TLBFLUSH_FILTER_RESET() kos_memset(mmu->tlbflushfilter.base, 0, mmu->tlbflushfilter.size) + + +////////////////////////////////////////////////////////////////////////////// +// process index in pagetable object table +////////////////////////////////////////////////////////////////////////////// +OSINLINE int +kgsl_mmu_getprocessindex(unsigned int pid, int *pindex) +{ + int status = GSL_SUCCESS; +#ifdef GSL_MMU_PAGETABLE_PERPROCESS + if (kgsl_driver_getcallerprocessindex(pid, pindex) != GSL_SUCCESS) + { + status = GSL_FAILURE; + } +#else + (void) pid; // unreferenced formal parameter + *pindex = 0; +#endif // GSL_MMU_PAGETABLE_PERPROCESS + return (status); +} + +////////////////////////////////////////////////////////////////////////////// +// pagetable object for current caller process +////////////////////////////////////////////////////////////////////////////// +OSINLINE gsl_pagetable_t* +kgsl_mmu_getpagetableobject(gsl_mmu_t *mmu, unsigned int pid) +{ + int pindex = 0; + if (kgsl_mmu_getprocessindex(pid, &pindex) == GSL_SUCCESS) + { + return (mmu->pagetable[pindex]); + } + else + { + return (NULL); + } +} + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +void +kgsl_mh_intrcallback(gsl_intrid_t id, void *cookie) +{ + gsl_mmu_t *mmu = (gsl_mmu_t *) cookie; + unsigned int devindex = mmu->device->id-1; // device_id is 1 based + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> void kgsl_mh_ntrcallback(gsl_intrid_t id=%I, void *cookie=0x%08x)\n", id, cookie ); + + // error condition interrupt + if (id == gsl_cfg_mh_intr[devindex].AXI_READ_ERROR || + id == gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR || + id == gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT) + { + mmu->device->ftbl.device_destroy(mmu->device); + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mh_intrcallback.\n" ); +} + +//---------------------------------------------------------------------------- + +#ifdef _DEBUG +static void +kgsl_mmu_debug(gsl_mmu_t *mmu, gsl_mmu_debug_t *regs) +{ + unsigned int devindex = mmu->device->id-1; // device_id is 1 based + + kos_memset(regs, 0, sizeof(gsl_mmu_debug_t)); + + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].CONFIG, ®s->config); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].MPU_BASE, ®s->mpu_base); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].MPU_END, ®s->mpu_end); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].VA_RANGE, ®s->va_range); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].PT_BASE, ®s->pt_base); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].PAGE_FAULT, ®s->page_fault); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].TRAN_ERROR, ®s->trans_error); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].INVALIDATE, ®s->invalidate); +} +#endif + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_checkconsistency(gsl_pagetable_t *pagetable) +{ + unsigned int pte; + unsigned int data; + gsl_pte_debug_t *pte_debug; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_mmu_checkconsistency(gsl_pagetable_t *pagetable=0x%08x)\n", pagetable ); + + if (pagetable->last_superpte % GSL_PT_SUPER_PTE != 0) + { + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_checkconsistency. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // go through page table and make sure there are no detectable errors + pte = 0; + while (pte < pagetable->max_entries) + { + pte_debug = GSL_PT_MAP_DEBUG(pte); + + if (GSL_PT_MAP_GETADDR(pte) != 0) + { + // pte is in use + + // access first couple bytes of a page + data = *((unsigned int *)GSL_PT_VIRT_GET(pte)); + } + + pte++; + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_checkconsistency. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_destroypagetableobject(gsl_mmu_t *mmu, unsigned int pid) +{ + gsl_deviceid_t tmp_id; + gsl_device_t *tmp_device; + int pindex; + gsl_pagetable_t *pagetable; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> gsl_pagetable_t* kgsl_mmu_destroypagetableobject(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid ); + + if (kgsl_mmu_getprocessindex(pid, &pindex) != GSL_SUCCESS) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_destroypagetableobject. Return value 0x%08x\n", GSL_SUCCESS ); + return (GSL_FAILURE); + } + + pagetable = mmu->pagetable[pindex]; + + // if pagetable object exists for current "current device mmu"/"current caller process" combination + if (pagetable) + { + // no more "device mmu"/"caller process" combinations attached to current pagetable object + if (pagetable->refcnt == 0) + { +#ifdef _DEBUG + // memory leak check + if (pagetable->last_superpte != 0 || GSL_PT_MAP_GETADDR(pagetable->last_superpte)) + { + /* many dumpx test cases forcefully exit, and thus trigger this assert. */ + /* Because it is an annoyance for HW guys, it is disabled for dumpx */ + if(!gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX) + { + KOS_ASSERT(0); + return (GSL_FAILURE); + } + } +#endif // _DEBUG + + if (pagetable->base.gpuaddr) + { + kgsl_sharedmem_free0(&pagetable->base, GSL_CALLER_PROCESSID_GET()); + } + + kos_free(pagetable); + + // clear pagetable object reference for all "device mmu"/"current caller process" combinations + for (tmp_id = GSL_DEVICE_ANY + 1; tmp_id <= GSL_DEVICE_MAX; tmp_id++) + { + tmp_device = &gsl_driver.device[tmp_id-1]; + + if (tmp_device->mmu.flags & GSL_FLAGS_STARTED) + { + tmp_device->mmu.pagetable[pindex] = NULL; + } + } + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_destroypagetableobject. Return value 0x%08x\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +gsl_pagetable_t* +kgsl_mmu_createpagetableobject(gsl_mmu_t *mmu, unsigned int pid) +{ + // + // create pagetable object for "current device mmu"/"current caller + // process" combination. If none exists, setup a new pagetable object. + // + int status = GSL_SUCCESS; + gsl_pagetable_t *tmp_pagetable = NULL; + gsl_deviceid_t tmp_id; + gsl_device_t *tmp_device; + int pindex; + gsl_flags_t flags; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> gsl_pagetable_t* kgsl_mmu_createpagetableobject(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid ); + + status = kgsl_mmu_getprocessindex(pid, &pindex); + if (status != GSL_SUCCESS) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", NULL ); + return (NULL); + } + // if pagetable object does not already exists for "current device mmu"/"current caller process" combination + if (!mmu->pagetable[pindex]) + { + // then, check if pagetable object already exists for any "other device mmu"/"current caller process" combination + for (tmp_id = GSL_DEVICE_ANY + 1; tmp_id <= GSL_DEVICE_MAX; tmp_id++) + { + tmp_device = &gsl_driver.device[tmp_id-1]; + + if (tmp_device->mmu.flags & GSL_FLAGS_STARTED) + { + if (tmp_device->mmu.pagetable[pindex]) + { + tmp_pagetable = tmp_device->mmu.pagetable[pindex]; + break; + } + } + } + + // pagetable object exists + if (tmp_pagetable) + { + KOS_ASSERT(tmp_pagetable->va_base == mmu->va_base); + KOS_ASSERT(tmp_pagetable->va_range == mmu->va_range); + + // set pagetable object reference + mmu->pagetable[pindex] = tmp_pagetable; + } + // create new pagetable object + else + { + mmu->pagetable[pindex] = (void *)kos_malloc(sizeof(gsl_pagetable_t)); + if (!mmu->pagetable[pindex]) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate pagetable object.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", NULL ); + return (NULL); + } + + kos_memset(mmu->pagetable[pindex], 0, sizeof(gsl_pagetable_t)); + + mmu->pagetable[pindex]->pid = pid; + mmu->pagetable[pindex]->refcnt = 0; + mmu->pagetable[pindex]->va_base = mmu->va_base; + mmu->pagetable[pindex]->va_range = mmu->va_range; + mmu->pagetable[pindex]->last_superpte = 0; + mmu->pagetable[pindex]->max_entries = (mmu->va_range >> GSL_PAGESIZE_SHIFT) + GSL_PT_EXTRA_ENTRIES; + + // allocate page table memory + flags = (GSL_MEMFLAGS_ALIGN4K | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST); + status = kgsl_sharedmem_alloc0(mmu->device->id, flags, mmu->pagetable[pindex]->max_entries * GSL_PT_ENTRY_SIZEBYTES, &mmu->pagetable[pindex]->base); + + if (status == GSL_SUCCESS) + { + // reset page table entries + kgsl_sharedmem_set0(&mmu->pagetable[pindex]->base, 0, 0, mmu->pagetable[pindex]->base.size); + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MMU_TBLADDR, mmu->pagetable[pindex]->base.gpuaddr, 0, mmu->pagetable[pindex]->base.size, "kgsl_mmu_init")); + } + else + { + kgsl_mmu_destroypagetableobject(mmu, pid); + } + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", mmu->pagetable[pindex] ); + + return (mmu->pagetable[pindex]); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_setpagetable(gsl_device_t *device, unsigned int pid) +{ + // + // set device mmu to use current caller process's page table + // + int status = GSL_SUCCESS; + unsigned int devindex = device->id-1; // device_id is 1 based + gsl_mmu_t *mmu = &device->mmu; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> gsl_pagetable_t* kgsl_mmu_setpagetable(gsl_device_t *device=0x%08x)\n", device ); + + if (mmu->flags & GSL_FLAGS_STARTED) + { +#ifdef GSL_MMU_PAGETABLE_PERPROCESS + // page table not current, then setup mmu to use new specified page table + if (mmu->hwpagetable->pid != pid) + { + gsl_pagetable_t *pagetable = kgsl_mmu_getpagetableobject(mmu, pid); + if (pagetable) + { + mmu->hwpagetable = pagetable; + + // flag tlb flush + mmu->flags |= GSL_MMUFLAGS_TLBFLUSH; + + status = mmu->device->ftbl.mmu_setpagetable(mmu->device, gsl_cfg_mmu_reg[devindex].PT_BASE, pagetable->base.gpuaddr, pid); + + GSL_MMU_STATS(mmu->stats.pt.switches++); + } + else + { + status = GSL_FAILURE; + } + } +#endif // GSL_MMU_PAGETABLE_PERPROCESS + + // if needed, invalidate device specific tlb + if ((mmu->flags & GSL_MMUFLAGS_TLBFLUSH) && status == GSL_SUCCESS) + { + mmu->flags &= ~GSL_MMUFLAGS_TLBFLUSH; + + GSL_TLBFLUSH_FILTER_RESET(); + + status = mmu->device->ftbl.mmu_tlbinvalidate(mmu->device, gsl_cfg_mmu_reg[devindex].INVALIDATE, pid); + + GSL_MMU_STATS(mmu->stats.tlbflushes++); + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_setpagetable. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_init(gsl_device_t *device) +{ + // + // intialize device mmu + // + // call this with the global lock held + // + int status; + gsl_flags_t flags; + gsl_pagetable_t *pagetable; + unsigned int devindex = device->id-1; // device_id is 1 based + gsl_mmu_t *mmu = &device->mmu; +#ifdef _DEBUG + gsl_mmu_debug_t regs; +#endif // _DEBUG + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_mmu_init(gsl_device_t *device=0x%08x)\n", device ); + + if (device->ftbl.mmu_tlbinvalidate == NULL || device->ftbl.mmu_setpagetable == NULL || + !(device->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + if (mmu->flags & GSL_FLAGS_INITIALIZED0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_INFO, "MMU already initialized.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + // setup backward reference + mmu->device = device; + + // disable MMU when running in safe mode + if (device->flags & GSL_FLAGS_SAFEMODE) + { + mmu->config = 0x00000000; + } + + // setup MMU and sub-client behavior + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].CONFIG, mmu->config); + + // enable axi interrupts + kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR, kgsl_mh_intrcallback, (void *) mmu); + kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR, kgsl_mh_intrcallback, (void *) mmu); + kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR); + kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR); + + mmu->refcnt = 0; + mmu->flags |= GSL_FLAGS_INITIALIZED0; + + // MMU enabled + if (mmu->config & 0x1) + { + // idle device + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + + // make sure aligned to pagesize + KOS_ASSERT((mmu->mpu_base & ((1 << GSL_PAGESIZE_SHIFT)-1)) == 0); + KOS_ASSERT(((mmu->mpu_base + mmu->mpu_range) & ((1 << GSL_PAGESIZE_SHIFT)-1)) == 0); + + // define physical memory range accessible by the core + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].MPU_BASE, mmu->mpu_base); + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].MPU_END, mmu->mpu_base + mmu->mpu_range); + + // enable page fault interrupt + kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT, kgsl_mh_intrcallback, (void *) mmu); + kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT); + + mmu->flags |= GSL_FLAGS_INITIALIZED; + + // sub-client MMU lookups require address translation + if ((mmu->config & ~0x1) > 0) + { + // make sure virtual address range is a multiple of 64Kb + KOS_ASSERT((mmu->va_range & ((1 << 16)-1)) == 0); + + // setup pagetable object + pagetable = kgsl_mmu_createpagetableobject(mmu, GSL_CALLER_PROCESSID_GET()); + if (!pagetable) + { + kgsl_mmu_close(device); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + mmu->hwpagetable = pagetable; + + // create tlb flush filter to track dirty superPTE's -- one bit per superPTE + mmu->tlbflushfilter.size = (mmu->va_range / (GSL_PAGESIZE * GSL_PT_SUPER_PTE * 8)) + 1; + mmu->tlbflushfilter.base = (unsigned int *)kos_malloc(mmu->tlbflushfilter.size); + if (!mmu->tlbflushfilter.base) + { + kgsl_mmu_close(device); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + GSL_TLBFLUSH_FILTER_RESET(); + + // set page table base + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].PT_BASE, mmu->hwpagetable->base.gpuaddr); + + // define virtual address range + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].VA_RANGE, (mmu->hwpagetable->va_base | (mmu->hwpagetable->va_range >> 16))); + + // allocate memory used for completing r/w operations that cannot be mapped by the MMU + flags = (GSL_MEMFLAGS_ALIGN32 | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST); + status = kgsl_sharedmem_alloc0(device->id, flags, 32, &mmu->dummyspace); + if (status != GSL_SUCCESS) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate dummy space memory.\n" ); + kgsl_mmu_close(device); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", status ); + return (status); + } + + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].TRAN_ERROR, mmu->dummyspace.gpuaddr); + + // call device specific tlb invalidate + device->ftbl.mmu_tlbinvalidate(device, gsl_cfg_mmu_reg[devindex].INVALIDATE, mmu->hwpagetable->pid); + + GSL_MMU_STATS(mmu->stats.tlbflushes++); + + mmu->flags |= GSL_FLAGS_STARTED; + } + } + + KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_debug(&device->mmu, ®s)); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *scatterlist, gsl_flags_t flags, unsigned int pid) +{ + // + // map physical pages into the gpu page table + // + int status = GSL_SUCCESS; + unsigned int i, phyaddr, ap; + unsigned int pte, ptefirst, ptelast, superpte; + int flushtlb; + gsl_pagetable_t *pagetable; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_mmu_map(gsl_mmu_t *mmu=0x%08x, gpuaddr_t gpubaseaddr=0x%08x, gsl_scatterlist_t *scatterlist=%M, gsl_flags_t flags=%d, unsigned int pid=%d)\n", + mmu, gpubaseaddr, scatterlist, flags, pid ); + + KOS_ASSERT(scatterlist); + + if (scatterlist->num <= 0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: num pages is too small.\n" ); + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_map. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // get gpu access permissions + ap = GSL_PT_PAGE_AP[((flags & GSL_MEMFLAGS_GPUAP_MASK) >> GSL_MEMFLAGS_GPUAP_SHIFT)]; + + pagetable = kgsl_mmu_getpagetableobject(mmu, pid); + if (!pagetable) + { + return (GSL_FAILURE); + } + + // check consistency, debug only + KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_checkconsistency(pagetable)); + + ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr); + ptelast = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (scatterlist->num-1))); + flushtlb = 0; + + if (!GSL_PT_MAP_GETADDR(ptefirst)) + { + // tlb needs to be flushed when the first and last pte are not at superpte boundaries + if ((ptefirst & (GSL_PT_SUPER_PTE-1)) != 0 || ((ptelast+1) & (GSL_PT_SUPER_PTE-1)) != 0) + { + flushtlb = 1; + } + + // create page table entries + for (pte = ptefirst; pte <= ptelast; pte++) + { + if (scatterlist->contiguous) + { + phyaddr = scatterlist->pages[0] + ((pte-ptefirst) * GSL_PAGESIZE); + } + else + { + phyaddr = scatterlist->pages[pte-ptefirst]; + } + + GSL_PT_MAP_SETADDR(pte, phyaddr); + GSL_PT_MAP_SETBITS(pte, ap); + + // tlb needs to be flushed when a dirty superPTE gets backed + if ((pte & (GSL_PT_SUPER_PTE-1)) == 0) + { + if (GSL_TLBFLUSH_FILTER_ISDIRTY(pte / GSL_PT_SUPER_PTE)) + { + flushtlb = 1; + } + } + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_SET_MMUTBL, pte , *(unsigned int*)(((char*)pagetable->base.hostptr) + (pte * GSL_PT_ENTRY_SIZEBYTES)), 0, "kgsl_mmu_map")); + } + + if (flushtlb) + { + // every device's tlb needs to be flushed because the current page table is shared among all devices + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + if (gsl_driver.device[i].flags & GSL_FLAGS_INITIALIZED) + { + gsl_driver.device[i].mmu.flags |= GSL_MMUFLAGS_TLBFLUSH; + } + } + } + + // determine new last mapped superPTE + superpte = ptelast - (ptelast & (GSL_PT_SUPER_PTE-1)); + if (superpte > pagetable->last_superpte) + { + pagetable->last_superpte = superpte; + } + + GSL_MMU_STATS(mmu->stats.pt.maps++); + } + else + { + // this should never happen + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, "FATAL: This should never happen.\n" ); + KOS_ASSERT(0); + status = GSL_FAILURE; + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_map. Return value %B\n", GSL_SUCCESS ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pid) +{ + // + // remove mappings in the specified address range from the gpu page table + // + int status = GSL_SUCCESS; + gsl_pagetable_t *pagetable; + unsigned int numpages; + unsigned int pte, ptefirst, ptelast, superpte; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_mmu_unmap(gsl_mmu_t *mmu=0x%08x, gpuaddr_t gpubaseaddr=0x%08x, int range=%d, unsigned int pid=%d)\n", + mmu, gpubaseaddr, range, pid ); + + if (range <= 0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Range is too small.\n" ); + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_unmap. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + numpages = (range >> GSL_PAGESIZE_SHIFT); + if (range & (GSL_PAGESIZE-1)) + { + numpages++; + } + + pagetable = kgsl_mmu_getpagetableobject(mmu, pid); + if (!pagetable) + { + return (GSL_FAILURE); + } + + // check consistency, debug only + KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_checkconsistency(pagetable)); + + ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr); + ptelast = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (numpages-1))); + + if (GSL_PT_MAP_GETADDR(ptefirst)) + { + superpte = ptefirst - (ptefirst & (GSL_PT_SUPER_PTE-1)); + GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / GSL_PT_SUPER_PTE); + + // remove page table entries + for (pte = ptefirst; pte <= ptelast; pte++) + { + GSL_PT_MAP_RESET(pte); + + superpte = pte - (pte & (GSL_PT_SUPER_PTE-1)); + if (pte == superpte) + { + GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / GSL_PT_SUPER_PTE); + } + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_SET_MMUTBL, pte, *(unsigned int*)(((char*)pagetable->base.hostptr) + (pte * GSL_PT_ENTRY_SIZEBYTES)), 0, "kgsl_mmu_unmap, reset superPTE")); + } + + // determine new last mapped superPTE + superpte = ptelast - (ptelast & (GSL_PT_SUPER_PTE-1)); + if (superpte == pagetable->last_superpte && pagetable->last_superpte >= GSL_PT_SUPER_PTE) + { + do + { + pagetable->last_superpte -= GSL_PT_SUPER_PTE; + } while (!GSL_PT_MAP_GETADDR(pagetable->last_superpte) && pagetable->last_superpte >= GSL_PT_SUPER_PTE); + } + + GSL_MMU_STATS(mmu->stats.pt.unmaps++); + } + else + { + // this should never happen + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, "FATAL: This should never happen.\n" ); + KOS_ASSERT(0); + status = GSL_FAILURE; + } + + // invalidate tlb, debug only + KGSL_DEBUG(GSL_DBGFLAGS_MMU, mmu->device->ftbl.mmu_tlbinvalidate(mmu->device, gsl_cfg_mmu_reg[mmu->device->id-1].INVALIDATE, pagetable->pid)); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_unmap. Return value %B\n", GSL_SUCCESS ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_getmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, gsl_scatterlist_t *scatterlist, unsigned int pid) +{ + // + // obtain scatter list of physical pages for the given gpu address range. + // if all pages are physically contiguous they are coalesced into a single + // scatterlist entry. + // + gsl_pagetable_t *pagetable; + unsigned int numpages; + unsigned int pte, ptefirst, ptelast; + unsigned int contiguous = 1; + + numpages = (range >> GSL_PAGESIZE_SHIFT); + if (range & (GSL_PAGESIZE-1)) + { + numpages++; + } + + if (range <= 0 || scatterlist->num != numpages) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Range is too small.\n" ); + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_getmap. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + pagetable = kgsl_mmu_getpagetableobject(mmu, pid); + if (!pagetable) + { + return (GSL_FAILURE); + } + + ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr); + ptelast = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (numpages-1))); + + // determine whether pages are physically contiguous + if (numpages > 1) + { + for (pte = ptefirst; pte <= ptelast-1; pte++) + { + if (GSL_PT_MAP_GETADDR(pte) + GSL_PAGESIZE != GSL_PT_MAP_GETADDR(pte+1)) + { + contiguous = 0; + break; + } + } + } + + if (!contiguous) + { + // populate scatter list + for (pte = ptefirst; pte <= ptelast; pte++) + { + scatterlist->pages[pte-ptefirst] = GSL_PT_MAP_GETADDR(pte); + } + } + else + { + // coalesce physically contiguous pages into a single scatter list entry + scatterlist->pages[0] = GSL_PT_MAP_GETADDR(ptefirst); + } + + scatterlist->contiguous = contiguous; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_close(gsl_device_t *device) +{ + // + // close device mmu + // + // call this with the global lock held + // + gsl_mmu_t *mmu = &device->mmu; + unsigned int devindex = mmu->device->id-1; // device_id is 1 based +#ifdef _DEBUG + int i; +#endif // _DEBUG + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_close(gsl_device_t *device=0x%08x)\n", device ); + + if (mmu->flags & GSL_FLAGS_INITIALIZED0) + { + if (mmu->flags & GSL_FLAGS_STARTED) + { + // terminate pagetable object + kgsl_mmu_destroypagetableobject(mmu, GSL_CALLER_PROCESSID_GET()); + } + + // no more processes attached to current device mmu + if (mmu->refcnt == 0) + { +#ifdef _DEBUG + // check if there are any orphaned pagetable objects lingering around + for (i = 0; i < GSL_MMU_PAGETABLE_MAX; i++) + { + if (mmu->pagetable[i]) + { + /* many dumpx test cases forcefully exit, and thus trigger this assert. */ + /* Because it is an annoyance for HW guys, it is disabled for dumpx */ + if(!gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX) + { + KOS_ASSERT(0); + return (GSL_FAILURE); + } + } + } +#endif // _DEBUG + + // disable mh interrupts + kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR); + kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR); + kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT); + + // disable MMU + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].CONFIG, 0x00000000); + + if (mmu->tlbflushfilter.base) + { + kos_free(mmu->tlbflushfilter.base); + } + + if (mmu->dummyspace.gpuaddr) + { + kgsl_sharedmem_free0(&mmu->dummyspace, GSL_CALLER_PROCESSID_GET()); + } + + mmu->flags &= ~GSL_FLAGS_STARTED; + mmu->flags &= ~GSL_FLAGS_INITIALIZED; + mmu->flags &= ~GSL_FLAGS_INITIALIZED0; + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_close. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_attachcallback(gsl_mmu_t *mmu, unsigned int pid) +{ + // + // attach process + // + // call this with the global lock held + // + int status = GSL_SUCCESS; + gsl_pagetable_t *pagetable; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_attachcallback(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid ); + + if (mmu->flags & GSL_FLAGS_INITIALIZED0) + { + // attach to current device mmu + mmu->refcnt++; + + if (mmu->flags & GSL_FLAGS_STARTED) + { + // attach to pagetable object + pagetable = kgsl_mmu_createpagetableobject(mmu, pid); + if(pagetable) + { + pagetable->refcnt++; + } + else + { + status = GSL_FAILURE; + } + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_attachcallback. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_detachcallback(gsl_mmu_t *mmu, unsigned int pid) +{ + // + // detach process + // + int status = GSL_SUCCESS; + gsl_pagetable_t *pagetable; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_detachcallback(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid ); + + if (mmu->flags & GSL_FLAGS_INITIALIZED0) + { + // detach from current device mmu + mmu->refcnt--; + + if (mmu->flags & GSL_FLAGS_STARTED) + { + // detach from pagetable object + pagetable = kgsl_mmu_getpagetableobject(mmu, pid); + if(pagetable) + { + pagetable->refcnt--; + } + else + { + status = GSL_FAILURE; + } + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_detachcallback. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_querystats(gsl_mmu_t *mmu, gsl_mmustats_t *stats) +{ +#ifdef GSL_STATS_MMU + int status = GSL_SUCCESS; + + KOS_ASSERT(stats); + + if (mmu->flags & GSL_FLAGS_STARTED) + { + kos_memcpy(stats, &mmu->stats, sizeof(gsl_mmustats_t)); + } + else + { + kos_memset(stats, 0, sizeof(gsl_mmustats_t)); + } + + return (status); +#else + // unreferenced formal parameters + (void) mmu; + (void) stats; + + return (GSL_FAILURE_NOTSUPPORTED); +#endif // GSL_STATS_MMU +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_bist(gsl_mmu_t *mmu) +{ + // unreferenced formal parameter + (void) mmu; + + return (GSL_SUCCESS); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c new file mode 100644 index 000000000000..c4b62b0174d2 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c @@ -0,0 +1,1154 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#include "gsl_cmdstream.h" + +#ifdef GSL_BLD_YAMATO + +////////////////////////////////////////////////////////////////////////////// +// ucode +////////////////////////////////////////////////////////////////////////////// +#define uint32 unsigned int + +#include "pm4_microcode.inl" +#include "pfp_microcode_nrt.inl" + +#undef uint32 + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_RB_NOP_SIZEDWORDS 2 // default is 2 +#define GSL_RB_PROTECTED_MODE_CONTROL 0x00000000 // protected mode error checking below register address 0x800 + // note: if CP_INTERRUPT packet is used then checking needs + // to change to below register address 0x7C8 + + +////////////////////////////////////////////////////////////////////////////// +// ringbuffer size log2 quadwords equivalent +////////////////////////////////////////////////////////////////////////////// +OSINLINE unsigned int +gsl_ringbuffer_sizelog2quadwords(unsigned int sizedwords) +{ + unsigned int sizelog2quadwords = 0; + int i = sizedwords >> 1; + while (i >>= 1) + { + sizelog2quadwords++; + } + return (sizelog2quadwords); +} + + +////////////////////////////////////////////////////////////////////////////// +// private prototypes +////////////////////////////////////////////////////////////////////////////// +#ifdef _DEBUG +static void kgsl_ringbuffer_debug(gsl_ringbuffer_t *rb, gsl_rb_debug_t *rb_debug); +#endif + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +void +kgsl_cp_intrcallback(gsl_intrid_t id, void *cookie) +{ + gsl_ringbuffer_t *rb = (gsl_ringbuffer_t *) cookie; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> void kgsl_cp_intrcallback(gsl_intrid_t id=%I, void *cookie=0x%08x)\n", id, cookie ); + + switch(id) + { + // error condition interrupt + case GSL_INTR_YDX_CP_T0_PACKET_IN_IB: + case GSL_INTR_YDX_CP_OPCODE_ERROR: + case GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR: + case GSL_INTR_YDX_CP_RESERVED_BIT_ERROR: + case GSL_INTR_YDX_CP_IB_ERROR: + + rb->device->ftbl.device_destroy(rb->device); + break; + + // non-error condition interrupt + case GSL_INTR_YDX_CP_SW_INT: + case GSL_INTR_YDX_CP_IB2_INT: + case GSL_INTR_YDX_CP_IB1_INT: + case GSL_INTR_YDX_CP_RING_BUFFER: + + // signal intr completion event + kos_event_signal(rb->device->intr.evnt[id]); + break; + + default: + + break; + } + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cp_intrcallback.\n" ); +} + +//---------------------------------------------------------------------------- + +void +kgsl_ringbuffer_watchdog() +{ + gsl_ringbuffer_t *rb = &(gsl_driver.device[GSL_DEVICE_YAMATO-1]).ringbuffer; // device_id is 1 based + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> void kgsl_ringbuffer_watchdog()\n" ); + + if (rb->flags & GSL_FLAGS_STARTED) + { + GSL_RB_GET_READPTR(rb, &rb->rptr); + + // ringbuffer is currently not empty + if (rb->rptr != rb->wptr) + { + // and a rptr sample was taken during interval n-1 + if (rb->watchdog.flags & GSL_FLAGS_ACTIVE) + { + // and the rptr did not advance between interval n-1 and n + if (rb->rptr == rb->watchdog.rptr_sample) + { + // then the core has hung + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_FATAL, + "ERROR: Watchdog detected core hung.\n" ); + + rb->device->ftbl.device_destroy(rb->device); + return; + } + } + + // save rptr sample for interval n + rb->watchdog.flags |= GSL_FLAGS_ACTIVE; + rb->watchdog.rptr_sample = rb->rptr; + } + else + { + // clear rptr sample for interval n + rb->watchdog.flags &= ~GSL_FLAGS_ACTIVE; + } + + } + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_watchdog.\n" ); +} + +//---------------------------------------------------------------------------- + +#ifdef _DEBUG + +OSINLINE void +kgsl_ringbuffer_checkregister(unsigned int reg, int pmodecheck) +{ + if (pmodecheck) + { + // check for register protection mode violation + if (reg <= (GSL_RB_PROTECTED_MODE_CONTROL & 0x3FFF)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Register protection mode violation.\n" ); + KOS_ASSERT(0); + } + } + + // range check register offset + if (reg > (gsl_driver.device[GSL_DEVICE_YAMATO-1].regspace.sizebytes >> 2)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Register out of range.\n" ); + KOS_ASSERT(0); + } +} + +//---------------------------------------------------------------------------- + +void +kgsl_ringbuffer_checkpm4type0(unsigned int header, unsigned int** cmds, int pmodeoff) +{ + pm4_type0 pm4header = *((pm4_type0*) &header); + unsigned int reg; + + if (pm4header.one_reg_wr) + { + reg = pm4header.base_index; + } + else + { + reg = pm4header.base_index + pm4header.count; + } + + kgsl_ringbuffer_checkregister(reg, !pmodeoff); + + *cmds += pm4header.count + 1; +} + +//---------------------------------------------------------------------------- + +void +kgsl_ringbuffer_checkpm4type3(unsigned int header, unsigned int** cmds, int indirection, int pmodeoff) +{ + pm4_type3 pm4header = *((pm4_type3*) &header); + unsigned int *ordinal2 = *cmds; + unsigned int *ibcmds, *end; + unsigned int reg, length; + + // check indirect buffer level + if (indirection > 2) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Only two levels of indirection supported.\n" ); + KOS_ASSERT(0); + } + + switch(pm4header.it_opcode) + { + case PM4_INDIRECT_BUFFER: + case PM4_INDIRECT_BUFFER_PFD: + + // determine ib host base and end address + ibcmds = (unsigned int*) kgsl_sharedmem_convertaddr(*ordinal2, 0); + end = ibcmds + *(ordinal2 + 1); + + // walk through the ib + while(ibcmds < end) + { + unsigned int tmpheader = *(ibcmds++); + + switch(tmpheader & PM4_PKT_MASK) + { + case PM4_TYPE0_PKT: + kgsl_ringbuffer_checkpm4type0(tmpheader, &ibcmds, pmodeoff); + break; + + case PM4_TYPE1_PKT: + case PM4_TYPE2_PKT: + break; + + case PM4_TYPE3_PKT: + kgsl_ringbuffer_checkpm4type3(tmpheader, &ibcmds, (indirection + 1), pmodeoff); + break; + } + } + break; + + case PM4_ME_INIT: + + if(indirection != 0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: ME INIT packet cannot reside in an ib.\n" ); + KOS_ASSERT(0); + } + break; + + case PM4_REG_RMW: + + reg = (*ordinal2) & 0x1FFF; + + kgsl_ringbuffer_checkregister(reg, !pmodeoff); + + break; + + case PM4_SET_CONSTANT: + + if((((*ordinal2) >> 16) & 0xFF) == 0x4) // incremental register update + { + reg = 0x2000 + ((*ordinal2) & 0x3FF); // gfx decode space address starts at 0x2000 + length = pm4header.count - 1; + + kgsl_ringbuffer_checkregister(reg + length, 0); + } + break; + + case PM4_LOAD_CONSTANT_CONTEXT: + + if(((*(ordinal2 + 1) >> 16) & 0xFF) == 0x4) // incremental register update + { + reg = 0x2000 + (*(ordinal2 + 1) & 0x3FF); // gfx decode space address starts at 0x2000 + length = *(ordinal2 + 2); + + kgsl_ringbuffer_checkregister(reg + length, 0); + } + break; + + case PM4_COND_WRITE: + + if(((*ordinal2) & 0x00000100) == 0x0) // write to register + { + reg = *(ordinal2 + 4) & 0x3FFF; + + kgsl_ringbuffer_checkregister(reg, !pmodeoff); + } + break; + } + + *cmds += pm4header.count + 1; +} + +//---------------------------------------------------------------------------- + +void +kgsl_ringbuffer_checkpm4(unsigned int* cmds, unsigned int sizedwords, int pmodeoff) +{ + unsigned int *ringcmds = cmds; + unsigned int *end = cmds + sizedwords; + + while(ringcmds < end) + { + unsigned int header = *(ringcmds++); + + switch(header & PM4_PKT_MASK) + { + case PM4_TYPE0_PKT: + kgsl_ringbuffer_checkpm4type0(header, &ringcmds, pmodeoff); + break; + + case PM4_TYPE1_PKT: + case PM4_TYPE2_PKT: + break; + + case PM4_TYPE3_PKT: + kgsl_ringbuffer_checkpm4type3(header, &ringcmds, 0, pmodeoff); + break; + } + } +} + +#endif // _DEBUG + +//---------------------------------------------------------------------------- + +static void +kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb) +{ + unsigned int value; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> static void kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb=0x%08x)\n", rb ); + + KOS_ASSERT(rb->wptr != 0); + + kgsl_device_active(rb->device); + + GSL_RB_UPDATE_WPTR_POLLING(rb); + + // send the wptr to the hw + rb->device->ftbl.device_regwrite(rb->device, mmCP_RB_WPTR, rb->wptr); + + // force wptr register to be updated + do + { + rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR, &value); + } while (value != rb->wptr); + + rb->flags |= GSL_FLAGS_ACTIVE; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_submit.\n" ); +} + +//---------------------------------------------------------------------------- + +static int +kgsl_ringbuffer_waitspace(gsl_ringbuffer_t *rb, unsigned int numcmds, int wptr_ahead) +{ + int nopcount; + unsigned int freecmds; + unsigned int *cmds; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> static int kgsl_ringbuffer_waitspace(gsl_ringbuffer_t *rb=0x%08x, unsigned int numcmds=%d, int wptr_ahead=%d)\n", + rb, numcmds, wptr_ahead ); + + + // if wptr ahead, fill the remaining with NOPs + if (wptr_ahead) + { + nopcount = rb->sizedwords - rb->wptr - 1; // -1 for header + + cmds = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr; + GSL_RB_WRITE(cmds, pm4_nop_packet(nopcount)); + rb->wptr++; + + kgsl_ringbuffer_submit(rb); + + rb->wptr = 0; + + GSL_RB_STATS(rb->stats.wraps++); + } + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RBWAIT, GSL_DEVICE_YAMATO, rb->wptr, numcmds, "kgsl_ringbuffer_waitspace")); + + // wait for space in ringbuffer + for( ; ; ) + { + GSL_RB_GET_READPTR(rb, &rb->rptr); + + freecmds = rb->rptr - rb->wptr; + + if ((freecmds == 0) || (freecmds > numcmds)) + { + break; + } + + } + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +static unsigned int * +kgsl_ringbuffer_addcmds(gsl_ringbuffer_t *rb, unsigned int numcmds) +{ + unsigned int *ptr; + int status = GSL_SUCCESS; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> static unsigned int* kgsl_ringbuffer_addcmds(gsl_ringbuffer_t *rb=0x%08x, unsigned int numcmds=%d)\n", + rb, numcmds ); + + KOS_ASSERT(numcmds < rb->sizedwords); + + // update host copy of read pointer when running in safe mode + if (rb->device->flags & GSL_FLAGS_SAFEMODE) + { + GSL_RB_GET_READPTR(rb, &rb->rptr); + } + + // check for available space + if (rb->wptr >= rb->rptr) + { + // wptr ahead or equal to rptr + if ((rb->wptr + numcmds) > (rb->sizedwords - GSL_RB_NOP_SIZEDWORDS)) // reserve dwords for nop packet + { + status = kgsl_ringbuffer_waitspace(rb, numcmds, 1); + } + } + else + { + // wptr behind rptr + if ((rb->wptr + numcmds) >= rb->rptr) + { + status = kgsl_ringbuffer_waitspace(rb, numcmds, 0); + } + + // check for remaining space + if ((rb->wptr + numcmds) > (rb->sizedwords - GSL_RB_NOP_SIZEDWORDS)) // reserve dwords for nop packet + { + status = kgsl_ringbuffer_waitspace(rb, numcmds, 1); + } + } + + ptr = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr; + rb->wptr += numcmds; + + if (status == GSL_SUCCESS) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value 0x%08x\n", ptr ); + return (ptr); + } + else + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value 0x%08x\n", NULL ); + return (NULL); + } +} + +//---------------------------------------------------------------------------- +int +kgsl_ringbuffer_start(gsl_ringbuffer_t *rb) +{ + int status; + cp_rb_cntl_u cp_rb_cntl; + int i; + unsigned int *cmds; + gsl_device_t *device = rb->device; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> static int kgsl_ringbuffer_start(gsl_ringbuffer_t *rb=0x%08x)\n", rb ); + + if (rb->flags & GSL_FLAGS_STARTED) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_start. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + // clear memptrs values + kgsl_sharedmem_set0(&rb->memptrs_desc, 0, 0, sizeof(gsl_rbmemptrs_t)); + + // clear ringbuffer + kgsl_sharedmem_set0(&rb->buffer_desc, 0, 0x12341234, (rb->sizedwords << 2)); + + // setup WPTR polling address + device->ftbl.device_regwrite(device, mmCP_RB_WPTR_BASE, (rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_WPTRPOLL_OFFSET)); + + // setup WPTR delay + device->ftbl.device_regwrite(device, mmCP_RB_WPTR_DELAY, 0/*0x70000010*/); + + // setup RB_CNTL + device->ftbl.device_regread(device, mmCP_RB_CNTL, (unsigned int *)&cp_rb_cntl); + + cp_rb_cntl.f.rb_bufsz = gsl_ringbuffer_sizelog2quadwords(rb->sizedwords); // size of ringbuffer + cp_rb_cntl.f.rb_blksz = rb->blksizequadwords; // quadwords to read before updating mem RPTR + cp_rb_cntl.f.rb_poll_en = GSL_RB_CNTL_POLL_EN; // WPTR polling + cp_rb_cntl.f.rb_no_update = GSL_RB_CNTL_NO_UPDATE; // mem RPTR writebacks + + device->ftbl.device_regwrite(device, mmCP_RB_CNTL, cp_rb_cntl.val); + + // setup RB_BASE + device->ftbl.device_regwrite(device, mmCP_RB_BASE, rb->buffer_desc.gpuaddr); + + // setup RPTR_ADDR + device->ftbl.device_regwrite(device, mmCP_RB_RPTR_ADDR, rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_RPTR_OFFSET); + + // explicitly clear all cp interrupts when running in safe mode + if (rb->device->flags & GSL_FLAGS_SAFEMODE) + { + device->ftbl.device_regwrite(device, mmCP_INT_ACK, 0xFFFFFFFF); + } + + // setup scratch/timestamp addr + device->ftbl.device_regwrite(device, mmSCRATCH_ADDR, device->memstore.gpuaddr + GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp)); + + // setup scratch/timestamp mask + device->ftbl.device_regwrite(device, mmSCRATCH_UMSK, GSL_RB_MEMPTRS_SCRATCH_MASK); + + // load the CP ucode + device->ftbl.device_regwrite(device, mmCP_DEBUG, 0x02000000); + device->ftbl.device_regwrite(device, mmCP_ME_RAM_WADDR, 0); + + for (i = 0; i < PM4_MICROCODE_SIZE; i++ ) + { + device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][0]); + device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][1]); + device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][2]); + } + + // load the prefetch parser ucode + device->ftbl.device_regwrite(device, mmCP_PFP_UCODE_ADDR, 0); + + for ( i = 0; i < PFP_MICROCODE_SIZE_NRT; i++ ) + { + device->ftbl.device_regwrite(device, mmCP_PFP_UCODE_DATA, aPFP_Microcode_nrt[i]); + } + + // queue thresholds ??? + device->ftbl.device_regwrite(device, mmCP_QUEUE_THRESHOLDS, 0x000C0804); + + // reset pointers + rb->rptr = 0; + rb->wptr = 0; + + // init timestamp + rb->timestamp = 0; + GSL_RB_INIT_TIMESTAMP(rb); + + // clear ME_HALT to start micro engine + device->ftbl.device_regwrite(device, mmCP_ME_CNTL, 0); + + // ME_INIT + cmds = kgsl_ringbuffer_addcmds(rb, 19); + + GSL_RB_WRITE(cmds, PM4_HDR_ME_INIT); + GSL_RB_WRITE(cmds, 0x000003ff); // All fields present (bits 9:0) + GSL_RB_WRITE(cmds, 0x00000000); // Disable/Enable Real-Time Stream processing (present but ignored) + GSL_RB_WRITE(cmds, 0x00000000); // Enable (2D to 3D) and (3D to 2D) implicit synchronization (present but ignored) + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmRB_SURFACE_INFO)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SC_WINDOW_OFFSET)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmVGT_MAX_VTX_INDX)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmSQ_PROGRAM_CNTL)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmRB_DEPTHCONTROL)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SU_POINT_SIZE)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SC_LINE_CNTL)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SU_POLY_OFFSET_FRONT_SCALE)); + GSL_RB_WRITE(cmds, 0x80000180); // Vertex and Pixel Shader Start Addresses in instructions (3 DWORDS per instruction) + GSL_RB_WRITE(cmds, 0x00000001); // Maximum Contexts + GSL_RB_WRITE(cmds, 0x00000000); // Write Confirm Interval and The CP will wait the wait_interval * 16 clocks between polling + GSL_RB_WRITE(cmds, 0x00000000); // NQ and External Memory Swap + GSL_RB_WRITE(cmds, GSL_RB_PROTECTED_MODE_CONTROL); // Protected mode error checking + GSL_RB_WRITE(cmds, 0x00000000); // Disable header dumping and Header dump address + GSL_RB_WRITE(cmds, 0x00000000); // Header dump size + + KGSL_DEBUG(GSL_DBGFLAGS_PM4CHECK, kgsl_ringbuffer_checkpm4((unsigned int *)rb->buffer_desc.hostptr, 19, 1)); + KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPPM4((unsigned int *)rb->buffer_desc.hostptr, 19)); + + kgsl_ringbuffer_submit(rb); + + // idle device to validate ME INIT + status = device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + + if (status == GSL_SUCCESS) + { + rb->flags |= GSL_FLAGS_STARTED; + } + + // enable cp interrupts + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_SW_INT, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB_ERROR, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB2_INT, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB1_INT, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_SW_INT); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB_ERROR); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB2_INT); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB1_INT); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER); + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_start. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb) +{ + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> static int kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb=0x%08x)\n", rb ); + + if (rb->flags & GSL_FLAGS_STARTED) + { + // disable cp interrupts + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_SW_INT); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB_ERROR); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB2_INT); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB1_INT); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_RING_BUFFER); + + // ME_HALT + rb->device->ftbl.device_regwrite(rb->device, mmCP_ME_CNTL, 0x10000000); + + rb->flags &= ~GSL_FLAGS_STARTED; + } + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_stop. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_ringbuffer_init(gsl_device_t *device) +{ + int status; + gsl_flags_t flags; + gsl_ringbuffer_t *rb = &device->ringbuffer; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_ringbuffer_init(gsl_device_t *device=0x%08x)\n", device ); + + rb->device = device; + rb->sizedwords = (2 << gsl_cfg_rb_sizelog2quadwords); + rb->blksizequadwords = gsl_cfg_rb_blksizequadwords; + + // allocate memory for ringbuffer, needs to be double octword aligned + // align on page from contiguous physical memory + flags = (GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST); + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = (GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_STRICTREQUEST)); /* set MMU table for ringbuffer */ + + status = kgsl_sharedmem_alloc0(device->id, flags, (rb->sizedwords << 2), &rb->buffer_desc); + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RINGBUF_SET, (unsigned int)rb->buffer_desc.gpuaddr, (unsigned int)rb->buffer_desc.hostptr, 0, "kgsl_ringbuffer_init")); + + if (status != GSL_SUCCESS) + { + kgsl_ringbuffer_close(rb); + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status ); + return (status); + } + + // allocate memory for polling and timestamps + flags = (GSL_MEMFLAGS_ALIGN32 | GSL_MEMFLAGS_CONPHYS); + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = GSL_MEMFLAGS_ALIGN32); + + status = kgsl_sharedmem_alloc0(device->id, flags, sizeof(gsl_rbmemptrs_t), &rb->memptrs_desc); + + if (status != GSL_SUCCESS) + { + kgsl_ringbuffer_close(rb); + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status ); + return (status); + } + + // overlay structure on memptrs memory + rb->memptrs = (gsl_rbmemptrs_t *)rb->memptrs_desc.hostptr; + + rb->flags |= GSL_FLAGS_INITIALIZED; + + // validate command stream data when running in safe mode + if (device->flags & GSL_FLAGS_SAFEMODE) + { + gsl_driver.flags_debug |= GSL_DBGFLAGS_PM4CHECK; + } + + // start ringbuffer + status = kgsl_ringbuffer_start(rb); + + if (status != GSL_SUCCESS) + { + kgsl_ringbuffer_close(rb); + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status ); + return (status); + } + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_ringbuffer_close(gsl_ringbuffer_t *rb) +{ + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_ringbuffer_close(gsl_ringbuffer_t *rb=0x%08x)\n", rb ); + + // stop ringbuffer + kgsl_ringbuffer_stop(rb); + + // free buffer + if (rb->buffer_desc.hostptr) + { + kgsl_sharedmem_free0(&rb->buffer_desc, GSL_CALLER_PROCESSID_GET()); + } + + // free memory pointers + if (rb->memptrs_desc.hostptr) + { + kgsl_sharedmem_free0(&rb->memptrs_desc, GSL_CALLER_PROCESSID_GET()); + } + + rb->flags &= ~GSL_FLAGS_INITIALIZED; + + kos_memset(rb, 0, sizeof(gsl_ringbuffer_t)); + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_close. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +gsl_timestamp_t +kgsl_ringbuffer_issuecmds(gsl_device_t *device, int pmodeoff, unsigned int *cmds, int sizedwords, unsigned int pid) +{ + gsl_ringbuffer_t *rb = &device->ringbuffer; + unsigned int pmodesizedwords; + unsigned int *ringcmds; + unsigned int timestamp; + + pmodeoff = 0; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> gsl_timestamp_t kgsl_ringbuffer_issuecmds(gsl_device_t *device=0x%08x, int pmodeoff=%d, unsigned int *cmds=0x%08x, int sizedwords=%d, unsigned int pid=0x%08x)\n", + device, pmodeoff, cmds, sizedwords, pid ); + + if (!(device->ringbuffer.flags & GSL_FLAGS_STARTED)) + { + return (0); + } + + // set mmu pagetable + kgsl_mmu_setpagetable(device, pid); + + KGSL_DEBUG(GSL_DBGFLAGS_PM4CHECK, kgsl_ringbuffer_checkpm4(cmds, sizedwords, pmodeoff)); + KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPPM4(cmds, sizedwords)); + + // reserve space to temporarily turn off protected mode error checking if needed + pmodesizedwords = pmodeoff ? 8 : 0; + +#if defined GSL_RB_TIMESTAMP_INTERUPT + pmodesizedwords += 2; +#endif + // allocate space in ringbuffer + ringcmds = kgsl_ringbuffer_addcmds(rb, pmodesizedwords + sizedwords + 6); + + if (pmodeoff) + { + // disable protected mode error checking + *ringcmds++ = pm4_type3_packet(PM4_ME_INIT, 2); + *ringcmds++ = 0x00000080; + *ringcmds++ = 0x00000000; + } + + // copy the cmds to the ringbuffer + kos_memcpy(ringcmds, cmds, (sizedwords << 2)); + + ringcmds += sizedwords; + + if (pmodeoff) + { + *ringcmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *ringcmds++ = 0; + + // re-enable protected mode error checking + *ringcmds++ = pm4_type3_packet(PM4_ME_INIT, 2); + *ringcmds++ = 0x00000080; + *ringcmds++ = GSL_RB_PROTECTED_MODE_CONTROL; + } + + // increment timestamp + rb->timestamp++; + timestamp = rb->timestamp; + + // start-of-pipeline and end-of-pipeline timestamps + *ringcmds++ = pm4_type0_packet(mmCP_TIMESTAMP, 1); + *ringcmds++ = rb->timestamp; + *ringcmds++ = pm4_type3_packet(PM4_EVENT_WRITE, 3); + *ringcmds++ = CACHE_FLUSH_TS; + *ringcmds++ = device->memstore.gpuaddr + GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp); + *ringcmds++ = rb->timestamp; + +#if defined GSL_RB_TIMESTAMP_INTERUPT + *ringcmds++ = pm4_type3_packet(PM4_INTERRUPT, 1); + *ringcmds++ = 0x80000000; +#endif + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, (unsigned int)((char*)ringcmds - ((pmodesizedwords + sizedwords + 6) << 2)), (unsigned int)((char*)ringcmds - ((pmodesizedwords + sizedwords + 6) << 2)), (pmodesizedwords + sizedwords + 6) << 2, "kgsl_ringbuffer_issuecmds")); + + // issue the commands + kgsl_ringbuffer_submit(rb); + + // stats + GSL_RB_STATS(rb->stats.wordstotal += sizedwords); + GSL_RB_STATS(rb->stats.issues++); + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issuecmds. Return value %d\n", timestamp ); + + // return timestamp of issued commands + return (timestamp); +} + +//---------------------------------------------------------------------------- +int +kgsl_ringbuffer_issueibcmds(gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags) +{ + unsigned int link[3]; + int dumpx_swap; + (void)dumpx_swap; // used only when BB_DUMPX is defined + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> gsl_timestamp_t kgsl_ringbuffer_issueibcmds(gsl_device_t device=%0x%08x, int drawctxt_index=%d, gpuaddr_t ibaddr=0x%08x, int sizedwords=%d, gsl_timestamp_t *timestamp=0x%08x)\n", + device, drawctxt_index, ibaddr, sizedwords, timestamp ); + + if (!(device->ringbuffer.flags & GSL_FLAGS_STARTED)) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issueibcmds. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + KOS_ASSERT(ibaddr); + KOS_ASSERT(sizedwords); + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, dumpx_swap = kgsl_dumpx_parse_ibs(ibaddr, sizedwords)); + + // context switch if needed + kgsl_drawctxt_switch(device, &device->drawctxt[drawctxt_index], flags); + + link[0] = PM4_HDR_INDIRECT_BUFFER_PFD; + link[1] = ibaddr; + link[2] = sizedwords; + + *timestamp = kgsl_ringbuffer_issuecmds(device, 0, &link[0], 3, GSL_CALLER_PROCESSID_GET()); + + // idle device when running in safe mode + if (device->flags & GSL_FLAGS_SAFEMODE) + { + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + } + else + { + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + // insert wait for idle after every IB1 + // this is conservative but works reliably and is ok even for performance simulations + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + }); + } + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + if(dumpx_swap) + { + KGSL_DEBUG_DUMPX( BB_DUMP_EXPORT_CBUF, 0, 0, 0, "resolve"); + KGSL_DEBUG_DUMPX( BB_DUMP_FLUSH,0,0,0," "); + } + }); + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issueibcmds. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +#ifdef _DEBUG +static void +kgsl_ringbuffer_debug(gsl_ringbuffer_t *rb, gsl_rb_debug_t *rb_debug) +{ + kos_memset(rb_debug, 0, sizeof(gsl_rb_debug_t)); + + rb_debug->pm4_ucode_rel = PM4_MICROCODE_VERSION; + rb_debug->pfp_ucode_rel = PFP_MICROCODE_VERSION; + + rb->device->ftbl.device_regread(rb->device, mmCP_RB_BASE, (unsigned int *)&rb_debug->cp_rb_base); + rb->device->ftbl.device_regread(rb->device, mmCP_RB_CNTL, (unsigned int *)&rb_debug->cp_rb_cntl); + rb->device->ftbl.device_regread(rb->device, mmCP_RB_RPTR_ADDR, (unsigned int *)&rb_debug->cp_rb_rptr_addr); + rb->device->ftbl.device_regread(rb->device, mmCP_RB_RPTR, (unsigned int *)&rb_debug->cp_rb_rptr); + rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR, (unsigned int *)&rb_debug->cp_rb_wptr); + rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR_BASE, (unsigned int *)&rb_debug->cp_rb_wptr_base); + rb->device->ftbl.device_regread(rb->device, mmSCRATCH_UMSK, (unsigned int *)&rb_debug->scratch_umsk); + rb->device->ftbl.device_regread(rb->device, mmSCRATCH_ADDR, (unsigned int *)&rb_debug->scratch_addr); + rb->device->ftbl.device_regread(rb->device, mmCP_ME_CNTL, (unsigned int *)&rb_debug->cp_me_cntl); + rb->device->ftbl.device_regread(rb->device, mmCP_ME_STATUS, (unsigned int *)&rb_debug->cp_me_status); + rb->device->ftbl.device_regread(rb->device, mmCP_DEBUG, (unsigned int *)&rb_debug->cp_debug); + rb->device->ftbl.device_regread(rb->device, mmCP_STAT, (unsigned int *)&rb_debug->cp_stat); + rb->device->ftbl.device_regread(rb->device, mmRBBM_STATUS, (unsigned int *)&rb_debug->rbbm_status); + rb_debug->sop_timestamp = kgsl_cmdstream_readtimestamp(rb->device->id, GSL_TIMESTAMP_CONSUMED); + rb_debug->eop_timestamp = kgsl_cmdstream_readtimestamp(rb->device->id, GSL_TIMESTAMP_RETIRED); +} +#endif + + +//---------------------------------------------------------------------------- + +int +kgsl_ringbuffer_querystats(gsl_ringbuffer_t *rb, gsl_rbstats_t *stats) +{ +#ifdef GSL_STATS_RINGBUFFER + KOS_ASSERT(stats); + + if (!(rb->flags & GSL_FLAGS_STARTED)) + { + return (GSL_FAILURE); + } + + kos_memcpy(stats, &rb->stats, sizeof(gsl_rbstats_t)); + + return (GSL_SUCCESS); +#else + // unreferenced formal parameters + (void) rb; + (void) stats; + + return (GSL_FAILURE_NOTSUPPORTED); +#endif // GSL_STATS_RINGBUFFER +} + +//---------------------------------------------------------------------------- + +int +kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb) +{ + unsigned int *cmds; + unsigned int temp, k, j; + int status; + int i; +#ifdef _DEBUG + gsl_rb_debug_t rb_debug; +#endif + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb=0x%08x)\n", rb ); + + if (!(rb->flags & GSL_FLAGS_STARTED)) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // simple nop submit + cmds = kgsl_ringbuffer_addcmds(rb, 2); + if (!cmds) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + GSL_RB_WRITE(cmds, pm4_nop_packet(1)); + GSL_RB_WRITE(cmds, 0xDEADBEEF); + + kgsl_ringbuffer_submit(rb); + + status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT); + + if (status != GSL_SUCCESS) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status ); + return (status); + } + + // simple scratch submit + cmds = kgsl_ringbuffer_addcmds(rb, 2); + if (!cmds) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + GSL_RB_WRITE(cmds, pm4_type0_packet(mmSCRATCH_REG7, 1)); + GSL_RB_WRITE(cmds, 0xFEEDF00D); + + kgsl_ringbuffer_submit(rb); + + status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT); + + if (status != GSL_SUCCESS) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status ); + return (status); + } + + rb->device->ftbl.device_regread(rb->device, mmSCRATCH_REG7, &temp); + + if (temp != 0xFEEDF00D) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // simple wraps + for (i = 0; i < 256; i+=2) + { + j = ((rb->sizedwords >> 2) - 256) + i; + + cmds = kgsl_ringbuffer_addcmds(rb, j); + if (!cmds) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + k = 0; + + while (k < j) + { + k+=2; + GSL_RB_WRITE(cmds, pm4_type0_packet(mmSCRATCH_REG7, 1)); + GSL_RB_WRITE(cmds, k); + } + + kgsl_ringbuffer_submit(rb); + + status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT); + + if (status != GSL_SUCCESS) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status ); + return (status); + } + + rb->device->ftbl.device_regread(rb->device, mmSCRATCH_REG7, &temp); + + if (temp != k) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + } + + // max size submits, TODO do this at least with regreads + for (i = 0; i < 256; i++) + { + cmds = kgsl_ringbuffer_addcmds(rb, (rb->sizedwords >> 2)); + if (!cmds) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + GSL_RB_WRITE(cmds, pm4_nop_packet((rb->sizedwords >> 2) - 1)); + + kgsl_ringbuffer_submit(rb); + + status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT); + + if (status != GSL_SUCCESS) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status ); + return (status); + } + } + + // submit load with randomness + +#ifdef GSL_RB_USE_MEM_TIMESTAMP + // scratch memptr validate +#endif // GSL_RB_USE_MEM_TIMESTAMP + +#ifdef GSL_RB_USE_MEM_RPTR + // rptr memptr validate +#endif // GSL_RB_USE_MEM_RPTR + +#ifdef GSL_RB_USE_WPTR_POLLING + // wptr memptr validate +#endif // GSL_RB_USE_WPTR_POLLING + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +#endif + diff --git a/drivers/mxc/amd-gpu/common/gsl_sharedmem.c b/drivers/mxc/amd-gpu/common/gsl_sharedmem.c new file mode 100644 index 000000000000..51e66f97c52e --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_sharedmem.c @@ -0,0 +1,937 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + +///////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define GSL_SHMEM_APERTURE_MARK(aperture_id) \ + (shmem->priv |= (((aperture_id + 1) << GSL_APERTURE_SHIFT) & GSL_APERTURE_MASK)) + +#define GSL_SHMEM_APERTURE_ISMARKED(aperture_id) \ + (((shmem->priv & GSL_APERTURE_MASK) >> GSL_APERTURE_SHIFT) & (aperture_id + 1)) + +#define GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id) \ + aperture_id = (gsl_apertureid_t)((flags & GSL_MEMFLAGS_APERTURE_MASK) >> GSL_MEMFLAGS_APERTURE_SHIFT); \ + KOS_ASSERT(aperture_id < GSL_APERTURE_MAX); + +#define GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id) \ + channel_id = (gsl_channelid_t)((flags & GSL_MEMFLAGS_CHANNEL_MASK) >> GSL_MEMFLAGS_CHANNEL_SHIFT); \ + KOS_ASSERT(channel_id < GSL_CHANNEL_MAX); + +#define GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index) \ + memdesc->priv = (memdesc->priv & ~GSL_APERTURE_MASK) | ((aperture_index << GSL_APERTURE_SHIFT) & GSL_APERTURE_MASK); + +#define GSL_MEMDESC_DEVICE_SET(memdesc, device_id) \ + memdesc->priv = (memdesc->priv & ~GSL_DEVICEID_MASK) | ((device_id << GSL_DEVICEID_SHIFT) & GSL_DEVICEID_MASK); + +#define GSL_MEMDESC_EXTALLOC_SET(memdesc, flag) \ + memdesc->priv = (memdesc->priv & ~GSL_EXTALLOC_MASK) | ((flag << GSL_EXTALLOC_SHIFT) & GSL_EXTALLOC_MASK); + +#define GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index) \ + KOS_ASSERT(memdesc); \ + aperture_index = ((memdesc->priv & GSL_APERTURE_MASK) >> GSL_APERTURE_SHIFT); \ + KOS_ASSERT(aperture_index < GSL_SHMEM_MAX_APERTURES); + +#define GSL_MEMDESC_DEVICE_GET(memdesc, device_id) \ + KOS_ASSERT(memdesc); \ + device_id = (gsl_deviceid_t)((memdesc->priv & GSL_DEVICEID_MASK) >> GSL_DEVICEID_SHIFT); \ + KOS_ASSERT(device_id <= GSL_DEVICE_MAX); + +#define GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc) \ + ((memdesc->priv & GSL_EXTALLOC_MASK) >> GSL_EXTALLOC_SHIFT) + + +////////////////////////////////////////////////////////////////////////////// +// aperture index in shared memory object +////////////////////////////////////////////////////////////////////////////// +OSINLINE int +kgsl_sharedmem_getapertureindex(gsl_sharedmem_t *shmem, gsl_apertureid_t aperture_id, gsl_channelid_t channel_id) +{ + KOS_ASSERT(shmem->aperturelookup[aperture_id][channel_id] < shmem->numapertures); + + return (shmem->aperturelookup[aperture_id][channel_id]); +} + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_sharedmem_init(gsl_sharedmem_t *shmem) +{ + int i; + int status; + gsl_shmemconfig_t config; + int mmu_virtualized; + gsl_apertureid_t aperture_id; + gsl_channelid_t channel_id; + unsigned int hostbaseaddr; + gpuaddr_t gpubaseaddr; + int sizebytes; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_init(gsl_sharedmem_t *shmem=0x%08x)\n", shmem ); + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + status = kgsl_hal_getshmemconfig(&config); + if (status != GSL_SUCCESS) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to get sharedmem config.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", status ); + return (status); + } + + shmem->numapertures = config.numapertures; + + for (i = 0; i < shmem->numapertures; i++) + { + aperture_id = config.apertures[i].id; + channel_id = config.apertures[i].channel; + hostbaseaddr = config.apertures[i].hostbase; + gpubaseaddr = config.apertures[i].gpubase; + sizebytes = config.apertures[i].sizebytes; + mmu_virtualized = 0; + + // handle mmu virtualized aperture + if (aperture_id == GSL_APERTURE_MMU) + { + mmu_virtualized = 1; + aperture_id = GSL_APERTURE_EMEM; + } + + // make sure aligned to page size + KOS_ASSERT((gpubaseaddr & ((1 << GSL_PAGESIZE_SHIFT) - 1)) == 0); + + // make a multiple of page size + sizebytes = (sizebytes & ~((1 << GSL_PAGESIZE_SHIFT) - 1)); + + if (sizebytes > 0) + { + shmem->apertures[i].memarena = kgsl_memarena_create(aperture_id, mmu_virtualized, hostbaseaddr, gpubaseaddr, sizebytes); + + if (!shmem->apertures[i].memarena) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate memarena.\n" ); + kgsl_sharedmem_close(shmem); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + shmem->apertures[i].id = aperture_id; + shmem->apertures[i].channel = channel_id; + shmem->apertures[i].numbanks = 1; + + // create aperture lookup table + if (GSL_SHMEM_APERTURE_ISMARKED(aperture_id)) + { + // update "current aperture_id"/"current channel_id" index + shmem->aperturelookup[aperture_id][channel_id] = i; + } + else + { + // initialize "current aperture_id"/"channel_id" indexes + for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++) + { + shmem->aperturelookup[aperture_id][channel_id] = i; + } + + GSL_SHMEM_APERTURE_MARK(aperture_id); + } + } + } + + shmem->flags |= GSL_FLAGS_INITIALIZED; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_close(gsl_sharedmem_t *shmem) +{ + int i; + int result = GSL_SUCCESS; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_close(gsl_sharedmem_t *shmem=0x%08x)\n", shmem ); + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + for (i = 0; i < shmem->numapertures; i++) + { + if (shmem->apertures[i].memarena) + { + result = kgsl_memarena_destroy(shmem->apertures[i].memarena); + } + } + + kos_memset(shmem, 0, sizeof(gsl_sharedmem_t)); + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_close. Return value %B\n", result ); + + return (result); +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_alloc0(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc) +{ + gsl_apertureid_t aperture_id; + gsl_channelid_t channel_id; + gsl_deviceid_t tmp_id; + int aperture_index, org_index; + int result = GSL_FAILURE; + gsl_mmu_t *mmu = NULL; + gsl_sharedmem_t *shmem = &gsl_driver.shmem; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_alloc(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x, int sizebytes=%d, gsl_memdesc_t *memdesc=%M)\n", + device_id, flags, sizebytes, memdesc ); + + KOS_ASSERT(sizebytes); + KOS_ASSERT(memdesc); + + GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id); + GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id); + + kos_memset(memdesc, 0, sizeof(gsl_memdesc_t)); + + if (!(shmem->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // execute pending device action + tmp_id = (device_id != GSL_DEVICE_ANY) ? device_id : device_id+1; + for ( ; tmp_id <= GSL_DEVICE_MAX; tmp_id++) + { + if (gsl_driver.device[tmp_id-1].flags & GSL_FLAGS_INITIALIZED) + { + kgsl_device_runpending(&gsl_driver.device[tmp_id-1]); + + if (tmp_id == device_id) + { + break; + } + } + } + + // convert any device to an actual existing device + if (device_id == GSL_DEVICE_ANY) + { + for ( ; ; ) + { + device_id++; + + if (device_id <= GSL_DEVICE_MAX) + { + if (gsl_driver.device[device_id-1].flags & GSL_FLAGS_INITIALIZED) + { + break; + } + } + else + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + } + } + + KOS_ASSERT(device_id > GSL_DEVICE_ANY && device_id <= GSL_DEVICE_MAX); + + // get mmu reference + mmu = &gsl_driver.device[device_id-1].mmu; + + aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id); + + //do not proceed if it is a strict request, the aperture requested is not present, and the MMU is enabled + if (!((flags & GSL_MEMFLAGS_STRICTREQUEST) && aperture_id != shmem->apertures[aperture_index].id && kgsl_mmu_isenabled(mmu))) + { + // do allocation + result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc); + + // if allocation failed + if (result != GSL_SUCCESS) + { + org_index = aperture_index; + + // then failover to other channels within the current aperture + for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++) + { + aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id); + + if (aperture_index != org_index) + { + // do allocation + result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc); + + if (result == GSL_SUCCESS) + { + break; + } + } + } + + // if allocation still has not succeeded, then failover to EMEM/MMU aperture, but + // not if it's a strict request and the MMU is enabled + if (result != GSL_SUCCESS && aperture_id != GSL_APERTURE_EMEM + && !((flags & GSL_MEMFLAGS_STRICTREQUEST) && kgsl_mmu_isenabled(mmu))) + { + aperture_id = GSL_APERTURE_EMEM; + + // try every channel + for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++) + { + aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id); + + if (aperture_index != org_index) + { + // do allocation + result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc); + + if (result == GSL_SUCCESS) + { + break; + } + } + } + } + } + } + + if (result == GSL_SUCCESS) + { + GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index); + GSL_MEMDESC_DEVICE_SET(memdesc, device_id); + + if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena)) + { + gsl_scatterlist_t scatterlist; + + scatterlist.contiguous = 0; + scatterlist.num = memdesc->size / GSL_PAGESIZE; + + if (memdesc->size & (GSL_PAGESIZE-1)) + { + scatterlist.num++; + } + + scatterlist.pages = kos_malloc(sizeof(unsigned int) * scatterlist.num); + if (scatterlist.pages) + { + // allocate physical pages + result = kgsl_hal_allocphysical(memdesc->gpuaddr, scatterlist.num, scatterlist.pages); + if (result == GSL_SUCCESS) + { + result = kgsl_mmu_map(mmu, memdesc->gpuaddr, &scatterlist, flags, GSL_CALLER_PROCESSID_GET()); + if (result != GSL_SUCCESS) + { + kgsl_hal_freephysical(memdesc->gpuaddr, scatterlist.num, scatterlist.pages); + } + } + + kos_free(scatterlist.pages); + } + else + { + result = GSL_FAILURE; + } + + if (result != GSL_SUCCESS) + { + kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc); + } + } + } + + KGSL_DEBUG_TBDUMP_SETMEM( memdesc->gpuaddr, 0, memdesc->size ); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", result ); + + return (result); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_alloc(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_sharedmem_alloc0(device_id, flags, sizebytes, memdesc); + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_free0(gsl_memdesc_t *memdesc, unsigned int pid) +{ + int status = GSL_SUCCESS; + int aperture_index; + gsl_deviceid_t device_id; + gsl_sharedmem_t *shmem; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_free(gsl_memdesc_t *memdesc=%M)\n", memdesc ); + + GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index); + GSL_MEMDESC_DEVICE_GET(memdesc, device_id); + + shmem = &gsl_driver.shmem; + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena)) + { + status |= kgsl_mmu_unmap(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, memdesc->size, pid); + + if (!GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc)) + { + status |= kgsl_hal_freephysical(memdesc->gpuaddr, memdesc->size / GSL_PAGESIZE, NULL); + } + } + + kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc); + + // clear descriptor + kos_memset(memdesc, 0, sizeof(gsl_memdesc_t)); + } + else + { + status = GSL_FAILURE; + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_free. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_free(gsl_memdesc_t *memdesc) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_sharedmem_free0(memdesc, GSL_CALLER_PROCESSID_GET()); + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_read0(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace) +{ + int aperture_index; + gsl_sharedmem_t *shmem; + unsigned int gpuoffsetbytes; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_read(gsl_memdesc_t *memdesc=%M, void *dst=0x%08x, unsigned int offsetbytes=%d, unsigned int sizebytes=%d)\n", + memdesc, dst, offsetbytes, sizebytes ); + + GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index); + + if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_FAILURE_BADPARAM ); + return (GSL_FAILURE_BADPARAM); + } + + shmem = &gsl_driver.shmem; + + if (!(shmem->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + KOS_ASSERT(dst); + KOS_ASSERT(sizebytes); + + if (memdesc->gpuaddr < shmem->apertures[aperture_index].memarena->gpubaseaddr) + { + return (GSL_FAILURE_BADPARAM); + } + + if (memdesc->gpuaddr + sizebytes > shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes) + { + return (GSL_FAILURE_BADPARAM); + } + + gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes; + + GSL_HAL_MEM_READ(dst, shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, sizebytes, touserspace); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_sharedmem_read0(memdesc, dst, offsetbytes, sizebytes, touserspace); + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_write0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace) +{ + int aperture_index; + gsl_sharedmem_t *shmem; + unsigned int gpuoffsetbytes; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_write(gsl_memdesc_t *memdesc=%M, unsigned int offsetbytes=%d, void *src=0x%08x, unsigned int sizebytes=%d)\n", + memdesc, offsetbytes, src, sizebytes ); + + GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index); + + if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_FAILURE_BADPARAM ); + return (GSL_FAILURE_BADPARAM); + } + + shmem = &gsl_driver.shmem; + + if (!(shmem->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + KOS_ASSERT(src); + KOS_ASSERT(sizebytes); + KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr); + KOS_ASSERT((memdesc->gpuaddr + sizebytes) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes)); + + gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes; + + GSL_HAL_MEM_WRITE(shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, src, sizebytes, fromuserspace); + + KGSL_DEBUG(GSL_DBGFLAGS_PM4MEM, KGSL_DEBUG_DUMPMEMWRITE((memdesc->gpuaddr + offsetbytes), sizebytes, src)); + + KGSL_DEBUG_TBDUMP_SYNCMEM( (memdesc->gpuaddr + offsetbytes), src, sizebytes ); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_write(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_sharedmem_write0(memdesc, offsetbytes, src, sizebytes, fromuserspace); + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_set0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes) +{ + int aperture_index; + gsl_sharedmem_t *shmem; + unsigned int gpuoffsetbytes; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_set(gsl_memdesc_t *memdesc=%M, unsigned int offsetbytes=%d, unsigned int value=0x%08x, unsigned int sizebytes=%d)\n", + memdesc, offsetbytes, value, sizebytes ); + + GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index); + + if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_FAILURE_BADPARAM ); + return (GSL_FAILURE_BADPARAM); + } + + shmem = &gsl_driver.shmem; + + if (!(shmem->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + KOS_ASSERT(sizebytes); + KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr); + KOS_ASSERT((memdesc->gpuaddr + sizebytes) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes)); + + gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes; + + GSL_HAL_MEM_SET(shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, value, sizebytes); + + KGSL_DEBUG(GSL_DBGFLAGS_PM4MEM, KGSL_DEBUG_DUMPMEMSET((memdesc->gpuaddr + offsetbytes), sizebytes, value)); + + KGSL_DEBUG_TBDUMP_SETMEM( (memdesc->gpuaddr + offsetbytes), value, sizebytes ); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_sharedmem_set0(memdesc, offsetbytes, value, sizebytes); + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +KGSL_API unsigned int +kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags) +{ + gsl_apertureid_t aperture_id; + gsl_channelid_t channel_id; + int aperture_index; + unsigned int result = 0; + gsl_sharedmem_t *shmem; + + // device_id is ignored at this level, it would be used with per-device memarena's + + // unreferenced formal parameter + (void) device_id; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x)\n", + device_id, flags ); + + GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id); + GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id); + + GSL_API_MUTEX_LOCK(); + + shmem = &gsl_driver.shmem; + + if (!(shmem->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" ); + GSL_API_MUTEX_UNLOCK(); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_largestfreeblock. Return value %d\n", 0 ); + return (0); + } + + aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id); + + if (aperture_id == shmem->apertures[aperture_index].id) + { + result = kgsl_memarena_getlargestfreeblock(shmem->apertures[aperture_index].memarena, flags); + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_largestfreeblock. Return value %d\n", result ); + + return (result); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_map(gsl_deviceid_t device_id, gsl_flags_t flags, const gsl_scatterlist_t *scatterlist, gsl_memdesc_t *memdesc) +{ + int status = GSL_FAILURE; + gsl_sharedmem_t *shmem = &gsl_driver.shmem; + int aperture_index; + gsl_deviceid_t tmp_id; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_map(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x, gsl_scatterlist_t scatterlist=%M, gsl_memdesc_t *memdesc=%M)\n", + device_id, flags, memdesc, scatterlist ); + + // execute pending device action + tmp_id = (device_id != GSL_DEVICE_ANY) ? device_id : device_id+1; + for ( ; tmp_id <= GSL_DEVICE_MAX; tmp_id++) + { + if (gsl_driver.device[tmp_id-1].flags & GSL_FLAGS_INITIALIZED) + { + kgsl_device_runpending(&gsl_driver.device[tmp_id-1]); + + if (tmp_id == device_id) + { + break; + } + } + } + + // convert any device to an actual existing device + if (device_id == GSL_DEVICE_ANY) + { + for ( ; ; ) + { + device_id++; + + if (device_id <= GSL_DEVICE_MAX) + { + if (gsl_driver.device[device_id-1].flags & GSL_FLAGS_INITIALIZED) + { + break; + } + } + else + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_map. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + } + } + + KOS_ASSERT(device_id > GSL_DEVICE_ANY && device_id <= GSL_DEVICE_MAX); + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + aperture_index = kgsl_sharedmem_getapertureindex(shmem, GSL_APERTURE_EMEM, GSL_CHANNEL_1); + + if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena)) + { + KOS_ASSERT(scatterlist->num); + KOS_ASSERT(scatterlist->pages); + + status = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, scatterlist->num *GSL_PAGESIZE, memdesc); + if (status == GSL_SUCCESS) + { + GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index); + GSL_MEMDESC_DEVICE_SET(memdesc, device_id); + + // mark descriptor's memory as externally allocated -- i.e. outside GSL + GSL_MEMDESC_EXTALLOC_SET(memdesc, 1); + + status = kgsl_mmu_map(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, scatterlist, flags, GSL_CALLER_PROCESSID_GET()); + if (status != GSL_SUCCESS) + { + kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc); + } + } + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_map. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_unmap(gsl_memdesc_t *memdesc) +{ + return (kgsl_sharedmem_free0(memdesc, GSL_CALLER_PROCESSID_GET())); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_getmap(const gsl_memdesc_t *memdesc, gsl_scatterlist_t *scatterlist) +{ + int status = GSL_SUCCESS; + int aperture_index; + gsl_deviceid_t device_id; + gsl_sharedmem_t *shmem; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_getmap(gsl_memdesc_t *memdesc=%M, gsl_scatterlist_t scatterlist=%M)\n", + memdesc, scatterlist ); + + GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index); + GSL_MEMDESC_DEVICE_GET(memdesc, device_id); + + shmem = &gsl_driver.shmem; + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + KOS_ASSERT(scatterlist->num); + KOS_ASSERT(scatterlist->pages); + KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr); + KOS_ASSERT((memdesc->gpuaddr + memdesc->size) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes)); + + kos_memset(scatterlist->pages, 0, sizeof(unsigned int) * scatterlist->num); + + if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena)) + { + status = kgsl_mmu_getmap(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, memdesc->size, scatterlist, GSL_CALLER_PROCESSID_GET()); + } + else + { + // coalesce physically contiguous pages into a single scatter list entry + scatterlist->pages[0] = memdesc->gpuaddr; + scatterlist->contiguous = 1; + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_getmap. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_querystats(gsl_sharedmem_t *shmem, gsl_sharedmem_stats_t *stats) +{ +#ifdef GSL_STATS_MEM + int status = GSL_SUCCESS; + int i; + + KOS_ASSERT(stats); + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + for (i = 0; i < shmem->numapertures; i++) + { + if (shmem->apertures[i].memarena) + { + stats->apertures[i].id = shmem->apertures[i].id; + stats->apertures[i].channel = shmem->apertures[i].channel; + + status |= kgsl_memarena_querystats(shmem->apertures[i].memarena, &stats->apertures[i].memarena); + } + } + } + else + { + kos_memset(stats, 0, sizeof(gsl_sharedmem_stats_t)); + } + + return (status); +#else + // unreferenced formal parameters + (void) shmem; + (void) stats; + + return (GSL_FAILURE_NOTSUPPORTED); +#endif // GSL_STATS_MEM +} + +//---------------------------------------------------------------------------- + +unsigned int +kgsl_sharedmem_convertaddr(unsigned int addr, int type) +{ + gsl_sharedmem_t *shmem = &gsl_driver.shmem; + unsigned int cvtaddr = 0; + unsigned int gpubaseaddr, hostbaseaddr, sizebytes; + int i; + + if ((shmem->flags & GSL_FLAGS_INITIALIZED)) + { + for (i = 0; i < shmem->numapertures; i++) + { + hostbaseaddr = shmem->apertures[i].memarena->hostbaseaddr; + gpubaseaddr = shmem->apertures[i].memarena->gpubaseaddr; + sizebytes = shmem->apertures[i].memarena->sizebytes; + + // convert from gpu to host + if (type == 0) + { + if (addr >= gpubaseaddr && addr < (gpubaseaddr + sizebytes)) + { + cvtaddr = hostbaseaddr + (addr - gpubaseaddr); + break; + } + } + // convert from host to gpu + else if (type == 1) + { + if (addr >= hostbaseaddr && addr < (hostbaseaddr + sizebytes)) + { + cvtaddr = gpubaseaddr + (addr - hostbaseaddr); + break; + } + } + } + } + + return (cvtaddr); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation) +{ + int status = GSL_FAILURE; + + /* unreferenced formal parameter */ + (void)memdesc; + (void)offsetbytes; + (void)sizebytes; + (void)operation; + + /* do cache operation */ + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr) +{ + int status = GSL_FAILURE; + + memdesc->gpuaddr = (gpuaddr_t)hostptr; /* map physical address with hostptr */ + memdesc->hostptr = hostptr; /* set virtual address also in memdesc */ + + /* unreferenced formal parameter */ + (void)device_id; + + return (status); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_tbdump.c b/drivers/mxc/amd-gpu/common/gsl_tbdump.c new file mode 100644 index 000000000000..e22cf894f7b2 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_tbdump.c @@ -0,0 +1,228 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#ifdef WIN32 +#include +#endif +#include "gsl.h" +#include "gsl_tbdump.h" +#include "kos_libapi.h" + +#ifdef TBDUMP + +typedef struct TBDump_ +{ + void* file; +} TBDump; + + +static TBDump g_tb; +static oshandle_t tbdump_mutex = 0; +#define TBDUMP_MUTEX_LOCK() if( tbdump_mutex ) kos_mutex_lock( tbdump_mutex ) +#define TBDUMP_MUTEX_UNLOCK() if( tbdump_mutex ) kos_mutex_unlock( tbdump_mutex ) + +/* ------------------------------------------------------------------------ */ +/* ------------------------------------------------------------------------ */ +/* ------------------------------------------------------------------------ */ + +static void tbdump_printline(const char* format, ...) +{ + if(g_tb.file) + { + va_list va; + va_start(va, format); + vfprintf((FILE*)g_tb.file, format, va); + va_end(va); + fprintf((FILE*)g_tb.file, "\n"); + } +} + +static void tbdump_printinfo(const char* message ) +{ + tbdump_printline("15 %s", message); +} + +static void tbdump_getmemhex(char* buffer, unsigned int addr, unsigned int sizewords) +{ + unsigned int i = 0; + static const char* hexChars = "0123456789abcdef"; + unsigned char* ptr = (unsigned char*)addr; + + for (i = 0; i < sizewords; i++) + { + buffer[(sizewords - i) * 2 - 1] = hexChars[ptr[i] & 0x0f]; + buffer[(sizewords - i) * 2 - 2] = hexChars[ptr[i] >> 4]; + } + buffer[sizewords * 2] = '\0'; +} + +/* ------------------------------------------------------------------------ */ + +void tbdump_open(char* filename) +{ + if( !tbdump_mutex ) tbdump_mutex = kos_mutex_create( "TBDUMP_MUTEX" ); + + kos_memset( &g_tb, 0, sizeof( g_tb ) ); + + g_tb.file = kos_fopen( filename, "wt" ); + + tbdump_printinfo("reset"); + tbdump_printline("0"); + tbdump_printline("1 00000000 00000eff"); + + /* Enable interrupts */ + tbdump_printline("1 00000000 00000003"); +} + +void tbdump_close() +{ + TBDUMP_MUTEX_LOCK(); + + kos_fclose( g_tb.file ); + g_tb.file = 0; + + TBDUMP_MUTEX_UNLOCK(); + + if( tbdump_mutex ) kos_mutex_free( tbdump_mutex ); +} + +/* ------------------------------------------------------------------------ */ + +void tbdump_syncmem(unsigned int addr, unsigned int src, unsigned int sizebytes) +{ + /* Align starting address and size */ + unsigned int beg = addr; + unsigned int end = addr+sizebytes; + char buffer[65]; + + TBDUMP_MUTEX_LOCK(); + + beg = (beg+15) & ~15; + end &= ~15; + + if( sizebytes <= 16 ) + { + tbdump_getmemhex(buffer, src, 16); + + tbdump_printline("19 %08x %i 1 %s", addr, sizebytes, buffer); + + TBDUMP_MUTEX_UNLOCK(); + return; + } + + /* Handle unaligned start */ + if( beg != addr ) + { + tbdump_getmemhex(buffer, src, 16); + + tbdump_printline("19 %08x %i 1 %s", addr, beg-addr, buffer); + + src += beg-addr; + } + + /* Dump the memory writes */ + while( beg < end ) + { + tbdump_getmemhex(buffer, src, 16); + + tbdump_printline("2 %08x %s", beg, buffer); + + beg += 16; + src += 16; + } + + /* Handle unaligned end */ + if( end != addr+sizebytes ) + { + tbdump_getmemhex(buffer, src, 16); + + tbdump_printline("19 %08x %i 1 %s", end, (addr+sizebytes)-end, buffer); + } + + TBDUMP_MUTEX_UNLOCK(); +} + +/* ------------------------------------------------------------------------ */ + +void tbdump_setmem(unsigned int addr, unsigned int value, unsigned int sizebytes) +{ + TBDUMP_MUTEX_LOCK(); + + tbdump_printline("19 %08x 4 %i %032x", addr, (sizebytes+3)/4, value ); + + TBDUMP_MUTEX_UNLOCK(); +} + +/* ------------------------------------------------------------------------ */ + +void tbdump_slavewrite(unsigned int addr, unsigned int value) +{ + TBDUMP_MUTEX_LOCK(); + + tbdump_printline("1 %08x %08x", addr, value); + + TBDUMP_MUTEX_UNLOCK(); +} + +/* ------------------------------------------------------------------------ */ + + +KGSL_API int +kgsl_tbdump_waitirq() +{ + if(!g_tb.file) return GSL_FAILURE; + + TBDUMP_MUTEX_LOCK(); + + tbdump_printinfo("wait irq"); + tbdump_printline("10"); + + /* ACK IRQ */ + tbdump_printline("1 00000418 00000003"); + tbdump_printline("18 00000018 00000000 # slave read & assert"); + + TBDUMP_MUTEX_UNLOCK(); + + return GSL_SUCCESS; +} + +/* ------------------------------------------------------------------------ */ + +KGSL_API int +kgsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height) +{ + static char filename[20]; + static int numframe = 0; + + if(!g_tb.file) return GSL_FAILURE; + + TBDUMP_MUTEX_LOCK(); + #pragma warning(disable:4996) + sprintf( filename, "tbdump_%08d.bmp", numframe++ ); + + tbdump_printline("13 %s %d %08x %d %d %d 0", filename, format, (unsigned int)addr, stride, width, height); + + TBDUMP_MUTEX_UNLOCK(); + + return GSL_SUCCESS; +} + +/* ------------------------------------------------------------------------ */ + +#endif /* TBDUMP */ diff --git a/drivers/mxc/amd-gpu/common/gsl_yamato.c b/drivers/mxc/amd-gpu/common/gsl_yamato.c new file mode 100644 index 000000000000..e52d4274c6a6 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_yamato.c @@ -0,0 +1,887 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#ifdef _LINUX +#include +#endif + +#ifdef GSL_BLD_YAMATO + +#include "gsl_ringbuffer.h" +#include "gsl_drawctxt.h" + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +static int +kgsl_yamato_gmeminit(gsl_device_t *device) +{ + rb_edram_info_u rb_edram_info = {0}; + unsigned int gmem_size; + unsigned int edram_value = 0; + + // make sure edram range is aligned to size + KOS_ASSERT((device->gmemspace.gpu_base & (device->gmemspace.sizebytes - 1)) == 0); + + // get edram_size value equivalent + gmem_size = (device->gmemspace.sizebytes >> 14); + while (gmem_size >>= 1) + { + edram_value++; + } + + rb_edram_info.f.edram_size = edram_value; + rb_edram_info.f.edram_mapping_mode = 0; // EDRAM_MAP_UPPER + rb_edram_info.f.edram_range = (device->gmemspace.gpu_base >> 14); // must be aligned to size + + device->ftbl.device_regwrite(device, mmRB_EDRAM_INFO, (unsigned int)rb_edram_info.val); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +static int +kgsl_yamato_gmemclose(gsl_device_t *device) +{ + device->ftbl.device_regwrite(device, mmRB_EDRAM_INFO, 0x00000000); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +void +kgsl_yamato_rbbmintrcallback(gsl_intrid_t id, void *cookie) +{ + gsl_device_t *device = (gsl_device_t *) cookie; + + switch(id) + { + // error condition interrupt + case GSL_INTR_YDX_RBBM_READ_ERROR: + + device->ftbl.device_destroy(device); + break; + + // non-error condition interrupt + case GSL_INTR_YDX_RBBM_DISPLAY_UPDATE: + case GSL_INTR_YDX_RBBM_GUI_IDLE: + + kos_event_signal(device->intr.evnt[id]); + break; + + default: + + break; + } +} + +//---------------------------------------------------------------------------- + +void +kgsl_yamato_cpintrcallback(gsl_intrid_t id, void *cookie) +{ + gsl_device_t *device = (gsl_device_t *) cookie; + + switch(id) + { + case GSL_INTR_YDX_CP_RING_BUFFER: +#ifndef _LINUX + kos_event_signal(device->timestamp_event); +#else + wake_up_interruptible_all(&(device->timestamp_waitq)); +#endif + break; + default: + break; + } +} +//---------------------------------------------------------------------------- + +void +kgsl_yamato_sqintrcallback(gsl_intrid_t id, void *cookie) +{ + (void) cookie; // unreferenced formal parameter + /*gsl_device_t *device = (gsl_device_t *) cookie;*/ + + switch(id) + { + // error condition interrupt + case GSL_INTR_YDX_SQ_PS_WATCHDOG: + case GSL_INTR_YDX_SQ_VS_WATCHDOG: + + // todo: take appropriate action + + break; + + default: + + break; + } +} + +//---------------------------------------------------------------------------- + +#ifdef _DEBUG + +static int +kgsl_yamato_bist(gsl_device_t *device) +{ + int status = GSL_FAILURE; + unsigned int link[2]; + + if (!(device->flags & GSL_FLAGS_STARTED)) + { + return (GSL_FAILURE); + } + + status = kgsl_ringbuffer_bist(&device->ringbuffer); + if (status != GSL_SUCCESS) + { + return (status); + } + + // interrupt bist + link[0] = pm4_type3_packet(PM4_INTERRUPT, 1); + link[1] = CP_INT_CNTL__RB_INT_MASK; + kgsl_ringbuffer_issuecmds(device, 1, &link[0], 2, GSL_CALLER_PROCESSID_GET()); + + status = kgsl_mmu_bist(&device->mmu); + if (status != GSL_SUCCESS) + { + return (status); + } + + return (status); +} +#endif + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_isr(gsl_device_t *device) +{ + unsigned int status; +#ifdef _DEBUG + mh_mmu_page_fault_u page_fault = {0}; + mh_axi_error_u axi_error = {0}; + mh_clnt_axi_id_reuse_u clnt_axi_id_reuse = {0}; + rbbm_read_error_u read_error = {0}; +#endif // DEBUG + + // determine if yamato is interrupting, and if so, which block + device->ftbl.device_regread(device, mmMASTER_INT_SIGNAL, &status); + + if (status & MASTER_INT_SIGNAL__MH_INT_STAT) + { +#ifdef _DEBUG + // obtain mh error information + device->ftbl.device_regread(device, mmMH_MMU_PAGE_FAULT, (unsigned int *)&page_fault); + device->ftbl.device_regread(device, mmMH_AXI_ERROR, (unsigned int *)&axi_error); + device->ftbl.device_regread(device, mmMH_CLNT_AXI_ID_REUSE, (unsigned int *)&clnt_axi_id_reuse); +#endif // DEBUG + + kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_MH); + } + + if (status & MASTER_INT_SIGNAL__CP_INT_STAT) + { + kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_CP); + } + + if (status & MASTER_INT_SIGNAL__RBBM_INT_STAT) + { +#ifdef _DEBUG + // obtain rbbm error information + device->ftbl.device_regread(device, mmRBBM_READ_ERROR, (unsigned int *)&read_error); +#endif // DEBUG + + kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_RBBM); + } + + if (status & MASTER_INT_SIGNAL__SQ_INT_STAT) + { + kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_SQ); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_tlbinvalidate(gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid) +{ + unsigned int link[2]; + mh_mmu_invalidate_u mh_mmu_invalidate = {0}; + + mh_mmu_invalidate.f.invalidate_all = 1; + mh_mmu_invalidate.f.invalidate_tc = 1; + + // if possible, invalidate via command stream, otherwise via direct register writes + if (device->flags & GSL_FLAGS_STARTED) + { + link[0] = pm4_type0_packet(reg_invalidate, 1); + link[1] = mh_mmu_invalidate.val; + + kgsl_ringbuffer_issuecmds(device, 1, &link[0], 2, pid); + } + else + { + + device->ftbl.device_regwrite(device, reg_invalidate, mh_mmu_invalidate.val); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_setpagetable(gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid) +{ + unsigned int link[25]; + + // if there is an active draw context, set via command stream, + if (device->flags & GSL_FLAGS_STARTED) + { + // wait for graphics pipe to be idle + link[0] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + link[1] = 0x00000000; + + // set page table base + link[2] = pm4_type0_packet(reg_ptbase, 1); + link[3] = ptbase; + + // HW workaround: to resolve MMU page fault interrupts caused by the VGT. It prevents + // the CP PFP from filling the VGT DMA request fifo too early, thereby ensuring that + // the VGT will not fetch vertex/bin data until after the page table base register + // has been updated. + // + // Two null DRAW_INDX_BIN packets are inserted right after the page table base update, + // followed by a wait for idle. The null packets will fill up the VGT DMA request + // fifo and prevent any further vertex/bin updates from occurring until the wait + // has finished. + link[4] = pm4_type3_packet(PM4_SET_CONSTANT, 2); + link[5] = (0x4 << 16) | (mmPA_SU_SC_MODE_CNTL - 0x2000); + link[6] = 0; // disable faceness generation + link[7] = pm4_type3_packet(PM4_SET_BIN_BASE_OFFSET, 1); + link[8] = device->mmu.dummyspace.gpuaddr; + link[9] = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6); + link[10] = 0; // viz query info + link[11] = 0x0003C004; // draw indicator + link[12] = 0; // bin base + link[13] = 3; // bin size + link[14] = device->mmu.dummyspace.gpuaddr; // dma base + link[15] = 6; // dma size + link[16] = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6); + link[17] = 0; // viz query info + link[18] = 0x0003C004; // draw indicator + link[19] = 0; // bin base + link[20] = 3; // bin size + link[21] = device->mmu.dummyspace.gpuaddr; // dma base + link[22] = 6; // dma size + link[23] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + link[24] = 0x00000000; + + kgsl_ringbuffer_issuecmds(device, 1, &link[0], 25, pid); + } + else + { + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + device->ftbl.device_regwrite(device, reg_ptbase, ptbase); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_init(gsl_device_t *device) +{ + int status = GSL_FAILURE; + + device->flags |= GSL_FLAGS_INITIALIZED; + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_ON, 100); + + //We need to make sure all blocks are powered up and clocked before + //issuing a soft reset. The overrides will be turned off (set to 0) + //later in kgsl_yamato_start. + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0xfffffffe); + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0xffffffff); + + // soft reset + device->ftbl.device_regwrite(device, mmRBBM_SOFT_RESET, 0xFFFFFFFF); + kos_sleep(50); + device->ftbl.device_regwrite(device, mmRBBM_SOFT_RESET, 0x00000000); + + // RBBM control + device->ftbl.device_regwrite(device, mmRBBM_CNTL, 0x00004442); + + // setup MH arbiter + device->ftbl.device_regwrite(device, mmMH_ARBITER_CONFIG, *(unsigned int *) &gsl_cfg_yamato_mharb); + + // SQ_*_PROGRAM + device->ftbl.device_regwrite(device, mmSQ_VS_PROGRAM, 0x00000000); + device->ftbl.device_regwrite(device, mmSQ_PS_PROGRAM, 0x00000000); + + // init interrupt + status = kgsl_intr_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + // init mmu + status = kgsl_mmu_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + return(status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_close(gsl_device_t *device) +{ + if (device->refcnt == 0) + { + // shutdown mmu + kgsl_mmu_close(device); + + // shutdown interrupt + kgsl_intr_close(device); + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_OFF, 0); + + device->flags &= ~GSL_FLAGS_INITIALIZED; + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_destroy(gsl_device_t *device) +{ + int i; + unsigned int pid; + +#ifdef _DEBUG + // for now, signal catastrophic failure in a brute force way + KOS_ASSERT(0); +#endif // _DEBUG + + // todo: - hard reset core? + + kgsl_drawctxt_destroyall(device); + + for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++) + { + pid = device->callerprocess[i]; + if (pid) + { + device->ftbl.device_stop(device); + kgsl_driver_destroy(pid); + + // todo: terminate client process? + } + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_start(gsl_device_t *device, gsl_flags_t flags) +{ + int status = GSL_FAILURE; + unsigned int pm1, pm2; + + KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPFBSTART(device)); + + (void) flags; // unreferenced formal parameter + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_ON, 100); + + // default power management override when running in safe mode + pm1 = (device->flags & GSL_FLAGS_SAFEMODE) ? 0xFFFFFFFE : 0x00000000; + pm2 = (device->flags & GSL_FLAGS_SAFEMODE) ? 0x000000FF : 0x00000000; + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, pm1); + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, pm2); + + // enable rbbm interrupts + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR, kgsl_yamato_rbbmintrcallback, (void *) device); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE, kgsl_yamato_rbbmintrcallback, (void *) device); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE, kgsl_yamato_rbbmintrcallback, (void *) device); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE); +#if defined GSL_RB_TIMESTAMP_INTERUPT + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER, kgsl_yamato_cpintrcallback, (void *) device); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER); +#endif + + //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE); + + // enable sq interrupts + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG, kgsl_yamato_sqintrcallback, (void *) device); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG, kgsl_yamato_sqintrcallback, (void *) device); + //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG); + //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG); + + // init gmem + kgsl_yamato_gmeminit(device); + + // init ring buffer + status = kgsl_ringbuffer_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + // init draw context + status = kgsl_drawctxt_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + device->flags |= GSL_FLAGS_STARTED; + + KGSL_DEBUG(GSL_DBGFLAGS_BIST, kgsl_yamato_bist(device)); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_stop(gsl_device_t *device) +{ + // disable rbbm interrupts + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR); + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE); + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE); +#if defined GSL_RB_TIMESTAMP_INTERUPT + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER); +#endif + + // disable sq interrupts + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG); + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG); + + kgsl_drawctxt_close(device); + + // shutdown ringbuffer + kgsl_ringbuffer_close(&device->ringbuffer); + + // shutdown gmem + kgsl_yamato_gmemclose(device); + + if(device->refcnt == 0) + { + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_OFF, 0); + } + + device->flags &= ~GSL_FLAGS_STARTED; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_getproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_FAILURE; + +#ifndef _DEBUG + (void) sizebytes; // unreferenced formal parameter +#endif + + if (type == GSL_PROP_DEVICE_INFO) + { + gsl_devinfo_t *devinfo = (gsl_devinfo_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_devinfo_t)); + + devinfo->device_id = device->id; + devinfo->chip_id = (gsl_chipid_t)device->chip_id; + devinfo->mmu_enabled = kgsl_mmu_isenabled(&device->mmu); + devinfo->gmem_hostbaseaddr = device->gmemspace.mmio_virt_base; + devinfo->gmem_gpubaseaddr = device->gmemspace.gpu_base; + devinfo->gmem_sizebytes = device->gmemspace.sizebytes; + devinfo->high_precision = 0; + + status = GSL_SUCCESS; + } + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_setproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_FAILURE; + +#ifndef _DEBUG + (void) sizebytes; // unreferenced formal parameter +#endif + + if (type == GSL_PROP_DEVICE_POWER) + { + gsl_powerprop_t *power = (gsl_powerprop_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_powerprop_t)); + + if (!(device->flags & GSL_FLAGS_SAFEMODE)) + { + if (power->flags & GSL_PWRFLAGS_OVERRIDE_ON) + { + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0xfffffffe); + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0xffffffff); + } + else if (power->flags & GSL_PWRFLAGS_OVERRIDE_OFF) + { + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0x00000000); + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0x00000000); + } + else + { + kgsl_hal_setpowerstate(device->id, power->flags, power->value); + } + } + + status = GSL_SUCCESS; + } + else if (type == GSL_PROP_DEVICE_DMI) + { + gsl_dmiprop_t *dmi = (gsl_dmiprop_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_dmiprop_t)); + + // + // In order to enable DMI, it must not already be enabled. + // + switch (dmi->flags) + { + case GSL_DMIFLAGS_ENABLE_SINGLE: + case GSL_DMIFLAGS_ENABLE_DOUBLE: + if (!gsl_driver.dmi_state) + { + gsl_driver.dmi_state = OS_TRUE; + gsl_driver.dmi_mode = dmi->flags; + gsl_driver.dmi_frame = -1; + status = GSL_SUCCESS; + } + break; + case GSL_DMIFLAGS_DISABLE: + // + // To disable, we must be enabled. + // + if (gsl_driver.dmi_state) + { + gsl_driver.dmi_state = OS_FALSE; + gsl_driver.dmi_mode = -1; + gsl_driver.dmi_frame = -2; + status = GSL_SUCCESS; + } + break; + case GSL_DMIFLAGS_NEXT_BUFFER: + // + // Going to the next buffer is dependent upon what mod we are in with respect to single, double, or triple buffering. + // DMI must also be enabled. + // + if (gsl_driver.dmi_state) + { + unsigned int cmdbuf[10]; + unsigned int *cmds = &cmdbuf[0]; + int size; + + if (gsl_driver.dmi_frame == -1) + { + size = 8; + + *cmds++ = pm4_type0_packet(mmRBBM_DSPLY, 1); + switch (gsl_driver.dmi_mode) + { + case GSL_DMIFLAGS_ENABLE_SINGLE: + gsl_driver.dmi_max_frame = 1; + *cmds++ = 0x041000410; + break; + case GSL_DMIFLAGS_ENABLE_DOUBLE: + gsl_driver.dmi_max_frame = 2; + *cmds++ = 0x041000510; + break; + case GSL_DMIFLAGS_ENABLE_TRIPLE: + gsl_driver.dmi_max_frame = 3; + *cmds++ = 0x041000610; + break; + } + } + else + { + size = 6; + } + + + // + // Wait for 3D core to be idle and wait for vsync + // + *cmds++ = pm4_type0_packet(mmWAIT_UNTIL, 1); + *cmds++ = 0x00008000; // 3d idle + // *cmds++ = 0x00008008; // 3d idle & vsync + + // + // Update the render latest register. + // + *cmds++ = pm4_type0_packet(mmRBBM_RENDER_LATEST, 1); + switch (gsl_driver.dmi_frame) + { + case 0: + // + // Render frame 0 + // + *cmds++ = 0; + // + // Wait for our max frame # indicator to be de-asserted + // + *cmds++ = pm4_type0_packet(mmWAIT_UNTIL, 1); + *cmds++ = 0x00000008 << gsl_driver.dmi_max_frame; + gsl_driver.dmi_frame = 1; + break; + case -1: + case 1: + // + // Render frame 1 + // + *cmds++ = 1; + *cmds++ = pm4_type0_packet(mmWAIT_UNTIL, 1); + *cmds++ = 0x00000010; // Wait for frame 0 to be deasserted + gsl_driver.dmi_frame = 2; + break; + case 2: + // + // Render frame 2 + // + *cmds++ = 2; + *cmds++ = pm4_type0_packet(mmWAIT_UNTIL, 1); + *cmds++ = 0x00000020; // Wait for frame 1 to be deasserted + gsl_driver.dmi_frame = 0; + break; + } + + // issue the commands + kgsl_ringbuffer_issuecmds(device, 1, &cmdbuf[0], size, GSL_CALLER_PROCESSID_GET()); + + gsl_driver.dmi_frame %= gsl_driver.dmi_max_frame; + status = GSL_SUCCESS; + } + break; + default: + status = GSL_FAILURE; + break; + } + } + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_idle(gsl_device_t *device, unsigned int timeout) +{ + int status = GSL_FAILURE; + gsl_ringbuffer_t *rb = &device->ringbuffer; + rbbm_status_u rbbm_status; + + (void) timeout; // unreferenced formal parameter + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_REGPOLL, device->id, mmRBBM_STATUS, 0x80000000, "kgsl_yamato_idle")); + + // first, wait until the CP has consumed all the commands in the ring buffer + if (rb->flags & GSL_FLAGS_STARTED) + { + do + { + GSL_RB_GET_READPTR(rb, &rb->rptr); + + } while (rb->rptr != rb->wptr); + } + + // now, wait for the GPU to finish its operations + for ( ; ; ) + { + device->ftbl.device_regread(device, mmRBBM_STATUS, (unsigned int *)&rbbm_status); + + if (!(rbbm_status.val & 0x80000000)) + { + status = GSL_SUCCESS; + break; + } + + } + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_regread(gsl_device_t *device, unsigned int offsetwords, unsigned int *value) +{ + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + if (!(gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX_WITHOUT_IFH)) + { + if(offsetwords == mmCP_RB_RPTR || offsetwords == mmCP_RB_WPTR) + { + *value = device->ringbuffer.wptr; + return (GSL_SUCCESS); + } + } + }); + + GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_regwrite(gsl_device_t *device, unsigned int offsetwords, unsigned int value) +{ + KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPREGWRITE(offsetwords, value)); + + GSL_HAL_REG_WRITE(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value); + + // idle device when running in safe mode + if (device->flags & GSL_FLAGS_SAFEMODE) + { + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_waitirq(gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout) +{ + int status = GSL_FAILURE_NOTSUPPORTED; + + if (intr_id == GSL_INTR_YDX_CP_IB1_INT || intr_id == GSL_INTR_YDX_CP_IB2_INT || + intr_id == GSL_INTR_YDX_CP_SW_INT || intr_id == GSL_INTR_YDX_RBBM_DISPLAY_UPDATE) + { + if (kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS) + { + // wait until intr completion event is received + if (kos_event_wait(device->intr.evnt[intr_id], timeout) == OS_SUCCESS) + { + *count = 1; + status = GSL_SUCCESS; + } + else + { + status = GSL_FAILURE_TIMEOUT; + } + } + } + + return (status); +} + +int +kgsl_yamato_waittimestamp(gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout) +{ +#if defined GSL_RB_TIMESTAMP_INTERUPT +#ifndef _LINUX + return kos_event_wait( device->timestamp_event, timeout ); +#else + int status = wait_event_interruptible_timeout(device->timestamp_waitq, + kgsl_cmdstream_check_timestamp(device->id, timestamp), + msecs_to_jiffies(timeout)); + if (status > 0) + return GSL_SUCCESS; + else + return GSL_FAILURE; +#endif +#else + return (GSL_SUCCESS); +#endif +} +//---------------------------------------------------------------------------- + +int +kgsl_yamato_runpending(gsl_device_t *device) +{ + (void) device; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_getfunctable(gsl_functable_t *ftbl) +{ + ftbl->device_init = kgsl_yamato_init; + ftbl->device_close = kgsl_yamato_close; + ftbl->device_destroy = kgsl_yamato_destroy; + ftbl->device_start = kgsl_yamato_start; + ftbl->device_stop = kgsl_yamato_stop; + ftbl->device_getproperty = kgsl_yamato_getproperty; + ftbl->device_setproperty = kgsl_yamato_setproperty; + ftbl->device_idle = kgsl_yamato_idle; + ftbl->device_waittimestamp = kgsl_yamato_waittimestamp; + ftbl->device_regread = kgsl_yamato_regread; + ftbl->device_regwrite = kgsl_yamato_regwrite; + ftbl->device_waitirq = kgsl_yamato_waitirq; + ftbl->device_runpending = kgsl_yamato_runpending; + ftbl->intr_isr = kgsl_yamato_isr; + ftbl->mmu_tlbinvalidate = kgsl_yamato_tlbinvalidate; + ftbl->mmu_setpagetable = kgsl_yamato_setpagetable; + ftbl->cmdstream_issueibcmds = kgsl_ringbuffer_issueibcmds; + ftbl->context_create = kgsl_drawctxt_create; + ftbl->context_destroy = kgsl_drawctxt_destroy; + + return (GSL_SUCCESS); +} + +#endif + diff --git a/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl b/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl new file mode 100644 index 000000000000..dfe61295e9ef --- /dev/null +++ b/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl @@ -0,0 +1,327 @@ +/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of QUALCOMM Incorporated nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef PFP_MICROCODE_NRT_H +#define PFP_MICROCODE_NRT_H + +#define PFP_MICROCODE_VERSION 308308 + +#define PFP_MICROCODE_SIZE_NRT 288 + +uint32 aPFP_Microcode_nrt[PFP_MICROCODE_SIZE_NRT]={ +0xc60400, +0x7e424b, +0xa00000, +0x7e828b, +0x800001, +0xc60400, +0xcc4003, +0x800000, +0xd60003, +0x800000, +0xc62c00, +0xc80c35, +0x98c000, +0xc80c35, +0x880000, +0xc80c1d, +0x84000b, +0xc60800, +0x98c007, +0xc61000, +0x978003, +0xcc4003, +0xd60004, +0x800000, +0xcd0003, +0x9783e8, +0xc60400, +0x800000, +0xc60400, +0x84000b, +0xc60800, +0x98c00c, +0xc61000, +0xcc4003, +0xc61400, +0xc61800, +0x7d6d40, +0xcd401e, +0x978003, +0xcd801e, +0xd60004, +0x800000, +0xcd0003, +0x800000, +0xd6001f, +0x84000b, +0xc60800, +0x98c007, +0xc60c00, +0xcc4003, +0xcc8003, +0xccc003, +0x800000, +0xd60003, +0x800000, +0xd6001f, +0xc60800, +0x348c08, +0x98c006, +0xc80c1e, +0x98c000, +0xc80c1e, +0x800041, +0xcc8007, +0xcc8008, +0xcc4003, +0x800000, +0xcc8003, +0xc60400, +0x1a9c07, +0xca8821, +0x95c3b9, +0xc8102c, +0x98800a, +0x329418, +0x9a4004, +0xcc6810, +0x042401, +0xd00143, +0xd00162, +0xcd0002, +0x7d514c, +0xcd4003, +0x9b8007, +0x06a801, +0x964003, +0xc28000, +0xcf4003, +0x800001, +0xc60400, +0x800045, +0xc60400, +0x800001, +0xc60400, +0xc60800, +0xc60c00, +0xc8102d, +0x349402, +0x99000b, +0xc8182e, +0xcd4002, +0xcd8002, +0xd001e3, +0xd001c3, +0xccc003, +0xcc801c, +0xcd801d, +0x800001, +0xc60400, +0xd00203, +0x800000, +0xd001c3, +0xc8081f, +0xc60c00, +0xc80c20, +0x988000, +0xc8081f, +0xcc4003, +0xccc003, +0xd60003, +0xccc022, +0xcc001f, +0x800000, +0xcc001f, +0xc81c2f, +0xc60400, +0xc60800, +0xc60c00, +0xc81030, +0x99c000, +0xc81c2f, +0xcc8021, +0xcc4020, +0x990011, +0xc107ff, +0xd00223, +0xd00243, +0x345402, +0x7cb18b, +0x7d95cc, +0xcdc002, +0xccc002, +0xd00263, +0x978005, +0xccc003, +0xc60800, +0x80008a, +0xc60c00, +0x800000, +0xd00283, +0x97836b, +0xc60400, +0xd6001f, +0x800001, +0xc60400, +0xd2000d, +0xcc000d, +0x800000, +0xcc000d, +0xc60800, +0xc60c00, +0xca1433, +0xd022a0, +0xcce000, +0x99435c, +0xcce005, +0x800000, +0x062001, +0xc60800, +0xc60c00, +0xd202c3, +0xcc8003, +0xccc003, +0xcce027, +0x800000, +0x062001, +0xca0831, +0x9883ff, +0xca0831, +0xd6001f, +0x800001, +0xc60400, +0x0a2001, +0x800001, +0xc60400, +0xd20009, +0xd2000a, +0xcc001f, +0x800000, +0xcc001f, +0xd2000b, +0xd2000c, +0xcc001f, +0x800000, +0xcc001f, +0xcc0023, +0xcc4003, +0xce0003, +0x800000, +0xd60003, +0xd00303, +0xcc0024, +0xcc4003, +0x800000, +0xd60003, +0xd00323, +0xcc0025, +0xcc4003, +0x800000, +0xd60003, +0xd00343, +0xcc0026, +0xcc4003, +0x800000, +0xd60003, +0x800000, +0xd6001f, +0x280401, +0xd20001, +0xcc4001, +0xcc4006, +0x8400e7, +0xc40802, +0xc40c02, +0xcc402b, +0x98831f, +0xc63800, +0x8400e7, +0xcf802b, +0x800000, +0xd6001f, +0xcc001f, +0x880000, +0xcc001f, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x0100c8, +0x0200cd, +0x0300d2, +0x050004, +0x1000d7, +0x1700b6, +0x220010, +0x230038, +0x250044, +0x27005e, +0x2d0070, +0x2e007c, +0x4b0009, +0x34001d, +0x36002d, +0x3700a8, +0x3b009b, +0x3f009f, +0x4400d9, +0x4800c3, +0x5000b9, +0x5100be, +0x5500c9, +0x5600ce, +0x5700d3, +0x5d00b0, +0x000006, +0x000006, +0x000006, +0x000006, +0x000006, +0x000006, +}; + +#endif diff --git a/drivers/mxc/amd-gpu/common/pm4_microcode.inl b/drivers/mxc/amd-gpu/common/pm4_microcode.inl new file mode 100644 index 000000000000..03f6f4cd35e4 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/pm4_microcode.inl @@ -0,0 +1,815 @@ +/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of QUALCOMM Incorporated nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef PM4_MICROCODE_H +#define PM4_MICROCODE_H + +#define PM4_MICROCODE_VERSION 300684 + +#define PM4_MICROCODE_SIZE 768 + + +#ifdef _PRIMLIB_INCLUDE +extern uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]; +#else +uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0xc0200400, 0x000 }, + { 0x00000000, 0x00a0000a, 0x000 }, + { 0x000001f3, 0x00204411, 0x000 }, + { 0x01000000, 0x00204811, 0x000 }, + { 0x00000000, 0x00400000, 0x004 }, + { 0x0000ffff, 0x00284621, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x34e00000, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x0000ffff, 0xc0280a20, 0x000 }, + { 0x00000000, 0x00294582, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x0000ffff, 0xc0284620, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x00600000, 0x2a8 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x000021fc, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404803, 0x021 }, + { 0x00000000, 0x00600000, 0x2a8 }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x000021fc, 0x0029462c, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00003fff, 0x002f022f, 0x000 }, + { 0x00000000, 0x0ce00000, 0x000 }, + { 0x0000a1fd, 0x0029462c, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x021 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00001000, 0x00281223, 0x000 }, + { 0x00001000, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ce00000, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x0000000e, 0x00404811, 0x000 }, + { 0x00000394, 0x00204411, 0x000 }, + { 0x00000001, 0xc0404811, 0x000 }, + { 0x00000000, 0x00600000, 0x2a8 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000008, 0xc0210a20, 0x000 }, + { 0x00000000, 0x14e00000, 0x02d }, + { 0x00000007, 0x00404811, 0x000 }, + { 0x00000008, 0x00404811, 0x000 }, + { 0x0000001f, 0x40280a20, 0x000 }, + { 0x0000001b, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x043 }, + { 0x00000002, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x04a }, + { 0x00000003, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x051 }, + { 0x00000004, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x058 }, + { 0x00000014, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x058 }, + { 0x00000015, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x060 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0xc0404802, 0x000 }, + { 0x0000001f, 0x40280a20, 0x000 }, + { 0x0000001b, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x043 }, + { 0x00000002, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x04a }, + { 0x00000000, 0x00400000, 0x051 }, + { 0x0000001f, 0xc0210e20, 0x000 }, + { 0x00000612, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404802, 0x000 }, + { 0x0000001e, 0xc0210e20, 0x000 }, + { 0x00000600, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404802, 0x000 }, + { 0x0000001e, 0xc0210e20, 0x000 }, + { 0x00000605, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404802, 0x000 }, + { 0x0000001f, 0x40280a20, 0x000 }, + { 0x0000001f, 0xc0210e20, 0x000 }, + { 0x0000060a, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404802, 0x000 }, + { 0x0000001f, 0xc0680a20, 0x2a8 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404802, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00001fff, 0x40280a20, 0x000 }, + { 0x80000000, 0x40280e20, 0x000 }, + { 0x40000000, 0xc0281220, 0x000 }, + { 0x00040000, 0x00694622, 0x2b2 }, + { 0x00000000, 0x00201410, 0x000 }, + { 0x00000000, 0x002f0223, 0x000 }, + { 0x00000000, 0x0ae00000, 0x06d }, + { 0x00000000, 0xc0401800, 0x070 }, + { 0x00001fff, 0xc0281a20, 0x000 }, + { 0x00040000, 0x00694626, 0x2b2 }, + { 0x00000000, 0x00201810, 0x000 }, + { 0x00000000, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ae00000, 0x073 }, + { 0x00000000, 0xc0401c00, 0x076 }, + { 0x00001fff, 0xc0281e20, 0x000 }, + { 0x00040000, 0x00694627, 0x2b2 }, + { 0x00000000, 0x00201c10, 0x000 }, + { 0x00000000, 0x00204402, 0x000 }, + { 0x00000000, 0x002820c5, 0x000 }, + { 0x00000000, 0x004948e8, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x00000010, 0x40210a20, 0x000 }, + { 0x000000ff, 0x00280a22, 0x000 }, + { 0x000007ff, 0x40280e20, 0x000 }, + { 0x00000002, 0x00221e23, 0x000 }, + { 0x00000005, 0xc0211220, 0x000 }, + { 0x00080000, 0x00281224, 0x000 }, + { 0x00000013, 0x00210224, 0x000 }, + { 0x00000000, 0x14c00000, 0x084 }, + { 0xa100ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x088 }, + { 0x00000000, 0x0020162d, 0x000 }, + { 0x00004000, 0x00500e23, 0x097 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x08c }, + { 0x00000001, 0x0020162d, 0x000 }, + { 0x00004800, 0x00500e23, 0x097 }, + { 0x00000002, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x090 }, + { 0x00000003, 0x0020162d, 0x000 }, + { 0x00004900, 0x00500e23, 0x097 }, + { 0x00000003, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x094 }, + { 0x00000002, 0x0020162d, 0x000 }, + { 0x00004908, 0x00500e23, 0x097 }, + { 0x00000012, 0x0020162d, 0x000 }, + { 0x00002000, 0x00300e23, 0x000 }, + { 0x00000000, 0x00290d83, 0x000 }, + { 0x9400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x002948e5, 0x000 }, + { 0x00000000, 0x00294483, 0x000 }, + { 0x00000000, 0x40201800, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000013, 0x00210224, 0x000 }, + { 0x00000000, 0x14c00000, 0x000 }, + { 0x9400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x002948e5, 0x000 }, + { 0x9300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00404806, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00000000, 0xc0201400, 0x000 }, + { 0x0000001f, 0x00211a25, 0x000 }, + { 0x00000000, 0x14e00000, 0x000 }, + { 0x000007ff, 0x00280e25, 0x000 }, + { 0x00000010, 0x00211225, 0x000 }, + { 0x8300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0ae }, + { 0x00000000, 0x00203622, 0x000 }, + { 0x00004000, 0x00504a23, 0x0bd }, + { 0x00000001, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0b2 }, + { 0x00000001, 0x00203622, 0x000 }, + { 0x00004800, 0x00504a23, 0x0bd }, + { 0x00000002, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0b6 }, + { 0x00000003, 0x00203622, 0x000 }, + { 0x00004900, 0x00504a23, 0x0bd }, + { 0x00000003, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0ba }, + { 0x00000002, 0x00203622, 0x000 }, + { 0x00004908, 0x00504a23, 0x0bd }, + { 0x00000012, 0x00203622, 0x000 }, + { 0x00000000, 0x00290d83, 0x000 }, + { 0x00002000, 0x00304a23, 0x000 }, + { 0x8400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0x21000000, 0x000 }, + { 0x00000000, 0x00400000, 0x0a4 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00040578, 0x00604411, 0x2b2 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x00000000, 0xc0201400, 0x000 }, + { 0x00000000, 0xc0201800, 0x000 }, + { 0x00007f00, 0x00280a21, 0x000 }, + { 0x00004500, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x0cd }, + { 0x00000000, 0xc0201c00, 0x000 }, + { 0x00000000, 0x17000000, 0x000 }, + { 0x00000010, 0x00280a23, 0x000 }, + { 0x00000010, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x0d5 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00040000, 0x00694624, 0x2b2 }, + { 0x00000000, 0x00400000, 0x0d6 }, + { 0x00000000, 0x00600000, 0x135 }, + { 0x00000000, 0x002820d0, 0x000 }, + { 0x00000007, 0x00280a23, 0x000 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0dd }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x04e00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000002, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0e2 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x02e00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000003, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0e7 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x0ce00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000004, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0ec }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000005, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0f1 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x06e00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000006, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0f6 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x08e00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00007f00, 0x00280a21, 0x000 }, + { 0x00004500, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x000 }, + { 0x00000008, 0x00210a23, 0x000 }, + { 0x00000000, 0x14e00000, 0x11b }, + { 0x00000000, 0xc0204400, 0x000 }, + { 0x00000000, 0xc0404800, 0x000 }, + { 0x00007f00, 0x00280a21, 0x000 }, + { 0x00004500, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x102 }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00000000, 0x00404c07, 0x0cd }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x00000000, 0xc0201400, 0x000 }, + { 0x00000000, 0xc0201800, 0x000 }, + { 0x00000000, 0xc0201c00, 0x000 }, + { 0x00000000, 0x17000000, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00040000, 0x00694624, 0x2b2 }, + { 0x00000000, 0x002820d0, 0x000 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x0ce00000, 0x000 }, + { 0x00000000, 0x00404c07, 0x107 }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x00000000, 0xc0201400, 0x000 }, + { 0x00000000, 0xc0201800, 0x000 }, + { 0x00000000, 0xc0201c00, 0x000 }, + { 0x00000000, 0x17000000, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00040000, 0x00694624, 0x2b2 }, + { 0x00000000, 0x002820d0, 0x000 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x06e00000, 0x000 }, + { 0x00000000, 0x00404c07, 0x113 }, + { 0x0000060d, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x0000860e, 0x00204411, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000009, 0x00204811, 0x000 }, + { 0x0000060d, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0x00404810, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00007fff, 0x00281a22, 0x000 }, + { 0x00040000, 0x00694626, 0x2b2 }, + { 0x00000000, 0x00200c10, 0x000 }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x80000000, 0x00281a22, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, + { 0x00000000, 0x0ce00000, 0x132 }, + { 0x00000000, 0x00600000, 0x135 }, + { 0x00000000, 0x00201c10, 0x000 }, + { 0x00000000, 0x00300c67, 0x000 }, + { 0x0000060d, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000000, 0x00404803, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0xa400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0x000001ea, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000000, 0x1ac00000, 0x13b }, + { 0x9e00ffff, 0x00204411, 0x000 }, + { 0xdeadbeef, 0x00204811, 0x000 }, + { 0x00000000, 0x1ae00000, 0x13e }, + { 0xa400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x0080480b, 0x000 }, + { 0x000001f3, 0x00204411, 0x000 }, + { 0xe0000000, 0xc0484a20, 0x000 }, + { 0x00000000, 0xd9000000, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x8c00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000fff, 0x00281223, 0x000 }, + { 0x0000000f, 0x00203624, 0x000 }, + { 0x00000003, 0x00381224, 0x000 }, + { 0x00005000, 0x00301224, 0x000 }, + { 0x0000000e, 0x00203624, 0x000 }, + { 0x8700ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000001, 0x00331224, 0x000 }, + { 0x8600ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x0000001d, 0x00211223, 0x000 }, + { 0x00000020, 0x00222091, 0x000 }, + { 0x00000003, 0x00381228, 0x000 }, + { 0x8800ffff, 0x00204411, 0x000 }, + { 0x00004fff, 0x00304a24, 0x000 }, + { 0x00000010, 0x00211623, 0x000 }, + { 0x00000fff, 0x00281625, 0x000 }, + { 0x00000fff, 0x00281a23, 0x000 }, + { 0x00000000, 0x00331ca6, 0x000 }, + { 0x8f00ffff, 0x00204411, 0x000 }, + { 0x00000003, 0x00384a27, 0x000 }, + { 0x00000010, 0x00211223, 0x000 }, + { 0x00000fff, 0x00281224, 0x000 }, + { 0x0000000d, 0x00203624, 0x000 }, + { 0x8b00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000003, 0x00381224, 0x000 }, + { 0x00005000, 0x00301224, 0x000 }, + { 0x0000000c, 0x00203624, 0x000 }, + { 0x8500ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000000, 0x00331cc8, 0x000 }, + { 0x9000ffff, 0x00204411, 0x000 }, + { 0x00000003, 0x00384a27, 0x000 }, + { 0x00300000, 0x00493a2e, 0x000 }, + { 0x00000000, 0x00202c11, 0x000 }, + { 0x00000001, 0x00303e2f, 0x000 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x172 }, + { 0x00000000, 0xd9000000, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x00000000, 0x002f0230, 0x000 }, + { 0x00000000, 0x0ae00000, 0x175 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00000009, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x17d }, + { 0x00000000, 0x00600000, 0x2af }, + { 0x00000000, 0x00200c11, 0x000 }, + { 0x00000016, 0x00203623, 0x000 }, + { 0x00000000, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x180 }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000001, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x183 }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000002, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x18d }, + { 0x00000004, 0xc0203620, 0x000 }, + { 0x00000005, 0xc0203620, 0x000 }, + { 0x00000006, 0xc0203620, 0x000 }, + { 0x00000007, 0xc0203620, 0x000 }, + { 0x00000008, 0xc0203620, 0x000 }, + { 0x00000009, 0xc0203620, 0x000 }, + { 0x0000000a, 0xc0203620, 0x000 }, + { 0x0000000b, 0xc0203620, 0x000 }, + { 0x00000003, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1b5 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x8c00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000fff, 0x00281223, 0x000 }, + { 0x0000000f, 0x00203624, 0x000 }, + { 0x00000003, 0x00381224, 0x000 }, + { 0x00005000, 0x00301224, 0x000 }, + { 0x0000000e, 0x00203624, 0x000 }, + { 0x8700ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000001, 0x00331224, 0x000 }, + { 0x8600ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x0000001d, 0x00211223, 0x000 }, + { 0x00000020, 0x00222091, 0x000 }, + { 0x00000003, 0x00381228, 0x000 }, + { 0x8800ffff, 0x00204411, 0x000 }, + { 0x00004fff, 0x00304a24, 0x000 }, + { 0x00000010, 0x00211623, 0x000 }, + { 0x00000fff, 0x00281625, 0x000 }, + { 0x00000fff, 0x00281a23, 0x000 }, + { 0x00000000, 0x00331ca6, 0x000 }, + { 0x8f00ffff, 0x00204411, 0x000 }, + { 0x00000003, 0x00384a27, 0x000 }, + { 0x00000010, 0x00211223, 0x000 }, + { 0x00000fff, 0x00281224, 0x000 }, + { 0x0000000d, 0x00203624, 0x000 }, + { 0x8b00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000003, 0x00381224, 0x000 }, + { 0x00005000, 0x00301224, 0x000 }, + { 0x0000000c, 0x00203624, 0x000 }, + { 0x8500ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000000, 0x00331cc8, 0x000 }, + { 0x9000ffff, 0x00204411, 0x000 }, + { 0x00000003, 0x00384a27, 0x000 }, + { 0x00300000, 0x00293a2e, 0x000 }, + { 0x00000004, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1bd }, + { 0xa300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x40204800, 0x000 }, + { 0x0000000a, 0xc0220e20, 0x000 }, + { 0x00000011, 0x00203623, 0x000 }, + { 0x000021f4, 0x00204411, 0x000 }, + { 0x0000000a, 0x00614a2c, 0x2af }, + { 0x00000005, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1c0 }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000006, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1c6 }, + { 0x9c00ffff, 0x00204411, 0x000 }, + { 0x0000001f, 0x40214a20, 0x000 }, + { 0x9600ffff, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000007, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1d0 }, + { 0x3fffffff, 0x00283a2e, 0x000 }, + { 0xc0000000, 0x40280e20, 0x000 }, + { 0x00000000, 0x0029386e, 0x000 }, + { 0x18000000, 0x40280e20, 0x000 }, + { 0x00000016, 0x00203623, 0x000 }, + { 0xa400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0xc0202c00, 0x000 }, + { 0x00000000, 0x0020480b, 0x000 }, + { 0x00000008, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1dc }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x00000013, 0x00203623, 0x000 }, + { 0x00000015, 0x00203623, 0x000 }, + { 0x00000002, 0x40221220, 0x000 }, + { 0x00000000, 0x00301083, 0x000 }, + { 0x00000014, 0x00203624, 0x000 }, + { 0x00000003, 0xc0210e20, 0x000 }, + { 0x10000000, 0x00280e23, 0x000 }, + { 0xefffffff, 0x00283a2e, 0x000 }, + { 0x00000000, 0x0029386e, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x0000001f, 0x00210e22, 0x000 }, + { 0x00000000, 0x14e00000, 0x000 }, + { 0x000003ff, 0x00280e22, 0x000 }, + { 0x00000018, 0x00211222, 0x000 }, + { 0x00000004, 0x00301224, 0x000 }, + { 0x00000000, 0x0020108d, 0x000 }, + { 0x00002000, 0x00291224, 0x000 }, + { 0x8300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00294984, 0x000 }, + { 0x8400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x21000000, 0x000 }, + { 0x00000000, 0x00400000, 0x1de }, + { 0x8200ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00003fff, 0x40280e20, 0x000 }, + { 0x00000010, 0xc0211220, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x1fb }, + { 0x00000000, 0x2ae00000, 0x205 }, + { 0x20000080, 0x00281e2e, 0x000 }, + { 0x00000080, 0x002f0227, 0x000 }, + { 0x00000000, 0x0ce00000, 0x1f8 }, + { 0x00000000, 0x00401c0c, 0x1f9 }, + { 0x00000010, 0x00201e2d, 0x000 }, + { 0x000021f9, 0x00294627, 0x000 }, + { 0x00000000, 0x00404811, 0x205 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x23a }, + { 0x00000000, 0x28e00000, 0x205 }, + { 0x00800080, 0x00281e2e, 0x000 }, + { 0x00000080, 0x002f0227, 0x000 }, + { 0x00000000, 0x0ce00000, 0x202 }, + { 0x00000000, 0x00401c0c, 0x203 }, + { 0x00000010, 0x00201e2d, 0x000 }, + { 0x000021f9, 0x00294627, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x20c }, + { 0x00000003, 0x00204811, 0x000 }, + { 0x0000000c, 0x0020162d, 0x000 }, + { 0x0000000d, 0x00201a2d, 0x000 }, + { 0xffdfffff, 0x00483a2e, 0x210 }, + { 0x00000004, 0x00204811, 0x000 }, + { 0x0000000e, 0x0020162d, 0x000 }, + { 0x0000000f, 0x00201a2d, 0x000 }, + { 0xffefffff, 0x00283a2e, 0x000 }, + { 0x00000000, 0x00201c10, 0x000 }, + { 0x00000000, 0x002f0067, 0x000 }, + { 0x00000000, 0x04e00000, 0x205 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000006, 0x00204811, 0x000 }, + { 0x8300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204805, 0x000 }, + { 0x8900ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204806, 0x000 }, + { 0x8400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x21000000, 0x000 }, + { 0x00000000, 0x00601010, 0x28c }, + { 0x0000000c, 0x00221e24, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x22d }, + { 0x20000000, 0x00293a2e, 0x000 }, + { 0x000021f7, 0x0029462c, 0x000 }, + { 0x00000000, 0x002948c7, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000005, 0x00204811, 0x000 }, + { 0x0000000c, 0x00203630, 0x000 }, + { 0x00000007, 0x00204811, 0x000 }, + { 0x0000000d, 0x00203630, 0x000 }, + { 0x9100ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x23000000, 0x000 }, + { 0x8d00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00404803, 0x240 }, + { 0x00800000, 0x00293a2e, 0x000 }, + { 0x000021f6, 0x0029462c, 0x000 }, + { 0x00000000, 0x002948c7, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000005, 0x00204811, 0x000 }, + { 0x0000000e, 0x00203630, 0x000 }, + { 0x00000007, 0x00204811, 0x000 }, + { 0x0000000f, 0x00203630, 0x000 }, + { 0x9200ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x25000000, 0x000 }, + { 0x8e00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00404803, 0x240 }, + { 0x8300ffff, 0x00204411, 0x000 }, + { 0x00000003, 0x00381224, 0x000 }, + { 0x00005000, 0x00304a24, 0x000 }, + { 0x8400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x21000000, 0x000 }, + { 0x8200ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00404811, 0x000 }, + { 0x00000003, 0x40280a20, 0x000 }, + { 0xffffffe0, 0xc0280e20, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x24a }, + { 0x000021f6, 0x0029122c, 0x000 }, + { 0x00040000, 0x00494624, 0x24c }, + { 0x000021f7, 0x0029122c, 0x000 }, + { 0x00040000, 0x00294624, 0x000 }, + { 0x00000000, 0x00600000, 0x2b2 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x252 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x252 }, + { 0x00000000, 0x00481630, 0x258 }, + { 0x00000fff, 0x00281630, 0x000 }, + { 0x0000000c, 0x00211a30, 0x000 }, + { 0x00000fff, 0x00281a26, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, + { 0x00000000, 0x0ae00000, 0x258 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00040d02, 0x00604411, 0x2b2 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x25d }, + { 0x00000010, 0x00211e30, 0x000 }, + { 0x00000fff, 0x00482630, 0x267 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x261 }, + { 0x00000fff, 0x00281e30, 0x000 }, + { 0x00000200, 0x00402411, 0x267 }, + { 0x00000000, 0x00281e30, 0x000 }, + { 0x00000010, 0x00212630, 0x000 }, + { 0x00000010, 0x00211a30, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, + { 0x00000000, 0x0ae00000, 0x258 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00000003, 0x00381625, 0x000 }, + { 0x00000003, 0x00381a26, 0x000 }, + { 0x00000003, 0x00381e27, 0x000 }, + { 0x00000003, 0x00382629, 0x000 }, + { 0x00005000, 0x00302629, 0x000 }, + { 0x0000060d, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0x00204806, 0x000 }, + { 0x00005000, 0x00302225, 0x000 }, + { 0x00040000, 0x00694628, 0x2b2 }, + { 0x00000001, 0x00302228, 0x000 }, + { 0x00000000, 0x00202810, 0x000 }, + { 0x00040000, 0x00694628, 0x2b2 }, + { 0x00000001, 0x00302228, 0x000 }, + { 0x00000000, 0x00200810, 0x000 }, + { 0x00040000, 0x00694628, 0x2b2 }, + { 0x00000001, 0x00302228, 0x000 }, + { 0x00000000, 0x00201410, 0x000 }, + { 0x0000060d, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x0000860e, 0x00204411, 0x000 }, + { 0x00000000, 0x0020480a, 0x000 }, + { 0x00000000, 0x00204802, 0x000 }, + { 0x00000000, 0x00204805, 0x000 }, + { 0x00000000, 0x002f0128, 0x000 }, + { 0x00000000, 0x0ae00000, 0x282 }, + { 0x00005000, 0x00302227, 0x000 }, + { 0x0000000c, 0x00300e23, 0x000 }, + { 0x00000003, 0x00331a26, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, + { 0x00000000, 0x0ae00000, 0x270 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x000001f3, 0x00204411, 0x000 }, + { 0x04000000, 0x00204811, 0x000 }, + { 0x00000000, 0x00400000, 0x289 }, + { 0x00000000, 0xc0600000, 0x28c }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x0ec00000, 0x28e }, + { 0x00000000, 0x00800000, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000005, 0x00204811, 0x000 }, + { 0x00000000, 0x0020280c, 0x000 }, + { 0x00000011, 0x0020262d, 0x000 }, + { 0x00000000, 0x002f012c, 0x000 }, + { 0x00000000, 0x0ae00000, 0x295 }, + { 0x00000000, 0x00403011, 0x296 }, + { 0x00000400, 0x0030322c, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x0000000a, 0x0021262c, 0x000 }, + { 0x00000000, 0x00210130, 0x000 }, + { 0x00000000, 0x14c00000, 0x29d }, + { 0xa500ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00404811, 0x299 }, + { 0xa500ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0x000021f4, 0x0029462c, 0x000 }, + { 0x0000000a, 0x00214a2a, 0x000 }, + { 0xa200ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x00000000, 0x00210130, 0x000 }, + { 0xdf7fffff, 0x00283a2e, 0x000 }, + { 0x00000010, 0x0080362a, 0x000 }, + { 0x9700ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x0020480c, 0x000 }, + { 0xa200ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x00000000, 0x00810130, 0x000 }, + { 0x00000000, 0x00203011, 0x000 }, + { 0x00000010, 0x0080362c, 0x000 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00000000, 0x1ac00000, 0x2b2 }, + { 0x9f00ffff, 0x00204411, 0x000 }, + { 0xdeadbeef, 0x00204811, 0x000 }, + { 0x00000000, 0x1ae00000, 0x2b5 }, + { 0x00000000, 0x00800000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00020143, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x01dd0002, 0x000 }, + { 0x006301ee, 0x00280012, 0x000 }, + { 0x00020002, 0x00020026, 0x000 }, + { 0x00020002, 0x01ec0002, 0x000 }, + { 0x00790242, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00200012, 0x00020016, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x011b00c5, 0x00020125, 0x000 }, + { 0x00020141, 0x00020002, 0x000 }, + { 0x00c50002, 0x0143002e, 0x000 }, + { 0x00a2016b, 0x00020145, 0x000 }, + { 0x00020002, 0x01200002, 0x000 }, + { 0x00020002, 0x010f0103, 0x000 }, + { 0x00090002, 0x000e000e, 0x000 }, + { 0x0058003d, 0x00600002, 0x000 }, + { 0x000200c1, 0x0002028a, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x000502b1, 0x00020008, 0x000 }, +}; + +#endif +static const uint32 ME_JUMP_TABLE_START = 740; +static const uint32 ME_JUMP_TABLE_END = 768; + +#endif diff --git a/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h b/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h new file mode 100644 index 000000000000..7ec10b0c2556 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h @@ -0,0 +1,86 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DISPLAYAPI_H +#define __GSL_DISPLAYAPI_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +////////////////////////////////////////////////////////////////////////////// +// entrypoints +////////////////////////////////////////////////////////////////////////////// +#ifdef __GSLDISPLAY_EXPORTS +#define DISP_API OS_DLLEXPORT +#else +#define DISP_API OS_DLLIMPORT +#endif // __GSLDISPLAY_EXPORTS + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_DISPLAY_PANEL_TOSHIBA_640x480 0 +#define GSL_DISPLAY_PANEL_HITACHI_240x320 1 +#define GSL_DISPLAY_PANEL_DEFAULT GSL_DISPLAY_PANEL_TOSHIBA_640x480 + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// +typedef int gsl_display_id_t; +typedef int gsl_surface_id_t; + +typedef struct _gsl_displaymode_t { + int panel_id; + int width; + int height; + int bpp; + int orientation; + int frequency; +} gsl_displaymode_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +DISP_API gsl_display_id_t gsl_display_open(gsl_devhandle_t devhandle, int panel_id); +DISP_API int gsl_display_close(gsl_display_id_t display_id); +DISP_API int gsl_display_getcount(void); +DISP_API int gsl_display_setmode(gsl_display_id_t display_id, gsl_displaymode_t displaymode); +DISP_API int gsl_display_getmode(gsl_display_id_t display_id, gsl_displaymode_t *displaymode); +DISP_API gsl_surface_id_t gsl_display_setsurface(gsl_display_id_t display_id, void *buffer); +DISP_API int gsl_display_getactivesurface(gsl_display_id_t display_id, void **buffer); +DISP_API int gsl_display_flipsurface(gsl_display_id_t display_id, gsl_surface_id_t surface_id); + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // __GSL_DISPLAYAPI_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h b/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h new file mode 100644 index 000000000000..8476f5a95969 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h @@ -0,0 +1,135 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_KLIBAPI_H +#define __GSL_KLIBAPI_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#include "gsl_types.h" +#include "gsl_properties.h" + + +////////////////////////////////////////////////////////////////////////////// +// entrypoints +////////////////////////////////////////////////////////////////////////////// +#ifdef __KGSLLIB_EXPORTS +#define KGSL_API OS_DLLEXPORT +#else +#ifdef __KERNEL_MODE__ +#define KGSL_API extern +#else +#define KGSL_API OS_DLLIMPORT +#endif +#endif // __KGSLLIB_EXPORTS + + +////////////////////////////////////////////////////////////////////////////// +// version control +////////////////////////////////////////////////////////////////////////////// +#define KGSLLIB_NAME "AMD GSL Kernel Library" +#define KGSLLIB_VERSION "0.1" + + +////////////////////////////////////////////////////////////////////////////// +// library API +////////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_driver_init(void); +KGSL_API int kgsl_driver_close(void); +KGSL_API int kgsl_driver_entry(gsl_flags_t flags); +KGSL_API int kgsl_driver_exit(void); +KGSL_API int kgsl_driver_destroy(unsigned int pid); + + +//////////////////////////////////////////////////////////////////////////// +// device API +//////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_device_start(gsl_deviceid_t device_id, gsl_flags_t flags); +KGSL_API int kgsl_device_stop(gsl_deviceid_t device_id); +KGSL_API int kgsl_device_idle(gsl_deviceid_t device_id, unsigned int timeout); +KGSL_API int kgsl_device_getproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes); +KGSL_API int kgsl_device_setproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes); +KGSL_API int kgsl_device_regread(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int *value); +KGSL_API int kgsl_device_regwrite(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int value); +KGSL_API int kgsl_device_waitirq(gsl_deviceid_t device_id, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout); + + +//////////////////////////////////////////////////////////////////////////// +// command API +//////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_cmdstream_issueibcmds(gsl_deviceid_t device_id, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags); +KGSL_API gsl_timestamp_t kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id, gsl_timestamp_type_t type); +KGSL_API int kgsl_cmdstream_freememontimestamp(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type); +KGSL_API int kgsl_cmdstream_waittimestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp, unsigned int timeout); +KGSL_API int kgsl_cmdwindow_write(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data); +KGSL_API int kgsl_add_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t *timestamp); +KGSL_API int kgsl_cmdstream_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp); + +//////////////////////////////////////////////////////////////////////////// +// context API +//////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_context_create(gsl_deviceid_t device_id, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags); +KGSL_API int kgsl_context_destroy(gsl_deviceid_t device_id, unsigned int drawctxt_id); +KGSL_API int kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id); + + +//////////////////////////////////////////////////////////////////////////// +// sharedmem API +//////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_sharedmem_alloc(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc); +KGSL_API int kgsl_sharedmem_free(gsl_memdesc_t *memdesc); +KGSL_API int kgsl_sharedmem_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace); +KGSL_API int kgsl_sharedmem_write(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace); +KGSL_API int kgsl_sharedmem_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes); +KGSL_API unsigned int kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags); +KGSL_API int kgsl_sharedmem_map(gsl_deviceid_t device_id, gsl_flags_t flags, const gsl_scatterlist_t *scatterlist, gsl_memdesc_t *memdesc); +KGSL_API int kgsl_sharedmem_unmap(gsl_memdesc_t *memdesc); +KGSL_API int kgsl_sharedmem_getmap(const gsl_memdesc_t *memdesc, gsl_scatterlist_t *scatterlist); +KGSL_API int kgsl_sharedmem_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation); +KGSL_API int kgsl_sharedmem_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr); + + +//////////////////////////////////////////////////////////////////////////// +// interrupt API +//////////////////////////////////////////////////////////////////////////// +KGSL_API void kgsl_intr_isr(void); + + +//////////////////////////////////////////////////////////////////////////// +// TB dump API +//////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_tbdump_waitirq(void); +KGSL_API int kgsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height); + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // __GSL_KLIBAPI_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_libapi.h b/drivers/mxc/amd-gpu/include/api/gsl_libapi.h new file mode 100644 index 000000000000..7a5be862f3ee --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_libapi.h @@ -0,0 +1,142 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_LIBAPI_H +#define __GSL_LIBAPI_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#include "gsl_types.h" + +////////////////////////////////////////////////////////////////////////////// +// entrypoints +////////////////////////////////////////////////////////////////////////////// +#ifdef __GSLLIB_EXPORTS +#define GSL_API OS_DLLEXPORT +#else +#define GSL_API OS_DLLIMPORT +#endif // __GSLLIB_EXPORTS + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSLLIB_NAME "AMD GSL User Library" +#define GSLLIB_VERSION "0.1" + + +////////////////////////////////////////////////////////////////////////////// +// libary API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_library_open(gsl_flags_t flags); +GSL_API int gsl_library_close(void); + + +//////////////////////////////////////////////////////////////////////////// +// device API +//////////////////////////////////////////////////////////////////////////// +GSL_API gsl_devhandle_t gsl_device_open(gsl_deviceid_t device_id, gsl_flags_t flags); +GSL_API int gsl_device_close(gsl_devhandle_t devhandle); +GSL_API int gsl_device_idle(gsl_devhandle_t devhandle, unsigned int timeout); +GSL_API int gsl_device_getcount(void); +GSL_API int gsl_device_getinfo(gsl_devhandle_t devhandle, gsl_devinfo_t *devinfo); +GSL_API int gsl_device_setpowerstate(gsl_devhandle_t devhandle, gsl_flags_t flags); +GSL_API int gsl_device_setdmistate(gsl_devhandle_t devhandle, gsl_flags_t flags); +GSL_API int gsl_device_waitirq(gsl_devhandle_t devhandle, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout); +GSL_API int gsl_device_waittimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t timestamp, unsigned int timeout); +GSL_API int gsl_device_addtimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t *timestamp); + +////////////////////////////////////////////////////////////////////////////// +// direct register API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_register_read(gsl_devhandle_t devhandle, unsigned int offsetwords, unsigned int *data); + + +////////////////////////////////////////////////////////////////////////////// +// command API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_cp_issueibcommands(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle, gpuaddr_t ibaddr, unsigned int sizewords, gsl_timestamp_t *timestamp, gsl_flags_t flags); +GSL_API gsl_timestamp_t gsl_cp_readtimestamp(gsl_devhandle_t devhandle, gsl_timestamp_type_t type); +GSL_API int gsl_cp_checktimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t timestamp, gsl_timestamp_type_t type); +GSL_API int gsl_cp_freememontimestamp(gsl_devhandle_t devhandle, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type); +GSL_API int gsl_v3_issuecommand(gsl_devhandle_t devhandle, gsl_cmdwindow_t target, unsigned int addr, unsigned int data); + + +////////////////////////////////////////////////////////////////////////////// +// context API +////////////////////////////////////////////////////////////////////////////// +GSL_API gsl_ctxthandle_t gsl_context_create(gsl_devhandle_t devhandle, gsl_context_type_t type, gsl_flags_t flags); +GSL_API int gsl_context_destroy(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle); +GSL_API int gsl_context_bind_gmem_shadow(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id); + + + +////////////////////////////////////////////////////////////////////////////// +// sharedmem API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_memory_alloc(gsl_deviceid_t device_id, unsigned int sizebytes, gsl_flags_t flags, gsl_memdesc_t *memdesc); +GSL_API int gsl_memory_free(gsl_memdesc_t *memdesc); +GSL_API int gsl_memory_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int sizebytes, unsigned int offsetbytes); +GSL_API int gsl_memory_write(const gsl_memdesc_t *memdesc, void *src, unsigned int sizebytes, unsigned int offsetbytes); +GSL_API int gsl_memory_write_multiple(const gsl_memdesc_t *memdesc, void *src, unsigned int srcstridebytes, unsigned int dststridebytes, unsigned int blocksizebytes, unsigned int numblocks, unsigned int offsetbytes); +GSL_API unsigned int gsl_memory_getlargestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags); +GSL_API int gsl_memory_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes); +GSL_API int gsl_memory_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation); +GSL_API int gsl_memory_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr); + +#ifdef _DIRECT_MAPPED +GSL_API unsigned int gsl_sharedmem_gethostaddr(const gsl_memdesc_t *memdesc); +#endif // _DIRECT_MAPPED + +////////////////////////////////////////////////////////////////////////////// +// address translation API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_translate_physaddr(void* virtAddr, unsigned int* physAddr); + + +////////////////////////////////////////////////////////////////////////////// +// TB dump API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_tbdump_waitirq(); +GSL_API int gsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height); + +////////////////////////////////////////////////////////////////////////////// +// OS specific APIs - need to go into their own gsl_libapi_platform.h file +////////////////////////////////////////////////////////////////////////////// +#ifdef WM7 +GSL_API int gsl_kos_wm7_surfobjfromhbitmap(HBITMAP hbitmap, SURFOBJ *surfobj); +#endif // WM7 + + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // __GSL_LIBAPI_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h b/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h new file mode 100644 index 000000000000..891c7b645ad6 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h @@ -0,0 +1,157 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_PM4TYPES_H +#define __GSL_PM4TYPES_H + + +////////////////////////////////////////////////////////////////////////////// +// packet mask +////////////////////////////////////////////////////////////////////////////// +#define PM4_PKT_MASK 0xc0000000 + + +////////////////////////////////////////////////////////////////////////////// +// packet types +////////////////////////////////////////////////////////////////////////////// +#define PM4_TYPE0_PKT ((unsigned int)0 << 30) +#define PM4_TYPE1_PKT ((unsigned int)1 << 30) +#define PM4_TYPE2_PKT ((unsigned int)2 << 30) +#define PM4_TYPE3_PKT ((unsigned int)3 << 30) + + +////////////////////////////////////////////////////////////////////////////// +// type3 packets +////////////////////////////////////////////////////////////////////////////// +#define PM4_ME_INIT 0x48 // initialize CP's micro-engine + +#define PM4_NOP 0x10 // skip N 32-bit words to get to the next packet + +#define PM4_INDIRECT_BUFFER 0x3f // indirect buffer dispatch. prefetch parser uses this packet type to determine whether to pre-fetch the IB +#define PM4_INDIRECT_BUFFER_PFD 0x37 // indirect buffer dispatch. same as IB, but init is pipelined + +#define PM4_WAIT_FOR_IDLE 0x26 // wait for the IDLE state of the engine +#define PM4_WAIT_REG_MEM 0x3c // wait until a register or memory location is a specific value +#define PM4_WAIT_REG_EQ 0x52 // wait until a register location is equal to a specific value +#define PM4_WAT_REG_GTE 0x53 // wait until a register location is >= a specific value +#define PM4_WAIT_UNTIL_READ 0x5c // wait until a read completes +#define PM4_WAIT_IB_PFD_COMPLETE 0x5d // wait until all base/size writes from an IB_PFD packet have completed + +#define PM4_REG_RMW 0x21 // register read/modify/write +#define PM4_REG_TO_MEM 0x3e // reads register in chip and writes to memory +#define PM4_MEM_WRITE 0x3d // write N 32-bit words to memory +#define PM4_MEM_WRITE_CNTR 0x4f // write CP_PROG_COUNTER value to memory +#define PM4_COND_EXEC 0x44 // conditional execution of a sequence of packets +#define PM4_COND_WRITE 0x45 // conditional write to memory or register + +#define PM4_EVENT_WRITE 0x46 // generate an event that creates a write to memory when completed +#define PM4_EVENT_WRITE_SHD 0x58 // generate a VS|PS_done event +#define PM4_EVENT_WRITE_CFL 0x59 // generate a cache flush done event +#define PM4_EVENT_WRITE_ZPD 0x5b // generate a z_pass done event + +#define PM4_DRAW_INDX 0x22 // initiate fetch of index buffer and draw +#define PM4_DRAW_INDX_2 0x36 // draw using supplied indices in packet +#define PM4_DRAW_INDX_BIN 0x34 // initiate fetch of index buffer and binIDs and draw +#define PM4_DRAW_INDX_2_BIN 0x35 // initiate fetch of bin IDs and draw using supplied indices + +#define PM4_VIZ_QUERY 0x23 // begin/end initiator for viz query extent processing +#define PM4_SET_STATE 0x25 // fetch state sub-blocks and initiate shader code DMAs +#define PM4_SET_CONSTANT 0x2d // load constant into chip and to memory +#define PM4_IM_LOAD 0x27 // load sequencer instruction memory (pointer-based) +#define PM4_IM_LOAD_IMMEDIATE 0x2b // load sequencer instruction memory (code embedded in packet) +#define PM4_LOAD_CONSTANT_CONTEXT 0x2e // load constants from a location in memory +#define PM4_INVALIDATE_STATE 0x3b // selective invalidation of state pointers + +#define PM4_SET_SHADER_BASES 0x4A // dynamically changes shader instruction memory partition +#define PM4_SET_BIN_BASE_OFFSET 0x4B // program an offset that will added to the BIN_BASE value of the 3D_DRAW_INDX_BIN packet +#define PM4_SET_BIN_MASK 0x50 // sets the 64-bit BIN_MASK register in the PFP +#define PM4_SET_BIN_SELECT 0x51 // sets the 64-bit BIN_SELECT register in the PFP + +#define PM4_CONTEXT_UPDATE 0x5e // updates the current context, if needed +#define PM4_INTERRUPT 0x40 // generate interrupt from the command stream + +#define PM4_IM_STORE 0x2c // copy sequencer instruction memory to system memory + + +////////////////////////////////////////////////////////////////////////////// +// packet header building macros +////////////////////////////////////////////////////////////////////////////// +#define pm4_type0_packet(regindx, cnt) (PM4_TYPE0_PKT | (((cnt)-1) << 16) | ((regindx) & 0x7FFF)) +#define pm4_type0_packet_for_sameregister(regindx, cnt) (PM4_TYPE0_PKT | (((cnt)-1) << 16) | ((1 << 15) | ((regindx) & 0x7FFF)) +#define pm4_type1_packet(reg0, reg1) (PM4_TYPE1_PKT | ((reg1) << 12) | (reg0)) +#define pm4_type3_packet(opcode, cnt) (PM4_TYPE3_PKT | (((cnt)-1) << 16) | (((opcode) & 0xFF) << 8)) +#define pm4_predicated_type3_packet(opcode, cnt) (PM4_TYPE3_PKT | (((cnt)-1) << 16) | (((opcode) & 0xFF) << 8) | 0x1)) +#define pm4_nop_packet(cnt) (PM4_TYPE3_PKT | (((cnt)-1) << 16) | (PM4_NOP << 8)) + + +////////////////////////////////////////////////////////////////////////////// +// packet headers +////////////////////////////////////////////////////////////////////////////// +#define PM4_HDR_ME_INIT pm4_type3_packet(PM4_ME_INIT, 18) +#define PM4_HDR_INDIRECT_BUFFER_PFD pm4_type3_packet(PM4_INDIRECT_BUFFER_PFD, 2) +#define PM4_HDR_INDIRECT_BUFFER pm4_type3_packet(PM4_INDIRECT_BUFFER, 2) + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ----------------------- +// pm4 type0 packet header +// ----------------------- +typedef struct __pm4_type0 +{ + unsigned int base_index :15; + unsigned int one_reg_wr :1; + unsigned int count :14; + unsigned int type :2; +} pm4_type0; + +// ----------------------- +// pm4 type2 packet header +// ----------------------- +typedef struct __pm4_type2 +{ + unsigned int reserved :30; + unsigned int type :2; +} pm4_type2; + +// ----------------------- +// pm4 type3 packet header +// ----------------------- +typedef struct __pm4_type3 +{ + unsigned int predicate :1; + unsigned int reserved1 :7; + unsigned int it_opcode :7; + unsigned int reserved2 :1; + unsigned int count :14; + unsigned int type :2; +} pm4_type3; + +#endif // __GSL_PM4TYPES_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_properties.h b/drivers/mxc/amd-gpu/include/api/gsl_properties.h new file mode 100644 index 000000000000..520761fe3490 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_properties.h @@ -0,0 +1,94 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_PROPERTIES_H +#define __GSL_PROPERTIES_H + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// -------------- +// property types +// -------------- +typedef enum _gsl_property_type_t +{ + GSL_PROP_DEVICE_INFO = 0x00000001, + GSL_PROP_DEVICE_SHADOW = 0x00000002, + GSL_PROP_DEVICE_POWER = 0x00000003, + GSL_PROP_SHMEM = 0x00000004, + GSL_PROP_SHMEM_APERTURES = 0x00000005, + GSL_PROP_DEVICE_DMI = 0x00000006 +} gsl_property_type_t; + +// ----------------- +// aperture property +// ----------------- +typedef struct _gsl_apertureprop_t { + unsigned int gpuaddr; + unsigned int hostaddr; +} gsl_apertureprop_t; + +// -------------- +// shmem property +// -------------- +typedef struct _gsl_shmemprop_t { + int numapertures; + unsigned int aperture_mask; + unsigned int aperture_shift; + gsl_apertureprop_t *aperture; +} gsl_shmemprop_t; + +// ----------------------------- +// device shadow memory property +// ----------------------------- +typedef struct _gsl_shadowprop_t { + unsigned int hostaddr; + unsigned int size; + gsl_flags_t flags; +} gsl_shadowprop_t; + +// --------------------- +// device power property +// --------------------- +typedef struct _gsl_powerprop_t { + unsigned int value; + gsl_flags_t flags; +} gsl_powerprop_t; + + +// --------------------- +// device DMI property +// --------------------- +typedef struct _gsl_dmiprop_t { + unsigned int value; + gsl_flags_t flags; +} gsl_dmiprop_t; + +#endif // __GSL_PROPERTIES_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_types.h b/drivers/mxc/amd-gpu/include/api/gsl_types.h new file mode 100644 index 000000000000..310c1a9f5d00 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_types.h @@ -0,0 +1,479 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_TYPES_H +#define __GSL_TYPES_H + +#include "stddef.h" + + +////////////////////////////////////////////////////////////////////////////// +// status +////////////////////////////////////////////////////////////////////////////// +#define GSL_SUCCESS OS_SUCCESS +#define GSL_FAILURE OS_FAILURE +#define GSL_FAILURE_SYSTEMERROR OS_FAILURE_SYSTEMERROR +#define GSL_FAILURE_DEVICEERROR OS_FAILURE_DEVICEERROR +#define GSL_FAILURE_OUTOFMEM OS_FAILURE_OUTOFMEM +#define GSL_FAILURE_BADPARAM OS_FAILURE_BADPARAM +#define GSL_FAILURE_OFFSETINVALID OS_FAILURE_OFFSETINVALID +#define GSL_FAILURE_NOTSUPPORTED OS_FAILURE_NOTSUPPORTED +#define GSL_FAILURE_NOMOREAVAILABLE OS_FAILURE_NOMOREAVAILABLE +#define GSL_FAILURE_NOTINITIALIZED OS_FAILURE_NOTINITIALIZED +#define GSL_FAILURE_ALREADYINITIALIZED OS_FAILURE_ALREADYINITIALIZED +#define GSL_FAILURE_TIMEOUT OS_FAILURE_TIMEOUT + + +////////////////////////////////////////////////////////////////////////////// +// memory allocation flags +////////////////////////////////////////////////////////////////////////////// +#define GSL_MEMFLAGS_ANY 0x00000000 // dont care + +#define GSL_MEMFLAGS_CHANNELANY 0x00000000 +#define GSL_MEMFLAGS_CHANNEL1 0x00000000 +#define GSL_MEMFLAGS_CHANNEL2 0x00000001 +#define GSL_MEMFLAGS_CHANNEL3 0x00000002 +#define GSL_MEMFLAGS_CHANNEL4 0x00000003 + +#define GSL_MEMFLAGS_BANKANY 0x00000000 +#define GSL_MEMFLAGS_BANK1 0x00000010 +#define GSL_MEMFLAGS_BANK2 0x00000020 +#define GSL_MEMFLAGS_BANK3 0x00000040 +#define GSL_MEMFLAGS_BANK4 0x00000080 + +#define GSL_MEMFLAGS_DIRANY 0x00000000 +#define GSL_MEMFLAGS_DIRTOP 0x00000100 +#define GSL_MEMFLAGS_DIRBOT 0x00000200 + +#define GSL_MEMFLAGS_APERTUREANY 0x00000000 +#define GSL_MEMFLAGS_EMEM 0x00000000 +#define GSL_MEMFLAGS_CONPHYS 0x00001000 + +#define GSL_MEMFLAGS_ALIGNANY 0x00000000 // minimum alignment is 32 bytes +#define GSL_MEMFLAGS_ALIGN32 0x00000000 +#define GSL_MEMFLAGS_ALIGN64 0x00060000 +#define GSL_MEMFLAGS_ALIGN128 0x00070000 +#define GSL_MEMFLAGS_ALIGN256 0x00080000 +#define GSL_MEMFLAGS_ALIGN512 0x00090000 +#define GSL_MEMFLAGS_ALIGN1K 0x000A0000 +#define GSL_MEMFLAGS_ALIGN2K 0x000B0000 +#define GSL_MEMFLAGS_ALIGN4K 0x000C0000 +#define GSL_MEMFLAGS_ALIGN8K 0x000D0000 +#define GSL_MEMFLAGS_ALIGN16K 0x000E0000 +#define GSL_MEMFLAGS_ALIGN32K 0x000F0000 +#define GSL_MEMFLAGS_ALIGN64K 0x00100000 +#define GSL_MEMFLAGS_ALIGNPAGE GSL_MEMFLAGS_ALIGN4K + +#define GSL_MEMFLAGS_GPUREADWRITE 0x00000000 +#define GSL_MEMFLAGS_GPUREADONLY 0x01000000 +#define GSL_MEMFLAGS_GPUWRITEONLY 0x02000000 +#define GSL_MEMFLAGS_GPUNOACCESS 0x04000000 + +#define GSL_MEMFLAGS_FORCEPAGESIZE 0x40000000 +#define GSL_MEMFLAGS_STRICTREQUEST 0x80000000 // fail the alloc if the flags cannot be honored + +#define GSL_MEMFLAGS_CHANNEL_MASK 0x0000000F +#define GSL_MEMFLAGS_BANK_MASK 0x000000F0 +#define GSL_MEMFLAGS_DIR_MASK 0x00000F00 +#define GSL_MEMFLAGS_APERTURE_MASK 0x0000F000 +#define GSL_MEMFLAGS_ALIGN_MASK 0x00FF0000 +#define GSL_MEMFLAGS_GPUAP_MASK 0x0F000000 + +#define GSL_MEMFLAGS_CHANNEL_SHIFT 0 +#define GSL_MEMFLAGS_BANK_SHIFT 4 +#define GSL_MEMFLAGS_DIR_SHIFT 8 +#define GSL_MEMFLAGS_APERTURE_SHIFT 12 +#define GSL_MEMFLAGS_ALIGN_SHIFT 16 +#define GSL_MEMFLAGS_GPUAP_SHIFT 24 + + +////////////////////////////////////////////////////////////////////////////// +// debug flags +////////////////////////////////////////////////////////////////////////////// +#define GSL_DBGFLAGS_ALL 0xFFFFFFFF +#define GSL_DBGFLAGS_DEVICE 0x00000001 +#define GSL_DBGFLAGS_CTXT 0x00000002 +#define GSL_DBGFLAGS_MEMMGR 0x00000004 +#define GSL_DBGFLAGS_MMU 0x00000008 +#define GSL_DBGFLAGS_POWER 0x00000010 +#define GSL_DBGFLAGS_IRQ 0x00000020 +#define GSL_DBGFLAGS_BIST 0x00000040 +#define GSL_DBGFLAGS_PM4 0x00000080 +#define GSL_DBGFLAGS_PM4MEM 0x00000100 +#define GSL_DBGFLAGS_PM4CHECK 0x00000200 +#define GSL_DBGFLAGS_DUMPX 0x00000400 +#define GSL_DBGFLAGS_DUMPX_WITHOUT_IFH 0x00000800 +#define GSL_DBGFLAGS_IFH 0x00001000 +#define GSL_DBGFLAGS_NULL 0x00002000 + + +////////////////////////////////////////////////////////////////////////////// +// generic flag values +////////////////////////////////////////////////////////////////////////////// +#define GSL_FLAGS_NORMALMODE 0x00000000 +#define GSL_FLAGS_SAFEMODE 0x00000001 +#define GSL_FLAGS_INITIALIZED0 0x00000002 +#define GSL_FLAGS_INITIALIZED 0x00000004 +#define GSL_FLAGS_STARTED 0x00000008 +#define GSL_FLAGS_ACTIVE 0x00000010 +#define GSL_FLAGS_RESERVED0 0x00000020 +#define GSL_FLAGS_RESERVED1 0x00000040 +#define GSL_FLAGS_RESERVED2 0x00000080 + + +////////////////////////////////////////////////////////////////////////////// +// power flags +////////////////////////////////////////////////////////////////////////////// +#define GSL_PWRFLAGS_POWER_OFF 0x00000001 +#define GSL_PWRFLAGS_POWER_ON 0x00000002 +#define GSL_PWRFLAGS_CLK_ON 0x00000004 +#define GSL_PWRFLAGS_CLK_OFF 0x00000008 +#define GSL_PWRFLAGS_OVERRIDE_ON 0x00000010 +#define GSL_PWRFLAGS_OVERRIDE_OFF 0x00000020 + +////////////////////////////////////////////////////////////////////////////// +// DMI flags +////////////////////////////////////////////////////////////////////////////// +#define GSL_DMIFLAGS_ENABLE_SINGLE 0x00000001 // Single buffered DMI +#define GSL_DMIFLAGS_ENABLE_DOUBLE 0x00000002 // Double buffered DMI +#define GSL_DMIFLAGS_ENABLE_TRIPLE 0x00000004 // Triple buffered DMI +#define GSL_DMIFLAGS_DISABLE 0x00000008 +#define GSL_DMIFLAGS_NEXT_BUFFER 0x00000010 + +////////////////////////////////////////////////////////////////////////////// +// cache flags +////////////////////////////////////////////////////////////////////////////// +#define GSL_CACHEFLAGS_CLEAN 0x00000001 /* flush cache */ +#define GSL_CACHEFLAGS_INVALIDATE 0x00000002 /* invalidate cache */ +#define GSL_CACHEFLAGS_WRITECLEAN 0x00000004 /* flush write cache */ + + +////////////////////////////////////////////////////////////////////////////// +// context +////////////////////////////////////////////////////////////////////////////// +#define GSL_CONTEXT_MAX 20 +#define GSL_CONTEXT_NONE 0 +#define GSL_CONTEXT_SAVE_GMEM 1 +#define GSL_CONTEXT_NO_GMEM_ALLOC 2 + + +////////////////////////////////////////////////////////////////////////////// +// other +////////////////////////////////////////////////////////////////////////////// +#define GSL_TIMEOUT_NONE 0 +#define GSL_TIMEOUT_DEFAULT 0xFFFFFFFF + +#ifdef _LINUX +#define GSL_PAGESIZE PAGE_SIZE +#define GSL_PAGESIZE_SHIFT PAGE_SHIFT +#else +#define GSL_PAGESIZE 0x1000 +#define GSL_PAGESIZE_SHIFT 12 +#endif + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// +typedef unsigned int gsl_devhandle_t; +typedef unsigned int gsl_ctxthandle_t; +typedef int gsl_timestamp_t; +typedef unsigned int gsl_flags_t; +typedef unsigned int gpuaddr_t; + +// --------- +// device id +// --------- +typedef enum _gsl_deviceid_t +{ + GSL_DEVICE_ANY = 0, + GSL_DEVICE_YAMATO = 1, + GSL_DEVICE_G12 = 2, + GSL_DEVICE_MAX = 2, + + GSL_DEVICE_FOOBAR = 0x7FFFFFFF +} gsl_deviceid_t; + +// ---------------- +// chip revision id +// ---------------- +// +// coreid:8 majorrev:8 minorrev:8 patch:8 +// +// coreid = 0x00 = YAMATO_DX +// coreid = 0x80 = G12 +// + +#define COREID(x) ((((unsigned int)x & 0xFF) << 24)) +#define MAJORID(x) ((((unsigned int)x & 0xFF) << 16)) +#define MINORID(x) ((((unsigned int)x & 0xFF) << 8)) +#define PATCHID(x) ((((unsigned int)x & 0xFF) << 0)) + +typedef enum _gsl_chipid_t +{ + GSL_CHIPID_YAMATODX_REV13 = (COREID(0x00) | MAJORID(0x01) | MINORID(0x03) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV14 = (COREID(0x00) | MAJORID(0x01) | MINORID(0x04) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV20 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x00) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV21 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x01) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV211 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x01) | PATCHID(0x01)), + GSL_CHIPID_YAMATODX_REV22 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x02) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV23 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x03) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV231 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x03) | PATCHID(0x01)), + GSL_CHIPID_YAMATODX_REV24 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x04) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV25 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x05) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV251 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x05) | PATCHID(0x01)), + GSL_CHIPID_G12_REV00 = (int)(COREID(0x80) | MAJORID(0x00) | MINORID(0x00) | PATCHID(0x00)), + GSL_CHIPID_ERROR = (int)0xFFFFFFFF + +} gsl_chipid_t; + +#undef COREID +#undef MAJORID +#undef MINORID +#undef PATCHID + +// ----------- +// device info +// ----------- +typedef struct _gsl_devinfo_t { + + gsl_deviceid_t device_id; // ID of this device + gsl_chipid_t chip_id; + int mmu_enabled; // mmu address translation enabled + unsigned int gmem_gpubaseaddr; + void * gmem_hostbaseaddr; // if gmem_hostbaseaddr is NULL, we would know its not mapped into mmio space + unsigned int gmem_sizebytes; + unsigned int high_precision; /* mx50 z160 has higher gradient/texture precision */ + +} gsl_devinfo_t; + +// ------------------- +// device memory store +// ------------------- +typedef struct _gsl_devmemstore_t { + volatile unsigned int soptimestamp; + unsigned int sbz; + volatile unsigned int eoptimestamp; + unsigned int sbz2; +} gsl_devmemstore_t; + +#define GSL_DEVICE_MEMSTORE_OFFSET(field) offsetof(gsl_devmemstore_t, field) + +// ----------- +// aperture id +// ----------- +typedef enum _gsl_apertureid_t +{ + GSL_APERTURE_EMEM = (GSL_MEMFLAGS_EMEM), + GSL_APERTURE_PHYS = (GSL_MEMFLAGS_CONPHYS >> GSL_MEMFLAGS_APERTURE_SHIFT), + GSL_APERTURE_MMU = (GSL_APERTURE_EMEM | 0x10000000), + GSL_APERTURE_MAX = 2, + + GSL_APERTURE_FOOBAR = 0x7FFFFFFF +} gsl_apertureid_t; + +// ---------- +// channel id +// ---------- +typedef enum _gsl_channelid_t +{ + GSL_CHANNEL_1 = (GSL_MEMFLAGS_CHANNEL1 >> GSL_MEMFLAGS_CHANNEL_SHIFT), + GSL_CHANNEL_2 = (GSL_MEMFLAGS_CHANNEL2 >> GSL_MEMFLAGS_CHANNEL_SHIFT), + GSL_CHANNEL_3 = (GSL_MEMFLAGS_CHANNEL3 >> GSL_MEMFLAGS_CHANNEL_SHIFT), + GSL_CHANNEL_4 = (GSL_MEMFLAGS_CHANNEL4 >> GSL_MEMFLAGS_CHANNEL_SHIFT), + GSL_CHANNEL_MAX = 4, + + GSL_CHANNEL_FOOBAR = 0x7FFFFFFF +} gsl_channelid_t; + +// ---------------------- +// page access permission +// ---------------------- +typedef enum _gsl_ap_t +{ + GSL_AP_NULL = 0x0, + GSL_AP_R = 0x1, + GSL_AP_W = 0x2, + GSL_AP_RW = 0x3, + GSL_AP_X = 0x4, + GSL_AP_RWX = 0x5, + GSL_AP_MAX = 0x6, + + GSL_AP_FOOBAR = 0x7FFFFFFF +} gsl_ap_t; + +// ------------- +// memory region +// ------------- +typedef struct _gsl_memregion_t { + unsigned char *mmio_virt_base; + unsigned int mmio_phys_base; + gpuaddr_t gpu_base; + unsigned int sizebytes; +} gsl_memregion_t; + +// ------------------------ +// shared memory allocation +// ------------------------ +typedef struct _gsl_memdesc_t { + void *hostptr; + gpuaddr_t gpuaddr; + int size; + unsigned int priv; // private + unsigned int priv2; // private + +} gsl_memdesc_t; + +// --------------------------------- +// physical page scatter/gatter list +// --------------------------------- +typedef struct _gsl_scatterlist_t { + int contiguous; // flag whether pages on the list are physically contiguous + unsigned int num; + unsigned int *pages; +} gsl_scatterlist_t; + +// -------------- +// mem free queue +// -------------- +// +// this could be compressed down into the just the memdesc for the node +// +typedef struct _gsl_memnode_t { + gsl_timestamp_t timestamp; + gsl_memdesc_t memdesc; + unsigned int pid; + struct _gsl_memnode_t *next; +} gsl_memnode_t; + +typedef struct _gsl_memqueue_t { + gsl_memnode_t *head; + gsl_memnode_t *tail; +} gsl_memqueue_t; + +// ------------ +// timestamp id +// ------------ +typedef enum _gsl_timestamp_type_t +{ + GSL_TIMESTAMP_CONSUMED = 1, // start-of-pipeline timestamp + GSL_TIMESTAMP_RETIRED = 2, // end-of-pipeline timestamp + GSL_TIMESTAMP_MAX = 2, + + GSL_TIMESTAMP_FOOBAR = 0x7FFFFFFF +} gsl_timestamp_type_t; + +// ------------ +// context type +// ------------ +typedef enum _gsl_context_type_t +{ + GSL_CONTEXT_TYPE_GENERIC = 1, + GSL_CONTEXT_TYPE_OPENGL = 2, + GSL_CONTEXT_TYPE_OPENVG = 3, + + GSL_CONTEXT_TYPE_FOOBAR = 0x7FFFFFFF +} gsl_context_type_t; + +// --------- +// rectangle +// --------- +typedef struct _gsl_rect_t { + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; +} gsl_rect_t; + +// ----------------------- +// pixel buffer descriptor +// ----------------------- +typedef struct _gsl_buffer_desc_t { + gsl_memdesc_t data; + unsigned int stride_bytes; + unsigned int bpp; + unsigned int enabled; +} gsl_buffer_desc_t; + +// --------------------- +// command window target +// --------------------- +typedef enum _gsl_cmdwindow_t +{ + GSL_CMDWINDOW_MIN = 0x00000000, + GSL_CMDWINDOW_2D = 0x00000000, + GSL_CMDWINDOW_3D = 0x00000001, // legacy + GSL_CMDWINDOW_MMU = 0x00000002, + GSL_CMDWINDOW_ARBITER = 0x000000FF, + GSL_CMDWINDOW_MAX = 0x000000FF, + + GSL_CMDWINDOW_FOOBAR = 0x7FFFFFFF +} gsl_cmdwindow_t; + +// ------------ +// interrupt id +// ------------ +typedef enum _gsl_intrid_t +{ + GSL_INTR_YDX_MH_AXI_READ_ERROR = 0, + GSL_INTR_YDX_MH_AXI_WRITE_ERROR, + GSL_INTR_YDX_MH_MMU_PAGE_FAULT, + + GSL_INTR_YDX_CP_SW_INT, + GSL_INTR_YDX_CP_T0_PACKET_IN_IB, + GSL_INTR_YDX_CP_OPCODE_ERROR, + GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR, + GSL_INTR_YDX_CP_RESERVED_BIT_ERROR, + GSL_INTR_YDX_CP_IB_ERROR, + GSL_INTR_YDX_CP_IB2_INT, + GSL_INTR_YDX_CP_IB1_INT, + GSL_INTR_YDX_CP_RING_BUFFER, + + GSL_INTR_YDX_RBBM_READ_ERROR, + GSL_INTR_YDX_RBBM_DISPLAY_UPDATE, + GSL_INTR_YDX_RBBM_GUI_IDLE, + + GSL_INTR_YDX_SQ_PS_WATCHDOG, + GSL_INTR_YDX_SQ_VS_WATCHDOG, + + GSL_INTR_G12_MH, + GSL_INTR_G12_G2D, + GSL_INTR_G12_FIFO, +#ifndef _Z180 + GSL_INTR_G12_FBC, +#endif // _Z180 + + GSL_INTR_G12_MH_AXI_READ_ERROR, + GSL_INTR_G12_MH_AXI_WRITE_ERROR, + GSL_INTR_G12_MH_MMU_PAGE_FAULT, + + GSL_INTR_COUNT, + + GSL_INTR_FOOBAR = 0x7FFFFFFF +} gsl_intrid_t; + +#endif // __GSL_TYPES_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_utils.h b/drivers/mxc/amd-gpu/include/api/gsl_utils.h new file mode 100644 index 000000000000..1078b634173d --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_utils.h @@ -0,0 +1,43 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_UTILS_H +#define __GSL_UTILS_H + + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define GSL_QUADPOW2_TO_SIZEBYTES(quadpow2) (8 << (quadpow2)) +#define GSL_QUADPOW2_TO_SIZEDWORDS(quadpow2) (2 << (quadpow2)) +#define GSL_POW2TEST(size) ((size) && !((size) & ((size) - 1))) +#define GSL_POW2ALIGN_DOWN(addr, alignsize) ((addr) & ~((alignsize) - 1)); +#define GSL_POW2ALIGN_UP(addr, alignsize) (((addr) + ((alignsize) - 1)) & ~((alignsize) - 1)) + + +#endif // __GSL_UTILS_H diff --git a/drivers/mxc/amd-gpu/include/gsl.h b/drivers/mxc/amd-gpu/include/gsl.h new file mode 100644 index 000000000000..07d8e97dcee3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl.h @@ -0,0 +1,79 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_H +#define __GSL_H + +//#define __KGSLLIB_EXPORTS +#define __KERNEL_MODE__ + + +////////////////////////////////////////////////////////////////////////////// +// forward typedefs +////////////////////////////////////////////////////////////////////////////// +//struct _gsl_device_t; +typedef struct _gsl_device_t gsl_device_t; + + +////////////////////////////////////////////////////////////////////////////// +// includes +////////////////////////////////////////////////////////////////////////////// +#include "gsl_buildconfig.h" + +#include "kos_libapi.h" + +#include "gsl_klibapi.h" + +#ifdef GSL_BLD_YAMATO +#include + +#include "gsl_pm4types.h" +#include "gsl_utils.h" +#include "gsl_drawctxt.h" +#include "gsl_ringbuffer.h" +#endif + +#ifdef GSL_BLD_G12 +#include + +#include "gsl_cmdwindow.h" +#endif + +#include "gsl_debug.h" +#include "gsl_mmu.h" +#include "gsl_memmgr.h" +#include "gsl_sharedmem.h" +#include "gsl_intrmgr.h" +#include "gsl_cmdstream.h" +#include "gsl_device.h" +#include "gsl_driver.h" +#include "gsl_log.h" + +#include "gsl_config.h" + +#endif // __GSL_H diff --git a/drivers/mxc/amd-gpu/include/gsl_buildconfig.h b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h new file mode 100644 index 000000000000..01ba14e4cb66 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h @@ -0,0 +1,55 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __GSL__BUILDCONFIG_H +#define __GSL__BUILDCONFIG_H + +#define GSL_BLD_YAMATO +#define GSL_BLD_G12 + +#define GSL_LOCKING_COURSEGRAIN + +#define GSL_STATS_MEM +#define GSL_STATS_RINGBUFFER +#define GSL_STATS_MMU + +#define GSL_RB_USE_MEM_RPTR +#define GSL_RB_USE_MEM_TIMESTAMP +#define GSL_RB_TIMESTAMP_INTERUPT +/* #define GSL_RB_USE_WPTR_POLLING */ + +/* #define GSL_MMU_PAGETABLE_PERPROCESS */ + +#define GSL_CALLER_PROCESS_MAX 10 +#define GSL_SHMEM_MAX_APERTURES 3 + +#endif /* __GSL__BUILDCONFIG_H */ diff --git a/drivers/mxc/amd-gpu/include/gsl_cmdstream.h b/drivers/mxc/amd-gpu/include/gsl_cmdstream.h new file mode 100644 index 000000000000..550d5d0005ab --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_cmdstream.h @@ -0,0 +1,62 @@ +/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_CMDSTREAM_H +#define __GSL_CMDSTREAM_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// + +#ifdef VG_HDK +#define GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data) +#else +#define GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data) kgsl_sharedmem_read0(&device->memstore, (data), GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp), 4, false) +#endif + +#ifdef VG_HDK +#define GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, data) (*((int*)data) = (gsl_driver.device[GSL_DEVICE_G12-1]).timestamp) +#else +#define GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, data) kgsl_sharedmem_read0(&device->memstore, (data), GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), 4, false) +#endif + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// +gsl_timestamp_t kgsl_cmdstream_readtimestamp0(gsl_deviceid_t device_id, gsl_timestamp_type_t type); +void kgsl_cmdstream_memqueue_drain(gsl_device_t *device); +int kgsl_cmdstream_init(gsl_device_t *device); +int kgsl_cmdstream_close(gsl_device_t *device); + +#endif // __GSL_CMDSTREAM_H diff --git a/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h b/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h new file mode 100644 index 000000000000..0152dd75a631 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h @@ -0,0 +1,51 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_CMDWINDOW_H +#define __GSL_CMDWINDOW_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#ifndef _Z180 +#define GSL_G12_INTR_COUNT 4 +#else +#define GSL_G12_INTR_COUNT 3 +#endif + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_cmdwindow_init(gsl_device_t *device); +int kgsl_cmdwindow_close(gsl_device_t *device); +int kgsl_cmdwindow_write0(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data); + +#endif // __GSL_CMDWINDOW_H diff --git a/drivers/mxc/amd-gpu/include/gsl_config.h b/drivers/mxc/amd-gpu/include/gsl_config.h new file mode 100644 index 000000000000..aa911b4096a3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_config.h @@ -0,0 +1,221 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __GSL__CONFIG_H +#define __GSL__CONFIG_H + +/* ------------------------ + * Yamato ringbuffer config + * ------------------------ */ +static const unsigned int gsl_cfg_rb_sizelog2quadwords = GSL_RB_SIZE_32K; +static const unsigned int gsl_cfg_rb_blksizequadwords = GSL_RB_SIZE_16; + +/* ------------------------ + * Yamato MH arbiter config + * ------------------------ */ +static const mh_arbiter_config_t gsl_cfg_yamato_mharb = { + 0x10, /* same_page_limit */ + 0, /* same_page_granularity */ + 1, /* l1_arb_enable */ + 1, /* l1_arb_hold_enable */ + 0, /* l2_arb_control */ + 1, /* page_size */ + 1, /* tc_reorder_enable */ + 1, /* tc_arb_hold_enable */ + 1, /* in_flight_limit_enable */ + 0x8, /* in_flight_limit */ + 1, /* cp_clnt_enable */ + 1, /* vgt_clnt_enable */ + 1, /* tc_clnt_enable */ + 1, /* rb_clnt_enable */ + 1, /* pa_clnt_enable */ +}; + +/* --------------------- + * G12 MH arbiter config + * --------------------- */ +static const REG_MH_ARBITER_CONFIG gsl_cfg_g12_mharb = { + 0x10, /* SAME_PAGE_LIMIT */ + 0, /* SAME_PAGE_GRANULARITY */ + 1, /* L1_ARB_ENABLE */ + 1, /* L1_ARB_HOLD_ENABLE */ + 0, /* L2_ARB_CONTROL */ + 1, /* PAGE_SIZE */ + 1, /* TC_REORDER_ENABLE */ + 1, /* TC_ARB_HOLD_ENABLE */ + 0, /* IN_FLIGHT_LIMIT_ENABLE */ + 0x8, /* IN_FLIGHT_LIMIT */ + 1, /* CP_CLNT_ENABLE */ + 1, /* VGT_CLNT_ENABLE */ + 1, /* TC_CLNT_ENABLE */ + 1, /* RB_CLNT_ENABLE */ + 1, /* PA_CLNT_ENABLE */ +}; + +/* ----------------------------- + * interrupt block register data + * ----------------------------- */ +static const gsl_intrblock_reg_t gsl_cfg_intrblock_reg[GSL_INTR_BLOCK_COUNT] = { + { /* Yamato MH */ + GSL_INTR_BLOCK_YDX_MH, + GSL_INTR_YDX_MH_AXI_READ_ERROR, + GSL_INTR_YDX_MH_MMU_PAGE_FAULT, + mmMH_INTERRUPT_STATUS, + mmMH_INTERRUPT_CLEAR, + mmMH_INTERRUPT_MASK + }, + { /* Yamato CP */ + GSL_INTR_BLOCK_YDX_CP, + GSL_INTR_YDX_CP_SW_INT, + GSL_INTR_YDX_CP_RING_BUFFER, + mmCP_INT_STATUS, + mmCP_INT_ACK, + mmCP_INT_CNTL + }, + { /* Yamato RBBM */ + GSL_INTR_BLOCK_YDX_RBBM, + GSL_INTR_YDX_RBBM_READ_ERROR, + GSL_INTR_YDX_RBBM_GUI_IDLE, + mmRBBM_INT_STATUS, + mmRBBM_INT_ACK, + mmRBBM_INT_CNTL + }, + { /* Yamato SQ */ + GSL_INTR_BLOCK_YDX_SQ, + GSL_INTR_YDX_SQ_PS_WATCHDOG, + GSL_INTR_YDX_SQ_VS_WATCHDOG, + mmSQ_INT_STATUS, + mmSQ_INT_ACK, + mmSQ_INT_CNTL + }, + { /* G12 */ + GSL_INTR_BLOCK_G12, + GSL_INTR_G12_MH, +#ifndef _Z180 + GSL_INTR_G12_FBC, +#else + GSL_INTR_G12_FIFO, +#endif /* _Z180 */ + (ADDR_VGC_IRQSTATUS >> 2), + (ADDR_VGC_IRQSTATUS >> 2), + (ADDR_VGC_IRQENABLE >> 2) + }, + { /* G12 MH */ + GSL_INTR_BLOCK_G12_MH, + GSL_INTR_G12_MH_AXI_READ_ERROR, + GSL_INTR_G12_MH_MMU_PAGE_FAULT, + ADDR_MH_INTERRUPT_STATUS, /* G12 MH offsets are considered to be dword based, therefore no down shift */ + ADDR_MH_INTERRUPT_CLEAR, + ADDR_MH_INTERRUPT_MASK + }, +}; + +/* ----------------------- + * interrupt mask bit data + * ----------------------- */ +static const int gsl_cfg_intr_mask[GSL_INTR_COUNT] = { + MH_INTERRUPT_MASK__AXI_READ_ERROR, + MH_INTERRUPT_MASK__AXI_WRITE_ERROR, + MH_INTERRUPT_MASK__MMU_PAGE_FAULT, + + CP_INT_CNTL__SW_INT_MASK, + CP_INT_CNTL__T0_PACKET_IN_IB_MASK, + CP_INT_CNTL__OPCODE_ERROR_MASK, + CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK, + CP_INT_CNTL__RESERVED_BIT_ERROR_MASK, + CP_INT_CNTL__IB_ERROR_MASK, + CP_INT_CNTL__IB2_INT_MASK, + CP_INT_CNTL__IB1_INT_MASK, + CP_INT_CNTL__RB_INT_MASK, + + RBBM_INT_CNTL__RDERR_INT_MASK, + RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK, + RBBM_INT_CNTL__GUI_IDLE_INT_MASK, + + SQ_INT_CNTL__PS_WATCHDOG_MASK, + SQ_INT_CNTL__VS_WATCHDOG_MASK, + + (1 << VGC_IRQENABLE_MH_FSHIFT), + (1 << VGC_IRQENABLE_G2D_FSHIFT), + (1 << VGC_IRQENABLE_FIFO_FSHIFT), +#ifndef _Z180 + (1 << VGC_IRQENABLE_FBC_FSHIFT), +#endif + (1 << MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT), + (1 << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT), + (1 << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT), +}; + +/* ----------------- + * mmu register data + * ----------------- */ +static const gsl_mmu_reg_t gsl_cfg_mmu_reg[GSL_DEVICE_MAX] = { + { /* Yamato */ + mmMH_MMU_CONFIG, + mmMH_MMU_MPU_BASE, + mmMH_MMU_MPU_END, + mmMH_MMU_VA_RANGE, + mmMH_MMU_PT_BASE, + mmMH_MMU_PAGE_FAULT, + mmMH_MMU_TRAN_ERROR, + mmMH_MMU_INVALIDATE, + }, + { /* G12 - MH offsets are considered to be dword based, therefore no down shift */ + ADDR_MH_MMU_CONFIG, + ADDR_MH_MMU_MPU_BASE, + ADDR_MH_MMU_MPU_END, + ADDR_MH_MMU_VA_RANGE, + ADDR_MH_MMU_PT_BASE, + ADDR_MH_MMU_PAGE_FAULT, + ADDR_MH_MMU_TRAN_ERROR, + ADDR_MH_MMU_INVALIDATE, + }, +}; + +/* ----------------- + * mh interrupt data + * ----------------- */ +static const gsl_mh_intr_t gsl_cfg_mh_intr[GSL_DEVICE_MAX] = +{ + { /* Yamato */ + GSL_INTR_YDX_MH_AXI_READ_ERROR, + GSL_INTR_YDX_MH_AXI_WRITE_ERROR, + GSL_INTR_YDX_MH_MMU_PAGE_FAULT, + }, + { /* G12 */ + GSL_INTR_G12_MH_AXI_READ_ERROR, + GSL_INTR_G12_MH_AXI_WRITE_ERROR, + GSL_INTR_G12_MH_MMU_PAGE_FAULT, + } +}; + +#endif /* __GSL__CONFIG_H */ diff --git a/drivers/mxc/amd-gpu/include/gsl_context.h b/drivers/mxc/amd-gpu/include/gsl_context.h new file mode 100644 index 000000000000..6e83bdb34036 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_context.h @@ -0,0 +1,45 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_CONTEXT_H +#define __GSL_CONTEXT_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +#endif // __GSL_CONTEXT_H diff --git a/drivers/mxc/amd-gpu/include/gsl_debug.h b/drivers/mxc/amd-gpu/include/gsl_debug.h new file mode 100644 index 000000000000..1275278f9eae --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_debug.h @@ -0,0 +1,126 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DEBUG_H +#define __GSL_DEBUG_H + +#ifdef BB_DUMPX +#include "dumpx.h" +#endif + +#ifdef TBDUMP +#include "gsl_tbdump.h" +#endif + + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#ifdef _DEBUG +#define KGSL_DEBUG(flag, action) if (gsl_driver.flags_debug & flag) {action;} +#ifdef GSL_BLD_YAMATO +#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords) Yamato_DumpPM4((cmds), (sizedwords)) +#define KGSL_DEBUG_DUMPREGWRITE(addr, value) Yamato_DumpRegisterWrite((addr), (value)) +#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data) Yamato_DumpWriteMemory(addr, sizebytes, data) +#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value) Yamato_DumpSetMemory(addr, sizebytes, value) +#define KGSL_DEBUG_DUMPFBSTART(device) Yamato_DumpFbStart(device) +#define KGSL_DEBUG_DUMPREGSPACE(device) Yamato_DumpRegSpace(device) +#define KGSL_DEBUG_DUMPWINDOW(addr, width, height) Yamato_DumpWindow(addr, width, height) +#else +#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords) +#define KGSL_DEBUG_DUMPREGWRITE(addr, value) +#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data) +#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value) +#define KGSL_DEBUG_DUMPFBSTART(device) +#define KGSL_DEBUG_DUMPREGSPACE(device) +#define KGSL_DEBUG_DUMPWINDOW(addr, width, height) +#endif +#ifdef TBDUMP + +#define KGSL_DEBUG_TBDUMP_OPEN(filename) tbdump_open(filename) +#define KGSL_DEBUG_TBDUMP_CLOSE() tbdump_close() +#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes) tbdump_syncmem((unsigned int)addr, (unsigned int)src, sizebytes) +#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes) tbdump_setmem((unsigned int)addr, value, sizebytes) +#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value) tbdump_slavewrite(addr, value) +#define KGSL_DEBUG_TBDUMP_WAITIRQ() tbdump_waitirq() + +#else +#define KGSL_DEBUG_TBDUMP_OPEN(file) +#define KGSL_DEBUG_TBDUMP_CLOSE() +#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes) +#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes) +#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value) +#define KGSL_DEBUG_TBDUMP_WAITIRQ() +#endif +#ifdef BB_DUMPX +#define KGSL_DEBUG_DUMPX_OPEN(filename, param) dumpx_open((filename), (param)) +#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment) dumpx(cmd, (par1), (par2), (par3), (comment)) +#define KGSL_DEBUG_DUMPX_CLOSE() dumpx_close() +#else +#define KGSL_DEBUG_DUMPX_OPEN(filename, param) +#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment) +#define KGSL_DEBUG_DUMPX_CLOSE() +#endif +#else +#define KGSL_DEBUG(flag, action) +#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords) +#define KGSL_DEBUG_DUMPREGWRITE(addr, value) +#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data) +#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value) +#define KGSL_DEBUG_DUMPFBSTART(device) +#define KGSL_DEBUG_DUMPREGSPACE(device) +#define KGSL_DEBUG_DUMPWINDOW(addr, width, height) +#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment) + +#define KGSL_DEBUG_TBDUMP_OPEN(file) +#define KGSL_DEBUG_TBDUMP_CLOSE() +#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes) +#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes) +#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value) +#define KGSL_DEBUG_TBDUMP_WAITIRQ() +#endif // _DEBUG + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +#ifdef GSL_BLD_YAMATO +void Yamato_DumpPM4(unsigned int *cmds, unsigned int sizedwords); +void Yamato_DumpRegisterWrite(unsigned int dwAddress, unsigned int value); +void Yamato_DumpWriteMemory(unsigned int dwAddress, unsigned int dwSize, void* pData); +void Yamato_DumpSetMemory(unsigned int dwAddress, unsigned int dwSize, unsigned int pData); +void Yamato_DumpFbStart(gsl_device_t *device); +void Yamato_DumpRegSpace(gsl_device_t *device); +#ifdef _WIN32 +void Yamato_DumpWindow(unsigned int addr, unsigned int width, unsigned int height); +#endif +#endif +#ifdef _DEBUG +int kgsl_dumpx_parse_ibs(gpuaddr_t gpuaddr, int sizedwords); +#endif //_DEBUG +#endif // __GSL_DRIVER_H diff --git a/drivers/mxc/amd-gpu/include/gsl_device.h b/drivers/mxc/amd-gpu/include/gsl_device.h new file mode 100644 index 000000000000..433dc6963dfd --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_device.h @@ -0,0 +1,142 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DEVICE_H +#define __GSL_DEVICE_H + +#ifdef _LINUX +#include +#include +#endif + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// -------------- +// function table +// -------------- +typedef struct _gsl_functable_t { + int (*device_init) (gsl_device_t *device); + int (*device_close) (gsl_device_t *device); + int (*device_destroy) (gsl_device_t *device); + int (*device_start) (gsl_device_t *device, gsl_flags_t flags); + int (*device_stop) (gsl_device_t *device); + int (*device_getproperty) (gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes); + int (*device_setproperty) (gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes); + int (*device_idle) (gsl_device_t *device, unsigned int timeout); + int (*device_regread) (gsl_device_t *device, unsigned int offsetwords, unsigned int *value); + int (*device_regwrite) (gsl_device_t *device, unsigned int offsetwords, unsigned int value); + int (*device_waitirq) (gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout); + int (*device_waittimestamp) (gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout); + int (*device_runpending) (gsl_device_t *device); + int (*device_addtimestamp) (gsl_device_t *device_id, gsl_timestamp_t *timestamp); + int (*intr_isr) (gsl_device_t *device); + int (*mmu_tlbinvalidate) (gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid); + int (*mmu_setpagetable) (gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid); + int (*cmdstream_issueibcmds) (gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags); + int (*context_create) (gsl_device_t *device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags); + int (*context_destroy) (gsl_device_t *device_id, unsigned int drawctxt_id); +} gsl_functable_t; + +// ------------- +// device object +// ------------- +struct _gsl_device_t { + + unsigned int refcnt; + unsigned int callerprocess[GSL_CALLER_PROCESS_MAX]; // caller process table + gsl_functable_t ftbl; + gsl_flags_t flags; + gsl_deviceid_t id; + unsigned int chip_id; + gsl_memregion_t regspace; + gsl_intr_t intr; + gsl_memdesc_t memstore; + gsl_memqueue_t memqueue; // queue of memfrees pending timestamp elapse + +#ifdef GSL_DEVICE_SHADOW_MEMSTORE_TO_USER + unsigned int memstoreshadow[GSL_CALLER_PROCESS_MAX]; +#endif // GSL_DEVICE_SHADOW_MEMSTORE_TO_USER + +#ifndef GSL_NO_MMU + gsl_mmu_t mmu; +#endif // GSL_NO_MMU + +#ifdef GSL_BLD_YAMATO + gsl_memregion_t gmemspace; + gsl_ringbuffer_t ringbuffer; + unsigned int drawctxt_count; + gsl_drawctxt_t *drawctxt_active; + gsl_drawctxt_t drawctxt[GSL_CONTEXT_MAX]; +#endif // GSL_BLD_YAMATO + +#ifdef GSL_BLD_G12 + unsigned int intrcnt[GSL_G12_INTR_COUNT]; + gsl_timestamp_t current_timestamp; + gsl_timestamp_t timestamp; +#ifndef _LINUX + unsigned int irq_thread; + oshandle_t irq_thread_handle; +#endif +#ifdef IRQTHREAD_POLL + oshandle_t irqthread_event; +#endif +#endif // GSL_BLD_G12 +#ifndef _LINUX + oshandle_t timestamp_event; +#else + wait_queue_head_t timestamp_waitq; + struct workqueue_struct *irq_workq; + struct work_struct irq_work; +#endif + void *autogate; +}; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_device_init(gsl_device_t *device, gsl_deviceid_t device_id); +int kgsl_device_close(gsl_device_t *device); +int kgsl_device_destroy(gsl_device_t *device); +int kgsl_device_attachcallback(gsl_device_t *device, unsigned int pid); +int kgsl_device_detachcallback(gsl_device_t *device, unsigned int pid); +int kgsl_device_runpending(gsl_device_t *device); + +int kgsl_yamato_getfunctable(gsl_functable_t *ftbl); +int kgsl_g12_getfunctable(gsl_functable_t *ftbl); + +int kgsl_clock(gsl_deviceid_t dev, int enable); +int kgsl_device_active(gsl_device_t *dev); +int kgsl_device_clock(gsl_deviceid_t id, int enable); +int kgsl_device_autogate_init(gsl_device_t *dev); +void kgsl_device_autogate_exit(gsl_device_t *dev); + + +#endif // __GSL_DEVICE_H diff --git a/drivers/mxc/amd-gpu/include/gsl_display.h b/drivers/mxc/amd-gpu/include/gsl_display.h new file mode 100644 index 000000000000..82300647b3ef --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_display.h @@ -0,0 +1,62 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DISPLAY_H +#define __GSL_DISPLAY_H + +#define __GSLDISPLAY_EXPORTS + +#include "gsl_libapi.h" +#include "gsl_klibapi.h" // hack to enable direct reg write +#include "gsl_displayapi.h" + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_LIB_MAXDISPLAYS 1 +#define GSL_LIB_MAXSURFACES 3 + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// +typedef struct _gsl_display_t { + int numdisplays; + gsl_displaymode_t mode[GSL_LIB_MAXDISPLAYS]; + gsl_devhandle_t devhandle; +} gsl_display_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int gsl_display_hitachi_240x320_tft_init(int display_id); +int gsl_display_toshiba_640x480_tft_init(int display_id); + +#endif // __GSL_DISPLAY_H diff --git a/drivers/mxc/amd-gpu/include/gsl_drawctxt.h b/drivers/mxc/amd-gpu/include/gsl_drawctxt.h new file mode 100644 index 000000000000..15b8097828af --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_drawctxt.h @@ -0,0 +1,110 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DRAWCTXT_H +#define __GSL_DRAWCTXT_H + +////////////////////////////////////////////////////////////////////////////// +// Flags +////////////////////////////////////////////////////////////////////////////// + +#define CTXT_FLAGS_NOT_IN_USE 0x00000000 +#define CTXT_FLAGS_IN_USE 0x00000001 + +#define CTXT_FLAGS_STATE_SHADOW 0x00000010 // state shadow memory allocated + +#define CTXT_FLAGS_GMEM_SHADOW 0x00000100 // gmem shadow memory allocated +#define CTXT_FLAGS_GMEM_SAVE 0x00000200 // gmem must be copied to shadow +#define CTXT_FLAGS_GMEM_RESTORE 0x00000400 // gmem can be restored from shadow + +#define CTXT_FLAGS_SHADER_SAVE 0x00002000 // shader must be copied to shadow +#define CTXT_FLAGS_SHADER_RESTORE 0x00004000 // shader can be restored from shadow + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ------------ +// draw context +// ------------ + +typedef struct _gmem_shadow_t +{ + gsl_memdesc_t gmemshadow; // Shadow buffer address + + // 256 KB GMEM surface = 4 bytes-per-pixel x 256 pixels/row x 256 rows. + // width & height must be a multiples of 32, in case tiled textures are used. + unsigned int size; // Size of surface used to store GMEM + unsigned int width; // Width of surface used to store GMEM + unsigned int height; // Height of surface used to store GMEM + unsigned int pitch; // Pitch of surface used to store GMEM + int offset; + unsigned int offset_x; + unsigned int offset_y; + unsigned int gmem_offset_x; + unsigned int gmem_offset_y; + + unsigned int* gmem_save_commands; + unsigned int* gmem_restore_commands; + unsigned int gmem_save[3]; + unsigned int gmem_restore[3]; + + gsl_memdesc_t quad_vertices; + gsl_memdesc_t quad_texcoords; +} gmem_shadow_t; + +#define GSL_MAX_GMEM_SHADOW_BUFFERS 2 + +typedef struct _gsl_drawctxt_t { + unsigned int pid; + gsl_flags_t flags; + gsl_context_type_t type; + gsl_memdesc_t gpustate; + + unsigned int reg_save[3]; + unsigned int reg_restore[3]; + unsigned int shader_save[3]; + unsigned int shader_fixup[3]; + unsigned int shader_restore[3]; + unsigned int chicken_restore[3]; + gmem_shadow_t context_gmem_shadow; // Information of the GMEM shadow that is created in context create + gmem_shadow_t user_gmem_shadow[GSL_MAX_GMEM_SHADOW_BUFFERS]; // User defined GMEM shadow buffers +} gsl_drawctxt_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_drawctxt_init(gsl_device_t *device); +int kgsl_drawctxt_close(gsl_device_t *device); +int kgsl_drawctxt_destroyall(gsl_device_t *device); +void kgsl_drawctxt_switch(gsl_device_t *device, gsl_drawctxt_t *drawctxt, gsl_flags_t flags); +int kgsl_drawctxt_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags); +int kgsl_drawctxt_destroy(gsl_device_t* device, unsigned int drawctxt_id); + +#endif // __GSL_DRAWCTXT_H diff --git a/drivers/mxc/amd-gpu/include/gsl_driver.h b/drivers/mxc/amd-gpu/include/gsl_driver.h new file mode 100644 index 000000000000..42dff457dc49 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_driver.h @@ -0,0 +1,106 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DRIVER_H +#define __GSL_DRIVER_H + + +///////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#ifdef GSL_DEDICATED_PROCESS +#define GSL_CALLER_PROCESSID_GET() kos_callerprocess_getid() +#else +#define GSL_CALLER_PROCESSID_GET() kos_process_getid() +#endif // GSL_DEDICATED_PROCESS + +#ifdef GSL_LOCKING_COURSEGRAIN +#define GSL_API_MUTEX_CREATE() gsl_driver.mutex = kos_mutex_create("gsl_global"); \ + if (!gsl_driver.mutex) {return (GSL_FAILURE);} +#define GSL_API_MUTEX_LOCK() kos_mutex_lock(gsl_driver.mutex) +#define GSL_API_MUTEX_UNLOCK() kos_mutex_unlock(gsl_driver.mutex) +#define GSL_API_MUTEX_FREE() kos_mutex_free(gsl_driver.mutex); gsl_driver.mutex = 0; +#else +#define GSL_API_MUTEX_CREATE() +#define GSL_API_MUTEX_LOCK() +#define GSL_API_MUTEX_UNLOCK() +#define GSL_API_MUTEX_FREE() +#endif + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ------------- +// driver object +// ------------- +typedef struct _gsl_driver_t { + gsl_flags_t flags_debug; + int refcnt; + unsigned int callerprocess[GSL_CALLER_PROCESS_MAX]; // caller process table + oshandle_t mutex; // global API mutex + void *hal; + gsl_sharedmem_t shmem; + gsl_device_t device[GSL_DEVICE_MAX]; + int dmi_state; // OS_TRUE = enabled, OS_FALSE otherwise + gsl_flags_t dmi_mode; // single, double, or triple buffering + int dmi_frame; // set to -1 when DMI is enabled + int dmi_max_frame; // indicates the maximum frame # that we will support + int enable_mmu; +} gsl_driver_t; + + +////////////////////////////////////////////////////////////////////////////// +// external variable declarations +////////////////////////////////////////////////////////////////////////////// +extern gsl_driver_t gsl_driver; + + +////////////////////////////////////////////////////////////////////////////// +// inline functions +////////////////////////////////////////////////////////////////////////////// +OSINLINE int +kgsl_driver_getcallerprocessindex(unsigned int pid, int *index) +{ + int i; + + // obtain index in caller process table + for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++) + { + if (gsl_driver.callerprocess[i] == pid) + { + *index = i; + return (GSL_SUCCESS); + } + } + + return (GSL_FAILURE); +} + +#endif // __GSL_DRIVER_H diff --git a/drivers/mxc/amd-gpu/include/gsl_hal.h b/drivers/mxc/amd-gpu/include/gsl_hal.h new file mode 100644 index 000000000000..fcf9f0891f16 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_hal.h @@ -0,0 +1,151 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_HALAPI_H +#define __GSL_HALAPI_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/* +#include "gsl_buildconfig.h" +#include "kos_libapi.h" +#include "gsl_klibapi.h" +#ifdef GSL_BLD_YAMATO +#include +#endif +#ifdef GSL_BLD_G12 +#include +#endif +#include "gsl_hwaccess.h" +*/ + +#include "gsl.h" +#include "gsl_hwaccess.h" + + +////////////////////////////////////////////////////////////////////////////// +// linkage +////////////////////////////////////////////////////////////////////////////// +#ifdef __KGSLHAL_EXPORTS +#define KGSLHAL_API OS_DLLEXPORT +#else +#define KGSLHAL_API +#endif // __KGSLLIB_EXPORTS + + +////////////////////////////////////////////////////////////////////////////// +// version control +////////////////////////////////////////////////////////////////////////////// +#define KGSLHAL_NAME "AMD GSL Kernel HAL" +#define KGSLHAL_VERSION "0.1" + + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define GSL_HAL_REG_READ(device_id, gpubase, offsetwords, value) kgsl_hwaccess_regread(device_id, gpubase, (offsetwords), (value)) +#define GSL_HAL_REG_WRITE(device_id, gpubase, offsetwords, value) kgsl_hwaccess_regwrite(device_id, gpubase, (offsetwords), (value)) + +#define GSL_HAL_MEM_READ(dst, gpubase, gpuoffset, sizebytes, touserspace) kgsl_hwaccess_memread(dst, gpubase, (gpuoffset), (sizebytes), touserspace) +#define GSL_HAL_MEM_WRITE(gpubase, gpuoffset, src, sizebytes, fromuserspace) kgsl_hwaccess_memwrite(gpubase, (gpuoffset), src, (sizebytes), fromuserspace) +#define GSL_HAL_MEM_SET(gpubase, gpuoffset, value, sizebytes) kgsl_hwaccess_memset(gpubase, (gpuoffset), (value), (sizebytes)) + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ------------- +// device config +// ------------- +typedef struct _gsl_devconfig_t { + + gsl_memregion_t regspace; + + unsigned int mmu_config; + gpuaddr_t mpu_base; + int mpu_range; + gpuaddr_t va_base; + unsigned int va_range; + +#ifdef GSL_BLD_YAMATO + gsl_memregion_t gmemspace; +#endif // GSL_BLD_YAMATO + +} gsl_devconfig_t; + +// ---------------------- +// memory aperture config +// ---------------------- +typedef struct _gsl_apertureconfig_t +{ + gsl_apertureid_t id; + gsl_channelid_t channel; + unsigned int hostbase; + unsigned int gpubase; + unsigned int sizebytes; +} gsl_apertureconfig_t; + +// -------------------- +// shared memory config +// -------------------- +typedef struct _gsl_shmemconfig_t +{ + int numapertures; + gsl_apertureconfig_t apertures[GSL_SHMEM_MAX_APERTURES]; +} gsl_shmemconfig_t; + +typedef struct _gsl_hal_t { + gsl_memregion_t z160_regspace; + gsl_memregion_t z430_regspace; + gsl_memregion_t memchunk; + gsl_memregion_t memspace[GSL_SHMEM_MAX_APERTURES]; + unsigned int has_z160; + unsigned int has_z430; +} gsl_hal_t; + + +////////////////////////////////////////////////////////////////////////////// +// HAL API +////////////////////////////////////////////////////////////////////////////// +KGSLHAL_API int kgsl_hal_init(void); +KGSLHAL_API int kgsl_hal_close(void); +KGSLHAL_API int kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config); +KGSLHAL_API int kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config); +KGSLHAL_API int kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value); +KGSLHAL_API gsl_chipid_t kgsl_hal_getchipid(gsl_deviceid_t device_id); +KGSLHAL_API int kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]); +KGSLHAL_API int kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]); + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // __GSL_HALAPI_H diff --git a/drivers/mxc/amd-gpu/include/gsl_halconfig.h b/drivers/mxc/amd-gpu/include/gsl_halconfig.h new file mode 100755 index 000000000000..363474b7a6bb --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_halconfig.h @@ -0,0 +1,49 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __GSL_HALCONFIG_H +#define __GSL_HALCONFIG_H + +#define GSL_HAL_GPUBASE_REG_YDX 0x30000000 +#define GSL_HAL_SIZE_REG_YDX 0x00020000 /* 128KB */ + +#define GSL_HAL_SIZE_REG_G12 0x00001000 /* 4KB */ + +#define GSL_HAL_SHMEM_SIZE_EMEM1_MMU 0x01800000 /* 24MB */ +#define GSL_HAL_SHMEM_SIZE_EMEM2_MMU 0x00400000 /* 4MB */ +#define GSL_HAL_SHMEM_SIZE_PHYS_MMU 0x00400000 /* 4MB */ + +#define GSL_HAL_SHMEM_SIZE_EMEM1_NOMMU 0x00A00000 /* 10MB */ +#define GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU 0x00200000 /* 2MB */ +#define GSL_HAL_SHMEM_SIZE_PHYS_NOMMU 0x00100000 /* 1MB */ + +#endif /* __GSL_HALCONFIG_H */ diff --git a/drivers/mxc/amd-gpu/include/gsl_intrmgr.h b/drivers/mxc/amd-gpu/include/gsl_intrmgr.h new file mode 100644 index 000000000000..f46f6d8e6a86 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_intrmgr.h @@ -0,0 +1,104 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_INTRMGR_H +#define __GSL_INTRMGR_H + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ------------------------------------- +// block which can generate an interrupt +// ------------------------------------- +typedef enum _gsl_intrblock_t +{ + GSL_INTR_BLOCK_YDX_MH = 0, + GSL_INTR_BLOCK_YDX_CP, + GSL_INTR_BLOCK_YDX_RBBM, + GSL_INTR_BLOCK_YDX_SQ, + GSL_INTR_BLOCK_G12, + GSL_INTR_BLOCK_G12_MH, + + GSL_INTR_BLOCK_COUNT, +} gsl_intrblock_t; + +// ------------------------ +// interrupt block register +// ------------------------ +typedef struct _gsl_intrblock_reg_t +{ + gsl_intrblock_t id; + gsl_intrid_t first_id; + gsl_intrid_t last_id; + unsigned int status_reg; + unsigned int clear_reg; + unsigned int mask_reg; +} gsl_intrblock_reg_t; + +// -------- +// callback +// -------- +typedef void (*gsl_intr_callback_t)(gsl_intrid_t id, void *cookie); + +// ----------------- +// interrupt routine +// ----------------- +typedef struct _gsl_intr_handler_t +{ + gsl_intr_callback_t callback; + void * cookie; +} gsl_intr_handler_t; + +// ----------------- +// interrupt manager +// ----------------- +typedef struct _gsl_intr_t +{ + gsl_flags_t flags; + gsl_device_t *device; + unsigned int enabled[GSL_INTR_BLOCK_COUNT]; + gsl_intr_handler_t handler[GSL_INTR_COUNT]; + oshandle_t evnt[GSL_INTR_COUNT]; +} gsl_intr_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_intr_init(gsl_device_t *device); +int kgsl_intr_close(gsl_device_t *device); +int kgsl_intr_attach(gsl_intr_t *intr, gsl_intrid_t id, gsl_intr_callback_t callback, void *cookie); +int kgsl_intr_detach(gsl_intr_t *intr, gsl_intrid_t id); +int kgsl_intr_enable(gsl_intr_t *intr, gsl_intrid_t id); +int kgsl_intr_disable(gsl_intr_t *intr, gsl_intrid_t id); +int kgsl_intr_isenabled(gsl_intr_t *intr, gsl_intrid_t id); +void kgsl_intr_decode(gsl_device_t *device, gsl_intrblock_t block_id); + +#endif // __GSL_INTMGR_H diff --git a/drivers/mxc/amd-gpu/include/gsl_ioctl.h b/drivers/mxc/amd-gpu/include/gsl_ioctl.h new file mode 100644 index 000000000000..0f1983e4c770 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_ioctl.h @@ -0,0 +1,238 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _GSL_IOCTL_H +#define _GSL_IOCTL_H + +#include "gsl_types.h" +#include "gsl_properties.h" + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +typedef struct _kgsl_device_start_t { + gsl_deviceid_t device_id; + gsl_flags_t flags; +} kgsl_device_start_t; + +typedef struct _kgsl_device_stop_t { + gsl_deviceid_t device_id; +} kgsl_device_stop_t; + +typedef struct _kgsl_device_idle_t { + gsl_deviceid_t device_id; + unsigned int timeout; +} kgsl_device_idle_t; + +typedef struct _kgsl_device_getproperty_t { + gsl_deviceid_t device_id; + gsl_property_type_t type; + unsigned int *value; + unsigned int sizebytes; +} kgsl_device_getproperty_t; + +typedef struct _kgsl_device_setproperty_t { + gsl_deviceid_t device_id; + gsl_property_type_t type; + void *value; + unsigned int sizebytes; +} kgsl_device_setproperty_t; + +typedef struct _kgsl_device_regread_t { + gsl_deviceid_t device_id; + unsigned int offsetwords; + unsigned int *value; +} kgsl_device_regread_t; + +typedef struct _kgsl_device_regwrite_t { + gsl_deviceid_t device_id; + unsigned int offsetwords; + unsigned int value; +} kgsl_device_regwrite_t; + +typedef struct _kgsl_device_waitirq_t { + gsl_deviceid_t device_id; + gsl_intrid_t intr_id; + unsigned int *count; + unsigned int timeout; +} kgsl_device_waitirq_t; + +typedef struct _kgsl_cmdstream_issueibcmds_t { + gsl_deviceid_t device_id; + int drawctxt_index; + gpuaddr_t ibaddr; + int sizedwords; + gsl_timestamp_t *timestamp; + gsl_flags_t flags; +} kgsl_cmdstream_issueibcmds_t; + +typedef struct _kgsl_cmdstream_readtimestamp_t { + gsl_deviceid_t device_id; + gsl_timestamp_type_t type; + gsl_timestamp_t *timestamp; +} kgsl_cmdstream_readtimestamp_t; + +typedef struct _kgsl_cmdstream_freememontimestamp_t { + gsl_deviceid_t device_id; + gsl_memdesc_t *memdesc; + gsl_timestamp_t timestamp; + gsl_timestamp_type_t type; +} kgsl_cmdstream_freememontimestamp_t; + +typedef struct _kgsl_cmdstream_waittimestamp_t { + gsl_deviceid_t device_id; + gsl_timestamp_t timestamp; + unsigned int timeout; +} kgsl_cmdstream_waittimestamp_t; + +typedef struct _kgsl_cmdwindow_write_t { + gsl_deviceid_t device_id; + gsl_cmdwindow_t target; + unsigned int addr; + unsigned int data; +} kgsl_cmdwindow_write_t; + +typedef struct _kgsl_context_create_t { + gsl_deviceid_t device_id; + gsl_context_type_t type; + unsigned int *drawctxt_id; + gsl_flags_t flags; +} kgsl_context_create_t; + +typedef struct _kgsl_context_destroy_t { + gsl_deviceid_t device_id; + unsigned int drawctxt_id; +} kgsl_context_destroy_t; + +typedef struct _kgsl_drawctxt_bind_gmem_shadow_t { + gsl_deviceid_t device_id; + unsigned int drawctxt_id; + const gsl_rect_t* gmem_rect; + unsigned int shadow_x; + unsigned int shadow_y; + const gsl_buffer_desc_t* shadow_buffer; + unsigned int buffer_id; +} kgsl_drawctxt_bind_gmem_shadow_t; + +typedef struct _kgsl_sharedmem_alloc_t { + gsl_deviceid_t device_id; + gsl_flags_t flags; + int sizebytes; + gsl_memdesc_t *memdesc; +} kgsl_sharedmem_alloc_t; + +typedef struct _kgsl_sharedmem_free_t { + gsl_memdesc_t *memdesc; +} kgsl_sharedmem_free_t; + +typedef struct _kgsl_sharedmem_read_t { + const gsl_memdesc_t *memdesc; + unsigned int *dst; + unsigned int offsetbytes; + unsigned int sizebytes; +} kgsl_sharedmem_read_t; + +typedef struct _kgsl_sharedmem_write_t { + const gsl_memdesc_t *memdesc; + unsigned int offsetbytes; + unsigned int *src; + unsigned int sizebytes; +} kgsl_sharedmem_write_t; + +typedef struct _kgsl_sharedmem_set_t { + const gsl_memdesc_t *memdesc; + unsigned int offsetbytes; + unsigned int value; + unsigned int sizebytes; +} kgsl_sharedmem_set_t; + +typedef struct _kgsl_sharedmem_largestfreeblock_t { + gsl_deviceid_t device_id; + gsl_flags_t flags; + unsigned int *largestfreeblock; +} kgsl_sharedmem_largestfreeblock_t; + +typedef struct _kgsl_sharedmem_cacheoperation_t { + const gsl_memdesc_t *memdesc; + unsigned int offsetbytes; + unsigned int sizebytes; + unsigned int operation; +} kgsl_sharedmem_cacheoperation_t; + +typedef struct _kgsl_sharedmem_fromhostpointer_t { + gsl_deviceid_t device_id; + gsl_memdesc_t *memdesc; + void *hostptr; +} kgsl_sharedmem_fromhostpointer_t; + +typedef struct _kgsl_add_timestamp_t { + gsl_deviceid_t device_id; + gsl_timestamp_t *timestamp; +} kgsl_add_timestamp_t; + +typedef struct _kgsl_device_clock_t { + gsl_deviceid_t device; /* GSL_DEVICE_YAMATO = 1, GSL_DEVICE_G12 = 2 */ + int enable; /* 0: disable, 1: enable */ +} kgsl_device_clock_t; + +////////////////////////////////////////////////////////////////////////////// +// ioctl numbers +////////////////////////////////////////////////////////////////////////////// + +#define GSL_MAGIC 0xF9 +#define IOCTL_KGSL_DEVICE_START _IOW(GSL_MAGIC, 0x20, struct _kgsl_device_start_t) +#define IOCTL_KGSL_DEVICE_STOP _IOW(GSL_MAGIC, 0x21, struct _kgsl_device_stop_t) +#define IOCTL_KGSL_DEVICE_IDLE _IOW(GSL_MAGIC, 0x22, struct _kgsl_device_idle_t) +#define IOCTL_KGSL_DEVICE_GETPROPERTY _IOWR(GSL_MAGIC, 0x23, struct _kgsl_device_getproperty_t) +#define IOCTL_KGSL_DEVICE_SETPROPERTY _IOW(GSL_MAGIC, 0x24, struct _kgsl_device_setproperty_t) +#define IOCTL_KGSL_DEVICE_REGREAD _IOWR(GSL_MAGIC, 0x25, struct _kgsl_device_regread_t) +#define IOCTL_KGSL_DEVICE_REGWRITE _IOW(GSL_MAGIC, 0x26, struct _kgsl_device_regwrite_t) +#define IOCTL_KGSL_DEVICE_WAITIRQ _IOWR(GSL_MAGIC, 0x27, struct _kgsl_device_waitirq_t) +#define IOCTL_KGSL_CMDSTREAM_ISSUEIBCMDS _IOWR(GSL_MAGIC, 0x28, struct _kgsl_cmdstream_issueibcmds_t) +#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP _IOWR(GSL_MAGIC, 0x29, struct _kgsl_cmdstream_readtimestamp_t) +#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP _IOW(GSL_MAGIC, 0x2A, struct _kgsl_cmdstream_freememontimestamp_t) +#define IOCTL_KGSL_CMDSTREAM_WAITTIMESTAMP _IOW(GSL_MAGIC, 0x2B, struct _kgsl_cmdstream_waittimestamp_t) +#define IOCTL_KGSL_CMDWINDOW_WRITE _IOW(GSL_MAGIC, 0x2C, struct _kgsl_cmdwindow_write_t) +#define IOCTL_KGSL_CONTEXT_CREATE _IOWR(GSL_MAGIC, 0x2D, struct _kgsl_context_create_t) +#define IOCTL_KGSL_CONTEXT_DESTROY _IOW(GSL_MAGIC, 0x2E, struct _kgsl_context_destroy_t) +#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW _IOW(GSL_MAGIC, 0x2F, struct _kgsl_drawctxt_bind_gmem_shadow_t) +#define IOCTL_KGSL_SHAREDMEM_ALLOC _IOWR(GSL_MAGIC, 0x30, struct _kgsl_sharedmem_alloc_t) +#define IOCTL_KGSL_SHAREDMEM_FREE _IOW(GSL_MAGIC, 0x31, struct _kgsl_sharedmem_free_t) +#define IOCTL_KGSL_SHAREDMEM_READ _IOWR(GSL_MAGIC, 0x32, struct _kgsl_sharedmem_read_t) +#define IOCTL_KGSL_SHAREDMEM_WRITE _IOW(GSL_MAGIC, 0x33, struct _kgsl_sharedmem_write_t) +#define IOCTL_KGSL_SHAREDMEM_SET _IOW(GSL_MAGIC, 0x34, struct _kgsl_sharedmem_set_t) +#define IOCTL_KGSL_SHAREDMEM_LARGESTFREEBLOCK _IOWR(GSL_MAGIC, 0x35, struct _kgsl_sharedmem_largestfreeblock_t) +#define IOCTL_KGSL_SHAREDMEM_CACHEOPERATION _IOW(GSL_MAGIC, 0x36, struct _kgsl_sharedmem_cacheoperation_t) +#define IOCTL_KGSL_SHAREDMEM_FROMHOSTPOINTER _IOW(GSL_MAGIC, 0x37, struct _kgsl_sharedmem_fromhostpointer_t) +#define IOCTL_KGSL_ADD_TIMESTAMP _IOWR(GSL_MAGIC, 0x38, struct _kgsl_add_timestamp_t) +#define IOCTL_KGSL_DRIVER_EXIT _IOWR(GSL_MAGIC, 0x39, NULL) +#define IOCTL_KGSL_DEVICE_CLOCK _IOWR(GSL_MAGIC, 0x60, struct _kgsl_device_clock_t) + + +#endif diff --git a/drivers/mxc/amd-gpu/include/gsl_log.h b/drivers/mxc/amd-gpu/include/gsl_log.h new file mode 100644 index 000000000000..dbb7e4c6ef96 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_log.h @@ -0,0 +1,74 @@ +/* Copyright (c) 2002,2008-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_LOG_H +#define __GSL_LOG_H + +#define KGSL_LOG_GROUP_DRIVER 0x00000001 +#define KGSL_LOG_GROUP_DEVICE 0x00000002 +#define KGSL_LOG_GROUP_COMMAND 0x00000004 +#define KGSL_LOG_GROUP_CONTEXT 0x00000008 +#define KGSL_LOG_GROUP_MEMORY 0x00000010 +#define KGSL_LOG_GROUP_ALL 0x000000ff + +#define KGSL_LOG_LEVEL_ALL 0x0000ff00 +#define KGSL_LOG_LEVEL_TRACE 0x00003f00 +#define KGSL_LOG_LEVEL_DEBUG 0x00001f00 +#define KGSL_LOG_LEVEL_INFO 0x00000f00 +#define KGSL_LOG_LEVEL_WARN 0x00000700 +#define KGSL_LOG_LEVEL_ERROR 0x00000300 +#define KGSL_LOG_LEVEL_FATAL 0x00000100 + +#define KGSL_LOG_TIMESTAMP 0x00010000 +#define KGSL_LOG_THREAD_ID 0x00020000 +#define KGSL_LOG_PROCESS_ID 0x00040000 + +#ifdef GSL_LOG + +int kgsl_log_init(void); +int kgsl_log_close(void); +int kgsl_log_open_stdout( unsigned int log_flags ); +int kgsl_log_write( unsigned int log_flags, char* format, ... ); +int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags ); +int kgsl_log_open_file( char* filename, unsigned int log_flags ); +int kgsl_log_flush_membuf( char* filename, int memBufId ); + +#else + +// Empty function definitions +OSINLINE int kgsl_log_init(void) { return GSL_SUCCESS; } +OSINLINE int kgsl_log_close(void) { return GSL_SUCCESS; } +OSINLINE int kgsl_log_open_stdout( unsigned int log_flags ) { (void)log_flags; return GSL_SUCCESS; } +OSINLINE int kgsl_log_write( unsigned int log_flags, char* format, ... ) { (void)log_flags; (void)format; return GSL_SUCCESS; } +OSINLINE int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags ) { (void)memBufId; (void)log_flags; return GSL_SUCCESS; } +OSINLINE int kgsl_log_open_file( char* filename, unsigned int log_flags ) { (void)filename; (void)log_flags; return GSL_SUCCESS; } +OSINLINE int kgsl_log_flush_membuf( char* filename, int memBufId ) { (void) filename; (void) memBufId; return GSL_SUCCESS; } + +#endif + +#endif // __GSL_LOG_H diff --git a/drivers/mxc/amd-gpu/include/gsl_memmgr.h b/drivers/mxc/amd-gpu/include/gsl_memmgr.h new file mode 100644 index 000000000000..ef9ad93ea96e --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_memmgr.h @@ -0,0 +1,122 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_MEMMGR_H +#define __GSL_MEMMGR_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_MEMARENA_NODE_POOL_MAX 32 // max is 32 + +#define GSL_MEMARENA_PAGE_DIST_MAX 12 // 4MB + +//#define GSL_MEMARENA_NODE_POOL_ENABLED + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ------------------ +// memory arena stats +// ------------------ +typedef struct _gsl_memarena_stats_t { + __int64 bytes_read; + __int64 bytes_written; + __int64 allocs_success; + __int64 allocs_fail; + __int64 frees; + __int64 allocs_pagedistribution[GSL_MEMARENA_PAGE_DIST_MAX]; // 0=0--(4K-1), 1=4--(8K-1), 2=8--(16K-1),... max-1=(GSL_PAGESIZE<<(max-1))--infinity + __int64 frees_pagedistribution[GSL_MEMARENA_PAGE_DIST_MAX]; +} gsl_memarena_stats_t; + +// ------------ +// memory block +// ------------ +typedef struct _memblk_t { + unsigned int blkaddr; + unsigned int blksize; + struct _memblk_t *next; + struct _memblk_t *prev; + int nodepoolindex; +} memblk_t; + +// ---------------------- +// memory block free list +// ---------------------- +typedef struct _gsl_freelist_t { + memblk_t *head; + memblk_t *allocrover; + memblk_t *freerover; +} gsl_freelist_t; + +// ---------------------- +// memory block node pool +// ---------------------- +typedef struct _gsl_nodepool_t { + unsigned int priv; + memblk_t memblk[GSL_MEMARENA_NODE_POOL_MAX]; + struct _gsl_nodepool_t *next; + struct _gsl_nodepool_t *prev; +} gsl_nodepool_t; + +// ------------------- +// memory arena object +// ------------------- +typedef struct _gsl_memarena_t { + oshandle_t mutex; + unsigned int gpubaseaddr; + unsigned int hostbaseaddr; + unsigned int sizebytes; + gsl_nodepool_t *nodepool; + gsl_freelist_t freelist; + unsigned int priv; + +#ifdef GSL_STATS_MEM + gsl_memarena_stats_t stats; +#endif // GSL_STATS_MEM + +} gsl_memarena_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +gsl_memarena_t* kgsl_memarena_create(int aperture_id, int mmu_virtualized, unsigned int hostbaseaddr, gpuaddr_t gpubaseaddr, int sizebytes); +int kgsl_memarena_destroy(gsl_memarena_t *memarena); +int kgsl_memarena_isvirtualized(gsl_memarena_t *memarena); +int kgsl_memarena_querystats(gsl_memarena_t *memarena, gsl_memarena_stats_t *stats); +int kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_memdesc_t *memdesc); +void kgsl_memarena_free(gsl_memarena_t *memarena, gsl_memdesc_t *memdesc); +void* kgsl_memarena_gethostptr(gsl_memarena_t *memarena, gpuaddr_t gpuaddr); +unsigned int kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena, void *hostptr); +unsigned int kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena, gsl_flags_t flags); + +#endif // __GSL_MEMMGR_H diff --git a/drivers/mxc/amd-gpu/include/gsl_mmu.h b/drivers/mxc/amd-gpu/include/gsl_mmu.h new file mode 100644 index 000000000000..868c5156f290 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_mmu.h @@ -0,0 +1,183 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_MMU_H +#define __GSL_MMU_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#ifdef GSL_STATS_MMU +#define GSL_MMU_STATS(x) x +#else +#define GSL_MMU_STATS(x) +#endif // GSL_STATS_MMU + +#ifdef GSL_MMU_PAGETABLE_PERPROCESS +#define GSL_MMU_PAGETABLE_MAX GSL_CALLER_PROCESS_MAX // all device mmu's share a single page table per process +#else +#define GSL_MMU_PAGETABLE_MAX 1 // all device mmu's share a single global page table +#endif // GSL_MMU_PAGETABLE_PERPROCESS + +#define GSL_PT_SUPER_PTE 8 + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +#ifdef _DEBUG +// --------- +// mmu debug +// --------- +typedef struct _gsl_mmu_debug_t { + unsigned int config; + unsigned int mpu_base; + unsigned int mpu_end; + unsigned int va_range; + unsigned int pt_base; + unsigned int page_fault; + unsigned int trans_error; + unsigned int invalidate; +} gsl_mmu_debug_t; +#endif // _DEBUG + +// ------------ +// mmu register +// ------------ +typedef struct _gsl_mmu_reg_t +{ + unsigned int CONFIG; + unsigned int MPU_BASE; + unsigned int MPU_END; + unsigned int VA_RANGE; + unsigned int PT_BASE; + unsigned int PAGE_FAULT; + unsigned int TRAN_ERROR; + unsigned int INVALIDATE; +} gsl_mmu_reg_t; + +// ------------ +// mh interrupt +// ------------ +typedef struct _gsl_mh_intr_t +{ + gsl_intrid_t AXI_READ_ERROR; + gsl_intrid_t AXI_WRITE_ERROR; + gsl_intrid_t MMU_PAGE_FAULT; +} gsl_mh_intr_t; + +// ---------------- +// page table stats +// ---------------- +typedef struct _gsl_ptstats_t { + __int64 maps; + __int64 unmaps; + __int64 switches; +} gsl_ptstats_t; + +// --------- +// mmu stats +// --------- +typedef struct _gsl_mmustats_t { + gsl_ptstats_t pt; + __int64 tlbflushes; +} gsl_mmustats_t; + +// ----------------- +// page table object +// ----------------- +typedef struct _gsl_pagetable_t { + unsigned int pid; + unsigned int refcnt; + gsl_memdesc_t base; + gpuaddr_t va_base; + unsigned int va_range; + unsigned int last_superpte; + unsigned int max_entries; +} gsl_pagetable_t; + +// ------------------------- +// tlb flush filter object +// ------------------------- +typedef struct _gsl_tlbflushfilter_t { + unsigned int *base; + unsigned int size; +} gsl_tlbflushfilter_t; + +// ---------- +// mmu object +// ---------- +typedef struct _gsl_mmu_t { + unsigned int refcnt; + gsl_flags_t flags; + gsl_device_t *device; + unsigned int config; + gpuaddr_t mpu_base; + int mpu_range; + gpuaddr_t va_base; + unsigned int va_range; + gsl_memdesc_t dummyspace; + gsl_tlbflushfilter_t tlbflushfilter; + gsl_pagetable_t *hwpagetable; // current page table object being used by device mmu + gsl_pagetable_t *pagetable[GSL_MMU_PAGETABLE_MAX]; // page table object table +#ifdef GSL_STATS_MMU + gsl_mmustats_t stats; +#endif // GSL_STATS_MMU +} gsl_mmu_t; + + +////////////////////////////////////////////////////////////////////////////// +// inline functions +////////////////////////////////////////////////////////////////////////////// +OSINLINE int +kgsl_mmu_isenabled(gsl_mmu_t *mmu) +{ + // address translation enabled + int enabled = ((mmu)->flags & GSL_FLAGS_STARTED) ? 1 : 0; + + return (enabled); +} + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_mmu_init(gsl_device_t *device); +int kgsl_mmu_close(gsl_device_t *device); +int kgsl_mmu_attachcallback(gsl_mmu_t *mmu, unsigned int pid); +int kgsl_mmu_detachcallback(gsl_mmu_t *mmu, unsigned int pid); +int kgsl_mmu_setpagetable(gsl_device_t *device, unsigned int pid); +int kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *scatterlist, gsl_flags_t flags, unsigned int pid); +int kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pid); +int kgsl_mmu_getmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, gsl_scatterlist_t *scatterlist, unsigned int pid); +int kgsl_mmu_querystats(gsl_mmu_t *mmu, gsl_mmustats_t *stats); +int kgsl_mmu_bist(gsl_mmu_t *mmu); + +#endif // __GSL_MMU_H diff --git a/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h b/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h new file mode 100644 index 000000000000..6081c396f6e4 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h @@ -0,0 +1,235 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_RINGBUFFER_H +#define __GSL_RINGBUFFER_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// + +// ringbuffer sizes log2quadword +#define GSL_RB_SIZE_8 0 +#define GSL_RB_SIZE_16 1 +#define GSL_RB_SIZE_32 2 +#define GSL_RB_SIZE_64 3 +#define GSL_RB_SIZE_128 4 +#define GSL_RB_SIZE_256 5 +#define GSL_RB_SIZE_512 6 +#define GSL_RB_SIZE_1K 7 +#define GSL_RB_SIZE_2K 8 +#define GSL_RB_SIZE_4K 9 +#define GSL_RB_SIZE_8K 10 +#define GSL_RB_SIZE_16K 11 +#define GSL_RB_SIZE_32K 12 +#define GSL_RB_SIZE_64K 13 +#define GSL_RB_SIZE_128K 14 +#define GSL_RB_SIZE_256K 15 +#define GSL_RB_SIZE_512K 16 +#define GSL_RB_SIZE_1M 17 +#define GSL_RB_SIZE_2M 18 +#define GSL_RB_SIZE_4M 19 + +// offsets into memptrs +#define GSL_RB_MEMPTRS_RPTR_OFFSET 0 +#define GSL_RB_MEMPTRS_WPTRPOLL_OFFSET (GSL_RB_MEMPTRS_RPTR_OFFSET + sizeof(unsigned int)) + +// dword base address of the GFX decode space +#define GSL_HAL_SUBBLOCK_OFFSET(reg) ((unsigned int)((reg) - (0x2000))) + +// CP timestamp register +#define mmCP_TIMESTAMP mmSCRATCH_REG0 + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +#ifdef _DEBUG +// ---------------- +// ringbuffer debug +// ---------------- +typedef struct _gsl_rb_debug_t { + unsigned int pm4_ucode_rel; + unsigned int pfp_ucode_rel; + unsigned int cp_rb_base; + cp_rb_cntl_u cp_rb_cntl; + unsigned int cp_rb_rptr_addr; + unsigned int cp_rb_rptr; + unsigned int cp_rb_wptr; + unsigned int cp_rb_wptr_base; + scratch_umsk_u scratch_umsk; + unsigned int scratch_addr; + cp_me_cntl_u cp_me_cntl; + cp_me_status_u cp_me_status; + cp_debug_u cp_debug; + cp_stat_u cp_stat; + rbbm_status_u rbbm_status; + unsigned int sop_timestamp; + unsigned int eop_timestamp; +} gsl_rb_debug_t; +#endif // _DEBUG + +// ------------------- +// ringbuffer watchdog +// ------------------- +typedef struct _gsl_rbwatchdog_t { + gsl_flags_t flags; + unsigned int rptr_sample; +} gsl_rbwatchdog_t; + +// ------------------ +// memory ptr objects +// ------------------ +#ifdef __GNUC__ +#pragma pack(push, 1) +#else +#pragma pack(push) +#pragma pack(1) +#endif +typedef struct _gsl_rbmemptrs_t { + volatile int rptr; + int wptr_poll; +} gsl_rbmemptrs_t; +#pragma pack(pop) + +// ----- +// stats +// ----- +typedef struct _gsl_rbstats_t { + __int64 wraps; + __int64 issues; + __int64 wordstotal; +} gsl_rbstats_t; + + +// ----------------- +// ringbuffer object +// ----------------- +typedef struct _gsl_ringbuffer_t { + + gsl_device_t *device; + gsl_flags_t flags; + + gsl_memdesc_t buffer_desc; // allocated memory descriptor + gsl_memdesc_t memptrs_desc; + + gsl_rbmemptrs_t *memptrs; + + unsigned int sizedwords; // ring buffer size dwords + unsigned int blksizequadwords; + + unsigned int wptr; // write pointer offset in dwords from baseaddr + unsigned int rptr; // read pointer offset in dwords from baseaddr + gsl_timestamp_t timestamp; + + + gsl_rbwatchdog_t watchdog; + +#ifdef GSL_STATS_RINGBUFFER + gsl_rbstats_t stats; +#endif // GSL_STATS_RINGBUFFER + +} gsl_ringbuffer_t; + + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// + +// ---------- +// ring write +// ---------- +#define GSL_RB_WRITE(ring, data) \ + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RINGBUF_WRT, (unsigned int)ring, data, 0, "GSL_RB_WRITE")); \ + *(unsigned int *)(ring)++ = (unsigned int)(data); + +// --------- +// timestamp +// --------- +#ifdef GSL_DEVICE_SHADOW_MEMSTORE_TO_USER +#define GSL_RB_USE_MEM_TIMESTAMP +#endif //GSL_DEVICE_SHADOW_MEMSTORE_TO_USER + +#ifdef GSL_RB_USE_MEM_TIMESTAMP +#define GSL_RB_MEMPTRS_SCRATCH_MASK 0x1 // enable timestamp (...scratch0) memory shadowing +#define GSL_RB_INIT_TIMESTAMP(rb) + +#else +#define GSL_RB_MEMPTRS_SCRATCH_MASK 0x0 // disable +#define GSL_RB_INIT_TIMESTAMP(rb) kgsl_device_regwrite((rb)->device->id, mmCP_TIMESTAMP, 0); +#endif // GSL_RB_USE_MEMTIMESTAMP + +// -------- +// mem rptr +// -------- +#ifdef GSL_RB_USE_MEM_RPTR +#define GSL_RB_CNTL_NO_UPDATE 0x0 // enable +#define GSL_RB_GET_READPTR(rb, data) kgsl_sharedmem_read0(&(rb)->memptrs_desc, (data), GSL_RB_MEMPTRS_RPTR_OFFSET, 4, false) +#else +#define GSL_RB_CNTL_NO_UPDATE 0x1 // disable +#define GSL_RB_GET_READPTR(rb, data) (rb)->device->fbtl.device_regread((rb)->device, mmCP_RB_RPTR,(data)) +#endif // GSL_RB_USE_MEMRPTR + +// ------------ +// wptr polling +// ------------ +#ifdef GSL_RB_USE_WPTR_POLLING +#define GSL_RB_CNTL_POLL_EN 0x1 // enable +#define GSL_RB_UPDATE_WPTR_POLLING(rb) (rb)->memptrs->wptr_poll = (rb)->wptr +#else +#define GSL_RB_CNTL_POLL_EN 0x0 // disable +#define GSL_RB_UPDATE_WPTR_POLLING(rb) +#endif // GSL_RB_USE_WPTR_POLLING + +// ----- +// stats +// ----- +#ifdef GSL_STATS_RINGBUFFER +#define GSL_RB_STATS(x) x +#else +#define GSL_RB_STATS(x) +#endif // GSL_STATS_RINGBUFFER + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_ringbuffer_init(gsl_device_t *device); +int kgsl_ringbuffer_close(gsl_ringbuffer_t *rb); +int kgsl_ringbuffer_start(gsl_ringbuffer_t *rb); +int kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb); +gsl_timestamp_t kgsl_ringbuffer_issuecmds(gsl_device_t *device, int pmodeoff, unsigned int *cmdaddr, int sizedwords, unsigned int pid); +int kgsl_ringbuffer_issueibcmds(gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags); +void kgsl_ringbuffer_watchdog(void); + +int kgsl_ringbuffer_querystats(gsl_ringbuffer_t *rb, gsl_rbstats_t *stats); +int kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb); + +#endif // __GSL_RINGBUFFER_H diff --git a/drivers/mxc/amd-gpu/include/gsl_sharedmem.h b/drivers/mxc/amd-gpu/include/gsl_sharedmem.h new file mode 100644 index 000000000000..bb9692cc1e44 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_sharedmem.h @@ -0,0 +1,110 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_SHAREDMEM_H +#define __GSL_SHAREDMEM_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// + +#define GSL_APERTURE_MASK 0x000000FF +#define GSL_DEVICEID_MASK 0x0000FF00 +#define GSL_EXTALLOC_MASK 0x000F0000 + +#define GSL_APERTURE_SHIFT 0 +#define GSL_DEVICEID_SHIFT 8 +#define GSL_EXTALLOC_SHIFT 16 + +#define GSL_APERTURE_GETGPUADDR(shmem, aperture_index) \ + shmem.apertures[aperture_index].memarena->gpubaseaddr; + +#define GSL_APERTURE_GETHOSTADDR(shmem, aperture_index) \ + shmem.apertures[aperture_index].memarena->hostbaseaddr; + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// --------------------- +// memory aperture stats +// --------------------- +typedef struct _gsl_aperture_stats_t +{ + gsl_apertureid_t id; + gsl_channelid_t channel; + gsl_memarena_stats_t memarena; +} gsl_aperture_stats_t; + +// ------------------- +// shared memory stats +// ------------------- +typedef struct _gsl_sharedmem_stats_t +{ + gsl_aperture_stats_t apertures[GSL_SHMEM_MAX_APERTURES]; +} gsl_sharedmem_stats_t; + +// --------------- +// memory aperture +// --------------- +typedef struct _gsl_aperture_t +{ + gsl_apertureid_t id; + gsl_channelid_t channel; + int numbanks; + gsl_memarena_t *memarena; +} gsl_aperture_t; + +// -------------------- +// shared memory object +// -------------------- +typedef struct _gsl_sharedmem_t +{ + gsl_flags_t flags; + unsigned int priv; + int numapertures; + gsl_aperture_t apertures[GSL_SHMEM_MAX_APERTURES]; + int aperturelookup[GSL_APERTURE_MAX][GSL_CHANNEL_MAX]; +} gsl_sharedmem_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_sharedmem_init(gsl_sharedmem_t *shmem); +int kgsl_sharedmem_close(gsl_sharedmem_t *shmem); +int kgsl_sharedmem_alloc0(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc); +int kgsl_sharedmem_free0(gsl_memdesc_t *memdesc, unsigned int pid); +int kgsl_sharedmem_read0(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace); +int kgsl_sharedmem_write0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace); +int kgsl_sharedmem_set0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes); +int kgsl_sharedmem_querystats(gsl_sharedmem_t *shmem, gsl_sharedmem_stats_t *stats); +unsigned int kgsl_sharedmem_convertaddr(unsigned int addr, int type); + +#endif // __GSL_SHAREDMEM_H diff --git a/drivers/mxc/amd-gpu/include/gsl_tbdump.h b/drivers/mxc/amd-gpu/include/gsl_tbdump.h new file mode 100644 index 000000000000..53b30a8442e7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_tbdump.h @@ -0,0 +1,38 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_TBDUMP_H +#define __GSL_TBDUMP_H + +void tbdump_open(char* filename); +void tbdump_close(); +void tbdump_syncmem(unsigned int addr, unsigned int src, unsigned int sizebytes); +void tbdump_setmem(unsigned int addr, unsigned int value, unsigned int sizebytes); +void tbdump_slavewrite(unsigned int addr, unsigned int value); + +#endif // __GSL_TBDUMP_H diff --git a/drivers/mxc/amd-gpu/include/reg/g12_reg.h b/drivers/mxc/amd-gpu/include/reg/g12_reg.h new file mode 100644 index 000000000000..d12d419822a2 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/g12_reg.h @@ -0,0 +1,41 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _G12_H +#define _G12_H + +#ifdef _Z180 +#include "vgc/vgregs_z180.h" +#include "vgc/vgenums_z180.h" +#else +#include "vgc/vgregs_z160.h" +#include "vgc/vgenums_z160.h" +#endif + +#endif // _G12_H diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h new file mode 100644 index 000000000000..911c22fbbba6 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h @@ -0,0 +1,291 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REGS_ENUMS_H +#define __REGS_ENUMS_H + +typedef enum _BB_CULL { + BB_CULL_NONE = 0, + BB_CULL_CW = 1, + BB_CULL_CCW = 2, +} BB_CULL; + +typedef enum _BB_TEXTUREADDRESS { + BB_TADDRESS_WRAP = 0, + BB_TADDRESS_CLAMP = 1, + BB_TADDRESS_BORDER = 2, + BB_TADDRESS_MIRROR = 4, + BB_TADDRESS_MIRRORCLAMP = 5, // Not supported on G3x cores + BB_TADDRESS_MIRRORBORDER = 6, // Not supported on G3x cores +} BB_TEXTUREADDRESS; + +typedef enum _BB_TEXTYPE { + BB_TEXTYPE_4444 = 0, + BB_TEXTYPE_1555 = 1, + BB_TEXTYPE_5551 = 2, + BB_TEXTYPE_565 = 3, + BB_TEXTYPE_8888 = 4, + BB_TEXTYPE_8 = 5, + BB_TEXTYPE_88 = 6, + BB_TEXTYPE_4 = 7, + BB_TEXTYPE_44 = 8, + BB_TEXTYPE_UYVY = 9, + BB_TEXTYPE_YUY2 = 10, + BB_TEXTYPE_YVYU = 11, + BB_TEXTYPE_DXT1 = 12, + BB_TEXTYPE_PACKMAN = 13, + BB_TEXTYPE_PACKMAN_ALPHA4 = 14, + BB_TEXTYPE_1F16 = 15, + BB_TEXTYPE_2F16 = 16, + BB_TEXTYPE_4F16 = 17, + BB_TEXTYPE_IPACKMAN_RGB = 18, + BB_TEXTYPE_IPACKMAN_RGBA = 19, +} BB_TEXTYPE; + +typedef enum _BB_CMPFUNC { + BB_CMP_NEVER = 0, + BB_CMP_LESS = 1, + BB_CMP_EQUAL = 2, + BB_CMP_LESSEQUAL = 3, + BB_CMP_GREATER = 4, + BB_CMP_NOTEQUAL = 5, + BB_CMP_GREATEREQUAL = 6, + BB_CMP_ALWAYS = 7, +} BB_CMPFUNC; + +typedef enum _BB_STENCILOP { + BB_STENCILOP_KEEP = 0, + BB_STENCILOP_ZERO = 1, + BB_STENCILOP_REPLACE = 2, + BB_STENCILOP_INCRSAT = 3, + BB_STENCILOP_DECRSAT = 4, + BB_STENCILOP_INVERT = 5, + BB_STENCILOP_INCR = 6, + BB_STENCILOP_DECR = 7, +} BB_STENCILOP; + +typedef enum _BB_PRIMITIVETYPE { + BB_PT_POINTLIST = 0, + BB_PT_LINELIST = 1, + BB_PT_LINESTRIP = 2, + BB_PT_TRIANGLELIST = 3, + BB_PT_TRIANGLESTRIP = 4, + BB_PT_TRIANGLEFAN = 5, +} BB_PRIMITIVETYPE; + +typedef enum _BB_TEXTUREFILTERTYPE { + BB_TEXF_NONE = 0, // filtering disabled (valid for mip filter only) + BB_TEXF_POINT = 1, // nearest + BB_TEXF_LINEAR = 2, // linear interpolation +} BB_TEXTUREFILTERTYPE; + +typedef enum _BB_BUFFER { + BB_BUFFER_PPCODE = 0, // Pixel processor code + BB_BUFFER_UNUSED = 1, // Unused + BB_BUFFER_CBUF = 2, // Color buffer + BB_BUFFER_ZBUF = 3, // Z buffer + BB_BUFFER_AUXBUF0 = 4, // AUX0 buffer + BB_BUFFER_AUXBUF1 = 5, // AUX1 buffer + BB_BUFFER_AUXBUF2 = 6, // AUX2 buffer + BB_BUFFER_AUXBUF3 = 7, // AUX3 buffer +} BB_BUFFER; + +typedef enum _BB_COLORFORMAT { + BB_COLOR_ARGB4444 = 0, + BB_COLOR_ARGB0565 = 1, + BB_COLOR_ARGB1555 = 2, + BB_COLOR_RGBA5551 = 3, + BB_COLOR_ARGB8888 = 4, + BB_COLOR_R16 = 5, + BB_COLOR_RG1616 = 6, + BB_COLOR_ARGB16161616 = 7, + BB_COLOR_D16 = 8, + BB_COLOR_S4D12 = 9, + BB_COLOR_S1D15 = 10, + BB_COLOR_X8D24 = 11, + BB_COLOR_S8D24 = 12, + BB_COLOR_X2D30 = 13, +} BB_COLORFORMAT; + +typedef enum _BB_PP_REGCONFIG { + BB_PP_REGCONFIG_1 = 0, + BB_PP_REGCONFIG_2 = 1, + BB_PP_REGCONFIG_3 = 8, + BB_PP_REGCONFIG_4 = 2, + BB_PP_REGCONFIG_6 = 9, + BB_PP_REGCONFIG_8 = 3, + BB_PP_REGCONFIG_12 = 10, + BB_PP_REGCONFIG_16 = 4, + BB_PP_REGCONFIG_24 = 11, + BB_PP_REGCONFIG_32 = 5, +} BB_PP_REGCONFIG; + +typedef enum _G2D_read_t { + G2D_READ_DST = 0, + G2D_READ_SRC1 = 1, + G2D_READ_SRC2 = 2, + G2D_READ_SRC3 = 3, +} G2D_read_t; + +typedef enum _G2D_format_t { + G2D_1 = 0, // foreground & background + G2D_1BW = 1, // black & white + G2D_4 = 2, + G2D_8 = 3, // alpha + G2D_4444 = 4, + G2D_1555 = 5, + G2D_0565 = 6, + G2D_8888 = 7, + G2D_YUY2 = 8, + G2D_UYVY = 9, + G2D_YVYU = 10, + G2D_4444_RGBA = 11, + G2D_5551_RGBA = 12, + G2D_8888_RGBA = 13, + G2D_A8 = 14, // for alpha texture only +} G2D_format_t; + +typedef enum _G2D_wrap_t { + G2D_WRAP_CLAMP = 0, + G2D_WRAP_REPEAT = 1, + G2D_WRAP_MIRROR = 2, + G2D_WRAP_BORDER = 3, +} G2D_wrap_t; + +typedef enum _G2D_BLEND_OP { + G2D_BLENDOP_ADD = 0, + G2D_BLENDOP_SUB = 1, + G2D_BLENDOP_MIN = 2, + G2D_BLENDOP_MAX = 3, +} G2D_BLEND_OP; + +typedef enum _G2D_GRAD_OP { + G2D_GRADOP_DOT = 0, + G2D_GRADOP_RCP = 1, + G2D_GRADOP_SQRTMUL = 2, + G2D_GRADOP_SQRTADD = 3, +} G2D_GRAD_OP; + +typedef enum _G2D_BLEND_SRC { + G2D_BLENDSRC_ZERO = 0, // One with invert + G2D_BLENDSRC_SOURCE = 1, // Paint with coverage alpha applied + G2D_BLENDSRC_DESTINATION = 2, + G2D_BLENDSRC_IMAGE = 3, // Second texture + G2D_BLENDSRC_TEMP0 = 4, + G2D_BLENDSRC_TEMP1 = 5, + G2D_BLENDSRC_TEMP2 = 6, +} G2D_BLEND_SRC; + +typedef enum _G2D_BLEND_DST { + G2D_BLENDDST_IGNORE = 0, // Ignore destination + G2D_BLENDDST_TEMP0 = 1, + G2D_BLENDDST_TEMP1 = 2, + G2D_BLENDDST_TEMP2 = 3, +} G2D_BLEND_DST; + +typedef enum _G2D_BLEND_CONST { + G2D_BLENDSRC_CONST0 = 0, + G2D_BLENDSRC_CONST1 = 1, + G2D_BLENDSRC_CONST2 = 2, + G2D_BLENDSRC_CONST3 = 3, + G2D_BLENDSRC_CONST4 = 4, + G2D_BLENDSRC_CONST5 = 5, + G2D_BLENDSRC_CONST6 = 6, + G2D_BLENDSRC_CONST7 = 7, +} G2D_BLEND_CONST; + +typedef enum _V3_NEXTCMD { + VGV3_NEXTCMD_CONTINUE = 0, // Continue reading at current address, COUNT gives size of next packet. + VGV3_NEXTCMD_JUMP = 1, // Jump to CALLADDR, COUNT gives size of next packet. + VGV3_NEXTCMD_CALL = 2, // First call a sub-stream at CALLADDR for CALLCOUNT dwords. Then perform a continue. + VGV3_NEXTCMD_CALLV2TRUE = 3, // Not supported. + VGV3_NEXTCMD_CALLV2FALSE = 4, // Not supported. + VGV3_NEXTCMD_ABORT = 5, // Abort reading. This ends the stream. Normally stream can just be paused (or automatically pauses at the end) which avoids any data being lost. +} V3_NEXTCMD; + +typedef enum _V3_FORMAT { + VGV3_FORMAT_S8 = 0, // Signed 8 bit data (4 writes per data dword) => VGV2-float + VGV3_FORMAT_S16 = 1, // Signed 16 bit data (2 writes per data dword) => VGV2-float + VGV3_FORMAT_S32 = 2, // Signed 32 bit data => VGV2-float + VGV3_FORMAT_F32 = 3, // IEEE 32-bit floating point => VGV2-float + VGV3_FORMAT_RAW = 4, // No conversion +} V3_FORMAT; + +typedef enum _V2_ACTION { + VGV2_ACTION_END = 0, // end previous path + VGV2_ACTION_MOVETOOPEN = 1, // end previous path, C1=C4, start new open subpath + VGV2_ACTION_MOVETOCLOSED = 2, // end previous path, C1=C4, start new closed subpath + VGV2_ACTION_LINETO = 3, // line C1,C4 + VGV2_ACTION_CUBICTO = 4, // cubic C1,C2,C3,C4. + VGV2_ACTION_QUADTO = 5, // quadratic C1,C3,C4. + VGV2_ACTION_SCUBICTO = 6, // smooth cubic C1,C4. + VGV2_ACTION_SQUADTO = 7, // smooth quadratic C1,C3,C4. + VGV2_ACTION_VERTEXTO = 8, // half lineto C4=pos, C3=normal. + VGV2_ACTION_VERTEXTOOPEN = 9, // moveto open + half lineto C4=pos, C3=normal. + VGV2_ACTION_VERTEXTOCLOSED = 10, // moveto closed + half lineto C4=pos, C3=normal. + VGV2_ACTION_MOVETOMOVE = 11, // end previous path, C1=C4, move but do not start a subpath + VGV2_ACTION_FLUSH = 15, // end previous path and block following regwrites until all lines sent +} V2_ACTION; + +typedef enum _V2_CAP { + VGV2_CAP_BUTT = 0, // butt caps (straight line overlappin starting point + VGV2_CAP_ROUND = 1, // round caps (smoothness depends on ARCSIN/ARCCOS registers) + VGV2_CAP_SQUARE = 2, // square caps (square centered on starting point) +} V2_CAP; + +typedef enum _V2_JOIN { + VGV2_JOIN_MITER = 0, // miter joins (both sides extended towards intersection. If angle is too small (compared to STMITER register) the miter is converted into a BEVEL. + VGV2_JOIN_ROUND = 1, // round joins (smoothness depends on ARCSIN/ARCCOS registers) + VGV2_JOIN_BEVEL = 2, // bevel joins (ends of both sides are connected with a single line) +} V2_JOIN; + +enum +{ + G2D_GRADREG_X = 0, // also usable as temp + G2D_GRADREG_Y = 1, // also usable as temp + G2D_GRADREG_OUTX = 8, + G2D_GRADREG_OUTY = 9, + G2D_GRADREG_C0 = 16, + G2D_GRADREG_C1 = 17, + G2D_GRADREG_C2 = 18, + G2D_GRADREG_C3 = 19, + G2D_GRADREG_C4 = 20, + G2D_GRADREG_C5 = 21, + G2D_GRADREG_C6 = 22, + G2D_GRADREG_C7 = 23, + G2D_GRADREG_C8 = 24, + G2D_GRADREG_C9 = 25, + G2D_GRADREG_C10 = 26, + G2D_GRADREG_C11 = 27, + G2D_GRADREG_ZERO = 28, + G2D_GRADREG_ONE = 29, + G2D_GRADREG_MINUSONE = 30, +}; + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h new file mode 100644 index 000000000000..1660bc1c12a9 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h @@ -0,0 +1,3775 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REGS_G4X_DRIVER_H +#define __REGS_G4X_DRIVER_H + +#ifndef _LINUX +#include +#else +#ifndef assert +#define assert(expr) +#endif +#endif + +//----------------------------------------------------- +// REGISTER ADDRESSES +//----------------------------------------------------- + +#define ADDR_FBC_BASE 0x84 +#define ADDR_FBC_DATA 0x86 +#define ADDR_FBC_HEIGHT 0x8a +#define ADDR_FBC_START 0x8e +#define ADDR_FBC_STRIDE 0x8c +#define ADDR_FBC_WIDTH 0x88 +#define ADDR_VGC_CLOCKEN 0x508 +#define ADDR_VGC_COMMANDSTREAM 0x0 +#define ADDR_VGC_FIFOFREE 0x7c0 +#define ADDR_VGC_IRQENABLE 0x438 +#define ADDR_VGC_IRQSTATUS 0x418 +#define ADDR_VGC_IRQ_ACTIVE_CNT 0x4e0 +#define ADDR_VGC_MMUCOMMANDSTREAM 0x3fc +#define ADDR_VGC_REVISION 0x400 +#define ADDR_VGC_SYSSTATUS 0x410 +#define ADDR_G2D_ALPHABLEND 0xc +#define ADDR_G2D_BACKGROUND 0xb +#define ADDR_G2D_BASE0 0x0 +#define ADDR_G2D_BASE1 0x2 +#define ADDR_G2D_BASE2 0x4 +#define ADDR_G2D_BASE3 0x6 +#define ADDR_G2D_BLENDERCFG 0x11 +#define ADDR_G2D_BLEND_A0 0x14 +#define ADDR_G2D_BLEND_A1 0x15 +#define ADDR_G2D_BLEND_A2 0x16 +#define ADDR_G2D_BLEND_A3 0x17 +#define ADDR_G2D_BLEND_C0 0x18 +#define ADDR_G2D_BLEND_C1 0x19 +#define ADDR_G2D_BLEND_C2 0x1a +#define ADDR_G2D_BLEND_C3 0x1b +#define ADDR_G2D_BLEND_C4 0x1c +#define ADDR_G2D_BLEND_C5 0x1d +#define ADDR_G2D_BLEND_C6 0x1e +#define ADDR_G2D_BLEND_C7 0x1f +#define ADDR_G2D_CFG0 0x1 +#define ADDR_G2D_CFG1 0x3 +#define ADDR_G2D_CFG2 0x5 +#define ADDR_G2D_CFG3 0x7 +#define ADDR_G2D_COLOR 0xff +#define ADDR_G2D_CONFIG 0xe +#define ADDR_G2D_CONST0 0xb0 +#define ADDR_G2D_CONST1 0xb1 +#define ADDR_G2D_CONST2 0xb2 +#define ADDR_G2D_CONST3 0xb3 +#define ADDR_G2D_CONST4 0xb4 +#define ADDR_G2D_CONST5 0xb5 +#define ADDR_G2D_CONST6 0xb6 +#define ADDR_G2D_CONST7 0xb7 +#define ADDR_G2D_FOREGROUND 0xa +#define ADDR_G2D_GRADIENT 0xd0 +#define ADDR_G2D_IDLE 0xfe +#define ADDR_G2D_INPUT 0xf +#define ADDR_G2D_MASK 0x10 +#define ADDR_G2D_ROP 0xd +#define ADDR_G2D_SCISSORX 0x8 +#define ADDR_G2D_SCISSORY 0x9 +#define ADDR_G2D_SXY 0xf2 +#define ADDR_G2D_SXY2 0xf3 +#define ADDR_G2D_VGSPAN 0xf4 +#define ADDR_G2D_WIDTHHEIGHT 0xf1 +#define ADDR_G2D_XY 0xf0 +#define ADDR_GRADW_BORDERCOLOR 0xd4 +#define ADDR_GRADW_CONST0 0xc0 +#define ADDR_GRADW_CONST1 0xc1 +#define ADDR_GRADW_CONST2 0xc2 +#define ADDR_GRADW_CONST3 0xc3 +#define ADDR_GRADW_CONST4 0xc4 +#define ADDR_GRADW_CONST5 0xc5 +#define ADDR_GRADW_CONST6 0xc6 +#define ADDR_GRADW_CONST7 0xc7 +#define ADDR_GRADW_CONST8 0xc8 +#define ADDR_GRADW_CONST9 0xc9 +#define ADDR_GRADW_CONSTA 0xca +#define ADDR_GRADW_CONSTB 0xcb +#define ADDR_GRADW_INST0 0xe0 +#define ADDR_GRADW_INST1 0xe1 +#define ADDR_GRADW_INST2 0xe2 +#define ADDR_GRADW_INST3 0xe3 +#define ADDR_GRADW_INST4 0xe4 +#define ADDR_GRADW_INST5 0xe5 +#define ADDR_GRADW_INST6 0xe6 +#define ADDR_GRADW_INST7 0xe7 +#define ADDR_GRADW_TEXBASE 0xd3 +#define ADDR_GRADW_TEXCFG 0xd1 +#define ADDR_GRADW_TEXSIZE 0xd2 +#define ADDR_MH_ARBITER_CONFIG 0xa40 +#define ADDR_MH_AXI_ERROR 0xa45 +#define ADDR_MH_AXI_HALT_CONTROL 0xa50 +#define ADDR_MH_CLNT_AXI_ID_REUSE 0xa41 +#define ADDR_MH_DEBUG_CTRL 0xa4e +#define ADDR_MH_DEBUG_DATA 0xa4f +#define ADDR_MH_INTERRUPT_CLEAR 0xa44 +#define ADDR_MH_INTERRUPT_MASK 0xa42 +#define ADDR_MH_INTERRUPT_STATUS 0xa43 +#define ADDR_MH_MMU_CONFIG 0x40 +#define ADDR_MH_MMU_INVALIDATE 0x45 +#define ADDR_MH_MMU_MPU_BASE 0x46 +#define ADDR_MH_MMU_MPU_END 0x47 +#define ADDR_MH_MMU_PAGE_FAULT 0x43 +#define ADDR_MH_MMU_PT_BASE 0x42 +#define ADDR_MH_MMU_TRAN_ERROR 0x44 +#define ADDR_MH_MMU_VA_RANGE 0x41 +#define ADDR_MH_PERFCOUNTER0_CONFIG 0xa47 +#define ADDR_MH_PERFCOUNTER0_HI 0xa49 +#define ADDR_MH_PERFCOUNTER0_LOW 0xa48 +#define ADDR_MH_PERFCOUNTER0_SELECT 0xa46 +#define ADDR_MH_PERFCOUNTER1_CONFIG 0xa4b +#define ADDR_MH_PERFCOUNTER1_HI 0xa4d +#define ADDR_MH_PERFCOUNTER1_LOW 0xa4c +#define ADDR_MH_PERFCOUNTER1_SELECT 0xa4a +#define ADDR_MMU_READ_ADDR 0x510 +#define ADDR_MMU_READ_DATA 0x518 +#define ADDR_VGV1_CBASE1 0x2a +#define ADDR_VGV1_CFG1 0x27 +#define ADDR_VGV1_CFG2 0x28 +#define ADDR_VGV1_DIRTYBASE 0x29 +#define ADDR_VGV1_FILL 0x23 +#define ADDR_VGV1_SCISSORX 0x24 +#define ADDR_VGV1_SCISSORY 0x25 +#define ADDR_VGV1_TILEOFS 0x22 +#define ADDR_VGV1_UBASE2 0x2b +#define ADDR_VGV1_VTX0 0x20 +#define ADDR_VGV1_VTX1 0x21 +#define ADDR_VGV2_ACCURACY 0x60 +#define ADDR_VGV2_ACTION 0x6f +#define ADDR_VGV2_ARCCOS 0x62 +#define ADDR_VGV2_ARCSIN 0x63 +#define ADDR_VGV2_ARCTAN 0x64 +#define ADDR_VGV2_BBOXMAXX 0x5c +#define ADDR_VGV2_BBOXMAXY 0x5d +#define ADDR_VGV2_BBOXMINX 0x5a +#define ADDR_VGV2_BBOXMINY 0x5b +#define ADDR_VGV2_BIAS 0x5f +#define ADDR_VGV2_C1X 0x40 +#define ADDR_VGV2_C1XREL 0x48 +#define ADDR_VGV2_C1Y 0x41 +#define ADDR_VGV2_C1YREL 0x49 +#define ADDR_VGV2_C2X 0x42 +#define ADDR_VGV2_C2XREL 0x4a +#define ADDR_VGV2_C2Y 0x43 +#define ADDR_VGV2_C2YREL 0x4b +#define ADDR_VGV2_C3X 0x44 +#define ADDR_VGV2_C3XREL 0x4c +#define ADDR_VGV2_C3Y 0x45 +#define ADDR_VGV2_C3YREL 0x4d +#define ADDR_VGV2_C4X 0x46 +#define ADDR_VGV2_C4XREL 0x4e +#define ADDR_VGV2_C4Y 0x47 +#define ADDR_VGV2_C4YREL 0x4f +#define ADDR_VGV2_CLIP 0x68 +#define ADDR_VGV2_FIRST 0x40 +#define ADDR_VGV2_LAST 0x6f +#define ADDR_VGV2_MITER 0x66 +#define ADDR_VGV2_MODE 0x6e +#define ADDR_VGV2_RADIUS 0x65 +#define ADDR_VGV2_SCALE 0x5e +#define ADDR_VGV2_THINRADIUS 0x61 +#define ADDR_VGV2_XFSTXX 0x56 +#define ADDR_VGV2_XFSTXY 0x58 +#define ADDR_VGV2_XFSTYX 0x57 +#define ADDR_VGV2_XFSTYY 0x59 +#define ADDR_VGV2_XFXA 0x54 +#define ADDR_VGV2_XFXX 0x50 +#define ADDR_VGV2_XFXY 0x52 +#define ADDR_VGV2_XFYA 0x55 +#define ADDR_VGV2_XFYX 0x51 +#define ADDR_VGV2_XFYY 0x53 +#define ADDR_VGV3_CONTROL 0x70 +#define ADDR_VGV3_FIRST 0x70 +#define ADDR_VGV3_LAST 0x7f +#define ADDR_VGV3_MODE 0x71 +#define ADDR_VGV3_NEXTADDR 0x75 +#define ADDR_VGV3_NEXTCMD 0x76 +#define ADDR_VGV3_VGBYPASS 0x77 +#define ADDR_VGV3_WRITE 0x73 +#define ADDR_VGV3_WRITEADDR 0x72 +#define ADDR_VGV3_WRITEDMI 0x7d +#define ADDR_VGV3_WRITEF32 0x7b +#define ADDR_VGV3_WRITEIFPAUSED 0x74 +#define ADDR_VGV3_WRITERAW 0x7c +#define ADDR_VGV3_WRITES16 0x79 +#define ADDR_VGV3_WRITES32 0x7a +#define ADDR_VGV3_WRITES8 0x78 + +// FBC_BASE +typedef struct _REG_FBC_BASE { + unsigned BASE : 32; +} REG_FBC_BASE; + +// FBC_DATA +typedef struct _REG_FBC_DATA { + unsigned DATA : 32; +} REG_FBC_DATA; + +// FBC_HEIGHT +typedef struct _REG_FBC_HEIGHT { + unsigned HEIGHT : 11; +} REG_FBC_HEIGHT; + +// FBC_START +typedef struct _REG_FBC_START { + unsigned DUMMY : 1; +} REG_FBC_START; + +// FBC_STRIDE +typedef struct _REG_FBC_STRIDE { + unsigned STRIDE : 11; +} REG_FBC_STRIDE; + +// FBC_WIDTH +typedef struct _REG_FBC_WIDTH { + unsigned WIDTH : 11; +} REG_FBC_WIDTH; + +// VGC_CLOCKEN +typedef struct _REG_VGC_CLOCKEN { + unsigned BCACHE : 1; + unsigned G2D_VGL3 : 1; + unsigned VG_L1L2 : 1; + unsigned RESERVED : 3; +} REG_VGC_CLOCKEN; + +// VGC_COMMANDSTREAM +typedef struct _REG_VGC_COMMANDSTREAM { + unsigned DATA : 32; +} REG_VGC_COMMANDSTREAM; + +// VGC_FIFOFREE +typedef struct _REG_VGC_FIFOFREE { + unsigned FREE : 1; +} REG_VGC_FIFOFREE; + +// VGC_IRQENABLE +typedef struct _REG_VGC_IRQENABLE { + unsigned MH : 1; + unsigned G2D : 1; + unsigned FIFO : 1; + unsigned FBC : 1; +} REG_VGC_IRQENABLE; + +// VGC_IRQSTATUS +typedef struct _REG_VGC_IRQSTATUS { + unsigned MH : 1; + unsigned G2D : 1; + unsigned FIFO : 1; + unsigned FBC : 1; +} REG_VGC_IRQSTATUS; + +// VGC_IRQ_ACTIVE_CNT +typedef struct _REG_VGC_IRQ_ACTIVE_CNT { + unsigned MH : 8; + unsigned G2D : 8; + unsigned ERRORS : 8; + unsigned FBC : 8; +} REG_VGC_IRQ_ACTIVE_CNT; + +// VGC_MMUCOMMANDSTREAM +typedef struct _REG_VGC_MMUCOMMANDSTREAM { + unsigned DATA : 32; +} REG_VGC_MMUCOMMANDSTREAM; + +// VGC_REVISION +typedef struct _REG_VGC_REVISION { + unsigned MINOR_REVISION : 4; + unsigned MAJOR_REVISION : 4; +} REG_VGC_REVISION; + +// VGC_SYSSTATUS +typedef struct _REG_VGC_SYSSTATUS { + unsigned RESET : 1; +} REG_VGC_SYSSTATUS; + +// G2D_ALPHABLEND +typedef struct _REG_G2D_ALPHABLEND { + unsigned ALPHA : 8; + unsigned OBS_ENABLE : 1; + unsigned CONSTANT : 1; + unsigned INVERT : 1; + unsigned OPTIMIZE : 1; + unsigned MODULATE : 1; + unsigned INVERTMASK : 1; + unsigned PREMULTIPLYDST : 1; + unsigned MASKTOALPHA : 1; +} REG_G2D_ALPHABLEND; + +// G2D_BACKGROUND +typedef struct _REG_G2D_BACKGROUND { + unsigned COLOR : 32; +} REG_G2D_BACKGROUND; + +// G2D_BASE0 +typedef struct _REG_G2D_BASE0 { + unsigned ADDR : 32; +} REG_G2D_BASE0; + +// G2D_BASE1 +typedef struct _REG_G2D_BASE1 { + unsigned ADDR : 32; +} REG_G2D_BASE1; + +// G2D_BASE2 +typedef struct _REG_G2D_BASE2 { + unsigned ADDR : 32; +} REG_G2D_BASE2; + +// G2D_BASE3 +typedef struct _REG_G2D_BASE3 { + unsigned ADDR : 32; +} REG_G2D_BASE3; + +// G2D_BLENDERCFG +typedef struct _REG_G2D_BLENDERCFG { + unsigned PASSES : 3; + unsigned ALPHAPASSES : 2; + unsigned ENABLE : 1; + unsigned OOALPHA : 1; + unsigned OBS_DIVALPHA : 1; + unsigned NOMASK : 1; +} REG_G2D_BLENDERCFG; + +// G2D_BLEND_A0 +typedef struct _REG_G2D_BLEND_A0 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A0; + +// G2D_BLEND_A1 +typedef struct _REG_G2D_BLEND_A1 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A1; + +// G2D_BLEND_A2 +typedef struct _REG_G2D_BLEND_A2 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A2; + +// G2D_BLEND_A3 +typedef struct _REG_G2D_BLEND_A3 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A3; + +// G2D_BLEND_C0 +typedef struct _REG_G2D_BLEND_C0 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C0; + +// G2D_BLEND_C1 +typedef struct _REG_G2D_BLEND_C1 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C1; + +// G2D_BLEND_C2 +typedef struct _REG_G2D_BLEND_C2 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C2; + +// G2D_BLEND_C3 +typedef struct _REG_G2D_BLEND_C3 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C3; + +// G2D_BLEND_C4 +typedef struct _REG_G2D_BLEND_C4 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C4; + +// G2D_BLEND_C5 +typedef struct _REG_G2D_BLEND_C5 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C5; + +// G2D_BLEND_C6 +typedef struct _REG_G2D_BLEND_C6 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C6; + +// G2D_BLEND_C7 +typedef struct _REG_G2D_BLEND_C7 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C7; + +// G2D_CFG0 +typedef struct _REG_G2D_CFG0 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG0; + +// G2D_CFG1 +typedef struct _REG_G2D_CFG1 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG1; + +// G2D_CFG2 +typedef struct _REG_G2D_CFG2 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG2; + +// G2D_CFG3 +typedef struct _REG_G2D_CFG3 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG3; + +// G2D_COLOR +typedef struct _REG_G2D_COLOR { + unsigned ARGB : 32; +} REG_G2D_COLOR; + +// G2D_CONFIG +typedef struct _REG_G2D_CONFIG { + unsigned DST : 1; + unsigned SRC1 : 1; + unsigned SRC2 : 1; + unsigned SRC3 : 1; + unsigned SRCCK : 1; + unsigned DSTCK : 1; + unsigned ROTATE : 2; + unsigned OBS_GAMMA : 1; + unsigned IGNORECKALPHA : 1; + unsigned DITHER : 1; + unsigned WRITESRGB : 1; + unsigned ARGBMASK : 4; + unsigned ALPHATEX : 1; + unsigned PALMLINES : 1; + unsigned NOLASTPIXEL : 1; + unsigned NOPROTECT : 1; +} REG_G2D_CONFIG; + +// G2D_CONST0 +typedef struct _REG_G2D_CONST0 { + unsigned ARGB : 32; +} REG_G2D_CONST0; + +// G2D_CONST1 +typedef struct _REG_G2D_CONST1 { + unsigned ARGB : 32; +} REG_G2D_CONST1; + +// G2D_CONST2 +typedef struct _REG_G2D_CONST2 { + unsigned ARGB : 32; +} REG_G2D_CONST2; + +// G2D_CONST3 +typedef struct _REG_G2D_CONST3 { + unsigned ARGB : 32; +} REG_G2D_CONST3; + +// G2D_CONST4 +typedef struct _REG_G2D_CONST4 { + unsigned ARGB : 32; +} REG_G2D_CONST4; + +// G2D_CONST5 +typedef struct _REG_G2D_CONST5 { + unsigned ARGB : 32; +} REG_G2D_CONST5; + +// G2D_CONST6 +typedef struct _REG_G2D_CONST6 { + unsigned ARGB : 32; +} REG_G2D_CONST6; + +// G2D_CONST7 +typedef struct _REG_G2D_CONST7 { + unsigned ARGB : 32; +} REG_G2D_CONST7; + +// G2D_FOREGROUND +typedef struct _REG_G2D_FOREGROUND { + unsigned COLOR : 32; +} REG_G2D_FOREGROUND; + +// G2D_GRADIENT +typedef struct _REG_G2D_GRADIENT { + unsigned INSTRUCTIONS : 3; + unsigned INSTRUCTIONS2 : 3; + unsigned ENABLE : 1; + unsigned ENABLE2 : 1; + unsigned SEL : 1; +} REG_G2D_GRADIENT; + +// G2D_IDLE +typedef struct _REG_G2D_IDLE { + unsigned IRQ : 1; + unsigned BCFLUSH : 1; + unsigned V3 : 1; +} REG_G2D_IDLE; + +// G2D_INPUT +typedef struct _REG_G2D_INPUT { + unsigned COLOR : 1; + unsigned SCOORD1 : 1; + unsigned SCOORD2 : 1; + unsigned COPYCOORD : 1; + unsigned VGMODE : 1; + unsigned LINEMODE : 1; +} REG_G2D_INPUT; + +// G2D_MASK +typedef struct _REG_G2D_MASK { + unsigned YMASK : 12; + unsigned XMASK : 12; +} REG_G2D_MASK; + +// G2D_ROP +typedef struct _REG_G2D_ROP { + unsigned ROP : 16; +} REG_G2D_ROP; + +// G2D_SCISSORX +typedef struct _REG_G2D_SCISSORX { + unsigned LEFT : 11; + unsigned RIGHT : 11; +} REG_G2D_SCISSORX; + +// G2D_SCISSORY +typedef struct _REG_G2D_SCISSORY { + unsigned TOP : 11; + unsigned BOTTOM : 11; +} REG_G2D_SCISSORY; + +// G2D_SXY +typedef struct _REG_G2D_SXY { + unsigned Y : 11; + unsigned PAD : 5; + unsigned X : 11; +} REG_G2D_SXY; + +// G2D_SXY2 +typedef struct _REG_G2D_SXY2 { + unsigned Y : 11; + unsigned PAD : 5; + unsigned X : 11; +} REG_G2D_SXY2; + +// G2D_VGSPAN +typedef struct _REG_G2D_VGSPAN { + int WIDTH : 12; + unsigned PAD : 4; + unsigned COVERAGE : 4; +} REG_G2D_VGSPAN; + +// G2D_WIDTHHEIGHT +typedef struct _REG_G2D_WIDTHHEIGHT { + int HEIGHT : 12; + unsigned PAD : 4; + int WIDTH : 12; +} REG_G2D_WIDTHHEIGHT; + +// G2D_XY +typedef struct _REG_G2D_XY { + int Y : 12; + unsigned PAD : 4; + int X : 12; +} REG_G2D_XY; + +// GRADW_BORDERCOLOR +typedef struct _REG_GRADW_BORDERCOLOR { + unsigned COLOR : 32; +} REG_GRADW_BORDERCOLOR; + +// GRADW_CONST0 +typedef struct _REG_GRADW_CONST0 { + unsigned VALUE : 16; +} REG_GRADW_CONST0; + +// GRADW_CONST1 +typedef struct _REG_GRADW_CONST1 { + unsigned VALUE : 16; +} REG_GRADW_CONST1; + +// GRADW_CONST2 +typedef struct _REG_GRADW_CONST2 { + unsigned VALUE : 16; +} REG_GRADW_CONST2; + +// GRADW_CONST3 +typedef struct _REG_GRADW_CONST3 { + unsigned VALUE : 16; +} REG_GRADW_CONST3; + +// GRADW_CONST4 +typedef struct _REG_GRADW_CONST4 { + unsigned VALUE : 16; +} REG_GRADW_CONST4; + +// GRADW_CONST5 +typedef struct _REG_GRADW_CONST5 { + unsigned VALUE : 16; +} REG_GRADW_CONST5; + +// GRADW_CONST6 +typedef struct _REG_GRADW_CONST6 { + unsigned VALUE : 16; +} REG_GRADW_CONST6; + +// GRADW_CONST7 +typedef struct _REG_GRADW_CONST7 { + unsigned VALUE : 16; +} REG_GRADW_CONST7; + +// GRADW_CONST8 +typedef struct _REG_GRADW_CONST8 { + unsigned VALUE : 16; +} REG_GRADW_CONST8; + +// GRADW_CONST9 +typedef struct _REG_GRADW_CONST9 { + unsigned VALUE : 16; +} REG_GRADW_CONST9; + +// GRADW_CONSTA +typedef struct _REG_GRADW_CONSTA { + unsigned VALUE : 16; +} REG_GRADW_CONSTA; + +// GRADW_CONSTB +typedef struct _REG_GRADW_CONSTB { + unsigned VALUE : 16; +} REG_GRADW_CONSTB; + +// GRADW_INST0 +typedef struct _REG_GRADW_INST0 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST0; + +// GRADW_INST1 +typedef struct _REG_GRADW_INST1 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST1; + +// GRADW_INST2 +typedef struct _REG_GRADW_INST2 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST2; + +// GRADW_INST3 +typedef struct _REG_GRADW_INST3 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST3; + +// GRADW_INST4 +typedef struct _REG_GRADW_INST4 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST4; + +// GRADW_INST5 +typedef struct _REG_GRADW_INST5 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST5; + +// GRADW_INST6 +typedef struct _REG_GRADW_INST6 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST6; + +// GRADW_INST7 +typedef struct _REG_GRADW_INST7 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST7; + +// GRADW_TEXBASE +typedef struct _REG_GRADW_TEXBASE { + unsigned ADDR : 32; +} REG_GRADW_TEXBASE; + +// GRADW_TEXCFG +typedef struct _REG_GRADW_TEXCFG { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned WRAPU : 2; + unsigned WRAPV : 2; + unsigned BILIN : 1; + unsigned SRGB : 1; + unsigned PREMULTIPLY : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned TEX2D : 1; + unsigned SWAPBITS : 1; +} REG_GRADW_TEXCFG; + +// GRADW_TEXSIZE +typedef struct _REG_GRADW_TEXSIZE { + unsigned WIDTH : 11; + unsigned HEIGHT : 11; +} REG_GRADW_TEXSIZE; + +// MH_ARBITER_CONFIG +typedef struct _REG_MH_ARBITER_CONFIG { + unsigned SAME_PAGE_LIMIT : 6; + unsigned SAME_PAGE_GRANULARITY : 1; + unsigned L1_ARB_ENABLE : 1; + unsigned L1_ARB_HOLD_ENABLE : 1; + unsigned L2_ARB_CONTROL : 1; + unsigned PAGE_SIZE : 3; + unsigned TC_REORDER_ENABLE : 1; + unsigned TC_ARB_HOLD_ENABLE : 1; + unsigned IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned IN_FLIGHT_LIMIT : 6; + unsigned CP_CLNT_ENABLE : 1; + unsigned VGT_CLNT_ENABLE : 1; + unsigned TC_CLNT_ENABLE : 1; + unsigned RB_CLNT_ENABLE : 1; + unsigned PA_CLNT_ENABLE : 1; +} REG_MH_ARBITER_CONFIG; + +// MH_AXI_ERROR +typedef struct _REG_MH_AXI_ERROR { + unsigned AXI_READ_ID : 3; + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ID : 3; + unsigned AXI_WRITE_ERROR : 1; +} REG_MH_AXI_ERROR; + +// MH_AXI_HALT_CONTROL +typedef struct _REG_MH_AXI_HALT_CONTROL { + unsigned AXI_HALT : 1; +} REG_MH_AXI_HALT_CONTROL; + +// MH_CLNT_AXI_ID_REUSE +typedef struct _REG_MH_CLNT_AXI_ID_REUSE { + unsigned CPW_ID : 3; + unsigned PAD : 1; + unsigned RBW_ID : 3; + unsigned PAD2 : 1; + unsigned MMUR_ID : 3; + unsigned PAD3 : 1; + unsigned PAW_ID : 3; +} REG_MH_CLNT_AXI_ID_REUSE; + +// MH_DEBUG_CTRL +typedef struct _REG_MH_DEBUG_CTRL { + unsigned INDEX : 6; +} REG_MH_DEBUG_CTRL; + +// MH_DEBUG_DATA +typedef struct _REG_MH_DEBUG_DATA { + unsigned DATA : 32; +} REG_MH_DEBUG_DATA; + +// MH_INTERRUPT_CLEAR +typedef struct _REG_MH_INTERRUPT_CLEAR { + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ERROR : 1; + unsigned MMU_PAGE_FAULT : 1; +} REG_MH_INTERRUPT_CLEAR; + +// MH_INTERRUPT_MASK +typedef struct _REG_MH_INTERRUPT_MASK { + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ERROR : 1; + unsigned MMU_PAGE_FAULT : 1; +} REG_MH_INTERRUPT_MASK; + +// MH_INTERRUPT_STATUS +typedef struct _REG_MH_INTERRUPT_STATUS { + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ERROR : 1; + unsigned MMU_PAGE_FAULT : 1; +} REG_MH_INTERRUPT_STATUS; + +// MH_MMU_CONFIG +typedef struct _REG_MH_MMU_CONFIG { + unsigned MMU_ENABLE : 1; + unsigned SPLIT_MODE_ENABLE : 1; + unsigned PAD : 2; + unsigned RB_W_CLNT_BEHAVIOR : 2; + unsigned CP_W_CLNT_BEHAVIOR : 2; + unsigned CP_R0_CLNT_BEHAVIOR : 2; + unsigned CP_R1_CLNT_BEHAVIOR : 2; + unsigned CP_R2_CLNT_BEHAVIOR : 2; + unsigned CP_R3_CLNT_BEHAVIOR : 2; + unsigned CP_R4_CLNT_BEHAVIOR : 2; + unsigned VGT_R0_CLNT_BEHAVIOR : 2; + unsigned VGT_R1_CLNT_BEHAVIOR : 2; + unsigned TC_R_CLNT_BEHAVIOR : 2; + unsigned PA_W_CLNT_BEHAVIOR : 2; +} REG_MH_MMU_CONFIG; + +// MH_MMU_INVALIDATE +typedef struct _REG_MH_MMU_INVALIDATE { + unsigned INVALIDATE_ALL : 1; + unsigned INVALIDATE_TC : 1; +} REG_MH_MMU_INVALIDATE; + +// MH_MMU_MPU_BASE +typedef struct _REG_MH_MMU_MPU_BASE { + unsigned ZERO : 12; + unsigned MPU_BASE : 20; +} REG_MH_MMU_MPU_BASE; + +// MH_MMU_MPU_END +typedef struct _REG_MH_MMU_MPU_END { + unsigned ZERO : 12; + unsigned MPU_END : 20; +} REG_MH_MMU_MPU_END; + +// MH_MMU_PAGE_FAULT +typedef struct _REG_MH_MMU_PAGE_FAULT { + unsigned PAGE_FAULT : 1; + unsigned OP_TYPE : 1; + unsigned CLNT_BEHAVIOR : 2; + unsigned AXI_ID : 3; + unsigned PAD : 1; + unsigned MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned ADDRESS_OUT_OF_RANGE : 1; + unsigned READ_PROTECTION_ERROR : 1; + unsigned WRITE_PROTECTION_ERROR : 1; + unsigned REQ_VA : 20; +} REG_MH_MMU_PAGE_FAULT; + +// MH_MMU_PT_BASE +typedef struct _REG_MH_MMU_PT_BASE { + unsigned ZERO : 12; + unsigned PT_BASE : 20; +} REG_MH_MMU_PT_BASE; + +// MH_MMU_TRAN_ERROR +typedef struct _REG_MH_MMU_TRAN_ERROR { + unsigned ZERO : 5; + unsigned TRAN_ERROR : 27; +} REG_MH_MMU_TRAN_ERROR; + +// MH_MMU_VA_RANGE +typedef struct _REG_MH_MMU_VA_RANGE { + unsigned NUM_64KB_REGIONS : 12; + unsigned VA_BASE : 20; +} REG_MH_MMU_VA_RANGE; + +// MH_PERFCOUNTER0_CONFIG +typedef struct _REG_MH_PERFCOUNTER0_CONFIG { + unsigned N_VALUE : 8; +} REG_MH_PERFCOUNTER0_CONFIG; + +// MH_PERFCOUNTER0_HI +typedef struct _REG_MH_PERFCOUNTER0_HI { + unsigned PERF_COUNTER_HI : 16; +} REG_MH_PERFCOUNTER0_HI; + +// MH_PERFCOUNTER0_LOW +typedef struct _REG_MH_PERFCOUNTER0_LOW { + unsigned PERF_COUNTER_LOW : 32; +} REG_MH_PERFCOUNTER0_LOW; + +// MH_PERFCOUNTER0_SELECT +typedef struct _REG_MH_PERFCOUNTER0_SELECT { + unsigned PERF_SEL : 8; +} REG_MH_PERFCOUNTER0_SELECT; + +// MH_PERFCOUNTER1_CONFIG +typedef struct _REG_MH_PERFCOUNTER1_CONFIG { + unsigned N_VALUE : 8; +} REG_MH_PERFCOUNTER1_CONFIG; + +// MH_PERFCOUNTER1_HI +typedef struct _REG_MH_PERFCOUNTER1_HI { + unsigned PERF_COUNTER_HI : 16; +} REG_MH_PERFCOUNTER1_HI; + +// MH_PERFCOUNTER1_LOW +typedef struct _REG_MH_PERFCOUNTER1_LOW { + unsigned PERF_COUNTER_LOW : 32; +} REG_MH_PERFCOUNTER1_LOW; + +// MH_PERFCOUNTER1_SELECT +typedef struct _REG_MH_PERFCOUNTER1_SELECT { + unsigned PERF_SEL : 8; +} REG_MH_PERFCOUNTER1_SELECT; + +// MMU_READ_ADDR +typedef struct _REG_MMU_READ_ADDR { + unsigned ADDR : 15; +} REG_MMU_READ_ADDR; + +// MMU_READ_DATA +typedef struct _REG_MMU_READ_DATA { + unsigned DATA : 32; +} REG_MMU_READ_DATA; + +// VGV1_CBASE1 +typedef struct _REG_VGV1_CBASE1 { + unsigned ADDR : 32; +} REG_VGV1_CBASE1; + +// VGV1_CFG1 +typedef struct _REG_VGV1_CFG1 { + unsigned WINDRULE : 1; +} REG_VGV1_CFG1; + +// VGV1_CFG2 +typedef struct _REG_VGV1_CFG2 { + unsigned AAMODE : 2; +} REG_VGV1_CFG2; + +// VGV1_DIRTYBASE +typedef struct _REG_VGV1_DIRTYBASE { + unsigned ADDR : 32; +} REG_VGV1_DIRTYBASE; + +// VGV1_FILL +typedef struct _REG_VGV1_FILL { + unsigned INHERIT : 1; +} REG_VGV1_FILL; + +// VGV1_SCISSORX +typedef struct _REG_VGV1_SCISSORX { + unsigned LEFT : 11; + unsigned PAD : 5; + unsigned RIGHT : 11; +} REG_VGV1_SCISSORX; + +// VGV1_SCISSORY +typedef struct _REG_VGV1_SCISSORY { + unsigned TOP : 11; + unsigned PAD : 5; + unsigned BOTTOM : 11; +} REG_VGV1_SCISSORY; + +// VGV1_TILEOFS +typedef struct _REG_VGV1_TILEOFS { + unsigned X : 12; + unsigned Y : 12; + unsigned LEFTMOST : 1; +} REG_VGV1_TILEOFS; + +// VGV1_UBASE2 +typedef struct _REG_VGV1_UBASE2 { + unsigned ADDR : 32; +} REG_VGV1_UBASE2; + +// VGV1_VTX0 +typedef struct _REG_VGV1_VTX0 { + int X : 16; + int Y : 16; +} REG_VGV1_VTX0; + +// VGV1_VTX1 +typedef struct _REG_VGV1_VTX1 { + int X : 16; + int Y : 16; +} REG_VGV1_VTX1; + +// VGV2_ACCURACY +typedef struct _REG_VGV2_ACCURACY { + unsigned F : 24; +} REG_VGV2_ACCURACY; + +// VGV2_ACTION +typedef struct _REG_VGV2_ACTION { + unsigned ACTION : 4; +} REG_VGV2_ACTION; + +// VGV2_ARCCOS +typedef struct _REG_VGV2_ARCCOS { + unsigned F : 24; +} REG_VGV2_ARCCOS; + +// VGV2_ARCSIN +typedef struct _REG_VGV2_ARCSIN { + unsigned F : 24; +} REG_VGV2_ARCSIN; + +// VGV2_ARCTAN +typedef struct _REG_VGV2_ARCTAN { + unsigned F : 24; +} REG_VGV2_ARCTAN; + +// VGV2_BBOXMAXX +typedef struct _REG_VGV2_BBOXMAXX { + unsigned F : 24; +} REG_VGV2_BBOXMAXX; + +// VGV2_BBOXMAXY +typedef struct _REG_VGV2_BBOXMAXY { + unsigned F : 24; +} REG_VGV2_BBOXMAXY; + +// VGV2_BBOXMINX +typedef struct _REG_VGV2_BBOXMINX { + unsigned F : 24; +} REG_VGV2_BBOXMINX; + +// VGV2_BBOXMINY +typedef struct _REG_VGV2_BBOXMINY { + unsigned F : 24; +} REG_VGV2_BBOXMINY; + +// VGV2_BIAS +typedef struct _REG_VGV2_BIAS { + unsigned F : 24; +} REG_VGV2_BIAS; + +// VGV2_C1X +typedef struct _REG_VGV2_C1X { + unsigned F : 24; +} REG_VGV2_C1X; + +// VGV2_C1XREL +typedef struct _REG_VGV2_C1XREL { + unsigned F : 24; +} REG_VGV2_C1XREL; + +// VGV2_C1Y +typedef struct _REG_VGV2_C1Y { + unsigned F : 24; +} REG_VGV2_C1Y; + +// VGV2_C1YREL +typedef struct _REG_VGV2_C1YREL { + unsigned F : 24; +} REG_VGV2_C1YREL; + +// VGV2_C2X +typedef struct _REG_VGV2_C2X { + unsigned F : 24; +} REG_VGV2_C2X; + +// VGV2_C2XREL +typedef struct _REG_VGV2_C2XREL { + unsigned F : 24; +} REG_VGV2_C2XREL; + +// VGV2_C2Y +typedef struct _REG_VGV2_C2Y { + unsigned F : 24; +} REG_VGV2_C2Y; + +// VGV2_C2YREL +typedef struct _REG_VGV2_C2YREL { + unsigned F : 24; +} REG_VGV2_C2YREL; + +// VGV2_C3X +typedef struct _REG_VGV2_C3X { + unsigned F : 24; +} REG_VGV2_C3X; + +// VGV2_C3XREL +typedef struct _REG_VGV2_C3XREL { + unsigned F : 24; +} REG_VGV2_C3XREL; + +// VGV2_C3Y +typedef struct _REG_VGV2_C3Y { + unsigned F : 24; +} REG_VGV2_C3Y; + +// VGV2_C3YREL +typedef struct _REG_VGV2_C3YREL { + unsigned F : 24; +} REG_VGV2_C3YREL; + +// VGV2_C4X +typedef struct _REG_VGV2_C4X { + unsigned F : 24; +} REG_VGV2_C4X; + +// VGV2_C4XREL +typedef struct _REG_VGV2_C4XREL { + unsigned F : 24; +} REG_VGV2_C4XREL; + +// VGV2_C4Y +typedef struct _REG_VGV2_C4Y { + unsigned F : 24; +} REG_VGV2_C4Y; + +// VGV2_C4YREL +typedef struct _REG_VGV2_C4YREL { + unsigned F : 24; +} REG_VGV2_C4YREL; + +// VGV2_CLIP +typedef struct _REG_VGV2_CLIP { + unsigned F : 24; +} REG_VGV2_CLIP; + +// VGV2_FIRST +typedef struct _REG_VGV2_FIRST { + unsigned DUMMY : 1; +} REG_VGV2_FIRST; + +// VGV2_LAST +typedef struct _REG_VGV2_LAST { + unsigned DUMMY : 1; +} REG_VGV2_LAST; + +// VGV2_MITER +typedef struct _REG_VGV2_MITER { + unsigned F : 24; +} REG_VGV2_MITER; + +// VGV2_MODE +typedef struct _REG_VGV2_MODE { + unsigned MAXSPLIT : 4; + unsigned CAP : 2; + unsigned JOIN : 2; + unsigned STROKE : 1; + unsigned STROKESPLIT : 1; + unsigned FULLSPLIT : 1; + unsigned NODOTS : 1; + unsigned OPENFILL : 1; + unsigned DROPLEFT : 1; + unsigned DROPOTHER : 1; + unsigned SYMMETRICJOINS : 1; + unsigned SIMPLESTROKE : 1; + unsigned SIMPLECLIP : 1; + int EXPONENTADD : 6; +} REG_VGV2_MODE; + +// VGV2_RADIUS +typedef struct _REG_VGV2_RADIUS { + unsigned F : 24; +} REG_VGV2_RADIUS; + +// VGV2_SCALE +typedef struct _REG_VGV2_SCALE { + unsigned F : 24; +} REG_VGV2_SCALE; + +// VGV2_THINRADIUS +typedef struct _REG_VGV2_THINRADIUS { + unsigned F : 24; +} REG_VGV2_THINRADIUS; + +// VGV2_XFSTXX +typedef struct _REG_VGV2_XFSTXX { + unsigned F : 24; +} REG_VGV2_XFSTXX; + +// VGV2_XFSTXY +typedef struct _REG_VGV2_XFSTXY { + unsigned F : 24; +} REG_VGV2_XFSTXY; + +// VGV2_XFSTYX +typedef struct _REG_VGV2_XFSTYX { + unsigned F : 24; +} REG_VGV2_XFSTYX; + +// VGV2_XFSTYY +typedef struct _REG_VGV2_XFSTYY { + unsigned F : 24; +} REG_VGV2_XFSTYY; + +// VGV2_XFXA +typedef struct _REG_VGV2_XFXA { + unsigned F : 24; +} REG_VGV2_XFXA; + +// VGV2_XFXX +typedef struct _REG_VGV2_XFXX { + unsigned F : 24; +} REG_VGV2_XFXX; + +// VGV2_XFXY +typedef struct _REG_VGV2_XFXY { + unsigned F : 24; +} REG_VGV2_XFXY; + +// VGV2_XFYA +typedef struct _REG_VGV2_XFYA { + unsigned F : 24; +} REG_VGV2_XFYA; + +// VGV2_XFYX +typedef struct _REG_VGV2_XFYX { + unsigned F : 24; +} REG_VGV2_XFYX; + +// VGV2_XFYY +typedef struct _REG_VGV2_XFYY { + unsigned F : 24; +} REG_VGV2_XFYY; + +// VGV3_CONTROL +typedef struct _REG_VGV3_CONTROL { + unsigned MARKADD : 12; + unsigned DMIWAITCHMASK : 4; + unsigned PAUSE : 1; + unsigned ABORT : 1; + unsigned WRITE : 1; + unsigned BCFLUSH : 1; + unsigned V0SYNC : 1; + unsigned DMIWAITBUF : 3; +} REG_VGV3_CONTROL; + +// VGV3_FIRST +typedef struct _REG_VGV3_FIRST { + unsigned DUMMY : 1; +} REG_VGV3_FIRST; + +// VGV3_LAST +typedef struct _REG_VGV3_LAST { + unsigned DUMMY : 1; +} REG_VGV3_LAST; + +// VGV3_MODE +typedef struct _REG_VGV3_MODE { + unsigned FLIPENDIAN : 1; + unsigned UNUSED : 1; + unsigned WRITEFLUSH : 1; + unsigned DMIPAUSETYPE : 1; + unsigned DMIRESET : 1; +} REG_VGV3_MODE; + +// VGV3_NEXTADDR +typedef struct _REG_VGV3_NEXTADDR { + unsigned CALLADDR : 32; +} REG_VGV3_NEXTADDR; + +// VGV3_NEXTCMD +typedef struct _REG_VGV3_NEXTCMD { + unsigned COUNT : 12; + unsigned NEXTCMD : 3; + unsigned MARK : 1; + unsigned CALLCOUNT : 12; +} REG_VGV3_NEXTCMD; + +// VGV3_VGBYPASS +typedef struct _REG_VGV3_VGBYPASS { + unsigned BYPASS : 1; +} REG_VGV3_VGBYPASS; + +// VGV3_WRITE +typedef struct _REG_VGV3_WRITE { + unsigned VALUE : 32; +} REG_VGV3_WRITE; + +// VGV3_WRITEADDR +typedef struct _REG_VGV3_WRITEADDR { + unsigned ADDR : 32; +} REG_VGV3_WRITEADDR; + +// VGV3_WRITEDMI +typedef struct _REG_VGV3_WRITEDMI { + unsigned CHANMASK : 4; + unsigned BUFFER : 3; +} REG_VGV3_WRITEDMI; + +// VGV3_WRITEF32 +typedef struct _REG_VGV3_WRITEF32 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITEF32; + +// VGV3_WRITEIFPAUSED +typedef struct _REG_VGV3_WRITEIFPAUSED { + unsigned VALUE : 32; +} REG_VGV3_WRITEIFPAUSED; + +// VGV3_WRITERAW +typedef struct _REG_VGV3_WRITERAW { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITERAW; + +// VGV3_WRITES16 +typedef struct _REG_VGV3_WRITES16 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITES16; + +// VGV3_WRITES32 +typedef struct _REG_VGV3_WRITES32 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITES32; + +// VGV3_WRITES8 +typedef struct _REG_VGV3_WRITES8 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITES8; + +// Register address, down shift, AND mask +#define FBC_BASE_BASE_FADDR ADDR_FBC_BASE +#define FBC_BASE_BASE_FSHIFT 0 +#define FBC_BASE_BASE_FMASK 0xffffffff +#define FBC_DATA_DATA_FADDR ADDR_FBC_DATA +#define FBC_DATA_DATA_FSHIFT 0 +#define FBC_DATA_DATA_FMASK 0xffffffff +#define FBC_HEIGHT_HEIGHT_FADDR ADDR_FBC_HEIGHT +#define FBC_HEIGHT_HEIGHT_FSHIFT 0 +#define FBC_HEIGHT_HEIGHT_FMASK 0x7ff +#define FBC_START_DUMMY_FADDR ADDR_FBC_START +#define FBC_START_DUMMY_FSHIFT 0 +#define FBC_START_DUMMY_FMASK 0x1 +#define FBC_STRIDE_STRIDE_FADDR ADDR_FBC_STRIDE +#define FBC_STRIDE_STRIDE_FSHIFT 0 +#define FBC_STRIDE_STRIDE_FMASK 0x7ff +#define FBC_WIDTH_WIDTH_FADDR ADDR_FBC_WIDTH +#define FBC_WIDTH_WIDTH_FSHIFT 0 +#define FBC_WIDTH_WIDTH_FMASK 0x7ff +#define VGC_CLOCKEN_BCACHE_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_BCACHE_FSHIFT 0 +#define VGC_CLOCKEN_BCACHE_FMASK 0x1 +#define VGC_CLOCKEN_G2D_VGL3_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_G2D_VGL3_FSHIFT 1 +#define VGC_CLOCKEN_G2D_VGL3_FMASK 0x1 +#define VGC_CLOCKEN_VG_L1L2_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_VG_L1L2_FSHIFT 2 +#define VGC_CLOCKEN_VG_L1L2_FMASK 0x1 +#define VGC_CLOCKEN_RESERVED_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_RESERVED_FSHIFT 3 +#define VGC_CLOCKEN_RESERVED_FMASK 0x7 +#define VGC_COMMANDSTREAM_DATA_FADDR ADDR_VGC_COMMANDSTREAM +#define VGC_COMMANDSTREAM_DATA_FSHIFT 0 +#define VGC_COMMANDSTREAM_DATA_FMASK 0xffffffff +#define VGC_FIFOFREE_FREE_FADDR ADDR_VGC_FIFOFREE +#define VGC_FIFOFREE_FREE_FSHIFT 0 +#define VGC_FIFOFREE_FREE_FMASK 0x1 +#define VGC_IRQENABLE_MH_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_MH_FSHIFT 0 +#define VGC_IRQENABLE_MH_FMASK 0x1 +#define VGC_IRQENABLE_G2D_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_G2D_FSHIFT 1 +#define VGC_IRQENABLE_G2D_FMASK 0x1 +#define VGC_IRQENABLE_FIFO_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_FIFO_FSHIFT 2 +#define VGC_IRQENABLE_FIFO_FMASK 0x1 +#define VGC_IRQENABLE_FBC_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_FBC_FSHIFT 3 +#define VGC_IRQENABLE_FBC_FMASK 0x1 +#define VGC_IRQSTATUS_MH_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_MH_FSHIFT 0 +#define VGC_IRQSTATUS_MH_FMASK 0x1 +#define VGC_IRQSTATUS_G2D_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_G2D_FSHIFT 1 +#define VGC_IRQSTATUS_G2D_FMASK 0x1 +#define VGC_IRQSTATUS_FIFO_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_FIFO_FSHIFT 2 +#define VGC_IRQSTATUS_FIFO_FMASK 0x1 +#define VGC_IRQSTATUS_FBC_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_FBC_FSHIFT 3 +#define VGC_IRQSTATUS_FBC_FMASK 0x1 +#define VGC_IRQ_ACTIVE_CNT_MH_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_MH_FSHIFT 0 +#define VGC_IRQ_ACTIVE_CNT_MH_FMASK 0xff +#define VGC_IRQ_ACTIVE_CNT_G2D_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_G2D_FSHIFT 8 +#define VGC_IRQ_ACTIVE_CNT_G2D_FMASK 0xff +#define VGC_IRQ_ACTIVE_CNT_ERRORS_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_ERRORS_FSHIFT 16 +#define VGC_IRQ_ACTIVE_CNT_ERRORS_FMASK 0xff +#define VGC_IRQ_ACTIVE_CNT_FBC_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_FBC_FSHIFT 24 +#define VGC_IRQ_ACTIVE_CNT_FBC_FMASK 0xff +#define VGC_MMUCOMMANDSTREAM_DATA_FADDR ADDR_VGC_MMUCOMMANDSTREAM +#define VGC_MMUCOMMANDSTREAM_DATA_FSHIFT 0 +#define VGC_MMUCOMMANDSTREAM_DATA_FMASK 0xffffffff +#define VGC_REVISION_MINOR_REVISION_FADDR ADDR_VGC_REVISION +#define VGC_REVISION_MINOR_REVISION_FSHIFT 0 +#define VGC_REVISION_MINOR_REVISION_FMASK 0xf +#define VGC_REVISION_MAJOR_REVISION_FADDR ADDR_VGC_REVISION +#define VGC_REVISION_MAJOR_REVISION_FSHIFT 4 +#define VGC_REVISION_MAJOR_REVISION_FMASK 0xf +#define VGC_SYSSTATUS_RESET_FADDR ADDR_VGC_SYSSTATUS +#define VGC_SYSSTATUS_RESET_FSHIFT 0 +#define VGC_SYSSTATUS_RESET_FMASK 0x1 +#define G2D_ALPHABLEND_ALPHA_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_ALPHA_FSHIFT 0 +#define G2D_ALPHABLEND_ALPHA_FMASK 0xff +#define G2D_ALPHABLEND_OBS_ENABLE_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_OBS_ENABLE_FSHIFT 8 +#define G2D_ALPHABLEND_OBS_ENABLE_FMASK 0x1 +#define G2D_ALPHABLEND_CONSTANT_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_CONSTANT_FSHIFT 9 +#define G2D_ALPHABLEND_CONSTANT_FMASK 0x1 +#define G2D_ALPHABLEND_INVERT_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_INVERT_FSHIFT 10 +#define G2D_ALPHABLEND_INVERT_FMASK 0x1 +#define G2D_ALPHABLEND_OPTIMIZE_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_OPTIMIZE_FSHIFT 11 +#define G2D_ALPHABLEND_OPTIMIZE_FMASK 0x1 +#define G2D_ALPHABLEND_MODULATE_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_MODULATE_FSHIFT 12 +#define G2D_ALPHABLEND_MODULATE_FMASK 0x1 +#define G2D_ALPHABLEND_INVERTMASK_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_INVERTMASK_FSHIFT 13 +#define G2D_ALPHABLEND_INVERTMASK_FMASK 0x1 +#define G2D_ALPHABLEND_PREMULTIPLYDST_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_PREMULTIPLYDST_FSHIFT 14 +#define G2D_ALPHABLEND_PREMULTIPLYDST_FMASK 0x1 +#define G2D_ALPHABLEND_MASKTOALPHA_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_MASKTOALPHA_FSHIFT 15 +#define G2D_ALPHABLEND_MASKTOALPHA_FMASK 0x1 +#define G2D_BACKGROUND_COLOR_FADDR ADDR_G2D_BACKGROUND +#define G2D_BACKGROUND_COLOR_FSHIFT 0 +#define G2D_BACKGROUND_COLOR_FMASK 0xffffffff +#define G2D_BASE0_ADDR_FADDR ADDR_G2D_BASE0 +#define G2D_BASE0_ADDR_FSHIFT 0 +#define G2D_BASE0_ADDR_FMASK 0xffffffff +#define G2D_BASE1_ADDR_FADDR ADDR_G2D_BASE1 +#define G2D_BASE1_ADDR_FSHIFT 0 +#define G2D_BASE1_ADDR_FMASK 0xffffffff +#define G2D_BASE2_ADDR_FADDR ADDR_G2D_BASE2 +#define G2D_BASE2_ADDR_FSHIFT 0 +#define G2D_BASE2_ADDR_FMASK 0xffffffff +#define G2D_BASE3_ADDR_FADDR ADDR_G2D_BASE3 +#define G2D_BASE3_ADDR_FSHIFT 0 +#define G2D_BASE3_ADDR_FMASK 0xffffffff +#define G2D_BLENDERCFG_PASSES_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_PASSES_FSHIFT 0 +#define G2D_BLENDERCFG_PASSES_FMASK 0x7 +#define G2D_BLENDERCFG_ALPHAPASSES_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_ALPHAPASSES_FSHIFT 3 +#define G2D_BLENDERCFG_ALPHAPASSES_FMASK 0x3 +#define G2D_BLENDERCFG_ENABLE_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_ENABLE_FSHIFT 5 +#define G2D_BLENDERCFG_ENABLE_FMASK 0x1 +#define G2D_BLENDERCFG_OOALPHA_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_OOALPHA_FSHIFT 6 +#define G2D_BLENDERCFG_OOALPHA_FMASK 0x1 +#define G2D_BLENDERCFG_OBS_DIVALPHA_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_OBS_DIVALPHA_FSHIFT 7 +#define G2D_BLENDERCFG_OBS_DIVALPHA_FMASK 0x1 +#define G2D_BLENDERCFG_NOMASK_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_NOMASK_FSHIFT 8 +#define G2D_BLENDERCFG_NOMASK_FMASK 0x1 +#define G2D_BLEND_A0_OPERATION_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_OPERATION_FSHIFT 0 +#define G2D_BLEND_A0_OPERATION_FMASK 0x3 +#define G2D_BLEND_A0_DST_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_DST_A_FSHIFT 2 +#define G2D_BLEND_A0_DST_A_FMASK 0x3 +#define G2D_BLEND_A0_DST_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_DST_B_FSHIFT 4 +#define G2D_BLEND_A0_DST_B_FMASK 0x3 +#define G2D_BLEND_A0_DST_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_DST_C_FSHIFT 6 +#define G2D_BLEND_A0_DST_C_FMASK 0x3 +#define G2D_BLEND_A0_AR_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_A_FSHIFT 8 +#define G2D_BLEND_A0_AR_A_FMASK 0x1 +#define G2D_BLEND_A0_AR_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_B_FSHIFT 9 +#define G2D_BLEND_A0_AR_B_FMASK 0x1 +#define G2D_BLEND_A0_AR_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_C_FSHIFT 10 +#define G2D_BLEND_A0_AR_C_FMASK 0x1 +#define G2D_BLEND_A0_AR_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_D_FSHIFT 11 +#define G2D_BLEND_A0_AR_D_FMASK 0x1 +#define G2D_BLEND_A0_INV_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_A_FSHIFT 12 +#define G2D_BLEND_A0_INV_A_FMASK 0x1 +#define G2D_BLEND_A0_INV_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_B_FSHIFT 13 +#define G2D_BLEND_A0_INV_B_FMASK 0x1 +#define G2D_BLEND_A0_INV_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_C_FSHIFT 14 +#define G2D_BLEND_A0_INV_C_FMASK 0x1 +#define G2D_BLEND_A0_INV_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_D_FSHIFT 15 +#define G2D_BLEND_A0_INV_D_FMASK 0x1 +#define G2D_BLEND_A0_SRC_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_A_FSHIFT 16 +#define G2D_BLEND_A0_SRC_A_FMASK 0x7 +#define G2D_BLEND_A0_SRC_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_B_FSHIFT 19 +#define G2D_BLEND_A0_SRC_B_FMASK 0x7 +#define G2D_BLEND_A0_SRC_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_C_FSHIFT 22 +#define G2D_BLEND_A0_SRC_C_FMASK 0x7 +#define G2D_BLEND_A0_SRC_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_D_FSHIFT 25 +#define G2D_BLEND_A0_SRC_D_FMASK 0x7 +#define G2D_BLEND_A0_CONST_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_A_FSHIFT 28 +#define G2D_BLEND_A0_CONST_A_FMASK 0x1 +#define G2D_BLEND_A0_CONST_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_B_FSHIFT 29 +#define G2D_BLEND_A0_CONST_B_FMASK 0x1 +#define G2D_BLEND_A0_CONST_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_C_FSHIFT 30 +#define G2D_BLEND_A0_CONST_C_FMASK 0x1 +#define G2D_BLEND_A0_CONST_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_D_FSHIFT 31 +#define G2D_BLEND_A0_CONST_D_FMASK 0x1 +#define G2D_BLEND_A1_OPERATION_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_OPERATION_FSHIFT 0 +#define G2D_BLEND_A1_OPERATION_FMASK 0x3 +#define G2D_BLEND_A1_DST_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_DST_A_FSHIFT 2 +#define G2D_BLEND_A1_DST_A_FMASK 0x3 +#define G2D_BLEND_A1_DST_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_DST_B_FSHIFT 4 +#define G2D_BLEND_A1_DST_B_FMASK 0x3 +#define G2D_BLEND_A1_DST_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_DST_C_FSHIFT 6 +#define G2D_BLEND_A1_DST_C_FMASK 0x3 +#define G2D_BLEND_A1_AR_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_A_FSHIFT 8 +#define G2D_BLEND_A1_AR_A_FMASK 0x1 +#define G2D_BLEND_A1_AR_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_B_FSHIFT 9 +#define G2D_BLEND_A1_AR_B_FMASK 0x1 +#define G2D_BLEND_A1_AR_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_C_FSHIFT 10 +#define G2D_BLEND_A1_AR_C_FMASK 0x1 +#define G2D_BLEND_A1_AR_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_D_FSHIFT 11 +#define G2D_BLEND_A1_AR_D_FMASK 0x1 +#define G2D_BLEND_A1_INV_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_A_FSHIFT 12 +#define G2D_BLEND_A1_INV_A_FMASK 0x1 +#define G2D_BLEND_A1_INV_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_B_FSHIFT 13 +#define G2D_BLEND_A1_INV_B_FMASK 0x1 +#define G2D_BLEND_A1_INV_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_C_FSHIFT 14 +#define G2D_BLEND_A1_INV_C_FMASK 0x1 +#define G2D_BLEND_A1_INV_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_D_FSHIFT 15 +#define G2D_BLEND_A1_INV_D_FMASK 0x1 +#define G2D_BLEND_A1_SRC_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_A_FSHIFT 16 +#define G2D_BLEND_A1_SRC_A_FMASK 0x7 +#define G2D_BLEND_A1_SRC_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_B_FSHIFT 19 +#define G2D_BLEND_A1_SRC_B_FMASK 0x7 +#define G2D_BLEND_A1_SRC_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_C_FSHIFT 22 +#define G2D_BLEND_A1_SRC_C_FMASK 0x7 +#define G2D_BLEND_A1_SRC_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_D_FSHIFT 25 +#define G2D_BLEND_A1_SRC_D_FMASK 0x7 +#define G2D_BLEND_A1_CONST_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_A_FSHIFT 28 +#define G2D_BLEND_A1_CONST_A_FMASK 0x1 +#define G2D_BLEND_A1_CONST_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_B_FSHIFT 29 +#define G2D_BLEND_A1_CONST_B_FMASK 0x1 +#define G2D_BLEND_A1_CONST_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_C_FSHIFT 30 +#define G2D_BLEND_A1_CONST_C_FMASK 0x1 +#define G2D_BLEND_A1_CONST_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_D_FSHIFT 31 +#define G2D_BLEND_A1_CONST_D_FMASK 0x1 +#define G2D_BLEND_A2_OPERATION_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_OPERATION_FSHIFT 0 +#define G2D_BLEND_A2_OPERATION_FMASK 0x3 +#define G2D_BLEND_A2_DST_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_DST_A_FSHIFT 2 +#define G2D_BLEND_A2_DST_A_FMASK 0x3 +#define G2D_BLEND_A2_DST_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_DST_B_FSHIFT 4 +#define G2D_BLEND_A2_DST_B_FMASK 0x3 +#define G2D_BLEND_A2_DST_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_DST_C_FSHIFT 6 +#define G2D_BLEND_A2_DST_C_FMASK 0x3 +#define G2D_BLEND_A2_AR_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_A_FSHIFT 8 +#define G2D_BLEND_A2_AR_A_FMASK 0x1 +#define G2D_BLEND_A2_AR_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_B_FSHIFT 9 +#define G2D_BLEND_A2_AR_B_FMASK 0x1 +#define G2D_BLEND_A2_AR_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_C_FSHIFT 10 +#define G2D_BLEND_A2_AR_C_FMASK 0x1 +#define G2D_BLEND_A2_AR_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_D_FSHIFT 11 +#define G2D_BLEND_A2_AR_D_FMASK 0x1 +#define G2D_BLEND_A2_INV_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_A_FSHIFT 12 +#define G2D_BLEND_A2_INV_A_FMASK 0x1 +#define G2D_BLEND_A2_INV_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_B_FSHIFT 13 +#define G2D_BLEND_A2_INV_B_FMASK 0x1 +#define G2D_BLEND_A2_INV_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_C_FSHIFT 14 +#define G2D_BLEND_A2_INV_C_FMASK 0x1 +#define G2D_BLEND_A2_INV_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_D_FSHIFT 15 +#define G2D_BLEND_A2_INV_D_FMASK 0x1 +#define G2D_BLEND_A2_SRC_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_A_FSHIFT 16 +#define G2D_BLEND_A2_SRC_A_FMASK 0x7 +#define G2D_BLEND_A2_SRC_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_B_FSHIFT 19 +#define G2D_BLEND_A2_SRC_B_FMASK 0x7 +#define G2D_BLEND_A2_SRC_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_C_FSHIFT 22 +#define G2D_BLEND_A2_SRC_C_FMASK 0x7 +#define G2D_BLEND_A2_SRC_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_D_FSHIFT 25 +#define G2D_BLEND_A2_SRC_D_FMASK 0x7 +#define G2D_BLEND_A2_CONST_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_A_FSHIFT 28 +#define G2D_BLEND_A2_CONST_A_FMASK 0x1 +#define G2D_BLEND_A2_CONST_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_B_FSHIFT 29 +#define G2D_BLEND_A2_CONST_B_FMASK 0x1 +#define G2D_BLEND_A2_CONST_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_C_FSHIFT 30 +#define G2D_BLEND_A2_CONST_C_FMASK 0x1 +#define G2D_BLEND_A2_CONST_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_D_FSHIFT 31 +#define G2D_BLEND_A2_CONST_D_FMASK 0x1 +#define G2D_BLEND_A3_OPERATION_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_OPERATION_FSHIFT 0 +#define G2D_BLEND_A3_OPERATION_FMASK 0x3 +#define G2D_BLEND_A3_DST_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_DST_A_FSHIFT 2 +#define G2D_BLEND_A3_DST_A_FMASK 0x3 +#define G2D_BLEND_A3_DST_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_DST_B_FSHIFT 4 +#define G2D_BLEND_A3_DST_B_FMASK 0x3 +#define G2D_BLEND_A3_DST_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_DST_C_FSHIFT 6 +#define G2D_BLEND_A3_DST_C_FMASK 0x3 +#define G2D_BLEND_A3_AR_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_A_FSHIFT 8 +#define G2D_BLEND_A3_AR_A_FMASK 0x1 +#define G2D_BLEND_A3_AR_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_B_FSHIFT 9 +#define G2D_BLEND_A3_AR_B_FMASK 0x1 +#define G2D_BLEND_A3_AR_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_C_FSHIFT 10 +#define G2D_BLEND_A3_AR_C_FMASK 0x1 +#define G2D_BLEND_A3_AR_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_D_FSHIFT 11 +#define G2D_BLEND_A3_AR_D_FMASK 0x1 +#define G2D_BLEND_A3_INV_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_A_FSHIFT 12 +#define G2D_BLEND_A3_INV_A_FMASK 0x1 +#define G2D_BLEND_A3_INV_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_B_FSHIFT 13 +#define G2D_BLEND_A3_INV_B_FMASK 0x1 +#define G2D_BLEND_A3_INV_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_C_FSHIFT 14 +#define G2D_BLEND_A3_INV_C_FMASK 0x1 +#define G2D_BLEND_A3_INV_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_D_FSHIFT 15 +#define G2D_BLEND_A3_INV_D_FMASK 0x1 +#define G2D_BLEND_A3_SRC_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_A_FSHIFT 16 +#define G2D_BLEND_A3_SRC_A_FMASK 0x7 +#define G2D_BLEND_A3_SRC_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_B_FSHIFT 19 +#define G2D_BLEND_A3_SRC_B_FMASK 0x7 +#define G2D_BLEND_A3_SRC_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_C_FSHIFT 22 +#define G2D_BLEND_A3_SRC_C_FMASK 0x7 +#define G2D_BLEND_A3_SRC_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_D_FSHIFT 25 +#define G2D_BLEND_A3_SRC_D_FMASK 0x7 +#define G2D_BLEND_A3_CONST_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_A_FSHIFT 28 +#define G2D_BLEND_A3_CONST_A_FMASK 0x1 +#define G2D_BLEND_A3_CONST_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_B_FSHIFT 29 +#define G2D_BLEND_A3_CONST_B_FMASK 0x1 +#define G2D_BLEND_A3_CONST_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_C_FSHIFT 30 +#define G2D_BLEND_A3_CONST_C_FMASK 0x1 +#define G2D_BLEND_A3_CONST_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_D_FSHIFT 31 +#define G2D_BLEND_A3_CONST_D_FMASK 0x1 +#define G2D_BLEND_C0_OPERATION_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_OPERATION_FSHIFT 0 +#define G2D_BLEND_C0_OPERATION_FMASK 0x3 +#define G2D_BLEND_C0_DST_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_DST_A_FSHIFT 2 +#define G2D_BLEND_C0_DST_A_FMASK 0x3 +#define G2D_BLEND_C0_DST_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_DST_B_FSHIFT 4 +#define G2D_BLEND_C0_DST_B_FMASK 0x3 +#define G2D_BLEND_C0_DST_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_DST_C_FSHIFT 6 +#define G2D_BLEND_C0_DST_C_FMASK 0x3 +#define G2D_BLEND_C0_AR_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_A_FSHIFT 8 +#define G2D_BLEND_C0_AR_A_FMASK 0x1 +#define G2D_BLEND_C0_AR_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_B_FSHIFT 9 +#define G2D_BLEND_C0_AR_B_FMASK 0x1 +#define G2D_BLEND_C0_AR_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_C_FSHIFT 10 +#define G2D_BLEND_C0_AR_C_FMASK 0x1 +#define G2D_BLEND_C0_AR_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_D_FSHIFT 11 +#define G2D_BLEND_C0_AR_D_FMASK 0x1 +#define G2D_BLEND_C0_INV_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_A_FSHIFT 12 +#define G2D_BLEND_C0_INV_A_FMASK 0x1 +#define G2D_BLEND_C0_INV_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_B_FSHIFT 13 +#define G2D_BLEND_C0_INV_B_FMASK 0x1 +#define G2D_BLEND_C0_INV_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_C_FSHIFT 14 +#define G2D_BLEND_C0_INV_C_FMASK 0x1 +#define G2D_BLEND_C0_INV_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_D_FSHIFT 15 +#define G2D_BLEND_C0_INV_D_FMASK 0x1 +#define G2D_BLEND_C0_SRC_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_A_FSHIFT 16 +#define G2D_BLEND_C0_SRC_A_FMASK 0x7 +#define G2D_BLEND_C0_SRC_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_B_FSHIFT 19 +#define G2D_BLEND_C0_SRC_B_FMASK 0x7 +#define G2D_BLEND_C0_SRC_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_C_FSHIFT 22 +#define G2D_BLEND_C0_SRC_C_FMASK 0x7 +#define G2D_BLEND_C0_SRC_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_D_FSHIFT 25 +#define G2D_BLEND_C0_SRC_D_FMASK 0x7 +#define G2D_BLEND_C0_CONST_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_A_FSHIFT 28 +#define G2D_BLEND_C0_CONST_A_FMASK 0x1 +#define G2D_BLEND_C0_CONST_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_B_FSHIFT 29 +#define G2D_BLEND_C0_CONST_B_FMASK 0x1 +#define G2D_BLEND_C0_CONST_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_C_FSHIFT 30 +#define G2D_BLEND_C0_CONST_C_FMASK 0x1 +#define G2D_BLEND_C0_CONST_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_D_FSHIFT 31 +#define G2D_BLEND_C0_CONST_D_FMASK 0x1 +#define G2D_BLEND_C1_OPERATION_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_OPERATION_FSHIFT 0 +#define G2D_BLEND_C1_OPERATION_FMASK 0x3 +#define G2D_BLEND_C1_DST_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_DST_A_FSHIFT 2 +#define G2D_BLEND_C1_DST_A_FMASK 0x3 +#define G2D_BLEND_C1_DST_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_DST_B_FSHIFT 4 +#define G2D_BLEND_C1_DST_B_FMASK 0x3 +#define G2D_BLEND_C1_DST_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_DST_C_FSHIFT 6 +#define G2D_BLEND_C1_DST_C_FMASK 0x3 +#define G2D_BLEND_C1_AR_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_A_FSHIFT 8 +#define G2D_BLEND_C1_AR_A_FMASK 0x1 +#define G2D_BLEND_C1_AR_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_B_FSHIFT 9 +#define G2D_BLEND_C1_AR_B_FMASK 0x1 +#define G2D_BLEND_C1_AR_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_C_FSHIFT 10 +#define G2D_BLEND_C1_AR_C_FMASK 0x1 +#define G2D_BLEND_C1_AR_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_D_FSHIFT 11 +#define G2D_BLEND_C1_AR_D_FMASK 0x1 +#define G2D_BLEND_C1_INV_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_A_FSHIFT 12 +#define G2D_BLEND_C1_INV_A_FMASK 0x1 +#define G2D_BLEND_C1_INV_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_B_FSHIFT 13 +#define G2D_BLEND_C1_INV_B_FMASK 0x1 +#define G2D_BLEND_C1_INV_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_C_FSHIFT 14 +#define G2D_BLEND_C1_INV_C_FMASK 0x1 +#define G2D_BLEND_C1_INV_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_D_FSHIFT 15 +#define G2D_BLEND_C1_INV_D_FMASK 0x1 +#define G2D_BLEND_C1_SRC_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_A_FSHIFT 16 +#define G2D_BLEND_C1_SRC_A_FMASK 0x7 +#define G2D_BLEND_C1_SRC_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_B_FSHIFT 19 +#define G2D_BLEND_C1_SRC_B_FMASK 0x7 +#define G2D_BLEND_C1_SRC_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_C_FSHIFT 22 +#define G2D_BLEND_C1_SRC_C_FMASK 0x7 +#define G2D_BLEND_C1_SRC_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_D_FSHIFT 25 +#define G2D_BLEND_C1_SRC_D_FMASK 0x7 +#define G2D_BLEND_C1_CONST_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_A_FSHIFT 28 +#define G2D_BLEND_C1_CONST_A_FMASK 0x1 +#define G2D_BLEND_C1_CONST_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_B_FSHIFT 29 +#define G2D_BLEND_C1_CONST_B_FMASK 0x1 +#define G2D_BLEND_C1_CONST_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_C_FSHIFT 30 +#define G2D_BLEND_C1_CONST_C_FMASK 0x1 +#define G2D_BLEND_C1_CONST_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_D_FSHIFT 31 +#define G2D_BLEND_C1_CONST_D_FMASK 0x1 +#define G2D_BLEND_C2_OPERATION_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_OPERATION_FSHIFT 0 +#define G2D_BLEND_C2_OPERATION_FMASK 0x3 +#define G2D_BLEND_C2_DST_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_DST_A_FSHIFT 2 +#define G2D_BLEND_C2_DST_A_FMASK 0x3 +#define G2D_BLEND_C2_DST_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_DST_B_FSHIFT 4 +#define G2D_BLEND_C2_DST_B_FMASK 0x3 +#define G2D_BLEND_C2_DST_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_DST_C_FSHIFT 6 +#define G2D_BLEND_C2_DST_C_FMASK 0x3 +#define G2D_BLEND_C2_AR_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_A_FSHIFT 8 +#define G2D_BLEND_C2_AR_A_FMASK 0x1 +#define G2D_BLEND_C2_AR_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_B_FSHIFT 9 +#define G2D_BLEND_C2_AR_B_FMASK 0x1 +#define G2D_BLEND_C2_AR_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_C_FSHIFT 10 +#define G2D_BLEND_C2_AR_C_FMASK 0x1 +#define G2D_BLEND_C2_AR_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_D_FSHIFT 11 +#define G2D_BLEND_C2_AR_D_FMASK 0x1 +#define G2D_BLEND_C2_INV_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_A_FSHIFT 12 +#define G2D_BLEND_C2_INV_A_FMASK 0x1 +#define G2D_BLEND_C2_INV_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_B_FSHIFT 13 +#define G2D_BLEND_C2_INV_B_FMASK 0x1 +#define G2D_BLEND_C2_INV_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_C_FSHIFT 14 +#define G2D_BLEND_C2_INV_C_FMASK 0x1 +#define G2D_BLEND_C2_INV_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_D_FSHIFT 15 +#define G2D_BLEND_C2_INV_D_FMASK 0x1 +#define G2D_BLEND_C2_SRC_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_A_FSHIFT 16 +#define G2D_BLEND_C2_SRC_A_FMASK 0x7 +#define G2D_BLEND_C2_SRC_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_B_FSHIFT 19 +#define G2D_BLEND_C2_SRC_B_FMASK 0x7 +#define G2D_BLEND_C2_SRC_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_C_FSHIFT 22 +#define G2D_BLEND_C2_SRC_C_FMASK 0x7 +#define G2D_BLEND_C2_SRC_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_D_FSHIFT 25 +#define G2D_BLEND_C2_SRC_D_FMASK 0x7 +#define G2D_BLEND_C2_CONST_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_A_FSHIFT 28 +#define G2D_BLEND_C2_CONST_A_FMASK 0x1 +#define G2D_BLEND_C2_CONST_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_B_FSHIFT 29 +#define G2D_BLEND_C2_CONST_B_FMASK 0x1 +#define G2D_BLEND_C2_CONST_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_C_FSHIFT 30 +#define G2D_BLEND_C2_CONST_C_FMASK 0x1 +#define G2D_BLEND_C2_CONST_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_D_FSHIFT 31 +#define G2D_BLEND_C2_CONST_D_FMASK 0x1 +#define G2D_BLEND_C3_OPERATION_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_OPERATION_FSHIFT 0 +#define G2D_BLEND_C3_OPERATION_FMASK 0x3 +#define G2D_BLEND_C3_DST_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_DST_A_FSHIFT 2 +#define G2D_BLEND_C3_DST_A_FMASK 0x3 +#define G2D_BLEND_C3_DST_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_DST_B_FSHIFT 4 +#define G2D_BLEND_C3_DST_B_FMASK 0x3 +#define G2D_BLEND_C3_DST_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_DST_C_FSHIFT 6 +#define G2D_BLEND_C3_DST_C_FMASK 0x3 +#define G2D_BLEND_C3_AR_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_A_FSHIFT 8 +#define G2D_BLEND_C3_AR_A_FMASK 0x1 +#define G2D_BLEND_C3_AR_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_B_FSHIFT 9 +#define G2D_BLEND_C3_AR_B_FMASK 0x1 +#define G2D_BLEND_C3_AR_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_C_FSHIFT 10 +#define G2D_BLEND_C3_AR_C_FMASK 0x1 +#define G2D_BLEND_C3_AR_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_D_FSHIFT 11 +#define G2D_BLEND_C3_AR_D_FMASK 0x1 +#define G2D_BLEND_C3_INV_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_A_FSHIFT 12 +#define G2D_BLEND_C3_INV_A_FMASK 0x1 +#define G2D_BLEND_C3_INV_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_B_FSHIFT 13 +#define G2D_BLEND_C3_INV_B_FMASK 0x1 +#define G2D_BLEND_C3_INV_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_C_FSHIFT 14 +#define G2D_BLEND_C3_INV_C_FMASK 0x1 +#define G2D_BLEND_C3_INV_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_D_FSHIFT 15 +#define G2D_BLEND_C3_INV_D_FMASK 0x1 +#define G2D_BLEND_C3_SRC_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_A_FSHIFT 16 +#define G2D_BLEND_C3_SRC_A_FMASK 0x7 +#define G2D_BLEND_C3_SRC_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_B_FSHIFT 19 +#define G2D_BLEND_C3_SRC_B_FMASK 0x7 +#define G2D_BLEND_C3_SRC_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_C_FSHIFT 22 +#define G2D_BLEND_C3_SRC_C_FMASK 0x7 +#define G2D_BLEND_C3_SRC_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_D_FSHIFT 25 +#define G2D_BLEND_C3_SRC_D_FMASK 0x7 +#define G2D_BLEND_C3_CONST_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_A_FSHIFT 28 +#define G2D_BLEND_C3_CONST_A_FMASK 0x1 +#define G2D_BLEND_C3_CONST_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_B_FSHIFT 29 +#define G2D_BLEND_C3_CONST_B_FMASK 0x1 +#define G2D_BLEND_C3_CONST_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_C_FSHIFT 30 +#define G2D_BLEND_C3_CONST_C_FMASK 0x1 +#define G2D_BLEND_C3_CONST_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_D_FSHIFT 31 +#define G2D_BLEND_C3_CONST_D_FMASK 0x1 +#define G2D_BLEND_C4_OPERATION_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_OPERATION_FSHIFT 0 +#define G2D_BLEND_C4_OPERATION_FMASK 0x3 +#define G2D_BLEND_C4_DST_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_DST_A_FSHIFT 2 +#define G2D_BLEND_C4_DST_A_FMASK 0x3 +#define G2D_BLEND_C4_DST_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_DST_B_FSHIFT 4 +#define G2D_BLEND_C4_DST_B_FMASK 0x3 +#define G2D_BLEND_C4_DST_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_DST_C_FSHIFT 6 +#define G2D_BLEND_C4_DST_C_FMASK 0x3 +#define G2D_BLEND_C4_AR_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_A_FSHIFT 8 +#define G2D_BLEND_C4_AR_A_FMASK 0x1 +#define G2D_BLEND_C4_AR_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_B_FSHIFT 9 +#define G2D_BLEND_C4_AR_B_FMASK 0x1 +#define G2D_BLEND_C4_AR_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_C_FSHIFT 10 +#define G2D_BLEND_C4_AR_C_FMASK 0x1 +#define G2D_BLEND_C4_AR_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_D_FSHIFT 11 +#define G2D_BLEND_C4_AR_D_FMASK 0x1 +#define G2D_BLEND_C4_INV_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_A_FSHIFT 12 +#define G2D_BLEND_C4_INV_A_FMASK 0x1 +#define G2D_BLEND_C4_INV_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_B_FSHIFT 13 +#define G2D_BLEND_C4_INV_B_FMASK 0x1 +#define G2D_BLEND_C4_INV_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_C_FSHIFT 14 +#define G2D_BLEND_C4_INV_C_FMASK 0x1 +#define G2D_BLEND_C4_INV_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_D_FSHIFT 15 +#define G2D_BLEND_C4_INV_D_FMASK 0x1 +#define G2D_BLEND_C4_SRC_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_A_FSHIFT 16 +#define G2D_BLEND_C4_SRC_A_FMASK 0x7 +#define G2D_BLEND_C4_SRC_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_B_FSHIFT 19 +#define G2D_BLEND_C4_SRC_B_FMASK 0x7 +#define G2D_BLEND_C4_SRC_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_C_FSHIFT 22 +#define G2D_BLEND_C4_SRC_C_FMASK 0x7 +#define G2D_BLEND_C4_SRC_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_D_FSHIFT 25 +#define G2D_BLEND_C4_SRC_D_FMASK 0x7 +#define G2D_BLEND_C4_CONST_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_A_FSHIFT 28 +#define G2D_BLEND_C4_CONST_A_FMASK 0x1 +#define G2D_BLEND_C4_CONST_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_B_FSHIFT 29 +#define G2D_BLEND_C4_CONST_B_FMASK 0x1 +#define G2D_BLEND_C4_CONST_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_C_FSHIFT 30 +#define G2D_BLEND_C4_CONST_C_FMASK 0x1 +#define G2D_BLEND_C4_CONST_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_D_FSHIFT 31 +#define G2D_BLEND_C4_CONST_D_FMASK 0x1 +#define G2D_BLEND_C5_OPERATION_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_OPERATION_FSHIFT 0 +#define G2D_BLEND_C5_OPERATION_FMASK 0x3 +#define G2D_BLEND_C5_DST_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_DST_A_FSHIFT 2 +#define G2D_BLEND_C5_DST_A_FMASK 0x3 +#define G2D_BLEND_C5_DST_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_DST_B_FSHIFT 4 +#define G2D_BLEND_C5_DST_B_FMASK 0x3 +#define G2D_BLEND_C5_DST_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_DST_C_FSHIFT 6 +#define G2D_BLEND_C5_DST_C_FMASK 0x3 +#define G2D_BLEND_C5_AR_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_A_FSHIFT 8 +#define G2D_BLEND_C5_AR_A_FMASK 0x1 +#define G2D_BLEND_C5_AR_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_B_FSHIFT 9 +#define G2D_BLEND_C5_AR_B_FMASK 0x1 +#define G2D_BLEND_C5_AR_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_C_FSHIFT 10 +#define G2D_BLEND_C5_AR_C_FMASK 0x1 +#define G2D_BLEND_C5_AR_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_D_FSHIFT 11 +#define G2D_BLEND_C5_AR_D_FMASK 0x1 +#define G2D_BLEND_C5_INV_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_A_FSHIFT 12 +#define G2D_BLEND_C5_INV_A_FMASK 0x1 +#define G2D_BLEND_C5_INV_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_B_FSHIFT 13 +#define G2D_BLEND_C5_INV_B_FMASK 0x1 +#define G2D_BLEND_C5_INV_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_C_FSHIFT 14 +#define G2D_BLEND_C5_INV_C_FMASK 0x1 +#define G2D_BLEND_C5_INV_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_D_FSHIFT 15 +#define G2D_BLEND_C5_INV_D_FMASK 0x1 +#define G2D_BLEND_C5_SRC_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_A_FSHIFT 16 +#define G2D_BLEND_C5_SRC_A_FMASK 0x7 +#define G2D_BLEND_C5_SRC_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_B_FSHIFT 19 +#define G2D_BLEND_C5_SRC_B_FMASK 0x7 +#define G2D_BLEND_C5_SRC_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_C_FSHIFT 22 +#define G2D_BLEND_C5_SRC_C_FMASK 0x7 +#define G2D_BLEND_C5_SRC_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_D_FSHIFT 25 +#define G2D_BLEND_C5_SRC_D_FMASK 0x7 +#define G2D_BLEND_C5_CONST_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_A_FSHIFT 28 +#define G2D_BLEND_C5_CONST_A_FMASK 0x1 +#define G2D_BLEND_C5_CONST_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_B_FSHIFT 29 +#define G2D_BLEND_C5_CONST_B_FMASK 0x1 +#define G2D_BLEND_C5_CONST_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_C_FSHIFT 30 +#define G2D_BLEND_C5_CONST_C_FMASK 0x1 +#define G2D_BLEND_C5_CONST_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_D_FSHIFT 31 +#define G2D_BLEND_C5_CONST_D_FMASK 0x1 +#define G2D_BLEND_C6_OPERATION_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_OPERATION_FSHIFT 0 +#define G2D_BLEND_C6_OPERATION_FMASK 0x3 +#define G2D_BLEND_C6_DST_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_DST_A_FSHIFT 2 +#define G2D_BLEND_C6_DST_A_FMASK 0x3 +#define G2D_BLEND_C6_DST_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_DST_B_FSHIFT 4 +#define G2D_BLEND_C6_DST_B_FMASK 0x3 +#define G2D_BLEND_C6_DST_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_DST_C_FSHIFT 6 +#define G2D_BLEND_C6_DST_C_FMASK 0x3 +#define G2D_BLEND_C6_AR_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_A_FSHIFT 8 +#define G2D_BLEND_C6_AR_A_FMASK 0x1 +#define G2D_BLEND_C6_AR_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_B_FSHIFT 9 +#define G2D_BLEND_C6_AR_B_FMASK 0x1 +#define G2D_BLEND_C6_AR_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_C_FSHIFT 10 +#define G2D_BLEND_C6_AR_C_FMASK 0x1 +#define G2D_BLEND_C6_AR_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_D_FSHIFT 11 +#define G2D_BLEND_C6_AR_D_FMASK 0x1 +#define G2D_BLEND_C6_INV_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_A_FSHIFT 12 +#define G2D_BLEND_C6_INV_A_FMASK 0x1 +#define G2D_BLEND_C6_INV_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_B_FSHIFT 13 +#define G2D_BLEND_C6_INV_B_FMASK 0x1 +#define G2D_BLEND_C6_INV_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_C_FSHIFT 14 +#define G2D_BLEND_C6_INV_C_FMASK 0x1 +#define G2D_BLEND_C6_INV_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_D_FSHIFT 15 +#define G2D_BLEND_C6_INV_D_FMASK 0x1 +#define G2D_BLEND_C6_SRC_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_A_FSHIFT 16 +#define G2D_BLEND_C6_SRC_A_FMASK 0x7 +#define G2D_BLEND_C6_SRC_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_B_FSHIFT 19 +#define G2D_BLEND_C6_SRC_B_FMASK 0x7 +#define G2D_BLEND_C6_SRC_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_C_FSHIFT 22 +#define G2D_BLEND_C6_SRC_C_FMASK 0x7 +#define G2D_BLEND_C6_SRC_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_D_FSHIFT 25 +#define G2D_BLEND_C6_SRC_D_FMASK 0x7 +#define G2D_BLEND_C6_CONST_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_A_FSHIFT 28 +#define G2D_BLEND_C6_CONST_A_FMASK 0x1 +#define G2D_BLEND_C6_CONST_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_B_FSHIFT 29 +#define G2D_BLEND_C6_CONST_B_FMASK 0x1 +#define G2D_BLEND_C6_CONST_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_C_FSHIFT 30 +#define G2D_BLEND_C6_CONST_C_FMASK 0x1 +#define G2D_BLEND_C6_CONST_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_D_FSHIFT 31 +#define G2D_BLEND_C6_CONST_D_FMASK 0x1 +#define G2D_BLEND_C7_OPERATION_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_OPERATION_FSHIFT 0 +#define G2D_BLEND_C7_OPERATION_FMASK 0x3 +#define G2D_BLEND_C7_DST_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_DST_A_FSHIFT 2 +#define G2D_BLEND_C7_DST_A_FMASK 0x3 +#define G2D_BLEND_C7_DST_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_DST_B_FSHIFT 4 +#define G2D_BLEND_C7_DST_B_FMASK 0x3 +#define G2D_BLEND_C7_DST_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_DST_C_FSHIFT 6 +#define G2D_BLEND_C7_DST_C_FMASK 0x3 +#define G2D_BLEND_C7_AR_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_A_FSHIFT 8 +#define G2D_BLEND_C7_AR_A_FMASK 0x1 +#define G2D_BLEND_C7_AR_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_B_FSHIFT 9 +#define G2D_BLEND_C7_AR_B_FMASK 0x1 +#define G2D_BLEND_C7_AR_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_C_FSHIFT 10 +#define G2D_BLEND_C7_AR_C_FMASK 0x1 +#define G2D_BLEND_C7_AR_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_D_FSHIFT 11 +#define G2D_BLEND_C7_AR_D_FMASK 0x1 +#define G2D_BLEND_C7_INV_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_A_FSHIFT 12 +#define G2D_BLEND_C7_INV_A_FMASK 0x1 +#define G2D_BLEND_C7_INV_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_B_FSHIFT 13 +#define G2D_BLEND_C7_INV_B_FMASK 0x1 +#define G2D_BLEND_C7_INV_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_C_FSHIFT 14 +#define G2D_BLEND_C7_INV_C_FMASK 0x1 +#define G2D_BLEND_C7_INV_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_D_FSHIFT 15 +#define G2D_BLEND_C7_INV_D_FMASK 0x1 +#define G2D_BLEND_C7_SRC_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_A_FSHIFT 16 +#define G2D_BLEND_C7_SRC_A_FMASK 0x7 +#define G2D_BLEND_C7_SRC_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_B_FSHIFT 19 +#define G2D_BLEND_C7_SRC_B_FMASK 0x7 +#define G2D_BLEND_C7_SRC_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_C_FSHIFT 22 +#define G2D_BLEND_C7_SRC_C_FMASK 0x7 +#define G2D_BLEND_C7_SRC_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_D_FSHIFT 25 +#define G2D_BLEND_C7_SRC_D_FMASK 0x7 +#define G2D_BLEND_C7_CONST_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_A_FSHIFT 28 +#define G2D_BLEND_C7_CONST_A_FMASK 0x1 +#define G2D_BLEND_C7_CONST_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_B_FSHIFT 29 +#define G2D_BLEND_C7_CONST_B_FMASK 0x1 +#define G2D_BLEND_C7_CONST_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_C_FSHIFT 30 +#define G2D_BLEND_C7_CONST_C_FMASK 0x1 +#define G2D_BLEND_C7_CONST_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_D_FSHIFT 31 +#define G2D_BLEND_C7_CONST_D_FMASK 0x1 +#define G2D_CFG0_STRIDE_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_STRIDE_FSHIFT 0 +#define G2D_CFG0_STRIDE_FMASK 0xfff +#define G2D_CFG0_FORMAT_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_FORMAT_FSHIFT 12 +#define G2D_CFG0_FORMAT_FMASK 0xf +#define G2D_CFG0_TILED_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_TILED_FSHIFT 16 +#define G2D_CFG0_TILED_FMASK 0x1 +#define G2D_CFG0_SRGB_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SRGB_FSHIFT 17 +#define G2D_CFG0_SRGB_FMASK 0x1 +#define G2D_CFG0_SWAPWORDS_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPWORDS_FSHIFT 18 +#define G2D_CFG0_SWAPWORDS_FMASK 0x1 +#define G2D_CFG0_SWAPBYTES_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPBYTES_FSHIFT 19 +#define G2D_CFG0_SWAPBYTES_FMASK 0x1 +#define G2D_CFG0_SWAPALL_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPALL_FSHIFT 20 +#define G2D_CFG0_SWAPALL_FMASK 0x1 +#define G2D_CFG0_SWAPRB_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPRB_FSHIFT 21 +#define G2D_CFG0_SWAPRB_FMASK 0x1 +#define G2D_CFG0_SWAPBITS_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPBITS_FSHIFT 22 +#define G2D_CFG0_SWAPBITS_FMASK 0x1 +#define G2D_CFG0_STRIDESIGN_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_STRIDESIGN_FSHIFT 23 +#define G2D_CFG0_STRIDESIGN_FMASK 0x1 +#define G2D_CFG1_STRIDE_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_STRIDE_FSHIFT 0 +#define G2D_CFG1_STRIDE_FMASK 0xfff +#define G2D_CFG1_FORMAT_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_FORMAT_FSHIFT 12 +#define G2D_CFG1_FORMAT_FMASK 0xf +#define G2D_CFG1_TILED_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_TILED_FSHIFT 16 +#define G2D_CFG1_TILED_FMASK 0x1 +#define G2D_CFG1_SRGB_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SRGB_FSHIFT 17 +#define G2D_CFG1_SRGB_FMASK 0x1 +#define G2D_CFG1_SWAPWORDS_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPWORDS_FSHIFT 18 +#define G2D_CFG1_SWAPWORDS_FMASK 0x1 +#define G2D_CFG1_SWAPBYTES_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPBYTES_FSHIFT 19 +#define G2D_CFG1_SWAPBYTES_FMASK 0x1 +#define G2D_CFG1_SWAPALL_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPALL_FSHIFT 20 +#define G2D_CFG1_SWAPALL_FMASK 0x1 +#define G2D_CFG1_SWAPRB_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPRB_FSHIFT 21 +#define G2D_CFG1_SWAPRB_FMASK 0x1 +#define G2D_CFG1_SWAPBITS_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPBITS_FSHIFT 22 +#define G2D_CFG1_SWAPBITS_FMASK 0x1 +#define G2D_CFG1_STRIDESIGN_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_STRIDESIGN_FSHIFT 23 +#define G2D_CFG1_STRIDESIGN_FMASK 0x1 +#define G2D_CFG2_STRIDE_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_STRIDE_FSHIFT 0 +#define G2D_CFG2_STRIDE_FMASK 0xfff +#define G2D_CFG2_FORMAT_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_FORMAT_FSHIFT 12 +#define G2D_CFG2_FORMAT_FMASK 0xf +#define G2D_CFG2_TILED_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_TILED_FSHIFT 16 +#define G2D_CFG2_TILED_FMASK 0x1 +#define G2D_CFG2_SRGB_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SRGB_FSHIFT 17 +#define G2D_CFG2_SRGB_FMASK 0x1 +#define G2D_CFG2_SWAPWORDS_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPWORDS_FSHIFT 18 +#define G2D_CFG2_SWAPWORDS_FMASK 0x1 +#define G2D_CFG2_SWAPBYTES_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPBYTES_FSHIFT 19 +#define G2D_CFG2_SWAPBYTES_FMASK 0x1 +#define G2D_CFG2_SWAPALL_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPALL_FSHIFT 20 +#define G2D_CFG2_SWAPALL_FMASK 0x1 +#define G2D_CFG2_SWAPRB_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPRB_FSHIFT 21 +#define G2D_CFG2_SWAPRB_FMASK 0x1 +#define G2D_CFG2_SWAPBITS_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPBITS_FSHIFT 22 +#define G2D_CFG2_SWAPBITS_FMASK 0x1 +#define G2D_CFG2_STRIDESIGN_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_STRIDESIGN_FSHIFT 23 +#define G2D_CFG2_STRIDESIGN_FMASK 0x1 +#define G2D_CFG3_STRIDE_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_STRIDE_FSHIFT 0 +#define G2D_CFG3_STRIDE_FMASK 0xfff +#define G2D_CFG3_FORMAT_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_FORMAT_FSHIFT 12 +#define G2D_CFG3_FORMAT_FMASK 0xf +#define G2D_CFG3_TILED_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_TILED_FSHIFT 16 +#define G2D_CFG3_TILED_FMASK 0x1 +#define G2D_CFG3_SRGB_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SRGB_FSHIFT 17 +#define G2D_CFG3_SRGB_FMASK 0x1 +#define G2D_CFG3_SWAPWORDS_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPWORDS_FSHIFT 18 +#define G2D_CFG3_SWAPWORDS_FMASK 0x1 +#define G2D_CFG3_SWAPBYTES_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPBYTES_FSHIFT 19 +#define G2D_CFG3_SWAPBYTES_FMASK 0x1 +#define G2D_CFG3_SWAPALL_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPALL_FSHIFT 20 +#define G2D_CFG3_SWAPALL_FMASK 0x1 +#define G2D_CFG3_SWAPRB_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPRB_FSHIFT 21 +#define G2D_CFG3_SWAPRB_FMASK 0x1 +#define G2D_CFG3_SWAPBITS_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPBITS_FSHIFT 22 +#define G2D_CFG3_SWAPBITS_FMASK 0x1 +#define G2D_CFG3_STRIDESIGN_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_STRIDESIGN_FSHIFT 23 +#define G2D_CFG3_STRIDESIGN_FMASK 0x1 +#define G2D_COLOR_ARGB_FADDR ADDR_G2D_COLOR +#define G2D_COLOR_ARGB_FSHIFT 0 +#define G2D_COLOR_ARGB_FMASK 0xffffffff +#define G2D_CONFIG_DST_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_DST_FSHIFT 0 +#define G2D_CONFIG_DST_FMASK 0x1 +#define G2D_CONFIG_SRC1_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRC1_FSHIFT 1 +#define G2D_CONFIG_SRC1_FMASK 0x1 +#define G2D_CONFIG_SRC2_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRC2_FSHIFT 2 +#define G2D_CONFIG_SRC2_FMASK 0x1 +#define G2D_CONFIG_SRC3_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRC3_FSHIFT 3 +#define G2D_CONFIG_SRC3_FMASK 0x1 +#define G2D_CONFIG_SRCCK_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRCCK_FSHIFT 4 +#define G2D_CONFIG_SRCCK_FMASK 0x1 +#define G2D_CONFIG_DSTCK_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_DSTCK_FSHIFT 5 +#define G2D_CONFIG_DSTCK_FMASK 0x1 +#define G2D_CONFIG_ROTATE_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_ROTATE_FSHIFT 6 +#define G2D_CONFIG_ROTATE_FMASK 0x3 +#define G2D_CONFIG_OBS_GAMMA_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_OBS_GAMMA_FSHIFT 8 +#define G2D_CONFIG_OBS_GAMMA_FMASK 0x1 +#define G2D_CONFIG_IGNORECKALPHA_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_IGNORECKALPHA_FSHIFT 9 +#define G2D_CONFIG_IGNORECKALPHA_FMASK 0x1 +#define G2D_CONFIG_DITHER_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_DITHER_FSHIFT 10 +#define G2D_CONFIG_DITHER_FMASK 0x1 +#define G2D_CONFIG_WRITESRGB_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_WRITESRGB_FSHIFT 11 +#define G2D_CONFIG_WRITESRGB_FMASK 0x1 +#define G2D_CONFIG_ARGBMASK_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_ARGBMASK_FSHIFT 12 +#define G2D_CONFIG_ARGBMASK_FMASK 0xf +#define G2D_CONFIG_ALPHATEX_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_ALPHATEX_FSHIFT 16 +#define G2D_CONFIG_ALPHATEX_FMASK 0x1 +#define G2D_CONFIG_PALMLINES_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_PALMLINES_FSHIFT 17 +#define G2D_CONFIG_PALMLINES_FMASK 0x1 +#define G2D_CONFIG_NOLASTPIXEL_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_NOLASTPIXEL_FSHIFT 18 +#define G2D_CONFIG_NOLASTPIXEL_FMASK 0x1 +#define G2D_CONFIG_NOPROTECT_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_NOPROTECT_FSHIFT 19 +#define G2D_CONFIG_NOPROTECT_FMASK 0x1 +#define G2D_CONST0_ARGB_FADDR ADDR_G2D_CONST0 +#define G2D_CONST0_ARGB_FSHIFT 0 +#define G2D_CONST0_ARGB_FMASK 0xffffffff +#define G2D_CONST1_ARGB_FADDR ADDR_G2D_CONST1 +#define G2D_CONST1_ARGB_FSHIFT 0 +#define G2D_CONST1_ARGB_FMASK 0xffffffff +#define G2D_CONST2_ARGB_FADDR ADDR_G2D_CONST2 +#define G2D_CONST2_ARGB_FSHIFT 0 +#define G2D_CONST2_ARGB_FMASK 0xffffffff +#define G2D_CONST3_ARGB_FADDR ADDR_G2D_CONST3 +#define G2D_CONST3_ARGB_FSHIFT 0 +#define G2D_CONST3_ARGB_FMASK 0xffffffff +#define G2D_CONST4_ARGB_FADDR ADDR_G2D_CONST4 +#define G2D_CONST4_ARGB_FSHIFT 0 +#define G2D_CONST4_ARGB_FMASK 0xffffffff +#define G2D_CONST5_ARGB_FADDR ADDR_G2D_CONST5 +#define G2D_CONST5_ARGB_FSHIFT 0 +#define G2D_CONST5_ARGB_FMASK 0xffffffff +#define G2D_CONST6_ARGB_FADDR ADDR_G2D_CONST6 +#define G2D_CONST6_ARGB_FSHIFT 0 +#define G2D_CONST6_ARGB_FMASK 0xffffffff +#define G2D_CONST7_ARGB_FADDR ADDR_G2D_CONST7 +#define G2D_CONST7_ARGB_FSHIFT 0 +#define G2D_CONST7_ARGB_FMASK 0xffffffff +#define G2D_FOREGROUND_COLOR_FADDR ADDR_G2D_FOREGROUND +#define G2D_FOREGROUND_COLOR_FSHIFT 0 +#define G2D_FOREGROUND_COLOR_FMASK 0xffffffff +#define G2D_GRADIENT_INSTRUCTIONS_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_INSTRUCTIONS_FSHIFT 0 +#define G2D_GRADIENT_INSTRUCTIONS_FMASK 0x7 +#define G2D_GRADIENT_INSTRUCTIONS2_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_INSTRUCTIONS2_FSHIFT 3 +#define G2D_GRADIENT_INSTRUCTIONS2_FMASK 0x7 +#define G2D_GRADIENT_ENABLE_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_ENABLE_FSHIFT 6 +#define G2D_GRADIENT_ENABLE_FMASK 0x1 +#define G2D_GRADIENT_ENABLE2_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_ENABLE2_FSHIFT 7 +#define G2D_GRADIENT_ENABLE2_FMASK 0x1 +#define G2D_GRADIENT_SEL_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_SEL_FSHIFT 8 +#define G2D_GRADIENT_SEL_FMASK 0x1 +#define G2D_IDLE_IRQ_FADDR ADDR_G2D_IDLE +#define G2D_IDLE_IRQ_FSHIFT 0 +#define G2D_IDLE_IRQ_FMASK 0x1 +#define G2D_IDLE_BCFLUSH_FADDR ADDR_G2D_IDLE +#define G2D_IDLE_BCFLUSH_FSHIFT 1 +#define G2D_IDLE_BCFLUSH_FMASK 0x1 +#define G2D_IDLE_V3_FADDR ADDR_G2D_IDLE +#define G2D_IDLE_V3_FSHIFT 2 +#define G2D_IDLE_V3_FMASK 0x1 +#define G2D_INPUT_COLOR_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_COLOR_FSHIFT 0 +#define G2D_INPUT_COLOR_FMASK 0x1 +#define G2D_INPUT_SCOORD1_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_SCOORD1_FSHIFT 1 +#define G2D_INPUT_SCOORD1_FMASK 0x1 +#define G2D_INPUT_SCOORD2_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_SCOORD2_FSHIFT 2 +#define G2D_INPUT_SCOORD2_FMASK 0x1 +#define G2D_INPUT_COPYCOORD_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_COPYCOORD_FSHIFT 3 +#define G2D_INPUT_COPYCOORD_FMASK 0x1 +#define G2D_INPUT_VGMODE_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_VGMODE_FSHIFT 4 +#define G2D_INPUT_VGMODE_FMASK 0x1 +#define G2D_INPUT_LINEMODE_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_LINEMODE_FSHIFT 5 +#define G2D_INPUT_LINEMODE_FMASK 0x1 +#define G2D_MASK_YMASK_FADDR ADDR_G2D_MASK +#define G2D_MASK_YMASK_FSHIFT 0 +#define G2D_MASK_YMASK_FMASK 0xfff +#define G2D_MASK_XMASK_FADDR ADDR_G2D_MASK +#define G2D_MASK_XMASK_FSHIFT 12 +#define G2D_MASK_XMASK_FMASK 0xfff +#define G2D_ROP_ROP_FADDR ADDR_G2D_ROP +#define G2D_ROP_ROP_FSHIFT 0 +#define G2D_ROP_ROP_FMASK 0xffff +#define G2D_SCISSORX_LEFT_FADDR ADDR_G2D_SCISSORX +#define G2D_SCISSORX_LEFT_FSHIFT 0 +#define G2D_SCISSORX_LEFT_FMASK 0x7ff +#define G2D_SCISSORX_RIGHT_FADDR ADDR_G2D_SCISSORX +#define G2D_SCISSORX_RIGHT_FSHIFT 11 +#define G2D_SCISSORX_RIGHT_FMASK 0x7ff +#define G2D_SCISSORY_TOP_FADDR ADDR_G2D_SCISSORY +#define G2D_SCISSORY_TOP_FSHIFT 0 +#define G2D_SCISSORY_TOP_FMASK 0x7ff +#define G2D_SCISSORY_BOTTOM_FADDR ADDR_G2D_SCISSORY +#define G2D_SCISSORY_BOTTOM_FSHIFT 11 +#define G2D_SCISSORY_BOTTOM_FMASK 0x7ff +#define G2D_SXY_Y_FADDR ADDR_G2D_SXY +#define G2D_SXY_Y_FSHIFT 0 +#define G2D_SXY_Y_FMASK 0x7ff +#define G2D_SXY_PAD_FADDR ADDR_G2D_SXY +#define G2D_SXY_PAD_FSHIFT 11 +#define G2D_SXY_PAD_FMASK 0x1f +#define G2D_SXY_X_FADDR ADDR_G2D_SXY +#define G2D_SXY_X_FSHIFT 16 +#define G2D_SXY_X_FMASK 0x7ff +#define G2D_SXY2_Y_FADDR ADDR_G2D_SXY2 +#define G2D_SXY2_Y_FSHIFT 0 +#define G2D_SXY2_Y_FMASK 0x7ff +#define G2D_SXY2_PAD_FADDR ADDR_G2D_SXY2 +#define G2D_SXY2_PAD_FSHIFT 11 +#define G2D_SXY2_PAD_FMASK 0x1f +#define G2D_SXY2_X_FADDR ADDR_G2D_SXY2 +#define G2D_SXY2_X_FSHIFT 16 +#define G2D_SXY2_X_FMASK 0x7ff +#define G2D_VGSPAN_WIDTH_FADDR ADDR_G2D_VGSPAN +#define G2D_VGSPAN_WIDTH_FSHIFT 0 +#define G2D_VGSPAN_WIDTH_FMASK 0xfff +#define G2D_VGSPAN_PAD_FADDR ADDR_G2D_VGSPAN +#define G2D_VGSPAN_PAD_FSHIFT 12 +#define G2D_VGSPAN_PAD_FMASK 0xf +#define G2D_VGSPAN_COVERAGE_FADDR ADDR_G2D_VGSPAN +#define G2D_VGSPAN_COVERAGE_FSHIFT 16 +#define G2D_VGSPAN_COVERAGE_FMASK 0xf +#define G2D_WIDTHHEIGHT_HEIGHT_FADDR ADDR_G2D_WIDTHHEIGHT +#define G2D_WIDTHHEIGHT_HEIGHT_FSHIFT 0 +#define G2D_WIDTHHEIGHT_HEIGHT_FMASK 0xfff +#define G2D_WIDTHHEIGHT_PAD_FADDR ADDR_G2D_WIDTHHEIGHT +#define G2D_WIDTHHEIGHT_PAD_FSHIFT 12 +#define G2D_WIDTHHEIGHT_PAD_FMASK 0xf +#define G2D_WIDTHHEIGHT_WIDTH_FADDR ADDR_G2D_WIDTHHEIGHT +#define G2D_WIDTHHEIGHT_WIDTH_FSHIFT 16 +#define G2D_WIDTHHEIGHT_WIDTH_FMASK 0xfff +#define G2D_XY_Y_FADDR ADDR_G2D_XY +#define G2D_XY_Y_FSHIFT 0 +#define G2D_XY_Y_FMASK 0xfff +#define G2D_XY_PAD_FADDR ADDR_G2D_XY +#define G2D_XY_PAD_FSHIFT 12 +#define G2D_XY_PAD_FMASK 0xf +#define G2D_XY_X_FADDR ADDR_G2D_XY +#define G2D_XY_X_FSHIFT 16 +#define G2D_XY_X_FMASK 0xfff +#define GRADW_BORDERCOLOR_COLOR_FADDR ADDR_GRADW_BORDERCOLOR +#define GRADW_BORDERCOLOR_COLOR_FSHIFT 0 +#define GRADW_BORDERCOLOR_COLOR_FMASK 0xffffffff +#define GRADW_CONST0_VALUE_FADDR ADDR_GRADW_CONST0 +#define GRADW_CONST0_VALUE_FSHIFT 0 +#define GRADW_CONST0_VALUE_FMASK 0xffff +#define GRADW_CONST1_VALUE_FADDR ADDR_GRADW_CONST1 +#define GRADW_CONST1_VALUE_FSHIFT 0 +#define GRADW_CONST1_VALUE_FMASK 0xffff +#define GRADW_CONST2_VALUE_FADDR ADDR_GRADW_CONST2 +#define GRADW_CONST2_VALUE_FSHIFT 0 +#define GRADW_CONST2_VALUE_FMASK 0xffff +#define GRADW_CONST3_VALUE_FADDR ADDR_GRADW_CONST3 +#define GRADW_CONST3_VALUE_FSHIFT 0 +#define GRADW_CONST3_VALUE_FMASK 0xffff +#define GRADW_CONST4_VALUE_FADDR ADDR_GRADW_CONST4 +#define GRADW_CONST4_VALUE_FSHIFT 0 +#define GRADW_CONST4_VALUE_FMASK 0xffff +#define GRADW_CONST5_VALUE_FADDR ADDR_GRADW_CONST5 +#define GRADW_CONST5_VALUE_FSHIFT 0 +#define GRADW_CONST5_VALUE_FMASK 0xffff +#define GRADW_CONST6_VALUE_FADDR ADDR_GRADW_CONST6 +#define GRADW_CONST6_VALUE_FSHIFT 0 +#define GRADW_CONST6_VALUE_FMASK 0xffff +#define GRADW_CONST7_VALUE_FADDR ADDR_GRADW_CONST7 +#define GRADW_CONST7_VALUE_FSHIFT 0 +#define GRADW_CONST7_VALUE_FMASK 0xffff +#define GRADW_CONST8_VALUE_FADDR ADDR_GRADW_CONST8 +#define GRADW_CONST8_VALUE_FSHIFT 0 +#define GRADW_CONST8_VALUE_FMASK 0xffff +#define GRADW_CONST9_VALUE_FADDR ADDR_GRADW_CONST9 +#define GRADW_CONST9_VALUE_FSHIFT 0 +#define GRADW_CONST9_VALUE_FMASK 0xffff +#define GRADW_CONSTA_VALUE_FADDR ADDR_GRADW_CONSTA +#define GRADW_CONSTA_VALUE_FSHIFT 0 +#define GRADW_CONSTA_VALUE_FMASK 0xffff +#define GRADW_CONSTB_VALUE_FADDR ADDR_GRADW_CONSTB +#define GRADW_CONSTB_VALUE_FSHIFT 0 +#define GRADW_CONSTB_VALUE_FMASK 0xffff +#define GRADW_INST0_SRC_E_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_E_FSHIFT 0 +#define GRADW_INST0_SRC_E_FMASK 0x1f +#define GRADW_INST0_SRC_D_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_D_FSHIFT 5 +#define GRADW_INST0_SRC_D_FMASK 0x1f +#define GRADW_INST0_SRC_C_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_C_FSHIFT 10 +#define GRADW_INST0_SRC_C_FMASK 0x1f +#define GRADW_INST0_SRC_B_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_B_FSHIFT 15 +#define GRADW_INST0_SRC_B_FMASK 0x1f +#define GRADW_INST0_SRC_A_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_A_FSHIFT 20 +#define GRADW_INST0_SRC_A_FMASK 0x1f +#define GRADW_INST0_DST_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_DST_FSHIFT 25 +#define GRADW_INST0_DST_FMASK 0xf +#define GRADW_INST0_OPCODE_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_OPCODE_FSHIFT 29 +#define GRADW_INST0_OPCODE_FMASK 0x3 +#define GRADW_INST1_SRC_E_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_E_FSHIFT 0 +#define GRADW_INST1_SRC_E_FMASK 0x1f +#define GRADW_INST1_SRC_D_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_D_FSHIFT 5 +#define GRADW_INST1_SRC_D_FMASK 0x1f +#define GRADW_INST1_SRC_C_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_C_FSHIFT 10 +#define GRADW_INST1_SRC_C_FMASK 0x1f +#define GRADW_INST1_SRC_B_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_B_FSHIFT 15 +#define GRADW_INST1_SRC_B_FMASK 0x1f +#define GRADW_INST1_SRC_A_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_A_FSHIFT 20 +#define GRADW_INST1_SRC_A_FMASK 0x1f +#define GRADW_INST1_DST_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_DST_FSHIFT 25 +#define GRADW_INST1_DST_FMASK 0xf +#define GRADW_INST1_OPCODE_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_OPCODE_FSHIFT 29 +#define GRADW_INST1_OPCODE_FMASK 0x3 +#define GRADW_INST2_SRC_E_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_E_FSHIFT 0 +#define GRADW_INST2_SRC_E_FMASK 0x1f +#define GRADW_INST2_SRC_D_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_D_FSHIFT 5 +#define GRADW_INST2_SRC_D_FMASK 0x1f +#define GRADW_INST2_SRC_C_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_C_FSHIFT 10 +#define GRADW_INST2_SRC_C_FMASK 0x1f +#define GRADW_INST2_SRC_B_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_B_FSHIFT 15 +#define GRADW_INST2_SRC_B_FMASK 0x1f +#define GRADW_INST2_SRC_A_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_A_FSHIFT 20 +#define GRADW_INST2_SRC_A_FMASK 0x1f +#define GRADW_INST2_DST_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_DST_FSHIFT 25 +#define GRADW_INST2_DST_FMASK 0xf +#define GRADW_INST2_OPCODE_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_OPCODE_FSHIFT 29 +#define GRADW_INST2_OPCODE_FMASK 0x3 +#define GRADW_INST3_SRC_E_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_E_FSHIFT 0 +#define GRADW_INST3_SRC_E_FMASK 0x1f +#define GRADW_INST3_SRC_D_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_D_FSHIFT 5 +#define GRADW_INST3_SRC_D_FMASK 0x1f +#define GRADW_INST3_SRC_C_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_C_FSHIFT 10 +#define GRADW_INST3_SRC_C_FMASK 0x1f +#define GRADW_INST3_SRC_B_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_B_FSHIFT 15 +#define GRADW_INST3_SRC_B_FMASK 0x1f +#define GRADW_INST3_SRC_A_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_A_FSHIFT 20 +#define GRADW_INST3_SRC_A_FMASK 0x1f +#define GRADW_INST3_DST_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_DST_FSHIFT 25 +#define GRADW_INST3_DST_FMASK 0xf +#define GRADW_INST3_OPCODE_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_OPCODE_FSHIFT 29 +#define GRADW_INST3_OPCODE_FMASK 0x3 +#define GRADW_INST4_SRC_E_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_E_FSHIFT 0 +#define GRADW_INST4_SRC_E_FMASK 0x1f +#define GRADW_INST4_SRC_D_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_D_FSHIFT 5 +#define GRADW_INST4_SRC_D_FMASK 0x1f +#define GRADW_INST4_SRC_C_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_C_FSHIFT 10 +#define GRADW_INST4_SRC_C_FMASK 0x1f +#define GRADW_INST4_SRC_B_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_B_FSHIFT 15 +#define GRADW_INST4_SRC_B_FMASK 0x1f +#define GRADW_INST4_SRC_A_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_A_FSHIFT 20 +#define GRADW_INST4_SRC_A_FMASK 0x1f +#define GRADW_INST4_DST_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_DST_FSHIFT 25 +#define GRADW_INST4_DST_FMASK 0xf +#define GRADW_INST4_OPCODE_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_OPCODE_FSHIFT 29 +#define GRADW_INST4_OPCODE_FMASK 0x3 +#define GRADW_INST5_SRC_E_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_E_FSHIFT 0 +#define GRADW_INST5_SRC_E_FMASK 0x1f +#define GRADW_INST5_SRC_D_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_D_FSHIFT 5 +#define GRADW_INST5_SRC_D_FMASK 0x1f +#define GRADW_INST5_SRC_C_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_C_FSHIFT 10 +#define GRADW_INST5_SRC_C_FMASK 0x1f +#define GRADW_INST5_SRC_B_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_B_FSHIFT 15 +#define GRADW_INST5_SRC_B_FMASK 0x1f +#define GRADW_INST5_SRC_A_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_A_FSHIFT 20 +#define GRADW_INST5_SRC_A_FMASK 0x1f +#define GRADW_INST5_DST_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_DST_FSHIFT 25 +#define GRADW_INST5_DST_FMASK 0xf +#define GRADW_INST5_OPCODE_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_OPCODE_FSHIFT 29 +#define GRADW_INST5_OPCODE_FMASK 0x3 +#define GRADW_INST6_SRC_E_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_E_FSHIFT 0 +#define GRADW_INST6_SRC_E_FMASK 0x1f +#define GRADW_INST6_SRC_D_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_D_FSHIFT 5 +#define GRADW_INST6_SRC_D_FMASK 0x1f +#define GRADW_INST6_SRC_C_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_C_FSHIFT 10 +#define GRADW_INST6_SRC_C_FMASK 0x1f +#define GRADW_INST6_SRC_B_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_B_FSHIFT 15 +#define GRADW_INST6_SRC_B_FMASK 0x1f +#define GRADW_INST6_SRC_A_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_A_FSHIFT 20 +#define GRADW_INST6_SRC_A_FMASK 0x1f +#define GRADW_INST6_DST_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_DST_FSHIFT 25 +#define GRADW_INST6_DST_FMASK 0xf +#define GRADW_INST6_OPCODE_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_OPCODE_FSHIFT 29 +#define GRADW_INST6_OPCODE_FMASK 0x3 +#define GRADW_INST7_SRC_E_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_E_FSHIFT 0 +#define GRADW_INST7_SRC_E_FMASK 0x1f +#define GRADW_INST7_SRC_D_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_D_FSHIFT 5 +#define GRADW_INST7_SRC_D_FMASK 0x1f +#define GRADW_INST7_SRC_C_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_C_FSHIFT 10 +#define GRADW_INST7_SRC_C_FMASK 0x1f +#define GRADW_INST7_SRC_B_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_B_FSHIFT 15 +#define GRADW_INST7_SRC_B_FMASK 0x1f +#define GRADW_INST7_SRC_A_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_A_FSHIFT 20 +#define GRADW_INST7_SRC_A_FMASK 0x1f +#define GRADW_INST7_DST_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_DST_FSHIFT 25 +#define GRADW_INST7_DST_FMASK 0xf +#define GRADW_INST7_OPCODE_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_OPCODE_FSHIFT 29 +#define GRADW_INST7_OPCODE_FMASK 0x3 +#define GRADW_TEXBASE_ADDR_FADDR ADDR_GRADW_TEXBASE +#define GRADW_TEXBASE_ADDR_FSHIFT 0 +#define GRADW_TEXBASE_ADDR_FMASK 0xffffffff +#define GRADW_TEXCFG_STRIDE_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_STRIDE_FSHIFT 0 +#define GRADW_TEXCFG_STRIDE_FMASK 0xfff +#define GRADW_TEXCFG_FORMAT_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_FORMAT_FSHIFT 12 +#define GRADW_TEXCFG_FORMAT_FMASK 0xf +#define GRADW_TEXCFG_TILED_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_TILED_FSHIFT 16 +#define GRADW_TEXCFG_TILED_FMASK 0x1 +#define GRADW_TEXCFG_WRAPU_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_WRAPU_FSHIFT 17 +#define GRADW_TEXCFG_WRAPU_FMASK 0x3 +#define GRADW_TEXCFG_WRAPV_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_WRAPV_FSHIFT 19 +#define GRADW_TEXCFG_WRAPV_FMASK 0x3 +#define GRADW_TEXCFG_BILIN_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_BILIN_FSHIFT 21 +#define GRADW_TEXCFG_BILIN_FMASK 0x1 +#define GRADW_TEXCFG_SRGB_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SRGB_FSHIFT 22 +#define GRADW_TEXCFG_SRGB_FMASK 0x1 +#define GRADW_TEXCFG_PREMULTIPLY_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_PREMULTIPLY_FSHIFT 23 +#define GRADW_TEXCFG_PREMULTIPLY_FMASK 0x1 +#define GRADW_TEXCFG_SWAPWORDS_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPWORDS_FSHIFT 24 +#define GRADW_TEXCFG_SWAPWORDS_FMASK 0x1 +#define GRADW_TEXCFG_SWAPBYTES_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPBYTES_FSHIFT 25 +#define GRADW_TEXCFG_SWAPBYTES_FMASK 0x1 +#define GRADW_TEXCFG_SWAPALL_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPALL_FSHIFT 26 +#define GRADW_TEXCFG_SWAPALL_FMASK 0x1 +#define GRADW_TEXCFG_SWAPRB_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPRB_FSHIFT 27 +#define GRADW_TEXCFG_SWAPRB_FMASK 0x1 +#define GRADW_TEXCFG_TEX2D_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_TEX2D_FSHIFT 28 +#define GRADW_TEXCFG_TEX2D_FMASK 0x1 +#define GRADW_TEXCFG_SWAPBITS_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPBITS_FSHIFT 29 +#define GRADW_TEXCFG_SWAPBITS_FMASK 0x1 +#define GRADW_TEXSIZE_WIDTH_FADDR ADDR_GRADW_TEXSIZE +#define GRADW_TEXSIZE_WIDTH_FSHIFT 0 +#define GRADW_TEXSIZE_WIDTH_FMASK 0x7ff +#define GRADW_TEXSIZE_HEIGHT_FADDR ADDR_GRADW_TEXSIZE +#define GRADW_TEXSIZE_HEIGHT_FSHIFT 11 +#define GRADW_TEXSIZE_HEIGHT_FMASK 0x7ff +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FSHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FMASK 0x3f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FSHIFT 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FMASK 0x1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FSHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FSHIFT 8 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FSHIFT 9 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FMASK 0x1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_PAGE_SIZE_FSHIFT 10 +#define MH_ARBITER_CONFIG_PAGE_SIZE_FMASK 0x7 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FSHIFT 13 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FSHIFT 14 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FSHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FSHIFT 16 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FMASK 0x3f +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FSHIFT 22 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FSHIFT 23 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FSHIFT 24 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FSHIFT 25 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FSHIFT 26 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FMASK 0x1 +#define MH_AXI_ERROR_AXI_READ_ID_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_READ_ID_FSHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ID_FMASK 0x7 +#define MH_AXI_ERROR_AXI_READ_ERROR_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_READ_ERROR_FSHIFT 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_FMASK 0x1 +#define MH_AXI_ERROR_AXI_WRITE_ID_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_WRITE_ID_FSHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ID_FMASK 0x7 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_WRITE_ERROR_FSHIFT 7 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_AXI_HALT_CONTROL_AXI_HALT_FADDR ADDR_MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL_AXI_HALT_FSHIFT 0 +#define MH_AXI_HALT_CONTROL_AXI_HALT_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FSHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FMASK 0x7 +#define MH_CLNT_AXI_ID_REUSE_PAD_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAD_FSHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_PAD_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FSHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FMASK 0x7 +#define MH_CLNT_AXI_ID_REUSE_PAD2_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAD2_FSHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_PAD2_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FSHIFT 8 +#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FMASK 0x7 +#define MH_CLNT_AXI_ID_REUSE_PAD3_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAD3_FSHIFT 11 +#define MH_CLNT_AXI_ID_REUSE_PAD3_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FSHIFT 12 +#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FMASK 0x7 +#define MH_DEBUG_CTRL_INDEX_FADDR ADDR_MH_DEBUG_CTRL +#define MH_DEBUG_CTRL_INDEX_FSHIFT 0 +#define MH_DEBUG_CTRL_INDEX_FMASK 0x3f +#define MH_DEBUG_DATA_DATA_FADDR ADDR_MH_DEBUG_DATA +#define MH_DEBUG_DATA_DATA_FSHIFT 0 +#define MH_DEBUG_DATA_DATA_FMASK 0xffffffff +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FSHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FMASK 0x1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FSHIFT 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FSHIFT 2 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FMASK 0x1 +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT 0 +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FMASK 0x1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT 2 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FMASK 0x1 +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FSHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FMASK 0x1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FSHIFT 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FSHIFT 2 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FMASK 0x1 +#define MH_MMU_CONFIG_MMU_ENABLE_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_MMU_ENABLE_FSHIFT 0 +#define MH_MMU_CONFIG_MMU_ENABLE_FMASK 0x1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FSHIFT 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FMASK 0x1 +#define MH_MMU_CONFIG_PAD_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_PAD_FSHIFT 2 +#define MH_MMU_CONFIG_PAD_FMASK 0x3 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FSHIFT 4 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FSHIFT 6 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FSHIFT 8 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FSHIFT 10 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FSHIFT 12 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FSHIFT 14 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FSHIFT 16 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FSHIFT 18 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FSHIFT 20 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FSHIFT 22 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FSHIFT 24 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FADDR ADDR_MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FSHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FMASK 0x1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_FADDR ADDR_MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE_INVALIDATE_TC_FSHIFT 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_FMASK 0x1 +#define MH_MMU_MPU_BASE_ZERO_FADDR ADDR_MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE_ZERO_FSHIFT 0 +#define MH_MMU_MPU_BASE_ZERO_FMASK 0xfff +#define MH_MMU_MPU_BASE_MPU_BASE_FADDR ADDR_MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE_MPU_BASE_FSHIFT 12 +#define MH_MMU_MPU_BASE_MPU_BASE_FMASK 0xfffff +#define MH_MMU_MPU_END_ZERO_FADDR ADDR_MH_MMU_MPU_END +#define MH_MMU_MPU_END_ZERO_FSHIFT 0 +#define MH_MMU_MPU_END_ZERO_FMASK 0xfff +#define MH_MMU_MPU_END_MPU_END_FADDR ADDR_MH_MMU_MPU_END +#define MH_MMU_MPU_END_MPU_END_FSHIFT 12 +#define MH_MMU_MPU_END_MPU_END_FMASK 0xfffff +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FSHIFT 0 +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_OP_TYPE_FSHIFT 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FSHIFT 2 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_PAGE_FAULT_AXI_ID_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_AXI_ID_FSHIFT 4 +#define MH_MMU_PAGE_FAULT_AXI_ID_FMASK 0x7 +#define MH_MMU_PAGE_FAULT_PAD_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_PAD_FSHIFT 7 +#define MH_MMU_PAGE_FAULT_PAD_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FSHIFT 8 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FSHIFT 9 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FSHIFT 10 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FSHIFT 11 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_REQ_VA_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_REQ_VA_FSHIFT 12 +#define MH_MMU_PAGE_FAULT_REQ_VA_FMASK 0xfffff +#define MH_MMU_PT_BASE_ZERO_FADDR ADDR_MH_MMU_PT_BASE +#define MH_MMU_PT_BASE_ZERO_FSHIFT 0 +#define MH_MMU_PT_BASE_ZERO_FMASK 0xfff +#define MH_MMU_PT_BASE_PT_BASE_FADDR ADDR_MH_MMU_PT_BASE +#define MH_MMU_PT_BASE_PT_BASE_FSHIFT 12 +#define MH_MMU_PT_BASE_PT_BASE_FMASK 0xfffff +#define MH_MMU_TRAN_ERROR_ZERO_FADDR ADDR_MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR_ZERO_FSHIFT 0 +#define MH_MMU_TRAN_ERROR_ZERO_FMASK 0x1f +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FADDR ADDR_MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FSHIFT 5 +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FMASK 0x7ffffff +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FADDR ADDR_MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FSHIFT 0 +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FMASK 0xfff +#define MH_MMU_VA_RANGE_VA_BASE_FADDR ADDR_MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE_VA_BASE_FSHIFT 12 +#define MH_MMU_VA_RANGE_VA_BASE_FMASK 0xfffff +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FSHIFT 0 +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FMASK 0xff +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FSHIFT 0 +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FMASK 0xffff +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FSHIFT 0 +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FSHIFT 0 +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FMASK 0xff +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FSHIFT 0 +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FMASK 0xff +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FSHIFT 0 +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FMASK 0xffff +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FSHIFT 0 +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FSHIFT 0 +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FMASK 0xff +#define MMU_READ_ADDR_ADDR_FADDR ADDR_MMU_READ_ADDR +#define MMU_READ_ADDR_ADDR_FSHIFT 0 +#define MMU_READ_ADDR_ADDR_FMASK 0x7fff +#define MMU_READ_DATA_DATA_FADDR ADDR_MMU_READ_DATA +#define MMU_READ_DATA_DATA_FSHIFT 0 +#define MMU_READ_DATA_DATA_FMASK 0xffffffff +#define VGV1_CBASE1_ADDR_FADDR ADDR_VGV1_CBASE1 +#define VGV1_CBASE1_ADDR_FSHIFT 0 +#define VGV1_CBASE1_ADDR_FMASK 0xffffffff +#define VGV1_CFG1_WINDRULE_FADDR ADDR_VGV1_CFG1 +#define VGV1_CFG1_WINDRULE_FSHIFT 0 +#define VGV1_CFG1_WINDRULE_FMASK 0x1 +#define VGV1_CFG2_AAMODE_FADDR ADDR_VGV1_CFG2 +#define VGV1_CFG2_AAMODE_FSHIFT 0 +#define VGV1_CFG2_AAMODE_FMASK 0x3 +#define VGV1_DIRTYBASE_ADDR_FADDR ADDR_VGV1_DIRTYBASE +#define VGV1_DIRTYBASE_ADDR_FSHIFT 0 +#define VGV1_DIRTYBASE_ADDR_FMASK 0xffffffff +#define VGV1_FILL_INHERIT_FADDR ADDR_VGV1_FILL +#define VGV1_FILL_INHERIT_FSHIFT 0 +#define VGV1_FILL_INHERIT_FMASK 0x1 +#define VGV1_SCISSORX_LEFT_FADDR ADDR_VGV1_SCISSORX +#define VGV1_SCISSORX_LEFT_FSHIFT 0 +#define VGV1_SCISSORX_LEFT_FMASK 0x7ff +#define VGV1_SCISSORX_PAD_FADDR ADDR_VGV1_SCISSORX +#define VGV1_SCISSORX_PAD_FSHIFT 11 +#define VGV1_SCISSORX_PAD_FMASK 0x1f +#define VGV1_SCISSORX_RIGHT_FADDR ADDR_VGV1_SCISSORX +#define VGV1_SCISSORX_RIGHT_FSHIFT 16 +#define VGV1_SCISSORX_RIGHT_FMASK 0x7ff +#define VGV1_SCISSORY_TOP_FADDR ADDR_VGV1_SCISSORY +#define VGV1_SCISSORY_TOP_FSHIFT 0 +#define VGV1_SCISSORY_TOP_FMASK 0x7ff +#define VGV1_SCISSORY_PAD_FADDR ADDR_VGV1_SCISSORY +#define VGV1_SCISSORY_PAD_FSHIFT 11 +#define VGV1_SCISSORY_PAD_FMASK 0x1f +#define VGV1_SCISSORY_BOTTOM_FADDR ADDR_VGV1_SCISSORY +#define VGV1_SCISSORY_BOTTOM_FSHIFT 16 +#define VGV1_SCISSORY_BOTTOM_FMASK 0x7ff +#define VGV1_TILEOFS_X_FADDR ADDR_VGV1_TILEOFS +#define VGV1_TILEOFS_X_FSHIFT 0 +#define VGV1_TILEOFS_X_FMASK 0xfff +#define VGV1_TILEOFS_Y_FADDR ADDR_VGV1_TILEOFS +#define VGV1_TILEOFS_Y_FSHIFT 12 +#define VGV1_TILEOFS_Y_FMASK 0xfff +#define VGV1_TILEOFS_LEFTMOST_FADDR ADDR_VGV1_TILEOFS +#define VGV1_TILEOFS_LEFTMOST_FSHIFT 24 +#define VGV1_TILEOFS_LEFTMOST_FMASK 0x1 +#define VGV1_UBASE2_ADDR_FADDR ADDR_VGV1_UBASE2 +#define VGV1_UBASE2_ADDR_FSHIFT 0 +#define VGV1_UBASE2_ADDR_FMASK 0xffffffff +#define VGV1_VTX0_X_FADDR ADDR_VGV1_VTX0 +#define VGV1_VTX0_X_FSHIFT 0 +#define VGV1_VTX0_X_FMASK 0xffff +#define VGV1_VTX0_Y_FADDR ADDR_VGV1_VTX0 +#define VGV1_VTX0_Y_FSHIFT 16 +#define VGV1_VTX0_Y_FMASK 0xffff +#define VGV1_VTX1_X_FADDR ADDR_VGV1_VTX1 +#define VGV1_VTX1_X_FSHIFT 0 +#define VGV1_VTX1_X_FMASK 0xffff +#define VGV1_VTX1_Y_FADDR ADDR_VGV1_VTX1 +#define VGV1_VTX1_Y_FSHIFT 16 +#define VGV1_VTX1_Y_FMASK 0xffff +#define VGV2_ACCURACY_F_FADDR ADDR_VGV2_ACCURACY +#define VGV2_ACCURACY_F_FSHIFT 0 +#define VGV2_ACCURACY_F_FMASK 0xffffff +#define VGV2_ACTION_ACTION_FADDR ADDR_VGV2_ACTION +#define VGV2_ACTION_ACTION_FSHIFT 0 +#define VGV2_ACTION_ACTION_FMASK 0xf +#define VGV2_ARCCOS_F_FADDR ADDR_VGV2_ARCCOS +#define VGV2_ARCCOS_F_FSHIFT 0 +#define VGV2_ARCCOS_F_FMASK 0xffffff +#define VGV2_ARCSIN_F_FADDR ADDR_VGV2_ARCSIN +#define VGV2_ARCSIN_F_FSHIFT 0 +#define VGV2_ARCSIN_F_FMASK 0xffffff +#define VGV2_ARCTAN_F_FADDR ADDR_VGV2_ARCTAN +#define VGV2_ARCTAN_F_FSHIFT 0 +#define VGV2_ARCTAN_F_FMASK 0xffffff +#define VGV2_BBOXMAXX_F_FADDR ADDR_VGV2_BBOXMAXX +#define VGV2_BBOXMAXX_F_FSHIFT 0 +#define VGV2_BBOXMAXX_F_FMASK 0xffffff +#define VGV2_BBOXMAXY_F_FADDR ADDR_VGV2_BBOXMAXY +#define VGV2_BBOXMAXY_F_FSHIFT 0 +#define VGV2_BBOXMAXY_F_FMASK 0xffffff +#define VGV2_BBOXMINX_F_FADDR ADDR_VGV2_BBOXMINX +#define VGV2_BBOXMINX_F_FSHIFT 0 +#define VGV2_BBOXMINX_F_FMASK 0xffffff +#define VGV2_BBOXMINY_F_FADDR ADDR_VGV2_BBOXMINY +#define VGV2_BBOXMINY_F_FSHIFT 0 +#define VGV2_BBOXMINY_F_FMASK 0xffffff +#define VGV2_BIAS_F_FADDR ADDR_VGV2_BIAS +#define VGV2_BIAS_F_FSHIFT 0 +#define VGV2_BIAS_F_FMASK 0xffffff +#define VGV2_C1X_F_FADDR ADDR_VGV2_C1X +#define VGV2_C1X_F_FSHIFT 0 +#define VGV2_C1X_F_FMASK 0xffffff +#define VGV2_C1XREL_F_FADDR ADDR_VGV2_C1XREL +#define VGV2_C1XREL_F_FSHIFT 0 +#define VGV2_C1XREL_F_FMASK 0xffffff +#define VGV2_C1Y_F_FADDR ADDR_VGV2_C1Y +#define VGV2_C1Y_F_FSHIFT 0 +#define VGV2_C1Y_F_FMASK 0xffffff +#define VGV2_C1YREL_F_FADDR ADDR_VGV2_C1YREL +#define VGV2_C1YREL_F_FSHIFT 0 +#define VGV2_C1YREL_F_FMASK 0xffffff +#define VGV2_C2X_F_FADDR ADDR_VGV2_C2X +#define VGV2_C2X_F_FSHIFT 0 +#define VGV2_C2X_F_FMASK 0xffffff +#define VGV2_C2XREL_F_FADDR ADDR_VGV2_C2XREL +#define VGV2_C2XREL_F_FSHIFT 0 +#define VGV2_C2XREL_F_FMASK 0xffffff +#define VGV2_C2Y_F_FADDR ADDR_VGV2_C2Y +#define VGV2_C2Y_F_FSHIFT 0 +#define VGV2_C2Y_F_FMASK 0xffffff +#define VGV2_C2YREL_F_FADDR ADDR_VGV2_C2YREL +#define VGV2_C2YREL_F_FSHIFT 0 +#define VGV2_C2YREL_F_FMASK 0xffffff +#define VGV2_C3X_F_FADDR ADDR_VGV2_C3X +#define VGV2_C3X_F_FSHIFT 0 +#define VGV2_C3X_F_FMASK 0xffffff +#define VGV2_C3XREL_F_FADDR ADDR_VGV2_C3XREL +#define VGV2_C3XREL_F_FSHIFT 0 +#define VGV2_C3XREL_F_FMASK 0xffffff +#define VGV2_C3Y_F_FADDR ADDR_VGV2_C3Y +#define VGV2_C3Y_F_FSHIFT 0 +#define VGV2_C3Y_F_FMASK 0xffffff +#define VGV2_C3YREL_F_FADDR ADDR_VGV2_C3YREL +#define VGV2_C3YREL_F_FSHIFT 0 +#define VGV2_C3YREL_F_FMASK 0xffffff +#define VGV2_C4X_F_FADDR ADDR_VGV2_C4X +#define VGV2_C4X_F_FSHIFT 0 +#define VGV2_C4X_F_FMASK 0xffffff +#define VGV2_C4XREL_F_FADDR ADDR_VGV2_C4XREL +#define VGV2_C4XREL_F_FSHIFT 0 +#define VGV2_C4XREL_F_FMASK 0xffffff +#define VGV2_C4Y_F_FADDR ADDR_VGV2_C4Y +#define VGV2_C4Y_F_FSHIFT 0 +#define VGV2_C4Y_F_FMASK 0xffffff +#define VGV2_C4YREL_F_FADDR ADDR_VGV2_C4YREL +#define VGV2_C4YREL_F_FSHIFT 0 +#define VGV2_C4YREL_F_FMASK 0xffffff +#define VGV2_CLIP_F_FADDR ADDR_VGV2_CLIP +#define VGV2_CLIP_F_FSHIFT 0 +#define VGV2_CLIP_F_FMASK 0xffffff +#define VGV2_FIRST_DUMMY_FADDR ADDR_VGV2_FIRST +#define VGV2_FIRST_DUMMY_FSHIFT 0 +#define VGV2_FIRST_DUMMY_FMASK 0x1 +#define VGV2_LAST_DUMMY_FADDR ADDR_VGV2_LAST +#define VGV2_LAST_DUMMY_FSHIFT 0 +#define VGV2_LAST_DUMMY_FMASK 0x1 +#define VGV2_MITER_F_FADDR ADDR_VGV2_MITER +#define VGV2_MITER_F_FSHIFT 0 +#define VGV2_MITER_F_FMASK 0xffffff +#define VGV2_MODE_MAXSPLIT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_MAXSPLIT_FSHIFT 0 +#define VGV2_MODE_MAXSPLIT_FMASK 0xf +#define VGV2_MODE_CAP_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_CAP_FSHIFT 4 +#define VGV2_MODE_CAP_FMASK 0x3 +#define VGV2_MODE_JOIN_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_JOIN_FSHIFT 6 +#define VGV2_MODE_JOIN_FMASK 0x3 +#define VGV2_MODE_STROKE_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_STROKE_FSHIFT 8 +#define VGV2_MODE_STROKE_FMASK 0x1 +#define VGV2_MODE_STROKESPLIT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_STROKESPLIT_FSHIFT 9 +#define VGV2_MODE_STROKESPLIT_FMASK 0x1 +#define VGV2_MODE_FULLSPLIT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_FULLSPLIT_FSHIFT 10 +#define VGV2_MODE_FULLSPLIT_FMASK 0x1 +#define VGV2_MODE_NODOTS_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_NODOTS_FSHIFT 11 +#define VGV2_MODE_NODOTS_FMASK 0x1 +#define VGV2_MODE_OPENFILL_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_OPENFILL_FSHIFT 12 +#define VGV2_MODE_OPENFILL_FMASK 0x1 +#define VGV2_MODE_DROPLEFT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_DROPLEFT_FSHIFT 13 +#define VGV2_MODE_DROPLEFT_FMASK 0x1 +#define VGV2_MODE_DROPOTHER_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_DROPOTHER_FSHIFT 14 +#define VGV2_MODE_DROPOTHER_FMASK 0x1 +#define VGV2_MODE_SYMMETRICJOINS_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_SYMMETRICJOINS_FSHIFT 15 +#define VGV2_MODE_SYMMETRICJOINS_FMASK 0x1 +#define VGV2_MODE_SIMPLESTROKE_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_SIMPLESTROKE_FSHIFT 16 +#define VGV2_MODE_SIMPLESTROKE_FMASK 0x1 +#define VGV2_MODE_SIMPLECLIP_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_SIMPLECLIP_FSHIFT 17 +#define VGV2_MODE_SIMPLECLIP_FMASK 0x1 +#define VGV2_MODE_EXPONENTADD_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_EXPONENTADD_FSHIFT 18 +#define VGV2_MODE_EXPONENTADD_FMASK 0x3f +#define VGV2_RADIUS_F_FADDR ADDR_VGV2_RADIUS +#define VGV2_RADIUS_F_FSHIFT 0 +#define VGV2_RADIUS_F_FMASK 0xffffff +#define VGV2_SCALE_F_FADDR ADDR_VGV2_SCALE +#define VGV2_SCALE_F_FSHIFT 0 +#define VGV2_SCALE_F_FMASK 0xffffff +#define VGV2_THINRADIUS_F_FADDR ADDR_VGV2_THINRADIUS +#define VGV2_THINRADIUS_F_FSHIFT 0 +#define VGV2_THINRADIUS_F_FMASK 0xffffff +#define VGV2_XFSTXX_F_FADDR ADDR_VGV2_XFSTXX +#define VGV2_XFSTXX_F_FSHIFT 0 +#define VGV2_XFSTXX_F_FMASK 0xffffff +#define VGV2_XFSTXY_F_FADDR ADDR_VGV2_XFSTXY +#define VGV2_XFSTXY_F_FSHIFT 0 +#define VGV2_XFSTXY_F_FMASK 0xffffff +#define VGV2_XFSTYX_F_FADDR ADDR_VGV2_XFSTYX +#define VGV2_XFSTYX_F_FSHIFT 0 +#define VGV2_XFSTYX_F_FMASK 0xffffff +#define VGV2_XFSTYY_F_FADDR ADDR_VGV2_XFSTYY +#define VGV2_XFSTYY_F_FSHIFT 0 +#define VGV2_XFSTYY_F_FMASK 0xffffff +#define VGV2_XFXA_F_FADDR ADDR_VGV2_XFXA +#define VGV2_XFXA_F_FSHIFT 0 +#define VGV2_XFXA_F_FMASK 0xffffff +#define VGV2_XFXX_F_FADDR ADDR_VGV2_XFXX +#define VGV2_XFXX_F_FSHIFT 0 +#define VGV2_XFXX_F_FMASK 0xffffff +#define VGV2_XFXY_F_FADDR ADDR_VGV2_XFXY +#define VGV2_XFXY_F_FSHIFT 0 +#define VGV2_XFXY_F_FMASK 0xffffff +#define VGV2_XFYA_F_FADDR ADDR_VGV2_XFYA +#define VGV2_XFYA_F_FSHIFT 0 +#define VGV2_XFYA_F_FMASK 0xffffff +#define VGV2_XFYX_F_FADDR ADDR_VGV2_XFYX +#define VGV2_XFYX_F_FSHIFT 0 +#define VGV2_XFYX_F_FMASK 0xffffff +#define VGV2_XFYY_F_FADDR ADDR_VGV2_XFYY +#define VGV2_XFYY_F_FSHIFT 0 +#define VGV2_XFYY_F_FMASK 0xffffff +#define VGV3_CONTROL_MARKADD_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_MARKADD_FSHIFT 0 +#define VGV3_CONTROL_MARKADD_FMASK 0xfff +#define VGV3_CONTROL_DMIWAITCHMASK_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_DMIWAITCHMASK_FSHIFT 12 +#define VGV3_CONTROL_DMIWAITCHMASK_FMASK 0xf +#define VGV3_CONTROL_PAUSE_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_PAUSE_FSHIFT 16 +#define VGV3_CONTROL_PAUSE_FMASK 0x1 +#define VGV3_CONTROL_ABORT_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_ABORT_FSHIFT 17 +#define VGV3_CONTROL_ABORT_FMASK 0x1 +#define VGV3_CONTROL_WRITE_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_WRITE_FSHIFT 18 +#define VGV3_CONTROL_WRITE_FMASK 0x1 +#define VGV3_CONTROL_BCFLUSH_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_BCFLUSH_FSHIFT 19 +#define VGV3_CONTROL_BCFLUSH_FMASK 0x1 +#define VGV3_CONTROL_V0SYNC_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_V0SYNC_FSHIFT 20 +#define VGV3_CONTROL_V0SYNC_FMASK 0x1 +#define VGV3_CONTROL_DMIWAITBUF_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_DMIWAITBUF_FSHIFT 21 +#define VGV3_CONTROL_DMIWAITBUF_FMASK 0x7 +#define VGV3_FIRST_DUMMY_FADDR ADDR_VGV3_FIRST +#define VGV3_FIRST_DUMMY_FSHIFT 0 +#define VGV3_FIRST_DUMMY_FMASK 0x1 +#define VGV3_LAST_DUMMY_FADDR ADDR_VGV3_LAST +#define VGV3_LAST_DUMMY_FSHIFT 0 +#define VGV3_LAST_DUMMY_FMASK 0x1 +#define VGV3_MODE_FLIPENDIAN_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_FLIPENDIAN_FSHIFT 0 +#define VGV3_MODE_FLIPENDIAN_FMASK 0x1 +#define VGV3_MODE_UNUSED_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_UNUSED_FSHIFT 1 +#define VGV3_MODE_UNUSED_FMASK 0x1 +#define VGV3_MODE_WRITEFLUSH_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_WRITEFLUSH_FSHIFT 2 +#define VGV3_MODE_WRITEFLUSH_FMASK 0x1 +#define VGV3_MODE_DMIPAUSETYPE_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_DMIPAUSETYPE_FSHIFT 3 +#define VGV3_MODE_DMIPAUSETYPE_FMASK 0x1 +#define VGV3_MODE_DMIRESET_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_DMIRESET_FSHIFT 4 +#define VGV3_MODE_DMIRESET_FMASK 0x1 +#define VGV3_NEXTADDR_CALLADDR_FADDR ADDR_VGV3_NEXTADDR +#define VGV3_NEXTADDR_CALLADDR_FSHIFT 0 +#define VGV3_NEXTADDR_CALLADDR_FMASK 0xffffffff +#define VGV3_NEXTCMD_COUNT_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_COUNT_FSHIFT 0 +#define VGV3_NEXTCMD_COUNT_FMASK 0xfff +#define VGV3_NEXTCMD_NEXTCMD_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_NEXTCMD_FSHIFT 12 +#define VGV3_NEXTCMD_NEXTCMD_FMASK 0x7 +#define VGV3_NEXTCMD_MARK_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_MARK_FSHIFT 15 +#define VGV3_NEXTCMD_MARK_FMASK 0x1 +#define VGV3_NEXTCMD_CALLCOUNT_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_CALLCOUNT_FSHIFT 16 +#define VGV3_NEXTCMD_CALLCOUNT_FMASK 0xfff +#define VGV3_VGBYPASS_BYPASS_FADDR ADDR_VGV3_VGBYPASS +#define VGV3_VGBYPASS_BYPASS_FSHIFT 0 +#define VGV3_VGBYPASS_BYPASS_FMASK 0x1 +#define VGV3_WRITE_VALUE_FADDR ADDR_VGV3_WRITE +#define VGV3_WRITE_VALUE_FSHIFT 0 +#define VGV3_WRITE_VALUE_FMASK 0xffffffff +#define VGV3_WRITEADDR_ADDR_FADDR ADDR_VGV3_WRITEADDR +#define VGV3_WRITEADDR_ADDR_FSHIFT 0 +#define VGV3_WRITEADDR_ADDR_FMASK 0xffffffff +#define VGV3_WRITEDMI_CHANMASK_FADDR ADDR_VGV3_WRITEDMI +#define VGV3_WRITEDMI_CHANMASK_FSHIFT 0 +#define VGV3_WRITEDMI_CHANMASK_FMASK 0xf +#define VGV3_WRITEDMI_BUFFER_FADDR ADDR_VGV3_WRITEDMI +#define VGV3_WRITEDMI_BUFFER_FSHIFT 4 +#define VGV3_WRITEDMI_BUFFER_FMASK 0x7 +#define VGV3_WRITEF32_ADDR_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_ADDR_FSHIFT 0 +#define VGV3_WRITEF32_ADDR_FMASK 0xff +#define VGV3_WRITEF32_COUNT_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_COUNT_FSHIFT 8 +#define VGV3_WRITEF32_COUNT_FMASK 0xff +#define VGV3_WRITEF32_LOOP_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_LOOP_FSHIFT 16 +#define VGV3_WRITEF32_LOOP_FMASK 0xf +#define VGV3_WRITEF32_ACTION_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_ACTION_FSHIFT 20 +#define VGV3_WRITEF32_ACTION_FMASK 0xf +#define VGV3_WRITEF32_FORMAT_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_FORMAT_FSHIFT 24 +#define VGV3_WRITEF32_FORMAT_FMASK 0x7 +#define VGV3_WRITEIFPAUSED_VALUE_FADDR ADDR_VGV3_WRITEIFPAUSED +#define VGV3_WRITEIFPAUSED_VALUE_FSHIFT 0 +#define VGV3_WRITEIFPAUSED_VALUE_FMASK 0xffffffff +#define VGV3_WRITERAW_ADDR_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_ADDR_FSHIFT 0 +#define VGV3_WRITERAW_ADDR_FMASK 0xff +#define VGV3_WRITERAW_COUNT_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_COUNT_FSHIFT 8 +#define VGV3_WRITERAW_COUNT_FMASK 0xff +#define VGV3_WRITERAW_LOOP_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_LOOP_FSHIFT 16 +#define VGV3_WRITERAW_LOOP_FMASK 0xf +#define VGV3_WRITERAW_ACTION_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_ACTION_FSHIFT 20 +#define VGV3_WRITERAW_ACTION_FMASK 0xf +#define VGV3_WRITERAW_FORMAT_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_FORMAT_FSHIFT 24 +#define VGV3_WRITERAW_FORMAT_FMASK 0x7 +#define VGV3_WRITES16_ADDR_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_ADDR_FSHIFT 0 +#define VGV3_WRITES16_ADDR_FMASK 0xff +#define VGV3_WRITES16_COUNT_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_COUNT_FSHIFT 8 +#define VGV3_WRITES16_COUNT_FMASK 0xff +#define VGV3_WRITES16_LOOP_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_LOOP_FSHIFT 16 +#define VGV3_WRITES16_LOOP_FMASK 0xf +#define VGV3_WRITES16_ACTION_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_ACTION_FSHIFT 20 +#define VGV3_WRITES16_ACTION_FMASK 0xf +#define VGV3_WRITES16_FORMAT_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_FORMAT_FSHIFT 24 +#define VGV3_WRITES16_FORMAT_FMASK 0x7 +#define VGV3_WRITES32_ADDR_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_ADDR_FSHIFT 0 +#define VGV3_WRITES32_ADDR_FMASK 0xff +#define VGV3_WRITES32_COUNT_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_COUNT_FSHIFT 8 +#define VGV3_WRITES32_COUNT_FMASK 0xff +#define VGV3_WRITES32_LOOP_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_LOOP_FSHIFT 16 +#define VGV3_WRITES32_LOOP_FMASK 0xf +#define VGV3_WRITES32_ACTION_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_ACTION_FSHIFT 20 +#define VGV3_WRITES32_ACTION_FMASK 0xf +#define VGV3_WRITES32_FORMAT_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_FORMAT_FSHIFT 24 +#define VGV3_WRITES32_FORMAT_FMASK 0x7 +#define VGV3_WRITES8_ADDR_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_ADDR_FSHIFT 0 +#define VGV3_WRITES8_ADDR_FMASK 0xff +#define VGV3_WRITES8_COUNT_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_COUNT_FSHIFT 8 +#define VGV3_WRITES8_COUNT_FMASK 0xff +#define VGV3_WRITES8_LOOP_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_LOOP_FSHIFT 16 +#define VGV3_WRITES8_LOOP_FMASK 0xf +#define VGV3_WRITES8_ACTION_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_ACTION_FSHIFT 20 +#define VGV3_WRITES8_ACTION_FMASK 0xf +#define VGV3_WRITES8_FORMAT_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_FORMAT_FSHIFT 24 +#define VGV3_WRITES8_FORMAT_FMASK 0x7 +typedef struct { + unsigned RS[256]; + unsigned GRADW[2][40]; +} regstate_t; + +#define GRADW_WINDOW_START 0xc0 +#define GRADW_WINDOW_LEN 0x28 +#define GRADW_WINDOW_NUM 0x2 + +static unsigned __inline __getwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + assert( win < 2 ); + return (RS->GRADW[win][addr-0xc0] >> + shift) & mask; + } + return ((RS->RS[addr] >> shift) & mask); +} + +static void __inline __setwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & + ~(mask << shift)) | + ((mask & data) << shift); + } + RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift); +} + +static void __inline __setwreg__(regstate_t* RS, unsigned win, unsigned addr, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = data; + } + RS->RS[addr] = data; +} + +static unsigned __inline __getrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask) { + return ((RS->RS[addr] >> shift) & mask); +} + +static void __inline __setrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK); + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & + ~(mask << shift)) | ((mask & data) << shift); + } + RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift); +} + +static void __inline __setreg__(regstate_t* RS, unsigned addr, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK); + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = data; + } + RS->RS[addr] = data; +} + +#define SETWRS(win, id, value) __setwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK, value) +#define GETWRS(win, id) __getwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK) +#define SETWREG(win, reg, data) __setwreg__(&RS, win, reg, data) +#define SETRS(id, value) __setrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK, value) +#define GETRS(id) __getrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK) +#define SETREG(reg, data) __setreg__(&RS, reg, data) +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato.h b/drivers/mxc/amd-gpu/include/reg/yamato.h new file mode 100644 index 000000000000..05cae6c46403 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato.h @@ -0,0 +1,66 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _YAMATO_H +#define _YAMATO_H + +#ifndef qLittleEndian +#define qLittleEndian +#endif + +#if defined(_YDX14) +#if defined(_WIN32) && !defined(__SYMBIAN32__) +#pragma message("YDX 14 header files\r\n") +#endif +#include "yamato/14/yamato_enum.h" +#include "yamato/14/yamato_ipt.h" +#include "yamato/14/yamato_mask.h" +#include "yamato/14/yamato_offset.h" +#include "yamato/14/yamato_registers.h" +#include "yamato/14/yamato_shift.h" +#include "yamato/14/yamato_struct.h" +#include "yamato/14/yamato_typedef.h" +#define _YAMATO_GENENUM_H "reg/yamato/14/yamato_genenum.h" +#define _YAMATO_GENREG_H "reg/yamato/14/yamato_genreg.h" +#else +#if defined(_WIN32) && !defined(__SYMBIAN32__) +#pragma message("YDX 22 header files\r\n") +#endif +#include "yamato/22/yamato_enum.h" +#include "yamato/22/yamato_ipt.h" +#include "yamato/22/yamato_mask.h" +#include "yamato/22/yamato_offset.h" +#include "yamato/22/yamato_registers.h" +#include "yamato/22/yamato_shift.h" +#include "yamato/22/yamato_struct.h" +#include "yamato/22/yamato_typedef.h" +#define _YAMATO_GENENUM_H "reg/yamato/22/yamato_genenum.h" +#define _YAMATO_GENREG_H "reg/yamato/22/yamato_genreg.h" +#endif + +#endif // _YAMATO_H diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h new file mode 100644 index 000000000000..144e9151fd8a --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h @@ -0,0 +1,1895 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_ENUM_HEADER) +#define _yamato_ENUM_HEADER + +#ifndef _DRIVER_BUILD +#ifndef GL_ZERO +#define GL__ZERO BLEND_ZERO +#define GL__ONE BLEND_ONE +#define GL__SRC_COLOR BLEND_SRC_COLOR +#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR +#define GL__DST_COLOR BLEND_DST_COLOR +#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR +#define GL__SRC_ALPHA BLEND_SRC_ALPHA +#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA +#define GL__DST_ALPHA BLEND_DST_ALPHA +#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA +#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE +#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR +#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR +#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA +#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA +#endif +#endif + +/******************************************************* + * PA Enums + *******************************************************/ +#ifndef ENUMS_SU_PERFCNT_SELECT_H +#define ENUMS_SU_PERFCNT_SELECT_H +typedef enum SU_PERFCNT_SELECT { + PERF_PAPC_PASX_REQ = 0, + UNUSED1 = 1, + PERF_PAPC_PASX_FIRST_VECTOR = 2, + PERF_PAPC_PASX_SECOND_VECTOR = 3, + PERF_PAPC_PASX_FIRST_DEAD = 4, + PERF_PAPC_PASX_SECOND_DEAD = 5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, + PERF_PAPC_PA_INPUT_PRIM = 8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, + PERF_PAPC_CLPR_CULL_PRIM = 13, + UNUSED2 = 14, + PERF_PAPC_CLPR_VV_CULL_PRIM = 15, + UNUSED3 = 16, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, + UNUSED4 = 20, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, + UNUSED5 = 22, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, + PERF_PAPC_CLSM_NULL_PRIM = 36, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, + PERF_PAPC_CLSM_CLIP_PRIM = 38, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, + PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, + PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, + PERF_PAPC_SU_INPUT_PRIM = 47, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, + PERF_PAPC_SU_INPUT_NULL_PRIM = 49, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, + PERF_PAPC_SU_OUTPUT_PRIM = 57, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, + PERF_PAPC_PASX_REQ_IDLE = 69, + PERF_PAPC_PASX_REQ_BUSY = 70, + PERF_PAPC_PASX_REQ_STALLED = 71, + PERF_PAPC_PASX_REC_IDLE = 72, + PERF_PAPC_PASX_REC_BUSY = 73, + PERF_PAPC_PASX_REC_STARVED_SX = 74, + PERF_PAPC_PASX_REC_STALLED = 75, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, + PERF_PAPC_CCGSM_IDLE = 78, + PERF_PAPC_CCGSM_BUSY = 79, + PERF_PAPC_CCGSM_STALLED = 80, + PERF_PAPC_CLPRIM_IDLE = 81, + PERF_PAPC_CLPRIM_BUSY = 82, + PERF_PAPC_CLPRIM_STALLED = 83, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, + PERF_PAPC_CLIPSM_IDLE = 85, + PERF_PAPC_CLIPSM_BUSY = 86, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, + PERF_PAPC_CLIPGA_IDLE = 92, + PERF_PAPC_CLIPGA_BUSY = 93, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, + PERF_PAPC_CLIPGA_STALLED = 95, + PERF_PAPC_CLIP_IDLE = 96, + PERF_PAPC_CLIP_BUSY = 97, + PERF_PAPC_SU_IDLE = 98, + PERF_PAPC_SU_BUSY = 99, + PERF_PAPC_SU_STARVED_CLIP = 100, + PERF_PAPC_SU_STALLED_SC = 101, + PERF_PAPC_SU_FACENESS_CULL = 102, +} SU_PERFCNT_SELECT; +#endif /*ENUMS_SU_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SC_PERFCNT_SELECT_H +#define ENUMS_SC_PERFCNT_SELECT_H +typedef enum SC_PERFCNT_SELECT { + SC_SR_WINDOW_VALID = 0, + SC_CW_WINDOW_VALID = 1, + SC_QM_WINDOW_VALID = 2, + SC_FW_WINDOW_VALID = 3, + SC_EZ_WINDOW_VALID = 4, + SC_IT_WINDOW_VALID = 5, + SC_STARVED_BY_PA = 6, + SC_STALLED_BY_RB_TILE = 7, + SC_STALLED_BY_RB_SAMP = 8, + SC_STARVED_BY_RB_EZ = 9, + SC_STALLED_BY_SAMPLE_FF = 10, + SC_STALLED_BY_SQ = 11, + SC_STALLED_BY_SP = 12, + SC_TOTAL_NO_PRIMS = 13, + SC_NON_EMPTY_PRIMS = 14, + SC_NO_TILES_PASSING_QM = 15, + SC_NO_PIXELS_PRE_EZ = 16, + SC_NO_PIXELS_POST_EZ = 17, +} SC_PERFCNT_SELECT; +#endif /*ENUMS_SC_PERFCNT_SELECT_H*/ + +/******************************************************* + * VGT Enums + *******************************************************/ +#ifndef ENUMS_VGT_DI_PRIM_TYPE_H +#define ENUMS_VGT_DI_PRIM_TYPE_H +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0, + DI_PT_POINTLIST = 1, + DI_PT_LINELIST = 2, + DI_PT_LINESTRIP = 3, + DI_PT_TRILIST = 4, + DI_PT_TRIFAN = 5, + DI_PT_TRISTRIP = 6, + DI_PT_UNUSED_1 = 7, + DI_PT_RECTLIST = 8, + DI_PT_UNUSED_2 = 9, + DI_PT_UNUSED_3 = 10, + DI_PT_UNUSED_4 = 11, + DI_PT_UNUSED_5 = 12, + DI_PT_QUADLIST = 13, + DI_PT_QUADSTRIP = 14, + DI_PT_POLYGON = 15, + DI_PT_2D_COPY_RECT_LIST_V0 = 16, + DI_PT_2D_COPY_RECT_LIST_V1 = 17, + DI_PT_2D_COPY_RECT_LIST_V2 = 18, + DI_PT_2D_COPY_RECT_LIST_V3 = 19, + DI_PT_2D_FILL_RECT_LIST = 20, + DI_PT_2D_LINE_STRIP = 21, + DI_PT_2D_TRI_STRIP = 22, +} VGT_DI_PRIM_TYPE; +#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/ + +#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H +#define ENUMS_VGT_DI_SOURCE_SELECT_H +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0, + DI_SRC_SEL_IMMEDIATE = 1, + DI_SRC_SEL_AUTO_INDEX = 2, + DI_SRC_SEL_RESERVED = 3 +} VGT_DI_SOURCE_SELECT; +#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +typedef enum VGT_DI_FACENESS_CULL_SELECT { + DI_FACE_CULL_NONE = 0, + DI_FACE_CULL_FETCH = 1, + DI_FACE_BACKFACE_CULL = 2, + DI_FACE_FRONTFACE_CULL = 3 +} VGT_DI_FACENESS_CULL_SELECT; +#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_INDEX_SIZE_H +#define ENUMS_VGT_DI_INDEX_SIZE_H +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0, + DI_INDEX_SIZE_32_BIT = 1 +} VGT_DI_INDEX_SIZE; +#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/ + +#ifndef ENUMS_VGT_DI_SMALL_INDEX_H +#define ENUMS_VGT_DI_SMALL_INDEX_H +typedef enum VGT_DI_SMALL_INDEX { + DI_USE_INDEX_SIZE = 0, + DI_INDEX_SIZE_8_BIT = 1 +} VGT_DI_SMALL_INDEX; +#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/ + +#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE { + DISABLE_PRE_FETCH_CULL_ENABLE = 0, + PRE_FETCH_CULL_ENABLE = 1 +} VGT_DI_PRE_FETCH_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H +#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H +typedef enum VGT_DI_GRP_CULL_ENABLE { + DISABLE_GRP_CULL_ENABLE = 0, + GRP_CULL_ENABLE = 1 +} VGT_DI_GRP_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_EVENT_TYPE_H +#define ENUMS_VGT_EVENT_TYPE_H +typedef enum VGT_EVENT_TYPE { + VS_DEALLOC = 0, + PS_DEALLOC = 1, + VS_DONE_TS = 2, + PS_DONE_TS = 3, + CACHE_FLUSH_TS = 4, + CONTEXT_DONE = 5, + CACHE_FLUSH = 6, + VIZQUERY_START = 7, + VIZQUERY_END = 8, + SC_WAIT_WC = 9, + RST_PIX_CNT = 13, + RST_VTX_CNT = 14, + TILE_FLUSH = 15, + CACHE_FLUSH_AND_INV_TS_EVENT = 20, + ZPASS_DONE = 21, + CACHE_FLUSH_AND_INV_EVENT = 22, + PERFCOUNTER_START = 23, + PERFCOUNTER_STOP = 24, + VS_FETCH_DONE = 27, + FACENESS_FLUSH = 28, +} VGT_EVENT_TYPE; +#endif /*ENUMS_VGT_EVENT_TYPE_H*/ + +#ifndef ENUMS_VGT_DMA_SWAP_MODE_H +#define ENUMS_VGT_DMA_SWAP_MODE_H +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0, + VGT_DMA_SWAP_16_BIT = 1, + VGT_DMA_SWAP_32_BIT = 2, + VGT_DMA_SWAP_WORD = 3 +} VGT_DMA_SWAP_MODE; +#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/ + +#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H +#define ENUMS_VGT_PERFCOUNT_SELECT_H +typedef enum VGT_PERFCOUNT_SELECT { + VGT_SQ_EVENT_WINDOW_ACTIVE = 0, + VGT_SQ_SEND = 1, + VGT_SQ_STALLED = 2, + VGT_SQ_STARVED_BUSY = 3, + VGT_SQ_STARVED_IDLE = 4, + VGT_SQ_STATIC = 5, + VGT_PA_EVENT_WINDOW_ACTIVE = 6, + VGT_PA_CLIP_V_SEND = 7, + VGT_PA_CLIP_V_STALLED = 8, + VGT_PA_CLIP_V_STARVED_BUSY = 9, + VGT_PA_CLIP_V_STARVED_IDLE = 10, + VGT_PA_CLIP_V_STATIC = 11, + VGT_PA_CLIP_P_SEND = 12, + VGT_PA_CLIP_P_STALLED = 13, + VGT_PA_CLIP_P_STARVED_BUSY = 14, + VGT_PA_CLIP_P_STARVED_IDLE = 15, + VGT_PA_CLIP_P_STATIC = 16, + VGT_PA_CLIP_S_SEND = 17, + VGT_PA_CLIP_S_STALLED = 18, + VGT_PA_CLIP_S_STARVED_BUSY = 19, + VGT_PA_CLIP_S_STARVED_IDLE = 20, + VGT_PA_CLIP_S_STATIC = 21, + RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, + RBIU_IMMED_DATA_FIFO_STARVED = 23, + RBIU_IMMED_DATA_FIFO_STALLED = 24, + RBIU_DMA_REQUEST_FIFO_STARVED = 25, + RBIU_DMA_REQUEST_FIFO_STALLED = 26, + RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, + RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, + BIN_PRIM_NEAR_CULL = 29, + BIN_PRIM_ZERO_CULL = 30, + BIN_PRIM_FAR_CULL = 31, + BIN_PRIM_BIN_CULL = 32, + BIN_PRIM_FACE_CULL = 33, + SPARE34 = 34, + SPARE35 = 35, + SPARE36 = 36, + SPARE37 = 37, + SPARE38 = 38, + SPARE39 = 39, + TE_SU_IN_VALID = 40, + TE_SU_IN_READ = 41, + TE_SU_IN_PRIM = 42, + TE_SU_IN_EOP = 43, + TE_SU_IN_NULL_PRIM = 44, + TE_WK_IN_VALID = 45, + TE_WK_IN_READ = 46, + TE_OUT_PRIM_VALID = 47, + TE_OUT_PRIM_READ = 48, +} VGT_PERFCOUNT_SELECT; +#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TP Enums + *******************************************************/ +#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H +#define ENUMS_TCR_PERFCOUNT_SELECT_H +typedef enum TCR_PERFCOUNT_SELECT { + DGMMPD_IPMUX0_STALL = 0, + reserved_46 = 1, + reserved_47 = 2, + reserved_48 = 3, + DGMMPD_IPMUX_ALL_STALL = 4, + OPMUX0_L2_WRITES = 5, + reserved_49 = 6, + reserved_50 = 7, + reserved_51 = 8, +} TCR_PERFCOUNT_SELECT; +#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TP_PERFCOUNT_SELECT_H +#define ENUMS_TP_PERFCOUNT_SELECT_H +typedef enum TP_PERFCOUNT_SELECT { + POINT_QUADS = 0, + BILIN_QUADS = 1, + ANISO_QUADS = 2, + MIP_QUADS = 3, + VOL_QUADS = 4, + MIP_VOL_QUADS = 5, + MIP_ANISO_QUADS = 6, + VOL_ANISO_QUADS = 7, + ANISO_2_1_QUADS = 8, + ANISO_4_1_QUADS = 9, + ANISO_6_1_QUADS = 10, + ANISO_8_1_QUADS = 11, + ANISO_10_1_QUADS = 12, + ANISO_12_1_QUADS = 13, + ANISO_14_1_QUADS = 14, + ANISO_16_1_QUADS = 15, + MIP_VOL_ANISO_QUADS = 16, + ALIGN_2_QUADS = 17, + ALIGN_4_QUADS = 18, + PIX_0_QUAD = 19, + PIX_1_QUAD = 20, + PIX_2_QUAD = 21, + PIX_3_QUAD = 22, + PIX_4_QUAD = 23, + TP_MIPMAP_LOD0 = 24, + TP_MIPMAP_LOD1 = 25, + TP_MIPMAP_LOD2 = 26, + TP_MIPMAP_LOD3 = 27, + TP_MIPMAP_LOD4 = 28, + TP_MIPMAP_LOD5 = 29, + TP_MIPMAP_LOD6 = 30, + TP_MIPMAP_LOD7 = 31, + TP_MIPMAP_LOD8 = 32, + TP_MIPMAP_LOD9 = 33, + TP_MIPMAP_LOD10 = 34, + TP_MIPMAP_LOD11 = 35, + TP_MIPMAP_LOD12 = 36, + TP_MIPMAP_LOD13 = 37, + TP_MIPMAP_LOD14 = 38, +} TP_PERFCOUNT_SELECT; +#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H +#define ENUMS_TCM_PERFCOUNT_SELECT_H +typedef enum TCM_PERFCOUNT_SELECT { + QUAD0_RD_LAT_FIFO_EMPTY = 0, + reserved_01 = 1, + reserved_02 = 2, + QUAD0_RD_LAT_FIFO_4TH_FULL = 3, + QUAD0_RD_LAT_FIFO_HALF_FULL = 4, + QUAD0_RD_LAT_FIFO_FULL = 5, + QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, + reserved_07 = 7, + reserved_08 = 8, + reserved_09 = 9, + reserved_10 = 10, + reserved_11 = 11, + reserved_12 = 12, + reserved_13 = 13, + reserved_14 = 14, + reserved_15 = 15, + reserved_16 = 16, + reserved_17 = 17, + reserved_18 = 18, + reserved_19 = 19, + reserved_20 = 20, + reserved_21 = 21, + reserved_22 = 22, + reserved_23 = 23, + reserved_24 = 24, + reserved_25 = 25, + reserved_26 = 26, + reserved_27 = 27, + READ_STARVED_QUAD0 = 28, + reserved_29 = 29, + reserved_30 = 30, + reserved_31 = 31, + READ_STARVED = 32, + READ_STALLED_QUAD0 = 33, + reserved_34 = 34, + reserved_35 = 35, + reserved_36 = 36, + READ_STALLED = 37, + VALID_READ_QUAD0 = 38, + reserved_39 = 39, + reserved_40 = 40, + reserved_41 = 41, + TC_TP_STARVED_QUAD0 = 42, + reserved_43 = 43, + reserved_44 = 44, + reserved_45 = 45, + TC_TP_STARVED = 46, +} TCM_PERFCOUNT_SELECT; +#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H +#define ENUMS_TCF_PERFCOUNT_SELECT_H +typedef enum TCF_PERFCOUNT_SELECT { + VALID_CYCLES = 0, + SINGLE_PHASES = 1, + ANISO_PHASES = 2, + MIP_PHASES = 3, + VOL_PHASES = 4, + MIP_VOL_PHASES = 5, + MIP_ANISO_PHASES = 6, + VOL_ANISO_PHASES = 7, + ANISO_2_1_PHASES = 8, + ANISO_4_1_PHASES = 9, + ANISO_6_1_PHASES = 10, + ANISO_8_1_PHASES = 11, + ANISO_10_1_PHASES = 12, + ANISO_12_1_PHASES = 13, + ANISO_14_1_PHASES = 14, + ANISO_16_1_PHASES = 15, + MIP_VOL_ANISO_PHASES = 16, + ALIGN_2_PHASES = 17, + ALIGN_4_PHASES = 18, + TPC_BUSY = 19, + TPC_STALLED = 20, + TPC_STARVED = 21, + TPC_WORKING = 22, + TPC_WALKER_BUSY = 23, + TPC_WALKER_STALLED = 24, + TPC_WALKER_WORKING = 25, + TPC_ALIGNER_BUSY = 26, + TPC_ALIGNER_STALLED = 27, + TPC_ALIGNER_STALLED_BY_BLEND = 28, + TPC_ALIGNER_STALLED_BY_CACHE = 29, + TPC_ALIGNER_WORKING = 30, + TPC_BLEND_BUSY = 31, + TPC_BLEND_SYNC = 32, + TPC_BLEND_STARVED = 33, + TPC_BLEND_WORKING = 34, + OPCODE_0x00 = 35, + OPCODE_0x01 = 36, + OPCODE_0x04 = 37, + OPCODE_0x10 = 38, + OPCODE_0x11 = 39, + OPCODE_0x12 = 40, + OPCODE_0x13 = 41, + OPCODE_0x18 = 42, + OPCODE_0x19 = 43, + OPCODE_0x1A = 44, + OPCODE_OTHER = 45, + IN_FIFO_0_EMPTY = 56, + IN_FIFO_0_LT_HALF_FULL = 57, + IN_FIFO_0_HALF_FULL = 58, + IN_FIFO_0_FULL = 59, + IN_FIFO_TPC_EMPTY = 72, + IN_FIFO_TPC_LT_HALF_FULL = 73, + IN_FIFO_TPC_HALF_FULL = 74, + IN_FIFO_TPC_FULL = 75, + TPC_TC_XFC = 76, + TPC_TC_STATE = 77, + TC_STALL = 78, + QUAD0_TAPS = 79, + QUADS = 83, + TCA_SYNC_STALL = 84, + TAG_STALL = 85, + TCB_SYNC_STALL = 88, + TCA_VALID = 89, + PROBES_VALID = 90, + MISS_STALL = 91, + FETCH_FIFO_STALL = 92, + TCO_STALL = 93, + ANY_STALL = 94, + TAG_MISSES = 95, + TAG_HITS = 96, + SUB_TAG_MISSES = 97, + SET0_INVALIDATES = 98, + SET1_INVALIDATES = 99, + SET2_INVALIDATES = 100, + SET3_INVALIDATES = 101, + SET0_TAG_MISSES = 102, + SET1_TAG_MISSES = 103, + SET2_TAG_MISSES = 104, + SET3_TAG_MISSES = 105, + SET0_TAG_HITS = 106, + SET1_TAG_HITS = 107, + SET2_TAG_HITS = 108, + SET3_TAG_HITS = 109, + SET0_SUB_TAG_MISSES = 110, + SET1_SUB_TAG_MISSES = 111, + SET2_SUB_TAG_MISSES = 112, + SET3_SUB_TAG_MISSES = 113, + SET0_EVICT1 = 114, + SET0_EVICT2 = 115, + SET0_EVICT3 = 116, + SET0_EVICT4 = 117, + SET0_EVICT5 = 118, + SET0_EVICT6 = 119, + SET0_EVICT7 = 120, + SET0_EVICT8 = 121, + SET1_EVICT1 = 130, + SET1_EVICT2 = 131, + SET1_EVICT3 = 132, + SET1_EVICT4 = 133, + SET1_EVICT5 = 134, + SET1_EVICT6 = 135, + SET1_EVICT7 = 136, + SET1_EVICT8 = 137, + SET2_EVICT1 = 146, + SET2_EVICT2 = 147, + SET2_EVICT3 = 148, + SET2_EVICT4 = 149, + SET2_EVICT5 = 150, + SET2_EVICT6 = 151, + SET2_EVICT7 = 152, + SET2_EVICT8 = 153, + SET3_EVICT1 = 162, + SET3_EVICT2 = 163, + SET3_EVICT3 = 164, + SET3_EVICT4 = 165, + SET3_EVICT5 = 166, + SET3_EVICT6 = 167, + SET3_EVICT7 = 168, + SET3_EVICT8 = 169, + FF_EMPTY = 178, + FF_LT_HALF_FULL = 179, + FF_HALF_FULL = 180, + FF_FULL = 181, + FF_XFC = 182, + FF_STALLED = 183, + FG_MASKS = 184, + FG_LEFT_MASKS = 185, + FG_LEFT_MASK_STALLED = 186, + FG_LEFT_NOT_DONE_STALL = 187, + FG_LEFT_FG_STALL = 188, + FG_LEFT_SECTORS = 189, + FG0_REQUESTS = 195, + FG0_STALLED = 196, + MEM_REQ512 = 199, + MEM_REQ_SENT = 200, + MEM_LOCAL_READ_REQ = 202, + TC0_MH_STALLED = 203, +} TCF_PERFCOUNT_SELECT; +#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +#ifndef ENUMS_SQ_PERFCNT_SELECT_H +#define ENUMS_SQ_PERFCNT_SELECT_H +typedef enum SQ_PERFCNT_SELECT { + SQ_PIXEL_VECTORS_SUB = 0, + SQ_VERTEX_VECTORS_SUB = 1, + SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, + SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, + SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, + SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, + SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, + SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, + SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, + SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, + SQ_EXPORT_CYCLES = 10, + SQ_ALU_CST_WRITTEN = 11, + SQ_TEX_CST_WRITTEN = 12, + SQ_ALU_CST_STALL = 13, + SQ_ALU_TEX_STALL = 14, + SQ_INST_WRITTEN = 15, + SQ_BOOLEAN_WRITTEN = 16, + SQ_LOOPS_WRITTEN = 17, + SQ_PIXEL_SWAP_IN = 18, + SQ_PIXEL_SWAP_OUT = 19, + SQ_VERTEX_SWAP_IN = 20, + SQ_VERTEX_SWAP_OUT = 21, + SQ_ALU_VTX_INST_ISSUED = 22, + SQ_TEX_VTX_INST_ISSUED = 23, + SQ_VC_VTX_INST_ISSUED = 24, + SQ_CF_VTX_INST_ISSUED = 25, + SQ_ALU_PIX_INST_ISSUED = 26, + SQ_TEX_PIX_INST_ISSUED = 27, + SQ_VC_PIX_INST_ISSUED = 28, + SQ_CF_PIX_INST_ISSUED = 29, + SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, + SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, + SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, + SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, + SQ_ALU_NOPS = 34, + SQ_PRED_SKIP = 35, + SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, + SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, + SQ_SYNC_TEX_STALL_VTX = 38, + SQ_SYNC_VC_STALL_VTX = 39, + SQ_CONSTANTS_USED_SIMD0 = 40, + SQ_CONSTANTS_SENT_SP_SIMD0 = 41, + SQ_GPR_STALL_VTX = 42, + SQ_GPR_STALL_PIX = 43, + SQ_VTX_RS_STALL = 44, + SQ_PIX_RS_STALL = 45, + SQ_SX_PC_FULL = 46, + SQ_SX_EXP_BUFF_FULL = 47, + SQ_SX_POS_BUFF_FULL = 48, + SQ_INTERP_QUADS = 49, + SQ_INTERP_ACTIVE = 50, + SQ_IN_PIXEL_STALL = 51, + SQ_IN_VTX_STALL = 52, + SQ_VTX_CNT = 53, + SQ_VTX_VECTOR2 = 54, + SQ_VTX_VECTOR3 = 55, + SQ_VTX_VECTOR4 = 56, + SQ_PIXEL_VECTOR1 = 57, + SQ_PIXEL_VECTOR23 = 58, + SQ_PIXEL_VECTOR4 = 59, + SQ_CONSTANTS_USED_SIMD1 = 60, + SQ_CONSTANTS_SENT_SP_SIMD1 = 61, + SQ_SX_MEM_EXP_FULL = 62, + SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, + SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, + SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, + SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, + SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, + SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, + SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, + SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, + SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, + SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, + SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, + SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, + SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, + SQ_PERFCOUNT_VTX_POP_THREAD = 76, + SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, + SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, + SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, + SQ_PERFCOUNT_PIX_POP_THREAD = 80, + SQ_SYNC_TEX_STALL_PIX = 81, + SQ_SYNC_VC_STALL_PIX = 82, + SQ_CONSTANTS_USED_SIMD2 = 83, + SQ_CONSTANTS_SENT_SP_SIMD2 = 84, + SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, + SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, + SQ_ALU0_FIFO_FULL_SIMD0 = 87, + SQ_ALU1_FIFO_FULL_SIMD0 = 88, + SQ_ALU0_FIFO_FULL_SIMD1 = 89, + SQ_ALU1_FIFO_FULL_SIMD1 = 90, + SQ_ALU0_FIFO_FULL_SIMD2 = 91, + SQ_ALU1_FIFO_FULL_SIMD2 = 92, + SQ_ALU0_FIFO_FULL_SIMD3 = 93, + SQ_ALU1_FIFO_FULL_SIMD3 = 94, + VC_PERF_STATIC = 95, + VC_PERF_STALLED = 96, + VC_PERF_STARVED = 97, + VC_PERF_SEND = 98, + VC_PERF_ACTUAL_STARVED = 99, + PIXEL_THREAD_0_ACTIVE = 100, + VERTEX_THREAD_0_ACTIVE = 101, + PIXEL_THREAD_0_NUMBER = 102, + VERTEX_THREAD_0_NUMBER = 103, + VERTEX_EVENT_NUMBER = 104, + PIXEL_EVENT_NUMBER = 105, + PTRBUFF_EF_PUSH = 106, + PTRBUFF_EF_POP_EVENT = 107, + PTRBUFF_EF_POP_NEW_VTX = 108, + PTRBUFF_EF_POP_DEALLOC = 109, + PTRBUFF_EF_POP_PVECTOR = 110, + PTRBUFF_EF_POP_PVECTOR_X = 111, + PTRBUFF_EF_POP_PVECTOR_VNZ = 112, + PTRBUFF_PB_DEALLOC = 113, + PTRBUFF_PI_STATE_PPB_POP = 114, + PTRBUFF_PI_RTR = 115, + PTRBUFF_PI_READ_EN = 116, + PTRBUFF_PI_BUFF_SWAP = 117, + PTRBUFF_SQ_FREE_BUFF = 118, + PTRBUFF_SQ_DEC = 119, + PTRBUFF_SC_VALID_CNTL_EVENT = 120, + PTRBUFF_SC_VALID_IJ_XFER = 121, + PTRBUFF_SC_NEW_VECTOR_1_Q = 122, + PTRBUFF_QUAL_NEW_VECTOR = 123, + PTRBUFF_QUAL_EVENT = 124, + PTRBUFF_END_BUFFER = 125, + PTRBUFF_FILL_QUAD = 126, + VERTS_WRITTEN_SPI = 127, + TP_FETCH_INSTR_EXEC = 128, + TP_FETCH_INSTR_REQ = 129, + TP_DATA_RETURN = 130, + SPI_WRITE_CYCLES_SP = 131, + SPI_WRITES_SP = 132, + SP_ALU_INSTR_EXEC = 133, + SP_CONST_ADDR_TO_SQ = 134, + SP_PRED_KILLS_TO_SQ = 135, + SP_EXPORT_CYCLES_TO_SX = 136, + SP_EXPORTS_TO_SX = 137, + SQ_CYCLES_ELAPSED = 138, + SQ_TCFS_OPT_ALLOC_EXEC = 139, + SQ_TCFS_NO_OPT_ALLOC = 140, + SQ_ALU0_NO_OPT_ALLOC = 141, + SQ_ALU1_NO_OPT_ALLOC = 142, + SQ_TCFS_ARB_XFC_CNT = 143, + SQ_ALU0_ARB_XFC_CNT = 144, + SQ_ALU1_ARB_XFC_CNT = 145, + SQ_TCFS_CFS_UPDATE_CNT = 146, + SQ_ALU0_CFS_UPDATE_CNT = 147, + SQ_ALU1_CFS_UPDATE_CNT = 148, + SQ_VTX_PUSH_THREAD_CNT = 149, + SQ_VTX_POP_THREAD_CNT = 150, + SQ_PIX_PUSH_THREAD_CNT = 151, + SQ_PIX_POP_THREAD_CNT = 152, + SQ_PIX_TOTAL = 153, + SQ_PIX_KILLED = 154, +} SQ_PERFCNT_SELECT; +#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SX_PERFCNT_SELECT_H +#define ENUMS_SX_PERFCNT_SELECT_H +typedef enum SX_PERFCNT_SELECT { + SX_EXPORT_VECTORS = 0, + SX_DUMMY_QUADS = 1, + SX_ALPHA_FAIL = 2, + SX_RB_QUAD_BUSY = 3, + SX_RB_COLOR_BUSY = 4, + SX_RB_QUAD_STALL = 5, + SX_RB_COLOR_STALL = 6, +} SX_PERFCNT_SELECT; +#endif /*ENUMS_SX_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_Abs_modifier_H +#define ENUMS_Abs_modifier_H +typedef enum Abs_modifier { + NO_ABS_MOD = 0, + ABS_MOD = 1 +} Abs_modifier; +#endif /*ENUMS_Abs_modifier_H*/ + +#ifndef ENUMS_Exporting_H +#define ENUMS_Exporting_H +typedef enum Exporting { + NOT_EXPORTING = 0, + EXPORTING = 1 +} Exporting; +#endif /*ENUMS_Exporting_H*/ + +#ifndef ENUMS_ScalarOpcode_H +#define ENUMS_ScalarOpcode_H +typedef enum ScalarOpcode { + ADDs = 0, + ADD_PREVs = 1, + MULs = 2, + MUL_PREVs = 3, + MUL_PREV2s = 4, + MAXs = 5, + MINs = 6, + SETEs = 7, + SETGTs = 8, + SETGTEs = 9, + SETNEs = 10, + FRACs = 11, + TRUNCs = 12, + FLOORs = 13, + EXP_IEEE = 14, + LOG_CLAMP = 15, + LOG_IEEE = 16, + RECIP_CLAMP = 17, + RECIP_FF = 18, + RECIP_IEEE = 19, + RECIPSQ_CLAMP = 20, + RECIPSQ_FF = 21, + RECIPSQ_IEEE = 22, + MOVAs = 23, + MOVA_FLOORs = 24, + SUBs = 25, + SUB_PREVs = 26, + PRED_SETEs = 27, + PRED_SETNEs = 28, + PRED_SETGTs = 29, + PRED_SETGTEs = 30, + PRED_SET_INVs = 31, + PRED_SET_POPs = 32, + PRED_SET_CLRs = 33, + PRED_SET_RESTOREs = 34, + KILLEs = 35, + KILLGTs = 36, + KILLGTEs = 37, + KILLNEs = 38, + KILLONEs = 39, + SQRT_IEEE = 40, + MUL_CONST_0 = 42, + MUL_CONST_1 = 43, + ADD_CONST_0 = 44, + ADD_CONST_1 = 45, + SUB_CONST_0 = 46, + SUB_CONST_1 = 47, + SIN = 48, + COS = 49, + RETAIN_PREV = 50, +} ScalarOpcode; +#endif /*ENUMS_ScalarOpcode_H*/ + +#ifndef ENUMS_SwizzleType_H +#define ENUMS_SwizzleType_H +typedef enum SwizzleType { + NO_SWIZZLE = 0, + SHIFT_RIGHT_1 = 1, + SHIFT_RIGHT_2 = 2, + SHIFT_RIGHT_3 = 3 +} SwizzleType; +#endif /*ENUMS_SwizzleType_H*/ + +#ifndef ENUMS_InputModifier_H +#define ENUMS_InputModifier_H +typedef enum InputModifier { + NIL = 0, + NEGATE = 1 +} InputModifier; +#endif /*ENUMS_InputModifier_H*/ + +#ifndef ENUMS_PredicateSelect_H +#define ENUMS_PredicateSelect_H +typedef enum PredicateSelect { + NO_PREDICATION = 0, + PREDICATE_QUAD = 1, + PREDICATED_2 = 2, + PREDICATED_3 = 3 +} PredicateSelect; +#endif /*ENUMS_PredicateSelect_H*/ + +#ifndef ENUMS_OperandSelect1_H +#define ENUMS_OperandSelect1_H +typedef enum OperandSelect1 { + ABSOLUTE_REG = 0, + RELATIVE_REG = 1 +} OperandSelect1; +#endif /*ENUMS_OperandSelect1_H*/ + +#ifndef ENUMS_VectorOpcode_H +#define ENUMS_VectorOpcode_H +typedef enum VectorOpcode { + ADDv = 0, + MULv = 1, + MAXv = 2, + MINv = 3, + SETEv = 4, + SETGTv = 5, + SETGTEv = 6, + SETNEv = 7, + FRACv = 8, + TRUNCv = 9, + FLOORv = 10, + MULADDv = 11, + CNDEv = 12, + CNDGTEv = 13, + CNDGTv = 14, + DOT4v = 15, + DOT3v = 16, + DOT2ADDv = 17, + CUBEv = 18, + MAX4v = 19, + PRED_SETE_PUSHv = 20, + PRED_SETNE_PUSHv = 21, + PRED_SETGT_PUSHv = 22, + PRED_SETGTE_PUSHv = 23, + KILLEv = 24, + KILLGTv = 25, + KILLGTEv = 26, + KILLNEv = 27, + DSTv = 28, + MOVAv = 29, +} VectorOpcode; +#endif /*ENUMS_VectorOpcode_H*/ + +#ifndef ENUMS_OperandSelect0_H +#define ENUMS_OperandSelect0_H +typedef enum OperandSelect0 { + CONSTANT = 0, + NON_CONSTANT = 1 +} OperandSelect0; +#endif /*ENUMS_OperandSelect0_H*/ + +#ifndef ENUMS_Ressource_type_H +#define ENUMS_Ressource_type_H +typedef enum Ressource_type { + ALU = 0, + TEXTURE = 1 +} Ressource_type; +#endif /*ENUMS_Ressource_type_H*/ + +#ifndef ENUMS_Instruction_serial_H +#define ENUMS_Instruction_serial_H +typedef enum Instruction_serial { + NOT_SERIAL = 0, + SERIAL = 1 +} Instruction_serial; +#endif /*ENUMS_Instruction_serial_H*/ + +#ifndef ENUMS_VC_type_H +#define ENUMS_VC_type_H +typedef enum VC_type { + ALU_TP_REQUEST = 0, + VC_REQUEST = 1 +} VC_type; +#endif /*ENUMS_VC_type_H*/ + +#ifndef ENUMS_Addressing_H +#define ENUMS_Addressing_H +typedef enum Addressing { + RELATIVE_ADDR = 0, + ABSOLUTE_ADDR = 1 +} Addressing; +#endif /*ENUMS_Addressing_H*/ + +#ifndef ENUMS_CFOpcode_H +#define ENUMS_CFOpcode_H +typedef enum CFOpcode { + NOP = 0, + EXECUTE = 1, + EXECUTE_END = 2, + COND_EXECUTE = 3, + COND_EXECUTE_END = 4, + COND_PRED_EXECUTE = 5, + COND_PRED_EXECUTE_END = 6, + LOOP_START = 7, + LOOP_END = 8, + COND_CALL = 9, + RETURN = 10, + COND_JMP = 11, + ALLOCATE = 12, + COND_EXECUTE_PRED_CLEAN = 13, + COND_EXECUTE_PRED_CLEAN_END = 14, + MARK_VS_FETCH_DONE = 15 +} CFOpcode; +#endif /*ENUMS_CFOpcode_H*/ + +#ifndef ENUMS_Allocation_type_H +#define ENUMS_Allocation_type_H +typedef enum Allocation_type { + SQ_NO_ALLOC = 0, + SQ_POSITION = 1, + SQ_PARAMETER_PIXEL = 2, + SQ_MEMORY = 3 +} Allocation_type; +#endif /*ENUMS_Allocation_type_H*/ + +#ifndef ENUMS_TexInstOpcode_H +#define ENUMS_TexInstOpcode_H +typedef enum TexInstOpcode { + TEX_INST_FETCH = 1, + TEX_INST_RESERVED_1 = 2, + TEX_INST_RESERVED_2 = 3, + TEX_INST_RESERVED_3 = 4, + TEX_INST_GET_BORDER_COLOR_FRAC = 16, + TEX_INST_GET_COMP_TEX_LOD = 17, + TEX_INST_GET_GRADIENTS = 18, + TEX_INST_GET_WEIGHTS = 19, + TEX_INST_SET_TEX_LOD = 24, + TEX_INST_SET_GRADIENTS_H = 25, + TEX_INST_SET_GRADIENTS_V = 26, + TEX_INST_RESERVED_4 = 27, +} TexInstOpcode; +#endif /*ENUMS_TexInstOpcode_H*/ + +#ifndef ENUMS_Addressmode_H +#define ENUMS_Addressmode_H +typedef enum Addressmode { + LOGICAL = 0, + LOOP_RELATIVE = 1 +} Addressmode; +#endif /*ENUMS_Addressmode_H*/ + +#ifndef ENUMS_TexCoordDenorm_H +#define ENUMS_TexCoordDenorm_H +typedef enum TexCoordDenorm { + TEX_COORD_NORMALIZED = 0, + TEX_COORD_UNNORMALIZED = 1 +} TexCoordDenorm; +#endif /*ENUMS_TexCoordDenorm_H*/ + +#ifndef ENUMS_SrcSel_H +#define ENUMS_SrcSel_H +typedef enum SrcSel { + SRC_SEL_X = 0, + SRC_SEL_Y = 1, + SRC_SEL_Z = 2, + SRC_SEL_W = 3 +} SrcSel; +#endif /*ENUMS_SrcSel_H*/ + +#ifndef ENUMS_DstSel_H +#define ENUMS_DstSel_H +typedef enum DstSel { + DST_SEL_X = 0, + DST_SEL_Y = 1, + DST_SEL_Z = 2, + DST_SEL_W = 3, + DST_SEL_0 = 4, + DST_SEL_1 = 5, + DST_SEL_RSVD = 6, + DST_SEL_MASK = 7 +} DstSel; +#endif /*ENUMS_DstSel_H*/ + +#ifndef ENUMS_MagFilter_H +#define ENUMS_MagFilter_H +typedef enum MagFilter { + MAG_FILTER_POINT = 0, + MAG_FILTER_LINEAR = 1, + MAG_FILTER_RESERVED_0 = 2, + MAG_FILTER_USE_FETCH_CONST = 3 +} MagFilter; +#endif /*ENUMS_MagFilter_H*/ + +#ifndef ENUMS_MinFilter_H +#define ENUMS_MinFilter_H +typedef enum MinFilter { + MIN_FILTER_POINT = 0, + MIN_FILTER_LINEAR = 1, + MIN_FILTER_RESERVED_0 = 2, + MIN_FILTER_USE_FETCH_CONST = 3 +} MinFilter; +#endif /*ENUMS_MinFilter_H*/ + +#ifndef ENUMS_MipFilter_H +#define ENUMS_MipFilter_H +typedef enum MipFilter { + MIP_FILTER_POINT = 0, + MIP_FILTER_LINEAR = 1, + MIP_FILTER_BASEMAP = 2, + MIP_FILTER_USE_FETCH_CONST = 3 +} MipFilter; +#endif /*ENUMS_MipFilter_H*/ + +#ifndef ENUMS_AnisoFilter_H +#define ENUMS_AnisoFilter_H +typedef enum AnisoFilter { + ANISO_FILTER_DISABLED = 0, + ANISO_FILTER_MAX_1_1 = 1, + ANISO_FILTER_MAX_2_1 = 2, + ANISO_FILTER_MAX_4_1 = 3, + ANISO_FILTER_MAX_8_1 = 4, + ANISO_FILTER_MAX_16_1 = 5, + ANISO_FILTER_USE_FETCH_CONST = 7 +} AnisoFilter; +#endif /*ENUMS_AnisoFilter_H*/ + +#ifndef ENUMS_ArbitraryFilter_H +#define ENUMS_ArbitraryFilter_H +typedef enum ArbitraryFilter { + ARBITRARY_FILTER_2X4_SYM = 0, + ARBITRARY_FILTER_2X4_ASYM = 1, + ARBITRARY_FILTER_4X2_SYM = 2, + ARBITRARY_FILTER_4X2_ASYM = 3, + ARBITRARY_FILTER_4X4_SYM = 4, + ARBITRARY_FILTER_4X4_ASYM = 5, + ARBITRARY_FILTER_USE_FETCH_CONST = 7 +} ArbitraryFilter; +#endif /*ENUMS_ArbitraryFilter_H*/ + +#ifndef ENUMS_VolMagFilter_H +#define ENUMS_VolMagFilter_H +typedef enum VolMagFilter { + VOL_MAG_FILTER_POINT = 0, + VOL_MAG_FILTER_LINEAR = 1, + VOL_MAG_FILTER_USE_FETCH_CONST = 3 +} VolMagFilter; +#endif /*ENUMS_VolMagFilter_H*/ + +#ifndef ENUMS_VolMinFilter_H +#define ENUMS_VolMinFilter_H +typedef enum VolMinFilter { + VOL_MIN_FILTER_POINT = 0, + VOL_MIN_FILTER_LINEAR = 1, + VOL_MIN_FILTER_USE_FETCH_CONST = 3 +} VolMinFilter; +#endif /*ENUMS_VolMinFilter_H*/ + +#ifndef ENUMS_PredSelect_H +#define ENUMS_PredSelect_H +typedef enum PredSelect { + NOT_PREDICATED = 0, + PREDICATED = 1 +} PredSelect; +#endif /*ENUMS_PredSelect_H*/ + +#ifndef ENUMS_SampleLocation_H +#define ENUMS_SampleLocation_H +typedef enum SampleLocation { + SAMPLE_CENTROID = 0, + SAMPLE_CENTER = 1 +} SampleLocation; +#endif /*ENUMS_SampleLocation_H*/ + +#ifndef ENUMS_VertexMode_H +#define ENUMS_VertexMode_H +typedef enum VertexMode { + POSITION_1_VECTOR = 0, + POSITION_2_VECTORS_UNUSED = 1, + POSITION_2_VECTORS_SPRITE = 2, + POSITION_2_VECTORS_EDGE = 3, + POSITION_2_VECTORS_KILL = 4, + POSITION_2_VECTORS_SPRITE_KILL = 5, + POSITION_2_VECTORS_EDGE_KILL = 6, + MULTIPASS = 7 +} VertexMode; +#endif /*ENUMS_VertexMode_H*/ + +#ifndef ENUMS_Sample_Cntl_H +#define ENUMS_Sample_Cntl_H +typedef enum Sample_Cntl { + CENTROIDS_ONLY = 0, + CENTERS_ONLY = 1, + CENTROIDS_AND_CENTERS = 2, + UNDEF = 3 +} Sample_Cntl; +#endif /*ENUMS_Sample_Cntl_H*/ + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +#ifndef ENUMS_MhPerfEncode_H +#define ENUMS_MhPerfEncode_H +typedef enum MhPerfEncode { + CP_R0_REQUESTS = 0, + CP_R1_REQUESTS = 1, + CP_R2_REQUESTS = 2, + CP_R3_REQUESTS = 3, + CP_R4_REQUESTS = 4, + CP_TOTAL_READ_REQUESTS = 5, + CP_TOTAL_WRITE_REQUESTS = 6, + CP_TOTAL_REQUESTS = 7, + CP_DATA_BYTES_WRITTEN = 8, + CP_WRITE_CLEAN_RESPONSES = 9, + CP_R0_READ_BURSTS_RECEIVED = 10, + CP_R1_READ_BURSTS_RECEIVED = 11, + CP_R2_READ_BURSTS_RECEIVED = 12, + CP_R3_READ_BURSTS_RECEIVED = 13, + CP_R4_READ_BURSTS_RECEIVED = 14, + CP_TOTAL_READ_BURSTS_RECEIVED = 15, + CP_R0_DATA_BEATS_READ = 16, + CP_R1_DATA_BEATS_READ = 17, + CP_R2_DATA_BEATS_READ = 18, + CP_R3_DATA_BEATS_READ = 19, + CP_R4_DATA_BEATS_READ = 20, + CP_TOTAL_DATA_BEATS_READ = 21, + VGT_R0_REQUESTS = 22, + VGT_R1_REQUESTS = 23, + VGT_TOTAL_REQUESTS = 24, + VGT_R0_READ_BURSTS_RECEIVED = 25, + VGT_R1_READ_BURSTS_RECEIVED = 26, + VGT_TOTAL_READ_BURSTS_RECEIVED = 27, + VGT_R0_DATA_BEATS_READ = 28, + VGT_R1_DATA_BEATS_READ = 29, + VGT_TOTAL_DATA_BEATS_READ = 30, + TC_TOTAL_REQUESTS = 31, + TC_ROQ_REQUESTS = 32, + TC_INFO_SENT = 33, + TC_READ_BURSTS_RECEIVED = 34, + TC_DATA_BEATS_READ = 35, + TCD_BURSTS_READ = 36, + RB_REQUESTS = 37, + RB_DATA_BYTES_WRITTEN = 38, + RB_WRITE_CLEAN_RESPONSES = 39, + AXI_READ_REQUESTS_ID_0 = 40, + AXI_READ_REQUESTS_ID_1 = 41, + AXI_READ_REQUESTS_ID_2 = 42, + AXI_READ_REQUESTS_ID_3 = 43, + AXI_READ_REQUESTS_ID_4 = 44, + AXI_READ_REQUESTS_ID_5 = 45, + AXI_READ_REQUESTS_ID_6 = 46, + AXI_READ_REQUESTS_ID_7 = 47, + AXI_TOTAL_READ_REQUESTS = 48, + AXI_WRITE_REQUESTS_ID_0 = 49, + AXI_WRITE_REQUESTS_ID_1 = 50, + AXI_WRITE_REQUESTS_ID_2 = 51, + AXI_WRITE_REQUESTS_ID_3 = 52, + AXI_WRITE_REQUESTS_ID_4 = 53, + AXI_WRITE_REQUESTS_ID_5 = 54, + AXI_WRITE_REQUESTS_ID_6 = 55, + AXI_WRITE_REQUESTS_ID_7 = 56, + AXI_TOTAL_WRITE_REQUESTS = 57, + AXI_TOTAL_REQUESTS_ID_0 = 58, + AXI_TOTAL_REQUESTS_ID_1 = 59, + AXI_TOTAL_REQUESTS_ID_2 = 60, + AXI_TOTAL_REQUESTS_ID_3 = 61, + AXI_TOTAL_REQUESTS_ID_4 = 62, + AXI_TOTAL_REQUESTS_ID_5 = 63, + AXI_TOTAL_REQUESTS_ID_6 = 64, + AXI_TOTAL_REQUESTS_ID_7 = 65, + AXI_TOTAL_REQUESTS = 66, + AXI_READ_CHANNEL_BURSTS_ID_0 = 67, + AXI_READ_CHANNEL_BURSTS_ID_1 = 68, + AXI_READ_CHANNEL_BURSTS_ID_2 = 69, + AXI_READ_CHANNEL_BURSTS_ID_3 = 70, + AXI_READ_CHANNEL_BURSTS_ID_4 = 71, + AXI_READ_CHANNEL_BURSTS_ID_5 = 72, + AXI_READ_CHANNEL_BURSTS_ID_6 = 73, + AXI_READ_CHANNEL_BURSTS_ID_7 = 74, + AXI_READ_CHANNEL_TOTAL_BURSTS = 75, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, + AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, + AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, + AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, + AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, + AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, + AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, + AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, + AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, + AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, + AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, + AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, + AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, + TOTAL_MMU_MISSES = 112, + MMU_READ_MISSES = 113, + MMU_WRITE_MISSES = 114, + TOTAL_MMU_HITS = 115, + MMU_READ_HITS = 116, + MMU_WRITE_HITS = 117, + SPLIT_MODE_TC_HITS = 118, + SPLIT_MODE_TC_MISSES = 119, + SPLIT_MODE_NON_TC_HITS = 120, + SPLIT_MODE_NON_TC_MISSES = 121, + STALL_AWAITING_TLB_MISS_FETCH = 122, + MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, + MMU_TLB_MISS_DATA_BEATS_READ = 124, + CP_CYCLES_HELD_OFF = 125, + VGT_CYCLES_HELD_OFF = 126, + TC_CYCLES_HELD_OFF = 127, + TC_ROQ_CYCLES_HELD_OFF = 128, + TC_CYCLES_HELD_OFF_TCD_FULL = 129, + RB_CYCLES_HELD_OFF = 130, + TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, + TLB_MISS_CYCLES_HELD_OFF = 132, + AXI_READ_REQUEST_HELD_OFF = 133, + AXI_WRITE_REQUEST_HELD_OFF = 134, + AXI_REQUEST_HELD_OFF = 135, + AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, + AXI_WRITE_DATA_HELD_OFF = 137, + CP_SAME_PAGE_BANK_REQUESTS = 138, + VGT_SAME_PAGE_BANK_REQUESTS = 139, + TC_SAME_PAGE_BANK_REQUESTS = 140, + TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, + RB_SAME_PAGE_BANK_REQUESTS = 142, + TOTAL_SAME_PAGE_BANK_REQUESTS = 143, + CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, + VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, + TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, + RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, + TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, + TOTAL_MH_READ_REQUESTS = 149, + TOTAL_MH_WRITE_REQUESTS = 150, + TOTAL_MH_REQUESTS = 151, + MH_BUSY = 152, + CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, + VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, + TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, + RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, + TC_ROQ_N_VALID_ENTRIES = 157, + ARQ_N_ENTRIES = 158, + WDB_N_ENTRIES = 159, + MH_READ_LATENCY_OUTST_REQ_SUM = 160, + MC_READ_LATENCY_OUTST_REQ_SUM = 161, + MC_TOTAL_READ_REQUESTS = 162, + ELAPSED_CYCLES_MH_GATED_CLK = 163, + ELAPSED_CLK_CYCLES = 164, + CP_W_16B_REQUESTS = 165, + CP_W_32B_REQUESTS = 166, + TC_16B_REQUESTS = 167, + TC_32B_REQUESTS = 168, + PA_REQUESTS = 169, + PA_DATA_BYTES_WRITTEN = 170, + PA_WRITE_CLEAN_RESPONSES = 171, + PA_CYCLES_HELD_OFF = 172, + AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173, + AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174, + AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175, + AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176, + AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177, + AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178, + AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179, + AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180, + AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, +} MhPerfEncode; +#endif /*ENUMS_MhPerfEncode_H*/ + +#ifndef ENUMS_MmuClntBeh_H +#define ENUMS_MmuClntBeh_H +typedef enum MmuClntBeh { + BEH_NEVR = 0, + BEH_TRAN_RNG = 1, + BEH_TRAN_FLT = 2, +} MmuClntBeh; +#endif /*ENUMS_MmuClntBeh_H*/ + +/******************************************************* + * RBBM Enums + *******************************************************/ +#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H +#define ENUMS_RBBM_PERFCOUNT1_SEL_H +typedef enum RBBM_PERFCOUNT1_SEL { + RBBM1_COUNT = 0, + RBBM1_NRT_BUSY = 1, + RBBM1_RB_BUSY = 2, + RBBM1_SQ_CNTX0_BUSY = 3, + RBBM1_SQ_CNTX17_BUSY = 4, + RBBM1_VGT_BUSY = 5, + RBBM1_VGT_NODMA_BUSY = 6, + RBBM1_PA_BUSY = 7, + RBBM1_SC_CNTX_BUSY = 8, + RBBM1_TPC_BUSY = 9, + RBBM1_TC_BUSY = 10, + RBBM1_SX_BUSY = 11, + RBBM1_CP_COHER_BUSY = 12, + RBBM1_CP_NRT_BUSY = 13, + RBBM1_GFX_IDLE_STALL = 14, + RBBM1_INTERRUPT = 15, +} RBBM_PERFCOUNT1_SEL; +#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/ + +/******************************************************* + * CP Enums + *******************************************************/ +#ifndef ENUMS_CP_PERFCOUNT_SEL_H +#define ENUMS_CP_PERFCOUNT_SEL_H +typedef enum CP_PERFCOUNT_SEL { + ALWAYS_COUNT = 0, + TRANS_FIFO_FULL = 1, + TRANS_FIFO_AF = 2, + RCIU_PFPTRANS_WAIT = 3, + Reserved_04 = 4, + Reserved_05 = 5, + RCIU_NRTTRANS_WAIT = 6, + Reserved_07 = 7, + CSF_NRT_READ_WAIT = 8, + CSF_I1_FIFO_FULL = 9, + CSF_I2_FIFO_FULL = 10, + CSF_ST_FIFO_FULL = 11, + Reserved_12 = 12, + CSF_RING_ROQ_FULL = 13, + CSF_I1_ROQ_FULL = 14, + CSF_I2_ROQ_FULL = 15, + CSF_ST_ROQ_FULL = 16, + Reserved_17 = 17, + MIU_TAG_MEM_FULL = 18, + MIU_WRITECLEAN = 19, + Reserved_20 = 20, + Reserved_21 = 21, + MIU_NRT_WRITE_STALLED = 22, + MIU_NRT_READ_STALLED = 23, + ME_WRITE_CONFIRM_FIFO_FULL = 24, + ME_VS_DEALLOC_FIFO_FULL = 25, + ME_PS_DEALLOC_FIFO_FULL = 26, + ME_REGS_VS_EVENT_FIFO_FULL = 27, + ME_REGS_PS_EVENT_FIFO_FULL = 28, + ME_REGS_CF_EVENT_FIFO_FULL = 29, + ME_MICRO_RB_STARVED = 30, + ME_MICRO_I1_STARVED = 31, + ME_MICRO_I2_STARVED = 32, + ME_MICRO_ST_STARVED = 33, + Reserved_34 = 34, + Reserved_35 = 35, + Reserved_36 = 36, + Reserved_37 = 37, + Reserved_38 = 38, + Reserved_39 = 39, + RCIU_RBBM_DWORD_SENT = 40, + ME_BUSY_CLOCKS = 41, + ME_WAIT_CONTEXT_AVAIL = 42, + PFP_TYPE0_PACKET = 43, + PFP_TYPE3_PACKET = 44, + CSF_RB_WPTR_NEQ_RPTR = 45, + CSF_I1_SIZE_NEQ_ZERO = 46, + CSF_I2_SIZE_NEQ_ZERO = 47, + CSF_RBI1I2_FETCHING = 48, + Reserved_49 = 49, + Reserved_50 = 50, + Reserved_51 = 51, + Reserved_52 = 52, + Reserved_53 = 53, + Reserved_54 = 54, + Reserved_55 = 55, + Reserved_56 = 56, + Reserved_57 = 57, + Reserved_58 = 58, + Reserved_59 = 59, + Reserved_60 = 60, + Reserved_61 = 61, + Reserved_62 = 62, + Reserved_63 = 63 +} CP_PERFCOUNT_SEL; +#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/ + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +#ifndef ENUMS_ColorformatX_H +#define ENUMS_ColorformatX_H +typedef enum ColorformatX { + COLORX_4_4_4_4 = 0, + COLORX_1_5_5_5 = 1, + COLORX_5_6_5 = 2, + COLORX_8 = 3, + COLORX_8_8 = 4, + COLORX_8_8_8_8 = 5, + COLORX_S8_8_8_8 = 6, + COLORX_16_FLOAT = 7, + COLORX_16_16_FLOAT = 8, + COLORX_16_16_16_16_FLOAT = 9, + COLORX_32_FLOAT = 10, + COLORX_32_32_FLOAT = 11, + COLORX_32_32_32_32_FLOAT = 12, + COLORX_2_3_3 = 13, + COLORX_8_8_8 = 14, +} ColorformatX; +#endif /*ENUMS_ColorformatX_H*/ + +#ifndef ENUMS_DepthformatX_H +#define ENUMS_DepthformatX_H +typedef enum DepthformatX { + DEPTHX_16 = 0, + DEPTHX_24_8 = 1 +} DepthformatX; +#endif /*ENUMS_DepthformatX_H*/ + +#ifndef ENUMS_CompareFrag_H +#define ENUMS_CompareFrag_H +typedef enum CompareFrag { + FRAG_NEVER = 0, + FRAG_LESS = 1, + FRAG_EQUAL = 2, + FRAG_LEQUAL = 3, + FRAG_GREATER = 4, + FRAG_NOTEQUAL = 5, + FRAG_GEQUAL = 6, + FRAG_ALWAYS = 7 +} CompareFrag; +#endif /*ENUMS_CompareFrag_H*/ + +#ifndef ENUMS_CompareRef_H +#define ENUMS_CompareRef_H +typedef enum CompareRef { + REF_NEVER = 0, + REF_LESS = 1, + REF_EQUAL = 2, + REF_LEQUAL = 3, + REF_GREATER = 4, + REF_NOTEQUAL = 5, + REF_GEQUAL = 6, + REF_ALWAYS = 7 +} CompareRef; +#endif /*ENUMS_CompareRef_H*/ + +#ifndef ENUMS_StencilOp_H +#define ENUMS_StencilOp_H +typedef enum StencilOp { + STENCIL_KEEP = 0, + STENCIL_ZERO = 1, + STENCIL_REPLACE = 2, + STENCIL_INCR_CLAMP = 3, + STENCIL_DECR_CLAMP = 4, + STENCIL_INVERT = 5, + STENCIL_INCR_WRAP = 6, + STENCIL_DECR_WRAP = 7 +} StencilOp; +#endif /*ENUMS_StencilOp_H*/ + +#ifndef ENUMS_BlendOpX_H +#define ENUMS_BlendOpX_H +typedef enum BlendOpX { + BLENDX_ZERO = 0, + BLENDX_ONE = 1, + BLENDX_SRC_COLOR = 4, + BLENDX_ONE_MINUS_SRC_COLOR = 5, + BLENDX_SRC_ALPHA = 6, + BLENDX_ONE_MINUS_SRC_ALPHA = 7, + BLENDX_DST_COLOR = 8, + BLENDX_ONE_MINUS_DST_COLOR = 9, + BLENDX_DST_ALPHA = 10, + BLENDX_ONE_MINUS_DST_ALPHA = 11, + BLENDX_CONSTANT_COLOR = 12, + BLENDX_ONE_MINUS_CONSTANT_COLOR = 13, + BLENDX_CONSTANT_ALPHA = 14, + BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15, + BLENDX_SRC_ALPHA_SATURATE = 16, +} BlendOpX; +#endif /*ENUMS_BlendOpX_H*/ + +#ifndef ENUMS_CombFuncX_H +#define ENUMS_CombFuncX_H +typedef enum CombFuncX { + COMB_DST_PLUS_SRC = 0, + COMB_SRC_MINUS_DST = 1, + COMB_MIN_DST_SRC = 2, + COMB_MAX_DST_SRC = 3, + COMB_DST_MINUS_SRC = 4, + COMB_DST_PLUS_SRC_BIAS = 5, +} CombFuncX; +#endif /*ENUMS_CombFuncX_H*/ + +#ifndef ENUMS_DitherModeX_H +#define ENUMS_DitherModeX_H +typedef enum DitherModeX { + DITHER_DISABLE = 0, + DITHER_ALWAYS = 1, + DITHER_IF_ALPHA_OFF = 2, +} DitherModeX; +#endif /*ENUMS_DitherModeX_H*/ + +#ifndef ENUMS_DitherTypeX_H +#define ENUMS_DitherTypeX_H +typedef enum DitherTypeX { + DITHER_PIXEL = 0, + DITHER_SUBPIXEL = 1, +} DitherTypeX; +#endif /*ENUMS_DitherTypeX_H*/ + +#ifndef ENUMS_EdramMode_H +#define ENUMS_EdramMode_H +typedef enum EdramMode { + EDRAM_NOP = 0, + COLOR_DEPTH = 4, + DEPTH_ONLY = 5, + EDRAM_COPY = 6, +} EdramMode; +#endif /*ENUMS_EdramMode_H*/ + +#ifndef ENUMS_SurfaceEndian_H +#define ENUMS_SurfaceEndian_H +typedef enum SurfaceEndian { + ENDIAN_NONE = 0, + ENDIAN_8IN16 = 1, + ENDIAN_8IN32 = 2, + ENDIAN_16IN32 = 3, + ENDIAN_8IN64 = 4, + ENDIAN_8IN128 = 5, +} SurfaceEndian; +#endif /*ENUMS_SurfaceEndian_H*/ + +#ifndef ENUMS_EdramSizeX_H +#define ENUMS_EdramSizeX_H +typedef enum EdramSizeX { + EDRAMSIZE_16KB = 0, + EDRAMSIZE_32KB = 1, + EDRAMSIZE_64KB = 2, + EDRAMSIZE_128KB = 3, + EDRAMSIZE_256KB = 4, + EDRAMSIZE_512KB = 5, + EDRAMSIZE_1MB = 6, + EDRAMSIZE_2MB = 7, + EDRAMSIZE_4MB = 8, + EDRAMSIZE_8MB = 9, + EDRAMSIZE_16MB = 10, +} EdramSizeX; +#endif /*ENUMS_EdramSizeX_H*/ + +#ifndef ENUMS_RB_PERFCNT_SELECT_H +#define ENUMS_RB_PERFCNT_SELECT_H +typedef enum RB_PERFCNT_SELECT { + RBPERF_CNTX_BUSY = 0, + RBPERF_CNTX_BUSY_MAX = 1, + RBPERF_SX_QUAD_STARVED = 2, + RBPERF_SX_QUAD_STARVED_MAX = 3, + RBPERF_GA_GC_CH0_SYS_REQ = 4, + RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, + RBPERF_GA_GC_CH1_SYS_REQ = 6, + RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, + RBPERF_MH_STARVED = 8, + RBPERF_MH_STARVED_MAX = 9, + RBPERF_AZ_BC_COLOR_BUSY = 10, + RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, + RBPERF_AZ_BC_Z_BUSY = 12, + RBPERF_AZ_BC_Z_BUSY_MAX = 13, + RBPERF_RB_SC_TILE_RTR_N = 14, + RBPERF_RB_SC_TILE_RTR_N_MAX = 15, + RBPERF_RB_SC_SAMP_RTR_N = 16, + RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, + RBPERF_RB_SX_QUAD_RTR_N = 18, + RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, + RBPERF_RB_SX_COLOR_RTR_N = 20, + RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, + RBPERF_RB_SC_SAMP_LZ_BUSY = 22, + RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, + RBPERF_ZXP_STALL = 24, + RBPERF_ZXP_STALL_MAX = 25, + RBPERF_EVENT_PENDING = 26, + RBPERF_EVENT_PENDING_MAX = 27, + RBPERF_RB_MH_VALID = 28, + RBPERF_RB_MH_VALID_MAX = 29, + RBPERF_SX_RB_QUAD_SEND = 30, + RBPERF_SX_RB_COLOR_SEND = 31, + RBPERF_SC_RB_TILE_SEND = 32, + RBPERF_SC_RB_SAMPLE_SEND = 33, + RBPERF_SX_RB_MEM_EXPORT = 34, + RBPERF_SX_RB_QUAD_EVENT = 35, + RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, + RBPERF_SC_RB_TILE_EVENT_ALL = 37, + RBPERF_RB_SC_EZ_SEND = 38, + RBPERF_RB_SX_INDEX_SEND = 39, + RBPERF_GMEM_INTFO_RD = 40, + RBPERF_GMEM_INTF1_RD = 41, + RBPERF_GMEM_INTFO_WR = 42, + RBPERF_GMEM_INTF1_WR = 43, + RBPERF_RB_CP_CONTEXT_DONE = 44, + RBPERF_RB_CP_CACHE_FLUSH = 45, + RBPERF_ZPASS_DONE = 46, + RBPERF_ZCMD_VALID = 47, + RBPERF_CCMD_VALID = 48, + RBPERF_ACCUM_GRANT = 49, + RBPERF_ACCUM_C0_GRANT = 50, + RBPERF_ACCUM_C1_GRANT = 51, + RBPERF_ACCUM_FULL_BE_WR = 52, + RBPERF_ACCUM_REQUEST_NO_GRANT = 53, + RBPERF_ACCUM_TIMEOUT_PULSE = 54, + RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, + RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, +} RB_PERFCNT_SELECT; +#endif /*ENUMS_RB_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_DepthFormat_H +#define ENUMS_DepthFormat_H +typedef enum DepthFormat { + DEPTH_24_8 = 22, + DEPTH_24_8_FLOAT = 23, + DEPTH_16 = 24, +} DepthFormat; +#endif /*ENUMS_DepthFormat_H*/ + +#ifndef ENUMS_SurfaceSwap_H +#define ENUMS_SurfaceSwap_H +typedef enum SurfaceSwap { + SWAP_LOWRED = 0, + SWAP_LOWBLUE = 1 +} SurfaceSwap; +#endif /*ENUMS_SurfaceSwap_H*/ + +#ifndef ENUMS_DepthArray_H +#define ENUMS_DepthArray_H +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0, + ARRAY_2D_DEPTH = 1, +} DepthArray; +#endif /*ENUMS_DepthArray_H*/ + +#ifndef ENUMS_ColorArray_H +#define ENUMS_ColorArray_H +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0, + ARRAY_2D_COLOR = 1, + ARRAY_3D_SLICE_COLOR = 3 +} ColorArray; +#endif /*ENUMS_ColorArray_H*/ + +#ifndef ENUMS_ColorFormat_H +#define ENUMS_ColorFormat_H +typedef enum ColorFormat { + COLOR_8 = 2, + COLOR_1_5_5_5 = 3, + COLOR_5_6_5 = 4, + COLOR_6_5_5 = 5, + COLOR_8_8_8_8 = 6, + COLOR_2_10_10_10 = 7, + COLOR_8_A = 8, + COLOR_8_B = 9, + COLOR_8_8 = 10, + COLOR_8_8_8 = 11, + COLOR_8_8_8_8_A = 14, + COLOR_4_4_4_4 = 15, + COLOR_10_11_11 = 16, + COLOR_11_11_10 = 17, + COLOR_16 = 24, + COLOR_16_16 = 25, + COLOR_16_16_16_16 = 26, + COLOR_16_FLOAT = 30, + COLOR_16_16_FLOAT = 31, + COLOR_16_16_16_16_FLOAT = 32, + COLOR_32_FLOAT = 36, + COLOR_32_32_FLOAT = 37, + COLOR_32_32_32_32_FLOAT = 38, + COLOR_2_3_3 = 39, +} ColorFormat; +#endif /*ENUMS_ColorFormat_H*/ + +#ifndef ENUMS_SurfaceNumber_H +#define ENUMS_SurfaceNumber_H +typedef enum SurfaceNumber { + NUMBER_UREPEAT = 0, + NUMBER_SREPEAT = 1, + NUMBER_UINTEGER = 2, + NUMBER_SINTEGER = 3, + NUMBER_GAMMA = 4, + NUMBER_FIXED = 5, + NUMBER_FLOAT = 7 +} SurfaceNumber; +#endif /*ENUMS_SurfaceNumber_H*/ + +#ifndef ENUMS_SurfaceFormat_H +#define ENUMS_SurfaceFormat_H +typedef enum SurfaceFormat { + FMT_1_REVERSE = 0, + FMT_1 = 1, + FMT_8 = 2, + FMT_1_5_5_5 = 3, + FMT_5_6_5 = 4, + FMT_6_5_5 = 5, + FMT_8_8_8_8 = 6, + FMT_2_10_10_10 = 7, + FMT_8_A = 8, + FMT_8_B = 9, + FMT_8_8 = 10, + FMT_Cr_Y1_Cb_Y0 = 11, + FMT_Y1_Cr_Y0_Cb = 12, + FMT_5_5_5_1 = 13, + FMT_8_8_8_8_A = 14, + FMT_4_4_4_4 = 15, + FMT_8_8_8 = 16, + FMT_DXT1 = 18, + FMT_DXT2_3 = 19, + FMT_DXT4_5 = 20, + FMT_10_10_10_2 = 21, + FMT_24_8 = 22, + FMT_16 = 24, + FMT_16_16 = 25, + FMT_16_16_16_16 = 26, + FMT_16_EXPAND = 27, + FMT_16_16_EXPAND = 28, + FMT_16_16_16_16_EXPAND = 29, + FMT_16_FLOAT = 30, + FMT_16_16_FLOAT = 31, + FMT_16_16_16_16_FLOAT = 32, + FMT_32 = 33, + FMT_32_32 = 34, + FMT_32_32_32_32 = 35, + FMT_32_FLOAT = 36, + FMT_32_32_FLOAT = 37, + FMT_32_32_32_32_FLOAT = 38, + FMT_ATI_TC_RGB = 39, + FMT_ATI_TC_RGBA = 40, + FMT_ATI_TC_555_565_RGB = 41, + FMT_ATI_TC_555_565_RGBA = 42, + FMT_ATI_TC_RGBA_INTERP = 43, + FMT_ATI_TC_555_565_RGBA_INTERP = 44, + FMT_ETC1_RGBA_INTERP = 46, + FMT_ETC1_RGB = 47, + FMT_ETC1_RGBA = 48, + FMT_DXN = 49, + FMT_2_3_3 = 51, + FMT_2_10_10_10_AS_16_16_16_16 = 54, + FMT_10_10_10_2_AS_16_16_16_16 = 55, + FMT_32_32_32_FLOAT = 57, + FMT_DXT3A = 58, + FMT_DXT5A = 59, + FMT_CTX1 = 60, +} SurfaceFormat; +#endif /*ENUMS_SurfaceFormat_H*/ + +#ifndef ENUMS_SurfaceTiling_H +#define ENUMS_SurfaceTiling_H +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0, + ARRAY_TILED = 1 +} SurfaceTiling; +#endif /*ENUMS_SurfaceTiling_H*/ + +#ifndef ENUMS_SurfaceArray_H +#define ENUMS_SurfaceArray_H +typedef enum SurfaceArray { + ARRAY_1D = 0, + ARRAY_2D = 1, + ARRAY_3D = 2, + ARRAY_3D_SLICE = 3 +} SurfaceArray; +#endif /*ENUMS_SurfaceArray_H*/ + +#ifndef ENUMS_SurfaceNumberX_H +#define ENUMS_SurfaceNumberX_H +typedef enum SurfaceNumberX { + NUMBERX_UREPEAT = 0, + NUMBERX_SREPEAT = 1, + NUMBERX_UINTEGER = 2, + NUMBERX_SINTEGER = 3, + NUMBERX_FLOAT = 7 +} SurfaceNumberX; +#endif /*ENUMS_SurfaceNumberX_H*/ + +#ifndef ENUMS_ColorArrayX_H +#define ENUMS_ColorArrayX_H +typedef enum ColorArrayX { + ARRAYX_2D_COLOR = 0, + ARRAYX_3D_SLICE_COLOR = 1, +} ColorArrayX; +#endif /*ENUMS_ColorArrayX_H*/ + +#endif /*_yamato_ENUM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h new file mode 100644 index 000000000000..87a454a1e38a --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h @@ -0,0 +1,1703 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_ENUMTYPE(SU_PERFCNT_SELECT) + GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0) + GENERATE_ENUM(UNUSED1, 1) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13) + GENERATE_ENUM(UNUSED2, 14) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15) + GENERATE_ENUM(UNUSED3, 16) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19) + GENERATE_ENUM(UNUSED4, 20) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21) + GENERATE_ENUM(UNUSED5, 22) + GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35) + GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36) + GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37) + GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38) + GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45) + GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49) + GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50) + GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51) + GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71) + GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72) + GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77) + GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78) + GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79) + GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80) + GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81) + GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84) + GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85) + GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91) + GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92) + GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95) + GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96) + GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97) + GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98) + GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99) + GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100) + GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101) + GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102) +END_ENUMTYPE(SU_PERFCNT_SELECT) + +START_ENUMTYPE(SC_PERFCNT_SELECT) + GENERATE_ENUM(SC_SR_WINDOW_VALID, 0) + GENERATE_ENUM(SC_CW_WINDOW_VALID, 1) + GENERATE_ENUM(SC_QM_WINDOW_VALID, 2) + GENERATE_ENUM(SC_FW_WINDOW_VALID, 3) + GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4) + GENERATE_ENUM(SC_IT_WINDOW_VALID, 5) + GENERATE_ENUM(SC_STARVED_BY_PA, 6) + GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7) + GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8) + GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9) + GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10) + GENERATE_ENUM(SC_STALLED_BY_SQ, 11) + GENERATE_ENUM(SC_STALLED_BY_SP, 12) + GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13) + GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14) + GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15) + GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16) + GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17) +END_ENUMTYPE(SC_PERFCNT_SELECT) + +START_ENUMTYPE(VGT_DI_PRIM_TYPE) + GENERATE_ENUM(DI_PT_NONE, 0) + GENERATE_ENUM(DI_PT_POINTLIST, 1) + GENERATE_ENUM(DI_PT_LINELIST, 2) + GENERATE_ENUM(DI_PT_LINESTRIP, 3) + GENERATE_ENUM(DI_PT_TRILIST, 4) + GENERATE_ENUM(DI_PT_TRIFAN, 5) + GENERATE_ENUM(DI_PT_TRISTRIP, 6) + GENERATE_ENUM(DI_PT_UNUSED_1, 7) + GENERATE_ENUM(DI_PT_RECTLIST, 8) + GENERATE_ENUM(DI_PT_UNUSED_2, 9) + GENERATE_ENUM(DI_PT_UNUSED_3, 10) + GENERATE_ENUM(DI_PT_UNUSED_4, 11) + GENERATE_ENUM(DI_PT_UNUSED_5, 12) + GENERATE_ENUM(DI_PT_QUADLIST, 13) + GENERATE_ENUM(DI_PT_QUADSTRIP, 14) + GENERATE_ENUM(DI_PT_POLYGON, 15) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19) + GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20) + GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21) + GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22) +END_ENUMTYPE(VGT_DI_PRIM_TYPE) + +START_ENUMTYPE(VGT_DI_SOURCE_SELECT) + GENERATE_ENUM(DI_SRC_SEL_DMA, 0) + GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1) + GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2) + GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3) +END_ENUMTYPE(VGT_DI_SOURCE_SELECT) + +START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + GENERATE_ENUM(DI_FACE_CULL_NONE, 0) + GENERATE_ENUM(DI_FACE_CULL_FETCH, 1) + GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2) + GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3) +END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + +START_ENUMTYPE(VGT_DI_INDEX_SIZE) + GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0) + GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1) +END_ENUMTYPE(VGT_DI_INDEX_SIZE) + +START_ENUMTYPE(VGT_DI_SMALL_INDEX) + GENERATE_ENUM(DI_USE_INDEX_SIZE, 0) + GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1) +END_ENUMTYPE(VGT_DI_SMALL_INDEX) + +START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0) + GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + +START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0) + GENERATE_ENUM(GRP_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + +START_ENUMTYPE(VGT_EVENT_TYPE) + GENERATE_ENUM(VS_DEALLOC, 0) + GENERATE_ENUM(PS_DEALLOC, 1) + GENERATE_ENUM(VS_DONE_TS, 2) + GENERATE_ENUM(PS_DONE_TS, 3) + GENERATE_ENUM(CACHE_FLUSH_TS, 4) + GENERATE_ENUM(CONTEXT_DONE, 5) + GENERATE_ENUM(CACHE_FLUSH, 6) + GENERATE_ENUM(VIZQUERY_START, 7) + GENERATE_ENUM(VIZQUERY_END, 8) + GENERATE_ENUM(SC_WAIT_WC, 9) + GENERATE_ENUM(RST_PIX_CNT, 13) + GENERATE_ENUM(RST_VTX_CNT, 14) + GENERATE_ENUM(TILE_FLUSH, 15) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20) + GENERATE_ENUM(ZPASS_DONE, 21) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22) + GENERATE_ENUM(PERFCOUNTER_START, 23) + GENERATE_ENUM(PERFCOUNTER_STOP, 24) + GENERATE_ENUM(VS_FETCH_DONE, 27) + GENERATE_ENUM(FACENESS_FLUSH, 28) +END_ENUMTYPE(VGT_EVENT_TYPE) + +START_ENUMTYPE(VGT_DMA_SWAP_MODE) + GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0) + GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1) + GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2) + GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3) +END_ENUMTYPE(VGT_DMA_SWAP_MODE) + +START_ENUMTYPE(VGT_PERFCOUNT_SELECT) + GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0) + GENERATE_ENUM(VGT_SQ_SEND, 1) + GENERATE_ENUM(VGT_SQ_STALLED, 2) + GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3) + GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4) + GENERATE_ENUM(VGT_SQ_STATIC, 5) + GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6) + GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7) + GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10) + GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11) + GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12) + GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15) + GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16) + GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17) + GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20) + GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21) + GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28) + GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29) + GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30) + GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31) + GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32) + GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33) + GENERATE_ENUM(SPARE34, 34) + GENERATE_ENUM(SPARE35, 35) + GENERATE_ENUM(SPARE36, 36) + GENERATE_ENUM(SPARE37, 37) + GENERATE_ENUM(SPARE38, 38) + GENERATE_ENUM(SPARE39, 39) + GENERATE_ENUM(TE_SU_IN_VALID, 40) + GENERATE_ENUM(TE_SU_IN_READ, 41) + GENERATE_ENUM(TE_SU_IN_PRIM, 42) + GENERATE_ENUM(TE_SU_IN_EOP, 43) + GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44) + GENERATE_ENUM(TE_WK_IN_VALID, 45) + GENERATE_ENUM(TE_WK_IN_READ, 46) + GENERATE_ENUM(TE_OUT_PRIM_VALID, 47) + GENERATE_ENUM(TE_OUT_PRIM_READ, 48) +END_ENUMTYPE(VGT_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCR_PERFCOUNT_SELECT) + GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0) + GENERATE_ENUM(reserved_46, 1) + GENERATE_ENUM(reserved_47, 2) + GENERATE_ENUM(reserved_48, 3) + GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4) + GENERATE_ENUM(OPMUX0_L2_WRITES, 5) + GENERATE_ENUM(reserved_49, 6) + GENERATE_ENUM(reserved_50, 7) + GENERATE_ENUM(reserved_51, 8) +END_ENUMTYPE(TCR_PERFCOUNT_SELECT) + +START_ENUMTYPE(TP_PERFCOUNT_SELECT) + GENERATE_ENUM(POINT_QUADS, 0) + GENERATE_ENUM(BILIN_QUADS, 1) + GENERATE_ENUM(ANISO_QUADS, 2) + GENERATE_ENUM(MIP_QUADS, 3) + GENERATE_ENUM(VOL_QUADS, 4) + GENERATE_ENUM(MIP_VOL_QUADS, 5) + GENERATE_ENUM(MIP_ANISO_QUADS, 6) + GENERATE_ENUM(VOL_ANISO_QUADS, 7) + GENERATE_ENUM(ANISO_2_1_QUADS, 8) + GENERATE_ENUM(ANISO_4_1_QUADS, 9) + GENERATE_ENUM(ANISO_6_1_QUADS, 10) + GENERATE_ENUM(ANISO_8_1_QUADS, 11) + GENERATE_ENUM(ANISO_10_1_QUADS, 12) + GENERATE_ENUM(ANISO_12_1_QUADS, 13) + GENERATE_ENUM(ANISO_14_1_QUADS, 14) + GENERATE_ENUM(ANISO_16_1_QUADS, 15) + GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16) + GENERATE_ENUM(ALIGN_2_QUADS, 17) + GENERATE_ENUM(ALIGN_4_QUADS, 18) + GENERATE_ENUM(PIX_0_QUAD, 19) + GENERATE_ENUM(PIX_1_QUAD, 20) + GENERATE_ENUM(PIX_2_QUAD, 21) + GENERATE_ENUM(PIX_3_QUAD, 22) + GENERATE_ENUM(PIX_4_QUAD, 23) + GENERATE_ENUM(TP_MIPMAP_LOD0, 24) + GENERATE_ENUM(TP_MIPMAP_LOD1, 25) + GENERATE_ENUM(TP_MIPMAP_LOD2, 26) + GENERATE_ENUM(TP_MIPMAP_LOD3, 27) + GENERATE_ENUM(TP_MIPMAP_LOD4, 28) + GENERATE_ENUM(TP_MIPMAP_LOD5, 29) + GENERATE_ENUM(TP_MIPMAP_LOD6, 30) + GENERATE_ENUM(TP_MIPMAP_LOD7, 31) + GENERATE_ENUM(TP_MIPMAP_LOD8, 32) + GENERATE_ENUM(TP_MIPMAP_LOD9, 33) + GENERATE_ENUM(TP_MIPMAP_LOD10, 34) + GENERATE_ENUM(TP_MIPMAP_LOD11, 35) + GENERATE_ENUM(TP_MIPMAP_LOD12, 36) + GENERATE_ENUM(TP_MIPMAP_LOD13, 37) + GENERATE_ENUM(TP_MIPMAP_LOD14, 38) +END_ENUMTYPE(TP_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCM_PERFCOUNT_SELECT) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0) + GENERATE_ENUM(reserved_01, 1) + GENERATE_ENUM(reserved_02, 2) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6) + GENERATE_ENUM(reserved_07, 7) + GENERATE_ENUM(reserved_08, 8) + GENERATE_ENUM(reserved_09, 9) + GENERATE_ENUM(reserved_10, 10) + GENERATE_ENUM(reserved_11, 11) + GENERATE_ENUM(reserved_12, 12) + GENERATE_ENUM(reserved_13, 13) + GENERATE_ENUM(reserved_14, 14) + GENERATE_ENUM(reserved_15, 15) + GENERATE_ENUM(reserved_16, 16) + GENERATE_ENUM(reserved_17, 17) + GENERATE_ENUM(reserved_18, 18) + GENERATE_ENUM(reserved_19, 19) + GENERATE_ENUM(reserved_20, 20) + GENERATE_ENUM(reserved_21, 21) + GENERATE_ENUM(reserved_22, 22) + GENERATE_ENUM(reserved_23, 23) + GENERATE_ENUM(reserved_24, 24) + GENERATE_ENUM(reserved_25, 25) + GENERATE_ENUM(reserved_26, 26) + GENERATE_ENUM(reserved_27, 27) + GENERATE_ENUM(READ_STARVED_QUAD0, 28) + GENERATE_ENUM(reserved_29, 29) + GENERATE_ENUM(reserved_30, 30) + GENERATE_ENUM(reserved_31, 31) + GENERATE_ENUM(READ_STARVED, 32) + GENERATE_ENUM(READ_STALLED_QUAD0, 33) + GENERATE_ENUM(reserved_34, 34) + GENERATE_ENUM(reserved_35, 35) + GENERATE_ENUM(reserved_36, 36) + GENERATE_ENUM(READ_STALLED, 37) + GENERATE_ENUM(VALID_READ_QUAD0, 38) + GENERATE_ENUM(reserved_39, 39) + GENERATE_ENUM(reserved_40, 40) + GENERATE_ENUM(reserved_41, 41) + GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42) + GENERATE_ENUM(reserved_43, 43) + GENERATE_ENUM(reserved_44, 44) + GENERATE_ENUM(reserved_45, 45) + GENERATE_ENUM(TC_TP_STARVED, 46) +END_ENUMTYPE(TCM_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCF_PERFCOUNT_SELECT) + GENERATE_ENUM(VALID_CYCLES, 0) + GENERATE_ENUM(SINGLE_PHASES, 1) + GENERATE_ENUM(ANISO_PHASES, 2) + GENERATE_ENUM(MIP_PHASES, 3) + GENERATE_ENUM(VOL_PHASES, 4) + GENERATE_ENUM(MIP_VOL_PHASES, 5) + GENERATE_ENUM(MIP_ANISO_PHASES, 6) + GENERATE_ENUM(VOL_ANISO_PHASES, 7) + GENERATE_ENUM(ANISO_2_1_PHASES, 8) + GENERATE_ENUM(ANISO_4_1_PHASES, 9) + GENERATE_ENUM(ANISO_6_1_PHASES, 10) + GENERATE_ENUM(ANISO_8_1_PHASES, 11) + GENERATE_ENUM(ANISO_10_1_PHASES, 12) + GENERATE_ENUM(ANISO_12_1_PHASES, 13) + GENERATE_ENUM(ANISO_14_1_PHASES, 14) + GENERATE_ENUM(ANISO_16_1_PHASES, 15) + GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16) + GENERATE_ENUM(ALIGN_2_PHASES, 17) + GENERATE_ENUM(ALIGN_4_PHASES, 18) + GENERATE_ENUM(TPC_BUSY, 19) + GENERATE_ENUM(TPC_STALLED, 20) + GENERATE_ENUM(TPC_STARVED, 21) + GENERATE_ENUM(TPC_WORKING, 22) + GENERATE_ENUM(TPC_WALKER_BUSY, 23) + GENERATE_ENUM(TPC_WALKER_STALLED, 24) + GENERATE_ENUM(TPC_WALKER_WORKING, 25) + GENERATE_ENUM(TPC_ALIGNER_BUSY, 26) + GENERATE_ENUM(TPC_ALIGNER_STALLED, 27) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29) + GENERATE_ENUM(TPC_ALIGNER_WORKING, 30) + GENERATE_ENUM(TPC_BLEND_BUSY, 31) + GENERATE_ENUM(TPC_BLEND_SYNC, 32) + GENERATE_ENUM(TPC_BLEND_STARVED, 33) + GENERATE_ENUM(TPC_BLEND_WORKING, 34) + GENERATE_ENUM(OPCODE_0x00, 35) + GENERATE_ENUM(OPCODE_0x01, 36) + GENERATE_ENUM(OPCODE_0x04, 37) + GENERATE_ENUM(OPCODE_0x10, 38) + GENERATE_ENUM(OPCODE_0x11, 39) + GENERATE_ENUM(OPCODE_0x12, 40) + GENERATE_ENUM(OPCODE_0x13, 41) + GENERATE_ENUM(OPCODE_0x18, 42) + GENERATE_ENUM(OPCODE_0x19, 43) + GENERATE_ENUM(OPCODE_0x1A, 44) + GENERATE_ENUM(OPCODE_OTHER, 45) + GENERATE_ENUM(IN_FIFO_0_EMPTY, 56) + GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57) + GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58) + GENERATE_ENUM(IN_FIFO_0_FULL, 59) + GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72) + GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73) + GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74) + GENERATE_ENUM(IN_FIFO_TPC_FULL, 75) + GENERATE_ENUM(TPC_TC_XFC, 76) + GENERATE_ENUM(TPC_TC_STATE, 77) + GENERATE_ENUM(TC_STALL, 78) + GENERATE_ENUM(QUAD0_TAPS, 79) + GENERATE_ENUM(QUADS, 83) + GENERATE_ENUM(TCA_SYNC_STALL, 84) + GENERATE_ENUM(TAG_STALL, 85) + GENERATE_ENUM(TCB_SYNC_STALL, 88) + GENERATE_ENUM(TCA_VALID, 89) + GENERATE_ENUM(PROBES_VALID, 90) + GENERATE_ENUM(MISS_STALL, 91) + GENERATE_ENUM(FETCH_FIFO_STALL, 92) + GENERATE_ENUM(TCO_STALL, 93) + GENERATE_ENUM(ANY_STALL, 94) + GENERATE_ENUM(TAG_MISSES, 95) + GENERATE_ENUM(TAG_HITS, 96) + GENERATE_ENUM(SUB_TAG_MISSES, 97) + GENERATE_ENUM(SET0_INVALIDATES, 98) + GENERATE_ENUM(SET1_INVALIDATES, 99) + GENERATE_ENUM(SET2_INVALIDATES, 100) + GENERATE_ENUM(SET3_INVALIDATES, 101) + GENERATE_ENUM(SET0_TAG_MISSES, 102) + GENERATE_ENUM(SET1_TAG_MISSES, 103) + GENERATE_ENUM(SET2_TAG_MISSES, 104) + GENERATE_ENUM(SET3_TAG_MISSES, 105) + GENERATE_ENUM(SET0_TAG_HITS, 106) + GENERATE_ENUM(SET1_TAG_HITS, 107) + GENERATE_ENUM(SET2_TAG_HITS, 108) + GENERATE_ENUM(SET3_TAG_HITS, 109) + GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110) + GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111) + GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112) + GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113) + GENERATE_ENUM(SET0_EVICT1, 114) + GENERATE_ENUM(SET0_EVICT2, 115) + GENERATE_ENUM(SET0_EVICT3, 116) + GENERATE_ENUM(SET0_EVICT4, 117) + GENERATE_ENUM(SET0_EVICT5, 118) + GENERATE_ENUM(SET0_EVICT6, 119) + GENERATE_ENUM(SET0_EVICT7, 120) + GENERATE_ENUM(SET0_EVICT8, 121) + GENERATE_ENUM(SET1_EVICT1, 130) + GENERATE_ENUM(SET1_EVICT2, 131) + GENERATE_ENUM(SET1_EVICT3, 132) + GENERATE_ENUM(SET1_EVICT4, 133) + GENERATE_ENUM(SET1_EVICT5, 134) + GENERATE_ENUM(SET1_EVICT6, 135) + GENERATE_ENUM(SET1_EVICT7, 136) + GENERATE_ENUM(SET1_EVICT8, 137) + GENERATE_ENUM(SET2_EVICT1, 146) + GENERATE_ENUM(SET2_EVICT2, 147) + GENERATE_ENUM(SET2_EVICT3, 148) + GENERATE_ENUM(SET2_EVICT4, 149) + GENERATE_ENUM(SET2_EVICT5, 150) + GENERATE_ENUM(SET2_EVICT6, 151) + GENERATE_ENUM(SET2_EVICT7, 152) + GENERATE_ENUM(SET2_EVICT8, 153) + GENERATE_ENUM(SET3_EVICT1, 162) + GENERATE_ENUM(SET3_EVICT2, 163) + GENERATE_ENUM(SET3_EVICT3, 164) + GENERATE_ENUM(SET3_EVICT4, 165) + GENERATE_ENUM(SET3_EVICT5, 166) + GENERATE_ENUM(SET3_EVICT6, 167) + GENERATE_ENUM(SET3_EVICT7, 168) + GENERATE_ENUM(SET3_EVICT8, 169) + GENERATE_ENUM(FF_EMPTY, 178) + GENERATE_ENUM(FF_LT_HALF_FULL, 179) + GENERATE_ENUM(FF_HALF_FULL, 180) + GENERATE_ENUM(FF_FULL, 181) + GENERATE_ENUM(FF_XFC, 182) + GENERATE_ENUM(FF_STALLED, 183) + GENERATE_ENUM(FG_MASKS, 184) + GENERATE_ENUM(FG_LEFT_MASKS, 185) + GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186) + GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187) + GENERATE_ENUM(FG_LEFT_FG_STALL, 188) + GENERATE_ENUM(FG_LEFT_SECTORS, 189) + GENERATE_ENUM(FG0_REQUESTS, 195) + GENERATE_ENUM(FG0_STALLED, 196) + GENERATE_ENUM(MEM_REQ512, 199) + GENERATE_ENUM(MEM_REQ_SENT, 200) + GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202) + GENERATE_ENUM(TC0_MH_STALLED, 203) +END_ENUMTYPE(TCF_PERFCOUNT_SELECT) + +START_ENUMTYPE(SQ_PERFCNT_SELECT) + GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0) + GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9) + GENERATE_ENUM(SQ_EXPORT_CYCLES, 10) + GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11) + GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12) + GENERATE_ENUM(SQ_ALU_CST_STALL, 13) + GENERATE_ENUM(SQ_ALU_TEX_STALL, 14) + GENERATE_ENUM(SQ_INST_WRITTEN, 15) + GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16) + GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17) + GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18) + GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19) + GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20) + GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21) + GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22) + GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23) + GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24) + GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25) + GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26) + GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27) + GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28) + GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33) + GENERATE_ENUM(SQ_ALU_NOPS, 34) + GENERATE_ENUM(SQ_PRED_SKIP, 35) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38) + GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41) + GENERATE_ENUM(SQ_GPR_STALL_VTX, 42) + GENERATE_ENUM(SQ_GPR_STALL_PIX, 43) + GENERATE_ENUM(SQ_VTX_RS_STALL, 44) + GENERATE_ENUM(SQ_PIX_RS_STALL, 45) + GENERATE_ENUM(SQ_SX_PC_FULL, 46) + GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47) + GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48) + GENERATE_ENUM(SQ_INTERP_QUADS, 49) + GENERATE_ENUM(SQ_INTERP_ACTIVE, 50) + GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51) + GENERATE_ENUM(SQ_IN_VTX_STALL, 52) + GENERATE_ENUM(SQ_VTX_CNT, 53) + GENERATE_ENUM(SQ_VTX_VECTOR2, 54) + GENERATE_ENUM(SQ_VTX_VECTOR3, 55) + GENERATE_ENUM(SQ_VTX_VECTOR4, 56) + GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57) + GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58) + GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61) + GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81) + GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94) + GENERATE_ENUM(VC_PERF_STATIC, 95) + GENERATE_ENUM(VC_PERF_STALLED, 96) + GENERATE_ENUM(VC_PERF_STARVED, 97) + GENERATE_ENUM(VC_PERF_SEND, 98) + GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99) + GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100) + GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101) + GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102) + GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103) + GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104) + GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105) + GENERATE_ENUM(PTRBUFF_EF_PUSH, 106) + GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107) + GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108) + GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112) + GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113) + GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114) + GENERATE_ENUM(PTRBUFF_PI_RTR, 115) + GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116) + GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117) + GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118) + GENERATE_ENUM(PTRBUFF_SQ_DEC, 119) + GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120) + GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121) + GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122) + GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123) + GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124) + GENERATE_ENUM(PTRBUFF_END_BUFFER, 125) + GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126) + GENERATE_ENUM(VERTS_WRITTEN_SPI, 127) + GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128) + GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129) + GENERATE_ENUM(TP_DATA_RETURN, 130) + GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131) + GENERATE_ENUM(SPI_WRITES_SP, 132) + GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133) + GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134) + GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135) + GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136) + GENERATE_ENUM(SP_EXPORTS_TO_SX, 137) + GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138) + GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139) + GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140) + GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141) + GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142) + GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143) + GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144) + GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145) + GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146) + GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147) + GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148) + GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149) + GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150) + GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151) + GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152) + GENERATE_ENUM(SQ_PIX_TOTAL, 153) + GENERATE_ENUM(SQ_PIX_KILLED, 154) +END_ENUMTYPE(SQ_PERFCNT_SELECT) + +START_ENUMTYPE(SX_PERFCNT_SELECT) + GENERATE_ENUM(SX_EXPORT_VECTORS, 0) + GENERATE_ENUM(SX_DUMMY_QUADS, 1) + GENERATE_ENUM(SX_ALPHA_FAIL, 2) + GENERATE_ENUM(SX_RB_QUAD_BUSY, 3) + GENERATE_ENUM(SX_RB_COLOR_BUSY, 4) + GENERATE_ENUM(SX_RB_QUAD_STALL, 5) + GENERATE_ENUM(SX_RB_COLOR_STALL, 6) +END_ENUMTYPE(SX_PERFCNT_SELECT) + +START_ENUMTYPE(Abs_modifier) + GENERATE_ENUM(NO_ABS_MOD, 0) + GENERATE_ENUM(ABS_MOD, 1) +END_ENUMTYPE(Abs_modifier) + +START_ENUMTYPE(Exporting) + GENERATE_ENUM(NOT_EXPORTING, 0) + GENERATE_ENUM(EXPORTING, 1) +END_ENUMTYPE(Exporting) + +START_ENUMTYPE(ScalarOpcode) + GENERATE_ENUM(ADDs, 0) + GENERATE_ENUM(ADD_PREVs, 1) + GENERATE_ENUM(MULs, 2) + GENERATE_ENUM(MUL_PREVs, 3) + GENERATE_ENUM(MUL_PREV2s, 4) + GENERATE_ENUM(MAXs, 5) + GENERATE_ENUM(MINs, 6) + GENERATE_ENUM(SETEs, 7) + GENERATE_ENUM(SETGTs, 8) + GENERATE_ENUM(SETGTEs, 9) + GENERATE_ENUM(SETNEs, 10) + GENERATE_ENUM(FRACs, 11) + GENERATE_ENUM(TRUNCs, 12) + GENERATE_ENUM(FLOORs, 13) + GENERATE_ENUM(EXP_IEEE, 14) + GENERATE_ENUM(LOG_CLAMP, 15) + GENERATE_ENUM(LOG_IEEE, 16) + GENERATE_ENUM(RECIP_CLAMP, 17) + GENERATE_ENUM(RECIP_FF, 18) + GENERATE_ENUM(RECIP_IEEE, 19) + GENERATE_ENUM(RECIPSQ_CLAMP, 20) + GENERATE_ENUM(RECIPSQ_FF, 21) + GENERATE_ENUM(RECIPSQ_IEEE, 22) + GENERATE_ENUM(MOVAs, 23) + GENERATE_ENUM(MOVA_FLOORs, 24) + GENERATE_ENUM(SUBs, 25) + GENERATE_ENUM(SUB_PREVs, 26) + GENERATE_ENUM(PRED_SETEs, 27) + GENERATE_ENUM(PRED_SETNEs, 28) + GENERATE_ENUM(PRED_SETGTs, 29) + GENERATE_ENUM(PRED_SETGTEs, 30) + GENERATE_ENUM(PRED_SET_INVs, 31) + GENERATE_ENUM(PRED_SET_POPs, 32) + GENERATE_ENUM(PRED_SET_CLRs, 33) + GENERATE_ENUM(PRED_SET_RESTOREs, 34) + GENERATE_ENUM(KILLEs, 35) + GENERATE_ENUM(KILLGTs, 36) + GENERATE_ENUM(KILLGTEs, 37) + GENERATE_ENUM(KILLNEs, 38) + GENERATE_ENUM(KILLONEs, 39) + GENERATE_ENUM(SQRT_IEEE, 40) + GENERATE_ENUM(MUL_CONST_0, 42) + GENERATE_ENUM(MUL_CONST_1, 43) + GENERATE_ENUM(ADD_CONST_0, 44) + GENERATE_ENUM(ADD_CONST_1, 45) + GENERATE_ENUM(SUB_CONST_0, 46) + GENERATE_ENUM(SUB_CONST_1, 47) + GENERATE_ENUM(SIN, 48) + GENERATE_ENUM(COS, 49) + GENERATE_ENUM(RETAIN_PREV, 50) +END_ENUMTYPE(ScalarOpcode) + +START_ENUMTYPE(SwizzleType) + GENERATE_ENUM(NO_SWIZZLE, 0) + GENERATE_ENUM(SHIFT_RIGHT_1, 1) + GENERATE_ENUM(SHIFT_RIGHT_2, 2) + GENERATE_ENUM(SHIFT_RIGHT_3, 3) +END_ENUMTYPE(SwizzleType) + +START_ENUMTYPE(InputModifier) + GENERATE_ENUM(NIL, 0) + GENERATE_ENUM(NEGATE, 1) +END_ENUMTYPE(InputModifier) + +START_ENUMTYPE(PredicateSelect) + GENERATE_ENUM(NO_PREDICATION, 0) + GENERATE_ENUM(PREDICATE_QUAD, 1) + GENERATE_ENUM(PREDICATED_2, 2) + GENERATE_ENUM(PREDICATED_3, 3) +END_ENUMTYPE(PredicateSelect) + +START_ENUMTYPE(OperandSelect1) + GENERATE_ENUM(ABSOLUTE_REG, 0) + GENERATE_ENUM(RELATIVE_REG, 1) +END_ENUMTYPE(OperandSelect1) + +START_ENUMTYPE(VectorOpcode) + GENERATE_ENUM(ADDv, 0) + GENERATE_ENUM(MULv, 1) + GENERATE_ENUM(MAXv, 2) + GENERATE_ENUM(MINv, 3) + GENERATE_ENUM(SETEv, 4) + GENERATE_ENUM(SETGTv, 5) + GENERATE_ENUM(SETGTEv, 6) + GENERATE_ENUM(SETNEv, 7) + GENERATE_ENUM(FRACv, 8) + GENERATE_ENUM(TRUNCv, 9) + GENERATE_ENUM(FLOORv, 10) + GENERATE_ENUM(MULADDv, 11) + GENERATE_ENUM(CNDEv, 12) + GENERATE_ENUM(CNDGTEv, 13) + GENERATE_ENUM(CNDGTv, 14) + GENERATE_ENUM(DOT4v, 15) + GENERATE_ENUM(DOT3v, 16) + GENERATE_ENUM(DOT2ADDv, 17) + GENERATE_ENUM(CUBEv, 18) + GENERATE_ENUM(MAX4v, 19) + GENERATE_ENUM(PRED_SETE_PUSHv, 20) + GENERATE_ENUM(PRED_SETNE_PUSHv, 21) + GENERATE_ENUM(PRED_SETGT_PUSHv, 22) + GENERATE_ENUM(PRED_SETGTE_PUSHv, 23) + GENERATE_ENUM(KILLEv, 24) + GENERATE_ENUM(KILLGTv, 25) + GENERATE_ENUM(KILLGTEv, 26) + GENERATE_ENUM(KILLNEv, 27) + GENERATE_ENUM(DSTv, 28) + GENERATE_ENUM(MOVAv, 29) +END_ENUMTYPE(VectorOpcode) + +START_ENUMTYPE(OperandSelect0) + GENERATE_ENUM(CONSTANT, 0) + GENERATE_ENUM(NON_CONSTANT, 1) +END_ENUMTYPE(OperandSelect0) + +START_ENUMTYPE(Ressource_type) + GENERATE_ENUM(ALU, 0) + GENERATE_ENUM(TEXTURE, 1) +END_ENUMTYPE(Ressource_type) + +START_ENUMTYPE(Instruction_serial) + GENERATE_ENUM(NOT_SERIAL, 0) + GENERATE_ENUM(SERIAL, 1) +END_ENUMTYPE(Instruction_serial) + +START_ENUMTYPE(VC_type) + GENERATE_ENUM(ALU_TP_REQUEST, 0) + GENERATE_ENUM(VC_REQUEST, 1) +END_ENUMTYPE(VC_type) + +START_ENUMTYPE(Addressing) + GENERATE_ENUM(RELATIVE_ADDR, 0) + GENERATE_ENUM(ABSOLUTE_ADDR, 1) +END_ENUMTYPE(Addressing) + +START_ENUMTYPE(CFOpcode) + GENERATE_ENUM(NOP, 0) + GENERATE_ENUM(EXECUTE, 1) + GENERATE_ENUM(EXECUTE_END, 2) + GENERATE_ENUM(COND_EXECUTE, 3) + GENERATE_ENUM(COND_EXECUTE_END, 4) + GENERATE_ENUM(COND_PRED_EXECUTE, 5) + GENERATE_ENUM(COND_PRED_EXECUTE_END, 6) + GENERATE_ENUM(LOOP_START, 7) + GENERATE_ENUM(LOOP_END, 8) + GENERATE_ENUM(COND_CALL, 9) + GENERATE_ENUM(RETURN, 10) + GENERATE_ENUM(COND_JMP, 11) + GENERATE_ENUM(ALLOCATE, 12) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14) + GENERATE_ENUM(MARK_VS_FETCH_DONE, 15) +END_ENUMTYPE(CFOpcode) + +START_ENUMTYPE(Allocation_type) + GENERATE_ENUM(SQ_NO_ALLOC, 0) + GENERATE_ENUM(SQ_POSITION, 1) + GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2) + GENERATE_ENUM(SQ_MEMORY, 3) +END_ENUMTYPE(Allocation_type) + +START_ENUMTYPE(TexInstOpcode) + GENERATE_ENUM(TEX_INST_FETCH, 1) + GENERATE_ENUM(TEX_INST_RESERVED_1, 2) + GENERATE_ENUM(TEX_INST_RESERVED_2, 3) + GENERATE_ENUM(TEX_INST_RESERVED_3, 4) + GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16) + GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17) + GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18) + GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19) + GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26) + GENERATE_ENUM(TEX_INST_RESERVED_4, 27) +END_ENUMTYPE(TexInstOpcode) + +START_ENUMTYPE(Addressmode) + GENERATE_ENUM(LOGICAL, 0) + GENERATE_ENUM(LOOP_RELATIVE, 1) +END_ENUMTYPE(Addressmode) + +START_ENUMTYPE(TexCoordDenorm) + GENERATE_ENUM(TEX_COORD_NORMALIZED, 0) + GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1) +END_ENUMTYPE(TexCoordDenorm) + +START_ENUMTYPE(SrcSel) + GENERATE_ENUM(SRC_SEL_X, 0) + GENERATE_ENUM(SRC_SEL_Y, 1) + GENERATE_ENUM(SRC_SEL_Z, 2) + GENERATE_ENUM(SRC_SEL_W, 3) +END_ENUMTYPE(SrcSel) + +START_ENUMTYPE(DstSel) + GENERATE_ENUM(DST_SEL_X, 0) + GENERATE_ENUM(DST_SEL_Y, 1) + GENERATE_ENUM(DST_SEL_Z, 2) + GENERATE_ENUM(DST_SEL_W, 3) + GENERATE_ENUM(DST_SEL_0, 4) + GENERATE_ENUM(DST_SEL_1, 5) + GENERATE_ENUM(DST_SEL_RSVD, 6) + GENERATE_ENUM(DST_SEL_MASK, 7) +END_ENUMTYPE(DstSel) + +START_ENUMTYPE(MagFilter) + GENERATE_ENUM(MAG_FILTER_POINT, 0) + GENERATE_ENUM(MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MagFilter) + +START_ENUMTYPE(MinFilter) + GENERATE_ENUM(MIN_FILTER_POINT, 0) + GENERATE_ENUM(MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MinFilter) + +START_ENUMTYPE(MipFilter) + GENERATE_ENUM(MIP_FILTER_POINT, 0) + GENERATE_ENUM(MIP_FILTER_LINEAR, 1) + GENERATE_ENUM(MIP_FILTER_BASEMAP, 2) + GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MipFilter) + +START_ENUMTYPE(AnisoFilter) + GENERATE_ENUM(ANISO_FILTER_DISABLED, 0) + GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1) + GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2) + GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3) + GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4) + GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5) + GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(AnisoFilter) + +START_ENUMTYPE(ArbitraryFilter) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5) + GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(ArbitraryFilter) + +START_ENUMTYPE(VolMagFilter) + GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMagFilter) + +START_ENUMTYPE(VolMinFilter) + GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMinFilter) + +START_ENUMTYPE(PredSelect) + GENERATE_ENUM(NOT_PREDICATED, 0) + GENERATE_ENUM(PREDICATED, 1) +END_ENUMTYPE(PredSelect) + +START_ENUMTYPE(SampleLocation) + GENERATE_ENUM(SAMPLE_CENTROID, 0) + GENERATE_ENUM(SAMPLE_CENTER, 1) +END_ENUMTYPE(SampleLocation) + +START_ENUMTYPE(VertexMode) + GENERATE_ENUM(POSITION_1_VECTOR, 0) + GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3) + GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6) + GENERATE_ENUM(MULTIPASS, 7) +END_ENUMTYPE(VertexMode) + +START_ENUMTYPE(Sample_Cntl) + GENERATE_ENUM(CENTROIDS_ONLY, 0) + GENERATE_ENUM(CENTERS_ONLY, 1) + GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2) + GENERATE_ENUM(UNDEF, 3) +END_ENUMTYPE(Sample_Cntl) + +START_ENUMTYPE(MhPerfEncode) + GENERATE_ENUM(CP_R0_REQUESTS, 0) + GENERATE_ENUM(CP_R1_REQUESTS, 1) + GENERATE_ENUM(CP_R2_REQUESTS, 2) + GENERATE_ENUM(CP_R3_REQUESTS, 3) + GENERATE_ENUM(CP_R4_REQUESTS, 4) + GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5) + GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6) + GENERATE_ENUM(CP_TOTAL_REQUESTS, 7) + GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8) + GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9) + GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10) + GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11) + GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12) + GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13) + GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14) + GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15) + GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16) + GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17) + GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18) + GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19) + GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20) + GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21) + GENERATE_ENUM(VGT_R0_REQUESTS, 22) + GENERATE_ENUM(VGT_R1_REQUESTS, 23) + GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24) + GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25) + GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26) + GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27) + GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28) + GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29) + GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30) + GENERATE_ENUM(TC_TOTAL_REQUESTS, 31) + GENERATE_ENUM(TC_ROQ_REQUESTS, 32) + GENERATE_ENUM(TC_INFO_SENT, 33) + GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34) + GENERATE_ENUM(TC_DATA_BEATS_READ, 35) + GENERATE_ENUM(TCD_BURSTS_READ, 36) + GENERATE_ENUM(RB_REQUESTS, 37) + GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38) + GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47) + GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56) + GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65) + GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111) + GENERATE_ENUM(TOTAL_MMU_MISSES, 112) + GENERATE_ENUM(MMU_READ_MISSES, 113) + GENERATE_ENUM(MMU_WRITE_MISSES, 114) + GENERATE_ENUM(TOTAL_MMU_HITS, 115) + GENERATE_ENUM(MMU_READ_HITS, 116) + GENERATE_ENUM(MMU_WRITE_HITS, 117) + GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118) + GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119) + GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120) + GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121) + GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122) + GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123) + GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124) + GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125) + GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126) + GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127) + GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128) + GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129) + GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130) + GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131) + GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132) + GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133) + GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136) + GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140) + GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148) + GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149) + GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150) + GENERATE_ENUM(TOTAL_MH_REQUESTS, 151) + GENERATE_ENUM(MH_BUSY, 152) + GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153) + GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154) + GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155) + GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156) + GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157) + GENERATE_ENUM(ARQ_N_ENTRIES, 158) + GENERATE_ENUM(WDB_N_ENTRIES, 159) + GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160) + GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161) + GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162) + GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163) + GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164) + GENERATE_ENUM(CP_W_16B_REQUESTS, 165) + GENERATE_ENUM(CP_W_32B_REQUESTS, 166) + GENERATE_ENUM(TC_16B_REQUESTS, 167) + GENERATE_ENUM(TC_32B_REQUESTS, 168) + GENERATE_ENUM(PA_REQUESTS, 169) + GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170) + GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171) + GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180) + GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181) +END_ENUMTYPE(MhPerfEncode) + +START_ENUMTYPE(MmuClntBeh) + GENERATE_ENUM(BEH_NEVR, 0) + GENERATE_ENUM(BEH_TRAN_RNG, 1) + GENERATE_ENUM(BEH_TRAN_FLT, 2) +END_ENUMTYPE(MmuClntBeh) + +START_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + GENERATE_ENUM(RBBM1_COUNT, 0) + GENERATE_ENUM(RBBM1_NRT_BUSY, 1) + GENERATE_ENUM(RBBM1_RB_BUSY, 2) + GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3) + GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4) + GENERATE_ENUM(RBBM1_VGT_BUSY, 5) + GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6) + GENERATE_ENUM(RBBM1_PA_BUSY, 7) + GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8) + GENERATE_ENUM(RBBM1_TPC_BUSY, 9) + GENERATE_ENUM(RBBM1_TC_BUSY, 10) + GENERATE_ENUM(RBBM1_SX_BUSY, 11) + GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12) + GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13) + GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14) + GENERATE_ENUM(RBBM1_INTERRUPT, 15) +END_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + +START_ENUMTYPE(CP_PERFCOUNT_SEL) + GENERATE_ENUM(ALWAYS_COUNT, 0) + GENERATE_ENUM(TRANS_FIFO_FULL, 1) + GENERATE_ENUM(TRANS_FIFO_AF, 2) + GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3) + GENERATE_ENUM(Reserved_04, 4) + GENERATE_ENUM(Reserved_05, 5) + GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6) + GENERATE_ENUM(Reserved_07, 7) + GENERATE_ENUM(CSF_NRT_READ_WAIT, 8) + GENERATE_ENUM(CSF_I1_FIFO_FULL, 9) + GENERATE_ENUM(CSF_I2_FIFO_FULL, 10) + GENERATE_ENUM(CSF_ST_FIFO_FULL, 11) + GENERATE_ENUM(Reserved_12, 12) + GENERATE_ENUM(CSF_RING_ROQ_FULL, 13) + GENERATE_ENUM(CSF_I1_ROQ_FULL, 14) + GENERATE_ENUM(CSF_I2_ROQ_FULL, 15) + GENERATE_ENUM(CSF_ST_ROQ_FULL, 16) + GENERATE_ENUM(Reserved_17, 17) + GENERATE_ENUM(MIU_TAG_MEM_FULL, 18) + GENERATE_ENUM(MIU_WRITECLEAN, 19) + GENERATE_ENUM(Reserved_20, 20) + GENERATE_ENUM(Reserved_21, 21) + GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22) + GENERATE_ENUM(MIU_NRT_READ_STALLED, 23) + GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24) + GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25) + GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26) + GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27) + GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28) + GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29) + GENERATE_ENUM(ME_MICRO_RB_STARVED, 30) + GENERATE_ENUM(ME_MICRO_I1_STARVED, 31) + GENERATE_ENUM(ME_MICRO_I2_STARVED, 32) + GENERATE_ENUM(ME_MICRO_ST_STARVED, 33) + GENERATE_ENUM(Reserved_34, 34) + GENERATE_ENUM(Reserved_35, 35) + GENERATE_ENUM(Reserved_36, 36) + GENERATE_ENUM(Reserved_37, 37) + GENERATE_ENUM(Reserved_38, 38) + GENERATE_ENUM(Reserved_39, 39) + GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40) + GENERATE_ENUM(ME_BUSY_CLOCKS, 41) + GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42) + GENERATE_ENUM(PFP_TYPE0_PACKET, 43) + GENERATE_ENUM(PFP_TYPE3_PACKET, 44) + GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45) + GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46) + GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47) + GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48) + GENERATE_ENUM(Reserved_49, 49) + GENERATE_ENUM(Reserved_50, 50) + GENERATE_ENUM(Reserved_51, 51) + GENERATE_ENUM(Reserved_52, 52) + GENERATE_ENUM(Reserved_53, 53) + GENERATE_ENUM(Reserved_54, 54) + GENERATE_ENUM(Reserved_55, 55) + GENERATE_ENUM(Reserved_56, 56) + GENERATE_ENUM(Reserved_57, 57) + GENERATE_ENUM(Reserved_58, 58) + GENERATE_ENUM(Reserved_59, 59) + GENERATE_ENUM(Reserved_60, 60) + GENERATE_ENUM(Reserved_61, 61) + GENERATE_ENUM(Reserved_62, 62) + GENERATE_ENUM(Reserved_63, 63) +END_ENUMTYPE(CP_PERFCOUNT_SEL) + +START_ENUMTYPE(ColorformatX) + GENERATE_ENUM(COLORX_4_4_4_4, 0) + GENERATE_ENUM(COLORX_1_5_5_5, 1) + GENERATE_ENUM(COLORX_5_6_5, 2) + GENERATE_ENUM(COLORX_8, 3) + GENERATE_ENUM(COLORX_8_8, 4) + GENERATE_ENUM(COLORX_8_8_8_8, 5) + GENERATE_ENUM(COLORX_S8_8_8_8, 6) + GENERATE_ENUM(COLORX_16_FLOAT, 7) + GENERATE_ENUM(COLORX_16_16_FLOAT, 8) + GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9) + GENERATE_ENUM(COLORX_32_FLOAT, 10) + GENERATE_ENUM(COLORX_32_32_FLOAT, 11) + GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12) + GENERATE_ENUM(COLORX_2_3_3, 13) + GENERATE_ENUM(COLORX_8_8_8, 14) +END_ENUMTYPE(ColorformatX) + +START_ENUMTYPE(DepthformatX) + GENERATE_ENUM(DEPTHX_16, 0) + GENERATE_ENUM(DEPTHX_24_8, 1) +END_ENUMTYPE(DepthformatX) + +START_ENUMTYPE(CompareFrag) + GENERATE_ENUM(FRAG_NEVER, 0) + GENERATE_ENUM(FRAG_LESS, 1) + GENERATE_ENUM(FRAG_EQUAL, 2) + GENERATE_ENUM(FRAG_LEQUAL, 3) + GENERATE_ENUM(FRAG_GREATER, 4) + GENERATE_ENUM(FRAG_NOTEQUAL, 5) + GENERATE_ENUM(FRAG_GEQUAL, 6) + GENERATE_ENUM(FRAG_ALWAYS, 7) +END_ENUMTYPE(CompareFrag) + +START_ENUMTYPE(CompareRef) + GENERATE_ENUM(REF_NEVER, 0) + GENERATE_ENUM(REF_LESS, 1) + GENERATE_ENUM(REF_EQUAL, 2) + GENERATE_ENUM(REF_LEQUAL, 3) + GENERATE_ENUM(REF_GREATER, 4) + GENERATE_ENUM(REF_NOTEQUAL, 5) + GENERATE_ENUM(REF_GEQUAL, 6) + GENERATE_ENUM(REF_ALWAYS, 7) +END_ENUMTYPE(CompareRef) + +START_ENUMTYPE(StencilOp) + GENERATE_ENUM(STENCIL_KEEP, 0) + GENERATE_ENUM(STENCIL_ZERO, 1) + GENERATE_ENUM(STENCIL_REPLACE, 2) + GENERATE_ENUM(STENCIL_INCR_CLAMP, 3) + GENERATE_ENUM(STENCIL_DECR_CLAMP, 4) + GENERATE_ENUM(STENCIL_INVERT, 5) + GENERATE_ENUM(STENCIL_INCR_WRAP, 6) + GENERATE_ENUM(STENCIL_DECR_WRAP, 7) +END_ENUMTYPE(StencilOp) + +START_ENUMTYPE(BlendOpX) + GENERATE_ENUM(BLENDX_ZERO, 0) + GENERATE_ENUM(BLENDX_ONE, 1) + GENERATE_ENUM(BLENDX_SRC_COLOR, 4) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5) + GENERATE_ENUM(BLENDX_SRC_ALPHA, 6) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7) + GENERATE_ENUM(BLENDX_DST_COLOR, 8) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9) + GENERATE_ENUM(BLENDX_DST_ALPHA, 10) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11) + GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13) + GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15) + GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16) +END_ENUMTYPE(BlendOpX) + +START_ENUMTYPE(CombFuncX) + GENERATE_ENUM(COMB_DST_PLUS_SRC, 0) + GENERATE_ENUM(COMB_SRC_MINUS_DST, 1) + GENERATE_ENUM(COMB_MIN_DST_SRC, 2) + GENERATE_ENUM(COMB_MAX_DST_SRC, 3) + GENERATE_ENUM(COMB_DST_MINUS_SRC, 4) + GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5) +END_ENUMTYPE(CombFuncX) + +START_ENUMTYPE(DitherModeX) + GENERATE_ENUM(DITHER_DISABLE, 0) + GENERATE_ENUM(DITHER_ALWAYS, 1) + GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2) +END_ENUMTYPE(DitherModeX) + +START_ENUMTYPE(DitherTypeX) + GENERATE_ENUM(DITHER_PIXEL, 0) + GENERATE_ENUM(DITHER_SUBPIXEL, 1) +END_ENUMTYPE(DitherTypeX) + +START_ENUMTYPE(EdramMode) + GENERATE_ENUM(EDRAM_NOP, 0) + GENERATE_ENUM(COLOR_DEPTH, 4) + GENERATE_ENUM(DEPTH_ONLY, 5) + GENERATE_ENUM(EDRAM_COPY, 6) +END_ENUMTYPE(EdramMode) + +START_ENUMTYPE(SurfaceEndian) + GENERATE_ENUM(ENDIAN_NONE, 0) + GENERATE_ENUM(ENDIAN_8IN16, 1) + GENERATE_ENUM(ENDIAN_8IN32, 2) + GENERATE_ENUM(ENDIAN_16IN32, 3) + GENERATE_ENUM(ENDIAN_8IN64, 4) + GENERATE_ENUM(ENDIAN_8IN128, 5) +END_ENUMTYPE(SurfaceEndian) + +START_ENUMTYPE(EdramSizeX) + GENERATE_ENUM(EDRAMSIZE_16KB, 0) + GENERATE_ENUM(EDRAMSIZE_32KB, 1) + GENERATE_ENUM(EDRAMSIZE_64KB, 2) + GENERATE_ENUM(EDRAMSIZE_128KB, 3) + GENERATE_ENUM(EDRAMSIZE_256KB, 4) + GENERATE_ENUM(EDRAMSIZE_512KB, 5) + GENERATE_ENUM(EDRAMSIZE_1MB, 6) + GENERATE_ENUM(EDRAMSIZE_2MB, 7) + GENERATE_ENUM(EDRAMSIZE_4MB, 8) + GENERATE_ENUM(EDRAMSIZE_8MB, 9) + GENERATE_ENUM(EDRAMSIZE_16MB, 10) +END_ENUMTYPE(EdramSizeX) + +START_ENUMTYPE(RB_PERFCNT_SELECT) + GENERATE_ENUM(RBPERF_CNTX_BUSY, 0) + GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7) + GENERATE_ENUM(RBPERF_MH_STARVED, 8) + GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23) + GENERATE_ENUM(RBPERF_ZXP_STALL, 24) + GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25) + GENERATE_ENUM(RBPERF_EVENT_PENDING, 26) + GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27) + GENERATE_ENUM(RBPERF_RB_MH_VALID, 28) + GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30) + GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31) + GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32) + GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33) + GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37) + GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38) + GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39) + GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40) + GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41) + GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42) + GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43) + GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44) + GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45) + GENERATE_ENUM(RBPERF_ZPASS_DONE, 46) + GENERATE_ENUM(RBPERF_ZCMD_VALID, 47) + GENERATE_ENUM(RBPERF_CCMD_VALID, 48) + GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49) + GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50) + GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51) + GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52) + GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53) + GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54) + GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55) + GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56) +END_ENUMTYPE(RB_PERFCNT_SELECT) + +START_ENUMTYPE(DepthFormat) + GENERATE_ENUM(DEPTH_24_8, 22) + GENERATE_ENUM(DEPTH_24_8_FLOAT, 23) + GENERATE_ENUM(DEPTH_16, 24) +END_ENUMTYPE(DepthFormat) + +START_ENUMTYPE(SurfaceSwap) + GENERATE_ENUM(SWAP_LOWRED, 0) + GENERATE_ENUM(SWAP_LOWBLUE, 1) +END_ENUMTYPE(SurfaceSwap) + +START_ENUMTYPE(DepthArray) + GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0) + GENERATE_ENUM(ARRAY_2D_DEPTH, 1) +END_ENUMTYPE(DepthArray) + +START_ENUMTYPE(ColorArray) + GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0) + GENERATE_ENUM(ARRAY_2D_COLOR, 1) + GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3) +END_ENUMTYPE(ColorArray) + +START_ENUMTYPE(ColorFormat) + GENERATE_ENUM(COLOR_8, 2) + GENERATE_ENUM(COLOR_1_5_5_5, 3) + GENERATE_ENUM(COLOR_5_6_5, 4) + GENERATE_ENUM(COLOR_6_5_5, 5) + GENERATE_ENUM(COLOR_8_8_8_8, 6) + GENERATE_ENUM(COLOR_2_10_10_10, 7) + GENERATE_ENUM(COLOR_8_A, 8) + GENERATE_ENUM(COLOR_8_B, 9) + GENERATE_ENUM(COLOR_8_8, 10) + GENERATE_ENUM(COLOR_8_8_8, 11) + GENERATE_ENUM(COLOR_8_8_8_8_A, 14) + GENERATE_ENUM(COLOR_4_4_4_4, 15) + GENERATE_ENUM(COLOR_10_11_11, 16) + GENERATE_ENUM(COLOR_11_11_10, 17) + GENERATE_ENUM(COLOR_16, 24) + GENERATE_ENUM(COLOR_16_16, 25) + GENERATE_ENUM(COLOR_16_16_16_16, 26) + GENERATE_ENUM(COLOR_16_FLOAT, 30) + GENERATE_ENUM(COLOR_16_16_FLOAT, 31) + GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(COLOR_32_FLOAT, 36) + GENERATE_ENUM(COLOR_32_32_FLOAT, 37) + GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(COLOR_2_3_3, 39) +END_ENUMTYPE(ColorFormat) + +START_ENUMTYPE(SurfaceNumber) + GENERATE_ENUM(NUMBER_UREPEAT, 0) + GENERATE_ENUM(NUMBER_SREPEAT, 1) + GENERATE_ENUM(NUMBER_UINTEGER, 2) + GENERATE_ENUM(NUMBER_SINTEGER, 3) + GENERATE_ENUM(NUMBER_GAMMA, 4) + GENERATE_ENUM(NUMBER_FIXED, 5) + GENERATE_ENUM(NUMBER_FLOAT, 7) +END_ENUMTYPE(SurfaceNumber) + +START_ENUMTYPE(SurfaceFormat) + GENERATE_ENUM(FMT_1_REVERSE, 0) + GENERATE_ENUM(FMT_1, 1) + GENERATE_ENUM(FMT_8, 2) + GENERATE_ENUM(FMT_1_5_5_5, 3) + GENERATE_ENUM(FMT_5_6_5, 4) + GENERATE_ENUM(FMT_6_5_5, 5) + GENERATE_ENUM(FMT_8_8_8_8, 6) + GENERATE_ENUM(FMT_2_10_10_10, 7) + GENERATE_ENUM(FMT_8_A, 8) + GENERATE_ENUM(FMT_8_B, 9) + GENERATE_ENUM(FMT_8_8, 10) + GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11) + GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12) + GENERATE_ENUM(FMT_5_5_5_1, 13) + GENERATE_ENUM(FMT_8_8_8_8_A, 14) + GENERATE_ENUM(FMT_4_4_4_4, 15) + GENERATE_ENUM(FMT_8_8_8, 16) + GENERATE_ENUM(FMT_DXT1, 18) + GENERATE_ENUM(FMT_DXT2_3, 19) + GENERATE_ENUM(FMT_DXT4_5, 20) + GENERATE_ENUM(FMT_10_10_10_2, 21) + GENERATE_ENUM(FMT_24_8, 22) + GENERATE_ENUM(FMT_16, 24) + GENERATE_ENUM(FMT_16_16, 25) + GENERATE_ENUM(FMT_16_16_16_16, 26) + GENERATE_ENUM(FMT_16_EXPAND, 27) + GENERATE_ENUM(FMT_16_16_EXPAND, 28) + GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29) + GENERATE_ENUM(FMT_16_FLOAT, 30) + GENERATE_ENUM(FMT_16_16_FLOAT, 31) + GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(FMT_32, 33) + GENERATE_ENUM(FMT_32_32, 34) + GENERATE_ENUM(FMT_32_32_32_32, 35) + GENERATE_ENUM(FMT_32_FLOAT, 36) + GENERATE_ENUM(FMT_32_32_FLOAT, 37) + GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(FMT_ATI_TC_RGB, 39) + GENERATE_ENUM(FMT_ATI_TC_RGBA, 40) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42) + GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44) + GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46) + GENERATE_ENUM(FMT_ETC1_RGB, 47) + GENERATE_ENUM(FMT_ETC1_RGBA, 48) + GENERATE_ENUM(FMT_DXN, 49) + GENERATE_ENUM(FMT_2_3_3, 51) + GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54) + GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55) + GENERATE_ENUM(FMT_32_32_32_FLOAT, 57) + GENERATE_ENUM(FMT_DXT3A, 58) + GENERATE_ENUM(FMT_DXT5A, 59) + GENERATE_ENUM(FMT_CTX1, 60) +END_ENUMTYPE(SurfaceFormat) + +START_ENUMTYPE(SurfaceTiling) + GENERATE_ENUM(ARRAY_LINEAR, 0) + GENERATE_ENUM(ARRAY_TILED, 1) +END_ENUMTYPE(SurfaceTiling) + +START_ENUMTYPE(SurfaceArray) + GENERATE_ENUM(ARRAY_1D, 0) + GENERATE_ENUM(ARRAY_2D, 1) + GENERATE_ENUM(ARRAY_3D, 2) + GENERATE_ENUM(ARRAY_3D_SLICE, 3) +END_ENUMTYPE(SurfaceArray) + +START_ENUMTYPE(SurfaceNumberX) + GENERATE_ENUM(NUMBERX_UREPEAT, 0) + GENERATE_ENUM(NUMBERX_SREPEAT, 1) + GENERATE_ENUM(NUMBERX_UINTEGER, 2) + GENERATE_ENUM(NUMBERX_SINTEGER, 3) + GENERATE_ENUM(NUMBERX_FLOAT, 7) +END_ENUMTYPE(SurfaceNumberX) + +START_ENUMTYPE(ColorArrayX) + GENERATE_ENUM(ARRAYX_2D_COLOR, 0) + GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1) +END_ENUMTYPE(ColorArrayX) + + + + +// ************************************************************************** +// These are ones that had to be added in addition to what's generated +// by the autoreg (in CSIM) +// ************************************************************************** +START_ENUMTYPE(DXClipSpaceDef) + GENERATE_ENUM(DXCLIP_OPENGL, 0) + GENERATE_ENUM(DXCLIP_DIRECTX, 1) +END_ENUMTYPE(DXClipSpaceDef) + +START_ENUMTYPE(PixCenter) + GENERATE_ENUM(PIXCENTER_D3D, 0) + GENERATE_ENUM(PIXCENTER_OGL, 1) +END_ENUMTYPE(PixCenter) + +START_ENUMTYPE(RoundMode) + GENERATE_ENUM(TRUNCATE, 0) + GENERATE_ENUM(ROUND, 1) + GENERATE_ENUM(ROUNDTOEVEN, 2) + GENERATE_ENUM(ROUNDTOODD, 3) +END_ENUMTYPE(RoundMode) + +START_ENUMTYPE(QuantMode) + GENERATE_ENUM(ONE_SIXTEENTH, 0) + GENERATE_ENUM(ONE_EIGHTH, 1) + GENERATE_ENUM(ONE_QUARTER, 2) + GENERATE_ENUM(ONE_HALF, 3) + GENERATE_ENUM(ONE, 4) +END_ENUMTYPE(QuantMode) + +START_ENUMTYPE(FrontFace) + GENERATE_ENUM(FRONT_CCW, 0) + GENERATE_ENUM(FRONT_CW, 1) +END_ENUMTYPE(FrontFace) + +START_ENUMTYPE(PolyMode) + GENERATE_ENUM(DISABLED, 0) + GENERATE_ENUM(DUALMODE, 1) +END_ENUMTYPE(PolyMode) + +START_ENUMTYPE(PType) + GENERATE_ENUM(DRAW_POINTS, 0) + GENERATE_ENUM(DRAW_LINES, 1) + GENERATE_ENUM(DRAW_TRIANGLES, 2) +END_ENUMTYPE(PType) + +START_ENUMTYPE(MSAANumSamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 3) +END_ENUMTYPE(MSAANumSamples) + +START_ENUMTYPE(PatternBitOrder) + GENERATE_ENUM(LITTLE, 0) + GENERATE_ENUM(BIG, 1) +END_ENUMTYPE(PatternBitOrder) + +START_ENUMTYPE(AutoResetCntl) + GENERATE_ENUM(NEVER, 0) + GENERATE_ENUM(EACHPRIMITIVE, 1) + GENERATE_ENUM(EACHPACKET, 2) +END_ENUMTYPE(AutoResetCntl) + +START_ENUMTYPE(ParamShade) + GENERATE_ENUM(FLAT, 0) + GENERATE_ENUM(GOURAUD, 1) +END_ENUMTYPE(ParamShade) + +START_ENUMTYPE(SamplingPattern) + GENERATE_ENUM(CENTROID, 0) + GENERATE_ENUM(PIXCENTER, 1) +END_ENUMTYPE(SamplingPattern) + +START_ENUMTYPE(MSAASamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 2) +END_ENUMTYPE(MSAASamples) + +START_ENUMTYPE(CopySampleSelect) + GENERATE_ENUM(SAMPLE_0, 0) + GENERATE_ENUM(SAMPLE_1, 1) + GENERATE_ENUM(SAMPLE_2, 2) + GENERATE_ENUM(SAMPLE_3, 3) + GENERATE_ENUM(SAMPLE_01, 4) + GENERATE_ENUM(SAMPLE_23, 5) + GENERATE_ENUM(SAMPLE_0123, 6) +END_ENUMTYPE(CopySampleSelect) + + +#undef START_ENUMTYPE +#undef GENERATE_ENUM +#undef END_ENUMTYPE + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h new file mode 100644 index 000000000000..f7efe31bc8a8 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h @@ -0,0 +1,3404 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_REGISTER(PA_CL_VPORT_XSCALE) + GENERATE_FIELD(VPORT_XSCALE, float) +END_REGISTER(PA_CL_VPORT_XSCALE) + +START_REGISTER(PA_CL_VPORT_XOFFSET) + GENERATE_FIELD(VPORT_XOFFSET, float) +END_REGISTER(PA_CL_VPORT_XOFFSET) + +START_REGISTER(PA_CL_VPORT_YSCALE) + GENERATE_FIELD(VPORT_YSCALE, float) +END_REGISTER(PA_CL_VPORT_YSCALE) + +START_REGISTER(PA_CL_VPORT_YOFFSET) + GENERATE_FIELD(VPORT_YOFFSET, float) +END_REGISTER(PA_CL_VPORT_YOFFSET) + +START_REGISTER(PA_CL_VPORT_ZSCALE) + GENERATE_FIELD(VPORT_ZSCALE, float) +END_REGISTER(PA_CL_VPORT_ZSCALE) + +START_REGISTER(PA_CL_VPORT_ZOFFSET) + GENERATE_FIELD(VPORT_ZOFFSET, float) +END_REGISTER(PA_CL_VPORT_ZOFFSET) + +START_REGISTER(PA_CL_VTE_CNTL) + GENERATE_FIELD(PERFCOUNTER_REF, bool) + GENERATE_FIELD(VTX_W0_FMT, bool) + GENERATE_FIELD(VTX_Z_FMT, bool) + GENERATE_FIELD(VTX_XY_FMT, bool) + GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_X_SCALE_ENA, bool) +END_REGISTER(PA_CL_VTE_CNTL) + +START_REGISTER(PA_CL_CLIP_CNTL) + GENERATE_FIELD(W_NAN_RETAIN, bool) + GENERATE_FIELD(Z_NAN_RETAIN, bool) + GENERATE_FIELD(XY_NAN_RETAIN, bool) + GENERATE_FIELD(VTX_KILL_OR, bool) + GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool) + GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef) + GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool) + GENERATE_FIELD(CLIP_DISABLE, bool) +END_REGISTER(PA_CL_CLIP_CNTL) + +START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + +START_REGISTER(PA_CL_ENHANCE) + GENERATE_FIELD(ECO_SPARE0, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool) +END_REGISTER(PA_CL_ENHANCE) + +START_REGISTER(PA_SC_ENHANCE) + GENERATE_FIELD(ECO_SPARE0, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE3, int) +END_REGISTER(PA_SC_ENHANCE) + +START_REGISTER(PA_SU_VTX_CNTL) + GENERATE_FIELD(QUANT_MODE, QuantMode) + GENERATE_FIELD(ROUND_MODE, RoundMode) + GENERATE_FIELD(PIX_CENTER, PixCenter) +END_REGISTER(PA_SU_VTX_CNTL) + +START_REGISTER(PA_SU_POINT_SIZE) + GENERATE_FIELD(WIDTH, fixed12_4) + GENERATE_FIELD(HEIGHT, fixed12_4) +END_REGISTER(PA_SU_POINT_SIZE) + +START_REGISTER(PA_SU_POINT_MINMAX) + GENERATE_FIELD(MAX_SIZE, fixed12_4) + GENERATE_FIELD(MIN_SIZE, fixed12_4) +END_REGISTER(PA_SU_POINT_MINMAX) + +START_REGISTER(PA_SU_LINE_CNTL) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_LINE_CNTL) + +START_REGISTER(PA_SU_FACE_DATA) + GENERATE_FIELD(BASE_ADDR, int) +END_REGISTER(PA_SU_FACE_DATA) + +START_REGISTER(PA_SU_SC_MODE_CNTL) + GENERATE_FIELD(FACE_WRITE_ENABLE, bool) + GENERATE_FIELD(FACE_KILL_ENABLE, bool) + GENERATE_FIELD(ZERO_AREA_FACENESS, bool) + GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool) + GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool) + GENERATE_FIELD(QUAD_ORDER_ENABLE, bool) + GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool) + GENERATE_FIELD(PERSP_CORR_DIS, bool) + GENERATE_FIELD(PROVOKING_VTX_LAST, bool) + GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool) + GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool) + GENERATE_FIELD(MSAA_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool) + GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType) + GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType) + GENERATE_FIELD(POLY_MODE, PolyMode) + GENERATE_FIELD(FACE, FrontFace) + GENERATE_FIELD(CULL_BACK, bool) + GENERATE_FIELD(CULL_FRONT, bool) +END_REGISTER(PA_SU_SC_MODE_CNTL) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + +START_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT) +END_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_HI) + +START_REGISTER(PA_SU_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_HI) + +START_REGISTER(PA_SU_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_HI) + +START_REGISTER(PA_SU_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_HI) + +START_REGISTER(PA_SC_WINDOW_OFFSET) + GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15) + GENERATE_FIELD(WINDOW_X_OFFSET, signedint15) +END_REGISTER(PA_SC_WINDOW_OFFSET) + +START_REGISTER(PA_SC_AA_CONFIG) + GENERATE_FIELD(MAX_SAMPLE_DIST, int) + GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples) +END_REGISTER(PA_SC_AA_CONFIG) + +START_REGISTER(PA_SC_AA_MASK) + GENERATE_FIELD(AA_MASK, hex) +END_REGISTER(PA_SC_AA_MASK) + +START_REGISTER(PA_SC_LINE_STIPPLE) + GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl) + GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder) + GENERATE_FIELD(REPEAT_COUNT, intMinusOne) + GENERATE_FIELD(LINE_PATTERN, hex) +END_REGISTER(PA_SC_LINE_STIPPLE) + +START_REGISTER(PA_SC_LINE_CNTL) + GENERATE_FIELD(LAST_PIXEL, bool) + GENERATE_FIELD(EXPAND_LINE_WIDTH, bool) + GENERATE_FIELD(USE_BRES_CNTL, bool) + GENERATE_FIELD(BRES_CNTL, int) +END_REGISTER(PA_SC_LINE_CNTL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(TL_X, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + GENERATE_FIELD(BR_Y, int) + GENERATE_FIELD(BR_X, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(TL_X, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + GENERATE_FIELD(BR_Y, int) + GENERATE_FIELD(BR_X, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + +START_REGISTER(PA_SC_VIZ_QUERY) + GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool) + GENERATE_FIELD(VIZ_QUERY_ID, int) + GENERATE_FIELD(VIZ_QUERY_ENA, bool) +END_REGISTER(PA_SC_VIZ_QUERY) + +START_REGISTER(PA_SC_VIZ_QUERY_STATUS) + GENERATE_FIELD(STATUS_BITS, hex) +END_REGISTER(PA_SC_VIZ_QUERY_STATUS) + +START_REGISTER(PA_SC_LINE_STIPPLE_STATE) + GENERATE_FIELD(CURRENT_COUNT, int) + GENERATE_FIELD(CURRENT_PTR, int) +END_REGISTER(PA_SC_LINE_STIPPLE_STATE) + +START_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT) +END_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SC_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SC_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_HI) + +START_REGISTER(PA_CL_CNTL_STATUS) + GENERATE_FIELD(CL_BUSY, int) +END_REGISTER(PA_CL_CNTL_STATUS) + +START_REGISTER(PA_SU_CNTL_STATUS) + GENERATE_FIELD(SU_BUSY, int) +END_REGISTER(PA_SU_CNTL_STATUS) + +START_REGISTER(PA_SC_CNTL_STATUS) + GENERATE_FIELD(SC_BUSY, int) +END_REGISTER(PA_SC_CNTL_STATUS) + +START_REGISTER(PA_SU_DEBUG_CNTL) + GENERATE_FIELD(SU_DEBUG_INDX, int) +END_REGISTER(PA_SU_DEBUG_CNTL) + +START_REGISTER(PA_SU_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(PA_SU_DEBUG_DATA) + +START_REGISTER(PA_SC_DEBUG_CNTL) + GENERATE_FIELD(SC_DEBUG_INDX, int) +END_REGISTER(PA_SC_DEBUG_CNTL) + +START_REGISTER(PA_SC_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(PA_SC_DEBUG_DATA) + +START_REGISTER(GFX_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(GFX_COPY_STATE) + +START_REGISTER(VGT_DRAW_INITIATOR) + GENERATE_FIELD(NUM_INDICES, uint) + GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE) + GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX) + GENERATE_FIELD(NOT_EOP, bool) + GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE) + GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT) + GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT) + GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE) +END_REGISTER(VGT_DRAW_INITIATOR) + +START_REGISTER(VGT_EVENT_INITIATOR) + GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE) +END_REGISTER(VGT_EVENT_INITIATOR) + +START_REGISTER(VGT_DMA_BASE) + GENERATE_FIELD(BASE_ADDR, uint) +END_REGISTER(VGT_DMA_BASE) + +START_REGISTER(VGT_DMA_SIZE) + GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE) + GENERATE_FIELD(NUM_WORDS, uint) +END_REGISTER(VGT_DMA_SIZE) + +START_REGISTER(VGT_BIN_BASE) + GENERATE_FIELD(BIN_BASE_ADDR, uint) +END_REGISTER(VGT_BIN_BASE) + +START_REGISTER(VGT_BIN_SIZE) + GENERATE_FIELD(FACENESS_RESET, int) + GENERATE_FIELD(FACENESS_FETCH, int) + GENERATE_FIELD(NUM_WORDS, uint) +END_REGISTER(VGT_BIN_SIZE) + +START_REGISTER(VGT_CURRENT_BIN_ID_MIN) + GENERATE_FIELD(GUARD_BAND, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(COLUMN, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MIN) + +START_REGISTER(VGT_CURRENT_BIN_ID_MAX) + GENERATE_FIELD(GUARD_BAND, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(COLUMN, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MAX) + +START_REGISTER(VGT_IMMED_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_IMMED_DATA) + +START_REGISTER(VGT_MAX_VTX_INDX) + GENERATE_FIELD(MAX_INDX, int) +END_REGISTER(VGT_MAX_VTX_INDX) + +START_REGISTER(VGT_MIN_VTX_INDX) + GENERATE_FIELD(MIN_INDX, int) +END_REGISTER(VGT_MIN_VTX_INDX) + +START_REGISTER(VGT_INDX_OFFSET) + GENERATE_FIELD(INDX_OFFSET, int) +END_REGISTER(VGT_INDX_OFFSET) + +START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + GENERATE_FIELD(VTX_REUSE_DEPTH, int) +END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + +START_REGISTER(VGT_OUT_DEALLOC_CNTL) + GENERATE_FIELD(DEALLOC_DIST, int) +END_REGISTER(VGT_OUT_DEALLOC_CNTL) + +START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + GENERATE_FIELD(RESET_INDX, int) +END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + +START_REGISTER(VGT_ENHANCE) + GENERATE_FIELD(MISC, hex) +END_REGISTER(VGT_ENHANCE) + +START_REGISTER(VGT_VTX_VECT_EJECT_REG) + GENERATE_FIELD(PRIM_COUNT, int) +END_REGISTER(VGT_VTX_VECT_EJECT_REG) + +START_REGISTER(VGT_LAST_COPY_STATE) + GENERATE_FIELD(DST_STATE_ID, int) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(VGT_LAST_COPY_STATE) + +START_REGISTER(VGT_DEBUG_CNTL) + GENERATE_FIELD(VGT_DEBUG_INDX, int) +END_REGISTER(VGT_DEBUG_CNTL) + +START_REGISTER(VGT_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_DEBUG_DATA) + +START_REGISTER(VGT_CNTL_STATUS) + GENERATE_FIELD(VGT_OUT_INDX_BUSY, int) + GENERATE_FIELD(VGT_OUT_BUSY, int) + GENERATE_FIELD(VGT_PT_BUSY, int) + GENERATE_FIELD(VGT_BIN_BUSY, int) + GENERATE_FIELD(VGT_VR_BUSY, int) + GENERATE_FIELD(VGT_GRP_BUSY, int) + GENERATE_FIELD(VGT_DMA_REQ_BUSY, int) + GENERATE_FIELD(VGT_DMA_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) +END_REGISTER(VGT_CNTL_STATUS) + +START_REGISTER(VGT_CRC_SQ_DATA) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_DATA) + +START_REGISTER(VGT_CRC_SQ_CTRL) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_CTRL) + +START_REGISTER(VGT_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER0_SELECT) + +START_REGISTER(VGT_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER1_SELECT) + +START_REGISTER(VGT_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER2_SELECT) + +START_REGISTER(VGT_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER3_SELECT) + +START_REGISTER(VGT_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_LOW) + +START_REGISTER(VGT_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_LOW) + +START_REGISTER(VGT_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_LOW) + +START_REGISTER(VGT_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_LOW) + +START_REGISTER(VGT_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_HI) + +START_REGISTER(VGT_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_HI) + +START_REGISTER(VGT_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_HI) + +START_REGISTER(VGT_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_HI) + +START_REGISTER(TC_CNTL_STATUS) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(TC_L2_HIT_MISS, int) + GENERATE_FIELD(L2_INVALIDATE, int) +END_REGISTER(TC_CNTL_STATUS) + +START_REGISTER(TCR_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCR_CHICKEN) + +START_REGISTER(TCF_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCF_CHICKEN) + +START_REGISTER(TCM_CHICKEN) + GENERATE_FIELD(SPARE, hex) + GENERATE_FIELD(ETC_COLOR_ENDIAN, int) + GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int) +END_REGISTER(TCM_CHICKEN) + +START_REGISTER(TCR_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER0_SELECT) + +START_REGISTER(TCR_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER1_SELECT) + +START_REGISTER(TCR_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER0_HI) + +START_REGISTER(TCR_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER1_HI) + +START_REGISTER(TCR_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER0_LOW) + +START_REGISTER(TCR_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER1_LOW) + +START_REGISTER(TP_TC_CLKGATE_CNTL) + GENERATE_FIELD(TC_BUSY_EXTEND, int) + GENERATE_FIELD(TP_BUSY_EXTEND, int) +END_REGISTER(TP_TC_CLKGATE_CNTL) + +START_REGISTER(TPC_CNTL_STATUS) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(TP_SQ_DEC, int) + GENERATE_FIELD(TA_TF_TC_FIFO_REN, int) + GENERATE_FIELD(TA_TF_RTS, int) + GENERATE_FIELD(TA_TB_RTR, int) + GENERATE_FIELD(TA_TB_TT_RTS, int) + GENERATE_FIELD(TA_TB_RTS, int) + GENERATE_FIELD(TW_TA_RTR, int) + GENERATE_FIELD(TW_TA_LAST_RTS, int) + GENERATE_FIELD(TW_TA_TT_RTS, int) + GENERATE_FIELD(TW_TA_RTS, int) + GENERATE_FIELD(TF_TW_RTR, int) + GENERATE_FIELD(TF_TW_STATE_RTS, int) + GENERATE_FIELD(TF_TW_RTS, int) + GENERATE_FIELD(TPC_BLEND_BUSY, int) + GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int) + GENERATE_FIELD(TPC_RR_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_BUSY, int) + GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_WALKER_BUSY, int) + GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int) + GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int) + GENERATE_FIELD(TPC_TC_FIFO_BUSY, int) + GENERATE_FIELD(TPC_INPUT_BUSY, int) +END_REGISTER(TPC_CNTL_STATUS) + +START_REGISTER(TPC_DEBUG0) + GENERATE_FIELD(SQ_TP_WAKEUP, int) + GENERATE_FIELD(TPC_CLK_EN, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(ALIGNER_STATE, int) + GENERATE_FIELD(WALKER_STATE, int) + GENERATE_FIELD(PREV_TC_STATE_VALID, int) + GENERATE_FIELD(ALIGNER_CNTL, int) + GENERATE_FIELD(WALKER_CNTL, int) + GENERATE_FIELD(IC_CTR, int) + GENERATE_FIELD(LOD_CNTL, int) +END_REGISTER(TPC_DEBUG0) + +START_REGISTER(TPC_DEBUG1) + GENERATE_FIELD(UNUSED, int) +END_REGISTER(TPC_DEBUG1) + +START_REGISTER(TPC_CHICKEN) + GENERATE_FIELD(SPARE, int) + GENERATE_FIELD(BLEND_PRECISION, int) +END_REGISTER(TPC_CHICKEN) + +START_REGISTER(TP0_CNTL_STATUS) + GENERATE_FIELD(TP_BUSY, int) + GENERATE_FIELD(TB_TO_RTS, int) + GENERATE_FIELD(TB_TT_TT_RESET, int) + GENERATE_FIELD(TB_TT_RTS, int) + GENERATE_FIELD(TF_TB_TT_RTS, int) + GENERATE_FIELD(TF_TB_RTS, int) + GENERATE_FIELD(AL_TF_TT_RTS, int) + GENERATE_FIELD(AL_TF_RTS, int) + GENERATE_FIELD(FA_AL_TT_RTS, int) + GENERATE_FIELD(FA_AL_RTS, int) + GENERATE_FIELD(TA_FA_TT_RTS, int) + GENERATE_FIELD(TA_FA_RTS, int) + GENERATE_FIELD(FL_TA_RTS, int) + GENERATE_FIELD(LA_FL_RTS, int) + GENERATE_FIELD(LC_LA_RTS, int) + GENERATE_FIELD(IN_LC_RTS, int) + GENERATE_FIELD(TP_OUTPUT_BUSY, int) + GENERATE_FIELD(TP_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TP_BLEND_BUSY, int) + GENERATE_FIELD(TP_HICOLOR_BUSY, int) + GENERATE_FIELD(TP_TT_BUSY, int) + GENERATE_FIELD(TP_CH_BLEND_BUSY, int) + GENERATE_FIELD(TP_FETCH_BUSY, int) + GENERATE_FIELD(TP_RR_FIFO_BUSY, int) + GENERATE_FIELD(TP_TC_FIFO_BUSY, int) + GENERATE_FIELD(TP_ALIGNER_BUSY, int) + GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TP_ADDR_BUSY, int) + GENERATE_FIELD(TP_LOD_FIFO_BUSY, int) + GENERATE_FIELD(TP_LOD_BUSY, int) + GENERATE_FIELD(TP_INPUT_BUSY, int) +END_REGISTER(TP0_CNTL_STATUS) + +START_REGISTER(TP0_DEBUG) + GENERATE_FIELD(Q_ALIGNER_CNTL, int) + GENERATE_FIELD(Q_WALKER_CNTL, int) + GENERATE_FIELD(TP_CLK_EN, int) + GENERATE_FIELD(PERF_CLK_EN, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int) + GENERATE_FIELD(Q_SQ_TP_WAKEUP, int) + GENERATE_FIELD(Q_LOD_CNTL, int) +END_REGISTER(TP0_DEBUG) + +START_REGISTER(TP0_CHICKEN) + GENERATE_FIELD(SPARE, int) + GENERATE_FIELD(VFETCH_ADDRESS_MODE, int) + GENERATE_FIELD(TT_MODE, int) +END_REGISTER(TP0_CHICKEN) + +START_REGISTER(TP0_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT) +END_REGISTER(TP0_PERFCOUNTER0_SELECT) + +START_REGISTER(TP0_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER0_HI) + +START_REGISTER(TP0_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER0_LOW) + +START_REGISTER(TP0_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, int) +END_REGISTER(TP0_PERFCOUNTER1_SELECT) + +START_REGISTER(TP0_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER1_HI) + +START_REGISTER(TP0_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER1_LOW) + +START_REGISTER(TCM_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER0_SELECT) + +START_REGISTER(TCM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER1_SELECT) + +START_REGISTER(TCM_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER0_HI) + +START_REGISTER(TCM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER1_HI) + +START_REGISTER(TCM_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER0_LOW) + +START_REGISTER(TCM_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER0_SELECT) + +START_REGISTER(TCF_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER1_SELECT) + +START_REGISTER(TCF_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER2_SELECT) + +START_REGISTER(TCF_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER3_SELECT) + +START_REGISTER(TCF_PERFCOUNTER4_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER4_SELECT) + +START_REGISTER(TCF_PERFCOUNTER5_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER5_SELECT) + +START_REGISTER(TCF_PERFCOUNTER6_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER6_SELECT) + +START_REGISTER(TCF_PERFCOUNTER7_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER7_SELECT) + +START_REGISTER(TCF_PERFCOUNTER8_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER8_SELECT) + +START_REGISTER(TCF_PERFCOUNTER9_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER9_SELECT) + +START_REGISTER(TCF_PERFCOUNTER10_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER10_SELECT) + +START_REGISTER(TCF_PERFCOUNTER11_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER11_SELECT) + +START_REGISTER(TCF_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER0_HI) + +START_REGISTER(TCF_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER1_HI) + +START_REGISTER(TCF_PERFCOUNTER2_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER2_HI) + +START_REGISTER(TCF_PERFCOUNTER3_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER3_HI) + +START_REGISTER(TCF_PERFCOUNTER4_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER4_HI) + +START_REGISTER(TCF_PERFCOUNTER5_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER5_HI) + +START_REGISTER(TCF_PERFCOUNTER6_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER6_HI) + +START_REGISTER(TCF_PERFCOUNTER7_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER7_HI) + +START_REGISTER(TCF_PERFCOUNTER8_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER8_HI) + +START_REGISTER(TCF_PERFCOUNTER9_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER9_HI) + +START_REGISTER(TCF_PERFCOUNTER10_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER10_HI) + +START_REGISTER(TCF_PERFCOUNTER11_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER11_HI) + +START_REGISTER(TCF_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER0_LOW) + +START_REGISTER(TCF_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER2_LOW) + +START_REGISTER(TCF_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER3_LOW) + +START_REGISTER(TCF_PERFCOUNTER4_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER4_LOW) + +START_REGISTER(TCF_PERFCOUNTER5_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER5_LOW) + +START_REGISTER(TCF_PERFCOUNTER6_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER6_LOW) + +START_REGISTER(TCF_PERFCOUNTER7_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER7_LOW) + +START_REGISTER(TCF_PERFCOUNTER8_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER8_LOW) + +START_REGISTER(TCF_PERFCOUNTER9_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER9_LOW) + +START_REGISTER(TCF_PERFCOUNTER10_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER10_LOW) + +START_REGISTER(TCF_PERFCOUNTER11_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER11_LOW) + +START_REGISTER(TCF_DEBUG) + GENERATE_FIELD(tca_rts, int) + GENERATE_FIELD(tca_state_rts, int) + GENERATE_FIELD(not_TPC_rtr, int) + GENERATE_FIELD(TPC_full, int) + GENERATE_FIELD(TP0_full, int) + GENERATE_FIELD(PF0_stall, int) + GENERATE_FIELD(TCA_TCB_stall, int) + GENERATE_FIELD(TCB_miss_stall, int) + GENERATE_FIELD(TCB_ff_stall, int) + GENERATE_FIELD(not_TCB_TCO_rtr, int) + GENERATE_FIELD(not_FG0_rtr, int) + GENERATE_FIELD(TC_MH_send, int) + GENERATE_FIELD(not_MH_TC_rtr, int) +END_REGISTER(TCF_DEBUG) + +START_REGISTER(TCA_FIFO_DEBUG) + GENERATE_FIELD(FW_tpc_rts, int) + GENERATE_FIELD(not_FW_tpc_rtr, int) + GENERATE_FIELD(FW_rts0, int) + GENERATE_FIELD(not_FW_rtr0, int) + GENERATE_FIELD(FW_full, int) + GENERATE_FIELD(load_tp_fifos, int) + GENERATE_FIELD(load_tpc_fifo, int) + GENERATE_FIELD(tpc_full, int) + GENERATE_FIELD(tp0_full, int) +END_REGISTER(TCA_FIFO_DEBUG) + +START_REGISTER(TCA_PROBE_DEBUG) + GENERATE_FIELD(ProbeFilter_stall, int) +END_REGISTER(TCA_PROBE_DEBUG) + +START_REGISTER(TCA_TPC_DEBUG) + GENERATE_FIELD(capture_tca_rts, int) + GENERATE_FIELD(captue_state_rts, int) +END_REGISTER(TCA_TPC_DEBUG) + +START_REGISTER(TCB_CORE_DEBUG) + GENERATE_FIELD(sector_format512, int) + GENERATE_FIELD(sector_format, int) + GENERATE_FIELD(format, int) + GENERATE_FIELD(opcode, int) + GENERATE_FIELD(tiled, int) + GENERATE_FIELD(access512, int) +END_REGISTER(TCB_CORE_DEBUG) + +START_REGISTER(TCB_TAG0_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG0_DEBUG) + +START_REGISTER(TCB_TAG1_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG1_DEBUG) + +START_REGISTER(TCB_TAG2_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG2_DEBUG) + +START_REGISTER(TCB_TAG3_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG3_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + GENERATE_FIELD(valid_left_q, int) + GENERATE_FIELD(sector_mask_left_q, int) + GENERATE_FIELD(sector_mask_left_count_q, int) + GENERATE_FIELD(update_left, int) + GENERATE_FIELD(no_sectors_to_go, int) + GENERATE_FIELD(one_sector_to_go_left_q, int) + GENERATE_FIELD(fg0_sends_left, int) + GENERATE_FIELD(left_done, int) +END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + GENERATE_FIELD(setquads_to_send, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(ff_fg_type512, int) + GENERATE_FIELD(right_eq_left, int) + GENERATE_FIELD(set_sel_left, int) + GENERATE_FIELD(quad_sel_left, int) +END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + GENERATE_FIELD(arb_RTR, int) + GENERATE_FIELD(valid_q, int) + GENERATE_FIELD(mc_sel_q, int) + GENERATE_FIELD(ga_busy, int) + GENERATE_FIELD(fgo_busy, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(tc_arb_request_type, int) + GENERATE_FIELD(tc_arb_fmsopcode, int) + GENERATE_FIELD(tc_arb_format, int) + GENERATE_FIELD(ga_out_rts, int) + GENERATE_FIELD(tc0_arb_rts, int) +END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + +START_REGISTER(TCD_INPUT0_DEBUG) + GENERATE_FIELD(ipbuf_busy, int) + GENERATE_FIELD(ipbuf_dxt_send, int) + GENERATE_FIELD(ip_send, int) + GENERATE_FIELD(last_send_q1, int) + GENERATE_FIELD(cnt_q1, int) + GENERATE_FIELD(valid_q1, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(empty, int) +END_REGISTER(TCD_INPUT0_DEBUG) + +START_REGISTER(TCD_DEGAMMA_DEBUG) + GENERATE_FIELD(dgmm_pstate, int) + GENERATE_FIELD(dgmm_stall, int) + GENERATE_FIELD(dgmm_ctrl_send, int) + GENERATE_FIELD(dgmm_ctrl_last_send, int) + GENERATE_FIELD(dgmm_ctrl_dgmm8, int) + GENERATE_FIELD(dgmm_ftfconv_dgmmen, int) +END_REGISTER(TCD_DEGAMMA_DEBUG) + +START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + GENERATE_FIELD(dcmp_mux_send, int) + GENERATE_FIELD(dxtc_dgmmpd_send, int) + GENERATE_FIELD(dxtc_dgmmpd_last_send, int) + GENERATE_FIELD(dxtc_sctrarb_send, int) + GENERATE_FIELD(sctrmx0_sctrarb_rts, int) + GENERATE_FIELD(sctrarb_multcyl_send, int) + GENERATE_FIELD(dxtc_rtr, int) + GENERATE_FIELD(sctrmx_rtr, int) + GENERATE_FIELD(pstate, int) +END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + +START_REGISTER(TCD_DXTC_ARB_DEBUG) + GENERATE_FIELD(n0_dxt2_4_types, int) + GENERATE_FIELD(arb_dcmp01_send, int) + GENERATE_FIELD(arb_dcmp01_format, int) + GENERATE_FIELD(arb_dcmp01_cacheline, int) + GENERATE_FIELD(arb_dcmp01_sector, int) + GENERATE_FIELD(arb_dcmp01_cnt, int) + GENERATE_FIELD(arb_dcmp01_last_send, int) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(n0_stall, int) +END_REGISTER(TCD_DXTC_ARB_DEBUG) + +START_REGISTER(TCD_STALLS_DEBUG) + GENERATE_FIELD(not_incoming_rtr, int) + GENERATE_FIELD(not_mux_dcmp_rtr, int) + GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int) + GENERATE_FIELD(not_dcmp0_arb_rtr, int) + GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int) + GENERATE_FIELD(not_multcyl_sctrarb_rtr, int) +END_REGISTER(TCD_STALLS_DEBUG) + +START_REGISTER(TCO_STALLS_DEBUG) + GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int) + GENERATE_FIELD(quad0_rl_sg_RTR, int) + GENERATE_FIELD(quad0_sg_crd_RTR, int) +END_REGISTER(TCO_STALLS_DEBUG) + +START_REGISTER(TCO_QUAD0_DEBUG0) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(all_sectors_written_set0, int) + GENERATE_FIELD(all_sectors_written_set1, int) + GENERATE_FIELD(all_sectors_written_set2, int) + GENERATE_FIELD(all_sectors_written_set3, int) + GENERATE_FIELD(cache_read_RTR, int) + GENERATE_FIELD(read_cache_q, int) + GENERATE_FIELD(stageN1_valid_q, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_end_of_sample, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_end_of_sample, int) + GENERATE_FIELD(rl_sg_sector_format, int) +END_REGISTER(TCO_QUAD0_DEBUG0) + +START_REGISTER(TCO_QUAD0_DEBUG1) + GENERATE_FIELD(TCO_TCB_read_xfc, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(TCB_TCO_xfc_q, int) + GENERATE_FIELD(TCB_TCO_rtr_d, int) + GENERATE_FIELD(tco_quad_pipe_busy, int) + GENERATE_FIELD(input_quad_busy, int) + GENERATE_FIELD(latency_fifo_busy, int) + GENERATE_FIELD(cache_read_busy, int) + GENERATE_FIELD(fifo_read_ptr, int) + GENERATE_FIELD(fifo_write_ptr, int) + GENERATE_FIELD(write_enable, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(fifo_busy, int) +END_REGISTER(TCO_QUAD0_DEBUG1) + +START_REGISTER(SQ_GPR_MANAGEMENT) + GENERATE_FIELD(REG_SIZE_VTX, int) + GENERATE_FIELD(REG_SIZE_PIX, int) + GENERATE_FIELD(REG_DYNAMIC, int) +END_REGISTER(SQ_GPR_MANAGEMENT) + +START_REGISTER(SQ_FLOW_CONTROL) + GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int) + GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int) + GENERATE_FIELD(POS_EXP_PRIORITY, int) + GENERATE_FIELD(NO_CFS_EJECT, int) + GENERATE_FIELD(NO_ARB_EJECT, int) + GENERATE_FIELD(ALU_ARBITRATION_POLICY, int) + GENERATE_FIELD(VC_ARBITRATION_POLICY, int) + GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int) + GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int) + GENERATE_FIELD(NO_LOOP_EXIT, int) + GENERATE_FIELD(NO_PV_PS, int) + GENERATE_FIELD(CF_WR_BASE, hex) + GENERATE_FIELD(ONE_ALU, int) + GENERATE_FIELD(ONE_THREAD, int) + GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int) +END_REGISTER(SQ_FLOW_CONTROL) + +START_REGISTER(SQ_INST_STORE_MANAGMENT) + GENERATE_FIELD(INST_BASE_VTX, int) + GENERATE_FIELD(INST_BASE_PIX, int) +END_REGISTER(SQ_INST_STORE_MANAGMENT) + +START_REGISTER(SQ_RESOURCE_MANAGMENT) + GENERATE_FIELD(EXPORT_BUF_ENTRIES, int) + GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int) +END_REGISTER(SQ_RESOURCE_MANAGMENT) + +START_REGISTER(SQ_EO_RT) + GENERATE_FIELD(EO_TSTATE_RT, int) + GENERATE_FIELD(EO_CONSTANTS_RT, int) +END_REGISTER(SQ_EO_RT) + +START_REGISTER(SQ_DEBUG_MISC) + GENERATE_FIELD(DB_WEN_MEMORY_3, int) + GENERATE_FIELD(DB_WEN_MEMORY_2, int) + GENERATE_FIELD(DB_WEN_MEMORY_1, int) + GENERATE_FIELD(DB_WEN_MEMORY_0, int) + GENERATE_FIELD(DB_READ_MEMORY, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DB_READ_CTX, int) + GENERATE_FIELD(DB_TSTATE_SIZE, int) + GENERATE_FIELD(DB_ALUCST_SIZE, int) +END_REGISTER(SQ_DEBUG_MISC) + +START_REGISTER(SQ_ACTIVITY_METER_CNTL) + GENERATE_FIELD(SPARE, int) + GENERATE_FIELD(THRESHOLD_HIGH, int) + GENERATE_FIELD(THRESHOLD_LOW, int) + GENERATE_FIELD(TIMEBASE, int) +END_REGISTER(SQ_ACTIVITY_METER_CNTL) + +START_REGISTER(SQ_ACTIVITY_METER_STATUS) + GENERATE_FIELD(PERCENT_BUSY, int) +END_REGISTER(SQ_ACTIVITY_METER_STATUS) + +START_REGISTER(SQ_INPUT_ARB_PRIORITY) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) +END_REGISTER(SQ_INPUT_ARB_PRIORITY) + +START_REGISTER(SQ_THREAD_ARB_PRIORITY) + GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int) + GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) +END_REGISTER(SQ_THREAD_ARB_PRIORITY) + +START_REGISTER(SQ_VS_WATCHDOG_TIMER) + GENERATE_FIELD(TIMEOUT_COUNT, int) + GENERATE_FIELD(ENABLE, int) +END_REGISTER(SQ_VS_WATCHDOG_TIMER) + +START_REGISTER(SQ_PS_WATCHDOG_TIMER) + GENERATE_FIELD(TIMEOUT_COUNT, int) + GENERATE_FIELD(ENABLE, int) +END_REGISTER(SQ_PS_WATCHDOG_TIMER) + +START_REGISTER(SQ_INT_CNTL) + GENERATE_FIELD(VS_WATCHDOG_MASK, int) + GENERATE_FIELD(PS_WATCHDOG_MASK, int) +END_REGISTER(SQ_INT_CNTL) + +START_REGISTER(SQ_INT_STATUS) + GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int) + GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int) +END_REGISTER(SQ_INT_STATUS) + +START_REGISTER(SQ_INT_ACK) + GENERATE_FIELD(VS_WATCHDOG_ACK, int) + GENERATE_FIELD(PS_WATCHDOG_ACK, int) +END_REGISTER(SQ_INT_ACK) + +START_REGISTER(SQ_DEBUG_INPUT_FSM) + GENERATE_FIELD(PC_GPR_SIZE, int) + GENERATE_FIELD(PC_INTERP_CNT, int) + GENERATE_FIELD(PC_AS, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PC_PISM, int) + GENERATE_FIELD(VC_GPR_LD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VC_VSR_LD, int) +END_REGISTER(SQ_DEBUG_INPUT_FSM) + +START_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int) + GENERATE_FIELD(TEX_CONST_CNTX_VALID, int) + GENERATE_FIELD(ALU_CONST_CNTX_VALID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(ALU_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(TEX_CONST_EVENT_STATE, int) +END_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + +START_REGISTER(SQ_DEBUG_TP_FSM) + GENERATE_FIELD(ARB_TR_TP, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(FCS_TP, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(FCR_TP, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(GS_TP, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(TIS_TP, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(IF_TP, int) + GENERATE_FIELD(CF_TP, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(EX_TP, int) +END_REGISTER(SQ_DEBUG_TP_FSM) + +START_REGISTER(SQ_DEBUG_FSM_ALU_0) + GENERATE_FIELD(ARB_TR_ALU, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(EX_ALU_0, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_0) + +START_REGISTER(SQ_DEBUG_FSM_ALU_1) + GENERATE_FIELD(ARB_TR_ALU, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(EX_ALU_0, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_1) + +START_REGISTER(SQ_DEBUG_EXP_ALLOC) + GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(EA_BUF_AVAIL, int) + GENERATE_FIELD(COLOR_BUF_AVAIL, int) + GENERATE_FIELD(POS_BUF_AVAIL, int) +END_REGISTER(SQ_DEBUG_EXP_ALLOC) + +START_REGISTER(SQ_DEBUG_PTR_BUFF) + GENERATE_FIELD(VTX_SYNC_CNT, int) + GENERATE_FIELD(EF_EMPTY, int) + GENERATE_FIELD(PRIM_TYPE_POLYGON, int) + GENERATE_FIELD(QUAL_EVENT, int) + GENERATE_FIELD(SC_EVENT_ID, int) + GENERATE_FIELD(EVENT_CONTEXT_ID, int) + GENERATE_FIELD(QUAL_NEW_VECTOR, int) + GENERATE_FIELD(DEALLOC_CNT, int) + GENERATE_FIELD(END_OF_BUFFER, int) +END_REGISTER(SQ_DEBUG_PTR_BUFF) + +START_REGISTER(SQ_DEBUG_GPR_VTX) + GENERATE_FIELD(VTX_FREE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(VTX_MAX, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(VTX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VTX_TAIL_PTR, int) +END_REGISTER(SQ_DEBUG_GPR_VTX) + +START_REGISTER(SQ_DEBUG_GPR_PIX) + GENERATE_FIELD(PIX_FREE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(PIX_MAX, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(PIX_TAIL_PTR, int) +END_REGISTER(SQ_DEBUG_GPR_PIX) + +START_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int) + GENERATE_FIELD(VC_THREAD_BUF_DLY, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int) +END_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + +START_REGISTER(SQ_DEBUG_VTX_TB_0) + GENERATE_FIELD(BUSY_Q, int) + GENERATE_FIELD(SX_EVENT_FULL, int) + GENERATE_FIELD(NXT_PC_ALLOC_CNT, int) + GENERATE_FIELD(NXT_POS_ALLOC_CNT, int) + GENERATE_FIELD(FULL_CNT_Q, int) + GENERATE_FIELD(TAIL_PTR_Q, int) + GENERATE_FIELD(VTX_HEAD_PTR_Q, int) +END_REGISTER(SQ_DEBUG_VTX_TB_0) + +START_REGISTER(SQ_DEBUG_VTX_TB_1) + GENERATE_FIELD(VS_DONE_PTR, int) +END_REGISTER(SQ_DEBUG_VTX_TB_1) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + GENERATE_FIELD(VS_STATUS_REG, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + GENERATE_FIELD(VS_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + +START_REGISTER(SQ_DEBUG_PIX_TB_0) + GENERATE_FIELD(BUSY, int) + GENERATE_FIELD(NXT_PIX_EXP_CNT, int) + GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int) + GENERATE_FIELD(FULL_CNT, int) + GENERATE_FIELD(TAIL_PTR, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) +END_REGISTER(SQ_DEBUG_PIX_TB_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + GENERATE_FIELD(PIX_TB_STATUS_REG_0, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + GENERATE_FIELD(PIX_TB_STATUS_REG_1, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + GENERATE_FIELD(PIX_TB_STATUS_REG_2, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + GENERATE_FIELD(PIX_TB_STATUS_REG_3, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + GENERATE_FIELD(PIX_TB_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + +START_REGISTER(SQ_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT) +END_REGISTER(SQ_PERFCOUNTER0_SELECT) + +START_REGISTER(SQ_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER1_SELECT) + +START_REGISTER(SQ_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER2_SELECT) + +START_REGISTER(SQ_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER3_SELECT) + +START_REGISTER(SQ_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_LOW) + +START_REGISTER(SQ_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_HI) + +START_REGISTER(SQ_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_LOW) + +START_REGISTER(SQ_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_HI) + +START_REGISTER(SQ_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_LOW) + +START_REGISTER(SQ_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_HI) + +START_REGISTER(SQ_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_LOW) + +START_REGISTER(SQ_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_HI) + +START_REGISTER(SX_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT) +END_REGISTER(SX_PERFCOUNTER0_SELECT) + +START_REGISTER(SX_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_LOW) + +START_REGISTER(SX_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_HI) + +START_REGISTER(SQ_INSTRUCTION_ALU_0) + GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode) + GENERATE_FIELD(SCALAR_CLAMP, int) + GENERATE_FIELD(VECTOR_CLAMP, int) + GENERATE_FIELD(SCALAR_WRT_MSK, int) + GENERATE_FIELD(VECTOR_WRT_MSK, int) + GENERATE_FIELD(EXPORT_DATA, Exporting) + GENERATE_FIELD(SCALAR_DST_REL, int) + GENERATE_FIELD(SCALAR_RESULT, int) + GENERATE_FIELD(LOW_PRECISION_16B_FP, int) + GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier) + GENERATE_FIELD(VECTOR_RESULT, int) +END_REGISTER(SQ_INSTRUCTION_ALU_0) + +START_REGISTER(SQ_INSTRUCTION_ALU_1) + GENERATE_FIELD(CONST_0_REL_ABS, int) + GENERATE_FIELD(CONST_1_REL_ABS, int) + GENERATE_FIELD(RELATIVE_ADDR, int) + GENERATE_FIELD(PRED_SELECT, PredicateSelect) + GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType) +END_REGISTER(SQ_INSTRUCTION_ALU_1) + +START_REGISTER(SQ_INSTRUCTION_ALU_2) + GENERATE_FIELD(SRC_A_SEL, OperandSelect0) + GENERATE_FIELD(SRC_B_SEL, OperandSelect0) + GENERATE_FIELD(SRC_C_SEL, OperandSelect0) + GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode) + GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier) + GENERATE_FIELD(REG_SELECT_A, OperandSelect1) + GENERATE_FIELD(SRC_A_REG_PTR, int) + GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier) + GENERATE_FIELD(REG_SELECT_B, OperandSelect1) + GENERATE_FIELD(SRC_B_REG_PTR, int) + GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier) + GENERATE_FIELD(REG_SELECT_C, OperandSelect1) + GENERATE_FIELD(SRC_C_REG_PTR, int) +END_REGISTER(SQ_INSTRUCTION_ALU_2) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS, int) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(RESERVED_0, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(LOOP_ID, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(PREDICATED_JMP, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + GENERATE_FIELD(RESERVED_2, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(RESERVED_0, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(RESERVED_0, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_0) + GENERATE_FIELD(SRC_SEL_Z, SrcSel) + GENERATE_FIELD(SRC_SEL_Y, SrcSel) + GENERATE_FIELD(SRC_SEL_X, SrcSel) + GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(FETCH_VALID_ONLY, int) + GENERATE_FIELD(DST_GPR_AM, Addressmode) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, Addressmode) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(OPCODE, TexInstOpcode) +END_REGISTER(SQ_INSTRUCTION_TFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_1) + GENERATE_FIELD(PRED_SELECT, PredSelect) + GENERATE_FIELD(USE_REG_LOD, int) + GENERATE_FIELD(USE_COMP_LOD, int) + GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter) + GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter) + GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter) + GENERATE_FIELD(ANISO_FILTER, AnisoFilter) + GENERATE_FIELD(MIP_FILTER, MipFilter) + GENERATE_FIELD(MIN_FILTER, MinFilter) + GENERATE_FIELD(MAG_FILTER, MagFilter) + GENERATE_FIELD(DST_SEL_W, DstSel) + GENERATE_FIELD(DST_SEL_Z, DstSel) + GENERATE_FIELD(DST_SEL_Y, DstSel) + GENERATE_FIELD(DST_SEL_X, DstSel) +END_REGISTER(SQ_INSTRUCTION_TFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_2) + GENERATE_FIELD(PRED_CONDITION, int) + GENERATE_FIELD(OFFSET_Z, int) + GENERATE_FIELD(OFFSET_Y, int) + GENERATE_FIELD(OFFSET_X, int) + GENERATE_FIELD(UNUSED, int) + GENERATE_FIELD(LOD_BIAS, int) + GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation) + GENERATE_FIELD(USE_REG_GRADIENTS, int) +END_REGISTER(SQ_INSTRUCTION_TFETCH_2) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_0) + GENERATE_FIELD(SRC_SEL, int) + GENERATE_FIELD(CONST_INDEX_SEL, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(MUST_BE_ONE, int) + GENERATE_FIELD(DST_GPR_AM, int) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, int) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(OPCODE, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_1) + GENERATE_FIELD(PRED_SELECT, int) + GENERATE_FIELD(EXP_ADJUST_ALL, int) + GENERATE_FIELD(DATA_FORMAT, int) + GENERATE_FIELD(SIGNED_RF_MODE_ALL, int) + GENERATE_FIELD(NUM_FORMAT_ALL, int) + GENERATE_FIELD(FORMAT_COMP_ALL, int) + GENERATE_FIELD(DST_SEL_W, int) + GENERATE_FIELD(DST_SEL_Z, int) + GENERATE_FIELD(DST_SEL_Y, int) + GENERATE_FIELD(DST_SEL_X, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_2) + GENERATE_FIELD(PRED_CONDITION, int) + GENERATE_FIELD(OFFSET, int) + GENERATE_FIELD(STRIDE, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_2) + +START_REGISTER(SQ_CONSTANT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_0) + +START_REGISTER(SQ_CONSTANT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_1) + +START_REGISTER(SQ_CONSTANT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_2) + +START_REGISTER(SQ_CONSTANT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_3) + +START_REGISTER(SQ_FETCH_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_0) + +START_REGISTER(SQ_FETCH_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_1) + +START_REGISTER(SQ_FETCH_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_2) + +START_REGISTER(SQ_FETCH_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_3) + +START_REGISTER(SQ_FETCH_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_4) + +START_REGISTER(SQ_FETCH_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_5) + +START_REGISTER(SQ_CONSTANT_VFETCH_0) + GENERATE_FIELD(BASE_ADDRESS, hex) + GENERATE_FIELD(STATE, int) + GENERATE_FIELD(TYPE, int) +END_REGISTER(SQ_CONSTANT_VFETCH_0) + +START_REGISTER(SQ_CONSTANT_VFETCH_1) + GENERATE_FIELD(LIMIT_ADDRESS, hex) + GENERATE_FIELD(ENDIAN_SWAP, int) +END_REGISTER(SQ_CONSTANT_VFETCH_1) + +START_REGISTER(SQ_CONSTANT_T2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T2) + +START_REGISTER(SQ_CONSTANT_T3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T3) + +START_REGISTER(SQ_CF_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_3, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_0, int) +END_REGISTER(SQ_CF_BOOLEANS) + +START_REGISTER(SQ_CF_LOOP) + GENERATE_FIELD(CF_LOOP_STEP, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_COUNT, int) +END_REGISTER(SQ_CF_LOOP) + +START_REGISTER(SQ_CONSTANT_RT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_RT_0) + +START_REGISTER(SQ_CONSTANT_RT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_RT_1) + +START_REGISTER(SQ_CONSTANT_RT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_RT_2) + +START_REGISTER(SQ_CONSTANT_RT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_RT_3) + +START_REGISTER(SQ_FETCH_RT_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_0) + +START_REGISTER(SQ_FETCH_RT_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_1) + +START_REGISTER(SQ_FETCH_RT_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_2) + +START_REGISTER(SQ_FETCH_RT_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_3) + +START_REGISTER(SQ_FETCH_RT_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_4) + +START_REGISTER(SQ_FETCH_RT_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_5) + +START_REGISTER(SQ_CF_RT_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_3, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_0, int) +END_REGISTER(SQ_CF_RT_BOOLEANS) + +START_REGISTER(SQ_CF_RT_LOOP) + GENERATE_FIELD(CF_LOOP_STEP, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_COUNT, int) +END_REGISTER(SQ_CF_RT_LOOP) + +START_REGISTER(SQ_VS_PROGRAM) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_VS_PROGRAM) + +START_REGISTER(SQ_PS_PROGRAM) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_PS_PROGRAM) + +START_REGISTER(SQ_CF_PROGRAM_SIZE) + GENERATE_FIELD(PS_CF_SIZE, int) + GENERATE_FIELD(VS_CF_SIZE, int) +END_REGISTER(SQ_CF_PROGRAM_SIZE) + +START_REGISTER(SQ_INTERPOLATOR_CNTL) + GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern) + GENERATE_FIELD(PARAM_SHADE, ParamShade) +END_REGISTER(SQ_INTERPOLATOR_CNTL) + +START_REGISTER(SQ_PROGRAM_CNTL) + GENERATE_FIELD(GEN_INDEX_VTX, int) + GENERATE_FIELD(PS_EXPORT_MODE, int) + GENERATE_FIELD(VS_EXPORT_MODE, VertexMode) + GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne) + GENERATE_FIELD(GEN_INDEX_PIX, int) + GENERATE_FIELD(PARAM_GEN, int) + GENERATE_FIELD(PS_RESOURCE, int) + GENERATE_FIELD(VS_RESOURCE, int) + GENERATE_FIELD(PS_NUM_REG, intMinusOne) + GENERATE_FIELD(VS_NUM_REG, intMinusOne) +END_REGISTER(SQ_PROGRAM_CNTL) + +START_REGISTER(SQ_WRAPPING_0) + GENERATE_FIELD(PARAM_WRAP_7, hex) + GENERATE_FIELD(PARAM_WRAP_6, hex) + GENERATE_FIELD(PARAM_WRAP_5, hex) + GENERATE_FIELD(PARAM_WRAP_4, hex) + GENERATE_FIELD(PARAM_WRAP_3, hex) + GENERATE_FIELD(PARAM_WRAP_2, hex) + GENERATE_FIELD(PARAM_WRAP_1, hex) + GENERATE_FIELD(PARAM_WRAP_0, hex) +END_REGISTER(SQ_WRAPPING_0) + +START_REGISTER(SQ_WRAPPING_1) + GENERATE_FIELD(PARAM_WRAP_15, hex) + GENERATE_FIELD(PARAM_WRAP_14, hex) + GENERATE_FIELD(PARAM_WRAP_13, hex) + GENERATE_FIELD(PARAM_WRAP_12, hex) + GENERATE_FIELD(PARAM_WRAP_11, hex) + GENERATE_FIELD(PARAM_WRAP_10, hex) + GENERATE_FIELD(PARAM_WRAP_9, hex) + GENERATE_FIELD(PARAM_WRAP_8, hex) +END_REGISTER(SQ_WRAPPING_1) + +START_REGISTER(SQ_VS_CONST) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_VS_CONST) + +START_REGISTER(SQ_PS_CONST) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_PS_CONST) + +START_REGISTER(SQ_CONTEXT_MISC) + GENERATE_FIELD(TX_CACHE_SEL, int) + GENERATE_FIELD(YEILD_OPTIMIZE, int) + GENERATE_FIELD(PERFCOUNTER_REF, int) + GENERATE_FIELD(PARAM_GEN_POS, int) + GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl) + GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int) + GENERATE_FIELD(INST_PRED_OPTIMIZE, int) +END_REGISTER(SQ_CONTEXT_MISC) + +START_REGISTER(SQ_CF_RD_BASE) + GENERATE_FIELD(RD_BASE, hex) +END_REGISTER(SQ_CF_RD_BASE) + +START_REGISTER(SQ_DEBUG_MISC_0) + GENERATE_FIELD(DB_PROB_COUNT, int) + GENERATE_FIELD(DB_PROB_ADDR, int) + GENERATE_FIELD(DB_PROB_BREAK, int) + GENERATE_FIELD(DB_PROB_ON, int) +END_REGISTER(SQ_DEBUG_MISC_0) + +START_REGISTER(SQ_DEBUG_MISC_1) + GENERATE_FIELD(DB_BREAK_ADDR, int) + GENERATE_FIELD(DB_INST_COUNT, int) + GENERATE_FIELD(DB_ON_VTX, int) + GENERATE_FIELD(DB_ON_PIX, int) +END_REGISTER(SQ_DEBUG_MISC_1) + +START_REGISTER(MH_ARBITER_CONFIG) + GENERATE_FIELD(PA_CLNT_ENABLE, bool) + GENERATE_FIELD(RB_CLNT_ENABLE, bool) + GENERATE_FIELD(TC_CLNT_ENABLE, bool) + GENERATE_FIELD(VGT_CLNT_ENABLE, bool) + GENERATE_FIELD(CP_CLNT_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT, int) + GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool) + GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool) + GENERATE_FIELD(TC_REORDER_ENABLE, bool) + GENERATE_FIELD(PAGE_SIZE, int) + GENERATE_FIELD(L2_ARB_CONTROL, int) + GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int) + GENERATE_FIELD(L1_ARB_ENABLE, bool) + GENERATE_FIELD(SAME_PAGE_GRANULARITY, int) + GENERATE_FIELD(SAME_PAGE_LIMIT, int) +END_REGISTER(MH_ARBITER_CONFIG) + +START_REGISTER(MH_CLNT_AXI_ID_REUSE) + GENERATE_FIELD(PAw_ID, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(MMUr_ID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(RBw_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(CPw_ID, int) +END_REGISTER(MH_CLNT_AXI_ID_REUSE) + +START_REGISTER(MH_INTERRUPT_MASK) + GENERATE_FIELD(MMU_PAGE_FAULT, bool) + GENERATE_FIELD(AXI_WRITE_ERROR, bool) + GENERATE_FIELD(AXI_READ_ERROR, bool) +END_REGISTER(MH_INTERRUPT_MASK) + +START_REGISTER(MH_INTERRUPT_STATUS) + GENERATE_FIELD(MMU_PAGE_FAULT, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(AXI_READ_ERROR, int) +END_REGISTER(MH_INTERRUPT_STATUS) + +START_REGISTER(MH_INTERRUPT_CLEAR) + GENERATE_FIELD(MMU_PAGE_FAULT, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(AXI_READ_ERROR, int) +END_REGISTER(MH_INTERRUPT_CLEAR) + +START_REGISTER(MH_AXI_ERROR) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ID, int) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_READ_ID, int) +END_REGISTER(MH_AXI_ERROR) + +START_REGISTER(MH_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER0_SELECT) + +START_REGISTER(MH_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER1_SELECT) + +START_REGISTER(MH_PERFCOUNTER0_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER0_CONFIG) + +START_REGISTER(MH_PERFCOUNTER1_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER1_CONFIG) + +START_REGISTER(MH_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER0_LOW) + +START_REGISTER(MH_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER1_LOW) + +START_REGISTER(MH_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER0_HI) + +START_REGISTER(MH_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER1_HI) + +START_REGISTER(MH_DEBUG_CTRL) + GENERATE_FIELD(INDEX, int) +END_REGISTER(MH_DEBUG_CTRL) + +START_REGISTER(MH_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(MH_DEBUG_DATA) + +START_REGISTER(MH_AXI_HALT_CONTROL) + GENERATE_FIELD(AXI_HALT, bool) +END_REGISTER(MH_AXI_HALT_CONTROL) + +START_REGISTER(MH_MMU_CONFIG) + GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(SPLIT_MODE_ENABLE, bool) + GENERATE_FIELD(MMU_ENABLE, bool) +END_REGISTER(MH_MMU_CONFIG) + +START_REGISTER(MH_MMU_VA_RANGE) + GENERATE_FIELD(VA_BASE, int) + GENERATE_FIELD(NUM_64KB_REGIONS, int) +END_REGISTER(MH_MMU_VA_RANGE) + +START_REGISTER(MH_MMU_PT_BASE) + GENERATE_FIELD(PT_BASE, int) +END_REGISTER(MH_MMU_PT_BASE) + +START_REGISTER(MH_MMU_PAGE_FAULT) + GENERATE_FIELD(REQ_VA, int) + GENERATE_FIELD(WRITE_PROTECTION_ERROR, int) + GENERATE_FIELD(READ_PROTECTION_ERROR, int) + GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(AXI_ID, int) + GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(OP_TYPE, int) + GENERATE_FIELD(PAGE_FAULT, int) +END_REGISTER(MH_MMU_PAGE_FAULT) + +START_REGISTER(MH_MMU_TRAN_ERROR) + GENERATE_FIELD(TRAN_ERROR, int) +END_REGISTER(MH_MMU_TRAN_ERROR) + +START_REGISTER(MH_MMU_INVALIDATE) + GENERATE_FIELD(INVALIDATE_TC, int) + GENERATE_FIELD(INVALIDATE_ALL, int) +END_REGISTER(MH_MMU_INVALIDATE) + +START_REGISTER(MH_MMU_MPU_BASE) + GENERATE_FIELD(MPU_BASE, int) +END_REGISTER(MH_MMU_MPU_BASE) + +START_REGISTER(MH_MMU_MPU_END) + GENERATE_FIELD(MPU_END, int) +END_REGISTER(MH_MMU_MPU_END) + +START_REGISTER(WAIT_UNTIL) + GENERATE_FIELD(CMDFIFO_ENTRIES, int) + GENERATE_FIELD(WAIT_3D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_2D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_3D_IDLE, int) + GENERATE_FIELD(WAIT_2D_IDLE, int) + GENERATE_FIELD(WAIT_CMDFIFO, int) + GENERATE_FIELD(WAIT_DSPLY_ID2, int) + GENERATE_FIELD(WAIT_DSPLY_ID1, int) + GENERATE_FIELD(WAIT_DSPLY_ID0, int) + GENERATE_FIELD(WAIT_VSYNC, int) + GENERATE_FIELD(WAIT_FE_VSYNC, int) + GENERATE_FIELD(WAIT_RE_VSYNC, int) +END_REGISTER(WAIT_UNTIL) + +START_REGISTER(RBBM_ISYNC_CNTL) + GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int) + GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int) +END_REGISTER(RBBM_ISYNC_CNTL) + +START_REGISTER(RBBM_STATUS) + GENERATE_FIELD(GUI_ACTIVE, int) + GENERATE_FIELD(RB_CNTX_BUSY, int) + GENERATE_FIELD(SQ_CNTX0_BUSY, int) + GENERATE_FIELD(SQ_CNTX17_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(PA_BUSY, int) + GENERATE_FIELD(SC_CNTX_BUSY, int) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(SX_BUSY, int) + GENERATE_FIELD(MH_COHERENCY_BUSY, int) + GENERATE_FIELD(MH_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(RBBM_WU_BUSY, int) + GENERATE_FIELD(VGT_BUSY_NO_DMA, int) + GENERATE_FIELD(PFRQ_PENDING, int) + GENERATE_FIELD(CFRQ_PENDING, int) + GENERATE_FIELD(CPRQ_PENDING, int) + GENERATE_FIELD(HIRQ_PENDING, int) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(CMDFIFO_AVAIL, int) +END_REGISTER(RBBM_STATUS) + +START_REGISTER(RBBM_DSPLY) + GENERATE_FIELD(DMI_CH4_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH4_SW_CNTL, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH3_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH3_SW_CNTL, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID0, int) + GENERATE_FIELD(DMI_CHANNEL_SELECT, int) + GENERATE_FIELD(DMI_CH2_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH2_SW_CNTL, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH1_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH1_SW_CNTL, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID0, int) + GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int) +END_REGISTER(RBBM_DSPLY) + +START_REGISTER(RBBM_RENDER_LATEST) + GENERATE_FIELD(DMI_CH4_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH3_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH2_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH1_BUFFER_ID, int) +END_REGISTER(RBBM_RENDER_LATEST) + +START_REGISTER(RBBM_RTL_RELEASE) + GENERATE_FIELD(CHANGELIST, int) +END_REGISTER(RBBM_RTL_RELEASE) + +START_REGISTER(RBBM_PATCH_RELEASE) + GENERATE_FIELD(CUSTOMER_ID, int) + GENERATE_FIELD(PATCH_SELECTION, int) + GENERATE_FIELD(PATCH_REVISION, int) +END_REGISTER(RBBM_PATCH_RELEASE) + +START_REGISTER(RBBM_AUXILIARY_CONFIG) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(RBBM_AUXILIARY_CONFIG) + +START_REGISTER(RBBM_PERIPHID0) + GENERATE_FIELD(PARTNUMBER0, int) +END_REGISTER(RBBM_PERIPHID0) + +START_REGISTER(RBBM_PERIPHID1) + GENERATE_FIELD(DESIGNER0, int) + GENERATE_FIELD(PARTNUMBER1, int) +END_REGISTER(RBBM_PERIPHID1) + +START_REGISTER(RBBM_PERIPHID2) + GENERATE_FIELD(REVISION, int) + GENERATE_FIELD(DESIGNER1, int) +END_REGISTER(RBBM_PERIPHID2) + +START_REGISTER(RBBM_PERIPHID3) + GENERATE_FIELD(CONTINUATION, int) + GENERATE_FIELD(MH_INTERFACE, int) + GENERATE_FIELD(GARB_SLAVE_INTERFACE, int) + GENERATE_FIELD(RBBM_HOST_INTERFACE, int) +END_REGISTER(RBBM_PERIPHID3) + +START_REGISTER(RBBM_CNTL) + GENERATE_FIELD(REGCLK_DEASSERT_TIME, int) + GENERATE_FIELD(READ_TIMEOUT, int) +END_REGISTER(RBBM_CNTL) + +START_REGISTER(RBBM_SKEW_CNTL) + GENERATE_FIELD(SKEW_COUNT, int) + GENERATE_FIELD(SKEW_TOP_THRESHOLD, int) +END_REGISTER(RBBM_SKEW_CNTL) + +START_REGISTER(RBBM_SOFT_RESET) + GENERATE_FIELD(SOFT_RESET_VGT, int) + GENERATE_FIELD(SOFT_RESET_SC, int) + GENERATE_FIELD(SOFT_RESET_CIB, int) + GENERATE_FIELD(SOFT_RESET_SX, int) + GENERATE_FIELD(SOFT_RESET_SQ, int) + GENERATE_FIELD(SOFT_RESET_BC, int) + GENERATE_FIELD(SOFT_RESET_MH, int) + GENERATE_FIELD(SOFT_RESET_PA, int) + GENERATE_FIELD(SOFT_RESET_CP, int) +END_REGISTER(RBBM_SOFT_RESET) + +START_REGISTER(RBBM_PM_OVERRIDE1) + GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE1) + +START_REGISTER(RBBM_PM_OVERRIDE2) + GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int) + GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE2) + +START_REGISTER(GC_SYS_IDLE) + GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int) + GENERATE_FIELD(GC_SYS_IDLE_DELAY, int) +END_REGISTER(GC_SYS_IDLE) + +START_REGISTER(NQWAIT_UNTIL) + GENERATE_FIELD(WAIT_GUI_IDLE, int) +END_REGISTER(NQWAIT_UNTIL) + +START_REGISTER(RBBM_DEBUG_OUT) + GENERATE_FIELD(DEBUG_BUS_OUT, int) +END_REGISTER(RBBM_DEBUG_OUT) + +START_REGISTER(RBBM_DEBUG_CNTL) + GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int) + GENERATE_FIELD(SW_ENABLE, int) + GENERATE_FIELD(SUB_BLOCK_SEL, int) + GENERATE_FIELD(SUB_BLOCK_ADDR, int) +END_REGISTER(RBBM_DEBUG_CNTL) + +START_REGISTER(RBBM_DEBUG) + GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int) + GENERATE_FIELD(SQ_RBBM_NRTRTR, int) + GENERATE_FIELD(VGT_RBBM_NRTRTR, int) + GENERATE_FIELD(CP_RBBM_NRTRTR, int) + GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_RTR_FOR_HI, int) + GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int) + GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int) + GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int) + GENERATE_FIELD(IGNORE_CP_SCHED_WU, int) + GENERATE_FIELD(IGNORE_RTR, int) +END_REGISTER(RBBM_DEBUG) + +START_REGISTER(RBBM_READ_ERROR) + GENERATE_FIELD(READ_ERROR, int) + GENERATE_FIELD(READ_REQUESTER, int) + GENERATE_FIELD(READ_ADDRESS, int) +END_REGISTER(RBBM_READ_ERROR) + +START_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int) +END_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + +START_REGISTER(RBBM_INT_CNTL) + GENERATE_FIELD(GUI_IDLE_INT_MASK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int) + GENERATE_FIELD(RDERR_INT_MASK, int) +END_REGISTER(RBBM_INT_CNTL) + +START_REGISTER(RBBM_INT_STATUS) + GENERATE_FIELD(GUI_IDLE_INT_STAT, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int) + GENERATE_FIELD(RDERR_INT_STAT, int) +END_REGISTER(RBBM_INT_STATUS) + +START_REGISTER(RBBM_INT_ACK) + GENERATE_FIELD(GUI_IDLE_INT_ACK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int) + GENERATE_FIELD(RDERR_INT_ACK, int) +END_REGISTER(RBBM_INT_ACK) + +START_REGISTER(MASTER_INT_SIGNAL) + GENERATE_FIELD(RBBM_INT_STAT, int) + GENERATE_FIELD(CP_INT_STAT, int) + GENERATE_FIELD(SQ_INT_STAT, int) + GENERATE_FIELD(MH_INT_STAT, int) +END_REGISTER(MASTER_INT_SIGNAL) + +START_REGISTER(RBBM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL) +END_REGISTER(RBBM_PERFCOUNTER1_SELECT) + +START_REGISTER(RBBM_PERFCOUNTER1_LO) + GENERATE_FIELD(PERF_COUNT1_LO, int) +END_REGISTER(RBBM_PERFCOUNTER1_LO) + +START_REGISTER(RBBM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT1_HI, int) +END_REGISTER(RBBM_PERFCOUNTER1_HI) + +START_REGISTER(CP_RB_BASE) + GENERATE_FIELD(RB_BASE, int) +END_REGISTER(CP_RB_BASE) + +START_REGISTER(CP_RB_CNTL) + GENERATE_FIELD(RB_RPTR_WR_ENA, int) + GENERATE_FIELD(RB_NO_UPDATE, int) + GENERATE_FIELD(RB_POLL_EN, int) + GENERATE_FIELD(BUF_SWAP, int) + GENERATE_FIELD(RB_BLKSZ, int) + GENERATE_FIELD(RB_BUFSZ, int) +END_REGISTER(CP_RB_CNTL) + +START_REGISTER(CP_RB_RPTR_ADDR) + GENERATE_FIELD(RB_RPTR_ADDR, int) + GENERATE_FIELD(RB_RPTR_SWAP, int) +END_REGISTER(CP_RB_RPTR_ADDR) + +START_REGISTER(CP_RB_RPTR) + GENERATE_FIELD(RB_RPTR, int) +END_REGISTER(CP_RB_RPTR) + +START_REGISTER(CP_RB_RPTR_WR) + GENERATE_FIELD(RB_RPTR_WR, int) +END_REGISTER(CP_RB_RPTR_WR) + +START_REGISTER(CP_RB_WPTR) + GENERATE_FIELD(RB_WPTR, int) +END_REGISTER(CP_RB_WPTR) + +START_REGISTER(CP_RB_WPTR_DELAY) + GENERATE_FIELD(PRE_WRITE_LIMIT, int) + GENERATE_FIELD(PRE_WRITE_TIMER, int) +END_REGISTER(CP_RB_WPTR_DELAY) + +START_REGISTER(CP_RB_WPTR_BASE) + GENERATE_FIELD(RB_WPTR_BASE, int) + GENERATE_FIELD(RB_WPTR_SWAP, int) +END_REGISTER(CP_RB_WPTR_BASE) + +START_REGISTER(CP_IB1_BASE) + GENERATE_FIELD(IB1_BASE, int) +END_REGISTER(CP_IB1_BASE) + +START_REGISTER(CP_IB1_BUFSZ) + GENERATE_FIELD(IB1_BUFSZ, int) +END_REGISTER(CP_IB1_BUFSZ) + +START_REGISTER(CP_IB2_BASE) + GENERATE_FIELD(IB2_BASE, int) +END_REGISTER(CP_IB2_BASE) + +START_REGISTER(CP_IB2_BUFSZ) + GENERATE_FIELD(IB2_BUFSZ, int) +END_REGISTER(CP_IB2_BUFSZ) + +START_REGISTER(CP_ST_BASE) + GENERATE_FIELD(ST_BASE, int) +END_REGISTER(CP_ST_BASE) + +START_REGISTER(CP_ST_BUFSZ) + GENERATE_FIELD(ST_BUFSZ, int) +END_REGISTER(CP_ST_BUFSZ) + +START_REGISTER(CP_QUEUE_THRESHOLDS) + GENERATE_FIELD(CSQ_ST_START, int) + GENERATE_FIELD(CSQ_IB2_START, int) + GENERATE_FIELD(CSQ_IB1_START, int) +END_REGISTER(CP_QUEUE_THRESHOLDS) + +START_REGISTER(CP_MEQ_THRESHOLDS) + GENERATE_FIELD(ROQ_END, int) + GENERATE_FIELD(MEQ_END, int) +END_REGISTER(CP_MEQ_THRESHOLDS) + +START_REGISTER(CP_CSQ_AVAIL) + GENERATE_FIELD(CSQ_CNT_IB2, int) + GENERATE_FIELD(CSQ_CNT_IB1, int) + GENERATE_FIELD(CSQ_CNT_RING, int) +END_REGISTER(CP_CSQ_AVAIL) + +START_REGISTER(CP_STQ_AVAIL) + GENERATE_FIELD(STQ_CNT_ST, int) +END_REGISTER(CP_STQ_AVAIL) + +START_REGISTER(CP_MEQ_AVAIL) + GENERATE_FIELD(MEQ_CNT, int) +END_REGISTER(CP_MEQ_AVAIL) + +START_REGISTER(CP_CSQ_RB_STAT) + GENERATE_FIELD(CSQ_WPTR_PRIMARY, int) + GENERATE_FIELD(CSQ_RPTR_PRIMARY, int) +END_REGISTER(CP_CSQ_RB_STAT) + +START_REGISTER(CP_CSQ_IB1_STAT) + GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int) + GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int) +END_REGISTER(CP_CSQ_IB1_STAT) + +START_REGISTER(CP_CSQ_IB2_STAT) + GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int) + GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int) +END_REGISTER(CP_CSQ_IB2_STAT) + +START_REGISTER(CP_NON_PREFETCH_CNTRS) + GENERATE_FIELD(IB2_COUNTER, int) + GENERATE_FIELD(IB1_COUNTER, int) +END_REGISTER(CP_NON_PREFETCH_CNTRS) + +START_REGISTER(CP_STQ_ST_STAT) + GENERATE_FIELD(STQ_WPTR_ST, int) + GENERATE_FIELD(STQ_RPTR_ST, int) +END_REGISTER(CP_STQ_ST_STAT) + +START_REGISTER(CP_MEQ_STAT) + GENERATE_FIELD(MEQ_WPTR, int) + GENERATE_FIELD(MEQ_RPTR, int) +END_REGISTER(CP_MEQ_STAT) + +START_REGISTER(CP_MIU_TAG_STAT) + GENERATE_FIELD(INVALID_RETURN_TAG, int) + GENERATE_FIELD(TAG_17_STAT, int) + GENERATE_FIELD(TAG_16_STAT, int) + GENERATE_FIELD(TAG_15_STAT, int) + GENERATE_FIELD(TAG_14_STAT, int) + GENERATE_FIELD(TAG_13_STAT, int) + GENERATE_FIELD(TAG_12_STAT, int) + GENERATE_FIELD(TAG_11_STAT, int) + GENERATE_FIELD(TAG_10_STAT, int) + GENERATE_FIELD(TAG_9_STAT, int) + GENERATE_FIELD(TAG_8_STAT, int) + GENERATE_FIELD(TAG_7_STAT, int) + GENERATE_FIELD(TAG_6_STAT, int) + GENERATE_FIELD(TAG_5_STAT, int) + GENERATE_FIELD(TAG_4_STAT, int) + GENERATE_FIELD(TAG_3_STAT, int) + GENERATE_FIELD(TAG_2_STAT, int) + GENERATE_FIELD(TAG_1_STAT, int) + GENERATE_FIELD(TAG_0_STAT, int) +END_REGISTER(CP_MIU_TAG_STAT) + +START_REGISTER(CP_CMD_INDEX) + GENERATE_FIELD(CMD_QUEUE_SEL, int) + GENERATE_FIELD(CMD_INDEX, int) +END_REGISTER(CP_CMD_INDEX) + +START_REGISTER(CP_CMD_DATA) + GENERATE_FIELD(CMD_DATA, int) +END_REGISTER(CP_CMD_DATA) + +START_REGISTER(CP_ME_CNTL) + GENERATE_FIELD(PROG_CNT_SIZE, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(ME_HALT, int) + GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(ME_STATMUX, int) +END_REGISTER(CP_ME_CNTL) + +START_REGISTER(CP_ME_STATUS) + GENERATE_FIELD(ME_DEBUG_DATA, int) +END_REGISTER(CP_ME_STATUS) + +START_REGISTER(CP_ME_RAM_WADDR) + GENERATE_FIELD(ME_RAM_WADDR, int) +END_REGISTER(CP_ME_RAM_WADDR) + +START_REGISTER(CP_ME_RAM_RADDR) + GENERATE_FIELD(ME_RAM_RADDR, int) +END_REGISTER(CP_ME_RAM_RADDR) + +START_REGISTER(CP_ME_RAM_DATA) + GENERATE_FIELD(ME_RAM_DATA, int) +END_REGISTER(CP_ME_RAM_DATA) + +START_REGISTER(CP_ME_RDADDR) + GENERATE_FIELD(ME_RDADDR, int) +END_REGISTER(CP_ME_RDADDR) + +START_REGISTER(CP_DEBUG) + GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int) + GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int) + GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int) + GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int) + GENERATE_FIELD(PREFETCH_PASS_NOPS, int) + GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int) + GENERATE_FIELD(PROG_END_PTR_ENABLE, int) + GENERATE_FIELD(PREDICATE_DISABLE, int) + GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int) +END_REGISTER(CP_DEBUG) + +START_REGISTER(SCRATCH_REG0) + GENERATE_FIELD(SCRATCH_REG0, int) +END_REGISTER(SCRATCH_REG0) + +START_REGISTER(SCRATCH_REG1) + GENERATE_FIELD(SCRATCH_REG1, int) +END_REGISTER(SCRATCH_REG1) + +START_REGISTER(SCRATCH_REG2) + GENERATE_FIELD(SCRATCH_REG2, int) +END_REGISTER(SCRATCH_REG2) + +START_REGISTER(SCRATCH_REG3) + GENERATE_FIELD(SCRATCH_REG3, int) +END_REGISTER(SCRATCH_REG3) + +START_REGISTER(SCRATCH_REG4) + GENERATE_FIELD(SCRATCH_REG4, int) +END_REGISTER(SCRATCH_REG4) + +START_REGISTER(SCRATCH_REG5) + GENERATE_FIELD(SCRATCH_REG5, int) +END_REGISTER(SCRATCH_REG5) + +START_REGISTER(SCRATCH_REG6) + GENERATE_FIELD(SCRATCH_REG6, int) +END_REGISTER(SCRATCH_REG6) + +START_REGISTER(SCRATCH_REG7) + GENERATE_FIELD(SCRATCH_REG7, int) +END_REGISTER(SCRATCH_REG7) + +START_REGISTER(SCRATCH_UMSK) + GENERATE_FIELD(SCRATCH_SWAP, int) + GENERATE_FIELD(SCRATCH_UMSK, int) +END_REGISTER(SCRATCH_UMSK) + +START_REGISTER(SCRATCH_ADDR) + GENERATE_FIELD(SCRATCH_ADDR, hex) +END_REGISTER(SCRATCH_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_SRC) + GENERATE_FIELD(VS_DONE_CNTR, int) + GENERATE_FIELD(VS_DONE_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_SRC) + +START_REGISTER(CP_ME_VS_EVENT_ADDR) + GENERATE_FIELD(VS_DONE_ADDR, int) + GENERATE_FIELD(VS_DONE_SWAP, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_DATA) + GENERATE_FIELD(VS_DONE_DATA, int) +END_REGISTER(CP_ME_VS_EVENT_DATA) + +START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + GENERATE_FIELD(VS_DONE_ADDR_SWM, int) + GENERATE_FIELD(VS_DONE_SWAP_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + GENERATE_FIELD(VS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_PS_EVENT_SRC) + GENERATE_FIELD(PS_DONE_CNTR, int) + GENERATE_FIELD(PS_DONE_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_SRC) + +START_REGISTER(CP_ME_PS_EVENT_ADDR) + GENERATE_FIELD(PS_DONE_ADDR, int) + GENERATE_FIELD(PS_DONE_SWAP, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR) + +START_REGISTER(CP_ME_PS_EVENT_DATA) + GENERATE_FIELD(PS_DONE_DATA, int) +END_REGISTER(CP_ME_PS_EVENT_DATA) + +START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + GENERATE_FIELD(PS_DONE_ADDR_SWM, int) + GENERATE_FIELD(PS_DONE_SWAP_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + GENERATE_FIELD(PS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_CF_EVENT_SRC) + GENERATE_FIELD(CF_DONE_SRC, int) +END_REGISTER(CP_ME_CF_EVENT_SRC) + +START_REGISTER(CP_ME_CF_EVENT_ADDR) + GENERATE_FIELD(CF_DONE_ADDR, int) + GENERATE_FIELD(CF_DONE_SWAP, int) +END_REGISTER(CP_ME_CF_EVENT_ADDR) + +START_REGISTER(CP_ME_CF_EVENT_DATA) + GENERATE_FIELD(CF_DONE_DATA, int) +END_REGISTER(CP_ME_CF_EVENT_DATA) + +START_REGISTER(CP_ME_NRT_ADDR) + GENERATE_FIELD(NRT_WRITE_ADDR, int) + GENERATE_FIELD(NRT_WRITE_SWAP, int) +END_REGISTER(CP_ME_NRT_ADDR) + +START_REGISTER(CP_ME_NRT_DATA) + GENERATE_FIELD(NRT_WRITE_DATA, int) +END_REGISTER(CP_ME_NRT_DATA) + +START_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + GENERATE_FIELD(VS_FETCH_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + +START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + GENERATE_FIELD(VS_FETCH_DONE_ADDR, int) + GENERATE_FIELD(VS_FETCH_DONE_SWAP, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + +START_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + GENERATE_FIELD(VS_FETCH_DONE_DATA, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + +START_REGISTER(CP_INT_CNTL) + GENERATE_FIELD(RB_INT_MASK, int) + GENERATE_FIELD(IB1_INT_MASK, int) + GENERATE_FIELD(IB2_INT_MASK, int) + GENERATE_FIELD(IB_ERROR_MASK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int) + GENERATE_FIELD(OPCODE_ERROR_MASK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int) + GENERATE_FIELD(SW_INT_MASK, int) +END_REGISTER(CP_INT_CNTL) + +START_REGISTER(CP_INT_STATUS) + GENERATE_FIELD(RB_INT_STAT, int) + GENERATE_FIELD(IB1_INT_STAT, int) + GENERATE_FIELD(IB2_INT_STAT, int) + GENERATE_FIELD(IB_ERROR_STAT, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int) + GENERATE_FIELD(OPCODE_ERROR_STAT, int) + GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int) + GENERATE_FIELD(SW_INT_STAT, int) +END_REGISTER(CP_INT_STATUS) + +START_REGISTER(CP_INT_ACK) + GENERATE_FIELD(RB_INT_ACK, int) + GENERATE_FIELD(IB1_INT_ACK, int) + GENERATE_FIELD(IB2_INT_ACK, int) + GENERATE_FIELD(IB_ERROR_ACK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int) + GENERATE_FIELD(OPCODE_ERROR_ACK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int) + GENERATE_FIELD(SW_INT_ACK, int) +END_REGISTER(CP_INT_ACK) + +START_REGISTER(CP_PFP_UCODE_ADDR) + GENERATE_FIELD(UCODE_ADDR, hex) +END_REGISTER(CP_PFP_UCODE_ADDR) + +START_REGISTER(CP_PFP_UCODE_DATA) + GENERATE_FIELD(UCODE_DATA, hex) +END_REGISTER(CP_PFP_UCODE_DATA) + +START_REGISTER(CP_PERFMON_CNTL) + GENERATE_FIELD(PERFMON_ENABLE_MODE, int) + GENERATE_FIELD(PERFMON_STATE, int) +END_REGISTER(CP_PERFMON_CNTL) + +START_REGISTER(CP_PERFCOUNTER_SELECT) + GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL) +END_REGISTER(CP_PERFCOUNTER_SELECT) + +START_REGISTER(CP_PERFCOUNTER_LO) + GENERATE_FIELD(PERFCOUNT_LO, int) +END_REGISTER(CP_PERFCOUNTER_LO) + +START_REGISTER(CP_PERFCOUNTER_HI) + GENERATE_FIELD(PERFCOUNT_HI, int) +END_REGISTER(CP_PERFCOUNTER_HI) + +START_REGISTER(CP_BIN_MASK_LO) + GENERATE_FIELD(BIN_MASK_LO, int) +END_REGISTER(CP_BIN_MASK_LO) + +START_REGISTER(CP_BIN_MASK_HI) + GENERATE_FIELD(BIN_MASK_HI, int) +END_REGISTER(CP_BIN_MASK_HI) + +START_REGISTER(CP_BIN_SELECT_LO) + GENERATE_FIELD(BIN_SELECT_LO, int) +END_REGISTER(CP_BIN_SELECT_LO) + +START_REGISTER(CP_BIN_SELECT_HI) + GENERATE_FIELD(BIN_SELECT_HI, int) +END_REGISTER(CP_BIN_SELECT_HI) + +START_REGISTER(CP_NV_FLAGS_0) + GENERATE_FIELD(END_RCVD_15, int) + GENERATE_FIELD(DISCARD_15, int) + GENERATE_FIELD(END_RCVD_14, int) + GENERATE_FIELD(DISCARD_14, int) + GENERATE_FIELD(END_RCVD_13, int) + GENERATE_FIELD(DISCARD_13, int) + GENERATE_FIELD(END_RCVD_12, int) + GENERATE_FIELD(DISCARD_12, int) + GENERATE_FIELD(END_RCVD_11, int) + GENERATE_FIELD(DISCARD_11, int) + GENERATE_FIELD(END_RCVD_10, int) + GENERATE_FIELD(DISCARD_10, int) + GENERATE_FIELD(END_RCVD_9, int) + GENERATE_FIELD(DISCARD_9, int) + GENERATE_FIELD(END_RCVD_8, int) + GENERATE_FIELD(DISCARD_8, int) + GENERATE_FIELD(END_RCVD_7, int) + GENERATE_FIELD(DISCARD_7, int) + GENERATE_FIELD(END_RCVD_6, int) + GENERATE_FIELD(DISCARD_6, int) + GENERATE_FIELD(END_RCVD_5, int) + GENERATE_FIELD(DISCARD_5, int) + GENERATE_FIELD(END_RCVD_4, int) + GENERATE_FIELD(DISCARD_4, int) + GENERATE_FIELD(END_RCVD_3, int) + GENERATE_FIELD(DISCARD_3, int) + GENERATE_FIELD(END_RCVD_2, int) + GENERATE_FIELD(DISCARD_2, int) + GENERATE_FIELD(END_RCVD_1, int) + GENERATE_FIELD(DISCARD_1, int) + GENERATE_FIELD(END_RCVD_0, int) + GENERATE_FIELD(DISCARD_0, int) +END_REGISTER(CP_NV_FLAGS_0) + +START_REGISTER(CP_NV_FLAGS_1) + GENERATE_FIELD(END_RCVD_31, int) + GENERATE_FIELD(DISCARD_31, int) + GENERATE_FIELD(END_RCVD_30, int) + GENERATE_FIELD(DISCARD_30, int) + GENERATE_FIELD(END_RCVD_29, int) + GENERATE_FIELD(DISCARD_29, int) + GENERATE_FIELD(END_RCVD_28, int) + GENERATE_FIELD(DISCARD_28, int) + GENERATE_FIELD(END_RCVD_27, int) + GENERATE_FIELD(DISCARD_27, int) + GENERATE_FIELD(END_RCVD_26, int) + GENERATE_FIELD(DISCARD_26, int) + GENERATE_FIELD(END_RCVD_25, int) + GENERATE_FIELD(DISCARD_25, int) + GENERATE_FIELD(END_RCVD_24, int) + GENERATE_FIELD(DISCARD_24, int) + GENERATE_FIELD(END_RCVD_23, int) + GENERATE_FIELD(DISCARD_23, int) + GENERATE_FIELD(END_RCVD_22, int) + GENERATE_FIELD(DISCARD_22, int) + GENERATE_FIELD(END_RCVD_21, int) + GENERATE_FIELD(DISCARD_21, int) + GENERATE_FIELD(END_RCVD_20, int) + GENERATE_FIELD(DISCARD_20, int) + GENERATE_FIELD(END_RCVD_19, int) + GENERATE_FIELD(DISCARD_19, int) + GENERATE_FIELD(END_RCVD_18, int) + GENERATE_FIELD(DISCARD_18, int) + GENERATE_FIELD(END_RCVD_17, int) + GENERATE_FIELD(DISCARD_17, int) + GENERATE_FIELD(END_RCVD_16, int) + GENERATE_FIELD(DISCARD_16, int) +END_REGISTER(CP_NV_FLAGS_1) + +START_REGISTER(CP_NV_FLAGS_2) + GENERATE_FIELD(END_RCVD_47, int) + GENERATE_FIELD(DISCARD_47, int) + GENERATE_FIELD(END_RCVD_46, int) + GENERATE_FIELD(DISCARD_46, int) + GENERATE_FIELD(END_RCVD_45, int) + GENERATE_FIELD(DISCARD_45, int) + GENERATE_FIELD(END_RCVD_44, int) + GENERATE_FIELD(DISCARD_44, int) + GENERATE_FIELD(END_RCVD_43, int) + GENERATE_FIELD(DISCARD_43, int) + GENERATE_FIELD(END_RCVD_42, int) + GENERATE_FIELD(DISCARD_42, int) + GENERATE_FIELD(END_RCVD_41, int) + GENERATE_FIELD(DISCARD_41, int) + GENERATE_FIELD(END_RCVD_40, int) + GENERATE_FIELD(DISCARD_40, int) + GENERATE_FIELD(END_RCVD_39, int) + GENERATE_FIELD(DISCARD_39, int) + GENERATE_FIELD(END_RCVD_38, int) + GENERATE_FIELD(DISCARD_38, int) + GENERATE_FIELD(END_RCVD_37, int) + GENERATE_FIELD(DISCARD_37, int) + GENERATE_FIELD(END_RCVD_36, int) + GENERATE_FIELD(DISCARD_36, int) + GENERATE_FIELD(END_RCVD_35, int) + GENERATE_FIELD(DISCARD_35, int) + GENERATE_FIELD(END_RCVD_34, int) + GENERATE_FIELD(DISCARD_34, int) + GENERATE_FIELD(END_RCVD_33, int) + GENERATE_FIELD(DISCARD_33, int) + GENERATE_FIELD(END_RCVD_32, int) + GENERATE_FIELD(DISCARD_32, int) +END_REGISTER(CP_NV_FLAGS_2) + +START_REGISTER(CP_NV_FLAGS_3) + GENERATE_FIELD(END_RCVD_63, int) + GENERATE_FIELD(DISCARD_63, int) + GENERATE_FIELD(END_RCVD_62, int) + GENERATE_FIELD(DISCARD_62, int) + GENERATE_FIELD(END_RCVD_61, int) + GENERATE_FIELD(DISCARD_61, int) + GENERATE_FIELD(END_RCVD_60, int) + GENERATE_FIELD(DISCARD_60, int) + GENERATE_FIELD(END_RCVD_59, int) + GENERATE_FIELD(DISCARD_59, int) + GENERATE_FIELD(END_RCVD_58, int) + GENERATE_FIELD(DISCARD_58, int) + GENERATE_FIELD(END_RCVD_57, int) + GENERATE_FIELD(DISCARD_57, int) + GENERATE_FIELD(END_RCVD_56, int) + GENERATE_FIELD(DISCARD_56, int) + GENERATE_FIELD(END_RCVD_55, int) + GENERATE_FIELD(DISCARD_55, int) + GENERATE_FIELD(END_RCVD_54, int) + GENERATE_FIELD(DISCARD_54, int) + GENERATE_FIELD(END_RCVD_53, int) + GENERATE_FIELD(DISCARD_53, int) + GENERATE_FIELD(END_RCVD_52, int) + GENERATE_FIELD(DISCARD_52, int) + GENERATE_FIELD(END_RCVD_51, int) + GENERATE_FIELD(DISCARD_51, int) + GENERATE_FIELD(END_RCVD_50, int) + GENERATE_FIELD(DISCARD_50, int) + GENERATE_FIELD(END_RCVD_49, int) + GENERATE_FIELD(DISCARD_49, int) + GENERATE_FIELD(END_RCVD_48, int) + GENERATE_FIELD(DISCARD_48, int) +END_REGISTER(CP_NV_FLAGS_3) + +START_REGISTER(CP_STATE_DEBUG_INDEX) + GENERATE_FIELD(STATE_DEBUG_INDEX, int) +END_REGISTER(CP_STATE_DEBUG_INDEX) + +START_REGISTER(CP_STATE_DEBUG_DATA) + GENERATE_FIELD(STATE_DEBUG_DATA, int) +END_REGISTER(CP_STATE_DEBUG_DATA) + +START_REGISTER(CP_PROG_COUNTER) + GENERATE_FIELD(COUNTER, int) +END_REGISTER(CP_PROG_COUNTER) + +START_REGISTER(CP_STAT) + GENERATE_FIELD(CP_BUSY, int) + GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int) + GENERATE_FIELD(ME_WC_BUSY, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(_3D_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(MIU_WC_STALL, int) + GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int) + GENERATE_FIELD(MEQ_RING_BUSY, int) + GENERATE_FIELD(PFP_BUSY, int) + GENERATE_FIELD(ST_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int) + GENERATE_FIELD(RING_QUEUE_BUSY, int) + GENERATE_FIELD(CSF_BUSY, int) + GENERATE_FIELD(CSF_ST_BUSY, int) + GENERATE_FIELD(CSF_INDIRECT2_BUSY, int) + GENERATE_FIELD(CSF_INDIRECTS_BUSY, int) + GENERATE_FIELD(CSF_RING_BUSY, int) + GENERATE_FIELD(RCIU_BUSY, int) + GENERATE_FIELD(RBIU_BUSY, int) + GENERATE_FIELD(MIU_RD_RETURN_BUSY, int) + GENERATE_FIELD(MIU_RD_REQ_BUSY, int) + GENERATE_FIELD(MIU_WR_BUSY, int) +END_REGISTER(CP_STAT) + +START_REGISTER(BIOS_0_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_0_SCRATCH) + +START_REGISTER(BIOS_1_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_1_SCRATCH) + +START_REGISTER(BIOS_2_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_2_SCRATCH) + +START_REGISTER(BIOS_3_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_3_SCRATCH) + +START_REGISTER(BIOS_4_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_4_SCRATCH) + +START_REGISTER(BIOS_5_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_5_SCRATCH) + +START_REGISTER(BIOS_6_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_6_SCRATCH) + +START_REGISTER(BIOS_7_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_7_SCRATCH) + +START_REGISTER(BIOS_8_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_8_SCRATCH) + +START_REGISTER(BIOS_9_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_9_SCRATCH) + +START_REGISTER(BIOS_10_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_10_SCRATCH) + +START_REGISTER(BIOS_11_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_11_SCRATCH) + +START_REGISTER(BIOS_12_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_12_SCRATCH) + +START_REGISTER(BIOS_13_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_13_SCRATCH) + +START_REGISTER(BIOS_14_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_14_SCRATCH) + +START_REGISTER(BIOS_15_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_15_SCRATCH) + +START_REGISTER(COHER_SIZE_PM4) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_PM4) + +START_REGISTER(COHER_BASE_PM4) + GENERATE_FIELD(BASE, int) +END_REGISTER(COHER_BASE_PM4) + +START_REGISTER(COHER_STATUS_PM4) + GENERATE_FIELD(STATUS, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(MATCHING_CONTEXTS, int) +END_REGISTER(COHER_STATUS_PM4) + +START_REGISTER(COHER_SIZE_HOST) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_HOST) + +START_REGISTER(COHER_BASE_HOST) + GENERATE_FIELD(BASE, hex) +END_REGISTER(COHER_BASE_HOST) + +START_REGISTER(COHER_STATUS_HOST) + GENERATE_FIELD(STATUS, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(MATCHING_CONTEXTS, int) +END_REGISTER(COHER_STATUS_HOST) + +START_REGISTER(COHER_DEST_BASE_0) + GENERATE_FIELD(DEST_BASE_0, hex) +END_REGISTER(COHER_DEST_BASE_0) + +START_REGISTER(COHER_DEST_BASE_1) + GENERATE_FIELD(DEST_BASE_1, hex) +END_REGISTER(COHER_DEST_BASE_1) + +START_REGISTER(COHER_DEST_BASE_2) + GENERATE_FIELD(DEST_BASE_2, hex) +END_REGISTER(COHER_DEST_BASE_2) + +START_REGISTER(COHER_DEST_BASE_3) + GENERATE_FIELD(DEST_BASE_3, hex) +END_REGISTER(COHER_DEST_BASE_3) + +START_REGISTER(COHER_DEST_BASE_4) + GENERATE_FIELD(DEST_BASE_4, hex) +END_REGISTER(COHER_DEST_BASE_4) + +START_REGISTER(COHER_DEST_BASE_5) + GENERATE_FIELD(DEST_BASE_5, hex) +END_REGISTER(COHER_DEST_BASE_5) + +START_REGISTER(COHER_DEST_BASE_6) + GENERATE_FIELD(DEST_BASE_6, hex) +END_REGISTER(COHER_DEST_BASE_6) + +START_REGISTER(COHER_DEST_BASE_7) + GENERATE_FIELD(DEST_BASE_7, hex) +END_REGISTER(COHER_DEST_BASE_7) + +START_REGISTER(RB_SURFACE_INFO) + GENERATE_FIELD(MSAA_SAMPLES, MSAASamples) + GENERATE_FIELD(SURFACE_PITCH, uint) +END_REGISTER(RB_SURFACE_INFO) + +START_REGISTER(RB_COLOR_INFO) + GENERATE_FIELD(COLOR_BASE, uint) + GENERATE_FIELD(COLOR_SWAP, uint) + GENERATE_FIELD(COLOR_ENDIAN, uint) + GENERATE_FIELD(COLOR_LINEAR, bool) + GENERATE_FIELD(COLOR_ROUND_MODE, uint) + GENERATE_FIELD(COLOR_FORMAT, ColorformatX) +END_REGISTER(RB_COLOR_INFO) + +START_REGISTER(RB_DEPTH_INFO) + GENERATE_FIELD(DEPTH_BASE, uint) + GENERATE_FIELD(DEPTH_FORMAT, DepthformatX) +END_REGISTER(RB_DEPTH_INFO) + +START_REGISTER(RB_STENCILREFMASK) + GENERATE_FIELD(RESERVED1, bool) + GENERATE_FIELD(RESERVED0, bool) + GENERATE_FIELD(STENCILWRITEMASK, hex) + GENERATE_FIELD(STENCILMASK, hex) + GENERATE_FIELD(STENCILREF, hex) +END_REGISTER(RB_STENCILREFMASK) + +START_REGISTER(RB_ALPHA_REF) + GENERATE_FIELD(ALPHA_REF, float) +END_REGISTER(RB_ALPHA_REF) + +START_REGISTER(RB_COLOR_MASK) + GENERATE_FIELD(RESERVED3, bool) + GENERATE_FIELD(RESERVED2, bool) + GENERATE_FIELD(WRITE_ALPHA, bool) + GENERATE_FIELD(WRITE_BLUE, bool) + GENERATE_FIELD(WRITE_GREEN, bool) + GENERATE_FIELD(WRITE_RED, bool) +END_REGISTER(RB_COLOR_MASK) + +START_REGISTER(RB_BLEND_RED) + GENERATE_FIELD(BLEND_RED, uint) +END_REGISTER(RB_BLEND_RED) + +START_REGISTER(RB_BLEND_GREEN) + GENERATE_FIELD(BLEND_GREEN, uint) +END_REGISTER(RB_BLEND_GREEN) + +START_REGISTER(RB_BLEND_BLUE) + GENERATE_FIELD(BLEND_BLUE, uint) +END_REGISTER(RB_BLEND_BLUE) + +START_REGISTER(RB_BLEND_ALPHA) + GENERATE_FIELD(BLEND_ALPHA, uint) +END_REGISTER(RB_BLEND_ALPHA) + +START_REGISTER(RB_FOG_COLOR) + GENERATE_FIELD(FOG_BLUE, uint) + GENERATE_FIELD(FOG_GREEN, uint) + GENERATE_FIELD(FOG_RED, uint) +END_REGISTER(RB_FOG_COLOR) + +START_REGISTER(RB_STENCILREFMASK_BF) + GENERATE_FIELD(RESERVED5, bool) + GENERATE_FIELD(RESERVED4, bool) + GENERATE_FIELD(STENCILWRITEMASK_BF, hex) + GENERATE_FIELD(STENCILMASK_BF, hex) + GENERATE_FIELD(STENCILREF_BF, hex) +END_REGISTER(RB_STENCILREFMASK_BF) + +START_REGISTER(RB_DEPTHCONTROL) + GENERATE_FIELD(STENCILZFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILZPASS_BF, StencilOp) + GENERATE_FIELD(STENCILFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILFUNC_BF, CompareRef) + GENERATE_FIELD(STENCILZFAIL, StencilOp) + GENERATE_FIELD(STENCILZPASS, StencilOp) + GENERATE_FIELD(STENCILFAIL, StencilOp) + GENERATE_FIELD(STENCILFUNC, CompareRef) + GENERATE_FIELD(BACKFACE_ENABLE, bool) + GENERATE_FIELD(ZFUNC, CompareFrag) + GENERATE_FIELD(EARLY_Z_ENABLE, bool) + GENERATE_FIELD(Z_WRITE_ENABLE, bool) + GENERATE_FIELD(Z_ENABLE, bool) + GENERATE_FIELD(STENCIL_ENABLE, bool) +END_REGISTER(RB_DEPTHCONTROL) + +START_REGISTER(RB_BLENDCONTROL) + GENERATE_FIELD(BLEND_FORCE, bool) + GENERATE_FIELD(BLEND_FORCE_ENABLE, bool) + GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX) + GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX) + GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX) + GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX) + GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX) +END_REGISTER(RB_BLENDCONTROL) + +START_REGISTER(RB_COLORCONTROL) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex) + GENERATE_FIELD(PIXEL_FOG, bool) + GENERATE_FIELD(DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(DITHER_MODE, DitherModeX) + GENERATE_FIELD(ROP_CODE, uint) + GENERATE_FIELD(VS_EXPORTS_FOG, bool) + GENERATE_FIELD(FOG_ENABLE, bool) + GENERATE_FIELD(BLEND_DISABLE, bool) + GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool) + GENERATE_FIELD(ALPHA_TEST_ENABLE, bool) + GENERATE_FIELD(ALPHA_FUNC, CompareRef) +END_REGISTER(RB_COLORCONTROL) + +START_REGISTER(RB_MODECONTROL) + GENERATE_FIELD(EDRAM_MODE, EdramMode) +END_REGISTER(RB_MODECONTROL) + +START_REGISTER(RB_COLOR_DEST_MASK) + GENERATE_FIELD(COLOR_DEST_MASK, uint) +END_REGISTER(RB_COLOR_DEST_MASK) + +START_REGISTER(RB_COPY_CONTROL) + GENERATE_FIELD(CLEAR_MASK, uint) + GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool) + GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect) +END_REGISTER(RB_COPY_CONTROL) + +START_REGISTER(RB_COPY_DEST_BASE) + GENERATE_FIELD(COPY_DEST_BASE, uint) +END_REGISTER(RB_COPY_DEST_BASE) + +START_REGISTER(RB_COPY_DEST_PITCH) + GENERATE_FIELD(COPY_DEST_PITCH, uint) +END_REGISTER(RB_COPY_DEST_PITCH) + +START_REGISTER(RB_COPY_DEST_INFO) + GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex) + GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex) + GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex) + GENERATE_FIELD(COPY_MASK_WRITE_RED, hex) + GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX) + GENERATE_FIELD(COPY_DEST_SWAP, uint) + GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX) + GENERATE_FIELD(COPY_DEST_LINEAR, uint) + GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian) +END_REGISTER(RB_COPY_DEST_INFO) + +START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + GENERATE_FIELD(OFFSET_Y, uint) + GENERATE_FIELD(OFFSET_X, uint) +END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + +START_REGISTER(RB_DEPTH_CLEAR) + GENERATE_FIELD(DEPTH_CLEAR, uint) +END_REGISTER(RB_DEPTH_CLEAR) + +START_REGISTER(RB_SAMPLE_COUNT_CTL) + GENERATE_FIELD(COPY_SAMPLE_COUNT, bool) + GENERATE_FIELD(RESET_SAMPLE_COUNT, bool) +END_REGISTER(RB_SAMPLE_COUNT_CTL) + +START_REGISTER(RB_SAMPLE_COUNT_ADDR) + GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint) +END_REGISTER(RB_SAMPLE_COUNT_ADDR) + +START_REGISTER(RB_BC_CONTROL) + GENERATE_FIELD(RESERVED6, bool) + GENERATE_FIELD(CRC_SYSTEM, bool) + GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int) + GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool) + GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool) + GENERATE_FIELD(ACCUM_ALLOC_MASK, uint) + GENERATE_FIELD(DISABLE_ACCUM, bool) + GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool) + GENERATE_FIELD(CRC_MODE, bool) + GENERATE_FIELD(ENABLE_CRC_UPDATE, bool) + GENERATE_FIELD(AZ_THROTTLE_COUNT, uint) + GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool) + GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool) + GENERATE_FIELD(DISABLE_EDRAM_CAM, bool) + GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint) + GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool) +END_REGISTER(RB_BC_CONTROL) + +START_REGISTER(RB_EDRAM_INFO) + GENERATE_FIELD(EDRAM_RANGE, hex) + GENERATE_FIELD(EDRAM_MAPPING_MODE, uint) + GENERATE_FIELD(EDRAM_SIZE, EdramSizeX) +END_REGISTER(RB_EDRAM_INFO) + +START_REGISTER(RB_CRC_RD_PORT) + GENERATE_FIELD(CRC_DATA, hex) +END_REGISTER(RB_CRC_RD_PORT) + +START_REGISTER(RB_CRC_CONTROL) + GENERATE_FIELD(CRC_RD_ADVANCE, bool) +END_REGISTER(RB_CRC_CONTROL) + +START_REGISTER(RB_CRC_MASK) + GENERATE_FIELD(CRC_MASK, hex) +END_REGISTER(RB_CRC_MASK) + +START_REGISTER(RB_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT) +END_REGISTER(RB_PERFCOUNTER0_SELECT) + +START_REGISTER(RB_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_LOW) + +START_REGISTER(RB_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_HI) + +START_REGISTER(RB_TOTAL_SAMPLES) + GENERATE_FIELD(TOTAL_SAMPLES, int) +END_REGISTER(RB_TOTAL_SAMPLES) + +START_REGISTER(RB_ZPASS_SAMPLES) + GENERATE_FIELD(ZPASS_SAMPLES, int) +END_REGISTER(RB_ZPASS_SAMPLES) + +START_REGISTER(RB_ZFAIL_SAMPLES) + GENERATE_FIELD(ZFAIL_SAMPLES, int) +END_REGISTER(RB_ZFAIL_SAMPLES) + +START_REGISTER(RB_SFAIL_SAMPLES) + GENERATE_FIELD(SFAIL_SAMPLES, int) +END_REGISTER(RB_SFAIL_SAMPLES) + +START_REGISTER(RB_DEBUG_0) + GENERATE_FIELD(EZ_INFSAMP_FULL, bool) + GENERATE_FIELD(C_MASK_FULL, bool) + GENERATE_FIELD(C_REQ_FULL, bool) + GENERATE_FIELD(C_EZ_TILE_FULL, bool) + GENERATE_FIELD(C_SX_CMD_FULL, bool) + GENERATE_FIELD(C_SX_LAT_FULL, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool) + GENERATE_FIELD(WRREQ_C0_FULL, bool) + GENERATE_FIELD(WRREQ_C1_FULL, bool) + GENERATE_FIELD(WRREQ_Z0_FULL, bool) + GENERATE_FIELD(WRREQ_Z1_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool) + GENERATE_FIELD(RDREQ_C0_FULL, bool) + GENERATE_FIELD(RDREQ_C1_FULL, bool) + GENERATE_FIELD(RDREQ_Z0_FULL, bool) + GENERATE_FIELD(RDREQ_Z1_FULL, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool) +END_REGISTER(RB_DEBUG_0) + +START_REGISTER(RB_DEBUG_1) + GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool) + GENERATE_FIELD(C_MASK_EMPTY, bool) + GENERATE_FIELD(C_REQ_EMPTY, bool) + GENERATE_FIELD(C_EZ_TILE_EMPTY, bool) + GENERATE_FIELD(C_SX_CMD_EMPTY, bool) + GENERATE_FIELD(C_SX_LAT_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool) + GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z0_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z1_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_EMPTY, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool) +END_REGISTER(RB_DEBUG_1) + +START_REGISTER(RB_DEBUG_2) + GENERATE_FIELD(Z_TILE_EMPTY, bool) + GENERATE_FIELD(Z_SAMP_EMPTY, bool) + GENERATE_FIELD(Z1_REQ_EMPTY, bool) + GENERATE_FIELD(Z0_REQ_EMPTY, bool) + GENERATE_FIELD(Z1_MASK_EMPTY, bool) + GENERATE_FIELD(Z0_MASK_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_INFTILE_EMPTY, bool) + GENERATE_FIELD(Z_TILE_FULL, bool) + GENERATE_FIELD(Z_SAMP_FULL, bool) + GENERATE_FIELD(Z1_REQ_FULL, bool) + GENERATE_FIELD(Z0_REQ_FULL, bool) + GENERATE_FIELD(Z1_MASK_FULL, bool) + GENERATE_FIELD(Z0_MASK_FULL, bool) + GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool) + GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool) + GENERATE_FIELD(EZ_INFTILE_FULL, bool) + GENERATE_FIELD(CURRENT_TILE_EVENT, bool) + GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool) + GENERATE_FIELD(MEM_EXPORT_FLAG, bool) + GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool) + GENERATE_FIELD(TILE_FIFO_COUNT, bool) +END_REGISTER(RB_DEBUG_2) + +START_REGISTER(RB_DEBUG_3) + GENERATE_FIELD(ZEXP_UPPER_FULL, bool) + GENERATE_FIELD(ZEXP_LOWER_FULL, bool) + GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool) + GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool) + GENERATE_FIELD(SHD_EMPTY, bool) + GENERATE_FIELD(SHD_FULL, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool) + GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool) + GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool) + GENERATE_FIELD(ACCUM_FLUSHING, bool) + GENERATE_FIELD(ACCUM_VALID, bool) +END_REGISTER(RB_DEBUG_3) + +START_REGISTER(RB_DEBUG_4) + GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool) + GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool) + GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool) +END_REGISTER(RB_DEBUG_4) + +START_REGISTER(RB_FLAG_CONTROL) + GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool) +END_REGISTER(RB_FLAG_CONTROL) + +START_REGISTER(RB_BC_SPARES) + GENERATE_FIELD(RESERVED, bool) +END_REGISTER(RB_BC_SPARES) + +START_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber) + GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat) + GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat) +END_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + +START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX) +END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h new file mode 100644 index 000000000000..f31b2a74d1fa --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h @@ -0,0 +1,5920 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_MASK_HEADER) +#define _yamato_MASK_HEADER +/* +* yamato_mask.h +* +* Register Spec Release: Chip Spec 1.0 +* +* +* (c) 2000 ATI Technologies Inc. (unpublished) +* +* All rights reserved. This notice is intended as a precaution against +* inadvertent publication and does not imply publication or any waiver +* of confidentiality. The year included in the foregoing notice is the +* year of creation of the work. +* +*/ + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_XY_FMT 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_Z_FMT 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__VTX_W0_FMT 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF 0x00000800L + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE 0x00010000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR 0x00200000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN 0x00400000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK 0x00800000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN 0x00800000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN 0x01000000L + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA 0x00000001L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_CL_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_SC_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__PIX_CENTER 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR_MASK 0xffffffe0L + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_FRONT 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__CULL_BACK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__FACE 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE 0x00002000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK 0x00008000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE 0x00008000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE 0x00010000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK 0x00040000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE 0x00040000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA 0x00200000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK 0x00800000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE 0x00800000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK 0x20000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS 0x20000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK 0x80000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE 0x80000000L + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x00007fffL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0x7fff0000L + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK_MASK 0x0000ffffL + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL_MASK 0x000000ffL +#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK 0x00000100L +#define PA_SC_LINE_CNTL__USE_BRES_CNTL 0x00000100L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__LAST_PIXEL 0x00000400L + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x3fff0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE 0x80000000L + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x3fff0000L + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0x7fff0000L + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0x7fff0000L + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK 0x0000003eL +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK 0x00000080L +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z 0x00000080L + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK 0xffffffffL + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +#define PA_CL_CNTL_STATUS__CL_BUSY 0x80000000L + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +#define PA_SU_CNTL_STATUS__SU_BUSY 0x80000000L + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY_MASK 0x80000000L +#define PA_SC_CNTL_STATUS__SC_BUSY 0x80000000L + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00000008L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full 0x00000008L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full 0x00000020L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00000080L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full 0x00000080L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00000800L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full 0x00000800L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00002000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full 0x00002000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full 0x00020000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full 0x00080000L +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xfff00000L + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00380000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff000000L + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK 0x001fffffL +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK 0x7f000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK 0x00000007L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK 0x00000070L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK 0x000fff00L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK 0x00000007L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK 0x00000070L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event 0x00000080L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK 0xffffff00L + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK 0x00000006L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK 0x00030000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK 0xf0000000L + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK 0x00000001L +#define CLIPPER_DEBUG_REG09__clprim_in_back_event 0x00000001L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK 0x000000c0L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK 0x00003000L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK 0x000c0000L +#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK 0x00100000L +#define CLIPPER_DEBUG_REG09__prim_back_valid 0x00100000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK 0x20000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full 0x20000000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK 0x00000030L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK 0x00000c00L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK 0x00030000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK 0x00180000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK 0xfffffff0L + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK 0x00200000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid 0x00200000L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK 0xffc00000L + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK 0x000007f0L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK 0x00003800L +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK 0xf8000000L + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK 0x00000380L +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x00001c00L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK 0x0000e000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx 0x00010000L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK 0x00060000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x00780000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3f800000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel 0x80000000L + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK 0x00000003L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK 0x0000000cL +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK 0x00000780L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00007000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector 0x00008000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK 0x000f0000L +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG1__aux_sel 0x00100000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK 0x00600000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK 0x01800000L +#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK 0xfe000000L + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent_MASK 0x00000001L +#define SXIFCCG_DEBUG_REG2__sx_sent 0x00000001L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK 0x00000002L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3 0x00000002L +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_aux 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x000001f8L +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x0000fe00L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2 0x00010000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx 0x00020000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK 0x000c0000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK 0x03c00000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x04000000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded 0x04000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK 0xe0000000L + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK 0x00000010L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3 0x00000010L +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x000000e0L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK 0x00000f00L +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00003000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full 0x00008000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK 0x00030000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x00080000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full 0x00080000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x00200000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full 0x00200000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK 0xffc00000L + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000001fL +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x000007e0L +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00000800L +#define SETUP_DEBUG_REG0__ge_stallb 0x00000800L +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00001000L +#define SETUP_DEBUG_REG0__geom_enable 0x00001000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00004000L +#define SETUP_DEBUG_REG0__su_clip_rtr 0x00004000L +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00008000L +#define SETUP_DEBUG_REG0__pfifo_busy 0x00008000L +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00010000L +#define SETUP_DEBUG_REG0__su_cntl_busy 0x00010000L +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00020000L +#define SETUP_DEBUG_REG0__geom_busy 0x00020000L + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00000800L +#define SETUP_DEBUG_REG4__null_prim_gated 0x00000800L +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00001000L +#define SETUP_DEBUG_REG4__backfacing_gated 0x00001000L +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x0000e000L +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00010000L +#define SETUP_DEBUG_REG4__clipped_gated 0x00010000L +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x000e0000L +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00100000L +#define SETUP_DEBUG_REG4__xmajor_gated 0x00100000L +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x00600000L +#define SETUP_DEBUG_REG4__type_gated_MASK 0x03800000L +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x04000000L +#define SETUP_DEBUG_REG4__fpov_gated 0x04000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK 0x08000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated 0x08000000L +#define SETUP_DEBUG_REG4__event_gated_MASK 0x10000000L +#define SETUP_DEBUG_REG4__event_gated 0x10000000L +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x20000000L +#define SETUP_DEBUG_REG4__eop_gated 0x20000000L + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x003ff800L +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x00c00000L +#define SETUP_DEBUG_REG5__event_id_gated_MASK 0x1f000000L + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000001fL + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1_MASK 0x00000001L +#define SC_DEBUG_0__pa_freeze_b1 0x00000001L +#define SC_DEBUG_0__pa_sc_valid_MASK 0x00000002L +#define SC_DEBUG_0__pa_sc_valid 0x00000002L +#define SC_DEBUG_0__pa_sc_phase_MASK 0x0000001cL +#define SC_DEBUG_0__cntx_cnt_MASK 0x00000fe0L +#define SC_DEBUG_0__decr_cntx_cnt_MASK 0x00001000L +#define SC_DEBUG_0__decr_cntx_cnt 0x00001000L +#define SC_DEBUG_0__incr_cntx_cnt_MASK 0x00002000L +#define SC_DEBUG_0__incr_cntx_cnt 0x00002000L +#define SC_DEBUG_0__trigger_MASK 0x80000000L +#define SC_DEBUG_0__trigger 0x80000000L + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state_MASK 0x00000007L +#define SC_DEBUG_1__em1_data_ready_MASK 0x00000008L +#define SC_DEBUG_1__em1_data_ready 0x00000008L +#define SC_DEBUG_1__em2_data_ready_MASK 0x00000010L +#define SC_DEBUG_1__em2_data_ready 0x00000010L +#define SC_DEBUG_1__move_em1_to_em2_MASK 0x00000020L +#define SC_DEBUG_1__move_em1_to_em2 0x00000020L +#define SC_DEBUG_1__ef_data_ready_MASK 0x00000040L +#define SC_DEBUG_1__ef_data_ready 0x00000040L +#define SC_DEBUG_1__ef_state_MASK 0x00000180L +#define SC_DEBUG_1__pipe_valid_MASK 0x00000200L +#define SC_DEBUG_1__pipe_valid 0x00000200L +#define SC_DEBUG_1__trigger_MASK 0x80000000L +#define SC_DEBUG_1__trigger 0x80000000L + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly_MASK 0x00000001L +#define SC_DEBUG_2__rc_rtr_dly 0x00000001L +#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK 0x00000002L +#define SC_DEBUG_2__qmask_ff_alm_full_d1 0x00000002L +#define SC_DEBUG_2__pipe_freeze_b_MASK 0x00000008L +#define SC_DEBUG_2__pipe_freeze_b 0x00000008L +#define SC_DEBUG_2__prim_rts_MASK 0x00000010L +#define SC_DEBUG_2__prim_rts 0x00000010L +#define SC_DEBUG_2__next_prim_rts_dly_MASK 0x00000020L +#define SC_DEBUG_2__next_prim_rts_dly 0x00000020L +#define SC_DEBUG_2__next_prim_rtr_dly_MASK 0x00000040L +#define SC_DEBUG_2__next_prim_rtr_dly 0x00000040L +#define SC_DEBUG_2__pre_stage1_rts_d1_MASK 0x00000080L +#define SC_DEBUG_2__pre_stage1_rts_d1 0x00000080L +#define SC_DEBUG_2__stage0_rts_MASK 0x00000100L +#define SC_DEBUG_2__stage0_rts 0x00000100L +#define SC_DEBUG_2__phase_rts_dly_MASK 0x00000200L +#define SC_DEBUG_2__phase_rts_dly 0x00000200L +#define SC_DEBUG_2__end_of_prim_s1_dly_MASK 0x00008000L +#define SC_DEBUG_2__end_of_prim_s1_dly 0x00008000L +#define SC_DEBUG_2__pass_empty_prim_s1_MASK 0x00010000L +#define SC_DEBUG_2__pass_empty_prim_s1 0x00010000L +#define SC_DEBUG_2__event_id_s1_MASK 0x003e0000L +#define SC_DEBUG_2__event_s1_MASK 0x00400000L +#define SC_DEBUG_2__event_s1 0x00400000L +#define SC_DEBUG_2__trigger_MASK 0x80000000L +#define SC_DEBUG_2__trigger 0x80000000L + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1_MASK 0x000007ffL +#define SC_DEBUG_3__y_curr_s1_MASK 0x003ff800L +#define SC_DEBUG_3__trigger_MASK 0x80000000L +#define SC_DEBUG_3__trigger 0x80000000L + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1_MASK 0x00003fffL +#define SC_DEBUG_4__y_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_4__y_dir_s1_MASK 0x10000000L +#define SC_DEBUG_4__y_dir_s1 0x10000000L +#define SC_DEBUG_4__trigger_MASK 0x80000000L +#define SC_DEBUG_4__trigger 0x80000000L + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1_MASK 0x00003fffL +#define SC_DEBUG_5__x_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_5__x_dir_s1_MASK 0x10000000L +#define SC_DEBUG_5__x_dir_s1 0x10000000L +#define SC_DEBUG_5__trigger_MASK 0x80000000L +#define SC_DEBUG_5__trigger 0x80000000L + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty_MASK 0x00000001L +#define SC_DEBUG_6__z_ff_empty 0x00000001L +#define SC_DEBUG_6__qmcntl_ff_empty_MASK 0x00000002L +#define SC_DEBUG_6__qmcntl_ff_empty 0x00000002L +#define SC_DEBUG_6__xy_ff_empty_MASK 0x00000004L +#define SC_DEBUG_6__xy_ff_empty 0x00000004L +#define SC_DEBUG_6__event_flag_MASK 0x00000008L +#define SC_DEBUG_6__event_flag 0x00000008L +#define SC_DEBUG_6__z_mask_needed_MASK 0x00000010L +#define SC_DEBUG_6__z_mask_needed 0x00000010L +#define SC_DEBUG_6__state_MASK 0x000000e0L +#define SC_DEBUG_6__state_delayed_MASK 0x00000700L +#define SC_DEBUG_6__data_valid_MASK 0x00000800L +#define SC_DEBUG_6__data_valid 0x00000800L +#define SC_DEBUG_6__data_valid_d_MASK 0x00001000L +#define SC_DEBUG_6__data_valid_d 0x00001000L +#define SC_DEBUG_6__tilex_delayed_MASK 0x003fe000L +#define SC_DEBUG_6__tiley_delayed_MASK 0x7fc00000L +#define SC_DEBUG_6__trigger_MASK 0x80000000L +#define SC_DEBUG_6__trigger 0x80000000L + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag_MASK 0x00000001L +#define SC_DEBUG_7__event_flag 0x00000001L +#define SC_DEBUG_7__deallocate_MASK 0x0000000eL +#define SC_DEBUG_7__fposition_MASK 0x00000010L +#define SC_DEBUG_7__fposition 0x00000010L +#define SC_DEBUG_7__sr_prim_we_MASK 0x00000020L +#define SC_DEBUG_7__sr_prim_we 0x00000020L +#define SC_DEBUG_7__last_tile_MASK 0x00000040L +#define SC_DEBUG_7__last_tile 0x00000040L +#define SC_DEBUG_7__tile_ff_we_MASK 0x00000080L +#define SC_DEBUG_7__tile_ff_we 0x00000080L +#define SC_DEBUG_7__qs_data_valid_MASK 0x00000100L +#define SC_DEBUG_7__qs_data_valid 0x00000100L +#define SC_DEBUG_7__qs_q0_y_MASK 0x00000600L +#define SC_DEBUG_7__qs_q0_x_MASK 0x00001800L +#define SC_DEBUG_7__qs_q0_valid_MASK 0x00002000L +#define SC_DEBUG_7__qs_q0_valid 0x00002000L +#define SC_DEBUG_7__prim_ff_we_MASK 0x00004000L +#define SC_DEBUG_7__prim_ff_we 0x00004000L +#define SC_DEBUG_7__tile_ff_re_MASK 0x00008000L +#define SC_DEBUG_7__tile_ff_re 0x00008000L +#define SC_DEBUG_7__fw_prim_data_valid_MASK 0x00010000L +#define SC_DEBUG_7__fw_prim_data_valid 0x00010000L +#define SC_DEBUG_7__last_quad_of_tile_MASK 0x00020000L +#define SC_DEBUG_7__last_quad_of_tile 0x00020000L +#define SC_DEBUG_7__first_quad_of_tile_MASK 0x00040000L +#define SC_DEBUG_7__first_quad_of_tile 0x00040000L +#define SC_DEBUG_7__first_quad_of_prim_MASK 0x00080000L +#define SC_DEBUG_7__first_quad_of_prim 0x00080000L +#define SC_DEBUG_7__new_prim_MASK 0x00100000L +#define SC_DEBUG_7__new_prim 0x00100000L +#define SC_DEBUG_7__load_new_tile_data_MASK 0x00200000L +#define SC_DEBUG_7__load_new_tile_data 0x00200000L +#define SC_DEBUG_7__state_MASK 0x00c00000L +#define SC_DEBUG_7__fifos_ready_MASK 0x01000000L +#define SC_DEBUG_7__fifos_ready 0x01000000L +#define SC_DEBUG_7__trigger_MASK 0x80000000L +#define SC_DEBUG_7__trigger 0x80000000L + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last_MASK 0x00000001L +#define SC_DEBUG_8__sample_last 0x00000001L +#define SC_DEBUG_8__sample_mask_MASK 0x0000001eL +#define SC_DEBUG_8__sample_y_MASK 0x00000060L +#define SC_DEBUG_8__sample_x_MASK 0x00000180L +#define SC_DEBUG_8__sample_send_MASK 0x00000200L +#define SC_DEBUG_8__sample_send 0x00000200L +#define SC_DEBUG_8__next_cycle_MASK 0x00000c00L +#define SC_DEBUG_8__ez_sample_ff_full_MASK 0x00001000L +#define SC_DEBUG_8__ez_sample_ff_full 0x00001000L +#define SC_DEBUG_8__rb_sc_samp_rtr_MASK 0x00002000L +#define SC_DEBUG_8__rb_sc_samp_rtr 0x00002000L +#define SC_DEBUG_8__num_samples_MASK 0x0000c000L +#define SC_DEBUG_8__last_quad_of_tile_MASK 0x00010000L +#define SC_DEBUG_8__last_quad_of_tile 0x00010000L +#define SC_DEBUG_8__last_quad_of_prim_MASK 0x00020000L +#define SC_DEBUG_8__last_quad_of_prim 0x00020000L +#define SC_DEBUG_8__first_quad_of_prim_MASK 0x00040000L +#define SC_DEBUG_8__first_quad_of_prim 0x00040000L +#define SC_DEBUG_8__sample_we_MASK 0x00080000L +#define SC_DEBUG_8__sample_we 0x00080000L +#define SC_DEBUG_8__fposition_MASK 0x00100000L +#define SC_DEBUG_8__fposition 0x00100000L +#define SC_DEBUG_8__event_id_MASK 0x03e00000L +#define SC_DEBUG_8__event_flag_MASK 0x04000000L +#define SC_DEBUG_8__event_flag 0x04000000L +#define SC_DEBUG_8__fw_prim_data_valid_MASK 0x08000000L +#define SC_DEBUG_8__fw_prim_data_valid 0x08000000L +#define SC_DEBUG_8__trigger_MASK 0x80000000L +#define SC_DEBUG_8__trigger 0x80000000L + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send_MASK 0x00000001L +#define SC_DEBUG_9__rb_sc_send 0x00000001L +#define SC_DEBUG_9__rb_sc_ez_mask_MASK 0x0000001eL +#define SC_DEBUG_9__fifo_data_ready_MASK 0x00000020L +#define SC_DEBUG_9__fifo_data_ready 0x00000020L +#define SC_DEBUG_9__early_z_enable_MASK 0x00000040L +#define SC_DEBUG_9__early_z_enable 0x00000040L +#define SC_DEBUG_9__mask_state_MASK 0x00000180L +#define SC_DEBUG_9__next_ez_mask_MASK 0x01fffe00L +#define SC_DEBUG_9__mask_ready_MASK 0x02000000L +#define SC_DEBUG_9__mask_ready 0x02000000L +#define SC_DEBUG_9__drop_sample_MASK 0x04000000L +#define SC_DEBUG_9__drop_sample 0x04000000L +#define SC_DEBUG_9__fetch_new_sample_data_MASK 0x08000000L +#define SC_DEBUG_9__fetch_new_sample_data 0x08000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK 0x10000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask 0x10000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK 0x40000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data 0x40000000L +#define SC_DEBUG_9__trigger_MASK 0x80000000L +#define SC_DEBUG_9__trigger 0x80000000L + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask_MASK 0x0000ffffL +#define SC_DEBUG_10__trigger_MASK 0x80000000L +#define SC_DEBUG_10__trigger 0x80000000L + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready_MASK 0x00000001L +#define SC_DEBUG_11__ez_sample_data_ready 0x00000001L +#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK 0x00000002L +#define SC_DEBUG_11__pkr_fetch_new_sample_data 0x00000002L +#define SC_DEBUG_11__ez_prim_data_ready_MASK 0x00000004L +#define SC_DEBUG_11__ez_prim_data_ready 0x00000004L +#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK 0x00000008L +#define SC_DEBUG_11__pkr_fetch_new_prim_data 0x00000008L +#define SC_DEBUG_11__iterator_input_fz_MASK 0x00000010L +#define SC_DEBUG_11__iterator_input_fz 0x00000010L +#define SC_DEBUG_11__packer_send_quads_MASK 0x00000020L +#define SC_DEBUG_11__packer_send_quads 0x00000020L +#define SC_DEBUG_11__packer_send_cmd_MASK 0x00000040L +#define SC_DEBUG_11__packer_send_cmd 0x00000040L +#define SC_DEBUG_11__packer_send_event_MASK 0x00000080L +#define SC_DEBUG_11__packer_send_event 0x00000080L +#define SC_DEBUG_11__next_state_MASK 0x00000700L +#define SC_DEBUG_11__state_MASK 0x00003800L +#define SC_DEBUG_11__stall_MASK 0x00004000L +#define SC_DEBUG_11__stall 0x00004000L +#define SC_DEBUG_11__trigger_MASK 0x80000000L +#define SC_DEBUG_11__trigger 0x80000000L + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff_MASK 0x00000001L +#define SC_DEBUG_12__SQ_iterator_free_buff 0x00000001L +#define SC_DEBUG_12__event_id_MASK 0x0000003eL +#define SC_DEBUG_12__event_flag_MASK 0x00000040L +#define SC_DEBUG_12__event_flag 0x00000040L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK 0x00000080L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly 0x00000080L +#define SC_DEBUG_12__itercmdfifo_full_MASK 0x00000100L +#define SC_DEBUG_12__itercmdfifo_full 0x00000100L +#define SC_DEBUG_12__itercmdfifo_empty_MASK 0x00000200L +#define SC_DEBUG_12__itercmdfifo_empty 0x00000200L +#define SC_DEBUG_12__iter_ds_one_clk_command_MASK 0x00000400L +#define SC_DEBUG_12__iter_ds_one_clk_command 0x00000400L +#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_prim0 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_vector_MASK 0x00001000L +#define SC_DEBUG_12__iter_ds_end_of_vector 0x00001000L +#define SC_DEBUG_12__iter_qdhit0_MASK 0x00002000L +#define SC_DEBUG_12__iter_qdhit0 0x00002000L +#define SC_DEBUG_12__bc_use_centers_reg_MASK 0x00004000L +#define SC_DEBUG_12__bc_use_centers_reg 0x00004000L +#define SC_DEBUG_12__bc_output_xy_reg_MASK 0x00008000L +#define SC_DEBUG_12__bc_output_xy_reg 0x00008000L +#define SC_DEBUG_12__iter_phase_out_MASK 0x00030000L +#define SC_DEBUG_12__iter_phase_reg_MASK 0x000c0000L +#define SC_DEBUG_12__iterator_SP_valid_MASK 0x00100000L +#define SC_DEBUG_12__iterator_SP_valid 0x00100000L +#define SC_DEBUG_12__eopv_reg_MASK 0x00200000L +#define SC_DEBUG_12__eopv_reg 0x00200000L +#define SC_DEBUG_12__one_clk_cmd_reg_MASK 0x00400000L +#define SC_DEBUG_12__one_clk_cmd_reg 0x00400000L +#define SC_DEBUG_12__iter_dx_end_of_prim_MASK 0x00800000L +#define SC_DEBUG_12__iter_dx_end_of_prim 0x00800000L +#define SC_DEBUG_12__trigger_MASK 0x80000000L +#define SC_DEBUG_12__trigger 0x80000000L + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define GFX_COPY_STATE__SRC_STATE_ID 0x00000001L + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK 0x0000003fL +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x000000c0L +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK 0x00000300L +#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK 0x00000800L +#define VGT_DRAW_INITIATOR__INDEX_SIZE 0x00000800L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00001000L +#define VGT_DRAW_INITIATOR__NOT_EOP 0x00001000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK 0x00002000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX 0x00002000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK 0x00004000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE 0x00004000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK 0x00008000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE 0x00008000L +#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK 0xffff0000L + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_DMA_SIZE__SWAP_MODE_MASK 0xc0000000L + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK 0xffffffffL + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_BIN_SIZE__FACENESS_FETCH_MASK 0x40000000L +#define VGT_BIN_SIZE__FACENESS_FETCH 0x40000000L +#define VGT_BIN_SIZE__FACENESS_RESET_MASK 0x80000000L +#define VGT_BIN_SIZE__FACENESS_RESET 0x80000000L + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK 0x000001c0L + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK 0x000001c0L + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0x00ffffffL + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0x00ffffffL + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0x00ffffffL + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x00000007L + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x00000003L + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0x00ffffffL + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC_MASK 0x0000ffffL + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000001fL + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define VGT_LAST_COPY_STATE__SRC_STATE_ID 0x00000001L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00010000L +#define VGT_LAST_COPY_STATE__DST_STATE_ID 0x00010000L + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000001fL + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_BUSY 0x00000001L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY 0x00000004L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY 0x00000008L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY 0x00000010L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY 0x00000020L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_PT_BUSY 0x00000040L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY 0x00000100L + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy_MASK 0x00000001L +#define VGT_DEBUG_REG0__te_grp_busy 0x00000001L +#define VGT_DEBUG_REG0__pt_grp_busy_MASK 0x00000002L +#define VGT_DEBUG_REG0__pt_grp_busy 0x00000002L +#define VGT_DEBUG_REG0__vr_grp_busy_MASK 0x00000004L +#define VGT_DEBUG_REG0__vr_grp_busy 0x00000004L +#define VGT_DEBUG_REG0__dma_request_busy_MASK 0x00000008L +#define VGT_DEBUG_REG0__dma_request_busy 0x00000008L +#define VGT_DEBUG_REG0__out_busy_MASK 0x00000010L +#define VGT_DEBUG_REG0__out_busy 0x00000010L +#define VGT_DEBUG_REG0__grp_backend_busy_MASK 0x00000020L +#define VGT_DEBUG_REG0__grp_backend_busy 0x00000020L +#define VGT_DEBUG_REG0__grp_busy_MASK 0x00000040L +#define VGT_DEBUG_REG0__grp_busy 0x00000040L +#define VGT_DEBUG_REG0__dma_busy_MASK 0x00000080L +#define VGT_DEBUG_REG0__dma_busy 0x00000080L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK 0x00000100L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy 0x00000100L +#define VGT_DEBUG_REG0__rbiu_busy_MASK 0x00000200L +#define VGT_DEBUG_REG0__rbiu_busy 0x00000200L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK 0x00000800L +#define VGT_DEBUG_REG0__vgt_no_dma_busy 0x00000800L +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_extended 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00002000L +#define VGT_DEBUG_REG0__vgt_busy 0x00002000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK 0x00004000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out 0x00004000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK 0x00010000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy 0x00010000L + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read_MASK 0x00000001L +#define VGT_DEBUG_REG1__out_te_data_read 0x00000001L +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x00000002L +#define VGT_DEBUG_REG1__te_out_data_valid 0x00000002L +#define VGT_DEBUG_REG1__out_pt_prim_read_MASK 0x00000004L +#define VGT_DEBUG_REG1__out_pt_prim_read 0x00000004L +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00000008L +#define VGT_DEBUG_REG1__pt_out_prim_valid 0x00000008L +#define VGT_DEBUG_REG1__out_pt_data_read_MASK 0x00000010L +#define VGT_DEBUG_REG1__out_pt_data_read 0x00000010L +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00000020L +#define VGT_DEBUG_REG1__pt_out_indx_valid 0x00000020L +#define VGT_DEBUG_REG1__out_vr_prim_read_MASK 0x00000040L +#define VGT_DEBUG_REG1__out_vr_prim_read 0x00000040L +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00000080L +#define VGT_DEBUG_REG1__vr_out_prim_valid 0x00000080L +#define VGT_DEBUG_REG1__out_vr_indx_read_MASK 0x00000100L +#define VGT_DEBUG_REG1__out_vr_indx_read 0x00000100L +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00000200L +#define VGT_DEBUG_REG1__vr_out_indx_valid 0x00000200L +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00000400L +#define VGT_DEBUG_REG1__te_grp_read 0x00000400L +#define VGT_DEBUG_REG1__grp_te_valid_MASK 0x00000800L +#define VGT_DEBUG_REG1__grp_te_valid 0x00000800L +#define VGT_DEBUG_REG1__pt_grp_read_MASK 0x00001000L +#define VGT_DEBUG_REG1__pt_grp_read 0x00001000L +#define VGT_DEBUG_REG1__grp_pt_valid_MASK 0x00002000L +#define VGT_DEBUG_REG1__grp_pt_valid 0x00002000L +#define VGT_DEBUG_REG1__vr_grp_read_MASK 0x00004000L +#define VGT_DEBUG_REG1__vr_grp_read 0x00004000L +#define VGT_DEBUG_REG1__grp_vr_valid_MASK 0x00008000L +#define VGT_DEBUG_REG1__grp_vr_valid 0x00008000L +#define VGT_DEBUG_REG1__grp_dma_read_MASK 0x00010000L +#define VGT_DEBUG_REG1__grp_dma_read 0x00010000L +#define VGT_DEBUG_REG1__dma_grp_valid_MASK 0x00020000L +#define VGT_DEBUG_REG1__dma_grp_valid 0x00020000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK 0x00040000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read 0x00040000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK 0x00080000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid 0x00080000L +#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG1__MH_VGT_rtr 0x00100000L +#define VGT_DEBUG_REG1__VGT_MH_send_MASK 0x00200000L +#define VGT_DEBUG_REG1__VGT_MH_send 0x00200000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK 0x00400000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr 0x00400000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK 0x00800000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send 0x00800000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr 0x01000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK 0x02000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send 0x02000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr 0x04000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK 0x08000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send 0x08000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr 0x10000000L +#define VGT_DEBUG_REG1__VGT_SQ_send_MASK 0x20000000L +#define VGT_DEBUG_REG1__VGT_SQ_send 0x20000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK 0x40000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q 0x40000000L + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en_MASK 0x00000001L +#define VGT_DEBUG_REG3__vgt_clk_en 0x00000001L +#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK 0x00000002L +#define VGT_DEBUG_REG3__reg_fifos_clk_en 0x00000002L + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG6__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG6__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG6__input_data_valid 0x00000400L +#define VGT_DEBUG_REG6__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG6__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG6__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG6__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG6__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG6__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG6__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG6__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG6__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG6__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG6__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG6__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG6__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG6__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG6__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG6__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG6__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG6__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG6__extract_vector 0x02000000L +#define VGT_DEBUG_REG6__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG6__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG6__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG6__destination_rtr 0x08000000L +#define VGT_DEBUG_REG6__grp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG6__grp_trigger 0x10000000L + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG7__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG7__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG7__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG8__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG8__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG8__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG8__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG9__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG9__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG9__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG9__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG9__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG9__grp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG9__grp_trigger 0x40000000L + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L +#define VGT_DEBUG_REG10__di_state_sel_q_MASK 0x00000010L +#define VGT_DEBUG_REG10__di_state_sel_q 0x00000010L +#define VGT_DEBUG_REG10__last_decr_of_packet_MASK 0x00000020L +#define VGT_DEBUG_REG10__last_decr_of_packet 0x00000020L +#define VGT_DEBUG_REG10__bin_valid_MASK 0x00000040L +#define VGT_DEBUG_REG10__bin_valid 0x00000040L +#define VGT_DEBUG_REG10__read_block_MASK 0x00000080L +#define VGT_DEBUG_REG10__read_block 0x00000080L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK 0x00000100L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read 0x00000100L +#define VGT_DEBUG_REG10__last_bit_enable_q_MASK 0x00000200L +#define VGT_DEBUG_REG10__last_bit_enable_q 0x00000200L +#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK 0x00000400L +#define VGT_DEBUG_REG10__last_bit_end_di_q 0x00000400L +#define VGT_DEBUG_REG10__selected_data_MASK 0x0007f800L +#define VGT_DEBUG_REG10__mask_input_data_MASK 0x07f80000L +#define VGT_DEBUG_REG10__gap_q_MASK 0x08000000L +#define VGT_DEBUG_REG10__gap_q 0x08000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK 0x40000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x 0x40000000L +#define VGT_DEBUG_REG10__grp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG10__grp_trigger 0x80000000L + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG12__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG12__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG12__input_data_valid 0x00000400L +#define VGT_DEBUG_REG12__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG12__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG12__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG12__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG12__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG12__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG12__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG12__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG12__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG12__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG12__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG12__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG12__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG12__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG12__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG12__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG12__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG12__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG12__extract_vector 0x02000000L +#define VGT_DEBUG_REG12__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG12__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG12__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG12__destination_rtr 0x08000000L +#define VGT_DEBUG_REG12__bgrp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG12__bgrp_trigger 0x10000000L + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG13__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG13__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG13__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG14__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG14__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG14__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG14__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG15__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG15__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG15__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG15__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG15__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG15__bgrp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG15__bgrp_trigger 0x40000000L + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty 0x00000002L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK 0x00000004L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read 0x00000004L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we 0x00000008L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK 0x00000080L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we 0x00000080L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK 0x00000100L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill 0x00000100L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK 0x00000200L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid 0x00000200L +#define VGT_DEBUG_REG16__rst_last_bit_MASK 0x00000400L +#define VGT_DEBUG_REG16__rst_last_bit 0x00000400L +#define VGT_DEBUG_REG16__current_state_q_MASK 0x00000800L +#define VGT_DEBUG_REG16__current_state_q 0x00000800L +#define VGT_DEBUG_REG16__old_state_q_MASK 0x00001000L +#define VGT_DEBUG_REG16__old_state_q 0x00001000L +#define VGT_DEBUG_REG16__old_state_en_MASK 0x00002000L +#define VGT_DEBUG_REG16__old_state_en 0x00002000L +#define VGT_DEBUG_REG16__prev_last_bit_q_MASK 0x00004000L +#define VGT_DEBUG_REG16__prev_last_bit_q 0x00004000L +#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK 0x00008000L +#define VGT_DEBUG_REG16__dbl_last_bit_q 0x00008000L +#define VGT_DEBUG_REG16__last_bit_block_q_MASK 0x00010000L +#define VGT_DEBUG_REG16__last_bit_block_q 0x00010000L +#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK 0x00020000L +#define VGT_DEBUG_REG16__ast_bit_block2_q 0x00020000L +#define VGT_DEBUG_REG16__load_empty_reg_MASK 0x00040000L +#define VGT_DEBUG_REG16__load_empty_reg 0x00040000L +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK 0x07f80000L +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable 0x20000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK 0x40000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q 0x40000000L +#define VGT_DEBUG_REG16__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG16__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q_MASK 0x00000001L +#define VGT_DEBUG_REG17__save_read_q 0x00000001L +#define VGT_DEBUG_REG17__extend_read_q_MASK 0x00000002L +#define VGT_DEBUG_REG17__extend_read_q 0x00000002L +#define VGT_DEBUG_REG17__grp_indx_size_MASK 0x0000000cL +#define VGT_DEBUG_REG17__cull_prim_true_MASK 0x00000010L +#define VGT_DEBUG_REG17__cull_prim_true 0x00000010L +#define VGT_DEBUG_REG17__reset_bit2_q_MASK 0x00000020L +#define VGT_DEBUG_REG17__reset_bit2_q 0x00000020L +#define VGT_DEBUG_REG17__reset_bit1_q_MASK 0x00000040L +#define VGT_DEBUG_REG17__reset_bit1_q 0x00000040L +#define VGT_DEBUG_REG17__first_reg_first_q_MASK 0x00000080L +#define VGT_DEBUG_REG17__first_reg_first_q 0x00000080L +#define VGT_DEBUG_REG17__check_second_reg_MASK 0x00000100L +#define VGT_DEBUG_REG17__check_second_reg 0x00000100L +#define VGT_DEBUG_REG17__check_first_reg_MASK 0x00000200L +#define VGT_DEBUG_REG17__check_first_reg 0x00000200L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK 0x00000400L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata 0x00000400L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK 0x00001000L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q 0x00001000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK 0x00004000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q 0x00004000L +#define VGT_DEBUG_REG17__to_second_reg_q_MASK 0x00008000L +#define VGT_DEBUG_REG17__to_second_reg_q 0x00008000L +#define VGT_DEBUG_REG17__roll_over_msk_q_MASK 0x00010000L +#define VGT_DEBUG_REG17__roll_over_msk_q 0x00010000L +#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK 0x00fe0000L +#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK 0x7f000000L +#define VGT_DEBUG_REG17__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG17__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK 0x0000003fL +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK 0x00000fc0L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000L +#define VGT_DEBUG_REG18__dma_mem_full_MASK 0x00008000L +#define VGT_DEBUG_REG18__dma_mem_full 0x00008000L +#define VGT_DEBUG_REG18__dma_ram_re_MASK 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_re 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_we_MASK 0x00020000L +#define VGT_DEBUG_REG18__dma_ram_we 0x00020000L +#define VGT_DEBUG_REG18__dma_mem_empty_MASK 0x00040000L +#define VGT_DEBUG_REG18__dma_mem_empty 0x00040000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK 0x00100000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we 0x00100000L +#define VGT_DEBUG_REG18__bin_mem_full_MASK 0x00200000L +#define VGT_DEBUG_REG18__bin_mem_full 0x00200000L +#define VGT_DEBUG_REG18__bin_ram_we_MASK 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_we 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_re_MASK 0x00800000L +#define VGT_DEBUG_REG18__bin_ram_re 0x00800000L +#define VGT_DEBUG_REG18__bin_mem_empty_MASK 0x01000000L +#define VGT_DEBUG_REG18__bin_mem_empty 0x01000000L +#define VGT_DEBUG_REG18__start_bin_req_MASK 0x02000000L +#define VGT_DEBUG_REG18__start_bin_req 0x02000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK 0x04000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used 0x04000000L +#define VGT_DEBUG_REG18__dma_req_xfer_MASK 0x08000000L +#define VGT_DEBUG_REG18__dma_req_xfer 0x08000000L +#define VGT_DEBUG_REG18__have_valid_bin_req_MASK 0x10000000L +#define VGT_DEBUG_REG18__have_valid_bin_req 0x10000000L +#define VGT_DEBUG_REG18__have_valid_dma_req_MASK 0x20000000L +#define VGT_DEBUG_REG18__have_valid_dma_req 0x20000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK 0x00000001L +#define VGT_DEBUG_REG20__prim_side_indx_valid 0x00000001L +#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_empty 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_re 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_we 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG20__indx_side_fifo_full 0x00000010L +#define VGT_DEBUG_REG20__prim_buffer_empty_MASK 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_empty 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_re_MASK 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_re 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_we_MASK 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_we 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_full_MASK 0x00000100L +#define VGT_DEBUG_REG20__prim_buffer_full 0x00000100L +#define VGT_DEBUG_REG20__indx_buffer_empty_MASK 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_empty 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_re_MASK 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_re 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_we_MASK 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_we 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_full_MASK 0x00001000L +#define VGT_DEBUG_REG20__indx_buffer_full 0x00001000L +#define VGT_DEBUG_REG20__hold_prim_MASK 0x00002000L +#define VGT_DEBUG_REG20__hold_prim 0x00002000L +#define VGT_DEBUG_REG20__sent_cnt_MASK 0x0003c000L +#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK 0x00040000L +#define VGT_DEBUG_REG20__start_of_vtx_vector 0x00040000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK 0x00080000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim 0x00080000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK 0x00100000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim 0x00100000L +#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK 0x03e00000L +#define VGT_DEBUG_REG20__out_trigger_MASK 0x04000000L +#define VGT_DEBUG_REG20__out_trigger 0x04000000L + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK 0x00000001L +#define VGT_DEBUG_REG21__null_terminate_vtx_vector 0x00000001L +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK 0x0000000eL +#define VGT_DEBUG_REG21__alloc_counter_q_MASK 0x00000070L +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK 0x00000380L +#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK 0x00003c00L +#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK 0x0003c000L +#define VGT_DEBUG_REG21__new_packet_q_MASK 0x00040000L +#define VGT_DEBUG_REG21__new_packet_q 0x00040000L +#define VGT_DEBUG_REG21__new_allocate_q_MASK 0x00080000L +#define VGT_DEBUG_REG21__new_allocate_q 0x00080000L +#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK 0x00300000L +#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK 0x00400000L +#define VGT_DEBUG_REG21__inserted_null_prim_q 0x00400000L +#define VGT_DEBUG_REG21__insert_null_prim_MASK 0x00800000L +#define VGT_DEBUG_REG21__insert_null_prim 0x00800000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK 0x01000000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux 0x01000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK 0x02000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux 0x02000000L +#define VGT_DEBUG_REG21__buffered_thread_size_MASK 0x04000000L +#define VGT_DEBUG_REG21__buffered_thread_size 0x04000000L +#define VGT_DEBUG_REG21__out_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG21__out_trigger 0x80000000L + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC_MASK 0xffffffffL + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE_MASK 0x00000001L +#define TC_CNTL_STATUS__L2_INVALIDATE 0x00000001L +#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK 0x000c0000L +#define TC_CNTL_STATUS__TC_BUSY_MASK 0x80000000L +#define TC_CNTL_STATUS__TC_BUSY 0x80000000L + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE_MASK 0xffffffffL + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE_MASK 0xffffffffL + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL +#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK 0x00000100L +#define TCM_CHICKEN__ETC_COLOR_ENDIAN 0x00000100L +#define TCM_CHICKEN__SPARE_MASK 0xfffffe00L + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK 0x00000007L +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK 0x00000038L + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK 0x00000001L +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY 0x00000001L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK 0x00000002L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY 0x00000002L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK 0x00000004L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY 0x00000004L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK 0x00000008L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY 0x00000008L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK 0x00000040L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY 0x00000040L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK 0x00000400L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY 0x00000400L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK 0x00001000L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY 0x00001000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK 0x00002000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY 0x00002000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK 0x00004000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY 0x00004000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK 0x00008000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY 0x00008000L +#define TPC_CNTL_STATUS__TF_TW_RTS_MASK 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_RTS 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_RTR_MASK 0x00080000L +#define TPC_CNTL_STATUS__TF_TW_RTR 0x00080000L +#define TPC_CNTL_STATUS__TW_TA_RTS_MASK 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_RTS 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_RTR_MASK 0x00800000L +#define TPC_CNTL_STATUS__TW_TA_RTR 0x00800000L +#define TPC_CNTL_STATUS__TA_TB_RTS_MASK 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_RTS 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_RTR_MASK 0x08000000L +#define TPC_CNTL_STATUS__TA_TB_RTR 0x08000000L +#define TPC_CNTL_STATUS__TA_TF_RTS_MASK 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_RTS 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK 0x20000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN 0x20000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK 0x40000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC 0x40000000L +#define TPC_CNTL_STATUS__TPC_BUSY_MASK 0x80000000L +#define TPC_CNTL_STATUS__TPC_BUSY 0x80000000L + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL_MASK 0x00000003L +#define TPC_DEBUG0__IC_CTR_MASK 0x0000000cL +#define TPC_DEBUG0__WALKER_CNTL_MASK 0x000000f0L +#define TPC_DEBUG0__ALIGNER_CNTL_MASK 0x00000700L +#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK 0x00001000L +#define TPC_DEBUG0__PREV_TC_STATE_VALID 0x00001000L +#define TPC_DEBUG0__WALKER_STATE_MASK 0x03ff0000L +#define TPC_DEBUG0__ALIGNER_STATE_MASK 0x0c000000L +#define TPC_DEBUG0__REG_CLK_EN_MASK 0x20000000L +#define TPC_DEBUG0__REG_CLK_EN 0x20000000L +#define TPC_DEBUG0__TPC_CLK_EN_MASK 0x40000000L +#define TPC_DEBUG0__TPC_CLK_EN 0x40000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK 0x80000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP 0x80000000L + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED_MASK 0x00000001L +#define TPC_DEBUG1__UNUSED 0x00000001L + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION_MASK 0x00000001L +#define TPC_CHICKEN__BLEND_PRECISION 0x00000001L +#define TPC_CHICKEN__SPARE_MASK 0xfffffffeL + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK 0x00000001L +#define TP0_CNTL_STATUS__TP_INPUT_BUSY 0x00000001L +#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_BUSY 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK 0x00000004L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY 0x00000004L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK 0x00000008L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY 0x00000008L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK 0x00000020L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY 0x00000020L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK 0x00000040L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY 0x00000040L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK 0x00000080L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY 0x00000080L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK 0x00000100L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY 0x00000100L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK 0x00000200L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY 0x00000200L +#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK 0x00000400L +#define TP0_CNTL_STATUS__TP_TT_BUSY 0x00000400L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK 0x00000800L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY 0x00000800L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK 0x00001000L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY 0x00001000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK 0x00002000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY 0x00002000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK 0x00004000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY 0x00004000L +#define TP0_CNTL_STATUS__IN_LC_RTS_MASK 0x00010000L +#define TP0_CNTL_STATUS__IN_LC_RTS 0x00010000L +#define TP0_CNTL_STATUS__LC_LA_RTS_MASK 0x00020000L +#define TP0_CNTL_STATUS__LC_LA_RTS 0x00020000L +#define TP0_CNTL_STATUS__LA_FL_RTS_MASK 0x00040000L +#define TP0_CNTL_STATUS__LA_FL_RTS 0x00040000L +#define TP0_CNTL_STATUS__FL_TA_RTS_MASK 0x00080000L +#define TP0_CNTL_STATUS__FL_TA_RTS 0x00080000L +#define TP0_CNTL_STATUS__TA_FA_RTS_MASK 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_RTS 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK 0x00200000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS 0x00200000L +#define TP0_CNTL_STATUS__FA_AL_RTS_MASK 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_RTS 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK 0x00800000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS 0x00800000L +#define TP0_CNTL_STATUS__AL_TF_RTS_MASK 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_RTS 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK 0x02000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS 0x02000000L +#define TP0_CNTL_STATUS__TF_TB_RTS_MASK 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_RTS 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK 0x08000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS 0x08000000L +#define TP0_CNTL_STATUS__TB_TT_RTS_MASK 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_RTS 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK 0x20000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET 0x20000000L +#define TP0_CNTL_STATUS__TB_TO_RTS_MASK 0x40000000L +#define TP0_CNTL_STATUS__TB_TO_RTS 0x40000000L +#define TP0_CNTL_STATUS__TP_BUSY_MASK 0x80000000L +#define TP0_CNTL_STATUS__TP_BUSY 0x80000000L + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL_MASK 0x00000003L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK 0x00000008L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP 0x00000008L +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0L +#define TP0_DEBUG__REG_CLK_EN_MASK 0x00200000L +#define TP0_DEBUG__REG_CLK_EN 0x00200000L +#define TP0_DEBUG__PERF_CLK_EN_MASK 0x00400000L +#define TP0_DEBUG__PERF_CLK_EN 0x00400000L +#define TP0_DEBUG__TP_CLK_EN_MASK 0x00800000L +#define TP0_DEBUG__TP_CLK_EN 0x00800000L +#define TP0_DEBUG__Q_WALKER_CNTL_MASK 0x0f000000L +#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK 0x70000000L + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE_MASK 0x00000001L +#define TP0_CHICKEN__TT_MODE 0x00000001L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK 0x00000002L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE 0x00000002L +#define TP0_CHICKEN__SPARE_MASK 0xfffffffcL + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr_MASK 0x00000040L +#define TCF_DEBUG__not_MH_TC_rtr 0x00000040L +#define TCF_DEBUG__TC_MH_send_MASK 0x00000080L +#define TCF_DEBUG__TC_MH_send 0x00000080L +#define TCF_DEBUG__not_FG0_rtr_MASK 0x00000100L +#define TCF_DEBUG__not_FG0_rtr 0x00000100L +#define TCF_DEBUG__not_TCB_TCO_rtr_MASK 0x00001000L +#define TCF_DEBUG__not_TCB_TCO_rtr 0x00001000L +#define TCF_DEBUG__TCB_ff_stall_MASK 0x00002000L +#define TCF_DEBUG__TCB_ff_stall 0x00002000L +#define TCF_DEBUG__TCB_miss_stall_MASK 0x00004000L +#define TCF_DEBUG__TCB_miss_stall 0x00004000L +#define TCF_DEBUG__TCA_TCB_stall_MASK 0x00008000L +#define TCF_DEBUG__TCA_TCB_stall 0x00008000L +#define TCF_DEBUG__PF0_stall_MASK 0x00010000L +#define TCF_DEBUG__PF0_stall 0x00010000L +#define TCF_DEBUG__TP0_full_MASK 0x00100000L +#define TCF_DEBUG__TP0_full 0x00100000L +#define TCF_DEBUG__TPC_full_MASK 0x01000000L +#define TCF_DEBUG__TPC_full 0x01000000L +#define TCF_DEBUG__not_TPC_rtr_MASK 0x02000000L +#define TCF_DEBUG__not_TPC_rtr 0x02000000L +#define TCF_DEBUG__tca_state_rts_MASK 0x04000000L +#define TCF_DEBUG__tca_state_rts 0x04000000L +#define TCF_DEBUG__tca_rts_MASK 0x08000000L +#define TCF_DEBUG__tca_rts 0x08000000L + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full_MASK 0x00000001L +#define TCA_FIFO_DEBUG__tp0_full 0x00000001L +#define TCA_FIFO_DEBUG__tpc_full_MASK 0x00000010L +#define TCA_FIFO_DEBUG__tpc_full 0x00000010L +#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK 0x00000020L +#define TCA_FIFO_DEBUG__load_tpc_fifo 0x00000020L +#define TCA_FIFO_DEBUG__load_tp_fifos_MASK 0x00000040L +#define TCA_FIFO_DEBUG__load_tp_fifos 0x00000040L +#define TCA_FIFO_DEBUG__FW_full_MASK 0x00000080L +#define TCA_FIFO_DEBUG__FW_full 0x00000080L +#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK 0x00000100L +#define TCA_FIFO_DEBUG__not_FW_rtr0 0x00000100L +#define TCA_FIFO_DEBUG__FW_rts0_MASK 0x00001000L +#define TCA_FIFO_DEBUG__FW_rts0 0x00001000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK 0x00010000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr 0x00010000L +#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK 0x00020000L +#define TCA_FIFO_DEBUG__FW_tpc_rts 0x00020000L + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK 0x00000001L +#define TCA_PROBE_DEBUG__ProbeFilter_stall 0x00000001L + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts_MASK 0x00001000L +#define TCA_TPC_DEBUG__captue_state_rts 0x00001000L +#define TCA_TPC_DEBUG__capture_tca_rts_MASK 0x00002000L +#define TCA_TPC_DEBUG__capture_tca_rts 0x00002000L + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512_MASK 0x00000001L +#define TCB_CORE_DEBUG__access512 0x00000001L +#define TCB_CORE_DEBUG__tiled_MASK 0x00000002L +#define TCB_CORE_DEBUG__tiled 0x00000002L +#define TCB_CORE_DEBUG__opcode_MASK 0x00000070L +#define TCB_CORE_DEBUG__format_MASK 0x00003f00L +#define TCB_CORE_DEBUG__sector_format_MASK 0x001f0000L +#define TCB_CORE_DEBUG__sector_format512_MASK 0x07000000L + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG0_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG0_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG0_DEBUG__miss_stall 0x00800000L +#define TCB_TAG0_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG0_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG1_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG1_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG1_DEBUG__miss_stall 0x00800000L +#define TCB_TAG1_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG1_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG2_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG2_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG2_DEBUG__miss_stall 0x00800000L +#define TCB_TAG2_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG2_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG3_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG3_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG3_DEBUG__miss_stall 0x00800000L +#define TCB_TAG3_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG3_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q 0x10000000L + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK 0x00000030L +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK 0x000000c0L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK 0x00007000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK 0x000f0000L + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK 0x0000fff0L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK 0x001f0000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK 0x0c000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK 0x40000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR 0x40000000L + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty_MASK 0x00010000L +#define TCD_INPUT0_DEBUG__empty 0x00010000L +#define TCD_INPUT0_DEBUG__full_MASK 0x00020000L +#define TCD_INPUT0_DEBUG__full 0x00020000L +#define TCD_INPUT0_DEBUG__valid_q1_MASK 0x00100000L +#define TCD_INPUT0_DEBUG__valid_q1 0x00100000L +#define TCD_INPUT0_DEBUG__cnt_q1_MASK 0x00600000L +#define TCD_INPUT0_DEBUG__last_send_q1_MASK 0x00800000L +#define TCD_INPUT0_DEBUG__last_send_q1 0x00800000L +#define TCD_INPUT0_DEBUG__ip_send_MASK 0x01000000L +#define TCD_INPUT0_DEBUG__ip_send 0x01000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK 0x04000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy 0x04000000L + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK 0x00000003L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_stall 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK 0x00000040L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate 0x00000040L + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__pstate 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK 0x20000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send 0x20000000L + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK 0x00000010L +#define TCD_DXTC_ARB_DEBUG__n0_stall 0x00000010L +#define TCD_DXTC_ARB_DEBUG__pstate_MASK 0x00000020L +#define TCD_DXTC_ARB_DEBUG__pstate 0x00000020L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK 0x00000180L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK 0x00000e00L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK 0x0003f000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK 0x3ffc0000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK 0x40000000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send 0x40000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK 0x80000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types 0x80000000L + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK 0x00000400L +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr 0x00000400L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK 0x00000800L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr 0x00000800L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK 0x00020000L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr 0x00020000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK 0x00040000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr 0x00040000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK 0x00080000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr 0x00080000L +#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK 0x80000000L +#define TCD_STALLS_DEBUG__not_incoming_rtr 0x80000000L + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK 0x00000020L +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR 0x00000020L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK 0x00000040L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR 0x00000040L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK 0x00000080L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d 0x00000080L + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK 0x000000ffL +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK 0x00000400L +#define TCO_QUAD0_DEBUG0__rl_sg_rts 0x00000400L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK 0x00002000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts 0x00002000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK 0x00010000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q 0x00010000L +#define TCO_QUAD0_DEBUG0__read_cache_q_MASK 0x01000000L +#define TCO_QUAD0_DEBUG0__read_cache_q 0x01000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK 0x02000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR 0x02000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK 0x20000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0 0x20000000L +#define TCO_QUAD0_DEBUG0__busy_MASK 0x40000000L +#define TCO_QUAD0_DEBUG0__busy 0x40000000L + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy_MASK 0x00000001L +#define TCO_QUAD0_DEBUG1__fifo_busy 0x00000001L +#define TCO_QUAD0_DEBUG1__empty_MASK 0x00000002L +#define TCO_QUAD0_DEBUG1__empty 0x00000002L +#define TCO_QUAD0_DEBUG1__full_MASK 0x00000004L +#define TCO_QUAD0_DEBUG1__full 0x00000004L +#define TCO_QUAD0_DEBUG1__write_enable_MASK 0x00000008L +#define TCO_QUAD0_DEBUG1__write_enable 0x00000008L +#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK 0x000007f0L +#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK 0x0003f800L +#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK 0x00100000L +#define TCO_QUAD0_DEBUG1__cache_read_busy 0x00100000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK 0x00200000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy 0x00200000L +#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK 0x00400000L +#define TCO_QUAD0_DEBUG1__input_quad_busy 0x00400000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK 0x00800000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy 0x00800000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK 0x02000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q 0x02000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK 0x08000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts 0x08000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK 0x20000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts 0x20000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK 0x40000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc 0x40000000L + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK 0x000007f0L +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK 0x0007f000L + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK 0x00000003L +#define SQ_FLOW_CONTROL__ONE_THREAD_MASK 0x00000010L +#define SQ_FLOW_CONTROL__ONE_THREAD 0x00000010L +#define SQ_FLOW_CONTROL__ONE_ALU_MASK 0x00000100L +#define SQ_FLOW_CONTROL__ONE_ALU 0x00000100L +#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK 0x0000f000L +#define SQ_FLOW_CONTROL__NO_PV_PS_MASK 0x00010000L +#define SQ_FLOW_CONTROL__NO_PV_PS 0x00010000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK 0x00020000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT 0x00020000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK 0x00040000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE 0x00040000L +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK 0x00180000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK 0x00200000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY 0x00200000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK 0x00400000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY 0x00400000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK 0x00800000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT 0x00800000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK 0x01000000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT 0x01000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK 0x02000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY 0x02000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK 0x04000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION 0x04000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC 0x08000000L + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK 0x00000fffL +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK 0x0fff0000L + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK 0x01ff0000L + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT_MASK 0x000000ffL +#define SQ_EO_RT__EO_TSTATE_RT_MASK 0x00ff0000L + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK 0x000007ffL +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK 0x000ff000L +#define SQ_DEBUG_MISC__DB_READ_CTX_MASK 0x00100000L +#define SQ_DEBUG_MISC__DB_READ_CTX 0x00100000L +#define SQ_DEBUG_MISC__RESERVED_MASK 0x00600000L +#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK 0x01800000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK 0x10000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3 0x10000000L + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK 0x000000ffL +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK 0x0000ff00L +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK 0x00ff0000L +#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK 0xff000000L + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK 0x000000ffL + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L +#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK 0x000c0000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK 0x00000001L +#define SQ_INT_CNTL__PS_WATCHDOG_MASK 0x00000001L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK 0x00000002L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK 0x00000002L + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK 0x00000001L +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT 0x00000001L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK 0x00000002L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT 0x00000002L + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK 0x00000001L +#define SQ_INT_ACK__PS_WATCHDOG_ACK 0x00000001L +#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK 0x00000002L +#define SQ_INT_ACK__VS_WATCHDOG_ACK 0x00000002L + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK 0x00000007L +#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK 0x00000008L +#define SQ_DEBUG_INPUT_FSM__RESERVED 0x00000008L +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK 0x000000f0L +#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK 0x00000700L +#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_INPUT_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK 0x00007000L +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK 0x000f8000L +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK 0x0ff00000L + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK 0x000000e0L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK 0x0000e000L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK 0x00030000L +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK 0x000c0000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK 0x00800000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE 0x00800000L + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP_MASK 0x00000007L +#define SQ_DEBUG_TP_FSM__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_TP_FSM__RESERVED0 0x00000008L +#define SQ_DEBUG_TP_FSM__CF_TP_MASK 0x000000f0L +#define SQ_DEBUG_TP_FSM__IF_TP_MASK 0x00000700L +#define SQ_DEBUG_TP_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_TP_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_TP_FSM__TIS_TP_MASK 0x00003000L +#define SQ_DEBUG_TP_FSM__RESERVED2_MASK 0x0000c000L +#define SQ_DEBUG_TP_FSM__GS_TP_MASK 0x00030000L +#define SQ_DEBUG_TP_FSM__RESERVED3_MASK 0x000c0000L +#define SQ_DEBUG_TP_FSM__FCR_TP_MASK 0x00300000L +#define SQ_DEBUG_TP_FSM__RESERVED4_MASK 0x00c00000L +#define SQ_DEBUG_TP_FSM__FCS_TP_MASK 0x03000000L +#define SQ_DEBUG_TP_FSM__RESERVED5_MASK 0x0c000000L +#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK 0x0000000fL +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK 0x00000ff0L +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK 0x00007000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000L + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK 0x00000001L +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER 0x00000001L +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK 0x0000001eL +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK 0x00000020L +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR 0x00000020L +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK 0x000001c0L +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK 0x00003e00L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK 0x00004000L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT 0x00004000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK 0x00008000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON 0x00008000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK 0x00010000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY 0x00010000L +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK 0x0ffe0000L + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_VTX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_VTX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_VTX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_VTX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_PIX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_PIX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_PIX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_PIX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK 0x60000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC 0x80000000L + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK 0x0000000fL +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK 0x000000f0L +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK 0x00000f00L +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK 0x0000f000L +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK 0x000f0000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK 0x00100000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL 0x00100000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK 0x00200000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q 0x00200000L + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK 0x0000ffffL + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK 0xffffffffL + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK 0x0000003fL +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK 0x00000fc0L +#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK 0x0007f000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK 0x01f80000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK 0x7e000000L +#define SQ_DEBUG_PIX_TB_0__BUSY_MASK 0x80000000L +#define SQ_DEBUG_PIX_TB_0__BUSY 0x80000000L + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL 0x00000040L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP 0x00000080L +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL 0x00004000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA 0x00008000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK 0x000f0000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK 0x00f00000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP 0x01000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK 0xfc000000L + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK 0x00000003L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK 0x0000000cL +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK 0x00000030L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK 0x000000c0L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK 0x00000300L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK 0x00000c00L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK 0x00003000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK 0x0000c000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK 0x00030000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK 0x000c0000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK 0x00300000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK 0x00c00000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK 0x04000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD 0x04000000L +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK 0x18000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR 0x20000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS 0x80000000L + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C 0x00000080L +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B 0x00008000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK 0x003f0000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK 0x00800000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A 0x00800000L +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK 0x1f000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK 0x000001ffL +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK 0x00000e00L +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK 0x00007000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK 0x01ff0000L +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK 0x0e000000L +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK 0x70000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK 0x0000fc00L +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK 0x001f0000L +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK 0xffe00000L + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK 0x000007ffL +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK 0xfc000000L + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK 0x0000001fL +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK 0x07ffffe0L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK 0x00001c00L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK 0xffff8000L + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK 0x1c000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK 0xc0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK 0x0001ffffL +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK 0x0000000fL +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK 0xfffffff0L + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK 0x000000ffL +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK 0x00000600L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK 0x000f0000L +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK 0xfff00000L + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK 0x00ffffffL +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK 0x06000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK 0x30000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK 0xc0000000L + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK 0x00003000L +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK 0x0000c000L +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK 0x00030000L +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK 0x001c0000L +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK 0x00e00000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK 0x03000000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK 0x60000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK 0x000001fcL +#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK 0x0000fe00L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK 0x001f0000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK 0x03e00000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK 0x7c000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK 0x06000000L +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK 0xc0000000L + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK 0x003f0000L +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK 0x3f800000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK 0x000000ffL +#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK 0x00ff0000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE_MASK 0x00000001L +#define SQ_CONSTANT_VFETCH_0__TYPE 0x00000001L +#define SQ_CONSTANT_VFETCH_0__STATE_MASK 0x00000002L +#define SQ_CONSTANT_VFETCH_0__STATE 0x00000002L +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK 0x00000003L +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE_MASK 0xffffffffL + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE_MASK 0xffffffffL + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_VS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_PS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK 0x000007ffL +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK 0x007ff000L + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK 0x0000ffffL +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK 0xffff0000L + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK 0x0000003fL +#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK 0x00003f00L +#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK 0x00010000L +#define SQ_PROGRAM_CNTL__VS_RESOURCE 0x00010000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK 0x00020000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE 0x00020000L +#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK 0x00040000L +#define SQ_PROGRAM_CNTL__PARAM_GEN 0x00040000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK 0x00080000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX 0x00080000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK 0x00f00000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK 0x07000000L +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK 0x78000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK 0x80000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX 0x80000000L + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK 0x0000000fL +#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK 0x000000f0L +#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK 0x00000f00L +#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK 0x0000f000L +#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK 0x000f0000L +#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK 0x00f00000L +#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK 0x0f000000L +#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK 0xf0000000L + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK 0x0000000fL +#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK 0x000000f0L +#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK 0x00000f00L +#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK 0x0000f000L +#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK 0x000f0000L +#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK 0x00f00000L +#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK 0x0f000000L +#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK 0xf0000000L + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE_MASK 0x000001ffL +#define SQ_VS_CONST__SIZE_MASK 0x001ff000L + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE_MASK 0x000001ffL +#define SQ_PS_CONST__SIZE_MASK 0x001ff000L + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK 0x00000001L +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE 0x00000001L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK 0x00000002L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY 0x00000002L +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK 0x0000000cL +#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK 0x0000ff00L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK 0x00010000L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF 0x00010000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK 0x00020000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE 0x00020000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK 0x00040000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL 0x00040000L + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE_MASK 0x00000007L + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_ON 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK 0x0007ff00L +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK 0xff000000L + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_PIX 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK 0x00000002L +#define SQ_DEBUG_MISC_1__DB_ON_VTX 0x00000002L +#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK 0x0000ff00L +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK 0x07ff0000L + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK 0x0000003fL +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK 0x00000040L +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY 0x00000040L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK 0x00000100L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE 0x00000100L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK 0x00000200L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL 0x00000200L +#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK 0x00001c00L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK 0x00002000L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE 0x00002000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK 0x00004000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE 0x00004000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK 0x003f0000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK 0x00400000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE 0x00400000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK 0x00800000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE 0x00800000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK 0x01000000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE 0x01000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK 0x02000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE 0x02000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK 0x04000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE 0x04000000L + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK 0x00000007L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK 0x00000070L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK 0x00000700L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK 0x00007000L + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_MASK__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT 0x00000004L + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID_MASK 0x00000007L +#define MH_AXI_ERROR__AXI_READ_ERROR_MASK 0x00000008L +#define MH_AXI_ERROR__AXI_READ_ERROR 0x00000008L +#define MH_AXI_ERROR__AXI_WRITE_ID_MASK 0x00000070L +#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK 0x00000080L +#define MH_AXI_ERROR__AXI_WRITE_ERROR 0x00000080L + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX_MASK 0x0000003fL + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA_MASK 0xffffffffL + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK 0x00000001L +#define MH_AXI_HALT_CONTROL__AXI_HALT 0x00000001L + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY_MASK 0x00000001L +#define MH_DEBUG_REG00__MH_BUSY 0x00000001L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK 0x00000002L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING 0x00000002L +#define MH_DEBUG_REG00__CP_REQUEST_MASK 0x00000004L +#define MH_DEBUG_REG00__CP_REQUEST 0x00000004L +#define MH_DEBUG_REG00__VGT_REQUEST_MASK 0x00000008L +#define MH_DEBUG_REG00__VGT_REQUEST 0x00000008L +#define MH_DEBUG_REG00__TC_REQUEST_MASK 0x00000010L +#define MH_DEBUG_REG00__TC_REQUEST 0x00000010L +#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_EMPTY 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_FULL_MASK 0x00000040L +#define MH_DEBUG_REG00__TC_CAM_FULL 0x00000040L +#define MH_DEBUG_REG00__TCD_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG00__TCD_EMPTY 0x00000080L +#define MH_DEBUG_REG00__TCD_FULL_MASK 0x00000100L +#define MH_DEBUG_REG00__TCD_FULL 0x00000100L +#define MH_DEBUG_REG00__RB_REQUEST_MASK 0x00000200L +#define MH_DEBUG_REG00__RB_REQUEST 0x00000200L +#define MH_DEBUG_REG00__PA_REQUEST_MASK 0x00000400L +#define MH_DEBUG_REG00__PA_REQUEST 0x00000400L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK 0x00000800L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE 0x00000800L +#define MH_DEBUG_REG00__ARQ_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG00__ARQ_EMPTY 0x00001000L +#define MH_DEBUG_REG00__ARQ_FULL_MASK 0x00002000L +#define MH_DEBUG_REG00__ARQ_FULL 0x00002000L +#define MH_DEBUG_REG00__WDB_EMPTY_MASK 0x00004000L +#define MH_DEBUG_REG00__WDB_EMPTY 0x00004000L +#define MH_DEBUG_REG00__WDB_FULL_MASK 0x00008000L +#define MH_DEBUG_REG00__WDB_FULL 0x00008000L +#define MH_DEBUG_REG00__AXI_AVALID_MASK 0x00010000L +#define MH_DEBUG_REG00__AXI_AVALID 0x00010000L +#define MH_DEBUG_REG00__AXI_AREADY_MASK 0x00020000L +#define MH_DEBUG_REG00__AXI_AREADY 0x00020000L +#define MH_DEBUG_REG00__AXI_ARVALID_MASK 0x00040000L +#define MH_DEBUG_REG00__AXI_ARVALID 0x00040000L +#define MH_DEBUG_REG00__AXI_ARREADY_MASK 0x00080000L +#define MH_DEBUG_REG00__AXI_ARREADY 0x00080000L +#define MH_DEBUG_REG00__AXI_WVALID_MASK 0x00100000L +#define MH_DEBUG_REG00__AXI_WVALID 0x00100000L +#define MH_DEBUG_REG00__AXI_WREADY_MASK 0x00200000L +#define MH_DEBUG_REG00__AXI_WREADY 0x00200000L +#define MH_DEBUG_REG00__AXI_RVALID_MASK 0x00400000L +#define MH_DEBUG_REG00__AXI_RVALID 0x00400000L +#define MH_DEBUG_REG00__AXI_RREADY_MASK 0x00800000L +#define MH_DEBUG_REG00__AXI_RREADY 0x00800000L +#define MH_DEBUG_REG00__AXI_BVALID_MASK 0x01000000L +#define MH_DEBUG_REG00__AXI_BVALID 0x01000000L +#define MH_DEBUG_REG00__AXI_BREADY_MASK 0x02000000L +#define MH_DEBUG_REG00__AXI_BREADY 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK 0x08000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK 0x08000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK 0x10000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA 0x10000000L + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q_MASK 0x00000001L +#define MH_DEBUG_REG01__CP_SEND_q 0x00000001L +#define MH_DEBUG_REG01__CP_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG01__CP_RTR_q 0x00000002L +#define MH_DEBUG_REG01__CP_WRITE_q_MASK 0x00000004L +#define MH_DEBUG_REG01__CP_WRITE_q 0x00000004L +#define MH_DEBUG_REG01__CP_TAG_q_MASK 0x00000038L +#define MH_DEBUG_REG01__CP_BLEN_q_MASK 0x00000040L +#define MH_DEBUG_REG01__CP_BLEN_q 0x00000040L +#define MH_DEBUG_REG01__VGT_SEND_q_MASK 0x00000080L +#define MH_DEBUG_REG01__VGT_SEND_q 0x00000080L +#define MH_DEBUG_REG01__VGT_RTR_q_MASK 0x00000100L +#define MH_DEBUG_REG01__VGT_RTR_q 0x00000100L +#define MH_DEBUG_REG01__VGT_TAG_q_MASK 0x00000200L +#define MH_DEBUG_REG01__VGT_TAG_q 0x00000200L +#define MH_DEBUG_REG01__TC_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG01__TC_SEND_q 0x00000400L +#define MH_DEBUG_REG01__TC_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG01__TC_RTR_q 0x00000800L +#define MH_DEBUG_REG01__TC_BLEN_q_MASK 0x00001000L +#define MH_DEBUG_REG01__TC_BLEN_q 0x00001000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK 0x00004000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q 0x00004000L +#define MH_DEBUG_REG01__TC_MH_written_MASK 0x00008000L +#define MH_DEBUG_REG01__TC_MH_written 0x00008000L +#define MH_DEBUG_REG01__RB_SEND_q_MASK 0x00010000L +#define MH_DEBUG_REG01__RB_SEND_q 0x00010000L +#define MH_DEBUG_REG01__RB_RTR_q_MASK 0x00020000L +#define MH_DEBUG_REG01__RB_RTR_q 0x00020000L +#define MH_DEBUG_REG01__PA_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG01__PA_SEND_q 0x00040000L +#define MH_DEBUG_REG01__PA_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG01__PA_RTR_q 0x00080000L + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG02__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG02__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG02__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG02__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_rlast 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_tag_MASK 0x00000070L +#define MH_DEBUG_REG02__RDC_RID_MASK 0x00000380L +#define MH_DEBUG_REG02__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG02__MH_CP_writeclean_MASK 0x00001000L +#define MH_DEBUG_REG02__MH_CP_writeclean 0x00001000L +#define MH_DEBUG_REG02__MH_RB_writeclean_MASK 0x00002000L +#define MH_DEBUG_REG02__MH_RB_writeclean 0x00002000L +#define MH_DEBUG_REG02__MH_PA_writeclean_MASK 0x00004000L +#define MH_DEBUG_REG02__MH_PA_writeclean 0x00004000L +#define MH_DEBUG_REG02__BRC_BID_MASK 0x00038000L +#define MH_DEBUG_REG02__BRC_BRESP_MASK 0x000c0000L + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG05__CP_MH_send 0x00000001L +#define MH_DEBUG_REG05__CP_MH_write_MASK 0x00000002L +#define MH_DEBUG_REG05__CP_MH_write 0x00000002L +#define MH_DEBUG_REG05__CP_MH_tag_MASK 0x0000001cL +#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be_MASK 0x000000ffL +#define MH_DEBUG_REG08__RB_MH_be_MASK 0x0000ff00L +#define MH_DEBUG_REG08__PA_MH_be_MASK 0x00ff0000L + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK 0x00000007L +#define MH_DEBUG_REG09__VGT_MH_send_MASK 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_send 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_tagbe 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG10__TC_MH_send_MASK 0x00000004L +#define MH_DEBUG_REG10__TC_MH_send 0x00000004L +#define MH_DEBUG_REG10__TC_MH_mask_MASK 0x00000018L +#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info_MASK 0x01ffffffL +#define MH_DEBUG_REG11__TC_MH_send_MASK 0x02000000L +#define MH_DEBUG_REG11__TC_MH_send 0x02000000L + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK 0x01ffffffL +#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK 0x02000000L +#define MH_DEBUG_REG12__MH_TC_mcinfo_send 0x02000000L +#define MH_DEBUG_REG12__TC_MH_written_MASK 0x04000000L +#define MH_DEBUG_REG12__TC_MH_written 0x04000000L + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_SEND 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK 0x00000018L +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK 0x01ffffffL +#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK 0x02000000L +#define MH_DEBUG_REG14__TC_ROQ_SEND 0x02000000L + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG15__RB_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG15__RB_MH_send 0x00000010L +#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG18__PA_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG18__PA_MH_send 0x00000010L +#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG21__AVALID_q 0x00000001L +#define MH_DEBUG_REG21__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG21__AREADY_q 0x00000002L +#define MH_DEBUG_REG21__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG21__ALEN_q_2_0_MASK 0x000000e0L +#define MH_DEBUG_REG21__ARVALID_q_MASK 0x00000100L +#define MH_DEBUG_REG21__ARVALID_q 0x00000100L +#define MH_DEBUG_REG21__ARREADY_q_MASK 0x00000200L +#define MH_DEBUG_REG21__ARREADY_q 0x00000200L +#define MH_DEBUG_REG21__ARID_q_MASK 0x00001c00L +#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK 0x00006000L +#define MH_DEBUG_REG21__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG21__RVALID_q 0x00008000L +#define MH_DEBUG_REG21__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG21__RREADY_q 0x00010000L +#define MH_DEBUG_REG21__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG21__RLAST_q 0x00020000L +#define MH_DEBUG_REG21__RID_q_MASK 0x001c0000L +#define MH_DEBUG_REG21__WVALID_q_MASK 0x00200000L +#define MH_DEBUG_REG21__WVALID_q 0x00200000L +#define MH_DEBUG_REG21__WREADY_q_MASK 0x00400000L +#define MH_DEBUG_REG21__WREADY_q 0x00400000L +#define MH_DEBUG_REG21__WLAST_q_MASK 0x00800000L +#define MH_DEBUG_REG21__WLAST_q 0x00800000L +#define MH_DEBUG_REG21__WID_q_MASK 0x07000000L +#define MH_DEBUG_REG21__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG21__BVALID_q 0x08000000L +#define MH_DEBUG_REG21__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG21__BREADY_q 0x10000000L +#define MH_DEBUG_REG21__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG22__AVALID_q 0x00000001L +#define MH_DEBUG_REG22__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG22__AREADY_q 0x00000002L +#define MH_DEBUG_REG22__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG22__ALEN_q_1_0_MASK 0x00000060L +#define MH_DEBUG_REG22__ARVALID_q_MASK 0x00000080L +#define MH_DEBUG_REG22__ARVALID_q 0x00000080L +#define MH_DEBUG_REG22__ARREADY_q_MASK 0x00000100L +#define MH_DEBUG_REG22__ARREADY_q 0x00000100L +#define MH_DEBUG_REG22__ARID_q_MASK 0x00000e00L +#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK 0x00001000L +#define MH_DEBUG_REG22__ARLEN_q_1_1 0x00001000L +#define MH_DEBUG_REG22__WVALID_q_MASK 0x00002000L +#define MH_DEBUG_REG22__WVALID_q 0x00002000L +#define MH_DEBUG_REG22__WREADY_q_MASK 0x00004000L +#define MH_DEBUG_REG22__WREADY_q 0x00004000L +#define MH_DEBUG_REG22__WLAST_q_MASK 0x00008000L +#define MH_DEBUG_REG22__WLAST_q 0x00008000L +#define MH_DEBUG_REG22__WID_q_MASK 0x00070000L +#define MH_DEBUG_REG22__WSTRB_q_MASK 0x07f80000L +#define MH_DEBUG_REG22__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG22__BVALID_q 0x08000000L +#define MH_DEBUG_REG22__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG22__BREADY_q 0x10000000L +#define MH_DEBUG_REG22__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK 0x00000001L +#define MH_DEBUG_REG23__ARC_CTRL_RE_q 0x00000001L +#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK 0x0000000eL +#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG24__REG_A_MASK 0x0000fffcL +#define MH_DEBUG_REG24__REG_RE_MASK 0x00010000L +#define MH_DEBUG_REG24__REG_RE 0x00010000L +#define MH_DEBUG_REG24__REG_WE_MASK 0x00020000L +#define MH_DEBUG_REG24__REG_WE 0x00020000L +#define MH_DEBUG_REG24__BLOCK_RS_MASK 0x00040000L +#define MH_DEBUG_REG24__BLOCK_RS 0x00040000L + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD_MASK 0xffffffffL + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy_MASK 0x00000001L +#define MH_DEBUG_REG26__MH_RBBM_busy 0x00000001L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK 0x00000008L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int 0x00000008L +#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK 0x00000010L +#define MH_DEBUG_REG26__GAT_CLK_ENA 0x00000010L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK 0x00000020L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override 0x00000020L +#define MH_DEBUG_REG26__CNT_q_MASK 0x00000fc0L +#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK 0x00001000L +#define MH_DEBUG_REG26__TCD_EMPTY_q 0x00001000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY 0x00002000L +#define MH_DEBUG_REG26__MH_BUSY_d_MASK 0x00004000L +#define MH_DEBUG_REG26__MH_BUSY_d 0x00004000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK 0x00008000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY 0x00008000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC 0x00020000L +#define MH_DEBUG_REG26__CP_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG26__CP_SEND_q 0x00040000L +#define MH_DEBUG_REG26__CP_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG26__CP_RTR_q 0x00080000L +#define MH_DEBUG_REG26__VGT_SEND_q_MASK 0x00100000L +#define MH_DEBUG_REG26__VGT_SEND_q 0x00100000L +#define MH_DEBUG_REG26__VGT_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG26__VGT_RTR_q 0x00200000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK 0x00800000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q 0x00800000L +#define MH_DEBUG_REG26__RB_SEND_q_MASK 0x01000000L +#define MH_DEBUG_REG26__RB_SEND_q 0x01000000L +#define MH_DEBUG_REG26__RB_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG26__RB_RTR_q 0x02000000L +#define MH_DEBUG_REG26__PA_SEND_q_MASK 0x04000000L +#define MH_DEBUG_REG26__PA_SEND_q 0x04000000L +#define MH_DEBUG_REG26__PA_RTR_q_MASK 0x08000000L +#define MH_DEBUG_REG26__PA_RTR_q 0x08000000L +#define MH_DEBUG_REG26__RDC_VALID_MASK 0x10000000L +#define MH_DEBUG_REG26__RDC_VALID 0x10000000L +#define MH_DEBUG_REG26__RDC_RLAST_MASK 0x20000000L +#define MH_DEBUG_REG26__RDC_RLAST 0x20000000L +#define MH_DEBUG_REG26__TLBMISS_VALID_MASK 0x40000000L +#define MH_DEBUG_REG26__TLBMISS_VALID 0x40000000L +#define MH_DEBUG_REG26__BRC_VALID_MASK 0x80000000L +#define MH_DEBUG_REG26__BRC_VALID 0x80000000L + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK 0x00000038L +#define MH_DEBUG_REG27__EFF1_WINNER_MASK 0x000001c0L +#define MH_DEBUG_REG27__ARB_WINNER_MASK 0x00000e00L +#define MH_DEBUG_REG27__ARB_WINNER_q_MASK 0x00007000L +#define MH_DEBUG_REG27__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG27__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG27__KILL_EFF1_MASK 0x00010000L +#define MH_DEBUG_REG27__KILL_EFF1 0x00010000L +#define MH_DEBUG_REG27__ARB_HOLD_MASK 0x00020000L +#define MH_DEBUG_REG27__ARB_HOLD 0x00020000L +#define MH_DEBUG_REG27__ARB_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG27__ARB_RTR_q 0x00040000L +#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK 0x00080000L +#define MH_DEBUG_REG27__CP_SEND_QUAL 0x00080000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK 0x00100000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL 0x00100000L +#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_QUAL 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK 0x00400000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL 0x00400000L +#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK 0x00800000L +#define MH_DEBUG_REG27__RB_SEND_QUAL 0x00800000L +#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK 0x01000000L +#define MH_DEBUG_REG27__PA_SEND_QUAL 0x01000000L +#define MH_DEBUG_REG27__ARB_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG27__ARB_QUAL 0x02000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK 0x04000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ 0x04000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK 0x08000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ 0x08000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK 0x10000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ 0x10000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK 0x20000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ 0x20000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK 0x40000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q 0x40000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK 0x80000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q 0x80000000L + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG28__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK 0x00000040L +#define MH_DEBUG_REG28__CP_SEND_QUAL 0x00000040L +#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK 0x00000080L +#define MH_DEBUG_REG28__VGT_SEND_QUAL 0x00000080L +#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_QUAL 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK 0x00000200L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL 0x00000200L +#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK 0x00000400L +#define MH_DEBUG_REG28__RB_SEND_QUAL 0x00000400L +#define MH_DEBUG_REG28__ARB_QUAL_MASK 0x00000800L +#define MH_DEBUG_REG28__ARB_QUAL 0x00000800L +#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK 0x00001000L +#define MH_DEBUG_REG28__CP_EFF1_REQ 0x00001000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK 0x00002000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ 0x00002000L +#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK 0x00004000L +#define MH_DEBUG_REG28__TC_EFF1_REQ 0x00004000L +#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK 0x00008000L +#define MH_DEBUG_REG28__RB_EFF1_REQ 0x00008000L +#define MH_DEBUG_REG28__EFF1_WIN_MASK 0x00010000L +#define MH_DEBUG_REG28__EFF1_WIN 0x00010000L +#define MH_DEBUG_REG28__KILL_EFF1_MASK 0x00020000L +#define MH_DEBUG_REG28__KILL_EFF1 0x00020000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK 0x00040000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q 0x00040000L +#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK 0x00080000L +#define MH_DEBUG_REG28__TC_ARB_HOLD 0x00080000L +#define MH_DEBUG_REG28__ARB_HOLD_MASK 0x00100000L +#define MH_DEBUG_REG28__ARB_HOLD 0x00100000L +#define MH_DEBUG_REG28__ARB_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG28__ARB_RTR_q 0x00200000L +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000L + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK 0x00000007L +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK 0x00000038L +#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK 0x000001c0L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK 0x00000200L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d 0x00000200L +#define MH_DEBUG_REG29__ARB_HOLD_MASK 0x00000400L +#define MH_DEBUG_REG29__ARB_HOLD 0x00000400L +#define MH_DEBUG_REG29__ARB_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG29__ARB_RTR_q 0x00000800L +#define MH_DEBUG_REG29__CLNT_REQ_MASK 0x0001f000L +#define MH_DEBUG_REG29__RECENT_d_0_MASK 0x000e0000L +#define MH_DEBUG_REG29__RECENT_d_1_MASK 0x00700000L +#define MH_DEBUG_REG29__RECENT_d_2_MASK 0x03800000L +#define MH_DEBUG_REG29__RECENT_d_3_MASK 0x1c000000L +#define MH_DEBUG_REG29__RECENT_d_4_MASK 0xe0000000L + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK 0x00000001L +#define MH_DEBUG_REG30__TC_ARB_HOLD 0x00000001L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK 0x00000002L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK 0x00000004L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK 0x00000004L +#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK 0x00000008L +#define MH_DEBUG_REG30__TCD_NEARFULL_q 0x00000008L +#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_IP_q 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK 0x000000e0L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q 0x00000400L +#define MH_DEBUG_REG30__TC_MH_written_MASK 0x00000800L +#define MH_DEBUG_REG30__TC_MH_written 0x00000800L +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK 0x0007f000L +#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK 0x00080000L +#define MH_DEBUG_REG30__WBURST_ACTIVE 0x00080000L +#define MH_DEBUG_REG30__WLAST_q_MASK 0x00100000L +#define MH_DEBUG_REG30__WLAST_q 0x00100000L +#define MH_DEBUG_REG30__WBURST_IP_q_MASK 0x00200000L +#define MH_DEBUG_REG30__WBURST_IP_q 0x00200000L +#define MH_DEBUG_REG30__WBURST_CNT_q_MASK 0x01c00000L +#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG30__CP_SEND_QUAL 0x02000000L +#define MH_DEBUG_REG30__CP_MH_write_MASK 0x04000000L +#define MH_DEBUG_REG30__CP_MH_write 0x04000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK 0x08000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL 0x08000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK 0x10000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL 0x10000000L +#define MH_DEBUG_REG30__ARB_WINNER_MASK 0xe0000000L + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK 0x03ffffffL +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000L + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG32__ROQ_MARK_q_MASK 0x0000ff00L +#define MH_DEBUG_REG32__ROQ_VALID_q_MASK 0x00ff0000L +#define MH_DEBUG_REG32__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG32__TC_MH_send 0x01000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG32__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG32__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG33__ROQ_MARK_d_MASK 0x0000ff00L +#define MH_DEBUG_REG33__ROQ_VALID_d_MASK 0x00ff0000L +#define MH_DEBUG_REG33__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG33__TC_MH_send 0x01000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG33__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG33__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK 0x000000ffL +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK 0x0000ff00L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK 0xff000000L + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG35__TC_MH_send 0x00000001L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK 0x00000004L +#define MH_DEBUG_REG35__ROQ_MARK_q_0 0x00000004L +#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK 0x00000008L +#define MH_DEBUG_REG35__ROQ_VALID_q_0 0x00000008L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK 0x00000010L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0 0x00000010L +#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK 0xffffffe0L + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG36__TC_MH_send 0x00000001L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK 0x00000004L +#define MH_DEBUG_REG36__ROQ_MARK_q_1 0x00000004L +#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK 0x00000008L +#define MH_DEBUG_REG36__ROQ_VALID_q_1 0x00000008L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK 0x00000010L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1 0x00000010L +#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK 0xffffffe0L + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG37__TC_MH_send 0x00000001L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK 0x00000004L +#define MH_DEBUG_REG37__ROQ_MARK_q_2 0x00000004L +#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK 0x00000008L +#define MH_DEBUG_REG37__ROQ_VALID_q_2 0x00000008L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK 0x00000010L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2 0x00000010L +#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK 0xffffffe0L + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG38__TC_MH_send 0x00000001L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK 0x00000004L +#define MH_DEBUG_REG38__ROQ_MARK_q_3 0x00000004L +#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK 0x00000008L +#define MH_DEBUG_REG38__ROQ_VALID_q_3 0x00000008L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK 0x00000010L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3 0x00000010L +#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK 0xffffffe0L + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG39__TC_MH_send 0x00000001L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK 0x00000004L +#define MH_DEBUG_REG39__ROQ_MARK_q_4 0x00000004L +#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK 0x00000008L +#define MH_DEBUG_REG39__ROQ_VALID_q_4 0x00000008L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK 0x00000010L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4 0x00000010L +#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK 0xffffffe0L + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG40__TC_MH_send 0x00000001L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK 0x00000004L +#define MH_DEBUG_REG40__ROQ_MARK_q_5 0x00000004L +#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK 0x00000008L +#define MH_DEBUG_REG40__ROQ_VALID_q_5 0x00000008L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK 0x00000010L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5 0x00000010L +#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK 0xffffffe0L + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG41__TC_MH_send 0x00000001L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK 0x00000004L +#define MH_DEBUG_REG41__ROQ_MARK_q_6 0x00000004L +#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK 0x00000008L +#define MH_DEBUG_REG41__ROQ_VALID_q_6 0x00000008L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK 0x00000010L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6 0x00000010L +#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK 0xffffffe0L + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG42__TC_MH_send 0x00000001L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK 0x00000004L +#define MH_DEBUG_REG42__ROQ_MARK_q_7 0x00000004L +#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK 0x00000008L +#define MH_DEBUG_REG42__ROQ_VALID_q_7 0x00000008L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK 0x00000010L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7 0x00000010L +#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK 0xffffffe0L + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG43__ARB_REG_WE_q 0x00000001L +#define MH_DEBUG_REG43__ARB_WE_MASK 0x00000002L +#define MH_DEBUG_REG43__ARB_WE 0x00000002L +#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG43__ARB_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG43__ARB_RTR_q_MASK 0x00000008L +#define MH_DEBUG_REG43__ARB_RTR_q 0x00000008L +#define MH_DEBUG_REG43__ARB_REG_RTR_MASK 0x00000010L +#define MH_DEBUG_REG43__ARB_REG_RTR 0x00000010L +#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK 0x00000020L +#define MH_DEBUG_REG43__WDAT_BURST_RTR 0x00000020L +#define MH_DEBUG_REG43__MMU_RTR_MASK 0x00000040L +#define MH_DEBUG_REG43__MMU_RTR 0x00000040L +#define MH_DEBUG_REG43__ARB_ID_q_MASK 0x00000380L +#define MH_DEBUG_REG43__ARB_WRITE_q_MASK 0x00000400L +#define MH_DEBUG_REG43__ARB_WRITE_q 0x00000400L +#define MH_DEBUG_REG43__ARB_BLEN_q_MASK 0x00000800L +#define MH_DEBUG_REG43__ARB_BLEN_q 0x00000800L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY 0x00001000L +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK 0x0000e000L +#define MH_DEBUG_REG43__MMU_WE_MASK 0x00010000L +#define MH_DEBUG_REG43__MMU_WE 0x00010000L +#define MH_DEBUG_REG43__ARQ_RTR_MASK 0x00020000L +#define MH_DEBUG_REG43__ARQ_RTR 0x00020000L +#define MH_DEBUG_REG43__MMU_ID_MASK 0x001c0000L +#define MH_DEBUG_REG43__MMU_WRITE_MASK 0x00200000L +#define MH_DEBUG_REG43__MMU_WRITE 0x00200000L +#define MH_DEBUG_REG43__MMU_BLEN_MASK 0x00400000L +#define MH_DEBUG_REG43__MMU_BLEN 0x00400000L +#define MH_DEBUG_REG43__WBURST_IP_q_MASK 0x00800000L +#define MH_DEBUG_REG43__WBURST_IP_q 0x00800000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK 0x01000000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q 0x01000000L +#define MH_DEBUG_REG43__WDB_WE_MASK 0x02000000L +#define MH_DEBUG_REG43__WDB_WE 0x02000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK 0x08000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3 0x08000000L + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG44__ARB_WE 0x00000001L +#define MH_DEBUG_REG44__ARB_ID_q_MASK 0x0000000eL +#define MH_DEBUG_REG44__ARB_VAD_q_MASK 0xfffffff0L + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE_MASK 0x00000001L +#define MH_DEBUG_REG45__MMU_WE 0x00000001L +#define MH_DEBUG_REG45__MMU_ID_MASK 0x0000000eL +#define MH_DEBUG_REG45__MMU_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG46__WDAT_REG_WE_q 0x00000001L +#define MH_DEBUG_REG46__WDB_WE_MASK 0x00000002L +#define MH_DEBUG_REG46__WDB_WE 0x00000002L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK 0x00000008L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4 0x00000008L +#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK 0x00000ff0L +#define MH_DEBUG_REG46__ARB_WLAST_MASK 0x00001000L +#define MH_DEBUG_REG46__ARB_WLAST 0x00001000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY 0x00002000L +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK 0x0007c000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK 0x00080000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q 0x00080000L +#define MH_DEBUG_REG46__WDB_WDC_WID_MASK 0x00700000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK 0xff000000L + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK 0x00000001L +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY 0x00000001L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK 0x00000002L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY 0x00000002L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK 0x00000008L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE 0x00000008L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK 0x00000010L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS 0x00000010L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK 0x00000020L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q 0x00000020L +#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_q 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK 0x00001f80L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q 0x00002000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK 0x00004000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q 0x00004000L +#define MH_DEBUG_REG49__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG49__RVALID_q 0x00008000L +#define MH_DEBUG_REG49__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG49__RREADY_q 0x00010000L +#define MH_DEBUG_REG49__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG49__RLAST_q 0x00020000L +#define MH_DEBUG_REG49__BVALID_q_MASK 0x00040000L +#define MH_DEBUG_REG49__BVALID_q 0x00040000L +#define MH_DEBUG_REG49__BREADY_q_MASK 0x00080000L +#define MH_DEBUG_REG49__BREADY_q 0x00080000L + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG50__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG50__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG50__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG50__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK 0x00000008L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND 0x00000008L +#define MH_DEBUG_REG50__TLBMISS_VALID_MASK 0x00000010L +#define MH_DEBUG_REG50__TLBMISS_VALID 0x00000010L +#define MH_DEBUG_REG50__RDC_VALID_MASK 0x00000020L +#define MH_DEBUG_REG50__RDC_VALID 0x00000020L +#define MH_DEBUG_REG50__RDC_RID_MASK 0x000001c0L +#define MH_DEBUG_REG50__RDC_RLAST_MASK 0x00000200L +#define MH_DEBUG_REG50__RDC_RLAST 0x00000200L +#define MH_DEBUG_REG50__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK 0x00001000L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS 0x00001000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q 0x00002000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK 0x00004000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q 0x00004000L +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK 0x00200000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE 0x00200000L +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK 0x0fc00000L +#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK 0x10000000L +#define MH_DEBUG_REG50__CNT_HOLD_q1 0x10000000L +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000L + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK 0xffffffffL + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003L +#define MH_DEBUG_REG52__ARB_WE_MASK 0x00000004L +#define MH_DEBUG_REG52__ARB_WE 0x00000004L +#define MH_DEBUG_REG52__MMU_RTR_MASK 0x00000008L +#define MH_DEBUG_REG52__MMU_RTR 0x00000008L +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0L +#define MH_DEBUG_REG52__ARB_ID_q_MASK 0x1c000000L +#define MH_DEBUG_REG52__ARB_WRITE_q_MASK 0x20000000L +#define MH_DEBUG_REG52__ARB_WRITE_q 0x20000000L +#define MH_DEBUG_REG52__client_behavior_q_MASK 0xc0000000L + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid_MASK 0x00000001L +#define MH_DEBUG_REG53__stage1_valid 0x00000001L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK 0x00000002L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q 0x00000002L +#define MH_DEBUG_REG53__pa_in_mpu_range_MASK 0x00000004L +#define MH_DEBUG_REG53__pa_in_mpu_range 0x00000004L +#define MH_DEBUG_REG53__tag_match_q_MASK 0x00000008L +#define MH_DEBUG_REG53__tag_match_q 0x00000008L +#define MH_DEBUG_REG53__tag_miss_q_MASK 0x00000010L +#define MH_DEBUG_REG53__tag_miss_q 0x00000010L +#define MH_DEBUG_REG53__va_in_range_q_MASK 0x00000020L +#define MH_DEBUG_REG53__va_in_range_q 0x00000020L +#define MH_DEBUG_REG53__MMU_MISS_MASK 0x00000040L +#define MH_DEBUG_REG53__MMU_MISS 0x00000040L +#define MH_DEBUG_REG53__MMU_READ_MISS_MASK 0x00000080L +#define MH_DEBUG_REG53__MMU_READ_MISS 0x00000080L +#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK 0x00000100L +#define MH_DEBUG_REG53__MMU_WRITE_MISS 0x00000100L +#define MH_DEBUG_REG53__MMU_HIT_MASK 0x00000200L +#define MH_DEBUG_REG53__MMU_HIT 0x00000200L +#define MH_DEBUG_REG53__MMU_READ_HIT_MASK 0x00000400L +#define MH_DEBUG_REG53__MMU_READ_HIT 0x00000400L +#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK 0x00000800L +#define MH_DEBUG_REG53__MMU_WRITE_HIT 0x00000800L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT 0x00008000L +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK 0xffff0000L + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR_MASK 0x00000001L +#define MH_DEBUG_REG54__ARQ_RTR 0x00000001L +#define MH_DEBUG_REG54__MMU_WE_MASK 0x00000002L +#define MH_DEBUG_REG54__MMU_WE 0x00000002L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK 0x00000004L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q 0x00000004L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK 0x00000008L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS 0x00000008L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK 0x00000010L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND 0x00000010L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH 0x00000020L +#define MH_DEBUG_REG54__pa_in_mpu_range_MASK 0x00000040L +#define MH_DEBUG_REG54__pa_in_mpu_range 0x00000040L +#define MH_DEBUG_REG54__stage1_valid_MASK 0x00000080L +#define MH_DEBUG_REG54__stage1_valid 0x00000080L +#define MH_DEBUG_REG54__stage2_valid_MASK 0x00000100L +#define MH_DEBUG_REG54__stage2_valid 0x00000100L +#define MH_DEBUG_REG54__client_behavior_q_MASK 0x00000600L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK 0x00000800L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q 0x00000800L +#define MH_DEBUG_REG54__tag_match_q_MASK 0x00001000L +#define MH_DEBUG_REG54__tag_match_q 0x00001000L +#define MH_DEBUG_REG54__tag_miss_q_MASK 0x00002000L +#define MH_DEBUG_REG54__tag_miss_q 0x00002000L +#define MH_DEBUG_REG54__va_in_range_q_MASK 0x00004000L +#define MH_DEBUG_REG54__va_in_range_q 0x00004000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK 0x00008000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q 0x00008000L +#define MH_DEBUG_REG54__TAG_valid_q_MASK 0xffff0000L + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA_MASK 0x00001fffL +#define MH_DEBUG_REG55__TAG_valid_q_0_MASK 0x00002000L +#define MH_DEBUG_REG55__TAG_valid_q_0 0x00002000L +#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG55__TAG1_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG55__TAG_valid_q_1_MASK 0x20000000L +#define MH_DEBUG_REG55__TAG_valid_q_1 0x20000000L + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA_MASK 0x00001fffL +#define MH_DEBUG_REG56__TAG_valid_q_2_MASK 0x00002000L +#define MH_DEBUG_REG56__TAG_valid_q_2 0x00002000L +#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG56__TAG3_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG56__TAG_valid_q_3_MASK 0x20000000L +#define MH_DEBUG_REG56__TAG_valid_q_3 0x20000000L + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA_MASK 0x00001fffL +#define MH_DEBUG_REG57__TAG_valid_q_4_MASK 0x00002000L +#define MH_DEBUG_REG57__TAG_valid_q_4 0x00002000L +#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG57__TAG5_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG57__TAG_valid_q_5_MASK 0x20000000L +#define MH_DEBUG_REG57__TAG_valid_q_5 0x20000000L + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA_MASK 0x00001fffL +#define MH_DEBUG_REG58__TAG_valid_q_6_MASK 0x00002000L +#define MH_DEBUG_REG58__TAG_valid_q_6 0x00002000L +#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG58__TAG7_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG58__TAG_valid_q_7_MASK 0x20000000L +#define MH_DEBUG_REG58__TAG_valid_q_7 0x20000000L + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA_MASK 0x00001fffL +#define MH_DEBUG_REG59__TAG_valid_q_8_MASK 0x00002000L +#define MH_DEBUG_REG59__TAG_valid_q_8 0x00002000L +#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG59__TAG9_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG59__TAG_valid_q_9_MASK 0x20000000L +#define MH_DEBUG_REG59__TAG_valid_q_9 0x20000000L + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA_MASK 0x00001fffL +#define MH_DEBUG_REG60__TAG_valid_q_10_MASK 0x00002000L +#define MH_DEBUG_REG60__TAG_valid_q_10 0x00002000L +#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG60__TAG11_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG60__TAG_valid_q_11_MASK 0x20000000L +#define MH_DEBUG_REG60__TAG_valid_q_11 0x20000000L + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA_MASK 0x00001fffL +#define MH_DEBUG_REG61__TAG_valid_q_12_MASK 0x00002000L +#define MH_DEBUG_REG61__TAG_valid_q_12 0x00002000L +#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG61__TAG13_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG61__TAG_valid_q_13_MASK 0x20000000L +#define MH_DEBUG_REG61__TAG_valid_q_13 0x20000000L + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA_MASK 0x00001fffL +#define MH_DEBUG_REG62__TAG_valid_q_14_MASK 0x00002000L +#define MH_DEBUG_REG62__TAG_valid_q_14 0x00002000L +#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG62__TAG15_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG62__TAG_valid_q_15_MASK 0x20000000L +#define MH_DEBUG_REG62__TAG_valid_q_15 0x20000000L + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE_MASK 0x00000001L +#define MH_MMU_CONFIG__MMU_ENABLE 0x00000001L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK 0x00000002L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE 0x00000002L +#define MH_MMU_CONFIG__RESERVED1_MASK 0x0000000cL +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK 0x00000030L +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK 0x000000c0L +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK 0x00000300L +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00L +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK 0x00003000L +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000L +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK 0x00030000L +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000L +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000L +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK 0x00c00000L +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK 0x03000000L + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK 0x00000fffL +#define MH_MMU_VA_RANGE__VA_BASE_MASK 0xfffff000L + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE_MASK 0xfffff000L + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK 0x00000001L +#define MH_MMU_PAGE_FAULT__PAGE_FAULT 0x00000001L +#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK 0x00000002L +#define MH_MMU_PAGE_FAULT__OP_TYPE 0x00000002L +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK 0x0000000cL +#define MH_MMU_PAGE_FAULT__AXI_ID_MASK 0x00000070L +#define MH_MMU_PAGE_FAULT__RESERVED1_MASK 0x00000080L +#define MH_MMU_PAGE_FAULT__RESERVED1 0x00000080L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE 0x00000100L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK 0x00000200L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE 0x00000200L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK 0x00000400L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR 0x00000400L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK 0x00000800L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR 0x00000800L +#define MH_MMU_PAGE_FAULT__REQ_VA_MASK 0xfffff000L + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK 0xffffffe0L + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_ALL 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK 0x00000002L +#define MH_MMU_INVALIDATE__INVALIDATE_TC 0x00000002L + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE_MASK 0xfffff000L + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END_MASK 0xfffff000L + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK 0x00000002L +#define WAIT_UNTIL__WAIT_RE_VSYNC 0x00000002L +#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK 0x00000004L +#define WAIT_UNTIL__WAIT_FE_VSYNC 0x00000004L +#define WAIT_UNTIL__WAIT_VSYNC_MASK 0x00000008L +#define WAIT_UNTIL__WAIT_VSYNC 0x00000008L +#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID0 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID1 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK 0x00000040L +#define WAIT_UNTIL__WAIT_DSPLY_ID2 0x00000040L +#define WAIT_UNTIL__WAIT_CMDFIFO_MASK 0x00000400L +#define WAIT_UNTIL__WAIT_CMDFIFO 0x00000400L +#define WAIT_UNTIL__WAIT_2D_IDLE_MASK 0x00004000L +#define WAIT_UNTIL__WAIT_2D_IDLE 0x00004000L +#define WAIT_UNTIL__WAIT_3D_IDLE_MASK 0x00008000L +#define WAIT_UNTIL__WAIT_3D_IDLE 0x00008000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK 0x00010000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN 0x00010000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK 0x00020000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN 0x00020000L +#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK 0x00f00000L + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020L + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL +#define RBBM_STATUS__TC_BUSY_MASK 0x00000020L +#define RBBM_STATUS__TC_BUSY 0x00000020L +#define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L +#define RBBM_STATUS__HIRQ_PENDING 0x00000100L +#define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L +#define RBBM_STATUS__CPRQ_PENDING 0x00000200L +#define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L +#define RBBM_STATUS__CFRQ_PENDING 0x00000400L +#define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L +#define RBBM_STATUS__PFRQ_PENDING 0x00000800L +#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L +#define RBBM_STATUS__VGT_BUSY_NO_DMA 0x00001000L +#define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L +#define RBBM_STATUS__RBBM_WU_BUSY 0x00004000L +#define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L +#define RBBM_STATUS__CP_NRT_BUSY 0x00010000L +#define RBBM_STATUS__MH_BUSY_MASK 0x00040000L +#define RBBM_STATUS__MH_BUSY 0x00040000L +#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L +#define RBBM_STATUS__MH_COHERENCY_BUSY 0x00080000L +#define RBBM_STATUS__SX_BUSY_MASK 0x00200000L +#define RBBM_STATUS__SX_BUSY 0x00200000L +#define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L +#define RBBM_STATUS__TPC_BUSY 0x00400000L +#define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L +#define RBBM_STATUS__SC_CNTX_BUSY 0x01000000L +#define RBBM_STATUS__PA_BUSY_MASK 0x02000000L +#define RBBM_STATUS__PA_BUSY 0x02000000L +#define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L +#define RBBM_STATUS__VGT_BUSY 0x04000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY 0x08000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY 0x10000000L +#define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L +#define RBBM_STATUS__RB_CNTX_BUSY 0x40000000L +#define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +#define RBBM_STATUS__GUI_ACTIVE 0x80000000L + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2 0x00000004L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK 0x00000008L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID 0x00000008L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK 0x00000040L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2 0x00000040L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK 0x00000080L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL 0x00000080L +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK 0x00000300L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK 0x00001000L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2 0x00001000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK 0x00002000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL 0x00002000L +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK 0x0000c000L +#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK 0x00030000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK 0x00400000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2 0x00400000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK 0x00800000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL 0x00800000L +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK 0x03000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK 0x10000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2 0x10000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK 0x20000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL 0x20000000L +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK 0xc0000000L + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK 0x00000003L +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK 0x00000300L +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK 0x00030000L +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK 0x03000000L + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST_MASK 0xffffffffL + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK 0x0000ffffL +#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK 0x00ff0000L +#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK 0xff000000L + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK 0xffffffffL + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0_MASK 0x000000ffL + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1_MASK 0x0000000fL +#define RBBM_PERIPHID1__DESIGNER0_MASK 0x000000f0L + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1_MASK 0x0000000fL +#define RBBM_PERIPHID2__REVISION_MASK 0x000000f0L + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK 0x00000003L +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK 0x0000000cL +#define RBBM_PERIPHID3__MH_INTERFACE_MASK 0x00000030L +#define RBBM_PERIPHID3__CONTINUATION_MASK 0x00000080L +#define RBBM_PERIPHID3__CONTINUATION 0x00000080L + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL +#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK 0x0001ff00L + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000001fL +#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK 0x000003e0L + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_PA 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_MH 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_BC 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_SX 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK 0x00010000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT 0x00010000L + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE 0x00004000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE 0x00010000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE 0x00200000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE 0x01000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK 0x02000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE 0x02000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK 0x08000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE 0x08000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000L + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE 0x00000800L + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK 0x0000ffffL +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK 0x01000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP 0x01000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK 0x02000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI 0x02000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE 0x20000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE 0x40000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK 0x80000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE 0x80000000L + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK 0x00000001L +#define NQWAIT_UNTIL__WAIT_GUI_IDLE 0x00000001L + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK 0xffffffffL + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK 0x0000003fL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK 0x00000f00L +#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK 0x00001000L +#define RBBM_DEBUG_CNTL__SW_ENABLE 0x00001000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK 0x0f000000L +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK 0xf0000000L + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR_MASK 0x00000002L +#define RBBM_DEBUG__IGNORE_RTR 0x00000002L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI 0x00000010L +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK 0x00010000L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI 0x00010000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI 0x00020000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI 0x00040000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI 0x00080000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK 0x00100000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR 0x00100000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK 0x00200000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR 0x00200000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK 0x00400000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR 0x00400000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK 0x01000000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR 0x01000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK 0x80000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY 0x80000000L + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS_MASK 0x0001fffcL +#define RBBM_READ_ERROR__READ_REQUESTER_MASK 0x40000000L +#define RBBM_READ_ERROR__READ_REQUESTER 0x40000000L +#define RBBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define RBBM_READ_ERROR__READ_ERROR 0x80000000L + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ffL + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L +#define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK 0x00000002L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK 0x00080000L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L +#define RBBM_INT_STATUS__RDERR_INT_STAT 0x00000001L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK 0x00000002L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT 0x00000002L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK 0x00080000L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT 0x00080000L + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L +#define RBBM_INT_ACK__RDERR_INT_ACK 0x00000001L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK 0x00000002L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK 0x00000002L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK 0x00080000L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK 0x00080000L + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK 0x00000020L +#define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L +#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK 0x04000000L +#define MASTER_INT_SIGNAL__SQ_INT_STAT 0x04000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK 0x40000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK 0x80000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK 0x0000003fL + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0x0000ffffL + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE_MASK 0xffffffe0L + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB_CNTL__RB_POLL_EN_MASK 0x00100000L +#define CP_RB_CNTL__RB_POLL_EN 0x00100000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_NO_UPDATE 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA 0x80000000L + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK 0x00000003L +#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK 0xfffffffcL + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE_MASK 0xfffffffcL + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE_MASK 0xfffffffcL + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE_MASK 0xfffffffcL + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK 0x0000000fL +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK 0x00000f00L +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK 0x000f0000L + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END_MASK 0x001f0000L +#define CP_MEQ_THRESHOLDS__ROQ_END_MASK 0x1f000000L + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK 0x0000007fL +#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK 0x00007f00L +#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK 0x007f0000L + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST_MASK 0x0000007fL + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x0000001fL + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK 0x0000007fL +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK 0x007f0000L + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK 0x0000007fL +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK 0x007f0000L + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK 0x0000007fL +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK 0x007f0000L + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK 0x00000007L +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK 0x00000700L + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK 0x0000007fL +#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK 0x007f0000L + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK 0x00000001L +#define CP_MIU_TAG_STAT__TAG_0_STAT 0x00000001L +#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK 0x00000002L +#define CP_MIU_TAG_STAT__TAG_1_STAT 0x00000002L +#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK 0x00000004L +#define CP_MIU_TAG_STAT__TAG_2_STAT 0x00000004L +#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK 0x00000008L +#define CP_MIU_TAG_STAT__TAG_3_STAT 0x00000008L +#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK 0x00000010L +#define CP_MIU_TAG_STAT__TAG_4_STAT 0x00000010L +#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK 0x00000020L +#define CP_MIU_TAG_STAT__TAG_5_STAT 0x00000020L +#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK 0x00000040L +#define CP_MIU_TAG_STAT__TAG_6_STAT 0x00000040L +#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK 0x00000080L +#define CP_MIU_TAG_STAT__TAG_7_STAT 0x00000080L +#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK 0x00000100L +#define CP_MIU_TAG_STAT__TAG_8_STAT 0x00000100L +#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK 0x00000200L +#define CP_MIU_TAG_STAT__TAG_9_STAT 0x00000200L +#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK 0x00000400L +#define CP_MIU_TAG_STAT__TAG_10_STAT 0x00000400L +#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK 0x00000800L +#define CP_MIU_TAG_STAT__TAG_11_STAT 0x00000800L +#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK 0x00001000L +#define CP_MIU_TAG_STAT__TAG_12_STAT 0x00001000L +#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK 0x00002000L +#define CP_MIU_TAG_STAT__TAG_13_STAT 0x00002000L +#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK 0x00004000L +#define CP_MIU_TAG_STAT__TAG_14_STAT 0x00004000L +#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK 0x00008000L +#define CP_MIU_TAG_STAT__TAG_15_STAT 0x00008000L +#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK 0x00010000L +#define CP_MIU_TAG_STAT__TAG_16_STAT 0x00010000L +#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK 0x00020000L +#define CP_MIU_TAG_STAT__TAG_17_STAT 0x00020000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK 0x80000000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG 0x80000000L + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x0000007fL +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX_MASK 0x0000ffffL +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000L +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY 0x02000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY 0x04000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_HALT 0x10000000L +#define CP_ME_CNTL__ME_BUSY_MASK 0x20000000L +#define CP_ME_CNTL__ME_BUSY 0x20000000L +#define CP_ME_CNTL__PROG_CNT_SIZE_MASK 0x80000000L +#define CP_ME_CNTL__PROG_CNT_SIZE 0x80000000L + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA_MASK 0xffffffffL + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x000003ffL + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000003ffL + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR_MASK 0xffffffffL + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffffL +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__PREDICATE_DISABLE 0x00800000L +#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK 0x01000000L +#define CP_DEBUG__PROG_END_PTR_ENABLE 0x01000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK 0x02000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE 0x02000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK 0x04000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS 0x04000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK 0x08000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE 0x08000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK 0x10000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE 0x10000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL 0x40000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK 0x80000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE 0x80000000L + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK_MASK 0x000000ffL +#define SCRATCH_UMSK__SCRATCH_SWAP_MASK 0x00030000L + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR_MASK 0xffffffe0L + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR 0x00000002L + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR 0x00000002L + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK 0x00000001L +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC 0x00000001L + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK 0x00000003L +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK 0xffffffffL + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK 0x00000003L +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK 0xfffffffcL + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK 0xffffffffL + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK 0x00000001L +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR 0x00000001L + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK 0xffffffffL + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK_MASK 0x00080000L +#define CP_INT_CNTL__SW_INT_MASK 0x00080000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK 0x00800000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK 0x01000000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK 0x02000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L +#define CP_INT_CNTL__IB_ERROR_MASK_MASK 0x08000000L +#define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L +#define CP_INT_CNTL__IB2_INT_MASK_MASK 0x20000000L +#define CP_INT_CNTL__IB2_INT_MASK 0x20000000L +#define CP_INT_CNTL__IB1_INT_MASK_MASK 0x40000000L +#define CP_INT_CNTL__IB1_INT_MASK 0x40000000L +#define CP_INT_CNTL__RB_INT_MASK_MASK 0x80000000L +#define CP_INT_CNTL__RB_INT_MASK 0x80000000L + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__SW_INT_STAT 0x00080000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK 0x00800000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK 0x01000000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT 0x01000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK 0x02000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT 0x02000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT 0x04000000L +#define CP_INT_STATUS__IB_ERROR_STAT_MASK 0x08000000L +#define CP_INT_STATUS__IB_ERROR_STAT 0x08000000L +#define CP_INT_STATUS__IB2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__IB2_INT_STAT 0x20000000L +#define CP_INT_STATUS__IB1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__IB1_INT_STAT 0x40000000L +#define CP_INT_STATUS__RB_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS__RB_INT_STAT 0x80000000L + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK_MASK 0x00080000L +#define CP_INT_ACK__SW_INT_ACK 0x00080000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK 0x00800000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK 0x00800000L +#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK 0x01000000L +#define CP_INT_ACK__OPCODE_ERROR_ACK 0x01000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK 0x02000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK 0x02000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK 0x04000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK 0x04000000L +#define CP_INT_ACK__IB_ERROR_ACK_MASK 0x08000000L +#define CP_INT_ACK__IB_ERROR_ACK 0x08000000L +#define CP_INT_ACK__IB2_INT_ACK_MASK 0x20000000L +#define CP_INT_ACK__IB2_INT_ACK 0x20000000L +#define CP_INT_ACK__IB1_INT_ACK_MASK 0x40000000L +#define CP_INT_ACK__IB1_INT_ACK 0x40000000L +#define CP_INT_ACK__RB_INT_ACK_MASK 0x80000000L +#define CP_INT_ACK__RB_INT_ACK 0x80000000L + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000001ffL + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0x00ffffffL + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK 0x0000003fL + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK 0xffffffffL + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK 0x0000ffffL + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK 0xffffffffL + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK 0xffffffffL + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK 0xffffffffL + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK 0xffffffffL + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0_MASK 0x00000001L +#define CP_NV_FLAGS_0__DISCARD_0 0x00000001L +#define CP_NV_FLAGS_0__END_RCVD_0_MASK 0x00000002L +#define CP_NV_FLAGS_0__END_RCVD_0 0x00000002L +#define CP_NV_FLAGS_0__DISCARD_1_MASK 0x00000004L +#define CP_NV_FLAGS_0__DISCARD_1 0x00000004L +#define CP_NV_FLAGS_0__END_RCVD_1_MASK 0x00000008L +#define CP_NV_FLAGS_0__END_RCVD_1 0x00000008L +#define CP_NV_FLAGS_0__DISCARD_2_MASK 0x00000010L +#define CP_NV_FLAGS_0__DISCARD_2 0x00000010L +#define CP_NV_FLAGS_0__END_RCVD_2_MASK 0x00000020L +#define CP_NV_FLAGS_0__END_RCVD_2 0x00000020L +#define CP_NV_FLAGS_0__DISCARD_3_MASK 0x00000040L +#define CP_NV_FLAGS_0__DISCARD_3 0x00000040L +#define CP_NV_FLAGS_0__END_RCVD_3_MASK 0x00000080L +#define CP_NV_FLAGS_0__END_RCVD_3 0x00000080L +#define CP_NV_FLAGS_0__DISCARD_4_MASK 0x00000100L +#define CP_NV_FLAGS_0__DISCARD_4 0x00000100L +#define CP_NV_FLAGS_0__END_RCVD_4_MASK 0x00000200L +#define CP_NV_FLAGS_0__END_RCVD_4 0x00000200L +#define CP_NV_FLAGS_0__DISCARD_5_MASK 0x00000400L +#define CP_NV_FLAGS_0__DISCARD_5 0x00000400L +#define CP_NV_FLAGS_0__END_RCVD_5_MASK 0x00000800L +#define CP_NV_FLAGS_0__END_RCVD_5 0x00000800L +#define CP_NV_FLAGS_0__DISCARD_6_MASK 0x00001000L +#define CP_NV_FLAGS_0__DISCARD_6 0x00001000L +#define CP_NV_FLAGS_0__END_RCVD_6_MASK 0x00002000L +#define CP_NV_FLAGS_0__END_RCVD_6 0x00002000L +#define CP_NV_FLAGS_0__DISCARD_7_MASK 0x00004000L +#define CP_NV_FLAGS_0__DISCARD_7 0x00004000L +#define CP_NV_FLAGS_0__END_RCVD_7_MASK 0x00008000L +#define CP_NV_FLAGS_0__END_RCVD_7 0x00008000L +#define CP_NV_FLAGS_0__DISCARD_8_MASK 0x00010000L +#define CP_NV_FLAGS_0__DISCARD_8 0x00010000L +#define CP_NV_FLAGS_0__END_RCVD_8_MASK 0x00020000L +#define CP_NV_FLAGS_0__END_RCVD_8 0x00020000L +#define CP_NV_FLAGS_0__DISCARD_9_MASK 0x00040000L +#define CP_NV_FLAGS_0__DISCARD_9 0x00040000L +#define CP_NV_FLAGS_0__END_RCVD_9_MASK 0x00080000L +#define CP_NV_FLAGS_0__END_RCVD_9 0x00080000L +#define CP_NV_FLAGS_0__DISCARD_10_MASK 0x00100000L +#define CP_NV_FLAGS_0__DISCARD_10 0x00100000L +#define CP_NV_FLAGS_0__END_RCVD_10_MASK 0x00200000L +#define CP_NV_FLAGS_0__END_RCVD_10 0x00200000L +#define CP_NV_FLAGS_0__DISCARD_11_MASK 0x00400000L +#define CP_NV_FLAGS_0__DISCARD_11 0x00400000L +#define CP_NV_FLAGS_0__END_RCVD_11_MASK 0x00800000L +#define CP_NV_FLAGS_0__END_RCVD_11 0x00800000L +#define CP_NV_FLAGS_0__DISCARD_12_MASK 0x01000000L +#define CP_NV_FLAGS_0__DISCARD_12 0x01000000L +#define CP_NV_FLAGS_0__END_RCVD_12_MASK 0x02000000L +#define CP_NV_FLAGS_0__END_RCVD_12 0x02000000L +#define CP_NV_FLAGS_0__DISCARD_13_MASK 0x04000000L +#define CP_NV_FLAGS_0__DISCARD_13 0x04000000L +#define CP_NV_FLAGS_0__END_RCVD_13_MASK 0x08000000L +#define CP_NV_FLAGS_0__END_RCVD_13 0x08000000L +#define CP_NV_FLAGS_0__DISCARD_14_MASK 0x10000000L +#define CP_NV_FLAGS_0__DISCARD_14 0x10000000L +#define CP_NV_FLAGS_0__END_RCVD_14_MASK 0x20000000L +#define CP_NV_FLAGS_0__END_RCVD_14 0x20000000L +#define CP_NV_FLAGS_0__DISCARD_15_MASK 0x40000000L +#define CP_NV_FLAGS_0__DISCARD_15 0x40000000L +#define CP_NV_FLAGS_0__END_RCVD_15_MASK 0x80000000L +#define CP_NV_FLAGS_0__END_RCVD_15 0x80000000L + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16_MASK 0x00000001L +#define CP_NV_FLAGS_1__DISCARD_16 0x00000001L +#define CP_NV_FLAGS_1__END_RCVD_16_MASK 0x00000002L +#define CP_NV_FLAGS_1__END_RCVD_16 0x00000002L +#define CP_NV_FLAGS_1__DISCARD_17_MASK 0x00000004L +#define CP_NV_FLAGS_1__DISCARD_17 0x00000004L +#define CP_NV_FLAGS_1__END_RCVD_17_MASK 0x00000008L +#define CP_NV_FLAGS_1__END_RCVD_17 0x00000008L +#define CP_NV_FLAGS_1__DISCARD_18_MASK 0x00000010L +#define CP_NV_FLAGS_1__DISCARD_18 0x00000010L +#define CP_NV_FLAGS_1__END_RCVD_18_MASK 0x00000020L +#define CP_NV_FLAGS_1__END_RCVD_18 0x00000020L +#define CP_NV_FLAGS_1__DISCARD_19_MASK 0x00000040L +#define CP_NV_FLAGS_1__DISCARD_19 0x00000040L +#define CP_NV_FLAGS_1__END_RCVD_19_MASK 0x00000080L +#define CP_NV_FLAGS_1__END_RCVD_19 0x00000080L +#define CP_NV_FLAGS_1__DISCARD_20_MASK 0x00000100L +#define CP_NV_FLAGS_1__DISCARD_20 0x00000100L +#define CP_NV_FLAGS_1__END_RCVD_20_MASK 0x00000200L +#define CP_NV_FLAGS_1__END_RCVD_20 0x00000200L +#define CP_NV_FLAGS_1__DISCARD_21_MASK 0x00000400L +#define CP_NV_FLAGS_1__DISCARD_21 0x00000400L +#define CP_NV_FLAGS_1__END_RCVD_21_MASK 0x00000800L +#define CP_NV_FLAGS_1__END_RCVD_21 0x00000800L +#define CP_NV_FLAGS_1__DISCARD_22_MASK 0x00001000L +#define CP_NV_FLAGS_1__DISCARD_22 0x00001000L +#define CP_NV_FLAGS_1__END_RCVD_22_MASK 0x00002000L +#define CP_NV_FLAGS_1__END_RCVD_22 0x00002000L +#define CP_NV_FLAGS_1__DISCARD_23_MASK 0x00004000L +#define CP_NV_FLAGS_1__DISCARD_23 0x00004000L +#define CP_NV_FLAGS_1__END_RCVD_23_MASK 0x00008000L +#define CP_NV_FLAGS_1__END_RCVD_23 0x00008000L +#define CP_NV_FLAGS_1__DISCARD_24_MASK 0x00010000L +#define CP_NV_FLAGS_1__DISCARD_24 0x00010000L +#define CP_NV_FLAGS_1__END_RCVD_24_MASK 0x00020000L +#define CP_NV_FLAGS_1__END_RCVD_24 0x00020000L +#define CP_NV_FLAGS_1__DISCARD_25_MASK 0x00040000L +#define CP_NV_FLAGS_1__DISCARD_25 0x00040000L +#define CP_NV_FLAGS_1__END_RCVD_25_MASK 0x00080000L +#define CP_NV_FLAGS_1__END_RCVD_25 0x00080000L +#define CP_NV_FLAGS_1__DISCARD_26_MASK 0x00100000L +#define CP_NV_FLAGS_1__DISCARD_26 0x00100000L +#define CP_NV_FLAGS_1__END_RCVD_26_MASK 0x00200000L +#define CP_NV_FLAGS_1__END_RCVD_26 0x00200000L +#define CP_NV_FLAGS_1__DISCARD_27_MASK 0x00400000L +#define CP_NV_FLAGS_1__DISCARD_27 0x00400000L +#define CP_NV_FLAGS_1__END_RCVD_27_MASK 0x00800000L +#define CP_NV_FLAGS_1__END_RCVD_27 0x00800000L +#define CP_NV_FLAGS_1__DISCARD_28_MASK 0x01000000L +#define CP_NV_FLAGS_1__DISCARD_28 0x01000000L +#define CP_NV_FLAGS_1__END_RCVD_28_MASK 0x02000000L +#define CP_NV_FLAGS_1__END_RCVD_28 0x02000000L +#define CP_NV_FLAGS_1__DISCARD_29_MASK 0x04000000L +#define CP_NV_FLAGS_1__DISCARD_29 0x04000000L +#define CP_NV_FLAGS_1__END_RCVD_29_MASK 0x08000000L +#define CP_NV_FLAGS_1__END_RCVD_29 0x08000000L +#define CP_NV_FLAGS_1__DISCARD_30_MASK 0x10000000L +#define CP_NV_FLAGS_1__DISCARD_30 0x10000000L +#define CP_NV_FLAGS_1__END_RCVD_30_MASK 0x20000000L +#define CP_NV_FLAGS_1__END_RCVD_30 0x20000000L +#define CP_NV_FLAGS_1__DISCARD_31_MASK 0x40000000L +#define CP_NV_FLAGS_1__DISCARD_31 0x40000000L +#define CP_NV_FLAGS_1__END_RCVD_31_MASK 0x80000000L +#define CP_NV_FLAGS_1__END_RCVD_31 0x80000000L + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32_MASK 0x00000001L +#define CP_NV_FLAGS_2__DISCARD_32 0x00000001L +#define CP_NV_FLAGS_2__END_RCVD_32_MASK 0x00000002L +#define CP_NV_FLAGS_2__END_RCVD_32 0x00000002L +#define CP_NV_FLAGS_2__DISCARD_33_MASK 0x00000004L +#define CP_NV_FLAGS_2__DISCARD_33 0x00000004L +#define CP_NV_FLAGS_2__END_RCVD_33_MASK 0x00000008L +#define CP_NV_FLAGS_2__END_RCVD_33 0x00000008L +#define CP_NV_FLAGS_2__DISCARD_34_MASK 0x00000010L +#define CP_NV_FLAGS_2__DISCARD_34 0x00000010L +#define CP_NV_FLAGS_2__END_RCVD_34_MASK 0x00000020L +#define CP_NV_FLAGS_2__END_RCVD_34 0x00000020L +#define CP_NV_FLAGS_2__DISCARD_35_MASK 0x00000040L +#define CP_NV_FLAGS_2__DISCARD_35 0x00000040L +#define CP_NV_FLAGS_2__END_RCVD_35_MASK 0x00000080L +#define CP_NV_FLAGS_2__END_RCVD_35 0x00000080L +#define CP_NV_FLAGS_2__DISCARD_36_MASK 0x00000100L +#define CP_NV_FLAGS_2__DISCARD_36 0x00000100L +#define CP_NV_FLAGS_2__END_RCVD_36_MASK 0x00000200L +#define CP_NV_FLAGS_2__END_RCVD_36 0x00000200L +#define CP_NV_FLAGS_2__DISCARD_37_MASK 0x00000400L +#define CP_NV_FLAGS_2__DISCARD_37 0x00000400L +#define CP_NV_FLAGS_2__END_RCVD_37_MASK 0x00000800L +#define CP_NV_FLAGS_2__END_RCVD_37 0x00000800L +#define CP_NV_FLAGS_2__DISCARD_38_MASK 0x00001000L +#define CP_NV_FLAGS_2__DISCARD_38 0x00001000L +#define CP_NV_FLAGS_2__END_RCVD_38_MASK 0x00002000L +#define CP_NV_FLAGS_2__END_RCVD_38 0x00002000L +#define CP_NV_FLAGS_2__DISCARD_39_MASK 0x00004000L +#define CP_NV_FLAGS_2__DISCARD_39 0x00004000L +#define CP_NV_FLAGS_2__END_RCVD_39_MASK 0x00008000L +#define CP_NV_FLAGS_2__END_RCVD_39 0x00008000L +#define CP_NV_FLAGS_2__DISCARD_40_MASK 0x00010000L +#define CP_NV_FLAGS_2__DISCARD_40 0x00010000L +#define CP_NV_FLAGS_2__END_RCVD_40_MASK 0x00020000L +#define CP_NV_FLAGS_2__END_RCVD_40 0x00020000L +#define CP_NV_FLAGS_2__DISCARD_41_MASK 0x00040000L +#define CP_NV_FLAGS_2__DISCARD_41 0x00040000L +#define CP_NV_FLAGS_2__END_RCVD_41_MASK 0x00080000L +#define CP_NV_FLAGS_2__END_RCVD_41 0x00080000L +#define CP_NV_FLAGS_2__DISCARD_42_MASK 0x00100000L +#define CP_NV_FLAGS_2__DISCARD_42 0x00100000L +#define CP_NV_FLAGS_2__END_RCVD_42_MASK 0x00200000L +#define CP_NV_FLAGS_2__END_RCVD_42 0x00200000L +#define CP_NV_FLAGS_2__DISCARD_43_MASK 0x00400000L +#define CP_NV_FLAGS_2__DISCARD_43 0x00400000L +#define CP_NV_FLAGS_2__END_RCVD_43_MASK 0x00800000L +#define CP_NV_FLAGS_2__END_RCVD_43 0x00800000L +#define CP_NV_FLAGS_2__DISCARD_44_MASK 0x01000000L +#define CP_NV_FLAGS_2__DISCARD_44 0x01000000L +#define CP_NV_FLAGS_2__END_RCVD_44_MASK 0x02000000L +#define CP_NV_FLAGS_2__END_RCVD_44 0x02000000L +#define CP_NV_FLAGS_2__DISCARD_45_MASK 0x04000000L +#define CP_NV_FLAGS_2__DISCARD_45 0x04000000L +#define CP_NV_FLAGS_2__END_RCVD_45_MASK 0x08000000L +#define CP_NV_FLAGS_2__END_RCVD_45 0x08000000L +#define CP_NV_FLAGS_2__DISCARD_46_MASK 0x10000000L +#define CP_NV_FLAGS_2__DISCARD_46 0x10000000L +#define CP_NV_FLAGS_2__END_RCVD_46_MASK 0x20000000L +#define CP_NV_FLAGS_2__END_RCVD_46 0x20000000L +#define CP_NV_FLAGS_2__DISCARD_47_MASK 0x40000000L +#define CP_NV_FLAGS_2__DISCARD_47 0x40000000L +#define CP_NV_FLAGS_2__END_RCVD_47_MASK 0x80000000L +#define CP_NV_FLAGS_2__END_RCVD_47 0x80000000L + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48_MASK 0x00000001L +#define CP_NV_FLAGS_3__DISCARD_48 0x00000001L +#define CP_NV_FLAGS_3__END_RCVD_48_MASK 0x00000002L +#define CP_NV_FLAGS_3__END_RCVD_48 0x00000002L +#define CP_NV_FLAGS_3__DISCARD_49_MASK 0x00000004L +#define CP_NV_FLAGS_3__DISCARD_49 0x00000004L +#define CP_NV_FLAGS_3__END_RCVD_49_MASK 0x00000008L +#define CP_NV_FLAGS_3__END_RCVD_49 0x00000008L +#define CP_NV_FLAGS_3__DISCARD_50_MASK 0x00000010L +#define CP_NV_FLAGS_3__DISCARD_50 0x00000010L +#define CP_NV_FLAGS_3__END_RCVD_50_MASK 0x00000020L +#define CP_NV_FLAGS_3__END_RCVD_50 0x00000020L +#define CP_NV_FLAGS_3__DISCARD_51_MASK 0x00000040L +#define CP_NV_FLAGS_3__DISCARD_51 0x00000040L +#define CP_NV_FLAGS_3__END_RCVD_51_MASK 0x00000080L +#define CP_NV_FLAGS_3__END_RCVD_51 0x00000080L +#define CP_NV_FLAGS_3__DISCARD_52_MASK 0x00000100L +#define CP_NV_FLAGS_3__DISCARD_52 0x00000100L +#define CP_NV_FLAGS_3__END_RCVD_52_MASK 0x00000200L +#define CP_NV_FLAGS_3__END_RCVD_52 0x00000200L +#define CP_NV_FLAGS_3__DISCARD_53_MASK 0x00000400L +#define CP_NV_FLAGS_3__DISCARD_53 0x00000400L +#define CP_NV_FLAGS_3__END_RCVD_53_MASK 0x00000800L +#define CP_NV_FLAGS_3__END_RCVD_53 0x00000800L +#define CP_NV_FLAGS_3__DISCARD_54_MASK 0x00001000L +#define CP_NV_FLAGS_3__DISCARD_54 0x00001000L +#define CP_NV_FLAGS_3__END_RCVD_54_MASK 0x00002000L +#define CP_NV_FLAGS_3__END_RCVD_54 0x00002000L +#define CP_NV_FLAGS_3__DISCARD_55_MASK 0x00004000L +#define CP_NV_FLAGS_3__DISCARD_55 0x00004000L +#define CP_NV_FLAGS_3__END_RCVD_55_MASK 0x00008000L +#define CP_NV_FLAGS_3__END_RCVD_55 0x00008000L +#define CP_NV_FLAGS_3__DISCARD_56_MASK 0x00010000L +#define CP_NV_FLAGS_3__DISCARD_56 0x00010000L +#define CP_NV_FLAGS_3__END_RCVD_56_MASK 0x00020000L +#define CP_NV_FLAGS_3__END_RCVD_56 0x00020000L +#define CP_NV_FLAGS_3__DISCARD_57_MASK 0x00040000L +#define CP_NV_FLAGS_3__DISCARD_57 0x00040000L +#define CP_NV_FLAGS_3__END_RCVD_57_MASK 0x00080000L +#define CP_NV_FLAGS_3__END_RCVD_57 0x00080000L +#define CP_NV_FLAGS_3__DISCARD_58_MASK 0x00100000L +#define CP_NV_FLAGS_3__DISCARD_58 0x00100000L +#define CP_NV_FLAGS_3__END_RCVD_58_MASK 0x00200000L +#define CP_NV_FLAGS_3__END_RCVD_58 0x00200000L +#define CP_NV_FLAGS_3__DISCARD_59_MASK 0x00400000L +#define CP_NV_FLAGS_3__DISCARD_59 0x00400000L +#define CP_NV_FLAGS_3__END_RCVD_59_MASK 0x00800000L +#define CP_NV_FLAGS_3__END_RCVD_59 0x00800000L +#define CP_NV_FLAGS_3__DISCARD_60_MASK 0x01000000L +#define CP_NV_FLAGS_3__DISCARD_60 0x01000000L +#define CP_NV_FLAGS_3__END_RCVD_60_MASK 0x02000000L +#define CP_NV_FLAGS_3__END_RCVD_60 0x02000000L +#define CP_NV_FLAGS_3__DISCARD_61_MASK 0x04000000L +#define CP_NV_FLAGS_3__DISCARD_61 0x04000000L +#define CP_NV_FLAGS_3__END_RCVD_61_MASK 0x08000000L +#define CP_NV_FLAGS_3__END_RCVD_61 0x08000000L +#define CP_NV_FLAGS_3__DISCARD_62_MASK 0x10000000L +#define CP_NV_FLAGS_3__DISCARD_62 0x10000000L +#define CP_NV_FLAGS_3__END_RCVD_62_MASK 0x20000000L +#define CP_NV_FLAGS_3__END_RCVD_62 0x20000000L +#define CP_NV_FLAGS_3__DISCARD_63_MASK 0x40000000L +#define CP_NV_FLAGS_3__DISCARD_63 0x40000000L +#define CP_NV_FLAGS_3__END_RCVD_63_MASK 0x80000000L +#define CP_NV_FLAGS_3__END_RCVD_63 0x80000000L + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK 0x0000001fL + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK 0xffffffffL + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER_MASK 0xffffffffL + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY_MASK 0x00000001L +#define CP_STAT__MIU_WR_BUSY 0x00000001L +#define CP_STAT__MIU_RD_REQ_BUSY_MASK 0x00000002L +#define CP_STAT__MIU_RD_REQ_BUSY 0x00000002L +#define CP_STAT__MIU_RD_RETURN_BUSY_MASK 0x00000004L +#define CP_STAT__MIU_RD_RETURN_BUSY 0x00000004L +#define CP_STAT__RBIU_BUSY_MASK 0x00000008L +#define CP_STAT__RBIU_BUSY 0x00000008L +#define CP_STAT__RCIU_BUSY_MASK 0x00000010L +#define CP_STAT__RCIU_BUSY 0x00000010L +#define CP_STAT__CSF_RING_BUSY_MASK 0x00000020L +#define CP_STAT__CSF_RING_BUSY 0x00000020L +#define CP_STAT__CSF_INDIRECTS_BUSY_MASK 0x00000040L +#define CP_STAT__CSF_INDIRECTS_BUSY 0x00000040L +#define CP_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_STAT__CSF_INDIRECT2_BUSY 0x00000080L +#define CP_STAT__CSF_ST_BUSY_MASK 0x00000200L +#define CP_STAT__CSF_ST_BUSY 0x00000200L +#define CP_STAT__CSF_BUSY_MASK 0x00000400L +#define CP_STAT__CSF_BUSY 0x00000400L +#define CP_STAT__RING_QUEUE_BUSY_MASK 0x00000800L +#define CP_STAT__RING_QUEUE_BUSY 0x00000800L +#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK 0x00001000L +#define CP_STAT__INDIRECTS_QUEUE_BUSY 0x00001000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK 0x00002000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY 0x00002000L +#define CP_STAT__ST_QUEUE_BUSY_MASK 0x00010000L +#define CP_STAT__ST_QUEUE_BUSY 0x00010000L +#define CP_STAT__PFP_BUSY_MASK 0x00020000L +#define CP_STAT__PFP_BUSY 0x00020000L +#define CP_STAT__MEQ_RING_BUSY_MASK 0x00040000L +#define CP_STAT__MEQ_RING_BUSY 0x00040000L +#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK 0x00080000L +#define CP_STAT__MEQ_INDIRECTS_BUSY 0x00080000L +#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK 0x00100000L +#define CP_STAT__MEQ_INDIRECT2_BUSY 0x00100000L +#define CP_STAT__MIU_WC_STALL_MASK 0x00200000L +#define CP_STAT__MIU_WC_STALL 0x00200000L +#define CP_STAT__CP_NRT_BUSY_MASK 0x00400000L +#define CP_STAT__CP_NRT_BUSY 0x00400000L +#define CP_STAT___3D_BUSY_MASK 0x00800000L +#define CP_STAT___3D_BUSY 0x00800000L +#define CP_STAT__ME_BUSY_MASK 0x04000000L +#define CP_STAT__ME_BUSY 0x04000000L +#define CP_STAT__ME_WC_BUSY_MASK 0x20000000L +#define CP_STAT__ME_WC_BUSY 0x20000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +#define CP_STAT__CP_BUSY 0x80000000L + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE_MASK 0xffffffffL + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE_MASK 0xffffffffL + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_PM4__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_PM4__STATUS_MASK 0x80000000L +#define COHER_STATUS_PM4__STATUS 0x80000000L + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE_MASK 0xffffffffL + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE_MASK 0xffffffffL + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_HOST__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_HOST__STATUS_MASK 0x80000000L +#define COHER_STATUS_HOST__STATUS 0x80000000L + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0_MASK 0xfffff000L + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1_MASK 0xfffff000L + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2_MASK 0xfffff000L + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3_MASK 0xfffff000L + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4_MASK 0xfffff000L + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5_MASK 0xfffff000L + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6_MASK 0xfffff000L + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7_MASK 0xfffff000L + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH_MASK 0x00003fffL +#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK 0x0000c000L + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL +#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK 0x00000030L +#define RB_COLOR_INFO__COLOR_LINEAR_MASK 0x00000040L +#define RB_COLOR_INFO__COLOR_LINEAR 0x00000040L +#define RB_COLOR_INFO__COLOR_ENDIAN_MASK 0x00000180L +#define RB_COLOR_INFO__COLOR_SWAP_MASK 0x00000600L +#define RB_COLOR_INFO__COLOR_BASE_MASK 0xfffff000L + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK 0x00000001L +#define RB_DEPTH_INFO__DEPTH_FORMAT 0x00000001L +#define RB_DEPTH_INFO__DEPTH_BASE_MASK 0xfffff000L + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF_MASK 0x000000ffL +#define RB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L +#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L +#define RB_STENCILREFMASK__RESERVED0_MASK 0x01000000L +#define RB_STENCILREFMASK__RESERVED0 0x01000000L +#define RB_STENCILREFMASK__RESERVED1_MASK 0x02000000L +#define RB_STENCILREFMASK__RESERVED1 0x02000000L + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF_MASK 0xffffffffL + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED_MASK 0x00000001L +#define RB_COLOR_MASK__WRITE_RED 0x00000001L +#define RB_COLOR_MASK__WRITE_GREEN_MASK 0x00000002L +#define RB_COLOR_MASK__WRITE_GREEN 0x00000002L +#define RB_COLOR_MASK__WRITE_BLUE_MASK 0x00000004L +#define RB_COLOR_MASK__WRITE_BLUE 0x00000004L +#define RB_COLOR_MASK__WRITE_ALPHA_MASK 0x00000008L +#define RB_COLOR_MASK__WRITE_ALPHA 0x00000008L +#define RB_COLOR_MASK__RESERVED2_MASK 0x00000010L +#define RB_COLOR_MASK__RESERVED2 0x00000010L +#define RB_COLOR_MASK__RESERVED3_MASK 0x00000020L +#define RB_COLOR_MASK__RESERVED3 0x00000020L + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED_MASK 0x000000ffL + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN_MASK 0x000000ffL + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE_MASK 0x000000ffL + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK 0x000000ffL + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED_MASK 0x000000ffL +#define RB_FOG_COLOR__FOG_GREEN_MASK 0x0000ff00L +#define RB_FOG_COLOR__FOG_BLUE_MASK 0x00ff0000L + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK 0x000000ffL +#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L +#define RB_STENCILREFMASK_BF__RESERVED4_MASK 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED4 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED5_MASK 0x02000000L +#define RB_STENCILREFMASK_BF__RESERVED5 0x02000000L + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define RB_DEPTHCONTROL__STENCIL_ENABLE 0x00000001L +#define RB_DEPTHCONTROL__Z_ENABLE_MASK 0x00000002L +#define RB_DEPTHCONTROL__Z_ENABLE 0x00000002L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE 0x00000004L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK 0x00000008L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE 0x00000008L +#define RB_DEPTHCONTROL__ZFUNC_MASK 0x00000070L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE 0x00000080L +#define RB_DEPTHCONTROL__STENCILFUNC_MASK 0x00000700L +#define RB_DEPTHCONTROL__STENCILFAIL_MASK 0x00003800L +#define RB_DEPTHCONTROL__STENCILZPASS_MASK 0x0001c000L +#define RB_DEPTHCONTROL__STENCILZFAIL_MASK 0x000e0000L +#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK 0x03800000L +#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK 0x1c000000L +#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK 0xe0000000L + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_MASK 0x40000000L +#define RB_BLENDCONTROL__BLEND_FORCE 0x40000000L + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC_MASK 0x00000007L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK 0x00000008L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE 0x00000008L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK 0x00000010L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE 0x00000010L +#define RB_COLORCONTROL__BLEND_DISABLE_MASK 0x00000020L +#define RB_COLORCONTROL__BLEND_DISABLE 0x00000020L +#define RB_COLORCONTROL__FOG_ENABLE_MASK 0x00000040L +#define RB_COLORCONTROL__FOG_ENABLE 0x00000040L +#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK 0x00000080L +#define RB_COLORCONTROL__VS_EXPORTS_FOG 0x00000080L +#define RB_COLORCONTROL__ROP_CODE_MASK 0x00000f00L +#define RB_COLORCONTROL__DITHER_MODE_MASK 0x00003000L +#define RB_COLORCONTROL__DITHER_TYPE_MASK 0x0000c000L +#define RB_COLORCONTROL__PIXEL_FOG_MASK 0x00010000L +#define RB_COLORCONTROL__PIXEL_FOG 0x00010000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK 0x03000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK 0x30000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000L + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE_MASK 0x00000007L + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK 0xffffffffL + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK 0x00000007L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000008L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE 0x00000008L +#define RB_COPY_CONTROL__CLEAR_MASK_MASK 0x000000f0L + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK 0xfffff000L + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK 0x000001ffL + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK 0x00000007L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK 0x000000f0L +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK 0x00000300L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK 0x00000c00L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK 0x00003000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK 0x00020000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA 0x00020000L + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK 0x00001fffL +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK 0x03ffe000L + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK 0x00000001L +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT 0x00000001L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK 0x00000002L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT 0x00000002L + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK 0xffffffffL + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001L +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE 0x00000001L +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK 0x00000006L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK 0x00000008L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM 0x00000008L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP 0x00000020L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP 0x00000040L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK 0x00000080L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE 0x00000080L +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK 0x00001f00L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK 0x00004000L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE 0x00004000L +#define RB_BC_CONTROL__CRC_MODE_MASK 0x00008000L +#define RB_BC_CONTROL__CRC_MODE 0x00008000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK 0x00010000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS 0x00010000L +#define RB_BC_CONTROL__DISABLE_ACCUM_MASK 0x00020000L +#define RB_BC_CONTROL__DISABLE_ACCUM 0x00020000L +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK 0x003c0000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE 0x00400000L +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000L +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000L +#define RB_BC_CONTROL__CRC_SYSTEM_MASK 0x40000000L +#define RB_BC_CONTROL__CRC_SYSTEM 0x40000000L +#define RB_BC_CONTROL__RESERVED6_MASK 0x80000000L +#define RB_BC_CONTROL__RESERVED6 0x80000000L + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK 0x00000030L +#define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA_MASK 0xffffffffL + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK 0x00000001L +#define RB_CRC_CONTROL__CRC_RD_ADVANCE 0x00000001L + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK_MASK 0xffffffffL + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK 0xffffffffL + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK 0xffffffffL + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK 0xffffffffL + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK 0xffffffffL + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL 0x00000008L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK 0x00000010L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL 0x00000010L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK 0x00000020L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL 0x00000020L +#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK 0x00000040L +#define RB_DEBUG_0__RDREQ_Z1_FULL 0x00000040L +#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK 0x00000080L +#define RB_DEBUG_0__RDREQ_Z0_FULL 0x00000080L +#define RB_DEBUG_0__RDREQ_C1_FULL_MASK 0x00000100L +#define RB_DEBUG_0__RDREQ_C1_FULL 0x00000100L +#define RB_DEBUG_0__RDREQ_C0_FULL_MASK 0x00000200L +#define RB_DEBUG_0__RDREQ_C0_FULL 0x00000200L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL 0x00000800L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL 0x00002000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK 0x00008000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL 0x00008000L +#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK 0x00010000L +#define RB_DEBUG_0__WRREQ_Z1_FULL 0x00010000L +#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK 0x00020000L +#define RB_DEBUG_0__WRREQ_Z0_FULL 0x00020000L +#define RB_DEBUG_0__WRREQ_C1_FULL_MASK 0x00040000L +#define RB_DEBUG_0__WRREQ_C1_FULL 0x00040000L +#define RB_DEBUG_0__WRREQ_C0_FULL_MASK 0x00080000L +#define RB_DEBUG_0__WRREQ_C0_FULL 0x00080000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL 0x00200000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK 0x00800000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL 0x00800000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL 0x01000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK 0x02000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL 0x02000000L +#define RB_DEBUG_0__C_SX_LAT_FULL_MASK 0x04000000L +#define RB_DEBUG_0__C_SX_LAT_FULL 0x04000000L +#define RB_DEBUG_0__C_SX_CMD_FULL_MASK 0x08000000L +#define RB_DEBUG_0__C_SX_CMD_FULL 0x08000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK 0x10000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL 0x10000000L +#define RB_DEBUG_0__C_REQ_FULL_MASK 0x20000000L +#define RB_DEBUG_0__C_REQ_FULL 0x20000000L +#define RB_DEBUG_0__C_MASK_FULL_MASK 0x40000000L +#define RB_DEBUG_0__C_MASK_FULL 0x40000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK 0x80000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL 0x80000000L + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK 0x00000001L +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY 0x00000001L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK 0x00000002L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY 0x00000002L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK 0x00000004L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY 0x00000004L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK 0x00000008L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY 0x00000008L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY 0x00000010L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY 0x00000020L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK 0x00000040L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY 0x00000040L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK 0x00000080L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY 0x00000080L +#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK 0x00000100L +#define RB_DEBUG_1__RDREQ_C1_EMPTY 0x00000100L +#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK 0x00000200L +#define RB_DEBUG_1__RDREQ_C0_EMPTY 0x00000200L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY 0x00000800L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY 0x00002000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK 0x00008000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY 0x00008000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK 0x00010000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY 0x00010000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK 0x00020000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY 0x00020000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK 0x00040000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY 0x00040000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK 0x00080000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY 0x00080000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY 0x00200000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY 0x00800000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY 0x01000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY 0x02000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK 0x04000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY 0x04000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK 0x08000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY 0x08000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK 0x10000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY 0x10000000L +#define RB_DEBUG_1__C_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_1__C_REQ_EMPTY 0x20000000L +#define RB_DEBUG_1__C_MASK_EMPTY_MASK 0x40000000L +#define RB_DEBUG_1__C_MASK_EMPTY 0x40000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK 0x80000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY 0x80000000L + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK 0x0000000fL +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK 0x000007f0L +#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK 0x00000800L +#define RB_DEBUG_2__MEM_EXPORT_FLAG 0x00000800L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK 0x00001000L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG 0x00001000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK 0x00002000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT 0x00002000L +#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK 0x00004000L +#define RB_DEBUG_2__EZ_INFTILE_FULL 0x00004000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK 0x00008000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL 0x00008000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK 0x00010000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL 0x00010000L +#define RB_DEBUG_2__Z0_MASK_FULL_MASK 0x00020000L +#define RB_DEBUG_2__Z0_MASK_FULL 0x00020000L +#define RB_DEBUG_2__Z1_MASK_FULL_MASK 0x00040000L +#define RB_DEBUG_2__Z1_MASK_FULL 0x00040000L +#define RB_DEBUG_2__Z0_REQ_FULL_MASK 0x00080000L +#define RB_DEBUG_2__Z0_REQ_FULL 0x00080000L +#define RB_DEBUG_2__Z1_REQ_FULL_MASK 0x00100000L +#define RB_DEBUG_2__Z1_REQ_FULL 0x00100000L +#define RB_DEBUG_2__Z_SAMP_FULL_MASK 0x00200000L +#define RB_DEBUG_2__Z_SAMP_FULL 0x00200000L +#define RB_DEBUG_2__Z_TILE_FULL_MASK 0x00400000L +#define RB_DEBUG_2__Z_TILE_FULL 0x00400000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK 0x00800000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY 0x00800000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK 0x01000000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY 0x01000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY 0x02000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK 0x04000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY 0x04000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK 0x08000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY 0x08000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK 0x10000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY 0x10000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY 0x20000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK 0x40000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY 0x40000000L +#define RB_DEBUG_2__Z_TILE_EMPTY_MASK 0x80000000L +#define RB_DEBUG_2__Z_TILE_EMPTY 0x80000000L + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID_MASK 0x0000000fL +#define RB_DEBUG_3__ACCUM_FLUSHING_MASK 0x000000f0L +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK 0x00004000L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID 0x00004000L +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK 0x00078000L +#define RB_DEBUG_3__SHD_FULL_MASK 0x00080000L +#define RB_DEBUG_3__SHD_FULL 0x00080000L +#define RB_DEBUG_3__SHD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_3__SHD_EMPTY 0x00100000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK 0x01000000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL 0x01000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY 0x02000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK 0x04000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY 0x04000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK 0x08000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL 0x08000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK 0x10000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL 0x10000000L + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK 0x00000001L +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG 0x00000001L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK 0x00000002L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG 0x00000002L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG 0x00000004L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG 0x00000008L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY 0x00000010L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY 0x00000020L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK 0x00000040L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL 0x00000040L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK 0x00000080L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL 0x00000080L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW 0x00000100L +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK 0x00001e00L + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK 0x00000001L +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR 0x00000001L + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED_MASK 0xffffffffL + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK 0x00000600L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h new file mode 100644 index 000000000000..ec7c7e126612 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h @@ -0,0 +1,590 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamato_OFFSET_HEADER +#define _yamato_OFFSET_HEADER + +// Registers from PA block + +#define mmPA_CL_VPORT_XSCALE 0x210F +#define mmPA_CL_VPORT_XOFFSET 0x2110 +#define mmPA_CL_VPORT_YSCALE 0x2111 +#define mmPA_CL_VPORT_YOFFSET 0x2112 +#define mmPA_CL_VPORT_ZSCALE 0x2113 +#define mmPA_CL_VPORT_ZOFFSET 0x2114 +#define mmPA_CL_VTE_CNTL 0x2206 +#define mmPA_CL_CLIP_CNTL 0x2204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0x2303 +#define mmPA_CL_GB_VERT_DISC_ADJ 0x2304 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x2305 +#define mmPA_CL_GB_HORZ_DISC_ADJ 0x2306 +#define mmPA_CL_ENHANCE 0x0C85 +#define mmPA_SC_ENHANCE 0x0CA5 +#define mmPA_SU_VTX_CNTL 0x2302 +#define mmPA_SU_POINT_SIZE 0x2280 +#define mmPA_SU_POINT_MINMAX 0x2281 +#define mmPA_SU_LINE_CNTL 0x2282 +#define mmPA_SU_FACE_DATA 0x0C86 +#define mmPA_SU_SC_MODE_CNTL 0x2205 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 +#define mmPA_SU_PERFCOUNTER0_SELECT 0x0C88 +#define mmPA_SU_PERFCOUNTER1_SELECT 0x0C89 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x0C8A +#define mmPA_SU_PERFCOUNTER3_SELECT 0x0C8B +#define mmPA_SU_PERFCOUNTER0_LOW 0x0C8C +#define mmPA_SU_PERFCOUNTER0_HI 0x0C8D +#define mmPA_SU_PERFCOUNTER1_LOW 0x0C8E +#define mmPA_SU_PERFCOUNTER1_HI 0x0C8F +#define mmPA_SU_PERFCOUNTER2_LOW 0x0C90 +#define mmPA_SU_PERFCOUNTER2_HI 0x0C91 +#define mmPA_SU_PERFCOUNTER3_LOW 0x0C92 +#define mmPA_SU_PERFCOUNTER3_HI 0x0C93 +#define mmPA_SC_WINDOW_OFFSET 0x2080 +#define mmPA_SC_AA_CONFIG 0x2301 +#define mmPA_SC_AA_MASK 0x2312 +#define mmPA_SC_LINE_STIPPLE 0x2283 +#define mmPA_SC_LINE_CNTL 0x2300 +#define mmPA_SC_WINDOW_SCISSOR_TL 0x2081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0x2082 +#define mmPA_SC_SCREEN_SCISSOR_TL 0x200E +#define mmPA_SC_SCREEN_SCISSOR_BR 0x200F +#define mmPA_SC_VIZ_QUERY 0x2293 +#define mmPA_SC_VIZ_QUERY_STATUS 0x0C44 +#define mmPA_SC_LINE_STIPPLE_STATE 0x0C40 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x0C98 +#define mmPA_SC_PERFCOUNTER0_LOW 0x0C99 +#define mmPA_SC_PERFCOUNTER0_HI 0x0C9A +#define mmPA_CL_CNTL_STATUS 0x0C84 +#define mmPA_SU_CNTL_STATUS 0x0C94 +#define mmPA_SC_CNTL_STATUS 0x0CA4 +#define mmPA_SU_DEBUG_CNTL 0x0C80 +#define mmPA_SU_DEBUG_DATA 0x0C81 +#define mmPA_SC_DEBUG_CNTL 0x0C82 +#define mmPA_SC_DEBUG_DATA 0x0C83 + + +// Registers from VGT block + +#define mmGFX_COPY_STATE 0x21F4 +#define mmVGT_DRAW_INITIATOR 0x21FC +#define mmVGT_EVENT_INITIATOR 0x21F9 +#define mmVGT_DMA_BASE 0x21FA +#define mmVGT_DMA_SIZE 0x21FB +#define mmVGT_BIN_BASE 0x21FE +#define mmVGT_BIN_SIZE 0x21FF +#define mmVGT_CURRENT_BIN_ID_MIN 0x2207 +#define mmVGT_CURRENT_BIN_ID_MAX 0x2203 +#define mmVGT_IMMED_DATA 0x21FD +#define mmVGT_MAX_VTX_INDX 0x2100 +#define mmVGT_MIN_VTX_INDX 0x2101 +#define mmVGT_INDX_OFFSET 0x2102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 +#define mmVGT_OUT_DEALLOC_CNTL 0x2317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103 +#define mmVGT_ENHANCE 0x2294 +#define mmVGT_VTX_VECT_EJECT_REG 0x0C2C +#define mmVGT_LAST_COPY_STATE 0x0C30 +#define mmVGT_DEBUG_CNTL 0x0C38 +#define mmVGT_DEBUG_DATA 0x0C39 +#define mmVGT_CNTL_STATUS 0x0C3C +#define mmVGT_CRC_SQ_DATA 0x0C3A +#define mmVGT_CRC_SQ_CTRL 0x0C3B +#define mmVGT_PERFCOUNTER0_SELECT 0x0C48 +#define mmVGT_PERFCOUNTER1_SELECT 0x0C49 +#define mmVGT_PERFCOUNTER2_SELECT 0x0C4A +#define mmVGT_PERFCOUNTER3_SELECT 0x0C4B +#define mmVGT_PERFCOUNTER0_LOW 0x0C4C +#define mmVGT_PERFCOUNTER1_LOW 0x0C4E +#define mmVGT_PERFCOUNTER2_LOW 0x0C50 +#define mmVGT_PERFCOUNTER3_LOW 0x0C52 +#define mmVGT_PERFCOUNTER0_HI 0x0C4D +#define mmVGT_PERFCOUNTER1_HI 0x0C4F +#define mmVGT_PERFCOUNTER2_HI 0x0C51 +#define mmVGT_PERFCOUNTER3_HI 0x0C53 + + +// Registers from TP block + +#define mmTC_CNTL_STATUS 0x0E00 +#define mmTCR_CHICKEN 0x0E02 +#define mmTCF_CHICKEN 0x0E03 +#define mmTCM_CHICKEN 0x0E04 +#define mmTCR_PERFCOUNTER0_SELECT 0x0E05 +#define mmTCR_PERFCOUNTER1_SELECT 0x0E08 +#define mmTCR_PERFCOUNTER0_HI 0x0E06 +#define mmTCR_PERFCOUNTER1_HI 0x0E09 +#define mmTCR_PERFCOUNTER0_LOW 0x0E07 +#define mmTCR_PERFCOUNTER1_LOW 0x0E0A +#define mmTP_TC_CLKGATE_CNTL 0x0E17 +#define mmTPC_CNTL_STATUS 0x0E18 +#define mmTPC_DEBUG0 0x0E19 +#define mmTPC_DEBUG1 0x0E1A +#define mmTPC_CHICKEN 0x0E1B +#define mmTP0_CNTL_STATUS 0x0E1C +#define mmTP0_DEBUG 0x0E1D +#define mmTP0_CHICKEN 0x0E1E +#define mmTP0_PERFCOUNTER0_SELECT 0x0E1F +#define mmTP0_PERFCOUNTER0_HI 0x0E20 +#define mmTP0_PERFCOUNTER0_LOW 0x0E21 +#define mmTP0_PERFCOUNTER1_SELECT 0x0E22 +#define mmTP0_PERFCOUNTER1_HI 0x0E23 +#define mmTP0_PERFCOUNTER1_LOW 0x0E24 +#define mmTCM_PERFCOUNTER0_SELECT 0x0E54 +#define mmTCM_PERFCOUNTER1_SELECT 0x0E57 +#define mmTCM_PERFCOUNTER0_HI 0x0E55 +#define mmTCM_PERFCOUNTER1_HI 0x0E58 +#define mmTCM_PERFCOUNTER0_LOW 0x0E56 +#define mmTCM_PERFCOUNTER1_LOW 0x0E59 +#define mmTCF_PERFCOUNTER0_SELECT 0x0E5A +#define mmTCF_PERFCOUNTER1_SELECT 0x0E5D +#define mmTCF_PERFCOUNTER2_SELECT 0x0E60 +#define mmTCF_PERFCOUNTER3_SELECT 0x0E63 +#define mmTCF_PERFCOUNTER4_SELECT 0x0E66 +#define mmTCF_PERFCOUNTER5_SELECT 0x0E69 +#define mmTCF_PERFCOUNTER6_SELECT 0x0E6C +#define mmTCF_PERFCOUNTER7_SELECT 0x0E6F +#define mmTCF_PERFCOUNTER8_SELECT 0x0E72 +#define mmTCF_PERFCOUNTER9_SELECT 0x0E75 +#define mmTCF_PERFCOUNTER10_SELECT 0x0E78 +#define mmTCF_PERFCOUNTER11_SELECT 0x0E7B +#define mmTCF_PERFCOUNTER0_HI 0x0E5B +#define mmTCF_PERFCOUNTER1_HI 0x0E5E +#define mmTCF_PERFCOUNTER2_HI 0x0E61 +#define mmTCF_PERFCOUNTER3_HI 0x0E64 +#define mmTCF_PERFCOUNTER4_HI 0x0E67 +#define mmTCF_PERFCOUNTER5_HI 0x0E6A +#define mmTCF_PERFCOUNTER6_HI 0x0E6D +#define mmTCF_PERFCOUNTER7_HI 0x0E70 +#define mmTCF_PERFCOUNTER8_HI 0x0E73 +#define mmTCF_PERFCOUNTER9_HI 0x0E76 +#define mmTCF_PERFCOUNTER10_HI 0x0E79 +#define mmTCF_PERFCOUNTER11_HI 0x0E7C +#define mmTCF_PERFCOUNTER0_LOW 0x0E5C +#define mmTCF_PERFCOUNTER1_LOW 0x0E5F +#define mmTCF_PERFCOUNTER2_LOW 0x0E62 +#define mmTCF_PERFCOUNTER3_LOW 0x0E65 +#define mmTCF_PERFCOUNTER4_LOW 0x0E68 +#define mmTCF_PERFCOUNTER5_LOW 0x0E6B +#define mmTCF_PERFCOUNTER6_LOW 0x0E6E +#define mmTCF_PERFCOUNTER7_LOW 0x0E71 +#define mmTCF_PERFCOUNTER8_LOW 0x0E74 +#define mmTCF_PERFCOUNTER9_LOW 0x0E77 +#define mmTCF_PERFCOUNTER10_LOW 0x0E7A +#define mmTCF_PERFCOUNTER11_LOW 0x0E7D +#define mmTCF_DEBUG 0x0EC0 +#define mmTCA_FIFO_DEBUG 0x0EC1 +#define mmTCA_PROBE_DEBUG 0x0EC2 +#define mmTCA_TPC_DEBUG 0x0EC3 +#define mmTCB_CORE_DEBUG 0x0EC4 +#define mmTCB_TAG0_DEBUG 0x0EC5 +#define mmTCB_TAG1_DEBUG 0x0EC6 +#define mmTCB_TAG2_DEBUG 0x0EC7 +#define mmTCB_TAG3_DEBUG 0x0EC8 +#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9 +#define mmTCB_FETCH_GEN_WALKER_DEBUG 0x0ECB +#define mmTCB_FETCH_GEN_PIPE0_DEBUG 0x0ECC +#define mmTCD_INPUT0_DEBUG 0x0ED0 +#define mmTCD_DEGAMMA_DEBUG 0x0ED4 +#define mmTCD_DXTMUX_SCTARB_DEBUG 0x0ED5 +#define mmTCD_DXTC_ARB_DEBUG 0x0ED6 +#define mmTCD_STALLS_DEBUG 0x0ED7 +#define mmTCO_STALLS_DEBUG 0x0EE0 +#define mmTCO_QUAD0_DEBUG0 0x0EE1 +#define mmTCO_QUAD0_DEBUG1 0x0EE2 + + +// Registers from TC block + + + +// Registers from SQ block + +#define mmSQ_GPR_MANAGEMENT 0x0D00 +#define mmSQ_FLOW_CONTROL 0x0D01 +#define mmSQ_INST_STORE_MANAGMENT 0x0D02 +#define mmSQ_RESOURCE_MANAGMENT 0x0D03 +#define mmSQ_EO_RT 0x0D04 +#define mmSQ_DEBUG_MISC 0x0D05 +#define mmSQ_ACTIVITY_METER_CNTL 0x0D06 +#define mmSQ_ACTIVITY_METER_STATUS 0x0D07 +#define mmSQ_INPUT_ARB_PRIORITY 0x0D08 +#define mmSQ_THREAD_ARB_PRIORITY 0x0D09 +#define mmSQ_VS_WATCHDOG_TIMER 0x0D0A +#define mmSQ_PS_WATCHDOG_TIMER 0x0D0B +#define mmSQ_INT_CNTL 0x0D34 +#define mmSQ_INT_STATUS 0x0D35 +#define mmSQ_INT_ACK 0x0D36 +#define mmSQ_DEBUG_INPUT_FSM 0x0DAE +#define mmSQ_DEBUG_CONST_MGR_FSM 0x0DAF +#define mmSQ_DEBUG_TP_FSM 0x0DB0 +#define mmSQ_DEBUG_FSM_ALU_0 0x0DB1 +#define mmSQ_DEBUG_FSM_ALU_1 0x0DB2 +#define mmSQ_DEBUG_EXP_ALLOC 0x0DB3 +#define mmSQ_DEBUG_PTR_BUFF 0x0DB4 +#define mmSQ_DEBUG_GPR_VTX 0x0DB5 +#define mmSQ_DEBUG_GPR_PIX 0x0DB6 +#define mmSQ_DEBUG_TB_STATUS_SEL 0x0DB7 +#define mmSQ_DEBUG_VTX_TB_0 0x0DB8 +#define mmSQ_DEBUG_VTX_TB_1 0x0DB9 +#define mmSQ_DEBUG_VTX_TB_STATUS_REG 0x0DBA +#define mmSQ_DEBUG_VTX_TB_STATE_MEM 0x0DBB +#define mmSQ_DEBUG_PIX_TB_0 0x0DBC +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0 +#define mmSQ_DEBUG_PIX_TB_STATE_MEM 0x0DC1 +#define mmSQ_PERFCOUNTER0_SELECT 0x0DC8 +#define mmSQ_PERFCOUNTER1_SELECT 0x0DC9 +#define mmSQ_PERFCOUNTER2_SELECT 0x0DCA +#define mmSQ_PERFCOUNTER3_SELECT 0x0DCB +#define mmSQ_PERFCOUNTER0_LOW 0x0DCC +#define mmSQ_PERFCOUNTER0_HI 0x0DCD +#define mmSQ_PERFCOUNTER1_LOW 0x0DCE +#define mmSQ_PERFCOUNTER1_HI 0x0DCF +#define mmSQ_PERFCOUNTER2_LOW 0x0DD0 +#define mmSQ_PERFCOUNTER2_HI 0x0DD1 +#define mmSQ_PERFCOUNTER3_LOW 0x0DD2 +#define mmSQ_PERFCOUNTER3_HI 0x0DD3 +#define mmSX_PERFCOUNTER0_SELECT 0x0DD4 +#define mmSX_PERFCOUNTER0_LOW 0x0DD8 +#define mmSX_PERFCOUNTER0_HI 0x0DD9 +#define mmSQ_INSTRUCTION_ALU_0 0x5000 +#define mmSQ_INSTRUCTION_ALU_1 0x5001 +#define mmSQ_INSTRUCTION_ALU_2 0x5002 +#define mmSQ_INSTRUCTION_CF_EXEC_0 0x5080 +#define mmSQ_INSTRUCTION_CF_EXEC_1 0x5081 +#define mmSQ_INSTRUCTION_CF_EXEC_2 0x5082 +#define mmSQ_INSTRUCTION_CF_LOOP_0 0x5083 +#define mmSQ_INSTRUCTION_CF_LOOP_1 0x5084 +#define mmSQ_INSTRUCTION_CF_LOOP_2 0x5085 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088 +#define mmSQ_INSTRUCTION_CF_ALLOC_0 0x5089 +#define mmSQ_INSTRUCTION_CF_ALLOC_1 0x508A +#define mmSQ_INSTRUCTION_CF_ALLOC_2 0x508B +#define mmSQ_INSTRUCTION_TFETCH_0 0x5043 +#define mmSQ_INSTRUCTION_TFETCH_1 0x5044 +#define mmSQ_INSTRUCTION_TFETCH_2 0x5045 +#define mmSQ_INSTRUCTION_VFETCH_0 0x5040 +#define mmSQ_INSTRUCTION_VFETCH_1 0x5041 +#define mmSQ_INSTRUCTION_VFETCH_2 0x5042 +#define mmSQ_CONSTANT_0 0x4000 +#define mmSQ_CONSTANT_1 0x4001 +#define mmSQ_CONSTANT_2 0x4002 +#define mmSQ_CONSTANT_3 0x4003 +#define mmSQ_FETCH_0 0x4800 +#define mmSQ_FETCH_1 0x4801 +#define mmSQ_FETCH_2 0x4802 +#define mmSQ_FETCH_3 0x4803 +#define mmSQ_FETCH_4 0x4804 +#define mmSQ_FETCH_5 0x4805 +#define mmSQ_CONSTANT_VFETCH_0 0x4806 +#define mmSQ_CONSTANT_VFETCH_1 0x4808 +#define mmSQ_CONSTANT_T2 0x480C +#define mmSQ_CONSTANT_T3 0x4812 +#define mmSQ_CF_BOOLEANS 0x4900 +#define mmSQ_CF_LOOP 0x4908 +#define mmSQ_CONSTANT_RT_0 0x4940 +#define mmSQ_CONSTANT_RT_1 0x4941 +#define mmSQ_CONSTANT_RT_2 0x4942 +#define mmSQ_CONSTANT_RT_3 0x4943 +#define mmSQ_FETCH_RT_0 0x4D40 +#define mmSQ_FETCH_RT_1 0x4D41 +#define mmSQ_FETCH_RT_2 0x4D42 +#define mmSQ_FETCH_RT_3 0x4D43 +#define mmSQ_FETCH_RT_4 0x4D44 +#define mmSQ_FETCH_RT_5 0x4D45 +#define mmSQ_CF_RT_BOOLEANS 0x4E00 +#define mmSQ_CF_RT_LOOP 0x4E14 +#define mmSQ_VS_PROGRAM 0x21F7 +#define mmSQ_PS_PROGRAM 0x21F6 +#define mmSQ_CF_PROGRAM_SIZE 0x2315 +#define mmSQ_INTERPOLATOR_CNTL 0x2182 +#define mmSQ_PROGRAM_CNTL 0x2180 +#define mmSQ_WRAPPING_0 0x2183 +#define mmSQ_WRAPPING_1 0x2184 +#define mmSQ_VS_CONST 0x2307 +#define mmSQ_PS_CONST 0x2308 +#define mmSQ_CONTEXT_MISC 0x2181 +#define mmSQ_CF_RD_BASE 0x21F5 +#define mmSQ_DEBUG_MISC_0 0x2309 +#define mmSQ_DEBUG_MISC_1 0x230A + + +// Registers from SX block + + + +// Registers from MH block + +#define mmMH_ARBITER_CONFIG 0x0A40 +#define mmMH_CLNT_AXI_ID_REUSE 0x0A41 +#define mmMH_INTERRUPT_MASK 0x0A42 +#define mmMH_INTERRUPT_STATUS 0x0A43 +#define mmMH_INTERRUPT_CLEAR 0x0A44 +#define mmMH_AXI_ERROR 0x0A45 +#define mmMH_PERFCOUNTER0_SELECT 0x0A46 +#define mmMH_PERFCOUNTER1_SELECT 0x0A4A +#define mmMH_PERFCOUNTER0_CONFIG 0x0A47 +#define mmMH_PERFCOUNTER1_CONFIG 0x0A4B +#define mmMH_PERFCOUNTER0_LOW 0x0A48 +#define mmMH_PERFCOUNTER1_LOW 0x0A4C +#define mmMH_PERFCOUNTER0_HI 0x0A49 +#define mmMH_PERFCOUNTER1_HI 0x0A4D +#define mmMH_DEBUG_CTRL 0x0A4E +#define mmMH_DEBUG_DATA 0x0A4F +#define mmMH_AXI_HALT_CONTROL 0x0A50 +#define mmMH_MMU_CONFIG 0x0040 +#define mmMH_MMU_VA_RANGE 0x0041 +#define mmMH_MMU_PT_BASE 0x0042 +#define mmMH_MMU_PAGE_FAULT 0x0043 +#define mmMH_MMU_TRAN_ERROR 0x0044 +#define mmMH_MMU_INVALIDATE 0x0045 +#define mmMH_MMU_MPU_BASE 0x0046 +#define mmMH_MMU_MPU_END 0x0047 + + +// Registers from RBBM block + +#define mmWAIT_UNTIL 0x05C8 +#define mmRBBM_ISYNC_CNTL 0x05C9 +#define mmRBBM_STATUS 0x05D0 +#define mmRBBM_DSPLY 0x0391 +#define mmRBBM_RENDER_LATEST 0x0392 +#define mmRBBM_RTL_RELEASE 0x0000 +#define mmRBBM_PATCH_RELEASE 0x0001 +#define mmRBBM_AUXILIARY_CONFIG 0x0002 +#define mmRBBM_PERIPHID0 0x03F8 +#define mmRBBM_PERIPHID1 0x03F9 +#define mmRBBM_PERIPHID2 0x03FA +#define mmRBBM_PERIPHID3 0x03FB +#define mmRBBM_CNTL 0x003B +#define mmRBBM_SKEW_CNTL 0x003D +#define mmRBBM_SOFT_RESET 0x003C +#define mmRBBM_PM_OVERRIDE1 0x039C +#define mmRBBM_PM_OVERRIDE2 0x039D +#define mmGC_SYS_IDLE 0x039E +#define mmNQWAIT_UNTIL 0x0394 +#define mmRBBM_DEBUG_OUT 0x03A0 +#define mmRBBM_DEBUG_CNTL 0x03A1 +#define mmRBBM_DEBUG 0x039B +#define mmRBBM_READ_ERROR 0x03B3 +#define mmRBBM_WAIT_IDLE_CLOCKS 0x03B2 +#define mmRBBM_INT_CNTL 0x03B4 +#define mmRBBM_INT_STATUS 0x03B5 +#define mmRBBM_INT_ACK 0x03B6 +#define mmMASTER_INT_SIGNAL 0x03B7 +#define mmRBBM_PERFCOUNTER1_SELECT 0x0395 +#define mmRBBM_PERFCOUNTER1_LO 0x0397 +#define mmRBBM_PERFCOUNTER1_HI 0x0398 + + +// Registers from CP block + +#define mmCP_RB_BASE 0x01C0 +#define mmCP_RB_CNTL 0x01C1 +#define mmCP_RB_RPTR_ADDR 0x01C3 +#define mmCP_RB_RPTR 0x01C4 +#define mmCP_RB_RPTR_WR 0x01C7 +#define mmCP_RB_WPTR 0x01C5 +#define mmCP_RB_WPTR_DELAY 0x01C6 +#define mmCP_RB_WPTR_BASE 0x01C8 +#define mmCP_IB1_BASE 0x0458 +#define mmCP_IB1_BUFSZ 0x0459 +#define mmCP_IB2_BASE 0x045A +#define mmCP_IB2_BUFSZ 0x045B +#define mmCP_ST_BASE 0x044D +#define mmCP_ST_BUFSZ 0x044E +#define mmCP_QUEUE_THRESHOLDS 0x01D5 +#define mmCP_MEQ_THRESHOLDS 0x01D6 +#define mmCP_CSQ_AVAIL 0x01D7 +#define mmCP_STQ_AVAIL 0x01D8 +#define mmCP_MEQ_AVAIL 0x01D9 +#define mmCP_CSQ_RB_STAT 0x01FD +#define mmCP_CSQ_IB1_STAT 0x01FE +#define mmCP_CSQ_IB2_STAT 0x01FF +#define mmCP_NON_PREFETCH_CNTRS 0x0440 +#define mmCP_STQ_ST_STAT 0x0443 +#define mmCP_MEQ_STAT 0x044F +#define mmCP_MIU_TAG_STAT 0x0452 +#define mmCP_CMD_INDEX 0x01DA +#define mmCP_CMD_DATA 0x01DB +#define mmCP_ME_CNTL 0x01F6 +#define mmCP_ME_STATUS 0x01F7 +#define mmCP_ME_RAM_WADDR 0x01F8 +#define mmCP_ME_RAM_RADDR 0x01F9 +#define mmCP_ME_RAM_DATA 0x01FA +#define mmCP_ME_RDADDR 0x01EA +#define mmCP_DEBUG 0x01FC +#define mmSCRATCH_REG0 0x0578 +#define mmGUI_SCRATCH_REG0 0x0578 +#define mmSCRATCH_REG1 0x0579 +#define mmGUI_SCRATCH_REG1 0x0579 +#define mmSCRATCH_REG2 0x057A +#define mmGUI_SCRATCH_REG2 0x057A +#define mmSCRATCH_REG3 0x057B +#define mmGUI_SCRATCH_REG3 0x057B +#define mmSCRATCH_REG4 0x057C +#define mmGUI_SCRATCH_REG4 0x057C +#define mmSCRATCH_REG5 0x057D +#define mmGUI_SCRATCH_REG5 0x057D +#define mmSCRATCH_REG6 0x057E +#define mmGUI_SCRATCH_REG6 0x057E +#define mmSCRATCH_REG7 0x057F +#define mmGUI_SCRATCH_REG7 0x057F +#define mmSCRATCH_UMSK 0x01DC +#define mmSCRATCH_ADDR 0x01DD +#define mmCP_ME_VS_EVENT_SRC 0x0600 +#define mmCP_ME_VS_EVENT_ADDR 0x0601 +#define mmCP_ME_VS_EVENT_DATA 0x0602 +#define mmCP_ME_VS_EVENT_ADDR_SWM 0x0603 +#define mmCP_ME_VS_EVENT_DATA_SWM 0x0604 +#define mmCP_ME_PS_EVENT_SRC 0x0605 +#define mmCP_ME_PS_EVENT_ADDR 0x0606 +#define mmCP_ME_PS_EVENT_DATA 0x0607 +#define mmCP_ME_PS_EVENT_ADDR_SWM 0x0608 +#define mmCP_ME_PS_EVENT_DATA_SWM 0x0609 +#define mmCP_ME_CF_EVENT_SRC 0x060A +#define mmCP_ME_CF_EVENT_ADDR 0x060B +#define mmCP_ME_CF_EVENT_DATA 0x060C +#define mmCP_ME_NRT_ADDR 0x060D +#define mmCP_ME_NRT_DATA 0x060E +#define mmCP_ME_VS_FETCH_DONE_SRC 0x0612 +#define mmCP_ME_VS_FETCH_DONE_ADDR 0x0613 +#define mmCP_ME_VS_FETCH_DONE_DATA 0x0614 +#define mmCP_INT_CNTL 0x01F2 +#define mmCP_INT_STATUS 0x01F3 +#define mmCP_INT_ACK 0x01F4 +#define mmCP_PFP_UCODE_ADDR 0x00C0 +#define mmCP_PFP_UCODE_DATA 0x00C1 +#define mmCP_PERFMON_CNTL 0x0444 +#define mmCP_PERFCOUNTER_SELECT 0x0445 +#define mmCP_PERFCOUNTER_LO 0x0446 +#define mmCP_PERFCOUNTER_HI 0x0447 +#define mmCP_BIN_MASK_LO 0x0454 +#define mmCP_BIN_MASK_HI 0x0455 +#define mmCP_BIN_SELECT_LO 0x0456 +#define mmCP_BIN_SELECT_HI 0x0457 +#define mmCP_NV_FLAGS_0 0x01EE +#define mmCP_NV_FLAGS_1 0x01EF +#define mmCP_NV_FLAGS_2 0x01F0 +#define mmCP_NV_FLAGS_3 0x01F1 +#define mmCP_STATE_DEBUG_INDEX 0x01EC +#define mmCP_STATE_DEBUG_DATA 0x01ED +#define mmCP_PROG_COUNTER 0x044B +#define mmCP_STAT 0x047F +#define mmBIOS_0_SCRATCH 0x0004 +#define mmBIOS_1_SCRATCH 0x0005 +#define mmBIOS_2_SCRATCH 0x0006 +#define mmBIOS_3_SCRATCH 0x0007 +#define mmBIOS_4_SCRATCH 0x0008 +#define mmBIOS_5_SCRATCH 0x0009 +#define mmBIOS_6_SCRATCH 0x000A +#define mmBIOS_7_SCRATCH 0x000B +#define mmBIOS_8_SCRATCH 0x0580 +#define mmBIOS_9_SCRATCH 0x0581 +#define mmBIOS_10_SCRATCH 0x0582 +#define mmBIOS_11_SCRATCH 0x0583 +#define mmBIOS_12_SCRATCH 0x0584 +#define mmBIOS_13_SCRATCH 0x0585 +#define mmBIOS_14_SCRATCH 0x0586 +#define mmBIOS_15_SCRATCH 0x0587 +#define mmCOHER_SIZE_PM4 0x0A29 +#define mmCOHER_BASE_PM4 0x0A2A +#define mmCOHER_STATUS_PM4 0x0A2B +#define mmCOHER_SIZE_HOST 0x0A2F +#define mmCOHER_BASE_HOST 0x0A30 +#define mmCOHER_STATUS_HOST 0x0A31 +#define mmCOHER_DEST_BASE_0 0x2006 +#define mmCOHER_DEST_BASE_1 0x2007 +#define mmCOHER_DEST_BASE_2 0x2008 +#define mmCOHER_DEST_BASE_3 0x2009 +#define mmCOHER_DEST_BASE_4 0x200A +#define mmCOHER_DEST_BASE_5 0x200B +#define mmCOHER_DEST_BASE_6 0x200C +#define mmCOHER_DEST_BASE_7 0x200D + + +// Registers from SC block + + + +// Registers from BC block + +#define mmRB_SURFACE_INFO 0x2000 +#define mmRB_COLOR_INFO 0x2001 +#define mmRB_DEPTH_INFO 0x2002 +#define mmRB_STENCILREFMASK 0x210D +#define mmRB_ALPHA_REF 0x210E +#define mmRB_COLOR_MASK 0x2104 +#define mmRB_BLEND_RED 0x2105 +#define mmRB_BLEND_GREEN 0x2106 +#define mmRB_BLEND_BLUE 0x2107 +#define mmRB_BLEND_ALPHA 0x2108 +#define mmRB_FOG_COLOR 0x2109 +#define mmRB_STENCILREFMASK_BF 0x210C +#define mmRB_DEPTHCONTROL 0x2200 +#define mmRB_BLENDCONTROL 0x2201 +#define mmRB_COLORCONTROL 0x2202 +#define mmRB_MODECONTROL 0x2208 +#define mmRB_COLOR_DEST_MASK 0x2326 +#define mmRB_COPY_CONTROL 0x2318 +#define mmRB_COPY_DEST_BASE 0x2319 +#define mmRB_COPY_DEST_PITCH 0x231A +#define mmRB_COPY_DEST_INFO 0x231B +#define mmRB_COPY_DEST_PIXEL_OFFSET 0x231C +#define mmRB_DEPTH_CLEAR 0x231D +#define mmRB_SAMPLE_COUNT_CTL 0x2324 +#define mmRB_SAMPLE_COUNT_ADDR 0x2325 +#define mmRB_BC_CONTROL 0x0F01 +#define mmRB_EDRAM_INFO 0x0F02 +#define mmRB_CRC_RD_PORT 0x0F0C +#define mmRB_CRC_CONTROL 0x0F0D +#define mmRB_CRC_MASK 0x0F0E +#define mmRB_PERFCOUNTER0_SELECT 0x0F04 +#define mmRB_PERFCOUNTER0_LOW 0x0F08 +#define mmRB_PERFCOUNTER0_HI 0x0F09 +#define mmRB_TOTAL_SAMPLES 0x0F0F +#define mmRB_ZPASS_SAMPLES 0x0F10 +#define mmRB_ZFAIL_SAMPLES 0x0F11 +#define mmRB_SFAIL_SAMPLES 0x0F12 +#define mmRB_DEBUG_0 0x0F26 +#define mmRB_DEBUG_1 0x0F27 +#define mmRB_DEBUG_2 0x0F28 +#define mmRB_DEBUG_3 0x0F29 +#define mmRB_DEBUG_4 0x0F2A +#define mmRB_FLAG_CONTROL 0x0F2B +#define mmRB_BC_SPARES 0x0F2C +#define mmBC_DUMMY_CRAYRB_ENUMS 0x0F15 +#define mmBC_DUMMY_CRAYRB_MOREENUMS 0x0F16 +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h new file mode 100644 index 000000000000..17379dcfa0e7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h @@ -0,0 +1,223 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_RANDOM_HEADER) +#define _yamato_RANDOM_HEADER + +/************************************************************* + * THIS FILE IS AUTOMATICALLY CREATED. DO NOT EDIT THIS FILE. + *************************************************************/ +/******************************************************* + * PA Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * VGT Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * RBBM Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * CP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +#endif /*_yamato_RANDOM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h new file mode 100644 index 000000000000..3cd315f903db --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h @@ -0,0 +1,14292 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_REG_HEADER) +#define _yamato_REG_HEADER +/* +* yamato_registers.h +* +* Register Spec Release: Chip Spec 1.0 +* +* +* (c) 2000 ATI Technologies Inc. (unpublished) +* +* All rights reserved. This notice is intended as a precaution against +* inadvertent publication and does not imply publication or any waiver +* of confidentiality. The year included in the foregoing notice is the +* year of creation of the work. +* +*/ + + union PA_CL_VPORT_XSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_XOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VTE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_X_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int : 2; + unsigned int VTX_XY_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int PERFCOUNTER_REF : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_XY_FMT : 1; + unsigned int : 2; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_X_SCALE_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CLIP_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int CLIP_DISABLE : 1; + unsigned int : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int W_NAN_RETAIN : 1; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int W_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int : 1; + unsigned int CLIP_DISABLE : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int CLIP_VTX_REORDER_ENA : 1; + unsigned int : 27; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 27; + unsigned int CLIP_VTX_REORDER_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int : 28; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_VTX_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PIX_CENTER : 1; + unsigned int ROUND_MODE : 2; + unsigned int QUANT_MODE : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int QUANT_MODE : 3; + unsigned int ROUND_MODE : 2; + unsigned int PIX_CENTER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int HEIGHT : 16; + unsigned int WIDTH : 16; +#else /* !defined(qLittleEndian) */ + unsigned int WIDTH : 16; + unsigned int HEIGHT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_MINMAX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_SIZE : 16; + unsigned int MAX_SIZE : 16; +#else /* !defined(qLittleEndian) */ + unsigned int MAX_SIZE : 16; + unsigned int MIN_SIZE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int WIDTH : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int WIDTH : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_FACE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int BASE_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_SC_MODE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int CULL_FRONT : 1; + unsigned int CULL_BACK : 1; + unsigned int FACE : 1; + unsigned int POLY_MODE : 2; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int : 2; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int FACE_WRITE_ENABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACE_WRITE_ENABLE : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int : 2; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLY_MODE : 2; + unsigned int FACE : 1; + unsigned int CULL_BACK : 1; + unsigned int CULL_FRONT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int WINDOW_X_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_X_OFFSET : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MSAA_NUM_SAMPLES : 3; + unsigned int : 10; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 10; + unsigned int MSAA_NUM_SAMPLES : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AA_MASK : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int AA_MASK : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE { + struct { +#if defined(qLittleEndian) + unsigned int LINE_PATTERN : 16; + unsigned int REPEAT_COUNT : 8; + unsigned int : 4; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int : 4; + unsigned int REPEAT_COUNT : 8; + unsigned int LINE_PATTERN : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int BRES_CNTL : 8; + unsigned int USE_BRES_CNTL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int LAST_PIXEL : 1; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int LAST_PIXEL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int USE_BRES_CNTL : 1; + unsigned int BRES_CNTL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 14; + unsigned int : 2; + unsigned int TL_Y : 14; + unsigned int : 1; + unsigned int WINDOW_OFFSET_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int WINDOW_OFFSET_DISABLE : 1; + unsigned int : 1; + unsigned int TL_Y : 14; + unsigned int : 2; + unsigned int TL_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 14; + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; + unsigned int BR_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 15; + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; + unsigned int TL_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 15; + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; + unsigned int BR_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY { + struct { +#if defined(qLittleEndian) + unsigned int VIZ_QUERY_ENA : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int : 1; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int VIZ_QUERY_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int STATUS_BITS : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS_BITS : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE_STATE { + struct { +#if defined(qLittleEndian) + unsigned int CURRENT_PTR : 4; + unsigned int : 4; + unsigned int CURRENT_COUNT : 8; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int CURRENT_COUNT : 8; + unsigned int : 4; + unsigned int CURRENT_PTR : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int CL_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CL_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SU_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SU_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SC_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SU_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SU_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int clip_ga_bc_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ALWAYS_ZERO : 12; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 12; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_ga_bc_fifo_write : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int clip_to_outsm_end_of_packet : 1; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_vert_vte_valid : 3; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int ALWAYS_ZERO : 8; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 8; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int clip_vert_vte_valid : 3; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_end_of_packet : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO1 : 21; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; +#else /* !defined(qLittleEndian) */ + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO1 : 21; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO0 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 6; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO3 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO0 : 24; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 24; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO2 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 4; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int clprim_in_back_event : 1; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int prim_back_valid : 1; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_fifo_full : 1; + unsigned int clip_priority_seq_indx_load : 2; +#else /* !defined(qLittleEndian) */ + unsigned int clip_priority_seq_indx_load : 2; + unsigned int outsm_clr_fifo_full : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int prim_back_valid : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_event : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_event_id : 6; +#else /* !defined(qLittleEndian) */ + unsigned int clprim_in_back_event_id : 6; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int vertval_bits_vertex_vertex_store_msb : 4; + unsigned int ALWAYS_ZERO : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 28; + unsigned int vertval_bits_vertex_vertex_store_msb : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int clip_priority_available_vte_out_clip : 2; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int primic_to_clprim_valid : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int primic_to_clprim_valid : 1; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_priority_available_vte_out_clip : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int sm0_clip_vert_cnt : 4; + unsigned int sm0_prim_end_state : 7; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_current_state : 7; + unsigned int ALWAYS_ZERO0 : 5; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 5; + unsigned int sm0_current_state : 7; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_prim_end_state : 7; + unsigned int sm0_clip_vert_cnt : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int nan_kill_flag : 4; + unsigned int position_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_aux_sel : 1; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_rd_aux_sel : 1; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int position_address : 3; + unsigned int nan_kill_flag : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 2; + unsigned int sx_to_pa_empty : 2; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int sx_pending_advance : 1; + unsigned int sx_receive_indx : 3; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int pasx_req_cnt : 2; + unsigned int param_cache_base : 7; +#else /* !defined(qLittleEndian) */ + unsigned int param_cache_base : 7; + unsigned int pasx_req_cnt : 2; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int sx_receive_indx : 3; + unsigned int sx_pending_advance : 1; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int sx_to_pa_empty : 2; + unsigned int ALWAYS_ZERO3 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int sx_sent : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_aux : 1; + unsigned int sx_request_indx : 6; + unsigned int req_active_verts : 7; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int req_active_verts_loaded : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_contents : 3; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_fifo_contents : 3; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int req_active_verts_loaded : 1; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int req_active_verts : 7; + unsigned int sx_request_indx : 6; + unsigned int sx_aux : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_sent : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vertex_fifo_entriesavailable : 4; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int current_state : 2; + unsigned int vertex_fifo_empty : 1; + unsigned int vertex_fifo_full : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vertex_fifo_full : 1; + unsigned int vertex_fifo_empty : 1; + unsigned int current_state : 2; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int vertex_fifo_entriesavailable : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int su_cntl_state : 5; + unsigned int pmode_state : 6; + unsigned int ge_stallb : 1; + unsigned int geom_enable : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int su_clip_rtr : 1; + unsigned int pfifo_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int geom_busy : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int geom_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int pfifo_busy : 1; + unsigned int su_clip_rtr : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int geom_enable : 1; + unsigned int ge_stallb : 1; + unsigned int pmode_state : 6; + unsigned int su_cntl_state : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort0_gated_17_4 : 14; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int y_sort0_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort1_gated_17_4 : 14; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int y_sort1_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort2_gated_17_4 : 14; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int y_sort2_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort0_gated : 11; + unsigned int null_prim_gated : 1; + unsigned int backfacing_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int clipped_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int xmajor_gated : 1; + unsigned int diamond_rule_gated : 2; + unsigned int type_gated : 3; + unsigned int fpov_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int event_gated : 1; + unsigned int eop_gated : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int eop_gated : 1; + unsigned int event_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int fpov_gated : 1; + unsigned int type_gated : 3; + unsigned int diamond_rule_gated : 2; + unsigned int xmajor_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int clipped_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int backfacing_gated : 1; + unsigned int null_prim_gated : 1; + unsigned int attr_indx_sort0_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort2_gated : 11; + unsigned int attr_indx_sort1_gated : 11; + unsigned int provoking_vtx_gated : 2; + unsigned int event_id_gated : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int event_id_gated : 5; + unsigned int provoking_vtx_gated : 2; + unsigned int attr_indx_sort1_gated : 11; + unsigned int attr_indx_sort2_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SC_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SC_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int pa_freeze_b1 : 1; + unsigned int pa_sc_valid : 1; + unsigned int pa_sc_phase : 3; + unsigned int cntx_cnt : 7; + unsigned int decr_cntx_cnt : 1; + unsigned int incr_cntx_cnt : 1; + unsigned int : 17; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 17; + unsigned int incr_cntx_cnt : 1; + unsigned int decr_cntx_cnt : 1; + unsigned int cntx_cnt : 7; + unsigned int pa_sc_phase : 3; + unsigned int pa_sc_valid : 1; + unsigned int pa_freeze_b1 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int em_state : 3; + unsigned int em1_data_ready : 1; + unsigned int em2_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int ef_data_ready : 1; + unsigned int ef_state : 2; + unsigned int pipe_valid : 1; + unsigned int : 21; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 21; + unsigned int pipe_valid : 1; + unsigned int ef_state : 2; + unsigned int ef_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int em2_data_ready : 1; + unsigned int em1_data_ready : 1; + unsigned int em_state : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int rc_rtr_dly : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int : 1; + unsigned int pipe_freeze_b : 1; + unsigned int prim_rts : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int stage0_rts : 1; + unsigned int phase_rts_dly : 1; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : 1; + unsigned int pass_empty_prim_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int event_s1 : 1; + unsigned int : 8; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 8; + unsigned int event_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int pass_empty_prim_s1 : 1; + unsigned int end_of_prim_s1_dly : 1; + unsigned int : 5; + unsigned int phase_rts_dly : 1; + unsigned int stage0_rts : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int prim_rts : 1; + unsigned int pipe_freeze_b : 1; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int rc_rtr_dly : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int x_curr_s1 : 11; + unsigned int y_curr_s1 : 11; + unsigned int : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 9; + unsigned int y_curr_s1 : 11; + unsigned int x_curr_s1 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int y_end_s1 : 14; + unsigned int y_start_s1 : 14; + unsigned int y_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int y_dir_s1 : 1; + unsigned int y_start_s1 : 14; + unsigned int y_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_5 { + struct { +#if defined(qLittleEndian) + unsigned int x_end_s1 : 14; + unsigned int x_start_s1 : 14; + unsigned int x_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int x_dir_s1 : 1; + unsigned int x_start_s1 : 14; + unsigned int x_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_6 { + struct { +#if defined(qLittleEndian) + unsigned int z_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int xy_ff_empty : 1; + unsigned int event_flag : 1; + unsigned int z_mask_needed : 1; + unsigned int state : 3; + unsigned int state_delayed : 3; + unsigned int data_valid : 1; + unsigned int data_valid_d : 1; + unsigned int tilex_delayed : 9; + unsigned int tiley_delayed : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int tiley_delayed : 9; + unsigned int tilex_delayed : 9; + unsigned int data_valid_d : 1; + unsigned int data_valid : 1; + unsigned int state_delayed : 3; + unsigned int state : 3; + unsigned int z_mask_needed : 1; + unsigned int event_flag : 1; + unsigned int xy_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int z_ff_empty : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_7 { + struct { +#if defined(qLittleEndian) + unsigned int event_flag : 1; + unsigned int deallocate : 3; + unsigned int fposition : 1; + unsigned int sr_prim_we : 1; + unsigned int last_tile : 1; + unsigned int tile_ff_we : 1; + unsigned int qs_data_valid : 1; + unsigned int qs_q0_y : 2; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_valid : 1; + unsigned int prim_ff_we : 1; + unsigned int tile_ff_re : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int last_quad_of_tile : 1; + unsigned int first_quad_of_tile : 1; + unsigned int first_quad_of_prim : 1; + unsigned int new_prim : 1; + unsigned int load_new_tile_data : 1; + unsigned int state : 2; + unsigned int fifos_ready : 1; + unsigned int : 6; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 6; + unsigned int fifos_ready : 1; + unsigned int state : 2; + unsigned int load_new_tile_data : 1; + unsigned int new_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int first_quad_of_tile : 1; + unsigned int last_quad_of_tile : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int tile_ff_re : 1; + unsigned int prim_ff_we : 1; + unsigned int qs_q0_valid : 1; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_y : 2; + unsigned int qs_data_valid : 1; + unsigned int tile_ff_we : 1; + unsigned int last_tile : 1; + unsigned int sr_prim_we : 1; + unsigned int fposition : 1; + unsigned int deallocate : 3; + unsigned int event_flag : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_8 { + struct { +#if defined(qLittleEndian) + unsigned int sample_last : 1; + unsigned int sample_mask : 4; + unsigned int sample_y : 2; + unsigned int sample_x : 2; + unsigned int sample_send : 1; + unsigned int next_cycle : 2; + unsigned int ez_sample_ff_full : 1; + unsigned int rb_sc_samp_rtr : 1; + unsigned int num_samples : 2; + unsigned int last_quad_of_tile : 1; + unsigned int last_quad_of_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int sample_we : 1; + unsigned int fposition : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int : 3; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 3; + unsigned int fw_prim_data_valid : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int fposition : 1; + unsigned int sample_we : 1; + unsigned int first_quad_of_prim : 1; + unsigned int last_quad_of_prim : 1; + unsigned int last_quad_of_tile : 1; + unsigned int num_samples : 2; + unsigned int rb_sc_samp_rtr : 1; + unsigned int ez_sample_ff_full : 1; + unsigned int next_cycle : 2; + unsigned int sample_send : 1; + unsigned int sample_x : 2; + unsigned int sample_y : 2; + unsigned int sample_mask : 4; + unsigned int sample_last : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_9 { + struct { +#if defined(qLittleEndian) + unsigned int rb_sc_send : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int fifo_data_ready : 1; + unsigned int early_z_enable : 1; + unsigned int mask_state : 2; + unsigned int next_ez_mask : 16; + unsigned int mask_ready : 1; + unsigned int drop_sample : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int drop_sample : 1; + unsigned int mask_ready : 1; + unsigned int next_ez_mask : 16; + unsigned int mask_state : 2; + unsigned int early_z_enable : 1; + unsigned int fifo_data_ready : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int rb_sc_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_10 { + struct { +#if defined(qLittleEndian) + unsigned int combined_sample_mask : 16; + unsigned int : 15; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 15; + unsigned int combined_sample_mask : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_11 { + struct { +#if defined(qLittleEndian) + unsigned int ez_sample_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int iterator_input_fz : 1; + unsigned int packer_send_quads : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_event : 1; + unsigned int next_state : 3; + unsigned int state : 3; + unsigned int stall : 1; + unsigned int : 16; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 16; + unsigned int stall : 1; + unsigned int state : 3; + unsigned int next_state : 3; + unsigned int packer_send_event : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_quads : 1; + unsigned int iterator_input_fz : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_sample_data_ready : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_12 { + struct { +#if defined(qLittleEndian) + unsigned int SQ_iterator_free_buff : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_qdhit0 : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int bc_output_xy_reg : 1; + unsigned int iter_phase_out : 2; + unsigned int iter_phase_reg : 2; + unsigned int iterator_SP_valid : 1; + unsigned int eopv_reg : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int iter_dx_end_of_prim : 1; + unsigned int : 7; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int eopv_reg : 1; + unsigned int iterator_SP_valid : 1; + unsigned int iter_phase_reg : 2; + unsigned int iter_phase_out : 2; + unsigned int bc_output_xy_reg : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int iter_qdhit0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int SQ_iterator_free_buff : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GFX_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DRAW_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_TYPE : 6; + unsigned int SOURCE_SELECT : 2; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int : 1; + unsigned int INDEX_SIZE : 1; + unsigned int NOT_EOP : 1; + unsigned int SMALL_INDEX : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int NUM_INDICES : 16; +#else /* !defined(qLittleEndian) */ + unsigned int NUM_INDICES : 16; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int SMALL_INDEX : 1; + unsigned int NOT_EOP : 1; + unsigned int INDEX_SIZE : 1; + unsigned int : 1; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int SOURCE_SELECT : 2; + unsigned int PRIM_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_EVENT_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int EVENT_TYPE : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int EVENT_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int SWAP_MODE : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SWAP_MODE : 2; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BIN_BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int FACENESS_FETCH : 1; + unsigned int FACENESS_RESET : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACENESS_RESET : 1; + unsigned int FACENESS_FETCH : 1; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MIN { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MAX { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_IMMED_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MAX_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MAX_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MAX_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MIN_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MIN_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_INDX_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int INDX_OFFSET : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int INDX_OFFSET : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VERTEX_REUSE_BLOCK_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_REUSE_DEPTH : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int VTX_REUSE_DEPTH : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_OUT_DEALLOC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int DEALLOC_DIST : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DEALLOC_DIST : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MULTI_PRIM_IB_RESET_INDX { + struct { +#if defined(qLittleEndian) + unsigned int RESET_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int RESET_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int MISC : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MISC : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VTX_VECT_EJECT_REG { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_COUNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int PRIM_COUNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_LAST_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VGT_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int VGT_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int VGT_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int te_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int out_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int grp_busy : 1; + unsigned int dma_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int rbiu_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int VGT_RBBM_busy : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int VGT_RBBM_busy : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int vgt_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int rbiu_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int dma_busy : 1; + unsigned int grp_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int out_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int te_grp_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int out_te_data_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int te_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_SQ_send : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int VGT_SQ_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int te_grp_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_te_data_read : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vgt_clk_en : 1; + unsigned int reg_fifos_clk_en : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int reg_fifos_clk_en : 1; + unsigned int vgt_clk_en : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int grp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int grp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG8 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG9 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int grp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int grp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int temp_derived_di_prim_type_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int di_state_sel_q : 1; + unsigned int last_decr_of_packet : 1; + unsigned int bin_valid : 1; + unsigned int read_block : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int last_bit_enable_q : 1; + unsigned int last_bit_end_di_q : 1; + unsigned int selected_data : 8; + unsigned int mask_input_data : 8; + unsigned int gap_q : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int grp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int grp_trigger : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int gap_q : 1; + unsigned int mask_input_data : 8; + unsigned int selected_data : 8; + unsigned int last_bit_end_di_q : 1; + unsigned int last_bit_enable_q : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int read_block : 1; + unsigned int bin_valid : 1; + unsigned int last_decr_of_packet : 1; + unsigned int di_state_sel_q : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_prim_type_t0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int bgrp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int bgrp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int bgrp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int bgrp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int bgrp_cull_fetch_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int rst_last_bit : 1; + unsigned int current_state_q : 1; + unsigned int old_state_q : 1; + unsigned int old_state_en : 1; + unsigned int prev_last_bit_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int load_empty_reg : 1; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int load_empty_reg : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int prev_last_bit_q : 1; + unsigned int old_state_en : 1; + unsigned int old_state_q : 1; + unsigned int current_state_q : 1; + unsigned int rst_last_bit : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int bgrp_cull_fetch_fifo_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int save_read_q : 1; + unsigned int extend_read_q : 1; + unsigned int grp_indx_size : 2; + unsigned int cull_prim_true : 1; + unsigned int reset_bit2_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int first_reg_first_q : 1; + unsigned int check_second_reg : 1; + unsigned int check_first_reg : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int roll_over_msk_q : 1; + unsigned int max_msk_ptr_q : 7; + unsigned int min_msk_ptr_q : 7; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int min_msk_ptr_q : 7; + unsigned int max_msk_ptr_q : 7; + unsigned int roll_over_msk_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int check_first_reg : 1; + unsigned int check_second_reg : 1; + unsigned int first_reg_first_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int reset_bit2_q : 1; + unsigned int cull_prim_true : 1; + unsigned int grp_indx_size : 2; + unsigned int extend_read_q : 1; + unsigned int save_read_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int dma_data_fifo_mem_raddr : 6; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_mem_full : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int bin_mem_full : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_mem_empty : 1; + unsigned int start_bin_req : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int dma_req_xfer : 1; + unsigned int have_valid_bin_req : 1; + unsigned int have_valid_dma_req : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int have_valid_dma_req : 1; + unsigned int have_valid_bin_req : 1; + unsigned int dma_req_xfer : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int start_bin_req : 1; + unsigned int bin_mem_empty : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_mem_full : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_mem_full : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_data_fifo_mem_raddr : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int prim_side_indx_valid : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int prim_buffer_empty : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_full : 1; + unsigned int indx_buffer_empty : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_full : 1; + unsigned int hold_prim : 1; + unsigned int sent_cnt : 4; + unsigned int start_of_vtx_vector : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int out_trigger : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int out_trigger : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int start_of_vtx_vector : 1; + unsigned int sent_cnt : 4; + unsigned int hold_prim : 1; + unsigned int indx_buffer_full : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_empty : 1; + unsigned int prim_buffer_full : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_empty : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int prim_side_indx_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int null_terminate_vtx_vector : 1; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int alloc_counter_q : 3; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_dealloc_distance_q : 4; + unsigned int new_packet_q : 1; + unsigned int new_allocate_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int inserted_null_prim_q : 1; + unsigned int insert_null_prim : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_thread_size : 1; + unsigned int : 4; + unsigned int out_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int out_trigger : 1; + unsigned int : 4; + unsigned int buffered_thread_size : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int insert_null_prim : 1; + unsigned int inserted_null_prim_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int new_allocate_q : 1; + unsigned int new_packet_q : 1; + unsigned int curr_dealloc_distance_q : 4; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int alloc_counter_q : 3; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int null_terminate_vtx_vector : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int L2_INVALIDATE : 1; + unsigned int : 17; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 11; + unsigned int TC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_BUSY : 1; + unsigned int : 11; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 17; + unsigned int L2_INVALIDATE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int SPARE : 23; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 23; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP_TC_CLKGATE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TP_BUSY_EXTEND : 3; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int TP_BUSY_EXTEND : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TPC_INPUT_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int : 1; + unsigned int TF_TW_RTR : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int : 1; + unsigned int TA_TB_RTR : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TPC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TPC_BUSY : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TB_RTR : 1; + unsigned int : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TF_TW_RTR : 1; + unsigned int : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int LOD_CNTL : 2; + unsigned int IC_CTR : 2; + unsigned int WALKER_CNTL : 4; + unsigned int ALIGNER_CNTL : 3; + unsigned int : 1; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 3; + unsigned int WALKER_STATE : 10; + unsigned int ALIGNER_STATE : 2; + unsigned int : 1; + unsigned int REG_CLK_EN : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int SQ_TP_WAKEUP : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SQ_TP_WAKEUP : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int : 1; + unsigned int ALIGNER_STATE : 2; + unsigned int WALKER_STATE : 10; + unsigned int : 3; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 1; + unsigned int ALIGNER_CNTL : 3; + unsigned int WALKER_CNTL : 4; + unsigned int IC_CTR : 2; + unsigned int LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int UNUSED : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int UNUSED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_PRECISION : 1; + unsigned int SPARE : 31; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 31; + unsigned int BLEND_PRECISION : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TP_INPUT_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int : 1; + unsigned int IN_LC_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TP_BUSY : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int IN_LC_RTS : 1; + unsigned int : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int Q_LOD_CNTL : 2; + unsigned int : 1; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int REG_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int TP_CLK_EN : 1; + unsigned int Q_WALKER_CNTL : 4; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int Q_WALKER_CNTL : 4; + unsigned int TP_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int : 1; + unsigned int Q_LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TT_MODE : 1; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int SPARE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 30; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int TT_MODE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 6; + unsigned int not_MH_TC_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_FG0_rtr : 1; + unsigned int : 3; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int TCB_ff_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int PF0_stall : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int TPC_full : 1; + unsigned int not_TPC_rtr : 1; + unsigned int tca_state_rts : 1; + unsigned int tca_rts : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int tca_rts : 1; + unsigned int tca_state_rts : 1; + unsigned int not_TPC_rtr : 1; + unsigned int TPC_full : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int PF0_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCB_ff_stall : 1; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int : 3; + unsigned int not_FG0_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_MH_TC_rtr : 1; + unsigned int : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_FIFO_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tp0_full : 1; + unsigned int : 3; + unsigned int tpc_full : 1; + unsigned int load_tpc_fifo : 1; + unsigned int load_tp_fifos : 1; + unsigned int FW_full : 1; + unsigned int not_FW_rtr0 : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_tpc_rtr : 1; + unsigned int FW_tpc_rts : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int FW_tpc_rts : 1; + unsigned int not_FW_tpc_rtr : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_rtr0 : 1; + unsigned int FW_full : 1; + unsigned int load_tp_fifos : 1; + unsigned int load_tpc_fifo : 1; + unsigned int tpc_full : 1; + unsigned int : 3; + unsigned int tp0_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_PROBE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int ProbeFilter_stall : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int ProbeFilter_stall : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_TPC_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int captue_state_rts : 1; + unsigned int capture_tca_rts : 1; + unsigned int : 18; +#else /* !defined(qLittleEndian) */ + unsigned int : 18; + unsigned int capture_tca_rts : 1; + unsigned int captue_state_rts : 1; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_CORE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int access512 : 1; + unsigned int tiled : 1; + unsigned int : 2; + unsigned int opcode : 3; + unsigned int : 1; + unsigned int format : 6; + unsigned int : 2; + unsigned int sector_format : 5; + unsigned int : 3; + unsigned int sector_format512 : 3; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int sector_format512 : 3; + unsigned int : 3; + unsigned int sector_format : 5; + unsigned int : 2; + unsigned int format : 6; + unsigned int : 1; + unsigned int opcode : 3; + unsigned int : 2; + unsigned int tiled : 1; + unsigned int access512 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG1_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG2_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG3_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int left_done : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int no_sectors_to_go : 1; + unsigned int update_left : 1; + unsigned int sector_mask_left_count_q : 5; + unsigned int sector_mask_left_q : 16; + unsigned int valid_left_q : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int valid_left_q : 1; + unsigned int sector_mask_left_q : 16; + unsigned int sector_mask_left_count_q : 5; + unsigned int update_left : 1; + unsigned int no_sectors_to_go : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int left_done : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_WALKER_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int quad_sel_left : 2; + unsigned int set_sel_left : 2; + unsigned int : 3; + unsigned int right_eq_left : 1; + unsigned int ff_fg_type512 : 3; + unsigned int busy : 1; + unsigned int setquads_to_send : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int setquads_to_send : 4; + unsigned int busy : 1; + unsigned int ff_fg_type512 : 3; + unsigned int right_eq_left : 1; + unsigned int : 3; + unsigned int set_sel_left : 2; + unsigned int quad_sel_left : 2; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_PIPE0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tc0_arb_rts : 1; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc_arb_format : 12; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_request_type : 2; + unsigned int busy : 1; + unsigned int fgo_busy : 1; + unsigned int ga_busy : 1; + unsigned int mc_sel_q : 2; + unsigned int valid_q : 1; + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; + unsigned int valid_q : 1; + unsigned int mc_sel_q : 2; + unsigned int ga_busy : 1; + unsigned int fgo_busy : 1; + unsigned int busy : 1; + unsigned int tc_arb_request_type : 2; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_format : 12; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc0_arb_rts : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_INPUT0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int : 2; + unsigned int valid_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int last_send_q1 : 1; + unsigned int ip_send : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ipbuf_busy : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int ipbuf_busy : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ip_send : 1; + unsigned int last_send_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int valid_q1 : 1; + unsigned int : 2; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DEGAMMA_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int dgmm_ftfconv_dgmmen : 2; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_pstate : 1; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int dgmm_pstate : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ftfconv_dgmmen : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTMUX_SCTARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 9; + unsigned int pstate : 1; + unsigned int sctrmx_rtr : 1; + unsigned int dxtc_rtr : 1; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : 1; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dcmp_mux_send : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int dcmp_mux_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int sctrarb_multcyl_send : 1; + unsigned int : 3; + unsigned int dxtc_rtr : 1; + unsigned int sctrmx_rtr : 1; + unsigned int pstate : 1; + unsigned int : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTC_ARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int n0_stall : 1; + unsigned int pstate : 1; + unsigned int arb_dcmp01_last_send : 1; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_send : 1; + unsigned int n0_dxt2_4_types : 1; +#else /* !defined(qLittleEndian) */ + unsigned int n0_dxt2_4_types : 1; + unsigned int arb_dcmp01_send : 1; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_last_send : 1; + unsigned int pstate : 1; + unsigned int n0_stall : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int : 11; + unsigned int not_incoming_rtr : 1; +#else /* !defined(qLittleEndian) */ + unsigned int not_incoming_rtr : 1; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int rl_sg_sector_format : 8; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int : 2; + unsigned int stageN1_valid_q : 1; + unsigned int : 7; + unsigned int read_cache_q : 1; + unsigned int cache_read_RTR : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int busy : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int busy : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int cache_read_RTR : 1; + unsigned int read_cache_q : 1; + unsigned int : 7; + unsigned int stageN1_valid_q : 1; + unsigned int : 2; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_sector_format : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int fifo_busy : 1; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int write_enable : 1; + unsigned int fifo_write_ptr : 7; + unsigned int fifo_read_ptr : 7; + unsigned int : 2; + unsigned int cache_read_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int cache_read_busy : 1; + unsigned int : 2; + unsigned int fifo_read_ptr : 7; + unsigned int fifo_write_ptr : 7; + unsigned int write_enable : 1; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int fifo_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_GPR_MANAGEMENT { + struct { +#if defined(qLittleEndian) + unsigned int REG_DYNAMIC : 1; + unsigned int : 3; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 1; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 1; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 3; + unsigned int REG_DYNAMIC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FLOW_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int INPUT_ARBITRATION_POLICY : 2; + unsigned int : 2; + unsigned int ONE_THREAD : 1; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int CF_WR_BASE : 4; + unsigned int NO_PV_PS : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_PV_PS : 1; + unsigned int CF_WR_BASE : 4; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int ONE_THREAD : 1; + unsigned int : 2; + unsigned int INPUT_ARBITRATION_POLICY : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INST_STORE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int INST_BASE_PIX : 12; + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; + unsigned int INST_BASE_PIX : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_RESOURCE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int VTX_THREAD_BUF_ENTRIES : 8; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int VTX_THREAD_BUF_ENTRIES : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_EO_RT { + struct { +#if defined(qLittleEndian) + unsigned int EO_CONSTANTS_RT : 8; + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; + unsigned int EO_CONSTANTS_RT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC { + struct { +#if defined(qLittleEndian) + unsigned int DB_ALUCST_SIZE : 11; + unsigned int : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int DB_READ_CTX : 1; + unsigned int RESERVED : 2; + unsigned int DB_READ_MEMORY : 2; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_READ_MEMORY : 2; + unsigned int RESERVED : 2; + unsigned int DB_READ_CTX : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int : 1; + unsigned int DB_ALUCST_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TIMEBASE : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int SPARE : 8; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int TIMEBASE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PERCENT_BUSY : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERCENT_BUSY : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INPUT_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_THREAD_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int RESERVED : 2; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int RESERVED : 2; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_MASK : 1; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int PS_WATCHDOG_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_TIMEOUT : 1; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int PS_WATCHDOG_TIMEOUT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_ACK : 1; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int PS_WATCHDOG_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_INPUT_FSM { + struct { +#if defined(qLittleEndian) + unsigned int VC_VSR_LD : 3; + unsigned int RESERVED : 1; + unsigned int VC_GPR_LD : 4; + unsigned int PC_PISM : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_AS : 3; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_GPR_SIZE : 8; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PC_GPR_SIZE : 8; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_AS : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_PISM : 3; + unsigned int VC_GPR_LD : 4; + unsigned int RESERVED : 1; + unsigned int VC_VSR_LD : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_CONST_MGR_FSM { + struct { +#if defined(qLittleEndian) + unsigned int TEX_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int TEX_CONST_EVENT_STATE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TP_FSM { + struct { +#if defined(qLittleEndian) + unsigned int EX_TP : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_TP : 4; + unsigned int IF_TP : 3; + unsigned int RESERVED1 : 1; + unsigned int TIS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED5 : 2; + unsigned int ARB_TR_TP : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_TP : 3; + unsigned int RESERVED5 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int TIS_TP : 2; + unsigned int RESERVED1 : 1; + unsigned int IF_TP : 3; + unsigned int CF_TP : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_TP : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_EXP_ALLOC { + struct { +#if defined(qLittleEndian) + unsigned int POS_BUF_AVAIL : 4; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int EA_BUF_AVAIL : 3; + unsigned int RESERVED : 1; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int RESERVED : 1; + unsigned int EA_BUF_AVAIL : 3; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int POS_BUF_AVAIL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PTR_BUFF { + struct { +#if defined(qLittleEndian) + unsigned int END_OF_BUFFER : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int SC_EVENT_ID : 5; + unsigned int QUAL_EVENT : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int EF_EMPTY : 1; + unsigned int VTX_SYNC_CNT : 11; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int VTX_SYNC_CNT : 11; + unsigned int EF_EMPTY : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int QUAL_EVENT : 1; + unsigned int SC_EVENT_ID : 5; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int END_OF_BUFFER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_VTX { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int VTX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_PIX { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int PIX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TB_STATUS_SEL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TB_STATUS_REG_SEL : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int : 1; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int DISABLE_STRICT_CTX_SYNC : 1; +#else /* !defined(qLittleEndian) */ + unsigned int DISABLE_STRICT_CTX_SYNC : 1; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATUS_REG_SEL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int VTX_HEAD_PTR_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int SX_EVENT_FULL : 1; + unsigned int BUSY_Q : 1; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int BUSY_Q : 1; + unsigned int SX_EVENT_FULL : 1; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int VTX_HEAD_PTR_Q : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_1 { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_PTR : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int VS_DONE_PTR : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATUS_REG { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATUS_REG : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATUS_REG : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_HEAD_PTR : 6; + unsigned int TAIL_PTR : 6; + unsigned int FULL_CNT : 7; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BUSY : 1; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int FULL_CNT : 7; + unsigned int TAIL_PTR : 6; + unsigned int PIX_HEAD_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_1 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_2 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_3 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int VECTOR_RESULT : 6; + unsigned int VECTOR_DST_REL : 1; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int SCALAR_DST_REL : 1; + unsigned int EXPORT_DATA : 1; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_CLAMP : 1; + unsigned int SCALAR_OPCODE : 6; +#else /* !defined(qLittleEndian) */ + unsigned int SCALAR_OPCODE : 6; + unsigned int SCALAR_CLAMP : 1; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int EXPORT_DATA : 1; + unsigned int SCALAR_DST_REL : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int VECTOR_DST_REL : 1; + unsigned int VECTOR_RESULT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int PRED_SELECT : 2; + unsigned int RELATIVE_ADDR : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int CONST_0_REL_ABS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CONST_0_REL_ABS : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int RELATIVE_ADDR : 1; + unsigned int PRED_SELECT : 2; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_R : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_2 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_REG_PTR : 6; + unsigned int REG_SELECT_C : 1; + unsigned int REG_ABS_MOD_C : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_SELECT_B : 1; + unsigned int REG_ABS_MOD_B : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_SELECT_A : 1; + unsigned int REG_ABS_MOD_A : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int SRC_C_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_A_SEL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_A_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_C_SEL : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int REG_ABS_MOD_A : 1; + unsigned int REG_SELECT_A : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_ABS_MOD_B : 1; + unsigned int REG_SELECT_B : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_ABS_MOD_C : 1; + unsigned int REG_SELECT_C : 1; + unsigned int SRC_C_REG_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_1 { + struct { +#if defined(qLittleEndian) + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; +#else /* !defined(qLittleEndian) */ + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_2 { + struct { +#if defined(qLittleEndian) + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 6; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_1 : 11; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 11; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_0 : 6; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 11; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 6; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED_0 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_2 { + struct { +#if defined(qLittleEndian) + unsigned int LOOP_ID : 5; + unsigned int RESERVED : 22; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED : 22; + unsigned int LOOP_ID : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 3; + unsigned int FORCE_CALL : 1; + unsigned int PREDICATED_JMP : 1; + unsigned int RESERVED_1 : 17; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 17; + unsigned int PREDICATED_JMP : 1; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_0 : 3; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 1; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 3; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_2 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_2 : 2; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_1 : 3; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 17; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED : 17; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_0 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 4; + unsigned int RESERVED : 28; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 28; + unsigned int SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 8; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; + unsigned int SIZE : 4; + unsigned int RESERVED_1 : 12; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 12; + unsigned int SIZE : 4; + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 24; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int CONST_INDEX : 5; + unsigned int TX_COORD_DENORM : 1; + unsigned int SRC_SEL_X : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_Z : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL_Z : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_X : 2; + unsigned int TX_COORD_DENORM : 1; + unsigned int CONST_INDEX : 5; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int MAG_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MIP_FILTER : 2; + unsigned int ANISO_FILTER : 3; + unsigned int ARBITRARY_FILTER : 3; + unsigned int VOL_MAG_FILTER : 2; + unsigned int VOL_MIN_FILTER : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int USE_REG_LOD : 2; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int USE_REG_LOD : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int VOL_MIN_FILTER : 2; + unsigned int VOL_MAG_FILTER : 2; + unsigned int ARBITRARY_FILTER : 3; + unsigned int ANISO_FILTER : 3; + unsigned int MIP_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MAG_FILTER : 2; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int USE_REG_GRADIENTS : 1; + unsigned int SAMPLE_LOCATION : 1; + unsigned int LOD_BIAS : 7; + unsigned int UNUSED : 7; + unsigned int OFFSET_X : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_Z : 5; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int OFFSET_Z : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_X : 5; + unsigned int UNUSED : 7; + unsigned int LOD_BIAS : 7; + unsigned int SAMPLE_LOCATION : 1; + unsigned int USE_REG_GRADIENTS : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int MUST_BE_ONE : 1; + unsigned int CONST_INDEX : 5; + unsigned int CONST_INDEX_SEL : 2; + unsigned int : 3; + unsigned int SRC_SEL : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL : 2; + unsigned int : 3; + unsigned int CONST_INDEX_SEL : 2; + unsigned int CONST_INDEX : 5; + unsigned int MUST_BE_ONE : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int STRIDE : 8; + unsigned int : 8; + unsigned int OFFSET : 8; + unsigned int : 7; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int : 7; + unsigned int OFFSET : 8; + unsigned int : 8; + unsigned int STRIDE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int TYPE : 1; + unsigned int STATE : 1; + unsigned int BASE_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDRESS : 30; + unsigned int STATE : 1; + unsigned int TYPE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int ENDIAN_SWAP : 2; + unsigned int LIMIT_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int LIMIT_ADDRESS : 30; + unsigned int ENDIAN_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_PROGRAM_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int VS_CF_SIZE : 11; + unsigned int : 1; + unsigned int PS_CF_SIZE : 11; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int PS_CF_SIZE : 11; + unsigned int : 1; + unsigned int VS_CF_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INTERPOLATOR_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_SHADE : 16; + unsigned int SAMPLING_PATTERN : 16; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLING_PATTERN : 16; + unsigned int PARAM_SHADE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PROGRAM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VS_NUM_REG : 6; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_RESOURCE : 1; + unsigned int PS_RESOURCE : 1; + unsigned int PARAM_GEN : 1; + unsigned int GEN_INDEX_PIX : 1; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int PS_EXPORT_MODE : 4; + unsigned int GEN_INDEX_VTX : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GEN_INDEX_VTX : 1; + unsigned int PS_EXPORT_MODE : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int GEN_INDEX_PIX : 1; + unsigned int PARAM_GEN : 1; + unsigned int PS_RESOURCE : 1; + unsigned int VS_RESOURCE : 1; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_NUM_REG : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_0 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_0 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_7 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_7 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_0 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_1 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_8 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_15 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_15 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_8 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONTEXT_MISC { + struct { +#if defined(qLittleEndian) + unsigned int INST_PRED_OPTIMIZE : 1; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int : 4; + unsigned int PARAM_GEN_POS : 8; + unsigned int PERFCOUNTER_REF : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int TX_CACHE_SEL : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int TX_CACHE_SEL : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int PARAM_GEN_POS : 8; + unsigned int : 4; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int INST_PRED_OPTIMIZE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RD_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RD_BASE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int RD_BASE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_0 { + struct { +#if defined(qLittleEndian) + unsigned int DB_PROB_ON : 1; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 5; + unsigned int DB_PROB_COUNT : 8; +#else /* !defined(qLittleEndian) */ + unsigned int DB_PROB_COUNT : 8; + unsigned int : 5; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ON : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_1 { + struct { +#if defined(qLittleEndian) + unsigned int DB_ON_PIX : 1; + unsigned int DB_ON_VTX : 1; + unsigned int : 6; + unsigned int DB_INST_COUNT : 8; + unsigned int DB_BREAK_ADDR : 11; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int DB_BREAK_ADDR : 11; + unsigned int DB_INST_COUNT : 8; + unsigned int : 6; + unsigned int DB_ON_VTX : 1; + unsigned int DB_ON_PIX : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_ARBITER_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int SAME_PAGE_LIMIT : 6; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L2_ARB_CONTROL : 1; + unsigned int PAGE_SIZE : 3; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int PAGE_SIZE : 3; + unsigned int L2_ARB_CONTROL : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int SAME_PAGE_LIMIT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_CLNT_AXI_ID_REUSE { + struct { +#if defined(qLittleEndian) + unsigned int CPw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int PAw_ID : 3; + unsigned int : 17; +#else /* !defined(qLittleEndian) */ + unsigned int : 17; + unsigned int PAw_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int CPw_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_READ_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int INDEX : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int INDEX : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_HALT_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int AXI_HALT : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int AXI_HALT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int MH_BUSY : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int CP_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int TC_REQUEST : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TCD_FULL : 1; + unsigned int RB_REQUEST : 1; + unsigned int PA_REQUEST : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int WDB_FULL : 1; + unsigned int AXI_AVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int AXI_RDY_ENA : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_AVALID : 1; + unsigned int WDB_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int PA_REQUEST : 1; + unsigned int RB_REQUEST : 1; + unsigned int TCD_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int CP_REQUEST : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int MH_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_WRITE_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_BLEN_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_written : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_BLEN_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_WRITE_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_CLNT_tag : 3; + unsigned int RDC_RID : 3; + unsigned int RDC_RRESP : 2; + unsigned int MH_CP_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_PA_writeclean : 1; + unsigned int BRC_BID : 3; + unsigned int BRC_BRESP : 2; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BRC_BRESP : 2; + unsigned int BRC_BID : 3; + unsigned int MH_PA_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_CP_writeclean : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RID : 3; + unsigned int MH_CLNT_tag : 3; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_send : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_ad_31_5 : 27; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG06 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG07 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG08 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int PA_MH_be : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int PA_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int CP_MH_be : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 3; + unsigned int VGT_MH_send : 1; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int VGT_MH_ad_31_5 : 27; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_send : 1; + unsigned int ALWAYS_ZERO : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_MH_addr_31_5 : 27; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_send : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_info : 25; + unsigned int TC_MH_send : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_info : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int MH_TC_mcinfo : 25; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int TC_MH_written : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int TC_MH_written : 1; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int MH_TC_mcinfo : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_ADDR_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_ADDR_31_5 : 27; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ROQ_INFO : 25; + unsigned int TC_ROQ_SEND : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_INFO : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int RB_MH_send : 1; + unsigned int RB_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_addr_31_5 : 27; + unsigned int RB_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int PA_MH_send : 1; + unsigned int PA_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_addr_31_5 : 27; + unsigned int PA_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG19 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_2_0 : 3; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_0 : 2; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int RID_q : 3; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int RID_q : 3; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int ARLEN_q_1_0 : 2; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_2_0 : 3; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG22 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_1_0 : 2; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_1 : 1; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int WSTRB_q : 8; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WSTRB_q : 8; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int ARLEN_q_1_1 : 1; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_1_0 : 2; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG23 { + struct { +#if defined(qLittleEndian) + unsigned int ARC_CTRL_RE_q : 1; + unsigned int CTRL_ARC_ID : 3; + unsigned int CTRL_ARC_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int CTRL_ARC_PAD : 28; + unsigned int CTRL_ARC_ID : 3; + unsigned int ARC_CTRL_RE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG24 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int REG_A : 14; + unsigned int REG_RE : 1; + unsigned int REG_WE : 1; + unsigned int BLOCK_RS : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BLOCK_RS : 1; + unsigned int REG_WE : 1; + unsigned int REG_RE : 1; + unsigned int REG_A : 14; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG25 { + struct { +#if defined(qLittleEndian) + unsigned int REG_WD : 32; +#else /* !defined(qLittleEndian) */ + unsigned int REG_WD : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG26 { + struct { +#if defined(qLittleEndian) + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int CNT_q : 6; + unsigned int TCD_EMPTY_q : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int BRC_VALID : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BRC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int RDC_VALID : 1; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TCD_EMPTY_q : 1; + unsigned int CNT_q : 6; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_RBBM_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG27 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_FP_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int ARB_WINNER_q : 3; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int ARB_WINNER_q : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF2_FP_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG28 { + struct { +#if defined(qLittleEndian) + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; +#else /* !defined(qLittleEndian) */ + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG29 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int LEAST_RECENT_d : 3; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CLNT_REQ : 5; + unsigned int RECENT_d_0 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_4 : 3; +#else /* !defined(qLittleEndian) */ + unsigned int RECENT_d_4 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_0 : 3; + unsigned int CLNT_REQ : 5; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int LEAST_RECENT_d : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int EFF2_LRU_WINNER_out : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG30 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ARB_HOLD : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int WBURST_ACTIVE : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WINNER : 3; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int WBURST_IP_q : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_ACTIVE : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ARB_HOLD : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG31 { + struct { +#if defined(qLittleEndian) + unsigned int RF_ARBITER_CONFIG_q : 26; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int RF_ARBITER_CONFIG_q : 26; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG32 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int ROQ_VALID_q : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG33 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int ROQ_VALID_d : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_d : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG34 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int NON_SAME_ROW_BANK_REQ : 8; +#else /* !defined(qLittleEndian) */ + unsigned int NON_SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int SAME_ROW_BANK_WIN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG35 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_ADDR_0 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_0 : 27; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG36 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_ADDR_1 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_1 : 27; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG37 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_ADDR_2 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_2 : 27; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG38 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_ADDR_3 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_3 : 27; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG39 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_ADDR_4 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_4 : 27; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG40 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_ADDR_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_5 : 27; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG41 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_ADDR_6 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_6 : 27; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG42 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_ADDR_7 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_7 : 27; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG43 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_REG_WE_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int MMU_RTR : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_WRITE : 1; + unsigned int MMU_BLEN : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int MMU_BLEN : 1; + unsigned int MMU_WRITE : 1; + unsigned int MMU_ID : 3; + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int MMU_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG44 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_VAD_q : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_VAD_q : 28; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG45 { + struct { +#if defined(qLittleEndian) + unsigned int MMU_WE : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_PAD : 28; + unsigned int MMU_ID : 3; + unsigned int MMU_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG46 { + struct { +#if defined(qLittleEndian) + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int ARB_WLAST : 1; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WSTRB : 8; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WSTRB : 8; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int ARB_WLAST : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG47 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG48 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG49 { + struct { +#if defined(qLittleEndian) + unsigned int CTRL_ARC_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int INFLT_LIMIT_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int INFLT_LIMIT_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int CTRL_ARC_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG50 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RRESP : 2; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int CNT_HOLD_q1 : 1; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int CNT_HOLD_q1 : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG51 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_PAGE_FAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RF_MMU_PAGE_FAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG52 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int client_behavior_q : 2; +#else /* !defined(qLittleEndian) */ + unsigned int client_behavior_q : 2; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG53 { + struct { +#if defined(qLittleEndian) + unsigned int stage1_valid : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int MMU_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int REQ_VA_OFFSET_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA_OFFSET_q : 16; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_MISS : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int stage1_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG54 { + struct { +#if defined(qLittleEndian) + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int stage1_valid : 1; + unsigned int stage2_valid : 1; + unsigned int client_behavior_q : 2; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int TAG_valid_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int TAG_valid_q : 16; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int client_behavior_q : 2; + unsigned int stage2_valid : 1; + unsigned int stage1_valid : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG55 { + struct { +#if defined(qLittleEndian) + unsigned int TAG0_VA : 13; + unsigned int TAG_valid_q_0 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG1_VA : 13; + unsigned int TAG_valid_q_1 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_1 : 1; + unsigned int TAG1_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_0 : 1; + unsigned int TAG0_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG56 { + struct { +#if defined(qLittleEndian) + unsigned int TAG2_VA : 13; + unsigned int TAG_valid_q_2 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG3_VA : 13; + unsigned int TAG_valid_q_3 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_3 : 1; + unsigned int TAG3_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_2 : 1; + unsigned int TAG2_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG57 { + struct { +#if defined(qLittleEndian) + unsigned int TAG4_VA : 13; + unsigned int TAG_valid_q_4 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG5_VA : 13; + unsigned int TAG_valid_q_5 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_5 : 1; + unsigned int TAG5_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_4 : 1; + unsigned int TAG4_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG58 { + struct { +#if defined(qLittleEndian) + unsigned int TAG6_VA : 13; + unsigned int TAG_valid_q_6 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG7_VA : 13; + unsigned int TAG_valid_q_7 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_7 : 1; + unsigned int TAG7_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_6 : 1; + unsigned int TAG6_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG59 { + struct { +#if defined(qLittleEndian) + unsigned int TAG8_VA : 13; + unsigned int TAG_valid_q_8 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG9_VA : 13; + unsigned int TAG_valid_q_9 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_9 : 1; + unsigned int TAG9_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_8 : 1; + unsigned int TAG8_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG60 { + struct { +#if defined(qLittleEndian) + unsigned int TAG10_VA : 13; + unsigned int TAG_valid_q_10 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG11_VA : 13; + unsigned int TAG_valid_q_11 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_11 : 1; + unsigned int TAG11_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_10 : 1; + unsigned int TAG10_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG61 { + struct { +#if defined(qLittleEndian) + unsigned int TAG12_VA : 13; + unsigned int TAG_valid_q_12 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG13_VA : 13; + unsigned int TAG_valid_q_13 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_13 : 1; + unsigned int TAG13_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_12 : 1; + unsigned int TAG12_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG62 { + struct { +#if defined(qLittleEndian) + unsigned int TAG14_VA : 13; + unsigned int TAG_valid_q_14 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG15_VA : 13; + unsigned int TAG_valid_q_15 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_15 : 1; + unsigned int TAG15_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_14 : 1; + unsigned int TAG14_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG63 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MMU_ENABLE : 1; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int RESERVED1 : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int RESERVED1 : 2; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int MMU_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_VA_RANGE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_64KB_REGIONS : 12; + unsigned int VA_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int VA_BASE : 20; + unsigned int NUM_64KB_REGIONS : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PT_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int PT_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int PT_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PAGE_FAULT { + struct { +#if defined(qLittleEndian) + unsigned int PAGE_FAULT : 1; + unsigned int OP_TYPE : 1; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int AXI_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int REQ_VA : 20; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA : 20; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int RESERVED1 : 1; + unsigned int AXI_ID : 3; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int OP_TYPE : 1; + unsigned int PAGE_FAULT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_TRAN_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int TRAN_ERROR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TRAN_ERROR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_INVALIDATE { + struct { +#if defined(qLittleEndian) + unsigned int INVALIDATE_ALL : 1; + unsigned int INVALIDATE_TC : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int INVALIDATE_TC : 1; + unsigned int INVALIDATE_ALL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_END { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_END : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_END : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union WAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_2D_IDLE : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int : 2; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 2; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLE : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_ISYNC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int CMDFIFO_AVAIL : 5; + unsigned int TC_BUSY : 1; + unsigned int : 2; + unsigned int HIRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int MH_BUSY : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int : 1; + unsigned int SX_BUSY : 1; + unsigned int TPC_BUSY : 1; + unsigned int : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int GUI_ACTIVE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GUI_ACTIVE : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int TPC_BUSY : 1; + unsigned int SX_BUSY : 1; + unsigned int : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int MH_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int HIRQ_PENDING : 1; + unsigned int : 2; + unsigned int TC_BUSY : 1; + unsigned int CMDFIFO_AVAIL : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DSPLY { + struct { +#if defined(qLittleEndian) + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int : 2; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_NUM_BUFS : 2; +#else /* !defined(qLittleEndian) */ + unsigned int DMI_CH4_NUM_BUFS : 2; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RENDER_LATEST { + struct { +#if defined(qLittleEndian) + unsigned int DMI_CH1_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH1_BUFFER_ID : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RTL_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int CHANGELIST : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CHANGELIST : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PATCH_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int PATCH_REVISION : 16; + unsigned int PATCH_SELECTION : 8; + unsigned int CUSTOMER_ID : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CUSTOMER_ID : 8; + unsigned int PATCH_SELECTION : 8; + unsigned int PATCH_REVISION : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_AUXILIARY_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID0 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER0 : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PARTNUMBER0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID1 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER1 : 4; + unsigned int DESIGNER0 : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int DESIGNER0 : 4; + unsigned int PARTNUMBER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID2 { + struct { +#if defined(qLittleEndian) + unsigned int DESIGNER1 : 4; + unsigned int REVISION : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int REVISION : 4; + unsigned int DESIGNER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID3 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_HOST_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int MH_INTERFACE : 2; + unsigned int : 1; + unsigned int CONTINUATION : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CONTINUATION : 1; + unsigned int : 1; + unsigned int MH_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int RBBM_HOST_INTERFACE : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int READ_TIMEOUT : 8; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int READ_TIMEOUT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SKEW_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SKEW_TOP_THRESHOLD : 5; + unsigned int SKEW_COUNT : 5; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int SKEW_COUNT : 5; + unsigned int SKEW_TOP_THRESHOLD : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SOFT_RESET { + struct { +#if defined(qLittleEndian) + unsigned int SOFT_RESET_CP : 1; + unsigned int : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_SX : 1; + unsigned int : 5; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 2; + unsigned int SOFT_RESET_SC : 1; + unsigned int SOFT_RESET_VGT : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int SOFT_RESET_VGT : 1; + unsigned int SOFT_RESET_SC : 1; + unsigned int : 2; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 5; + unsigned int SOFT_RESET_SX : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int : 1; + unsigned int SOFT_RESET_CP : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE1 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE2 { + struct { +#if defined(qLittleEndian) + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GC_SYS_IDLE { + struct { +#if defined(qLittleEndian) + unsigned int GC_SYS_IDLE_DELAY : 16; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int : 2; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int : 3; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_IDLE_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GC_SYS_IDLE_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int : 3; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int : 2; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int GC_SYS_IDLE_DELAY : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union NQWAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_GUI_IDLE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int WAIT_GUI_IDLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_OUT { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_BUS_OUT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEBUG_BUS_OUT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int SW_ENABLE : 1; + unsigned int : 3; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int GPIO_BYTE_LANE_ENB : 4; +#else /* !defined(qLittleEndian) */ + unsigned int GPIO_BYTE_LANE_ENB : 4; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 3; + unsigned int SW_ENABLE : 1; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int SUB_BLOCK_ADDR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int IGNORE_RTR : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int : 3; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 4; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int : 6; + unsigned int IGNORE_SX_RBBM_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int IGNORE_SX_RBBM_BUSY : 1; + unsigned int : 6; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int : 4; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 3; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_RTR : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_READ_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int READ_ADDRESS : 15; + unsigned int : 13; + unsigned int READ_REQUESTER : 1; + unsigned int READ_ERROR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int READ_ERROR : 1; + unsigned int READ_REQUESTER : 1; + unsigned int : 13; + unsigned int READ_ADDRESS : 15; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_WAIT_IDLE_CLOCKS { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_MASK : 1; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int RDERR_INT_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_STAT : 1; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int RDERR_INT_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_ACK : 1; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int RDERR_INT_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MASTER_INT_SIGNAL { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int MH_INT_STAT : 1; + unsigned int : 20; + unsigned int SQ_INT_STAT : 1; + unsigned int : 3; + unsigned int CP_INT_STAT : 1; + unsigned int RBBM_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RBBM_INT_STAT : 1; + unsigned int CP_INT_STAT : 1; + unsigned int : 3; + unsigned int SQ_INT_STAT : 1; + unsigned int : 20; + unsigned int MH_INT_STAT : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERF_COUNT1_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT1_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT1_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int RB_BASE : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BASE : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RB_BUFSZ : 6; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_POLL_EN : 1; + unsigned int : 6; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 3; + unsigned int RB_RPTR_WR_ENA : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_WR_ENA : 1; + unsigned int : 3; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 6; + unsigned int RB_POLL_EN : 1; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int RB_BUFSZ : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_SWAP : 2; + unsigned int RB_RPTR_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_ADDR : 30; + unsigned int RB_RPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_WR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_WR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR_WR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_WPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_DELAY { + struct { +#if defined(qLittleEndian) + unsigned int PRE_WRITE_TIMER : 28; + unsigned int PRE_WRITE_LIMIT : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PRE_WRITE_LIMIT : 4; + unsigned int PRE_WRITE_TIMER : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR_SWAP : 2; + unsigned int RB_WPTR_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_WPTR_BASE : 30; + unsigned int RB_WPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB1_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB1_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB1_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB1_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB2_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB2_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB2_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB2_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int ST_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int ST_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int ST_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int ST_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_QUEUE_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_IB1_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_ST_START : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int CSQ_ST_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_IB1_START : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int MEQ_END : 5; + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; + unsigned int MEQ_END : 5; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_CNT_RING : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_RING : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int STQ_CNT_ST : 7; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int STQ_CNT_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_CNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int MEQ_CNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_RB_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_PRIMARY : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB1_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT1 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB2_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT2 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NON_PREFETCH_CNTRS { + struct { +#if defined(qLittleEndian) + unsigned int IB1_COUNTER : 3; + unsigned int : 5; + unsigned int IB2_COUNTER : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int IB2_COUNTER : 3; + unsigned int : 5; + unsigned int IB1_COUNTER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_ST_STAT { + struct { +#if defined(qLittleEndian) + unsigned int STQ_RPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_RPTR_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_RPTR : 10; + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; + unsigned int MEQ_RPTR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MIU_TAG_STAT { + struct { +#if defined(qLittleEndian) + unsigned int TAG_0_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_17_STAT : 1; + unsigned int : 13; + unsigned int INVALID_RETURN_TAG : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INVALID_RETURN_TAG : 1; + unsigned int : 13; + unsigned int TAG_17_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_0_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int CMD_INDEX : 7; + unsigned int : 9; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 9; + unsigned int CMD_INDEX : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CMD_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CMD_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int ME_STATMUX : 16; + unsigned int : 9; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 1; + unsigned int ME_HALT : 1; + unsigned int ME_BUSY : 1; + unsigned int : 1; + unsigned int PROG_CNT_SIZE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PROG_CNT_SIZE : 1; + unsigned int : 1; + unsigned int ME_BUSY : 1; + unsigned int ME_HALT : 1; + unsigned int : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 9; + unsigned int ME_STATMUX : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int ME_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_WADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_WADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_WADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_RADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_RADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_RADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_DATA { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RAM_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RDADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RDADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RDADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; + unsigned int PREDICATE_DISABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int MIU_WRITE_PACK_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MIU_WRITE_PACK_DISABLE : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int PREDICATE_DISABLE : 1; + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG4 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG4 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG5 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG5 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG6 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG6 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG7 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG7 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_UMSK { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_UMSK : 8; + unsigned int : 8; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 8; + unsigned int SCRATCH_UMSK : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int SCRATCH_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWM : 1; + unsigned int VS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_DONE_CNTR : 1; + unsigned int VS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP : 2; + unsigned int VS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR : 30; + unsigned int VS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP_SWM : 2; + unsigned int VS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR_SWM : 30; + unsigned int VS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWM : 1; + unsigned int PS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int PS_DONE_CNTR : 1; + unsigned int PS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP : 2; + unsigned int PS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR : 30; + unsigned int PS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP_SWM : 2; + unsigned int PS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR_SWM : 30; + unsigned int PS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SRC : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CF_DONE_SRC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SWAP : 2; + unsigned int CF_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_ADDR : 30; + unsigned int CF_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_SWAP : 2; + unsigned int NRT_WRITE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_ADDR : 30; + unsigned int NRT_WRITE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_CNTR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int VS_FETCH_DONE_CNTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_SWAP : 2; + unsigned int VS_FETCH_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_ADDR : 30; + unsigned int VS_FETCH_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_MASK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int RB_INT_MASK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int : 3; + unsigned int SW_INT_MASK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_STAT : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int RB_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int : 3; + unsigned int SW_INT_STAT : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_ACK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int RB_INT_ACK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int : 3; + unsigned int SW_INT_ACK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_ADDR : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int UCODE_ADDR : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_DATA : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int UCODE_DATA : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFMON_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PERFMON_STATE : 4; + unsigned int : 4; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 4; + unsigned int PERFMON_STATE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERFCOUNT_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNT_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_0 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_0 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_15 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_15 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_1 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_16 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_31 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_31 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_16 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_2 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_32 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_47 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_47 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_32 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_3 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_48 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_63 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_63 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_48 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_INDEX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int STATE_DEBUG_INDEX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATE_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PROG_COUNTER { + struct { +#if defined(qLittleEndian) + unsigned int COUNTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COUNTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MIU_WR_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int _3D_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int ME_WC_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int CP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CP_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int ME_WC_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int _3D_BUSY : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_WR_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_0_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_1_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_2_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_3_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_4_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_5_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_6_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_7_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_8_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_9_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_10_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_11_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_12_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_13_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_14_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_15_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_HOST { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_0 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_0 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_0 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_1 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_1 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_1 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_2 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_2 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_2 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_3 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_3 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_3 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_4 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_4 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_4 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_5 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_5 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_5 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_6 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_6 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_6 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_7 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_7 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_7 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SURFACE_INFO { + struct { +#if defined(qLittleEndian) + unsigned int SURFACE_PITCH : 14; + unsigned int MSAA_SAMPLES : 2; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MSAA_SAMPLES : 2; + unsigned int SURFACE_PITCH : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_FORMAT : 4; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_SWAP : 2; + unsigned int : 1; + unsigned int COLOR_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_BASE : 20; + unsigned int : 1; + unsigned int COLOR_SWAP : 2; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_FORMAT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_INFO { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_FORMAT : 1; + unsigned int : 11; + unsigned int DEPTH_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_BASE : 20; + unsigned int : 11; + unsigned int DEPTH_FORMAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int RESERVED0 : 1; + unsigned int RESERVED1 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED1 : 1; + unsigned int RESERVED0 : 1; + unsigned int STENCILWRITEMASK : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILREF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ALPHA_REF { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_REF : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_REF : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_MASK { + struct { +#if defined(qLittleEndian) + unsigned int WRITE_RED : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int RESERVED2 : 1; + unsigned int RESERVED3 : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int RESERVED3 : 1; + unsigned int RESERVED2 : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_RED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_RED { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_RED : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_GREEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_GREEN : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_GREEN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_BLUE { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_BLUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_BLUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_ALPHA { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_ALPHA : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_ALPHA : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FOG_COLOR { + struct { +#if defined(qLittleEndian) + unsigned int FOG_RED : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_BLUE : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int FOG_BLUE : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK_BF { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int RESERVED4 : 1; + unsigned int RESERVED5 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED5 : 1; + unsigned int RESERVED4 : 1; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILREF_BF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTHCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int STENCIL_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int STENCILFUNC : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILZFAIL_BF : 3; +#else /* !defined(qLittleEndian) */ + unsigned int STENCILZFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int STENCIL_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLENDCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_SRCBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int BLEND_FORCE : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BLEND_FORCE : 1; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_SRCBLEND : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLORCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_FUNC : 3; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int FOG_ENABLE : 1; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int ROP_CODE : 4; + unsigned int DITHER_MODE : 2; + unsigned int DITHER_TYPE : 2; + unsigned int PIXEL_FOG : 1; + unsigned int : 7; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int : 7; + unsigned int PIXEL_FOG : 1; + unsigned int DITHER_TYPE : 2; + unsigned int DITHER_MODE : 2; + unsigned int ROP_CODE : 4; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int FOG_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_FUNC : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_MODECONTROL { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_MODE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int EDRAM_MODE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_DEST_MASK { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_DEST_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_DEST_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COPY_SAMPLE_SELECT : 3; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int CLEAR_MASK : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CLEAR_MASK : 4; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int COPY_SAMPLE_SELECT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int COPY_DEST_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COPY_DEST_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PITCH { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_PITCH : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int COPY_DEST_PITCH : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_ENDIAN : 3; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_ENDIAN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PIXEL_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET_X : 13; + unsigned int OFFSET_Y : 13; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int OFFSET_Y : 13; + unsigned int OFFSET_X : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_CLEAR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_CLEAR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_CTL { + struct { +#if defined(qLittleEndian) + unsigned int RESET_SAMPLE_COUNT : 1; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int RESET_SAMPLE_COUNT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int SAMPLE_COUNT_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLE_COUNT_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int CRC_MODE : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int DISABLE_ACCUM : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int RESERVED6 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED6 : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int DISABLE_ACCUM : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int CRC_MODE : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_EDRAM_INFO { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_SIZE : 4; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int : 8; + unsigned int EDRAM_RANGE : 18; +#else /* !defined(qLittleEndian) */ + unsigned int EDRAM_RANGE : 18; + unsigned int : 8; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int EDRAM_SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_RD_PORT { + struct { +#if defined(qLittleEndian) + unsigned int CRC_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int CRC_RD_ADVANCE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CRC_RD_ADVANCE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_MASK { + struct { +#if defined(qLittleEndian) + unsigned int CRC_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_TOTAL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int TOTAL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int TOTAL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZPASS_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZPASS_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZPASS_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int SFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int EZ_INFSAMP_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_Z1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int EZ_INFSAMP_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_Z1_CMD_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int TILE_FIFO_COUNT : 4; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z_TILE_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int Z_TILE_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int TILE_FIFO_COUNT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_VALID : 4; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int SHD_FULL : 1; + unsigned int SHD_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int SHD_EMPTY : 1; + unsigned int SHD_FULL : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_VALID : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int GMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int : 19; +#else /* !defined(qLittleEndian) */ + unsigned int : 19; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int GMEM_RD_ACCESS_FLAG : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FLAG_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_FLAG_CLEAR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int DEBUG_FLAG_CLEAR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_SPARES { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_ENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_MOREENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h new file mode 100644 index 000000000000..10807b43ea44 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h @@ -0,0 +1,4183 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_SHIFT_HEADER) +#define _yamato_SHIFT_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT 0x00000016 +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT 0x00000017 +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT 0x00000018 + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT 0x00000005 + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT 0x0000000f +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT 0x00000012 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT 0x00000017 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT 0x00000019 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT 0x0000001d +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT 0x0000001e +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT 0x0000001f + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT 0x00000000 +#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT 0x00000008 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT 0x00000000 +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT 0x00000001 +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT 0x00000007 + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT 0x0000001f + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000014 + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000018 + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT 0x00000008 + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT 0x0000001c + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT 0x00000004 + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT 0x00000016 + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT 0x0000001b + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x0000000a +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT 0x0000000d +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001f + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT 0x0000000b +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT 0x00000019 + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT 0x00000001 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000003 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT 0x00000016 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT 0x0000001b +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x00000005 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT 0x00000008 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x0000000e +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT 0x00000016 + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000005 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000b +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000c +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT 0x0000000d +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x0000000e +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x0000000f +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000010 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000011 + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000c +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x0000000d +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000010 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000011 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000014 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000015 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x00000017 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001a +#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT 0x0000001b +#define SETUP_DEBUG_REG4__event_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001d + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x00000016 +#define SETUP_DEBUG_REG5__event_id_gated__SHIFT 0x00000018 + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1__SHIFT 0x00000000 +#define SC_DEBUG_0__pa_sc_valid__SHIFT 0x00000001 +#define SC_DEBUG_0__pa_sc_phase__SHIFT 0x00000002 +#define SC_DEBUG_0__cntx_cnt__SHIFT 0x00000005 +#define SC_DEBUG_0__decr_cntx_cnt__SHIFT 0x0000000c +#define SC_DEBUG_0__incr_cntx_cnt__SHIFT 0x0000000d +#define SC_DEBUG_0__trigger__SHIFT 0x0000001f + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state__SHIFT 0x00000000 +#define SC_DEBUG_1__em1_data_ready__SHIFT 0x00000003 +#define SC_DEBUG_1__em2_data_ready__SHIFT 0x00000004 +#define SC_DEBUG_1__move_em1_to_em2__SHIFT 0x00000005 +#define SC_DEBUG_1__ef_data_ready__SHIFT 0x00000006 +#define SC_DEBUG_1__ef_state__SHIFT 0x00000007 +#define SC_DEBUG_1__pipe_valid__SHIFT 0x00000009 +#define SC_DEBUG_1__trigger__SHIFT 0x0000001f + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly__SHIFT 0x00000000 +#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT 0x00000001 +#define SC_DEBUG_2__pipe_freeze_b__SHIFT 0x00000003 +#define SC_DEBUG_2__prim_rts__SHIFT 0x00000004 +#define SC_DEBUG_2__next_prim_rts_dly__SHIFT 0x00000005 +#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT 0x00000006 +#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT 0x00000007 +#define SC_DEBUG_2__stage0_rts__SHIFT 0x00000008 +#define SC_DEBUG_2__phase_rts_dly__SHIFT 0x00000009 +#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT 0x0000000f +#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT 0x00000010 +#define SC_DEBUG_2__event_id_s1__SHIFT 0x00000011 +#define SC_DEBUG_2__event_s1__SHIFT 0x00000016 +#define SC_DEBUG_2__trigger__SHIFT 0x0000001f + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1__SHIFT 0x00000000 +#define SC_DEBUG_3__y_curr_s1__SHIFT 0x0000000b +#define SC_DEBUG_3__trigger__SHIFT 0x0000001f + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_4__y_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_4__y_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_4__trigger__SHIFT 0x0000001f + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_5__x_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_5__x_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_5__trigger__SHIFT 0x0000001f + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty__SHIFT 0x00000000 +#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT 0x00000001 +#define SC_DEBUG_6__xy_ff_empty__SHIFT 0x00000002 +#define SC_DEBUG_6__event_flag__SHIFT 0x00000003 +#define SC_DEBUG_6__z_mask_needed__SHIFT 0x00000004 +#define SC_DEBUG_6__state__SHIFT 0x00000005 +#define SC_DEBUG_6__state_delayed__SHIFT 0x00000008 +#define SC_DEBUG_6__data_valid__SHIFT 0x0000000b +#define SC_DEBUG_6__data_valid_d__SHIFT 0x0000000c +#define SC_DEBUG_6__tilex_delayed__SHIFT 0x0000000d +#define SC_DEBUG_6__tiley_delayed__SHIFT 0x00000016 +#define SC_DEBUG_6__trigger__SHIFT 0x0000001f + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag__SHIFT 0x00000000 +#define SC_DEBUG_7__deallocate__SHIFT 0x00000001 +#define SC_DEBUG_7__fposition__SHIFT 0x00000004 +#define SC_DEBUG_7__sr_prim_we__SHIFT 0x00000005 +#define SC_DEBUG_7__last_tile__SHIFT 0x00000006 +#define SC_DEBUG_7__tile_ff_we__SHIFT 0x00000007 +#define SC_DEBUG_7__qs_data_valid__SHIFT 0x00000008 +#define SC_DEBUG_7__qs_q0_y__SHIFT 0x00000009 +#define SC_DEBUG_7__qs_q0_x__SHIFT 0x0000000b +#define SC_DEBUG_7__qs_q0_valid__SHIFT 0x0000000d +#define SC_DEBUG_7__prim_ff_we__SHIFT 0x0000000e +#define SC_DEBUG_7__tile_ff_re__SHIFT 0x0000000f +#define SC_DEBUG_7__fw_prim_data_valid__SHIFT 0x00000010 +#define SC_DEBUG_7__last_quad_of_tile__SHIFT 0x00000011 +#define SC_DEBUG_7__first_quad_of_tile__SHIFT 0x00000012 +#define SC_DEBUG_7__first_quad_of_prim__SHIFT 0x00000013 +#define SC_DEBUG_7__new_prim__SHIFT 0x00000014 +#define SC_DEBUG_7__load_new_tile_data__SHIFT 0x00000015 +#define SC_DEBUG_7__state__SHIFT 0x00000016 +#define SC_DEBUG_7__fifos_ready__SHIFT 0x00000018 +#define SC_DEBUG_7__trigger__SHIFT 0x0000001f + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last__SHIFT 0x00000000 +#define SC_DEBUG_8__sample_mask__SHIFT 0x00000001 +#define SC_DEBUG_8__sample_y__SHIFT 0x00000005 +#define SC_DEBUG_8__sample_x__SHIFT 0x00000007 +#define SC_DEBUG_8__sample_send__SHIFT 0x00000009 +#define SC_DEBUG_8__next_cycle__SHIFT 0x0000000a +#define SC_DEBUG_8__ez_sample_ff_full__SHIFT 0x0000000c +#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT 0x0000000d +#define SC_DEBUG_8__num_samples__SHIFT 0x0000000e +#define SC_DEBUG_8__last_quad_of_tile__SHIFT 0x00000010 +#define SC_DEBUG_8__last_quad_of_prim__SHIFT 0x00000011 +#define SC_DEBUG_8__first_quad_of_prim__SHIFT 0x00000012 +#define SC_DEBUG_8__sample_we__SHIFT 0x00000013 +#define SC_DEBUG_8__fposition__SHIFT 0x00000014 +#define SC_DEBUG_8__event_id__SHIFT 0x00000015 +#define SC_DEBUG_8__event_flag__SHIFT 0x0000001a +#define SC_DEBUG_8__fw_prim_data_valid__SHIFT 0x0000001b +#define SC_DEBUG_8__trigger__SHIFT 0x0000001f + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send__SHIFT 0x00000000 +#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT 0x00000001 +#define SC_DEBUG_9__fifo_data_ready__SHIFT 0x00000005 +#define SC_DEBUG_9__early_z_enable__SHIFT 0x00000006 +#define SC_DEBUG_9__mask_state__SHIFT 0x00000007 +#define SC_DEBUG_9__next_ez_mask__SHIFT 0x00000009 +#define SC_DEBUG_9__mask_ready__SHIFT 0x00000019 +#define SC_DEBUG_9__drop_sample__SHIFT 0x0000001a +#define SC_DEBUG_9__fetch_new_sample_data__SHIFT 0x0000001b +#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT 0x0000001c +#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT 0x0000001d +#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT 0x0000001e +#define SC_DEBUG_9__trigger__SHIFT 0x0000001f + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask__SHIFT 0x00000000 +#define SC_DEBUG_10__trigger__SHIFT 0x0000001f + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready__SHIFT 0x00000000 +#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT 0x00000001 +#define SC_DEBUG_11__ez_prim_data_ready__SHIFT 0x00000002 +#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT 0x00000003 +#define SC_DEBUG_11__iterator_input_fz__SHIFT 0x00000004 +#define SC_DEBUG_11__packer_send_quads__SHIFT 0x00000005 +#define SC_DEBUG_11__packer_send_cmd__SHIFT 0x00000006 +#define SC_DEBUG_11__packer_send_event__SHIFT 0x00000007 +#define SC_DEBUG_11__next_state__SHIFT 0x00000008 +#define SC_DEBUG_11__state__SHIFT 0x0000000b +#define SC_DEBUG_11__stall__SHIFT 0x0000000e +#define SC_DEBUG_11__trigger__SHIFT 0x0000001f + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT 0x00000000 +#define SC_DEBUG_12__event_id__SHIFT 0x00000001 +#define SC_DEBUG_12__event_flag__SHIFT 0x00000006 +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT 0x00000007 +#define SC_DEBUG_12__itercmdfifo_full__SHIFT 0x00000008 +#define SC_DEBUG_12__itercmdfifo_empty__SHIFT 0x00000009 +#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT 0x0000000a +#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT 0x0000000b +#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT 0x0000000c +#define SC_DEBUG_12__iter_qdhit0__SHIFT 0x0000000d +#define SC_DEBUG_12__bc_use_centers_reg__SHIFT 0x0000000e +#define SC_DEBUG_12__bc_output_xy_reg__SHIFT 0x0000000f +#define SC_DEBUG_12__iter_phase_out__SHIFT 0x00000010 +#define SC_DEBUG_12__iter_phase_reg__SHIFT 0x00000012 +#define SC_DEBUG_12__iterator_SP_valid__SHIFT 0x00000014 +#define SC_DEBUG_12__eopv_reg__SHIFT 0x00000015 +#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT 0x00000016 +#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT 0x00000017 +#define SC_DEBUG_12__trigger__SHIFT 0x0000001f + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000006 +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT 0x00000008 +#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT 0x0000000b +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x0000000c +#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT 0x0000000d +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT 0x0000000e +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT 0x0000000f +#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT 0x00000010 + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_DMA_SIZE__SWAP_MODE__SHIFT 0x0000001e + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT 0x00000000 + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT 0x0000001e +#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT 0x0000001f + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT 0x00000006 + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT 0x00000006 + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x00000000 + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 +#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT 0x00000001 +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT 0x00000002 +#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT 0x00000003 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000004 +#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT 0x00000005 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000006 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000007 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000008 + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT 0x00000001 +#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT 0x00000002 +#define VGT_DEBUG_REG0__dma_request_busy__SHIFT 0x00000003 +#define VGT_DEBUG_REG0__out_busy__SHIFT 0x00000004 +#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT 0x00000005 +#define VGT_DEBUG_REG0__grp_busy__SHIFT 0x00000006 +#define VGT_DEBUG_REG0__dma_busy__SHIFT 0x00000007 +#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT 0x00000008 +#define VGT_DEBUG_REG0__rbiu_busy__SHIFT 0x00000009 +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT 0x0000000a +#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT 0x0000000b +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0000000c +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x0000000d +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT 0x0000000e +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT 0x0000000f +#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT 0x00000010 + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read__SHIFT 0x00000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000001 +#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000003 +#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT 0x00000004 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000005 +#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT 0x00000006 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000007 +#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000a +#define VGT_DEBUG_REG1__grp_te_valid__SHIFT 0x0000000b +#define VGT_DEBUG_REG1__pt_grp_read__SHIFT 0x0000000c +#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__vr_grp_read__SHIFT 0x0000000e +#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT 0x0000000f +#define VGT_DEBUG_REG1__grp_dma_read__SHIFT 0x00000010 +#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT 0x00000011 +#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT 0x00000012 +#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT 0x00000013 +#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT 0x00000015 +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT 0x00000016 +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT 0x00000017 +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT 0x00000019 +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT 0x0000001b +#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT 0x0000001d +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT 0x0000001e + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT 0x00000000 +#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT 0x00000001 + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG6__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG6__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG6__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG6__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG6__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG6__grp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG7__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG8__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG8__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG8__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG9__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG9__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG9__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG9__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG9__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG9__grp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000 +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001 +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002 +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003 +#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT 0x00000005 +#define VGT_DEBUG_REG10__bin_valid__SHIFT 0x00000006 +#define VGT_DEBUG_REG10__read_block__SHIFT 0x00000007 +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG10__selected_data__SHIFT 0x0000000b +#define VGT_DEBUG_REG10__mask_input_data__SHIFT 0x00000013 +#define VGT_DEBUG_REG10__gap_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT 0x0000001c +#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT 0x0000001d +#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT 0x0000001e +#define VGT_DEBUG_REG10__grp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG12__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG12__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG12__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG12__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG12__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG13__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG14__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG14__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG14__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG15__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG15__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG15__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG15__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG15__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT 0x00000000 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT 0x00000008 +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG16__rst_last_bit__SHIFT 0x0000000a +#define VGT_DEBUG_REG16__current_state_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG16__old_state_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG16__old_state_en__SHIFT 0x0000000d +#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG16__load_empty_reg__SHIFT 0x00000012 +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT 0x00000013 +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG17__extend_read_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG17__grp_indx_size__SHIFT 0x00000002 +#define VGT_DEBUG_REG17__cull_prim_true__SHIFT 0x00000004 +#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG17__check_second_reg__SHIFT 0x00000008 +#define VGT_DEBUG_REG17__check_first_reg__SHIFT 0x00000009 +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT 0x00000006 +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d +#define VGT_DEBUG_REG18__dma_mem_full__SHIFT 0x0000000f +#define VGT_DEBUG_REG18__dma_ram_re__SHIFT 0x00000010 +#define VGT_DEBUG_REG18__dma_ram_we__SHIFT 0x00000011 +#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT 0x00000013 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT 0x00000014 +#define VGT_DEBUG_REG18__bin_mem_full__SHIFT 0x00000015 +#define VGT_DEBUG_REG18__bin_ram_we__SHIFT 0x00000016 +#define VGT_DEBUG_REG18__bin_ram_re__SHIFT 0x00000017 +#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT 0x00000018 +#define VGT_DEBUG_REG18__start_bin_req__SHIFT 0x00000019 +#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT 0x0000001a +#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT 0x0000001b +#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT 0x0000001c +#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT 0x0000001d +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT 0x00000000 +#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT 0x00000002 +#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT 0x00000006 +#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT 0x00000008 +#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT 0x0000000a +#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT 0x0000000b +#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT 0x0000000c +#define VGT_DEBUG_REG20__hold_prim__SHIFT 0x0000000d +#define VGT_DEBUG_REG20__sent_cnt__SHIFT 0x0000000e +#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT 0x00000012 +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT 0x00000013 +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT 0x00000014 +#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT 0x00000015 +#define VGT_DEBUG_REG20__out_trigger__SHIFT 0x0000001a + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT 0x00000000 +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001 +#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG21__new_packet_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG21__new_allocate_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT 0x00000014 +#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG21__insert_null_prim__SHIFT 0x00000017 +#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT 0x00000018 +#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT 0x00000019 +#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT 0x0000001a +#define VGT_DEBUG_REG21__out_trigger__SHIFT 0x0000001f + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC__SHIFT 0x00000000 + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT 0x00000000 +#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT 0x00000012 +#define TC_CNTL_STATUS__TC_BUSY__SHIFT 0x0000001f + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000 +#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT 0x00000008 +#define TCM_CHICKEN__SPARE__SHIFT 0x00000009 + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT 0x00000000 +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT 0x00000003 + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT 0x00000000 +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT 0x00000001 +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT 0x00000002 +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT 0x00000003 +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT 0x00000004 +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT 0x00000005 +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT 0x00000006 +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT 0x00000008 +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT 0x00000009 +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT 0x0000000a +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT 0x0000000c +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT 0x0000000d +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT 0x0000000e +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT 0x0000000f +#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT 0x00000010 +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT 0x00000011 +#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT 0x00000013 +#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT 0x00000014 +#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT 0x00000015 +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT 0x00000016 +#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT 0x00000017 +#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT 0x00000018 +#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT 0x00000019 +#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT 0x0000001b +#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT 0x0000001c +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT 0x0000001d +#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT 0x0000001e +#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT 0x0000001f + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL__SHIFT 0x00000000 +#define TPC_DEBUG0__IC_CTR__SHIFT 0x00000002 +#define TPC_DEBUG0__WALKER_CNTL__SHIFT 0x00000004 +#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT 0x00000008 +#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT 0x0000000c +#define TPC_DEBUG0__WALKER_STATE__SHIFT 0x00000010 +#define TPC_DEBUG0__ALIGNER_STATE__SHIFT 0x0000001a +#define TPC_DEBUG0__REG_CLK_EN__SHIFT 0x0000001d +#define TPC_DEBUG0__TPC_CLK_EN__SHIFT 0x0000001e +#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT 0x0000001f + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED__SHIFT 0x00000000 + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION__SHIFT 0x00000000 +#define TPC_CHICKEN__SPARE__SHIFT 0x00000001 + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT 0x00000000 +#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT 0x00000001 +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT 0x00000002 +#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT 0x00000003 +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT 0x00000004 +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT 0x00000005 +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT 0x00000006 +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT 0x00000007 +#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT 0x00000008 +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT 0x00000009 +#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT 0x0000000a +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT 0x0000000b +#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT 0x0000000c +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT 0x0000000d +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT 0x0000000e +#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT 0x00000010 +#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT 0x00000011 +#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT 0x00000012 +#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT 0x00000013 +#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT 0x00000014 +#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT 0x00000015 +#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT 0x00000016 +#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT 0x00000017 +#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT 0x00000018 +#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT 0x00000019 +#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT 0x0000001a +#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT 0x0000001b +#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT 0x0000001c +#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT 0x0000001d +#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT 0x0000001e +#define TP0_CNTL_STATUS__TP_BUSY__SHIFT 0x0000001f + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL__SHIFT 0x00000000 +#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT 0x00000003 +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT 0x00000004 +#define TP0_DEBUG__REG_CLK_EN__SHIFT 0x00000015 +#define TP0_DEBUG__PERF_CLK_EN__SHIFT 0x00000016 +#define TP0_DEBUG__TP_CLK_EN__SHIFT 0x00000017 +#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT 0x00000018 +#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT 0x0000001c + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE__SHIFT 0x00000000 +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT 0x00000001 +#define TP0_CHICKEN__SPARE__SHIFT 0x00000002 + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr__SHIFT 0x00000006 +#define TCF_DEBUG__TC_MH_send__SHIFT 0x00000007 +#define TCF_DEBUG__not_FG0_rtr__SHIFT 0x00000008 +#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT 0x0000000c +#define TCF_DEBUG__TCB_ff_stall__SHIFT 0x0000000d +#define TCF_DEBUG__TCB_miss_stall__SHIFT 0x0000000e +#define TCF_DEBUG__TCA_TCB_stall__SHIFT 0x0000000f +#define TCF_DEBUG__PF0_stall__SHIFT 0x00000010 +#define TCF_DEBUG__TP0_full__SHIFT 0x00000014 +#define TCF_DEBUG__TPC_full__SHIFT 0x00000018 +#define TCF_DEBUG__not_TPC_rtr__SHIFT 0x00000019 +#define TCF_DEBUG__tca_state_rts__SHIFT 0x0000001a +#define TCF_DEBUG__tca_rts__SHIFT 0x0000001b + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full__SHIFT 0x00000000 +#define TCA_FIFO_DEBUG__tpc_full__SHIFT 0x00000004 +#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT 0x00000005 +#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT 0x00000006 +#define TCA_FIFO_DEBUG__FW_full__SHIFT 0x00000007 +#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT 0x00000008 +#define TCA_FIFO_DEBUG__FW_rts0__SHIFT 0x0000000c +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT 0x00000010 +#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT 0x00000011 + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT 0x00000000 + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts__SHIFT 0x0000000c +#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT 0x0000000d + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512__SHIFT 0x00000000 +#define TCB_CORE_DEBUG__tiled__SHIFT 0x00000001 +#define TCB_CORE_DEBUG__opcode__SHIFT 0x00000004 +#define TCB_CORE_DEBUG__format__SHIFT 0x00000008 +#define TCB_CORE_DEBUG__sector_format__SHIFT 0x00000010 +#define TCB_CORE_DEBUG__sector_format512__SHIFT 0x00000018 + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG0_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG0_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG1_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG1_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG2_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG2_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG3_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG3_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT 0x00000004 +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT 0x0000000b +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT 0x0000000c +#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT 0x0000000f +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010 + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT 0x00000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT 0x00000002 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015 +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT 0x00000017 +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT 0x00000018 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT 0x00000019 +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT 0x0000001a +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT 0x0000001c +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT 0x0000001e + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty__SHIFT 0x00000010 +#define TCD_INPUT0_DEBUG__full__SHIFT 0x00000011 +#define TCD_INPUT0_DEBUG__valid_q1__SHIFT 0x00000014 +#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT 0x00000015 +#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT 0x00000017 +#define TCD_INPUT0_DEBUG__ip_send__SHIFT 0x00000018 +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT 0x00000019 +#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT 0x0000001a + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT 0x00000000 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT 0x00000002 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT 0x00000003 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT 0x00000004 +#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT 0x00000005 +#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT 0x00000006 + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT 0x00000009 +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT 0x0000000a +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT 0x0000000b +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT 0x00000014 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT 0x0000001c +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT 0x0000001d + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT 0x00000004 +#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT 0x00000005 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT 0x00000006 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT 0x00000007 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT 0x00000009 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT 0x0000000c +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT 0x00000012 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT 0x0000001e +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT 0x0000001f + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT 0x0000000a +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT 0x0000000b +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT 0x00000011 +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT 0x00000012 +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT 0x00000013 +#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT 0x0000001f + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT 0x00000005 +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT 0x00000006 +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT 0x00000007 + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT 0x00000008 +#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT 0x00000009 +#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT 0x0000000a +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT 0x0000000c +#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT 0x0000000d +#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT 0x00000010 +#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG0__busy__SHIFT 0x0000001e + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG1__empty__SHIFT 0x00000001 +#define TCO_QUAD0_DEBUG1__full__SHIFT 0x00000002 +#define TCO_QUAD0_DEBUG1__write_enable__SHIFT 0x00000003 +#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT 0x00000004 +#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT 0x00000014 +#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT 0x00000015 +#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT 0x00000016 +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT 0x00000017 +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT 0x0000001e + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT 0x00000000 +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT 0x00000004 +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT 0x0000000c + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT 0x00000000 +#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT 0x00000004 +#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT 0x00000008 +#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT 0x0000000c +#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT 0x00000010 +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT 0x00000011 +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT 0x00000012 +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013 +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT 0x00000015 +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT 0x00000016 +#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT 0x00000017 +#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT 0x00000018 +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT 0x00000019 +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT 0x0000001b + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT 0x00000000 +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT 0x00000010 + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000 +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008 +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT 0x00000010 + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT 0x00000000 +#define SQ_EO_RT__EO_TSTATE_RT__SHIFT 0x00000010 + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT 0x00000000 +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT 0x0000000c +#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT 0x00000014 +#define SQ_DEBUG_MISC__RESERVED__SHIFT 0x00000015 +#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT 0x00000017 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT 0x00000019 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT 0x0000001a +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT 0x0000001b +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT 0x0000001c + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT 0x00000000 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT 0x00000008 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT 0x00000010 +#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT 0x00000018 + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT 0x00000000 + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 +#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT 0x00000012 +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014 +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015 +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016 + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT 0x00000000 +#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT 0x00000001 + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT 0x00000000 +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT 0x00000001 + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT 0x00000000 +#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT 0x00000001 + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT 0x00000000 +#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT 0x00000003 +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT 0x00000004 +#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT 0x00000008 +#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT 0x0000000c +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT 0x0000000f +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT 0x00000014 + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT 0x00000005 +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT 0x0000000d +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010 +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017 + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT 0x00000000 +#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT 0x00000004 +#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT 0x00000008 +#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT 0x0000000c +#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT 0x0000000e +#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT 0x00000010 +#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT 0x00000012 +#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT 0x00000014 +#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT 0x00000016 +#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT 0x00000018 +#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT 0x0000001a +#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT 0x00000000 +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT 0x00000004 +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT 0x0000000c +#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT 0x0000000f +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT 0x00000010 + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT 0x00000000 +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT 0x00000001 +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT 0x00000005 +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT 0x00000006 +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT 0x00000009 +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT 0x0000000e +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT 0x0000000f +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT 0x00000010 +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT 0x00000011 + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017 +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT 0x0000001d +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT 0x00000000 +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT 0x00000004 +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT 0x00000008 +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT 0x00000010 +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT 0x00000014 +#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT 0x00000015 + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT 0x00000006 +#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT 0x00000013 +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT 0x00000019 +#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT 0x0000001f + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT 0x0000001a + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT 0x00000002 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT 0x00000004 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT 0x0000000a +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT 0x0000000c +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT 0x00000012 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT 0x0000001a +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT 0x0000001b +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT 0x0000001f + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT 0x00000017 +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT 0x00000013 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT 0x00000014 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT 0x00000015 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT 0x00000016 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT 0x00000017 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT 0x0000001e +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT 0x00000003 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT 0x00000006 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT 0x00000007 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT 0x00000015 + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT 0x0000001a + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT 0x0000000f + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT 0x0000001e + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT 0x00000004 + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT 0x00000014 + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT 0x00000013 +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT 0x00000019 +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT 0x0000001e + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT 0x0000000e +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT 0x00000018 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT 0x0000001d +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT 0x00000013 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT 0x00000019 +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT 0x0000001e + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT 0x00000017 +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT 0x00000001 +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE__SHIFT 0x00000000 + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE__SHIFT 0x00000000 + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_VS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_PS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT 0x00000000 +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT 0x0000000c + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT 0x00000000 +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT 0x00000010 + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT 0x00000000 +#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT 0x00000008 +#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT 0x00000010 +#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT 0x00000011 +#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT 0x00000012 +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT 0x00000013 +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT 0x00000014 +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT 0x00000018 +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT 0x0000001b +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT 0x0000001f + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT 0x00000000 +#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT 0x00000004 +#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT 0x00000008 +#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT 0x0000000c +#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT 0x00000010 +#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT 0x00000014 +#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT 0x00000018 +#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT 0x0000001c + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT 0x00000000 +#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT 0x00000004 +#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT 0x00000008 +#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT 0x0000000c +#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT 0x00000010 +#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT 0x00000014 +#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT 0x00000018 +#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT 0x0000001c + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE__SHIFT 0x00000000 +#define SQ_VS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE__SHIFT 0x00000000 +#define SQ_PS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT 0x00000000 +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT 0x00000001 +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT 0x00000002 +#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT 0x00000008 +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT 0x00000010 +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT 0x00000011 +#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT 0x00000012 + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE__SHIFT 0x00000000 + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT 0x00000004 +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT 0x00000018 + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT 0x00000001 +#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT 0x00000010 + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT 0x00000000 +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 +#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT 0x00000000 +#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT 0x00000003 +#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT 0x00000004 +#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT 0x00000007 +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT 0x00000008 +#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT 0x0000000b +#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT 0x0000000c + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID__SHIFT 0x00000000 +#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT 0x00000003 +#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT 0x00000004 +#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT 0x00000007 + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX__SHIFT 0x00000000 + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT 0x00000000 + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY__SHIFT 0x00000000 +#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT 0x00000001 +#define MH_DEBUG_REG00__CP_REQUEST__SHIFT 0x00000002 +#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT 0x00000003 +#define MH_DEBUG_REG00__TC_REQUEST__SHIFT 0x00000004 +#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT 0x00000005 +#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT 0x00000006 +#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG00__TCD_FULL__SHIFT 0x00000008 +#define MH_DEBUG_REG00__RB_REQUEST__SHIFT 0x00000009 +#define MH_DEBUG_REG00__PA_REQUEST__SHIFT 0x0000000a +#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT 0x0000000b +#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG00__ARQ_FULL__SHIFT 0x0000000d +#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT 0x0000000e +#define MH_DEBUG_REG00__WDB_FULL__SHIFT 0x0000000f +#define MH_DEBUG_REG00__AXI_AVALID__SHIFT 0x00000010 +#define MH_DEBUG_REG00__AXI_AREADY__SHIFT 0x00000011 +#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT 0x00000012 +#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT 0x00000013 +#define MH_DEBUG_REG00__AXI_WVALID__SHIFT 0x00000014 +#define MH_DEBUG_REG00__AXI_WREADY__SHIFT 0x00000015 +#define MH_DEBUG_REG00__AXI_RVALID__SHIFT 0x00000016 +#define MH_DEBUG_REG00__AXI_RREADY__SHIFT 0x00000017 +#define MH_DEBUG_REG00__AXI_BVALID__SHIFT 0x00000018 +#define MH_DEBUG_REG00__AXI_BREADY__SHIFT 0x00000019 +#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT 0x0000001b +#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT 0x0000001c + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q__SHIFT 0x00000000 +#define MH_DEBUG_REG01__CP_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG01__CP_TAG_q__SHIFT 0x00000003 +#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT 0x00000006 +#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT 0x00000007 +#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT 0x00000008 +#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG01__TC_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG01__TC_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT 0x0000000c +#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT 0x0000000d +#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT 0x0000000e +#define MH_DEBUG_REG01__TC_MH_written__SHIFT 0x0000000f +#define MH_DEBUG_REG01__RB_SEND_q__SHIFT 0x00000010 +#define MH_DEBUG_REG01__RB_RTR_q__SHIFT 0x00000011 +#define MH_DEBUG_REG01__PA_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG01__PA_RTR_q__SHIFT 0x00000013 + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT 0x00000003 +#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT 0x00000004 +#define MH_DEBUG_REG02__RDC_RID__SHIFT 0x00000007 +#define MH_DEBUG_REG02__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT 0x0000000c +#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT 0x0000000d +#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT 0x0000000e +#define MH_DEBUG_REG02__BRC_BID__SHIFT 0x0000000f +#define MH_DEBUG_REG02__BRC_BRESP__SHIFT 0x00000012 + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG05__CP_MH_write__SHIFT 0x00000001 +#define MH_DEBUG_REG05__CP_MH_tag__SHIFT 0x00000002 +#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be__SHIFT 0x00000000 +#define MH_DEBUG_REG08__RB_MH_be__SHIFT 0x00000008 +#define MH_DEBUG_REG08__PA_MH_be__SHIFT 0x00000010 + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG09__VGT_MH_send__SHIFT 0x00000003 +#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT 0x00000004 +#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG10__TC_MH_send__SHIFT 0x00000002 +#define MH_DEBUG_REG10__TC_MH_mask__SHIFT 0x00000003 +#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info__SHIFT 0x00000000 +#define MH_DEBUG_REG11__TC_MH_send__SHIFT 0x00000019 + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT 0x00000000 +#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT 0x00000019 +#define MH_DEBUG_REG12__TC_MH_written__SHIFT 0x0000001a + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT 0x00000002 +#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT 0x00000003 +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT 0x00000000 +#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT 0x00000019 + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG15__RB_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG18__PA_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG21__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG21__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT 0x00000005 +#define MH_DEBUG_REG21__ARVALID_q__SHIFT 0x00000008 +#define MH_DEBUG_REG21__ARREADY_q__SHIFT 0x00000009 +#define MH_DEBUG_REG21__ARID_q__SHIFT 0x0000000a +#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT 0x0000000d +#define MH_DEBUG_REG21__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG21__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG21__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG21__RID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG21__WVALID_q__SHIFT 0x00000015 +#define MH_DEBUG_REG21__WREADY_q__SHIFT 0x00000016 +#define MH_DEBUG_REG21__WLAST_q__SHIFT 0x00000017 +#define MH_DEBUG_REG21__WID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG21__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG21__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG21__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG22__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG22__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT 0x00000005 +#define MH_DEBUG_REG22__ARVALID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG22__ARREADY_q__SHIFT 0x00000008 +#define MH_DEBUG_REG22__ARID_q__SHIFT 0x00000009 +#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT 0x0000000c +#define MH_DEBUG_REG22__WVALID_q__SHIFT 0x0000000d +#define MH_DEBUG_REG22__WREADY_q__SHIFT 0x0000000e +#define MH_DEBUG_REG22__WLAST_q__SHIFT 0x0000000f +#define MH_DEBUG_REG22__WID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG22__WSTRB_q__SHIFT 0x00000013 +#define MH_DEBUG_REG22__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG22__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG22__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG24__REG_A__SHIFT 0x00000002 +#define MH_DEBUG_REG24__REG_RE__SHIFT 0x00000010 +#define MH_DEBUG_REG24__REG_WE__SHIFT 0x00000011 +#define MH_DEBUG_REG24__BLOCK_RS__SHIFT 0x00000012 + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD__SHIFT 0x00000000 + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT 0x00000000 +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT 0x00000001 +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT 0x00000002 +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT 0x00000003 +#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT 0x00000004 +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT 0x00000005 +#define MH_DEBUG_REG26__CNT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT 0x0000000c +#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT 0x0000000e +#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT 0x0000000f +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010 +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011 +#define MH_DEBUG_REG26__CP_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG26__CP_RTR_q__SHIFT 0x00000013 +#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT 0x00000014 +#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT 0x00000017 +#define MH_DEBUG_REG26__RB_SEND_q__SHIFT 0x00000018 +#define MH_DEBUG_REG26__RB_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG26__PA_SEND_q__SHIFT 0x0000001a +#define MH_DEBUG_REG26__PA_RTR_q__SHIFT 0x0000001b +#define MH_DEBUG_REG26__RDC_VALID__SHIFT 0x0000001c +#define MH_DEBUG_REG26__RDC_RLAST__SHIFT 0x0000001d +#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT 0x0000001e +#define MH_DEBUG_REG26__BRC_VALID__SHIFT 0x0000001f + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT 0x00000003 +#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT 0x00000006 +#define MH_DEBUG_REG27__ARB_WINNER__SHIFT 0x00000009 +#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT 0x0000000c +#define MH_DEBUG_REG27__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG27__KILL_EFF1__SHIFT 0x00000010 +#define MH_DEBUG_REG27__ARB_HOLD__SHIFT 0x00000011 +#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT 0x00000013 +#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT 0x00000014 +#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT 0x00000015 +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT 0x00000016 +#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT 0x00000017 +#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT 0x00000018 +#define MH_DEBUG_REG27__ARB_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT 0x0000001b +#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT 0x0000001c +#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT 0x0000001d +#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT 0x0000001e +#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT 0x0000001f + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG28__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT 0x00000006 +#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT 0x00000007 +#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT 0x00000008 +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT 0x00000009 +#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT 0x0000000a +#define MH_DEBUG_REG28__ARB_QUAL__SHIFT 0x0000000b +#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT 0x0000000d +#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT 0x0000000e +#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT 0x0000000f +#define MH_DEBUG_REG28__EFF1_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG28__KILL_EFF1__SHIFT 0x00000011 +#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT 0x00000012 +#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT 0x00000013 +#define MH_DEBUG_REG28__ARB_HOLD__SHIFT 0x00000014 +#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT 0x00000016 + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT 0x00000000 +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT 0x00000003 +#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT 0x00000006 +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT 0x00000009 +#define MH_DEBUG_REG29__ARB_HOLD__SHIFT 0x0000000a +#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG29__CLNT_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG29__RECENT_d_0__SHIFT 0x00000011 +#define MH_DEBUG_REG29__RECENT_d_1__SHIFT 0x00000014 +#define MH_DEBUG_REG29__RECENT_d_2__SHIFT 0x00000017 +#define MH_DEBUG_REG29__RECENT_d_3__SHIFT 0x0000001a +#define MH_DEBUG_REG29__RECENT_d_4__SHIFT 0x0000001d + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT 0x00000000 +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT 0x00000001 +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT 0x00000002 +#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT 0x00000003 +#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT 0x00000004 +#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT 0x00000005 +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008 +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG30__TC_MH_written__SHIFT 0x0000000b +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT 0x00000013 +#define MH_DEBUG_REG30__WLAST_q__SHIFT 0x00000014 +#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT 0x00000015 +#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG30__CP_MH_write__SHIFT 0x0000001a +#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT 0x0000001b +#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT 0x0000001c +#define MH_DEBUG_REG30__ARB_WINNER__SHIFT 0x0000001d + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT 0x00000008 +#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG32__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG32__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT 0x00000008 +#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT 0x00000010 +#define MH_DEBUG_REG33__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG33__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT 0x00000000 +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT 0x00000008 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT 0x00000018 + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT 0x00000002 +#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT 0x00000003 +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT 0x00000004 +#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT 0x00000005 + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT 0x00000002 +#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT 0x00000003 +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT 0x00000004 +#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT 0x00000005 + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT 0x00000002 +#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT 0x00000003 +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT 0x00000004 +#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT 0x00000005 + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT 0x00000002 +#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT 0x00000003 +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT 0x00000004 +#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT 0x00000005 + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT 0x00000002 +#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT 0x00000003 +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT 0x00000004 +#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT 0x00000005 + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT 0x00000002 +#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT 0x00000003 +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT 0x00000004 +#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT 0x00000005 + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT 0x00000002 +#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT 0x00000003 +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT 0x00000004 +#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT 0x00000005 + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT 0x00000002 +#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT 0x00000003 +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT 0x00000004 +#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT 0x00000005 + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG43__ARB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT 0x00000003 +#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT 0x00000004 +#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT 0x00000005 +#define MH_DEBUG_REG43__MMU_RTR__SHIFT 0x00000006 +#define MH_DEBUG_REG43__ARB_ID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT 0x0000000a +#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT 0x0000000b +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT 0x0000000d +#define MH_DEBUG_REG43__MMU_WE__SHIFT 0x00000010 +#define MH_DEBUG_REG43__ARQ_RTR__SHIFT 0x00000011 +#define MH_DEBUG_REG43__MMU_ID__SHIFT 0x00000012 +#define MH_DEBUG_REG43__MMU_WRITE__SHIFT 0x00000015 +#define MH_DEBUG_REG43__MMU_BLEN__SHIFT 0x00000016 +#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT 0x00000017 +#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT 0x00000018 +#define MH_DEBUG_REG43__WDB_WE__SHIFT 0x00000019 +#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT 0x0000001a +#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT 0x0000001b + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG44__ARB_ID_q__SHIFT 0x00000001 +#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT 0x00000004 + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG45__MMU_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG45__MMU_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG46__WDB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT 0x00000003 +#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT 0x00000004 +#define MH_DEBUG_REG46__ARB_WLAST__SHIFT 0x0000000c +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT 0x0000000e +#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT 0x00000013 +#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT 0x00000014 +#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT 0x00000017 +#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT 0x00000018 + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT 0x00000000 +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT 0x00000001 +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT 0x00000002 +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT 0x00000003 +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT 0x00000004 +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT 0x00000007 +#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT 0x0000000e +#define MH_DEBUG_REG49__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG49__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG49__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG49__BVALID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG49__BREADY_q__SHIFT 0x00000013 + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT 0x00000003 +#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT 0x00000004 +#define MH_DEBUG_REG50__RDC_VALID__SHIFT 0x00000005 +#define MH_DEBUG_REG50__RDC_RID__SHIFT 0x00000006 +#define MH_DEBUG_REG50__RDC_RLAST__SHIFT 0x00000009 +#define MH_DEBUG_REG50__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT 0x0000000c +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT 0x0000000e +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT 0x0000000f +#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT 0x00000015 +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT 0x0000001c +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT 0x00000000 +#define MH_DEBUG_REG52__ARB_WE__SHIFT 0x00000002 +#define MH_DEBUG_REG52__MMU_RTR__SHIFT 0x00000003 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT 0x00000004 +#define MH_DEBUG_REG52__ARB_ID_q__SHIFT 0x0000001a +#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT 0x0000001d +#define MH_DEBUG_REG52__client_behavior_q__SHIFT 0x0000001e + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid__SHIFT 0x00000000 +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT 0x00000001 +#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT 0x00000002 +#define MH_DEBUG_REG53__tag_match_q__SHIFT 0x00000003 +#define MH_DEBUG_REG53__tag_miss_q__SHIFT 0x00000004 +#define MH_DEBUG_REG53__va_in_range_q__SHIFT 0x00000005 +#define MH_DEBUG_REG53__MMU_MISS__SHIFT 0x00000006 +#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT 0x00000007 +#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT 0x00000008 +#define MH_DEBUG_REG53__MMU_HIT__SHIFT 0x00000009 +#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT 0x0000000a +#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT 0x0000000b +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT 0x0000000c +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT 0x0000000d +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT 0x0000000e +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT 0x0000000f +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT 0x00000010 + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR__SHIFT 0x00000000 +#define MH_DEBUG_REG54__MMU_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT 0x00000003 +#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT 0x00000004 +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005 +#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT 0x00000006 +#define MH_DEBUG_REG54__stage1_valid__SHIFT 0x00000007 +#define MH_DEBUG_REG54__stage2_valid__SHIFT 0x00000008 +#define MH_DEBUG_REG54__client_behavior_q__SHIFT 0x00000009 +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT 0x0000000b +#define MH_DEBUG_REG54__tag_match_q__SHIFT 0x0000000c +#define MH_DEBUG_REG54__tag_miss_q__SHIFT 0x0000000d +#define MH_DEBUG_REG54__va_in_range_q__SHIFT 0x0000000e +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT 0x0000000f +#define MH_DEBUG_REG54__TAG_valid_q__SHIFT 0x00000010 + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT 0x0000000d +#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG55__TAG1_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT 0x0000001d + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT 0x0000000d +#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG56__TAG3_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT 0x0000001d + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT 0x0000000d +#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG57__TAG5_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT 0x0000001d + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT 0x0000000d +#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG58__TAG7_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT 0x0000001d + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT 0x0000000d +#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG59__TAG9_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT 0x0000001d + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT 0x0000000d +#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG60__TAG11_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT 0x0000001d + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT 0x0000000d +#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG61__TAG13_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT 0x0000001d + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT 0x0000000d +#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG62__TAG15_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT 0x0000001d + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT 0x00000000 +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT 0x00000001 +#define MH_MMU_CONFIG__RESERVED1__SHIFT 0x00000002 +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004 +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006 +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008 +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010 +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012 +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014 +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016 +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT 0x00000018 + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT 0x00000000 +#define MH_MMU_VA_RANGE__VA_BASE__SHIFT 0x0000000c + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE__SHIFT 0x0000000c + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT 0x00000000 +#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT 0x00000001 +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT 0x00000002 +#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT 0x00000004 +#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT 0x00000007 +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008 +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT 0x00000009 +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT 0x0000000a +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT 0x0000000b +#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT 0x0000000c + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT 0x00000005 + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT 0x00000000 +#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT 0x00000001 + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT 0x0000000c + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END__SHIFT 0x0000000c + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT 0x00000001 +#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT 0x00000002 +#define WAIT_UNTIL__WAIT_VSYNC__SHIFT 0x00000003 +#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT 0x00000004 +#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT 0x00000005 +#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT 0x00000006 +#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT 0x0000000a +#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT 0x0000000e +#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT 0x0000000f +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT 0x00000010 +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT 0x00000011 +#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT 0x00000014 + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT 0x00000004 +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT 0x00000005 + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0x00000000 +#define RBBM_STATUS__TC_BUSY__SHIFT 0x00000005 +#define RBBM_STATUS__HIRQ_PENDING__SHIFT 0x00000008 +#define RBBM_STATUS__CPRQ_PENDING__SHIFT 0x00000009 +#define RBBM_STATUS__CFRQ_PENDING__SHIFT 0x0000000a +#define RBBM_STATUS__PFRQ_PENDING__SHIFT 0x0000000b +#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT 0x0000000c +#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT 0x0000000e +#define RBBM_STATUS__CP_NRT_BUSY__SHIFT 0x00000010 +#define RBBM_STATUS__MH_BUSY__SHIFT 0x00000012 +#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT 0x00000013 +#define RBBM_STATUS__SX_BUSY__SHIFT 0x00000015 +#define RBBM_STATUS__TPC_BUSY__SHIFT 0x00000016 +#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT 0x00000018 +#define RBBM_STATUS__PA_BUSY__SHIFT 0x00000019 +#define RBBM_STATUS__VGT_BUSY__SHIFT 0x0000001a +#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT 0x0000001b +#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT 0x0000001c +#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT 0x0000001e +#define RBBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT 0x00000000 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT 0x00000001 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT 0x00000002 +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT 0x00000003 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT 0x00000004 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT 0x00000005 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT 0x00000006 +#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT 0x00000007 +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT 0x00000008 +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT 0x0000000a +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT 0x0000000b +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT 0x0000000c +#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT 0x0000000d +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT 0x0000000e +#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT 0x00000010 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT 0x00000014 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT 0x00000015 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT 0x00000016 +#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT 0x00000017 +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT 0x00000018 +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT 0x0000001a +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT 0x0000001b +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT 0x0000001c +#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT 0x0000001d +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT 0x0000001e + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT 0x00000000 +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT 0x00000008 +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT 0x00000010 +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT 0x00000018 + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT 0x00000000 + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT 0x00000000 +#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT 0x00000010 +#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT 0x00000018 + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT 0x00000000 + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT 0x00000000 + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT 0x00000000 +#define RBBM_PERIPHID1__DESIGNER0__SHIFT 0x00000004 + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1__SHIFT 0x00000000 +#define RBBM_PERIPHID2__REVISION__SHIFT 0x00000004 + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT 0x00000000 +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT 0x00000002 +#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT 0x00000004 +#define RBBM_PERIPHID3__CONTINUATION__SHIFT 0x00000007 + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT 0x00000008 + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 +#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000005 + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 +#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT 0x00000002 +#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT 0x00000003 +#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT 0x00000004 +#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT 0x00000005 +#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT 0x00000006 +#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT 0x0000000c +#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT 0x0000000f +#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT 0x00000010 + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010 +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011 +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012 +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013 +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT 0x00000014 +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000015 +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT 0x00000016 +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000017 +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018 +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT 0x00000019 +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001a +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT 0x0000001b +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT 0x0000001c +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001d +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT 0x0000001e +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT 0x0000000b + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT 0x00000000 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT 0x00000010 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT 0x00000018 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT 0x00000019 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT 0x0000001d +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT 0x0000001e +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT 0x0000001f + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT 0x00000000 + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT 0x00000000 + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT 0x00000000 +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT 0x00000008 +#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT 0x0000000c +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT 0x00000010 +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT 0x00000018 +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT 0x0000001c + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR__SHIFT 0x00000001 +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT 0x00000002 +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT 0x00000003 +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT 0x00000004 +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT 0x00000008 +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT 0x00000010 +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000011 +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000012 +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000013 +#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT 0x00000014 +#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT 0x00000015 +#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT 0x00000016 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT 0x00000017 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT 0x00000018 +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT 0x0000001f + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT 0x0000001e +#define RBBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000 + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT 0x00000001 +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT 0x00000013 + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT 0x00000001 +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT 0x00000013 + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT 0x00000001 +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT 0x00000013 + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT 0x00000005 +#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT 0x0000001a +#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT 0x0000001e +#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT 0x0000001f + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x00000005 + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT 0x00000002 + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE__SHIFT 0x00000002 + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE__SHIFT 0x00000002 + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE__SHIFT 0x00000002 + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT 0x00000008 +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT 0x00000010 + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT 0x00000010 +#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT 0x00000018 + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT 0x00000000 +#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT 0x00000008 +#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT 0x00000010 + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT 0x00000000 + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT 0x00000010 + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT 0x00000010 + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT 0x00000010 + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT 0x00000000 +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT 0x00000008 + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT 0x00000000 +#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT 0x00000010 + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT 0x00000000 +#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT 0x00000001 +#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT 0x00000002 +#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT 0x00000003 +#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT 0x00000004 +#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT 0x00000005 +#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT 0x00000006 +#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT 0x00000007 +#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT 0x00000008 +#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT 0x00000009 +#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT 0x0000000a +#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT 0x0000000b +#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT 0x0000000c +#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT 0x0000000d +#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT 0x0000000e +#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT 0x0000000f +#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT 0x00000010 +#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT 0x00000011 +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT 0x0000001f + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX__SHIFT 0x00000000 +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT 0x00000019 +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT 0x0000001a +#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c +#define CP_ME_CNTL__ME_BUSY__SHIFT 0x0000001d +#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT 0x0000001f + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT 0x00000000 + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR__SHIFT 0x00000000 + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT 0x00000000 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x00000017 +#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT 0x00000018 +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT 0x00000019 +#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT 0x0000001a +#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT 0x0000001b +#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT 0x0000001c +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT 0x0000001e +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT 0x0000001f + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT 0x00000000 +#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT 0x00000010 + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT 0x00000005 + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT 0x00000000 +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT 0x00000002 + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000 + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK__SHIFT 0x00000013 +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT 0x00000017 +#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT 0x00000018 +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT 0x00000019 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT 0x0000001a +#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT 0x0000001b +#define CP_INT_CNTL__IB2_INT_MASK__SHIFT 0x0000001d +#define CP_INT_CNTL__IB1_INT_MASK__SHIFT 0x0000001e +#define CP_INT_CNTL__RB_INT_MASK__SHIFT 0x0000001f + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT 0x00000019 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS__IB2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS__IB1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS__RB_INT_STAT__SHIFT 0x0000001f + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK__SHIFT 0x00000013 +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT 0x00000017 +#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT 0x00000018 +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT 0x00000019 +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT 0x0000001a +#define CP_INT_ACK__IB_ERROR_ACK__SHIFT 0x0000001b +#define CP_INT_ACK__IB2_INT_ACK__SHIFT 0x0000001d +#define CP_INT_ACK__IB1_INT_ACK__SHIFT 0x0000001e +#define CP_INT_ACK__RB_INT_ACK__SHIFT 0x0000001f + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT 0x00000000 + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT 0x00000000 + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT 0x00000000 + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT 0x00000000 + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT 0x00000000 + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT 0x00000000 + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT 0x00000000 + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0__SHIFT 0x00000000 +#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT 0x00000001 +#define CP_NV_FLAGS_0__DISCARD_1__SHIFT 0x00000002 +#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT 0x00000003 +#define CP_NV_FLAGS_0__DISCARD_2__SHIFT 0x00000004 +#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT 0x00000005 +#define CP_NV_FLAGS_0__DISCARD_3__SHIFT 0x00000006 +#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT 0x00000007 +#define CP_NV_FLAGS_0__DISCARD_4__SHIFT 0x00000008 +#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT 0x00000009 +#define CP_NV_FLAGS_0__DISCARD_5__SHIFT 0x0000000a +#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT 0x0000000b +#define CP_NV_FLAGS_0__DISCARD_6__SHIFT 0x0000000c +#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT 0x0000000d +#define CP_NV_FLAGS_0__DISCARD_7__SHIFT 0x0000000e +#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT 0x0000000f +#define CP_NV_FLAGS_0__DISCARD_8__SHIFT 0x00000010 +#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT 0x00000011 +#define CP_NV_FLAGS_0__DISCARD_9__SHIFT 0x00000012 +#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT 0x00000013 +#define CP_NV_FLAGS_0__DISCARD_10__SHIFT 0x00000014 +#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT 0x00000015 +#define CP_NV_FLAGS_0__DISCARD_11__SHIFT 0x00000016 +#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT 0x00000017 +#define CP_NV_FLAGS_0__DISCARD_12__SHIFT 0x00000018 +#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT 0x00000019 +#define CP_NV_FLAGS_0__DISCARD_13__SHIFT 0x0000001a +#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT 0x0000001b +#define CP_NV_FLAGS_0__DISCARD_14__SHIFT 0x0000001c +#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT 0x0000001d +#define CP_NV_FLAGS_0__DISCARD_15__SHIFT 0x0000001e +#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT 0x0000001f + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16__SHIFT 0x00000000 +#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT 0x00000001 +#define CP_NV_FLAGS_1__DISCARD_17__SHIFT 0x00000002 +#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT 0x00000003 +#define CP_NV_FLAGS_1__DISCARD_18__SHIFT 0x00000004 +#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT 0x00000005 +#define CP_NV_FLAGS_1__DISCARD_19__SHIFT 0x00000006 +#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT 0x00000007 +#define CP_NV_FLAGS_1__DISCARD_20__SHIFT 0x00000008 +#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT 0x00000009 +#define CP_NV_FLAGS_1__DISCARD_21__SHIFT 0x0000000a +#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT 0x0000000b +#define CP_NV_FLAGS_1__DISCARD_22__SHIFT 0x0000000c +#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT 0x0000000d +#define CP_NV_FLAGS_1__DISCARD_23__SHIFT 0x0000000e +#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT 0x0000000f +#define CP_NV_FLAGS_1__DISCARD_24__SHIFT 0x00000010 +#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT 0x00000011 +#define CP_NV_FLAGS_1__DISCARD_25__SHIFT 0x00000012 +#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT 0x00000013 +#define CP_NV_FLAGS_1__DISCARD_26__SHIFT 0x00000014 +#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT 0x00000015 +#define CP_NV_FLAGS_1__DISCARD_27__SHIFT 0x00000016 +#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT 0x00000017 +#define CP_NV_FLAGS_1__DISCARD_28__SHIFT 0x00000018 +#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT 0x00000019 +#define CP_NV_FLAGS_1__DISCARD_29__SHIFT 0x0000001a +#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT 0x0000001b +#define CP_NV_FLAGS_1__DISCARD_30__SHIFT 0x0000001c +#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT 0x0000001d +#define CP_NV_FLAGS_1__DISCARD_31__SHIFT 0x0000001e +#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT 0x0000001f + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32__SHIFT 0x00000000 +#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT 0x00000001 +#define CP_NV_FLAGS_2__DISCARD_33__SHIFT 0x00000002 +#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT 0x00000003 +#define CP_NV_FLAGS_2__DISCARD_34__SHIFT 0x00000004 +#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT 0x00000005 +#define CP_NV_FLAGS_2__DISCARD_35__SHIFT 0x00000006 +#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT 0x00000007 +#define CP_NV_FLAGS_2__DISCARD_36__SHIFT 0x00000008 +#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT 0x00000009 +#define CP_NV_FLAGS_2__DISCARD_37__SHIFT 0x0000000a +#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT 0x0000000b +#define CP_NV_FLAGS_2__DISCARD_38__SHIFT 0x0000000c +#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT 0x0000000d +#define CP_NV_FLAGS_2__DISCARD_39__SHIFT 0x0000000e +#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT 0x0000000f +#define CP_NV_FLAGS_2__DISCARD_40__SHIFT 0x00000010 +#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT 0x00000011 +#define CP_NV_FLAGS_2__DISCARD_41__SHIFT 0x00000012 +#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT 0x00000013 +#define CP_NV_FLAGS_2__DISCARD_42__SHIFT 0x00000014 +#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT 0x00000015 +#define CP_NV_FLAGS_2__DISCARD_43__SHIFT 0x00000016 +#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT 0x00000017 +#define CP_NV_FLAGS_2__DISCARD_44__SHIFT 0x00000018 +#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT 0x00000019 +#define CP_NV_FLAGS_2__DISCARD_45__SHIFT 0x0000001a +#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT 0x0000001b +#define CP_NV_FLAGS_2__DISCARD_46__SHIFT 0x0000001c +#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT 0x0000001d +#define CP_NV_FLAGS_2__DISCARD_47__SHIFT 0x0000001e +#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT 0x0000001f + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48__SHIFT 0x00000000 +#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT 0x00000001 +#define CP_NV_FLAGS_3__DISCARD_49__SHIFT 0x00000002 +#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT 0x00000003 +#define CP_NV_FLAGS_3__DISCARD_50__SHIFT 0x00000004 +#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT 0x00000005 +#define CP_NV_FLAGS_3__DISCARD_51__SHIFT 0x00000006 +#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT 0x00000007 +#define CP_NV_FLAGS_3__DISCARD_52__SHIFT 0x00000008 +#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT 0x00000009 +#define CP_NV_FLAGS_3__DISCARD_53__SHIFT 0x0000000a +#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT 0x0000000b +#define CP_NV_FLAGS_3__DISCARD_54__SHIFT 0x0000000c +#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT 0x0000000d +#define CP_NV_FLAGS_3__DISCARD_55__SHIFT 0x0000000e +#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT 0x0000000f +#define CP_NV_FLAGS_3__DISCARD_56__SHIFT 0x00000010 +#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT 0x00000011 +#define CP_NV_FLAGS_3__DISCARD_57__SHIFT 0x00000012 +#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT 0x00000013 +#define CP_NV_FLAGS_3__DISCARD_58__SHIFT 0x00000014 +#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT 0x00000015 +#define CP_NV_FLAGS_3__DISCARD_59__SHIFT 0x00000016 +#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT 0x00000017 +#define CP_NV_FLAGS_3__DISCARD_60__SHIFT 0x00000018 +#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT 0x00000019 +#define CP_NV_FLAGS_3__DISCARD_61__SHIFT 0x0000001a +#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT 0x0000001b +#define CP_NV_FLAGS_3__DISCARD_62__SHIFT 0x0000001c +#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT 0x0000001d +#define CP_NV_FLAGS_3__DISCARD_63__SHIFT 0x0000001e +#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT 0x0000001f + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT 0x00000000 + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT 0x00000000 + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER__SHIFT 0x00000000 + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY__SHIFT 0x00000000 +#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT 0x00000001 +#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT 0x00000002 +#define CP_STAT__RBIU_BUSY__SHIFT 0x00000003 +#define CP_STAT__RCIU_BUSY__SHIFT 0x00000004 +#define CP_STAT__CSF_RING_BUSY__SHIFT 0x00000005 +#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT 0x00000006 +#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x00000007 +#define CP_STAT__CSF_ST_BUSY__SHIFT 0x00000009 +#define CP_STAT__CSF_BUSY__SHIFT 0x0000000a +#define CP_STAT__RING_QUEUE_BUSY__SHIFT 0x0000000b +#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT 0x0000000c +#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT 0x0000000d +#define CP_STAT__ST_QUEUE_BUSY__SHIFT 0x00000010 +#define CP_STAT__PFP_BUSY__SHIFT 0x00000011 +#define CP_STAT__MEQ_RING_BUSY__SHIFT 0x00000012 +#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT 0x00000013 +#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT 0x00000014 +#define CP_STAT__MIU_WC_STALL__SHIFT 0x00000015 +#define CP_STAT__CP_NRT_BUSY__SHIFT 0x00000016 +#define CP_STAT___3D_BUSY__SHIFT 0x00000017 +#define CP_STAT__ME_BUSY__SHIFT 0x0000001a +#define CP_STAT__ME_WC_BUSY__SHIFT 0x0000001d +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT 0x0000001e +#define CP_STAT__CP_BUSY__SHIFT 0x0000001f + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE__SHIFT 0x00000000 + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE__SHIFT 0x00000000 + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_PM4__STATUS__SHIFT 0x0000001f + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE__SHIFT 0x00000000 + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE__SHIFT 0x00000000 + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_HOST__STATUS__SHIFT 0x0000001f + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT 0x0000000c + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT 0x0000000c + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT 0x0000000c + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT 0x0000000c + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT 0x0000000c + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT 0x0000000c + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT 0x0000000c + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT 0x0000000c + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT 0x00000000 +#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT 0x0000000e + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000 +#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT 0x00000004 +#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT 0x00000006 +#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT 0x00000007 +#define RB_COLOR_INFO__COLOR_SWAP__SHIFT 0x00000009 +#define RB_COLOR_INFO__COLOR_BASE__SHIFT 0x0000000c + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT 0x00000000 +#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT 0x0000000c + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF__SHIFT 0x00000000 +#define RB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 +#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 +#define RB_STENCILREFMASK__RESERVED0__SHIFT 0x00000018 +#define RB_STENCILREFMASK__RESERVED1__SHIFT 0x00000019 + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF__SHIFT 0x00000000 + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED__SHIFT 0x00000000 +#define RB_COLOR_MASK__WRITE_GREEN__SHIFT 0x00000001 +#define RB_COLOR_MASK__WRITE_BLUE__SHIFT 0x00000002 +#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT 0x00000003 +#define RB_COLOR_MASK__RESERVED2__SHIFT 0x00000004 +#define RB_COLOR_MASK__RESERVED3__SHIFT 0x00000005 + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED__SHIFT 0x00000000 +#define RB_FOG_COLOR__FOG_GREEN__SHIFT 0x00000008 +#define RB_FOG_COLOR__FOG_BLUE__SHIFT 0x00000010 + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT 0x00000000 +#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 +#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT 0x00000018 +#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT 0x00000019 + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT 0x00000000 +#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT 0x00000001 +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT 0x00000003 +#define RB_DEPTHCONTROL__ZFUNC__SHIFT 0x00000004 +#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 +#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT 0x00000008 +#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT 0x0000000b +#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT 0x0000000e +#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT 0x00000011 +#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT 0x00000014 +#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT 0x00000017 +#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT 0x0000001a +#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT 0x0000001d + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT 0x0000001d +#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT 0x0000001e + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT 0x00000000 +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT 0x00000003 +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000004 +#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT 0x00000005 +#define RB_COLORCONTROL__FOG_ENABLE__SHIFT 0x00000006 +#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT 0x00000007 +#define RB_COLORCONTROL__ROP_CODE__SHIFT 0x00000008 +#define RB_COLORCONTROL__DITHER_MODE__SHIFT 0x0000000c +#define RB_COLORCONTROL__DITHER_TYPE__SHIFT 0x0000000e +#define RB_COLORCONTROL__PIXEL_FOG__SHIFT 0x00000010 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000018 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000001a +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000001c +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000001e + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE__SHIFT 0x00000000 + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT 0x00000000 + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT 0x00000000 +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000003 +#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT 0x00000004 + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT 0x0000000c + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT 0x00000000 + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT 0x00000000 +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT 0x00000003 +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004 +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT 0x00000008 +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT 0x0000000a +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT 0x0000000c +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT 0x0000000e +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT 0x0000000f +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT 0x00000010 +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT 0x00000011 + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT 0x00000000 +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT 0x0000000d + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT 0x00000000 +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT 0x00000001 + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT 0x00000000 + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT 0x00000000 +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT 0x00000001 +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT 0x00000003 +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004 +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT 0x00000005 +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT 0x00000006 +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT 0x00000007 +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT 0x00000008 +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT 0x0000000e +#define RB_BC_CONTROL__CRC_MODE__SHIFT 0x0000000f +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT 0x00000010 +#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT 0x00000011 +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT 0x00000012 +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT 0x00000016 +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT 0x00000017 +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT 0x0000001b +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d +#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT 0x0000001e +#define RB_BC_CONTROL__RESERVED6__SHIFT 0x0000001f + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT 0x00000000 +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004 +#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA__SHIFT 0x00000000 + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT 0x00000000 + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT 0x00000000 + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT 0x00000000 + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT 0x00000000 +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT 0x00000001 +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT 0x00000002 +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT 0x00000003 +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT 0x00000004 +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT 0x00000005 +#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT 0x00000006 +#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT 0x00000007 +#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT 0x00000008 +#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT 0x00000009 +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT 0x0000000a +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT 0x0000000b +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT 0x0000000c +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT 0x0000000d +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT 0x0000000e +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT 0x0000000f +#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT 0x00000010 +#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT 0x00000011 +#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT 0x00000012 +#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT 0x00000013 +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT 0x00000014 +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT 0x00000015 +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT 0x00000016 +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT 0x00000017 +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT 0x00000018 +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT 0x00000019 +#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT 0x0000001a +#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT 0x0000001b +#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT 0x0000001c +#define RB_DEBUG_0__C_REQ_FULL__SHIFT 0x0000001d +#define RB_DEBUG_0__C_MASK_FULL__SHIFT 0x0000001e +#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT 0x0000001f + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT 0x00000000 +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT 0x00000001 +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT 0x00000002 +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT 0x00000003 +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT 0x00000006 +#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT 0x00000007 +#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT 0x00000008 +#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT 0x00000009 +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT 0x0000000a +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT 0x0000000b +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT 0x0000000c +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT 0x0000000d +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT 0x0000000e +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT 0x0000000f +#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT 0x00000010 +#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT 0x00000011 +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT 0x00000012 +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT 0x00000013 +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT 0x00000000 +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT 0x00000004 +#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT 0x0000000b +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT 0x0000000c +#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT 0x0000000d +#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT 0x0000000e +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT 0x0000000f +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT 0x00000010 +#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT 0x00000011 +#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT 0x00000012 +#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT 0x00000013 +#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT 0x00000014 +#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT 0x00000015 +#define RB_DEBUG_2__Z_TILE_FULL__SHIFT 0x00000016 +#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID__SHIFT 0x00000000 +#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT 0x00000004 +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT 0x00000008 +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT 0x0000000e +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT 0x0000000f +#define RB_DEBUG_3__SHD_FULL__SHIFT 0x00000013 +#define RB_DEBUG_3__SHD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT 0x00000017 +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT 0x00000018 +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT 0x0000001b +#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT 0x0000001c + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT 0x00000000 +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT 0x00000001 +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT 0x00000002 +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT 0x00000003 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT 0x00000006 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT 0x00000007 +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT 0x00000008 +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT 0x00000009 + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT 0x00000000 + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED__SHIFT 0x00000000 + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT 0x00000009 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000 + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h new file mode 100644 index 000000000000..9e9c7282dcdb --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h @@ -0,0 +1,52571 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_CP_FIDDLE_H) +#define _CP_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * CP_RB_BASE struct + */ + +#define CP_RB_BASE_RB_BASE_SIZE 27 + +#define CP_RB_BASE_RB_BASE_SHIFT 5 + +#define CP_RB_BASE_RB_BASE_MASK 0xffffffe0 + +#define CP_RB_BASE_MASK \ + (CP_RB_BASE_RB_BASE_MASK) + +#define CP_RB_BASE(rb_base) \ + ((rb_base << CP_RB_BASE_RB_BASE_SHIFT)) + +#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \ + ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT) + +#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \ + cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int : 5; + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + } cp_rb_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + unsigned int : 5; + } cp_rb_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_base_t f; +} cp_rb_base_u; + + +/* + * CP_RB_CNTL struct + */ + +#define CP_RB_CNTL_RB_BUFSZ_SIZE 6 +#define CP_RB_CNTL_RB_BLKSZ_SIZE 6 +#define CP_RB_CNTL_BUF_SWAP_SIZE 2 +#define CP_RB_CNTL_RB_POLL_EN_SIZE 1 +#define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1 + +#define CP_RB_CNTL_RB_BUFSZ_SHIFT 0 +#define CP_RB_CNTL_RB_BLKSZ_SHIFT 8 +#define CP_RB_CNTL_BUF_SWAP_SHIFT 16 +#define CP_RB_CNTL_RB_POLL_EN_SHIFT 20 +#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT 27 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31 + +#define CP_RB_CNTL_RB_BUFSZ_MASK 0x0000003f +#define CP_RB_CNTL_RB_BLKSZ_MASK 0x00003f00 +#define CP_RB_CNTL_BUF_SWAP_MASK 0x00030000 +#define CP_RB_CNTL_RB_POLL_EN_MASK 0x00100000 +#define CP_RB_CNTL_RB_NO_UPDATE_MASK 0x08000000 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000 + +#define CP_RB_CNTL_MASK \ + (CP_RB_CNTL_RB_BUFSZ_MASK | \ + CP_RB_CNTL_RB_BLKSZ_MASK | \ + CP_RB_CNTL_BUF_SWAP_MASK | \ + CP_RB_CNTL_RB_POLL_EN_MASK | \ + CP_RB_CNTL_RB_NO_UPDATE_MASK | \ + CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) + +#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \ + ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \ + (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \ + (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \ + (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \ + (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \ + (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)) + +#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 6; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 3; + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + } cp_rb_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + unsigned int : 3; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 6; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + } cp_rb_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_cntl_t f; +} cp_rb_cntl_u; + + +/* + * CP_RB_RPTR_ADDR struct + */ + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc + +#define CP_RB_RPTR_ADDR_MASK \ + (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \ + CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) + +#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \ + ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \ + (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)) + +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + } cp_rb_rptr_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + } cp_rb_rptr_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_addr_t f; +} cp_rb_rptr_addr_u; + + +/* + * CP_RB_RPTR struct + */ + +#define CP_RB_RPTR_RB_RPTR_SIZE 20 + +#define CP_RB_RPTR_RB_RPTR_SHIFT 0 + +#define CP_RB_RPTR_RB_RPTR_MASK 0x000fffff + +#define CP_RB_RPTR_MASK \ + (CP_RB_RPTR_RB_RPTR_MASK) + +#define CP_RB_RPTR(rb_rptr) \ + ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)) + +#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \ + ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT) + +#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \ + cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + unsigned int : 12; + } cp_rb_rptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int : 12; + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + } cp_rb_rptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_t f; +} cp_rb_rptr_u; + + +/* + * CP_RB_RPTR_WR struct + */ + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE 20 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK 0x000fffff + +#define CP_RB_RPTR_WR_MASK \ + (CP_RB_RPTR_WR_RB_RPTR_WR_MASK) + +#define CP_RB_RPTR_WR(rb_rptr_wr) \ + ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)) + +#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \ + ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \ + cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + unsigned int : 12; + } cp_rb_rptr_wr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int : 12; + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + } cp_rb_rptr_wr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_wr_t f; +} cp_rb_rptr_wr_u; + + +/* + * CP_RB_WPTR struct + */ + +#define CP_RB_WPTR_RB_WPTR_SIZE 20 + +#define CP_RB_WPTR_RB_WPTR_SHIFT 0 + +#define CP_RB_WPTR_RB_WPTR_MASK 0x000fffff + +#define CP_RB_WPTR_MASK \ + (CP_RB_WPTR_RB_WPTR_MASK) + +#define CP_RB_WPTR(rb_wptr) \ + ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)) + +#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \ + ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT) + +#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \ + cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + unsigned int : 12; + } cp_rb_wptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int : 12; + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + } cp_rb_wptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_t f; +} cp_rb_wptr_u; + + +/* + * CP_RB_WPTR_DELAY struct + */ + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000 + +#define CP_RB_WPTR_DELAY_MASK \ + (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \ + CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) + +#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \ + ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \ + (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)) + +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + } cp_rb_wptr_delay_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + } cp_rb_wptr_delay_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_delay_t f; +} cp_rb_wptr_delay_u; + + +/* + * CP_RB_WPTR_BASE struct + */ + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc + +#define CP_RB_WPTR_BASE_MASK \ + (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \ + CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) + +#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \ + ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \ + (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)) + +#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + } cp_rb_wptr_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + } cp_rb_wptr_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_base_t f; +} cp_rb_wptr_base_u; + + +/* + * CP_IB1_BASE struct + */ + +#define CP_IB1_BASE_IB1_BASE_SIZE 30 + +#define CP_IB1_BASE_IB1_BASE_SHIFT 2 + +#define CP_IB1_BASE_IB1_BASE_MASK 0xfffffffc + +#define CP_IB1_BASE_MASK \ + (CP_IB1_BASE_IB1_BASE_MASK) + +#define CP_IB1_BASE(ib1_base) \ + ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)) + +#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \ + ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT) + +#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \ + cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int : 2; + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + } cp_ib1_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + unsigned int : 2; + } cp_ib1_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_base_t f; +} cp_ib1_base_u; + + +/* + * CP_IB1_BUFSZ struct + */ + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE 20 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT 0 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK 0x000fffff + +#define CP_IB1_BUFSZ_MASK \ + (CP_IB1_BUFSZ_IB1_BUFSZ_MASK) + +#define CP_IB1_BUFSZ(ib1_bufsz) \ + ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)) + +#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \ + ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \ + cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib1_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int : 12; + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + } cp_ib1_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_bufsz_t f; +} cp_ib1_bufsz_u; + + +/* + * CP_IB2_BASE struct + */ + +#define CP_IB2_BASE_IB2_BASE_SIZE 30 + +#define CP_IB2_BASE_IB2_BASE_SHIFT 2 + +#define CP_IB2_BASE_IB2_BASE_MASK 0xfffffffc + +#define CP_IB2_BASE_MASK \ + (CP_IB2_BASE_IB2_BASE_MASK) + +#define CP_IB2_BASE(ib2_base) \ + ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)) + +#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \ + ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT) + +#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \ + cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int : 2; + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + } cp_ib2_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + unsigned int : 2; + } cp_ib2_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_base_t f; +} cp_ib2_base_u; + + +/* + * CP_IB2_BUFSZ struct + */ + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE 20 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT 0 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK 0x000fffff + +#define CP_IB2_BUFSZ_MASK \ + (CP_IB2_BUFSZ_IB2_BUFSZ_MASK) + +#define CP_IB2_BUFSZ(ib2_bufsz) \ + ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)) + +#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \ + ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \ + cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib2_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int : 12; + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + } cp_ib2_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_bufsz_t f; +} cp_ib2_bufsz_u; + + +/* + * CP_ST_BASE struct + */ + +#define CP_ST_BASE_ST_BASE_SIZE 30 + +#define CP_ST_BASE_ST_BASE_SHIFT 2 + +#define CP_ST_BASE_ST_BASE_MASK 0xfffffffc + +#define CP_ST_BASE_MASK \ + (CP_ST_BASE_ST_BASE_MASK) + +#define CP_ST_BASE(st_base) \ + ((st_base << CP_ST_BASE_ST_BASE_SHIFT)) + +#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \ + ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT) + +#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \ + cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int : 2; + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + } cp_st_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + unsigned int : 2; + } cp_st_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_base_t f; +} cp_st_base_u; + + +/* + * CP_ST_BUFSZ struct + */ + +#define CP_ST_BUFSZ_ST_BUFSZ_SIZE 20 + +#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT 0 + +#define CP_ST_BUFSZ_ST_BUFSZ_MASK 0x000fffff + +#define CP_ST_BUFSZ_MASK \ + (CP_ST_BUFSZ_ST_BUFSZ_MASK) + +#define CP_ST_BUFSZ(st_bufsz) \ + ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)) + +#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \ + ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \ + cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + unsigned int : 12; + } cp_st_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int : 12; + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + } cp_st_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_bufsz_t f; +} cp_st_bufsz_u; + + +/* + * CP_QUEUE_THRESHOLDS struct + */ + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000 + +#define CP_QUEUE_THRESHOLDS_MASK \ + (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) + +#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \ + ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \ + (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \ + (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)) + +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 12; + } cp_queue_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int : 12; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + } cp_queue_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_queue_thresholds_t f; +} cp_queue_thresholds_u; + + +/* + * CP_MEQ_THRESHOLDS struct + */ + +#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5 +#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5 + +#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16 +#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24 + +#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000 +#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000 + +#define CP_MEQ_THRESHOLDS_MASK \ + (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \ + CP_MEQ_THRESHOLDS_ROQ_END_MASK) + +#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \ + ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \ + (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)) + +#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 16; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + } cp_meq_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 16; + } cp_meq_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_thresholds_t f; +} cp_meq_thresholds_u; + + +/* + * CP_CSQ_AVAIL struct + */ + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE 7 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK 0x00007f00 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK 0x007f0000 + +#define CP_CSQ_AVAIL_MASK \ + (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) + +#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \ + ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \ + (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \ + (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)) + +#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 9; + } cp_csq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int : 9; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + } cp_csq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_avail_t f; +} cp_csq_avail_u; + + +/* + * CP_STQ_AVAIL struct + */ + +#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE 7 + +#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT 0 + +#define CP_STQ_AVAIL_STQ_CNT_ST_MASK 0x0000007f + +#define CP_STQ_AVAIL_MASK \ + (CP_STQ_AVAIL_STQ_CNT_ST_MASK) + +#define CP_STQ_AVAIL(stq_cnt_st) \ + ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)) + +#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \ + ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \ + cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + unsigned int : 25; + } cp_stq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int : 25; + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + } cp_stq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_avail_t f; +} cp_stq_avail_u; + + +/* + * CP_MEQ_AVAIL struct + */ + +#define CP_MEQ_AVAIL_MEQ_CNT_SIZE 5 + +#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT 0 + +#define CP_MEQ_AVAIL_MEQ_CNT_MASK 0x0000001f + +#define CP_MEQ_AVAIL_MASK \ + (CP_MEQ_AVAIL_MEQ_CNT_MASK) + +#define CP_MEQ_AVAIL(meq_cnt) \ + ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)) + +#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \ + ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \ + cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + unsigned int : 27; + } cp_meq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int : 27; + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + } cp_meq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_avail_t f; +} cp_meq_avail_u; + + +/* + * CP_CSQ_RB_STAT struct + */ + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000 + +#define CP_CSQ_RB_STAT_MASK \ + (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \ + CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) + +#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \ + ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \ + (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)) + +#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + } cp_csq_rb_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + } cp_csq_rb_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_rb_stat_t f; +} cp_csq_rb_stat_u; + + +/* + * CP_CSQ_IB1_STAT struct + */ + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000 + +#define CP_CSQ_IB1_STAT_MASK \ + (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \ + CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) + +#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \ + ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \ + (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)) + +#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + } cp_csq_ib1_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + } cp_csq_ib1_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib1_stat_t f; +} cp_csq_ib1_stat_u; + + +/* + * CP_CSQ_IB2_STAT struct + */ + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000 + +#define CP_CSQ_IB2_STAT_MASK \ + (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \ + CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) + +#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \ + ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \ + (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)) + +#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + } cp_csq_ib2_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + } cp_csq_ib2_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib2_stat_t f; +} cp_csq_ib2_stat_u; + + +/* + * CP_NON_PREFETCH_CNTRS struct + */ + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700 + +#define CP_NON_PREFETCH_CNTRS_MASK \ + (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \ + CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) + +#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \ + ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \ + (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)) + +#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 21; + } cp_non_prefetch_cntrs_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int : 21; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + } cp_non_prefetch_cntrs_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_non_prefetch_cntrs_t f; +} cp_non_prefetch_cntrs_u; + + +/* + * CP_STQ_ST_STAT struct + */ + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f +#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000 + +#define CP_STQ_ST_STAT_MASK \ + (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \ + CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) + +#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \ + ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \ + (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)) + +#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + } cp_stq_st_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + } cp_stq_st_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_st_stat_t f; +} cp_stq_st_stat_u; + + +/* + * CP_MEQ_STAT struct + */ + +#define CP_MEQ_STAT_MEQ_RPTR_SIZE 10 +#define CP_MEQ_STAT_MEQ_WPTR_SIZE 10 + +#define CP_MEQ_STAT_MEQ_RPTR_SHIFT 0 +#define CP_MEQ_STAT_MEQ_WPTR_SHIFT 16 + +#define CP_MEQ_STAT_MEQ_RPTR_MASK 0x000003ff +#define CP_MEQ_STAT_MEQ_WPTR_MASK 0x03ff0000 + +#define CP_MEQ_STAT_MASK \ + (CP_MEQ_STAT_MEQ_RPTR_MASK | \ + CP_MEQ_STAT_MEQ_WPTR_MASK) + +#define CP_MEQ_STAT(meq_rptr, meq_wptr) \ + ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \ + (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)) + +#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + } cp_meq_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + } cp_meq_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_stat_t f; +} cp_meq_stat_u; + + +/* + * CP_MIU_TAG_STAT struct + */ + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001 +#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002 +#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004 +#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008 +#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010 +#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020 +#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040 +#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080 +#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100 +#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200 +#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400 +#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800 +#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000 +#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000 +#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000 +#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000 +#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000 +#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000 + +#define CP_MIU_TAG_STAT_MASK \ + (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \ + CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) + +#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \ + ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \ + (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \ + (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \ + (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \ + (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \ + (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \ + (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \ + (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \ + (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \ + (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \ + (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \ + (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \ + (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \ + (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \ + (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \ + (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \ + (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \ + (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \ + (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)) + +#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int : 13; + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + } cp_miu_tag_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + unsigned int : 13; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + } cp_miu_tag_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_miu_tag_stat_t f; +} cp_miu_tag_stat_u; + + +/* + * CP_CMD_INDEX struct + */ + +#define CP_CMD_INDEX_CMD_INDEX_SIZE 7 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2 + +#define CP_CMD_INDEX_CMD_INDEX_SHIFT 0 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16 + +#define CP_CMD_INDEX_CMD_INDEX_MASK 0x0000007f +#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000 + +#define CP_CMD_INDEX_MASK \ + (CP_CMD_INDEX_CMD_INDEX_MASK | \ + CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) + +#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \ + ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \ + (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)) + +#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + unsigned int : 9; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 14; + } cp_cmd_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int : 14; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 9; + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + } cp_cmd_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_index_t f; +} cp_cmd_index_u; + + +/* + * CP_CMD_DATA struct + */ + +#define CP_CMD_DATA_CMD_DATA_SIZE 32 + +#define CP_CMD_DATA_CMD_DATA_SHIFT 0 + +#define CP_CMD_DATA_CMD_DATA_MASK 0xffffffff + +#define CP_CMD_DATA_MASK \ + (CP_CMD_DATA_CMD_DATA_MASK) + +#define CP_CMD_DATA(cmd_data) \ + ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)) + +#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \ + ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT) + +#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \ + cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_data_t f; +} cp_cmd_data_u; + + +/* + * CP_ME_CNTL struct + */ + +#define CP_ME_CNTL_ME_STATMUX_SIZE 16 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_ME_HALT_SIZE 1 +#define CP_ME_CNTL_ME_BUSY_SIZE 1 +#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE 1 + +#define CP_ME_CNTL_ME_STATMUX_SHIFT 0 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26 +#define CP_ME_CNTL_ME_HALT_SHIFT 28 +#define CP_ME_CNTL_ME_BUSY_SHIFT 29 +#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31 + +#define CP_ME_CNTL_ME_STATMUX_MASK 0x0000ffff +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000 +#define CP_ME_CNTL_ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL_ME_BUSY_MASK 0x20000000 +#define CP_ME_CNTL_PROG_CNT_SIZE_MASK 0x80000000 + +#define CP_ME_CNTL_MASK \ + (CP_ME_CNTL_ME_STATMUX_MASK | \ + CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_ME_HALT_MASK | \ + CP_ME_CNTL_ME_BUSY_MASK | \ + CP_ME_CNTL_PROG_CNT_SIZE_MASK) + +#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \ + ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \ + (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \ + (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \ + (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)) + +#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + unsigned int : 9; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 1; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int : 1; + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + } cp_me_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + unsigned int : 1; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int : 1; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 9; + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + } cp_me_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cntl_t f; +} cp_me_cntl_u; + + +/* + * CP_ME_STATUS struct + */ + +#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32 + +#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0 + +#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff + +#define CP_ME_STATUS_MASK \ + (CP_ME_STATUS_ME_DEBUG_DATA_MASK) + +#define CP_ME_STATUS(me_debug_data) \ + ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)) + +#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \ + ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \ + cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_status_t f; +} cp_me_status_u; + + +/* + * CP_ME_RAM_WADDR struct + */ + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff + +#define CP_ME_RAM_WADDR_MASK \ + (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) + +#define CP_ME_RAM_WADDR(me_ram_waddr) \ + ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)) + +#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \ + ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \ + cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + unsigned int : 22; + } cp_me_ram_waddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int : 22; + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + } cp_me_ram_waddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_waddr_t f; +} cp_me_ram_waddr_u; + + +/* + * CP_ME_RAM_RADDR struct + */ + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff + +#define CP_ME_RAM_RADDR_MASK \ + (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) + +#define CP_ME_RAM_RADDR(me_ram_raddr) \ + ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)) + +#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \ + ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \ + cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + unsigned int : 22; + } cp_me_ram_raddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int : 22; + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + } cp_me_ram_raddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_raddr_t f; +} cp_me_ram_raddr_u; + + +/* + * CP_ME_RAM_DATA struct + */ + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff + +#define CP_ME_RAM_DATA_MASK \ + (CP_ME_RAM_DATA_ME_RAM_DATA_MASK) + +#define CP_ME_RAM_DATA(me_ram_data) \ + ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)) + +#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \ + ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \ + cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_data_t f; +} cp_me_ram_data_u; + + +/* + * CP_ME_RDADDR struct + */ + +#define CP_ME_RDADDR_ME_RDADDR_SIZE 32 + +#define CP_ME_RDADDR_ME_RDADDR_SHIFT 0 + +#define CP_ME_RDADDR_ME_RDADDR_MASK 0xffffffff + +#define CP_ME_RDADDR_MASK \ + (CP_ME_RDADDR_ME_RDADDR_MASK) + +#define CP_ME_RDADDR(me_rdaddr) \ + ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)) + +#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \ + ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \ + cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_rdaddr_t f; +} cp_me_rdaddr_u; + + +/* + * CP_DEBUG struct + */ + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23 +#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0 +#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff +#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000 +#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000 +#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000 + +#define CP_DEBUG_MASK \ + (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \ + CP_DEBUG_PREDICATE_DISABLE_MASK | \ + CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \ + CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \ + CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \ + CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \ + CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \ + CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \ + CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) + +#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \ + ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \ + (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \ + (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \ + (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \ + (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \ + (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \ + (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \ + (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \ + (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)) + +#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \ + ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \ + ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int : 1; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + } cp_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int : 1; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + } cp_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_debug_t f; +} cp_debug_u; + + +/* + * SCRATCH_REG0 struct + */ + +#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32 + +#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0 + +#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff + +#define SCRATCH_REG0_MASK \ + (SCRATCH_REG0_SCRATCH_REG0_MASK) + +#define SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)) + +#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \ + scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg0_t f; +} scratch_reg0_u; + + +/* + * SCRATCH_REG1 struct + */ + +#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32 + +#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0 + +#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff + +#define SCRATCH_REG1_MASK \ + (SCRATCH_REG1_SCRATCH_REG1_MASK) + +#define SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)) + +#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \ + scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg1_t f; +} scratch_reg1_u; + + +/* + * SCRATCH_REG2 struct + */ + +#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32 + +#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0 + +#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff + +#define SCRATCH_REG2_MASK \ + (SCRATCH_REG2_SCRATCH_REG2_MASK) + +#define SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)) + +#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \ + scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg2_t f; +} scratch_reg2_u; + + +/* + * SCRATCH_REG3 struct + */ + +#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32 + +#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0 + +#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff + +#define SCRATCH_REG3_MASK \ + (SCRATCH_REG3_SCRATCH_REG3_MASK) + +#define SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)) + +#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \ + scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg3_t f; +} scratch_reg3_u; + + +/* + * SCRATCH_REG4 struct + */ + +#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32 + +#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0 + +#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff + +#define SCRATCH_REG4_MASK \ + (SCRATCH_REG4_SCRATCH_REG4_MASK) + +#define SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)) + +#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \ + scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg4_t f; +} scratch_reg4_u; + + +/* + * SCRATCH_REG5 struct + */ + +#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32 + +#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0 + +#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff + +#define SCRATCH_REG5_MASK \ + (SCRATCH_REG5_SCRATCH_REG5_MASK) + +#define SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)) + +#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \ + scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg5_t f; +} scratch_reg5_u; + + +/* + * SCRATCH_REG6 struct + */ + +#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32 + +#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0 + +#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff + +#define SCRATCH_REG6_MASK \ + (SCRATCH_REG6_SCRATCH_REG6_MASK) + +#define SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)) + +#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \ + scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg6_t f; +} scratch_reg6_u; + + +/* + * SCRATCH_REG7 struct + */ + +#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32 + +#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0 + +#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff + +#define SCRATCH_REG7_MASK \ + (SCRATCH_REG7_SCRATCH_REG7_MASK) + +#define SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)) + +#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \ + scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg7_t f; +} scratch_reg7_u; + + +/* + * SCRATCH_UMSK struct + */ + +#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8 +#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2 + +#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0 +#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16 + +#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff +#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000 + +#define SCRATCH_UMSK_MASK \ + (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \ + SCRATCH_UMSK_SCRATCH_SWAP_MASK) + +#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \ + ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \ + (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)) + +#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + unsigned int : 8; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 14; + } scratch_umsk_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int : 14; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 8; + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + } scratch_umsk_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_umsk_t f; +} scratch_umsk_u; + + +/* + * SCRATCH_ADDR struct + */ + +#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27 + +#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5 + +#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0 + +#define SCRATCH_ADDR_MASK \ + (SCRATCH_ADDR_SCRATCH_ADDR_MASK) + +#define SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)) + +#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \ + scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int : 5; + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + } scratch_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + unsigned int : 5; + } scratch_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_addr_t f; +} scratch_addr_u; + + +/* + * CP_ME_VS_EVENT_SRC struct + */ + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_VS_EVENT_SRC_MASK \ + (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \ + CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) + +#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \ + ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \ + (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_vs_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int : 30; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + } cp_me_vs_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_src_t f; +} cp_me_vs_event_src_u; + + +/* + * CP_ME_VS_EVENT_ADDR struct + */ + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_MASK \ + (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \ + CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) + +#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \ + ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \ + (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + } cp_me_vs_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + } cp_me_vs_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_t f; +} cp_me_vs_event_addr_u; + + +/* + * CP_ME_VS_EVENT_DATA struct + */ + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_MASK \ + (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) + +#define CP_ME_VS_EVENT_DATA(vs_done_data) \ + ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \ + ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \ + cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_t f; +} cp_me_vs_event_data_u; + + +/* + * CP_ME_VS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_SWM_MASK \ + (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \ + CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) + +#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \ + ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \ + (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_swm_t f; +} cp_me_vs_event_addr_swm_u; + + +/* + * CP_ME_VS_EVENT_DATA_SWM struct + */ + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_SWM_MASK \ + (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) + +#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \ + ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \ + ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \ + cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_swm_t f; +} cp_me_vs_event_data_swm_u; + + +/* + * CP_ME_PS_EVENT_SRC struct + */ + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_PS_EVENT_SRC_MASK \ + (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \ + CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) + +#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \ + ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \ + (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)) + +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_ps_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int : 30; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + } cp_me_ps_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_src_t f; +} cp_me_ps_event_src_u; + + +/* + * CP_ME_PS_EVENT_ADDR struct + */ + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_MASK \ + (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \ + CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) + +#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \ + ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \ + (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + } cp_me_ps_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + } cp_me_ps_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_t f; +} cp_me_ps_event_addr_u; + + +/* + * CP_ME_PS_EVENT_DATA struct + */ + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_MASK \ + (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) + +#define CP_ME_PS_EVENT_DATA(ps_done_data) \ + ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \ + ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \ + cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_t f; +} cp_me_ps_event_data_u; + + +/* + * CP_ME_PS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_SWM_MASK \ + (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \ + CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) + +#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \ + ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \ + (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_swm_t f; +} cp_me_ps_event_addr_swm_u; + + +/* + * CP_ME_PS_EVENT_DATA_SWM struct + */ + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_SWM_MASK \ + (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) + +#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \ + ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \ + ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \ + cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_swm_t f; +} cp_me_ps_event_data_swm_u; + + +/* + * CP_ME_CF_EVENT_SRC struct + */ + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001 + +#define CP_ME_CF_EVENT_SRC_MASK \ + (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) + +#define CP_ME_CF_EVENT_SRC(cf_done_src) \ + ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)) + +#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \ + ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \ + cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + unsigned int : 31; + } cp_me_cf_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int : 31; + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + } cp_me_cf_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_src_t f; +} cp_me_cf_event_src_u; + + +/* + * CP_ME_CF_EVENT_ADDR struct + */ + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_CF_EVENT_ADDR_MASK \ + (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \ + CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) + +#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \ + ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \ + (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)) + +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + } cp_me_cf_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + } cp_me_cf_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_addr_t f; +} cp_me_cf_event_addr_u; + + +/* + * CP_ME_CF_EVENT_DATA struct + */ + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff + +#define CP_ME_CF_EVENT_DATA_MASK \ + (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) + +#define CP_ME_CF_EVENT_DATA(cf_done_data) \ + ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)) + +#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \ + ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \ + cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_data_t f; +} cp_me_cf_event_data_u; + + +/* + * CP_ME_NRT_ADDR struct + */ + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc + +#define CP_ME_NRT_ADDR_MASK \ + (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \ + CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) + +#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \ + ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \ + (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)) + +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + } cp_me_nrt_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + } cp_me_nrt_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_addr_t f; +} cp_me_nrt_addr_u; + + +/* + * CP_ME_NRT_DATA struct + */ + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff + +#define CP_ME_NRT_DATA_MASK \ + (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) + +#define CP_ME_NRT_DATA(nrt_write_data) \ + ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)) + +#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \ + ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \ + cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_data_t f; +} cp_me_nrt_data_u; + + +/* + * CP_ME_VS_FETCH_DONE_SRC struct + */ + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001 + +#define CP_ME_VS_FETCH_DONE_SRC_MASK \ + (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) + +#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \ + ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \ + ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \ + cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + unsigned int : 31; + } cp_me_vs_fetch_done_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int : 31; + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + } cp_me_vs_fetch_done_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_src_t f; +} cp_me_vs_fetch_done_src_u; + + +/* + * CP_ME_VS_FETCH_DONE_ADDR struct + */ + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_FETCH_DONE_ADDR_MASK \ + (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \ + CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) + +#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \ + ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \ + (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_addr_t f; +} cp_me_vs_fetch_done_addr_u; + + +/* + * CP_ME_VS_FETCH_DONE_DATA struct + */ + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_FETCH_DONE_DATA_MASK \ + (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) + +#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \ + ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \ + ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \ + cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_data_t f; +} cp_me_vs_fetch_done_data_u; + + +/* + * CP_INT_CNTL struct + */ + +#define CP_INT_CNTL_SW_INT_MASK_SIZE 1 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB2_INT_MASK_SIZE 1 +#define CP_INT_CNTL_IB1_INT_MASK_SIZE 1 +#define CP_INT_CNTL_RB_INT_MASK_SIZE 1 + +#define CP_INT_CNTL_SW_INT_MASK_SHIFT 19 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26 +#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27 +#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29 +#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30 +#define CP_INT_CNTL_RB_INT_MASK_SHIFT 31 + +#define CP_INT_CNTL_SW_INT_MASK_MASK 0x00080000 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000 +#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000 +#define CP_INT_CNTL_IB2_INT_MASK_MASK 0x20000000 +#define CP_INT_CNTL_IB1_INT_MASK_MASK 0x40000000 +#define CP_INT_CNTL_RB_INT_MASK_MASK 0x80000000 + +#define CP_INT_CNTL_MASK \ + (CP_INT_CNTL_SW_INT_MASK_MASK | \ + CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \ + CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB2_INT_MASK_MASK | \ + CP_INT_CNTL_IB1_INT_MASK_MASK | \ + CP_INT_CNTL_RB_INT_MASK_MASK) + +#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \ + ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \ + (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \ + (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \ + (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \ + (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \ + (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \ + (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \ + (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \ + (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)) + +#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int : 19; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int : 1; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + } cp_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int : 1; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int : 3; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 19; + } cp_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_cntl_t f; +} cp_int_cntl_u; + + +/* + * CP_INT_STATUS struct + */ + +#define CP_INT_STATUS_SW_INT_STAT_SIZE 1 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1 +#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1 +#define CP_INT_STATUS_RB_INT_STAT_SIZE 1 + +#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26 +#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27 +#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29 +#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30 +#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31 + +#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000 +#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000 +#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000 + +#define CP_INT_STATUS_MASK \ + (CP_INT_STATUS_SW_INT_STAT_MASK | \ + CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \ + CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB2_INT_STAT_MASK | \ + CP_INT_STATUS_IB1_INT_STAT_MASK | \ + CP_INT_STATUS_RB_INT_STAT_MASK) + +#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \ + ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \ + (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \ + (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \ + (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \ + (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \ + (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \ + (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \ + (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \ + (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)) + +#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int : 19; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int : 1; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + } cp_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int : 1; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int : 3; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 19; + } cp_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_status_t f; +} cp_int_status_u; + + +/* + * CP_INT_ACK struct + */ + +#define CP_INT_ACK_SW_INT_ACK_SIZE 1 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB2_INT_ACK_SIZE 1 +#define CP_INT_ACK_IB1_INT_ACK_SIZE 1 +#define CP_INT_ACK_RB_INT_ACK_SIZE 1 + +#define CP_INT_ACK_SW_INT_ACK_SHIFT 19 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26 +#define CP_INT_ACK_IB_ERROR_ACK_SHIFT 27 +#define CP_INT_ACK_IB2_INT_ACK_SHIFT 29 +#define CP_INT_ACK_IB1_INT_ACK_SHIFT 30 +#define CP_INT_ACK_RB_INT_ACK_SHIFT 31 + +#define CP_INT_ACK_SW_INT_ACK_MASK 0x00080000 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000 +#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000 +#define CP_INT_ACK_IB_ERROR_ACK_MASK 0x08000000 +#define CP_INT_ACK_IB2_INT_ACK_MASK 0x20000000 +#define CP_INT_ACK_IB1_INT_ACK_MASK 0x40000000 +#define CP_INT_ACK_RB_INT_ACK_MASK 0x80000000 + +#define CP_INT_ACK_MASK \ + (CP_INT_ACK_SW_INT_ACK_MASK | \ + CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \ + CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \ + CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \ + CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \ + CP_INT_ACK_IB_ERROR_ACK_MASK | \ + CP_INT_ACK_IB2_INT_ACK_MASK | \ + CP_INT_ACK_IB1_INT_ACK_MASK | \ + CP_INT_ACK_RB_INT_ACK_MASK) + +#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \ + ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \ + (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \ + (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \ + (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \ + (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \ + (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \ + (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \ + (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \ + (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)) + +#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT) + +#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int : 19; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int : 1; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + } cp_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int : 1; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int : 3; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 19; + } cp_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_ack_t f; +} cp_int_ack_u; + + +/* + * CP_PFP_UCODE_ADDR struct + */ + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff + +#define CP_PFP_UCODE_ADDR_MASK \ + (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) + +#define CP_PFP_UCODE_ADDR(ucode_addr) \ + ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)) + +#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \ + ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \ + cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + unsigned int : 23; + } cp_pfp_ucode_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int : 23; + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + } cp_pfp_ucode_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_addr_t f; +} cp_pfp_ucode_addr_u; + + +/* + * CP_PFP_UCODE_DATA struct + */ + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff + +#define CP_PFP_UCODE_DATA_MASK \ + (CP_PFP_UCODE_DATA_UCODE_DATA_MASK) + +#define CP_PFP_UCODE_DATA(ucode_data) \ + ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)) + +#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \ + ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \ + cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + unsigned int : 8; + } cp_pfp_ucode_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int : 8; + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + } cp_pfp_ucode_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_data_t f; +} cp_pfp_ucode_data_u; + + +/* + * CP_PERFMON_CNTL struct + */ + +#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2 + +#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8 + +#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300 + +#define CP_PERFMON_CNTL_MASK \ + (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \ + CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) + +#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \ + ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \ + (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)) + +#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + unsigned int : 4; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 22; + } cp_perfmon_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int : 22; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 4; + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + } cp_perfmon_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfmon_cntl_t f; +} cp_perfmon_cntl_u; + + +/* + * CP_PERFCOUNTER_SELECT struct + */ + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f + +#define CP_PERFCOUNTER_SELECT_MASK \ + (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) + +#define CP_PERFCOUNTER_SELECT(perfcount_sel) \ + ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)) + +#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \ + ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \ + cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + unsigned int : 26; + } cp_perfcounter_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int : 26; + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + } cp_perfcounter_select_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_select_t f; +} cp_perfcounter_select_u; + + +/* + * CP_PERFCOUNTER_LO struct + */ + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff + +#define CP_PERFCOUNTER_LO_MASK \ + (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) + +#define CP_PERFCOUNTER_LO(perfcount_lo) \ + ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)) + +#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \ + ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \ + cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_lo_t f; +} cp_perfcounter_lo_u; + + +/* + * CP_PERFCOUNTER_HI struct + */ + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff + +#define CP_PERFCOUNTER_HI_MASK \ + (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) + +#define CP_PERFCOUNTER_HI(perfcount_hi) \ + ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)) + +#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \ + ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \ + cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + unsigned int : 16; + } cp_perfcounter_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int : 16; + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + } cp_perfcounter_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_hi_t f; +} cp_perfcounter_hi_u; + + +/* + * CP_BIN_MASK_LO struct + */ + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff + +#define CP_BIN_MASK_LO_MASK \ + (CP_BIN_MASK_LO_BIN_MASK_LO_MASK) + +#define CP_BIN_MASK_LO(bin_mask_lo) \ + ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)) + +#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \ + ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \ + cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_lo_t f; +} cp_bin_mask_lo_u; + + +/* + * CP_BIN_MASK_HI struct + */ + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff + +#define CP_BIN_MASK_HI_MASK \ + (CP_BIN_MASK_HI_BIN_MASK_HI_MASK) + +#define CP_BIN_MASK_HI(bin_mask_hi) \ + ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)) + +#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \ + ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \ + cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_hi_t f; +} cp_bin_mask_hi_u; + + +/* + * CP_BIN_SELECT_LO struct + */ + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff + +#define CP_BIN_SELECT_LO_MASK \ + (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) + +#define CP_BIN_SELECT_LO(bin_select_lo) \ + ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)) + +#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \ + ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \ + cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_lo_t f; +} cp_bin_select_lo_u; + + +/* + * CP_BIN_SELECT_HI struct + */ + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff + +#define CP_BIN_SELECT_HI_MASK \ + (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) + +#define CP_BIN_SELECT_HI(bin_select_hi) \ + ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)) + +#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \ + ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \ + cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_hi_t f; +} cp_bin_select_hi_u; + + +/* + * CP_NV_FLAGS_0 struct + */ + +#define CP_NV_FLAGS_0_DISCARD_0_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_0_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_1_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_1_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_2_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_2_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_3_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_3_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_4_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_4_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_5_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_5_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_6_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_6_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_7_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_7_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_8_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_8_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_9_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_9_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_10_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_11_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_12_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_13_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_14_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_15_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1 + +#define CP_NV_FLAGS_0_DISCARD_0_SHIFT 0 +#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1 +#define CP_NV_FLAGS_0_DISCARD_1_SHIFT 2 +#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3 +#define CP_NV_FLAGS_0_DISCARD_2_SHIFT 4 +#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5 +#define CP_NV_FLAGS_0_DISCARD_3_SHIFT 6 +#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7 +#define CP_NV_FLAGS_0_DISCARD_4_SHIFT 8 +#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9 +#define CP_NV_FLAGS_0_DISCARD_5_SHIFT 10 +#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11 +#define CP_NV_FLAGS_0_DISCARD_6_SHIFT 12 +#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13 +#define CP_NV_FLAGS_0_DISCARD_7_SHIFT 14 +#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15 +#define CP_NV_FLAGS_0_DISCARD_8_SHIFT 16 +#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17 +#define CP_NV_FLAGS_0_DISCARD_9_SHIFT 18 +#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19 +#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20 +#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21 +#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22 +#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23 +#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24 +#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25 +#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26 +#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27 +#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28 +#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29 +#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30 +#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31 + +#define CP_NV_FLAGS_0_DISCARD_0_MASK 0x00000001 +#define CP_NV_FLAGS_0_END_RCVD_0_MASK 0x00000002 +#define CP_NV_FLAGS_0_DISCARD_1_MASK 0x00000004 +#define CP_NV_FLAGS_0_END_RCVD_1_MASK 0x00000008 +#define CP_NV_FLAGS_0_DISCARD_2_MASK 0x00000010 +#define CP_NV_FLAGS_0_END_RCVD_2_MASK 0x00000020 +#define CP_NV_FLAGS_0_DISCARD_3_MASK 0x00000040 +#define CP_NV_FLAGS_0_END_RCVD_3_MASK 0x00000080 +#define CP_NV_FLAGS_0_DISCARD_4_MASK 0x00000100 +#define CP_NV_FLAGS_0_END_RCVD_4_MASK 0x00000200 +#define CP_NV_FLAGS_0_DISCARD_5_MASK 0x00000400 +#define CP_NV_FLAGS_0_END_RCVD_5_MASK 0x00000800 +#define CP_NV_FLAGS_0_DISCARD_6_MASK 0x00001000 +#define CP_NV_FLAGS_0_END_RCVD_6_MASK 0x00002000 +#define CP_NV_FLAGS_0_DISCARD_7_MASK 0x00004000 +#define CP_NV_FLAGS_0_END_RCVD_7_MASK 0x00008000 +#define CP_NV_FLAGS_0_DISCARD_8_MASK 0x00010000 +#define CP_NV_FLAGS_0_END_RCVD_8_MASK 0x00020000 +#define CP_NV_FLAGS_0_DISCARD_9_MASK 0x00040000 +#define CP_NV_FLAGS_0_END_RCVD_9_MASK 0x00080000 +#define CP_NV_FLAGS_0_DISCARD_10_MASK 0x00100000 +#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000 +#define CP_NV_FLAGS_0_DISCARD_11_MASK 0x00400000 +#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000 +#define CP_NV_FLAGS_0_DISCARD_12_MASK 0x01000000 +#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000 +#define CP_NV_FLAGS_0_DISCARD_13_MASK 0x04000000 +#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000 +#define CP_NV_FLAGS_0_DISCARD_14_MASK 0x10000000 +#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000 +#define CP_NV_FLAGS_0_DISCARD_15_MASK 0x40000000 +#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000 + +#define CP_NV_FLAGS_0_MASK \ + (CP_NV_FLAGS_0_DISCARD_0_MASK | \ + CP_NV_FLAGS_0_END_RCVD_0_MASK | \ + CP_NV_FLAGS_0_DISCARD_1_MASK | \ + CP_NV_FLAGS_0_END_RCVD_1_MASK | \ + CP_NV_FLAGS_0_DISCARD_2_MASK | \ + CP_NV_FLAGS_0_END_RCVD_2_MASK | \ + CP_NV_FLAGS_0_DISCARD_3_MASK | \ + CP_NV_FLAGS_0_END_RCVD_3_MASK | \ + CP_NV_FLAGS_0_DISCARD_4_MASK | \ + CP_NV_FLAGS_0_END_RCVD_4_MASK | \ + CP_NV_FLAGS_0_DISCARD_5_MASK | \ + CP_NV_FLAGS_0_END_RCVD_5_MASK | \ + CP_NV_FLAGS_0_DISCARD_6_MASK | \ + CP_NV_FLAGS_0_END_RCVD_6_MASK | \ + CP_NV_FLAGS_0_DISCARD_7_MASK | \ + CP_NV_FLAGS_0_END_RCVD_7_MASK | \ + CP_NV_FLAGS_0_DISCARD_8_MASK | \ + CP_NV_FLAGS_0_END_RCVD_8_MASK | \ + CP_NV_FLAGS_0_DISCARD_9_MASK | \ + CP_NV_FLAGS_0_END_RCVD_9_MASK | \ + CP_NV_FLAGS_0_DISCARD_10_MASK | \ + CP_NV_FLAGS_0_END_RCVD_10_MASK | \ + CP_NV_FLAGS_0_DISCARD_11_MASK | \ + CP_NV_FLAGS_0_END_RCVD_11_MASK | \ + CP_NV_FLAGS_0_DISCARD_12_MASK | \ + CP_NV_FLAGS_0_END_RCVD_12_MASK | \ + CP_NV_FLAGS_0_DISCARD_13_MASK | \ + CP_NV_FLAGS_0_END_RCVD_13_MASK | \ + CP_NV_FLAGS_0_DISCARD_14_MASK | \ + CP_NV_FLAGS_0_END_RCVD_14_MASK | \ + CP_NV_FLAGS_0_DISCARD_15_MASK | \ + CP_NV_FLAGS_0_END_RCVD_15_MASK) + +#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \ + ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \ + (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \ + (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \ + (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \ + (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \ + (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \ + (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \ + (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \ + (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \ + (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \ + (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \ + (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \ + (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \ + (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \ + (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \ + (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \ + (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \ + (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \ + (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \ + (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \ + (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \ + (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \ + (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \ + (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \ + (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \ + (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \ + (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \ + (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \ + (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \ + (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \ + (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \ + (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)) + +#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + } cp_nv_flags_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + } cp_nv_flags_0_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_0_t f; +} cp_nv_flags_0_u; + + +/* + * CP_NV_FLAGS_1 struct + */ + +#define CP_NV_FLAGS_1_DISCARD_16_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_17_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_18_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_19_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_20_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_21_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_22_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_23_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_24_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_25_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_26_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_27_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_28_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_29_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_30_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_31_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1 + +#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0 +#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1 +#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2 +#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3 +#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4 +#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5 +#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6 +#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7 +#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8 +#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9 +#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10 +#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11 +#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12 +#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13 +#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14 +#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15 +#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16 +#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17 +#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18 +#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19 +#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20 +#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21 +#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22 +#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23 +#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24 +#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25 +#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26 +#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27 +#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28 +#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29 +#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30 +#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31 + +#define CP_NV_FLAGS_1_DISCARD_16_MASK 0x00000001 +#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002 +#define CP_NV_FLAGS_1_DISCARD_17_MASK 0x00000004 +#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008 +#define CP_NV_FLAGS_1_DISCARD_18_MASK 0x00000010 +#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020 +#define CP_NV_FLAGS_1_DISCARD_19_MASK 0x00000040 +#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080 +#define CP_NV_FLAGS_1_DISCARD_20_MASK 0x00000100 +#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200 +#define CP_NV_FLAGS_1_DISCARD_21_MASK 0x00000400 +#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800 +#define CP_NV_FLAGS_1_DISCARD_22_MASK 0x00001000 +#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000 +#define CP_NV_FLAGS_1_DISCARD_23_MASK 0x00004000 +#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000 +#define CP_NV_FLAGS_1_DISCARD_24_MASK 0x00010000 +#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000 +#define CP_NV_FLAGS_1_DISCARD_25_MASK 0x00040000 +#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000 +#define CP_NV_FLAGS_1_DISCARD_26_MASK 0x00100000 +#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000 +#define CP_NV_FLAGS_1_DISCARD_27_MASK 0x00400000 +#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000 +#define CP_NV_FLAGS_1_DISCARD_28_MASK 0x01000000 +#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000 +#define CP_NV_FLAGS_1_DISCARD_29_MASK 0x04000000 +#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000 +#define CP_NV_FLAGS_1_DISCARD_30_MASK 0x10000000 +#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000 +#define CP_NV_FLAGS_1_DISCARD_31_MASK 0x40000000 +#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000 + +#define CP_NV_FLAGS_1_MASK \ + (CP_NV_FLAGS_1_DISCARD_16_MASK | \ + CP_NV_FLAGS_1_END_RCVD_16_MASK | \ + CP_NV_FLAGS_1_DISCARD_17_MASK | \ + CP_NV_FLAGS_1_END_RCVD_17_MASK | \ + CP_NV_FLAGS_1_DISCARD_18_MASK | \ + CP_NV_FLAGS_1_END_RCVD_18_MASK | \ + CP_NV_FLAGS_1_DISCARD_19_MASK | \ + CP_NV_FLAGS_1_END_RCVD_19_MASK | \ + CP_NV_FLAGS_1_DISCARD_20_MASK | \ + CP_NV_FLAGS_1_END_RCVD_20_MASK | \ + CP_NV_FLAGS_1_DISCARD_21_MASK | \ + CP_NV_FLAGS_1_END_RCVD_21_MASK | \ + CP_NV_FLAGS_1_DISCARD_22_MASK | \ + CP_NV_FLAGS_1_END_RCVD_22_MASK | \ + CP_NV_FLAGS_1_DISCARD_23_MASK | \ + CP_NV_FLAGS_1_END_RCVD_23_MASK | \ + CP_NV_FLAGS_1_DISCARD_24_MASK | \ + CP_NV_FLAGS_1_END_RCVD_24_MASK | \ + CP_NV_FLAGS_1_DISCARD_25_MASK | \ + CP_NV_FLAGS_1_END_RCVD_25_MASK | \ + CP_NV_FLAGS_1_DISCARD_26_MASK | \ + CP_NV_FLAGS_1_END_RCVD_26_MASK | \ + CP_NV_FLAGS_1_DISCARD_27_MASK | \ + CP_NV_FLAGS_1_END_RCVD_27_MASK | \ + CP_NV_FLAGS_1_DISCARD_28_MASK | \ + CP_NV_FLAGS_1_END_RCVD_28_MASK | \ + CP_NV_FLAGS_1_DISCARD_29_MASK | \ + CP_NV_FLAGS_1_END_RCVD_29_MASK | \ + CP_NV_FLAGS_1_DISCARD_30_MASK | \ + CP_NV_FLAGS_1_END_RCVD_30_MASK | \ + CP_NV_FLAGS_1_DISCARD_31_MASK | \ + CP_NV_FLAGS_1_END_RCVD_31_MASK) + +#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \ + ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \ + (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \ + (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \ + (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \ + (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \ + (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \ + (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \ + (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \ + (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \ + (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \ + (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \ + (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \ + (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \ + (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \ + (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \ + (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \ + (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \ + (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \ + (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \ + (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \ + (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \ + (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \ + (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \ + (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \ + (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \ + (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \ + (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \ + (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \ + (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \ + (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \ + (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \ + (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)) + +#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + } cp_nv_flags_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + } cp_nv_flags_1_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_1_t f; +} cp_nv_flags_1_u; + + +/* + * CP_NV_FLAGS_2 struct + */ + +#define CP_NV_FLAGS_2_DISCARD_32_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_33_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_34_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_35_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_36_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_37_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_38_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_39_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_40_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_41_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_42_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_43_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_44_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_45_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_46_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_47_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1 + +#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0 +#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1 +#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2 +#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3 +#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4 +#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5 +#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6 +#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7 +#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8 +#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9 +#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10 +#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11 +#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12 +#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13 +#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14 +#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15 +#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16 +#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17 +#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18 +#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19 +#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20 +#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21 +#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22 +#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23 +#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24 +#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25 +#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26 +#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27 +#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28 +#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29 +#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30 +#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31 + +#define CP_NV_FLAGS_2_DISCARD_32_MASK 0x00000001 +#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002 +#define CP_NV_FLAGS_2_DISCARD_33_MASK 0x00000004 +#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008 +#define CP_NV_FLAGS_2_DISCARD_34_MASK 0x00000010 +#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020 +#define CP_NV_FLAGS_2_DISCARD_35_MASK 0x00000040 +#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080 +#define CP_NV_FLAGS_2_DISCARD_36_MASK 0x00000100 +#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200 +#define CP_NV_FLAGS_2_DISCARD_37_MASK 0x00000400 +#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800 +#define CP_NV_FLAGS_2_DISCARD_38_MASK 0x00001000 +#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000 +#define CP_NV_FLAGS_2_DISCARD_39_MASK 0x00004000 +#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000 +#define CP_NV_FLAGS_2_DISCARD_40_MASK 0x00010000 +#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000 +#define CP_NV_FLAGS_2_DISCARD_41_MASK 0x00040000 +#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000 +#define CP_NV_FLAGS_2_DISCARD_42_MASK 0x00100000 +#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000 +#define CP_NV_FLAGS_2_DISCARD_43_MASK 0x00400000 +#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000 +#define CP_NV_FLAGS_2_DISCARD_44_MASK 0x01000000 +#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000 +#define CP_NV_FLAGS_2_DISCARD_45_MASK 0x04000000 +#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000 +#define CP_NV_FLAGS_2_DISCARD_46_MASK 0x10000000 +#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000 +#define CP_NV_FLAGS_2_DISCARD_47_MASK 0x40000000 +#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000 + +#define CP_NV_FLAGS_2_MASK \ + (CP_NV_FLAGS_2_DISCARD_32_MASK | \ + CP_NV_FLAGS_2_END_RCVD_32_MASK | \ + CP_NV_FLAGS_2_DISCARD_33_MASK | \ + CP_NV_FLAGS_2_END_RCVD_33_MASK | \ + CP_NV_FLAGS_2_DISCARD_34_MASK | \ + CP_NV_FLAGS_2_END_RCVD_34_MASK | \ + CP_NV_FLAGS_2_DISCARD_35_MASK | \ + CP_NV_FLAGS_2_END_RCVD_35_MASK | \ + CP_NV_FLAGS_2_DISCARD_36_MASK | \ + CP_NV_FLAGS_2_END_RCVD_36_MASK | \ + CP_NV_FLAGS_2_DISCARD_37_MASK | \ + CP_NV_FLAGS_2_END_RCVD_37_MASK | \ + CP_NV_FLAGS_2_DISCARD_38_MASK | \ + CP_NV_FLAGS_2_END_RCVD_38_MASK | \ + CP_NV_FLAGS_2_DISCARD_39_MASK | \ + CP_NV_FLAGS_2_END_RCVD_39_MASK | \ + CP_NV_FLAGS_2_DISCARD_40_MASK | \ + CP_NV_FLAGS_2_END_RCVD_40_MASK | \ + CP_NV_FLAGS_2_DISCARD_41_MASK | \ + CP_NV_FLAGS_2_END_RCVD_41_MASK | \ + CP_NV_FLAGS_2_DISCARD_42_MASK | \ + CP_NV_FLAGS_2_END_RCVD_42_MASK | \ + CP_NV_FLAGS_2_DISCARD_43_MASK | \ + CP_NV_FLAGS_2_END_RCVD_43_MASK | \ + CP_NV_FLAGS_2_DISCARD_44_MASK | \ + CP_NV_FLAGS_2_END_RCVD_44_MASK | \ + CP_NV_FLAGS_2_DISCARD_45_MASK | \ + CP_NV_FLAGS_2_END_RCVD_45_MASK | \ + CP_NV_FLAGS_2_DISCARD_46_MASK | \ + CP_NV_FLAGS_2_END_RCVD_46_MASK | \ + CP_NV_FLAGS_2_DISCARD_47_MASK | \ + CP_NV_FLAGS_2_END_RCVD_47_MASK) + +#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \ + ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \ + (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \ + (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \ + (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \ + (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \ + (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \ + (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \ + (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \ + (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \ + (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \ + (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \ + (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \ + (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \ + (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \ + (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \ + (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \ + (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \ + (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \ + (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \ + (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \ + (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \ + (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \ + (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \ + (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \ + (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \ + (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \ + (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \ + (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \ + (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \ + (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \ + (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \ + (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)) + +#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + } cp_nv_flags_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + } cp_nv_flags_2_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_2_t f; +} cp_nv_flags_2_u; + + +/* + * CP_NV_FLAGS_3 struct + */ + +#define CP_NV_FLAGS_3_DISCARD_48_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_49_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_50_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_51_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_52_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_53_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_54_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_55_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_56_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_57_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_58_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_59_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_60_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_61_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_62_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_63_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1 + +#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0 +#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1 +#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2 +#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3 +#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4 +#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5 +#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6 +#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7 +#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8 +#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9 +#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10 +#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11 +#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12 +#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13 +#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14 +#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15 +#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16 +#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17 +#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18 +#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19 +#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20 +#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21 +#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22 +#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23 +#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24 +#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25 +#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26 +#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27 +#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28 +#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29 +#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30 +#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31 + +#define CP_NV_FLAGS_3_DISCARD_48_MASK 0x00000001 +#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002 +#define CP_NV_FLAGS_3_DISCARD_49_MASK 0x00000004 +#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008 +#define CP_NV_FLAGS_3_DISCARD_50_MASK 0x00000010 +#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020 +#define CP_NV_FLAGS_3_DISCARD_51_MASK 0x00000040 +#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080 +#define CP_NV_FLAGS_3_DISCARD_52_MASK 0x00000100 +#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200 +#define CP_NV_FLAGS_3_DISCARD_53_MASK 0x00000400 +#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800 +#define CP_NV_FLAGS_3_DISCARD_54_MASK 0x00001000 +#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000 +#define CP_NV_FLAGS_3_DISCARD_55_MASK 0x00004000 +#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000 +#define CP_NV_FLAGS_3_DISCARD_56_MASK 0x00010000 +#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000 +#define CP_NV_FLAGS_3_DISCARD_57_MASK 0x00040000 +#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000 +#define CP_NV_FLAGS_3_DISCARD_58_MASK 0x00100000 +#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000 +#define CP_NV_FLAGS_3_DISCARD_59_MASK 0x00400000 +#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000 +#define CP_NV_FLAGS_3_DISCARD_60_MASK 0x01000000 +#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000 +#define CP_NV_FLAGS_3_DISCARD_61_MASK 0x04000000 +#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000 +#define CP_NV_FLAGS_3_DISCARD_62_MASK 0x10000000 +#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000 +#define CP_NV_FLAGS_3_DISCARD_63_MASK 0x40000000 +#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000 + +#define CP_NV_FLAGS_3_MASK \ + (CP_NV_FLAGS_3_DISCARD_48_MASK | \ + CP_NV_FLAGS_3_END_RCVD_48_MASK | \ + CP_NV_FLAGS_3_DISCARD_49_MASK | \ + CP_NV_FLAGS_3_END_RCVD_49_MASK | \ + CP_NV_FLAGS_3_DISCARD_50_MASK | \ + CP_NV_FLAGS_3_END_RCVD_50_MASK | \ + CP_NV_FLAGS_3_DISCARD_51_MASK | \ + CP_NV_FLAGS_3_END_RCVD_51_MASK | \ + CP_NV_FLAGS_3_DISCARD_52_MASK | \ + CP_NV_FLAGS_3_END_RCVD_52_MASK | \ + CP_NV_FLAGS_3_DISCARD_53_MASK | \ + CP_NV_FLAGS_3_END_RCVD_53_MASK | \ + CP_NV_FLAGS_3_DISCARD_54_MASK | \ + CP_NV_FLAGS_3_END_RCVD_54_MASK | \ + CP_NV_FLAGS_3_DISCARD_55_MASK | \ + CP_NV_FLAGS_3_END_RCVD_55_MASK | \ + CP_NV_FLAGS_3_DISCARD_56_MASK | \ + CP_NV_FLAGS_3_END_RCVD_56_MASK | \ + CP_NV_FLAGS_3_DISCARD_57_MASK | \ + CP_NV_FLAGS_3_END_RCVD_57_MASK | \ + CP_NV_FLAGS_3_DISCARD_58_MASK | \ + CP_NV_FLAGS_3_END_RCVD_58_MASK | \ + CP_NV_FLAGS_3_DISCARD_59_MASK | \ + CP_NV_FLAGS_3_END_RCVD_59_MASK | \ + CP_NV_FLAGS_3_DISCARD_60_MASK | \ + CP_NV_FLAGS_3_END_RCVD_60_MASK | \ + CP_NV_FLAGS_3_DISCARD_61_MASK | \ + CP_NV_FLAGS_3_END_RCVD_61_MASK | \ + CP_NV_FLAGS_3_DISCARD_62_MASK | \ + CP_NV_FLAGS_3_END_RCVD_62_MASK | \ + CP_NV_FLAGS_3_DISCARD_63_MASK | \ + CP_NV_FLAGS_3_END_RCVD_63_MASK) + +#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \ + ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \ + (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \ + (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \ + (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \ + (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \ + (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \ + (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \ + (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \ + (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \ + (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \ + (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \ + (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \ + (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \ + (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \ + (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \ + (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \ + (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \ + (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \ + (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \ + (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \ + (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \ + (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \ + (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \ + (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \ + (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \ + (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \ + (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \ + (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \ + (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \ + (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \ + (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \ + (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)) + +#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + } cp_nv_flags_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + } cp_nv_flags_3_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_3_t f; +} cp_nv_flags_3_u; + + +/* + * CP_STATE_DEBUG_INDEX struct + */ + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f + +#define CP_STATE_DEBUG_INDEX_MASK \ + (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) + +#define CP_STATE_DEBUG_INDEX(state_debug_index) \ + ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)) + +#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \ + ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \ + cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + unsigned int : 27; + } cp_state_debug_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int : 27; + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + } cp_state_debug_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_index_t f; +} cp_state_debug_index_u; + + +/* + * CP_STATE_DEBUG_DATA struct + */ + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff + +#define CP_STATE_DEBUG_DATA_MASK \ + (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) + +#define CP_STATE_DEBUG_DATA(state_debug_data) \ + ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)) + +#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \ + ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \ + cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_data_t f; +} cp_state_debug_data_u; + + +/* + * CP_PROG_COUNTER struct + */ + +#define CP_PROG_COUNTER_COUNTER_SIZE 32 + +#define CP_PROG_COUNTER_COUNTER_SHIFT 0 + +#define CP_PROG_COUNTER_COUNTER_MASK 0xffffffff + +#define CP_PROG_COUNTER_MASK \ + (CP_PROG_COUNTER_COUNTER_MASK) + +#define CP_PROG_COUNTER(counter) \ + ((counter << CP_PROG_COUNTER_COUNTER_SHIFT)) + +#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \ + ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT) + +#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \ + cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_prog_counter_t f; +} cp_prog_counter_u; + + +/* + * CP_STAT struct + */ + +#define CP_STAT_MIU_WR_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_REQ_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1 +#define CP_STAT_RBIU_BUSY_SIZE 1 +#define CP_STAT_RCIU_BUSY_SIZE 1 +#define CP_STAT_CSF_RING_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_CSF_ST_BUSY_SIZE 1 +#define CP_STAT_CSF_BUSY_SIZE 1 +#define CP_STAT_RING_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1 +#define CP_STAT_ST_QUEUE_BUSY_SIZE 1 +#define CP_STAT_PFP_BUSY_SIZE 1 +#define CP_STAT_MEQ_RING_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_STALL_SIZE 1 +#define CP_STAT_CP_NRT_BUSY_SIZE 1 +#define CP_STAT__3D_BUSY_SIZE 1 +#define CP_STAT_ME_BUSY_SIZE 1 +#define CP_STAT_ME_WC_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1 +#define CP_STAT_CP_BUSY_SIZE 1 + +#define CP_STAT_MIU_WR_BUSY_SHIFT 0 +#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2 +#define CP_STAT_RBIU_BUSY_SHIFT 3 +#define CP_STAT_RCIU_BUSY_SHIFT 4 +#define CP_STAT_CSF_RING_BUSY_SHIFT 5 +#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6 +#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7 +#define CP_STAT_CSF_ST_BUSY_SHIFT 9 +#define CP_STAT_CSF_BUSY_SHIFT 10 +#define CP_STAT_RING_QUEUE_BUSY_SHIFT 11 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13 +#define CP_STAT_ST_QUEUE_BUSY_SHIFT 16 +#define CP_STAT_PFP_BUSY_SHIFT 17 +#define CP_STAT_MEQ_RING_BUSY_SHIFT 18 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20 +#define CP_STAT_MIU_WC_STALL_SHIFT 21 +#define CP_STAT_CP_NRT_BUSY_SHIFT 22 +#define CP_STAT__3D_BUSY_SHIFT 23 +#define CP_STAT_ME_BUSY_SHIFT 26 +#define CP_STAT_ME_WC_BUSY_SHIFT 29 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30 +#define CP_STAT_CP_BUSY_SHIFT 31 + +#define CP_STAT_MIU_WR_BUSY_MASK 0x00000001 +#define CP_STAT_MIU_RD_REQ_BUSY_MASK 0x00000002 +#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004 +#define CP_STAT_RBIU_BUSY_MASK 0x00000008 +#define CP_STAT_RCIU_BUSY_MASK 0x00000010 +#define CP_STAT_CSF_RING_BUSY_MASK 0x00000020 +#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040 +#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080 +#define CP_STAT_CSF_ST_BUSY_MASK 0x00000200 +#define CP_STAT_CSF_BUSY_MASK 0x00000400 +#define CP_STAT_RING_QUEUE_BUSY_MASK 0x00000800 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000 +#define CP_STAT_ST_QUEUE_BUSY_MASK 0x00010000 +#define CP_STAT_PFP_BUSY_MASK 0x00020000 +#define CP_STAT_MEQ_RING_BUSY_MASK 0x00040000 +#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000 +#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000 +#define CP_STAT_MIU_WC_STALL_MASK 0x00200000 +#define CP_STAT_CP_NRT_BUSY_MASK 0x00400000 +#define CP_STAT__3D_BUSY_MASK 0x00800000 +#define CP_STAT_ME_BUSY_MASK 0x04000000 +#define CP_STAT_ME_WC_BUSY_MASK 0x20000000 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000 +#define CP_STAT_CP_BUSY_MASK 0x80000000 + +#define CP_STAT_MASK \ + (CP_STAT_MIU_WR_BUSY_MASK | \ + CP_STAT_MIU_RD_REQ_BUSY_MASK | \ + CP_STAT_MIU_RD_RETURN_BUSY_MASK | \ + CP_STAT_RBIU_BUSY_MASK | \ + CP_STAT_RCIU_BUSY_MASK | \ + CP_STAT_CSF_RING_BUSY_MASK | \ + CP_STAT_CSF_INDIRECTS_BUSY_MASK | \ + CP_STAT_CSF_INDIRECT2_BUSY_MASK | \ + CP_STAT_CSF_ST_BUSY_MASK | \ + CP_STAT_CSF_BUSY_MASK | \ + CP_STAT_RING_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \ + CP_STAT_ST_QUEUE_BUSY_MASK | \ + CP_STAT_PFP_BUSY_MASK | \ + CP_STAT_MEQ_RING_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \ + CP_STAT_MIU_WC_STALL_MASK | \ + CP_STAT_CP_NRT_BUSY_MASK | \ + CP_STAT__3D_BUSY_MASK | \ + CP_STAT_ME_BUSY_MASK | \ + CP_STAT_ME_WC_BUSY_MASK | \ + CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \ + CP_STAT_CP_BUSY_MASK) + +#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \ + ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \ + (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \ + (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \ + (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \ + (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \ + (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \ + (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \ + (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \ + (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \ + (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \ + (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \ + (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \ + (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \ + (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \ + (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \ + (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \ + (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \ + (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \ + (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \ + (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \ + (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \ + (me_busy << CP_STAT_ME_BUSY_SHIFT) | \ + (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \ + (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \ + (cp_busy << CP_STAT_CP_BUSY_SHIFT)) + +#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_GET_RBIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_GET_RCIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_GET_CSF_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_PFP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_GET__3D_BUSY(cp_stat) \ + ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_GET_ME_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_GET_CP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT) + +#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + } cp_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + } cp_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stat_t f; +} cp_stat_u; + + +/* + * BIOS_0_SCRATCH struct + */ + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_0_SCRATCH_MASK \ + (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_0_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \ + ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \ + bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_0_scratch_t f; +} bios_0_scratch_u; + + +/* + * BIOS_1_SCRATCH struct + */ + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_1_SCRATCH_MASK \ + (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_1_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \ + ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \ + bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_1_scratch_t f; +} bios_1_scratch_u; + + +/* + * BIOS_2_SCRATCH struct + */ + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_2_SCRATCH_MASK \ + (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_2_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \ + ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \ + bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_2_scratch_t f; +} bios_2_scratch_u; + + +/* + * BIOS_3_SCRATCH struct + */ + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_3_SCRATCH_MASK \ + (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_3_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \ + ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \ + bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_3_scratch_t f; +} bios_3_scratch_u; + + +/* + * BIOS_4_SCRATCH struct + */ + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_4_SCRATCH_MASK \ + (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_4_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \ + ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \ + bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_4_scratch_t f; +} bios_4_scratch_u; + + +/* + * BIOS_5_SCRATCH struct + */ + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_5_SCRATCH_MASK \ + (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_5_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \ + ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \ + bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_5_scratch_t f; +} bios_5_scratch_u; + + +/* + * BIOS_6_SCRATCH struct + */ + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_6_SCRATCH_MASK \ + (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_6_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \ + ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \ + bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_6_scratch_t f; +} bios_6_scratch_u; + + +/* + * BIOS_7_SCRATCH struct + */ + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_7_SCRATCH_MASK \ + (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_7_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \ + ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \ + bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_7_scratch_t f; +} bios_7_scratch_u; + + +/* + * BIOS_8_SCRATCH struct + */ + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_8_SCRATCH_MASK \ + (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_8_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \ + ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \ + bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_8_scratch_t f; +} bios_8_scratch_u; + + +/* + * BIOS_9_SCRATCH struct + */ + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_9_SCRATCH_MASK \ + (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_9_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \ + ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \ + bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_9_scratch_t f; +} bios_9_scratch_u; + + +/* + * BIOS_10_SCRATCH struct + */ + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_10_SCRATCH_MASK \ + (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_10_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \ + ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \ + bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_10_scratch_t f; +} bios_10_scratch_u; + + +/* + * BIOS_11_SCRATCH struct + */ + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_11_SCRATCH_MASK \ + (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_11_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \ + ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \ + bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_11_scratch_t f; +} bios_11_scratch_u; + + +/* + * BIOS_12_SCRATCH struct + */ + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_12_SCRATCH_MASK \ + (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_12_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \ + ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \ + bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_12_scratch_t f; +} bios_12_scratch_u; + + +/* + * BIOS_13_SCRATCH struct + */ + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_13_SCRATCH_MASK \ + (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_13_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \ + ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \ + bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_13_scratch_t f; +} bios_13_scratch_u; + + +/* + * BIOS_14_SCRATCH struct + */ + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_14_SCRATCH_MASK \ + (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_14_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \ + ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \ + bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_14_scratch_t f; +} bios_14_scratch_u; + + +/* + * BIOS_15_SCRATCH struct + */ + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_15_SCRATCH_MASK \ + (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_15_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \ + ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \ + bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_15_scratch_t f; +} bios_15_scratch_u; + + +/* + * COHER_SIZE_PM4 struct + */ + +#define COHER_SIZE_PM4_SIZE_SIZE 32 + +#define COHER_SIZE_PM4_SIZE_SHIFT 0 + +#define COHER_SIZE_PM4_SIZE_MASK 0xffffffff + +#define COHER_SIZE_PM4_MASK \ + (COHER_SIZE_PM4_SIZE_MASK) + +#define COHER_SIZE_PM4(size) \ + ((size << COHER_SIZE_PM4_SIZE_SHIFT)) + +#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \ + ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT) + +#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \ + coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_pm4_t f; +} coher_size_pm4_u; + + +/* + * COHER_BASE_PM4 struct + */ + +#define COHER_BASE_PM4_BASE_SIZE 32 + +#define COHER_BASE_PM4_BASE_SHIFT 0 + +#define COHER_BASE_PM4_BASE_MASK 0xffffffff + +#define COHER_BASE_PM4_MASK \ + (COHER_BASE_PM4_BASE_MASK) + +#define COHER_BASE_PM4(base) \ + ((base << COHER_BASE_PM4_BASE_SHIFT)) + +#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \ + ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT) + +#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \ + coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_pm4_t f; +} coher_base_pm4_u; + + +/* + * COHER_STATUS_PM4 struct + */ + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_PM4_STATUS_SIZE 1 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_PM4_STATUS_SHIFT 31 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_PM4_STATUS_MASK 0x80000000 + +#define COHER_STATUS_PM4_MASK \ + (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \ + COHER_STATUS_PM4_STATUS_MASK) + +#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_PM4_STATUS_SHIFT)) + +#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT) + +#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + } coher_status_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + } coher_status_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_pm4_t f; +} coher_status_pm4_u; + + +/* + * COHER_SIZE_HOST struct + */ + +#define COHER_SIZE_HOST_SIZE_SIZE 32 + +#define COHER_SIZE_HOST_SIZE_SHIFT 0 + +#define COHER_SIZE_HOST_SIZE_MASK 0xffffffff + +#define COHER_SIZE_HOST_MASK \ + (COHER_SIZE_HOST_SIZE_MASK) + +#define COHER_SIZE_HOST(size) \ + ((size << COHER_SIZE_HOST_SIZE_SHIFT)) + +#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \ + ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT) + +#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \ + coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_host_t f; +} coher_size_host_u; + + +/* + * COHER_BASE_HOST struct + */ + +#define COHER_BASE_HOST_BASE_SIZE 32 + +#define COHER_BASE_HOST_BASE_SHIFT 0 + +#define COHER_BASE_HOST_BASE_MASK 0xffffffff + +#define COHER_BASE_HOST_MASK \ + (COHER_BASE_HOST_BASE_MASK) + +#define COHER_BASE_HOST(base) \ + ((base << COHER_BASE_HOST_BASE_SHIFT)) + +#define COHER_BASE_HOST_GET_BASE(coher_base_host) \ + ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT) + +#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \ + coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_host_t f; +} coher_base_host_u; + + +/* + * COHER_STATUS_HOST struct + */ + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_HOST_STATUS_SIZE 1 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_HOST_STATUS_SHIFT 31 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_HOST_STATUS_MASK 0x80000000 + +#define COHER_STATUS_HOST_MASK \ + (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \ + COHER_STATUS_HOST_STATUS_MASK) + +#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_HOST_STATUS_SHIFT)) + +#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT) + +#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + } coher_status_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + } coher_status_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_host_t f; +} coher_status_host_u; + + +/* + * COHER_DEST_BASE_0 struct + */ + +#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20 + +#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12 + +#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000 + +#define COHER_DEST_BASE_0_MASK \ + (COHER_DEST_BASE_0_DEST_BASE_0_MASK) + +#define COHER_DEST_BASE_0(dest_base_0) \ + ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)) + +#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \ + ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \ + coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int : 12; + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + } coher_dest_base_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + unsigned int : 12; + } coher_dest_base_0_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_0_t f; +} coher_dest_base_0_u; + + +/* + * COHER_DEST_BASE_1 struct + */ + +#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20 + +#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12 + +#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000 + +#define COHER_DEST_BASE_1_MASK \ + (COHER_DEST_BASE_1_DEST_BASE_1_MASK) + +#define COHER_DEST_BASE_1(dest_base_1) \ + ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)) + +#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \ + ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \ + coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int : 12; + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + } coher_dest_base_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + unsigned int : 12; + } coher_dest_base_1_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_1_t f; +} coher_dest_base_1_u; + + +/* + * COHER_DEST_BASE_2 struct + */ + +#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20 + +#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12 + +#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000 + +#define COHER_DEST_BASE_2_MASK \ + (COHER_DEST_BASE_2_DEST_BASE_2_MASK) + +#define COHER_DEST_BASE_2(dest_base_2) \ + ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)) + +#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \ + ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \ + coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int : 12; + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + } coher_dest_base_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + unsigned int : 12; + } coher_dest_base_2_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_2_t f; +} coher_dest_base_2_u; + + +/* + * COHER_DEST_BASE_3 struct + */ + +#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20 + +#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12 + +#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000 + +#define COHER_DEST_BASE_3_MASK \ + (COHER_DEST_BASE_3_DEST_BASE_3_MASK) + +#define COHER_DEST_BASE_3(dest_base_3) \ + ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)) + +#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \ + ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \ + coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int : 12; + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + } coher_dest_base_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + unsigned int : 12; + } coher_dest_base_3_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_3_t f; +} coher_dest_base_3_u; + + +/* + * COHER_DEST_BASE_4 struct + */ + +#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20 + +#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12 + +#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000 + +#define COHER_DEST_BASE_4_MASK \ + (COHER_DEST_BASE_4_DEST_BASE_4_MASK) + +#define COHER_DEST_BASE_4(dest_base_4) \ + ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)) + +#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \ + ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \ + coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int : 12; + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + } coher_dest_base_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + unsigned int : 12; + } coher_dest_base_4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_4_t f; +} coher_dest_base_4_u; + + +/* + * COHER_DEST_BASE_5 struct + */ + +#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20 + +#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12 + +#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000 + +#define COHER_DEST_BASE_5_MASK \ + (COHER_DEST_BASE_5_DEST_BASE_5_MASK) + +#define COHER_DEST_BASE_5(dest_base_5) \ + ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)) + +#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \ + ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \ + coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int : 12; + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + } coher_dest_base_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + unsigned int : 12; + } coher_dest_base_5_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_5_t f; +} coher_dest_base_5_u; + + +/* + * COHER_DEST_BASE_6 struct + */ + +#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20 + +#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12 + +#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000 + +#define COHER_DEST_BASE_6_MASK \ + (COHER_DEST_BASE_6_DEST_BASE_6_MASK) + +#define COHER_DEST_BASE_6(dest_base_6) \ + ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)) + +#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \ + ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \ + coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int : 12; + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + } coher_dest_base_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + unsigned int : 12; + } coher_dest_base_6_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_6_t f; +} coher_dest_base_6_u; + + +/* + * COHER_DEST_BASE_7 struct + */ + +#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20 + +#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12 + +#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000 + +#define COHER_DEST_BASE_7_MASK \ + (COHER_DEST_BASE_7_DEST_BASE_7_MASK) + +#define COHER_DEST_BASE_7(dest_base_7) \ + ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)) + +#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \ + ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \ + coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int : 12; + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + } coher_dest_base_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + unsigned int : 12; + } coher_dest_base_7_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_7_t f; +} coher_dest_base_7_u; + + +#endif + + +#if !defined (_RBBM_FIDDLE_H) +#define _RBBM_FIDDLE_H + +/***************************************************************************************************************** + * + * rbbm_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * WAIT_UNTIL struct + */ + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1 +#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2 +#define WAIT_UNTIL_WAIT_VSYNC_SHIFT 3 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6 +#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT 10 +#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT 14 +#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT 15 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK 0x00000002 +#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK 0x00000004 +#define WAIT_UNTIL_WAIT_VSYNC_MASK 0x00000008 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040 +#define WAIT_UNTIL_WAIT_CMDFIFO_MASK 0x00000400 +#define WAIT_UNTIL_WAIT_2D_IDLE_MASK 0x00004000 +#define WAIT_UNTIL_WAIT_3D_IDLE_MASK 0x00008000 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000 + +#define WAIT_UNTIL_MASK \ + (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \ + WAIT_UNTIL_WAIT_CMDFIFO_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \ + WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) + +#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \ + ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \ + (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \ + (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \ + (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \ + (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \ + (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \ + (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \ + (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \ + (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \ + (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \ + (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \ + (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)) + +#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \ + ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 1; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int : 2; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 8; + } wait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 8; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 2; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int : 1; + } wait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + wait_until_t f; +} wait_until_u; + + +/* + * RBBM_ISYNC_CNTL struct + */ + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020 + +#define RBBM_ISYNC_CNTL_MASK \ + (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \ + RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) + +#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \ + ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \ + (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)) + +#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 4; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int : 26; + } rbbm_isync_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 26; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int : 4; + } rbbm_isync_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_isync_cntl_t f; +} rbbm_isync_cntl_u; + + +/* + * RBBM_STATUS struct + */ + +#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5 +#define RBBM_STATUS_TC_BUSY_SIZE 1 +#define RBBM_STATUS_HIRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CPRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_PFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1 +#define RBBM_STATUS_RBBM_WU_BUSY_SIZE 1 +#define RBBM_STATUS_CP_NRT_BUSY_SIZE 1 +#define RBBM_STATUS_MH_BUSY_SIZE 1 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1 +#define RBBM_STATUS_SX_BUSY_SIZE 1 +#define RBBM_STATUS_TPC_BUSY_SIZE 1 +#define RBBM_STATUS_SC_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_PA_BUSY_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1 +#define RBBM_STATUS_RB_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_GUI_ACTIVE_SIZE 1 + +#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0 +#define RBBM_STATUS_TC_BUSY_SHIFT 5 +#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8 +#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9 +#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10 +#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12 +#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14 +#define RBBM_STATUS_CP_NRT_BUSY_SHIFT 16 +#define RBBM_STATUS_MH_BUSY_SHIFT 18 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19 +#define RBBM_STATUS_SX_BUSY_SHIFT 21 +#define RBBM_STATUS_TPC_BUSY_SHIFT 22 +#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24 +#define RBBM_STATUS_PA_BUSY_SHIFT 25 +#define RBBM_STATUS_VGT_BUSY_SHIFT 26 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28 +#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30 +#define RBBM_STATUS_GUI_ACTIVE_SHIFT 31 + +#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f +#define RBBM_STATUS_TC_BUSY_MASK 0x00000020 +#define RBBM_STATUS_HIRQ_PENDING_MASK 0x00000100 +#define RBBM_STATUS_CPRQ_PENDING_MASK 0x00000200 +#define RBBM_STATUS_CFRQ_PENDING_MASK 0x00000400 +#define RBBM_STATUS_PFRQ_PENDING_MASK 0x00000800 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000 +#define RBBM_STATUS_RBBM_WU_BUSY_MASK 0x00004000 +#define RBBM_STATUS_CP_NRT_BUSY_MASK 0x00010000 +#define RBBM_STATUS_MH_BUSY_MASK 0x00040000 +#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000 +#define RBBM_STATUS_SX_BUSY_MASK 0x00200000 +#define RBBM_STATUS_TPC_BUSY_MASK 0x00400000 +#define RBBM_STATUS_SC_CNTX_BUSY_MASK 0x01000000 +#define RBBM_STATUS_PA_BUSY_MASK 0x02000000 +#define RBBM_STATUS_VGT_BUSY_MASK 0x04000000 +#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000 +#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000 +#define RBBM_STATUS_RB_CNTX_BUSY_MASK 0x40000000 +#define RBBM_STATUS_GUI_ACTIVE_MASK 0x80000000 + +#define RBBM_STATUS_MASK \ + (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \ + RBBM_STATUS_TC_BUSY_MASK | \ + RBBM_STATUS_HIRQ_PENDING_MASK | \ + RBBM_STATUS_CPRQ_PENDING_MASK | \ + RBBM_STATUS_CFRQ_PENDING_MASK | \ + RBBM_STATUS_PFRQ_PENDING_MASK | \ + RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \ + RBBM_STATUS_RBBM_WU_BUSY_MASK | \ + RBBM_STATUS_CP_NRT_BUSY_MASK | \ + RBBM_STATUS_MH_BUSY_MASK | \ + RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \ + RBBM_STATUS_SX_BUSY_MASK | \ + RBBM_STATUS_TPC_BUSY_MASK | \ + RBBM_STATUS_SC_CNTX_BUSY_MASK | \ + RBBM_STATUS_PA_BUSY_MASK | \ + RBBM_STATUS_VGT_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \ + RBBM_STATUS_RB_CNTX_BUSY_MASK | \ + RBBM_STATUS_GUI_ACTIVE_MASK) + +#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \ + ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \ + (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \ + (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \ + (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \ + (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \ + (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \ + (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \ + (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \ + (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \ + (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \ + (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \ + (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \ + (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \ + (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \ + (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \ + (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \ + (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \ + (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \ + (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \ + (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)) + +#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int : 2; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int : 1; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int : 1; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int : 1; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + } rbbm_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int : 2; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + } rbbm_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_status_t f; +} rbbm_status_u; + + +/* + * RBBM_DSPLY struct + */ + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000 + +#define RBBM_DSPLY_MASK \ + (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \ + RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) + +#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \ + ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \ + (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \ + (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \ + (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \ + (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \ + (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \ + (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \ + (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \ + (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \ + (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \ + (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \ + (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \ + (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \ + (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \ + (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \ + (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \ + (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \ + (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \ + (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \ + (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \ + (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \ + (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \ + (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \ + (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \ + (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)) + +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int : 2; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + } rbbm_dsply_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int : 2; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + } rbbm_dsply_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_dsply_t f; +} rbbm_dsply_u; + + +/* + * RBBM_RENDER_LATEST struct + */ + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000 + +#define RBBM_RENDER_LATEST_MASK \ + (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) + +#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \ + ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \ + (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \ + (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \ + (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)) + +#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + } rbbm_render_latest_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + } rbbm_render_latest_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_render_latest_t f; +} rbbm_render_latest_u; + + +/* + * RBBM_RTL_RELEASE struct + */ + +#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32 + +#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0 + +#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff + +#define RBBM_RTL_RELEASE_MASK \ + (RBBM_RTL_RELEASE_CHANGELIST_MASK) + +#define RBBM_RTL_RELEASE(changelist) \ + ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)) + +#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \ + ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \ + rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_rtl_release_t f; +} rbbm_rtl_release_u; + + +/* + * RBBM_PATCH_RELEASE struct + */ + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000 + +#define RBBM_PATCH_RELEASE_MASK \ + (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \ + RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \ + RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) + +#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \ + ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \ + (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \ + (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)) + +#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + } rbbm_patch_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + } rbbm_patch_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_patch_release_t f; +} rbbm_patch_release_u; + + +/* + * RBBM_AUXILIARY_CONFIG struct + */ + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff + +#define RBBM_AUXILIARY_CONFIG_MASK \ + (RBBM_AUXILIARY_CONFIG_RESERVED_MASK) + +#define RBBM_AUXILIARY_CONFIG(reserved) \ + ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)) + +#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \ + ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \ + rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_auxiliary_config_t f; +} rbbm_auxiliary_config_u; + + +/* + * RBBM_PERIPHID0 struct + */ + +#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8 + +#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0 + +#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff + +#define RBBM_PERIPHID0_MASK \ + (RBBM_PERIPHID0_PARTNUMBER0_MASK) + +#define RBBM_PERIPHID0(partnumber0) \ + ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)) + +#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \ + ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \ + rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + unsigned int : 24; + } rbbm_periphid0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int : 24; + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + } rbbm_periphid0_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid0_t f; +} rbbm_periphid0_u; + + +/* + * RBBM_PERIPHID1 struct + */ + +#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4 +#define RBBM_PERIPHID1_DESIGNER0_SIZE 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0 +#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f +#define RBBM_PERIPHID1_DESIGNER0_MASK 0x000000f0 + +#define RBBM_PERIPHID1_MASK \ + (RBBM_PERIPHID1_PARTNUMBER1_MASK | \ + RBBM_PERIPHID1_DESIGNER0_MASK) + +#define RBBM_PERIPHID1(partnumber1, designer0) \ + ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \ + (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)) + +#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int : 24; + } rbbm_periphid1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int : 24; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + } rbbm_periphid1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid1_t f; +} rbbm_periphid1_u; + + +/* + * RBBM_PERIPHID2 struct + */ + +#define RBBM_PERIPHID2_DESIGNER1_SIZE 4 +#define RBBM_PERIPHID2_REVISION_SIZE 4 + +#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0 +#define RBBM_PERIPHID2_REVISION_SHIFT 4 + +#define RBBM_PERIPHID2_DESIGNER1_MASK 0x0000000f +#define RBBM_PERIPHID2_REVISION_MASK 0x000000f0 + +#define RBBM_PERIPHID2_MASK \ + (RBBM_PERIPHID2_DESIGNER1_MASK | \ + RBBM_PERIPHID2_REVISION_MASK) + +#define RBBM_PERIPHID2(designer1, revision) \ + ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \ + (revision << RBBM_PERIPHID2_REVISION_SHIFT)) + +#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT) + +#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int : 24; + } rbbm_periphid2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int : 24; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + } rbbm_periphid2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid2_t f; +} rbbm_periphid2_u; + + +/* + * RBBM_PERIPHID3 struct + */ + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_CONTINUATION_SIZE 1 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4 +#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c +#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030 +#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080 + +#define RBBM_PERIPHID3_MASK \ + (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \ + RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \ + RBBM_PERIPHID3_MH_INTERFACE_MASK | \ + RBBM_PERIPHID3_CONTINUATION_MASK) + +#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \ + ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \ + (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \ + (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \ + (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)) + +#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int : 1; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 24; + } rbbm_periphid3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int : 24; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 1; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + } rbbm_periphid3_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid3_t f; +} rbbm_periphid3_u; + + +/* + * RBBM_CNTL struct + */ + +#define RBBM_CNTL_READ_TIMEOUT_SIZE 8 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9 + +#define RBBM_CNTL_READ_TIMEOUT_SHIFT 0 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8 + +#define RBBM_CNTL_READ_TIMEOUT_MASK 0x000000ff +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00 + +#define RBBM_CNTL_MASK \ + (RBBM_CNTL_READ_TIMEOUT_MASK | \ + RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) + +#define RBBM_CNTL(read_timeout, regclk_deassert_time) \ + ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \ + (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)) + +#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int : 15; + } rbbm_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int : 15; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + } rbbm_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_cntl_t f; +} rbbm_cntl_u; + + +/* + * RBBM_SKEW_CNTL struct + */ + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f +#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0 + +#define RBBM_SKEW_CNTL_MASK \ + (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \ + RBBM_SKEW_CNTL_SKEW_COUNT_MASK) + +#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \ + ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \ + (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)) + +#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int : 22; + } rbbm_skew_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int : 22; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + } rbbm_skew_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_skew_cntl_t f; +} rbbm_skew_cntl_u; + + +/* + * RBBM_SOFT_RESET struct + */ + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000 + +#define RBBM_SOFT_RESET_MASK \ + (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) + +#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \ + ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \ + (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \ + (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \ + (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \ + (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \ + (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \ + (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \ + (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \ + (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)) + +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + unsigned int : 1; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int : 5; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 2; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int : 15; + } rbbm_soft_reset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int : 15; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int : 2; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 5; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int : 1; + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + } rbbm_soft_reset_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_soft_reset_t f; +} rbbm_soft_reset_u; + + +/* + * RBBM_PM_OVERRIDE1 struct + */ + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000 + +#define RBBM_PM_OVERRIDE1_MASK \ + (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \ + ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \ + (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override1_t f; +} rbbm_pm_override1_u; + + +/* + * RBBM_PM_OVERRIDE2 struct + */ + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800 + +#define RBBM_PM_OVERRIDE2_MASK \ + (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \ + ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \ + (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \ + (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int : 20; + } rbbm_pm_override2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int : 20; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override2_t f; +} rbbm_pm_override2_u; + + +/* + * GC_SYS_IDLE struct + */ + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000 + +#define GC_SYS_IDLE_MASK \ + (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) + +#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \ + ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \ + (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \ + (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \ + (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \ + (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \ + (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \ + (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)) + +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int : 2; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int : 3; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + } gc_sys_idle_t; + +#else // !BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int : 3; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int : 2; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + } gc_sys_idle_t; + +#endif + +typedef union { + unsigned int val : 32; + gc_sys_idle_t f; +} gc_sys_idle_u; + + +/* + * NQWAIT_UNTIL struct + */ + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001 + +#define NQWAIT_UNTIL_MASK \ + (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) + +#define NQWAIT_UNTIL(wait_gui_idle) \ + ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)) + +#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \ + ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \ + nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + unsigned int : 31; + } nqwait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int : 31; + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + } nqwait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + nqwait_until_t f; +} nqwait_until_u; + + +/* + * RBBM_DEBUG_OUT struct + */ + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff + +#define RBBM_DEBUG_OUT_MASK \ + (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) + +#define RBBM_DEBUG_OUT(debug_bus_out) \ + ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)) + +#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \ + ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \ + rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_out_t f; +} rbbm_debug_out_u; + + +/* + * RBBM_DEBUG_CNTL struct + */ + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00 +#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000 + +#define RBBM_DEBUG_CNTL_MASK \ + (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) + +#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \ + ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \ + (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \ + (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \ + (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \ + (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \ + (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)) + +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int : 3; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + } rbbm_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 3; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + } rbbm_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_cntl_t f; +} rbbm_debug_cntl_u; + + +/* + * RBBM_DEBUG struct + */ + +#define RBBM_DEBUG_IGNORE_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1 + +#define RBBM_DEBUG_IGNORE_RTR_SHIFT 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31 + +#define RBBM_DEBUG_IGNORE_RTR_MASK 0x00000002 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000 + +#define RBBM_DEBUG_MASK \ + (RBBM_DEBUG_IGNORE_RTR_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \ + RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \ + RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \ + RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) + +#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \ + ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \ + (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \ + (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \ + (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \ + (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \ + (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \ + (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \ + (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \ + (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \ + (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \ + (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \ + (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)) + +#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int : 1; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int : 3; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 4; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int : 6; + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + } rbbm_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + unsigned int : 6; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int : 4; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 3; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int : 1; + } rbbm_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_t f; +} rbbm_debug_u; + + +/* + * RBBM_READ_ERROR struct + */ + +#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15 +#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1 +#define RBBM_READ_ERROR_READ_ERROR_SIZE 1 + +#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2 +#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30 +#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31 + +#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc +#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000 +#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000 + +#define RBBM_READ_ERROR_MASK \ + (RBBM_READ_ERROR_READ_ADDRESS_MASK | \ + RBBM_READ_ERROR_READ_REQUESTER_MASK | \ + RBBM_READ_ERROR_READ_ERROR_MASK) + +#define RBBM_READ_ERROR(read_address, read_requester, read_error) \ + ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \ + (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \ + (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)) + +#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int : 2; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 13; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + } rbbm_read_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int : 13; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 2; + } rbbm_read_error_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_read_error_t f; +} rbbm_read_error_u; + + +/* + * RBBM_WAIT_IDLE_CLOCKS struct + */ + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff + +#define RBBM_WAIT_IDLE_CLOCKS_MASK \ + (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) + +#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \ + ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)) + +#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \ + ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \ + rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + unsigned int : 24; + } rbbm_wait_idle_clocks_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int : 24; + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + } rbbm_wait_idle_clocks_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_wait_idle_clocks_t f; +} rbbm_wait_idle_clocks_u; + + +/* + * RBBM_INT_CNTL struct + */ + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000 + +#define RBBM_INT_CNTL_MASK \ + (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \ + RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \ + RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) + +#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \ + ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \ + (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \ + (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)) + +#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 12; + } rbbm_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int : 12; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + } rbbm_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_cntl_t f; +} rbbm_int_cntl_u; + + +/* + * RBBM_INT_STATUS struct + */ + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000 + +#define RBBM_INT_STATUS_MASK \ + (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \ + RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \ + RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) + +#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \ + ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \ + (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \ + (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)) + +#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 12; + } rbbm_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int : 12; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + } rbbm_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_status_t f; +} rbbm_int_status_u; + + +/* + * RBBM_INT_ACK struct + */ + +#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1 + +#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19 + +#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000 + +#define RBBM_INT_ACK_MASK \ + (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \ + RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \ + RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) + +#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \ + ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \ + (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \ + (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)) + +#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 12; + } rbbm_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int : 12; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + } rbbm_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_ack_t f; +} rbbm_int_ack_u; + + +/* + * MASTER_INT_SIGNAL struct + */ + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000 +#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000 + +#define MASTER_INT_SIGNAL_MASK \ + (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) + +#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \ + ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \ + (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \ + (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \ + (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)) + +#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int : 5; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 20; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 3; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + } master_int_signal_t; + +#else // !BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int : 3; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 20; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 5; + } master_int_signal_t; + +#endif + +typedef union { + unsigned int val : 32; + master_int_signal_t f; +} master_int_signal_u; + + +/* + * RBBM_PERFCOUNTER1_SELECT struct + */ + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f + +#define RBBM_PERFCOUNTER1_SELECT_MASK \ + (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) + +#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \ + ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)) + +#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \ + ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \ + rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + unsigned int : 26; + } rbbm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int : 26; + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + } rbbm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_select_t f; +} rbbm_perfcounter1_select_u; + + +/* + * RBBM_PERFCOUNTER1_LO struct + */ + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff + +#define RBBM_PERFCOUNTER1_LO_MASK \ + (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) + +#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \ + ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)) + +#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \ + ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \ + rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_lo_t f; +} rbbm_perfcounter1_lo_u; + + +/* + * RBBM_PERFCOUNTER1_HI struct + */ + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff + +#define RBBM_PERFCOUNTER1_HI_MASK \ + (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) + +#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \ + ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)) + +#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \ + ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \ + rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + unsigned int : 16; + } rbbm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + } rbbm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_hi_t f; +} rbbm_perfcounter1_hi_u; + + +#endif + + +#if !defined (_MH_FIDDLE_H) +#define _MH_FIDDLE_H + +/***************************************************************************************************************** + * + * mh_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * MH_ARBITER_CONFIG struct + */ + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200 +#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000 + +#define MH_ARBITER_CONFIG_MASK \ + (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \ + MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \ + MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \ + MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \ + MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) + +#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \ + ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \ + (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \ + (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \ + (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \ + (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \ + (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \ + (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \ + (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \ + (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \ + (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \ + (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \ + (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \ + (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \ + (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)) + +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int : 5; + } mh_arbiter_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int : 5; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + } mh_arbiter_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_arbiter_config_t f; +} mh_arbiter_config_u; + + +/* + * MH_CLNT_AXI_ID_REUSE struct + */ + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000 + +#define MH_CLNT_AXI_ID_REUSE_MASK \ + (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \ + MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \ + MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \ + MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) + +#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \ + ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \ + (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \ + (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \ + (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \ + (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \ + (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \ + (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)) + +#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int : 17; + } mh_clnt_axi_id_reuse_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int : 17; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + } mh_clnt_axi_id_reuse_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_clnt_axi_id_reuse_t f; +} mh_clnt_axi_id_reuse_u; + + +/* + * MH_INTERRUPT_MASK struct + */ + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_MASK_MASK \ + (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + } mh_interrupt_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_mask_t f; +} mh_interrupt_mask_u; + + +/* + * MH_INTERRUPT_STATUS struct + */ + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_STATUS_MASK \ + (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + } mh_interrupt_status_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_status_t f; +} mh_interrupt_status_u; + + +/* + * MH_INTERRUPT_CLEAR struct + */ + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_CLEAR_MASK \ + (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + } mh_interrupt_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_clear_t f; +} mh_interrupt_clear_u; + + +/* + * MH_AXI_ERROR struct + */ + +#define MH_AXI_ERROR_AXI_READ_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1 +#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1 + +#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3 +#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7 + +#define MH_AXI_ERROR_AXI_READ_ID_MASK 0x00000007 +#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008 +#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080 + +#define MH_AXI_ERROR_MASK \ + (MH_AXI_ERROR_AXI_READ_ID_MASK | \ + MH_AXI_ERROR_AXI_READ_ERROR_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ID_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) + +#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \ + ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \ + (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \ + (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)) + +#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int : 24; + } mh_axi_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int : 24; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + } mh_axi_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_error_t f; +} mh_axi_error_u; + + +/* + * MH_PERFCOUNTER0_SELECT struct + */ + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER0_SELECT_MASK \ + (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \ + ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \ + mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } mh_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_select_t f; +} mh_perfcounter0_select_u; + + +/* + * MH_PERFCOUNTER1_SELECT struct + */ + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER1_SELECT_MASK \ + (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \ + ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \ + mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } mh_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_select_t f; +} mh_perfcounter1_select_u; + + +/* + * MH_PERFCOUNTER0_CONFIG struct + */ + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER0_CONFIG_MASK \ + (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER0_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \ + ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \ + mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter0_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + } mh_perfcounter0_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_config_t f; +} mh_perfcounter0_config_u; + + +/* + * MH_PERFCOUNTER1_CONFIG struct + */ + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER1_CONFIG_MASK \ + (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER1_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \ + ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \ + mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter1_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + } mh_perfcounter1_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_config_t f; +} mh_perfcounter1_config_u; + + +/* + * MH_PERFCOUNTER0_LOW struct + */ + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER0_LOW_MASK \ + (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER0_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \ + ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \ + mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_low_t f; +} mh_perfcounter0_low_u; + + +/* + * MH_PERFCOUNTER1_LOW struct + */ + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER1_LOW_MASK \ + (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER1_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \ + ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \ + mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_low_t f; +} mh_perfcounter1_low_u; + + +/* + * MH_PERFCOUNTER0_HI struct + */ + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER0_HI_MASK \ + (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER0_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \ + ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \ + mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_hi_t f; +} mh_perfcounter0_hi_u; + + +/* + * MH_PERFCOUNTER1_HI struct + */ + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER1_HI_MASK \ + (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER1_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \ + ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \ + mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_hi_t f; +} mh_perfcounter1_hi_u; + + +/* + * MH_DEBUG_CTRL struct + */ + +#define MH_DEBUG_CTRL_INDEX_SIZE 6 + +#define MH_DEBUG_CTRL_INDEX_SHIFT 0 + +#define MH_DEBUG_CTRL_INDEX_MASK 0x0000003f + +#define MH_DEBUG_CTRL_MASK \ + (MH_DEBUG_CTRL_INDEX_MASK) + +#define MH_DEBUG_CTRL(index) \ + ((index << MH_DEBUG_CTRL_INDEX_SHIFT)) + +#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \ + ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT) + +#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \ + mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + unsigned int : 26; + } mh_debug_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int : 26; + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + } mh_debug_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_ctrl_t f; +} mh_debug_ctrl_u; + + +/* + * MH_DEBUG_DATA struct + */ + +#define MH_DEBUG_DATA_DATA_SIZE 32 + +#define MH_DEBUG_DATA_DATA_SHIFT 0 + +#define MH_DEBUG_DATA_DATA_MASK 0xffffffff + +#define MH_DEBUG_DATA_MASK \ + (MH_DEBUG_DATA_DATA_MASK) + +#define MH_DEBUG_DATA(data) \ + ((data << MH_DEBUG_DATA_DATA_SHIFT)) + +#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \ + ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT) + +#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \ + mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_data_t f; +} mh_debug_data_u; + + +/* + * MH_AXI_HALT_CONTROL struct + */ + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001 + +#define MH_AXI_HALT_CONTROL_MASK \ + (MH_AXI_HALT_CONTROL_AXI_HALT_MASK) + +#define MH_AXI_HALT_CONTROL(axi_halt) \ + ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)) + +#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \ + ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \ + mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + unsigned int : 31; + } mh_axi_halt_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int : 31; + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + } mh_axi_halt_control_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_halt_control_t f; +} mh_axi_halt_control_u; + + +/* + * MH_DEBUG_REG00 struct + */ + +#define MH_DEBUG_REG00_MH_BUSY_SIZE 1 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1 +#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1 +#define MH_DEBUG_REG00_TCD_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TCD_FULL_SIZE 1 +#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1 +#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_ARQ_FULL_SIZE 1 +#define MH_DEBUG_REG00_WDB_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_WDB_FULL_SIZE 1 +#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1 + +#define MH_DEBUG_REG00_MH_BUSY_SHIFT 0 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1 +#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2 +#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3 +#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5 +#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6 +#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7 +#define MH_DEBUG_REG00_TCD_FULL_SHIFT 8 +#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9 +#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11 +#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12 +#define MH_DEBUG_REG00_ARQ_FULL_SHIFT 13 +#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14 +#define MH_DEBUG_REG00_WDB_FULL_SHIFT 15 +#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16 +#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17 +#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18 +#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19 +#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20 +#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21 +#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22 +#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23 +#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24 +#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28 + +#define MH_DEBUG_REG00_MH_BUSY_MASK 0x00000001 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002 +#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004 +#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008 +#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020 +#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040 +#define MH_DEBUG_REG00_TCD_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG00_TCD_FULL_MASK 0x00000100 +#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200 +#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800 +#define MH_DEBUG_REG00_ARQ_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG00_ARQ_FULL_MASK 0x00002000 +#define MH_DEBUG_REG00_WDB_EMPTY_MASK 0x00004000 +#define MH_DEBUG_REG00_WDB_FULL_MASK 0x00008000 +#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000 +#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000 +#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000 +#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000 +#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000 +#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000 +#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000 +#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000 +#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000 +#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000 +#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000 +#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000 +#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000 + +#define MH_DEBUG_REG00_MASK \ + (MH_DEBUG_REG00_MH_BUSY_MASK | \ + MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \ + MH_DEBUG_REG00_CP_REQUEST_MASK | \ + MH_DEBUG_REG00_VGT_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \ + MH_DEBUG_REG00_TC_CAM_FULL_MASK | \ + MH_DEBUG_REG00_TCD_EMPTY_MASK | \ + MH_DEBUG_REG00_TCD_FULL_MASK | \ + MH_DEBUG_REG00_RB_REQUEST_MASK | \ + MH_DEBUG_REG00_PA_REQUEST_MASK | \ + MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \ + MH_DEBUG_REG00_ARQ_EMPTY_MASK | \ + MH_DEBUG_REG00_ARQ_FULL_MASK | \ + MH_DEBUG_REG00_WDB_EMPTY_MASK | \ + MH_DEBUG_REG00_WDB_FULL_MASK | \ + MH_DEBUG_REG00_AXI_AVALID_MASK | \ + MH_DEBUG_REG00_AXI_AREADY_MASK | \ + MH_DEBUG_REG00_AXI_ARVALID_MASK | \ + MH_DEBUG_REG00_AXI_ARREADY_MASK | \ + MH_DEBUG_REG00_AXI_WVALID_MASK | \ + MH_DEBUG_REG00_AXI_WREADY_MASK | \ + MH_DEBUG_REG00_AXI_RVALID_MASK | \ + MH_DEBUG_REG00_AXI_RREADY_MASK | \ + MH_DEBUG_REG00_AXI_BVALID_MASK | \ + MH_DEBUG_REG00_AXI_BREADY_MASK | \ + MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \ + MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \ + MH_DEBUG_REG00_AXI_RDY_ENA_MASK) + +#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \ + ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \ + (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \ + (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \ + (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \ + (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \ + (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \ + (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \ + (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \ + (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \ + (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \ + (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \ + (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \ + (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \ + (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \ + (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \ + (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \ + (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \ + (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \ + (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \ + (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \ + (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \ + (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \ + (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \ + (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \ + (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \ + (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \ + (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \ + (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \ + (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)) + +#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int : 3; + } mh_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int : 3; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + } mh_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg00_t f; +} mh_debug_reg00_u; + + +/* + * MH_DEBUG_REG01 struct + */ + +#define MH_DEBUG_REG01_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1 +#define MH_DEBUG_REG01_CP_TAG_q_SIZE 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_TAG_q_SIZE 1 +#define MH_DEBUG_REG01_TC_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG01_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_PA_RTR_q_SIZE 1 + +#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0 +#define MH_DEBUG_REG01_CP_RTR_q_SHIFT 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2 +#define MH_DEBUG_REG01_CP_TAG_q_SHIFT 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6 +#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7 +#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8 +#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9 +#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10 +#define MH_DEBUG_REG01_TC_RTR_q_SHIFT 11 +#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14 +#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15 +#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16 +#define MH_DEBUG_REG01_RB_RTR_q_SHIFT 17 +#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18 +#define MH_DEBUG_REG01_PA_RTR_q_SHIFT 19 + +#define MH_DEBUG_REG01_CP_SEND_q_MASK 0x00000001 +#define MH_DEBUG_REG01_CP_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004 +#define MH_DEBUG_REG01_CP_TAG_q_MASK 0x00000038 +#define MH_DEBUG_REG01_CP_BLEN_q_MASK 0x00000040 +#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080 +#define MH_DEBUG_REG01_VGT_RTR_q_MASK 0x00000100 +#define MH_DEBUG_REG01_VGT_TAG_q_MASK 0x00000200 +#define MH_DEBUG_REG01_TC_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG01_TC_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG01_TC_BLEN_q_MASK 0x00001000 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000 +#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000 +#define MH_DEBUG_REG01_RB_SEND_q_MASK 0x00010000 +#define MH_DEBUG_REG01_RB_RTR_q_MASK 0x00020000 +#define MH_DEBUG_REG01_PA_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG01_PA_RTR_q_MASK 0x00080000 + +#define MH_DEBUG_REG01_MASK \ + (MH_DEBUG_REG01_CP_SEND_q_MASK | \ + MH_DEBUG_REG01_CP_RTR_q_MASK | \ + MH_DEBUG_REG01_CP_WRITE_q_MASK | \ + MH_DEBUG_REG01_CP_TAG_q_MASK | \ + MH_DEBUG_REG01_CP_BLEN_q_MASK | \ + MH_DEBUG_REG01_VGT_SEND_q_MASK | \ + MH_DEBUG_REG01_VGT_RTR_q_MASK | \ + MH_DEBUG_REG01_VGT_TAG_q_MASK | \ + MH_DEBUG_REG01_TC_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_BLEN_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_MH_written_MASK | \ + MH_DEBUG_REG01_RB_SEND_q_MASK | \ + MH_DEBUG_REG01_RB_RTR_q_MASK | \ + MH_DEBUG_REG01_PA_SEND_q_MASK | \ + MH_DEBUG_REG01_PA_RTR_q_MASK) + +#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \ + ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \ + (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \ + (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \ + (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \ + (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \ + (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \ + (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \ + (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)) + +#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int : 12; + } mh_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int : 12; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + } mh_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg01_t f; +} mh_debug_reg01_u; + + +/* + * MH_DEBUG_REG02 struct + */ + +#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3 +#define MH_DEBUG_REG02_RDC_RID_SIZE 3 +#define MH_DEBUG_REG02_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1 +#define MH_DEBUG_REG02_BRC_BID_SIZE 3 +#define MH_DEBUG_REG02_BRC_BRESP_SIZE 2 + +#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3 +#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4 +#define MH_DEBUG_REG02_RDC_RID_SHIFT 7 +#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12 +#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13 +#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14 +#define MH_DEBUG_REG02_BRC_BID_SHIFT 15 +#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18 + +#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008 +#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070 +#define MH_DEBUG_REG02_RDC_RID_MASK 0x00000380 +#define MH_DEBUG_REG02_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000 +#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000 +#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000 +#define MH_DEBUG_REG02_BRC_BID_MASK 0x00038000 +#define MH_DEBUG_REG02_BRC_BRESP_MASK 0x000c0000 + +#define MH_DEBUG_REG02_MASK \ + (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG02_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \ + MH_DEBUG_REG02_MH_CLNT_tag_MASK | \ + MH_DEBUG_REG02_RDC_RID_MASK | \ + MH_DEBUG_REG02_RDC_RRESP_MASK | \ + MH_DEBUG_REG02_MH_CP_writeclean_MASK | \ + MH_DEBUG_REG02_MH_RB_writeclean_MASK | \ + MH_DEBUG_REG02_MH_PA_writeclean_MASK | \ + MH_DEBUG_REG02_BRC_BID_MASK | \ + MH_DEBUG_REG02_BRC_BRESP_MASK) + +#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \ + ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \ + (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \ + (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \ + (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \ + (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \ + (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \ + (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \ + (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)) + +#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int : 12; + } mh_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int : 12; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + } mh_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg02_t f; +} mh_debug_reg02_u; + + +/* + * MH_DEBUG_REG03 struct + */ + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG03_MASK \ + (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) + +#define MH_DEBUG_REG03(mh_clnt_data_31_0) \ + ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)) + +#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \ + ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \ + mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg03_t f; +} mh_debug_reg03_u; + + +/* + * MH_DEBUG_REG04 struct + */ + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG04_MASK \ + (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) + +#define MH_DEBUG_REG04(mh_clnt_data_63_32) \ + ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)) + +#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \ + ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \ + mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg04_t f; +} mh_debug_reg04_u; + + +/* + * MH_DEBUG_REG05 struct + */ + +#define MH_DEBUG_REG05_CP_MH_send_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_tag_SIZE 3 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0 +#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1 +#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002 +#define MH_DEBUG_REG05_CP_MH_tag_MASK 0x0000001c +#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG05_MASK \ + (MH_DEBUG_REG05_CP_MH_send_MASK | \ + MH_DEBUG_REG05_CP_MH_write_MASK | \ + MH_DEBUG_REG05_CP_MH_tag_MASK | \ + MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \ + ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \ + (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \ + (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + } mh_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + } mh_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg05_t f; +} mh_debug_reg05_u; + + +/* + * MH_DEBUG_REG06 struct + */ + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG06_MASK \ + (MH_DEBUG_REG06_CP_MH_data_31_0_MASK) + +#define MH_DEBUG_REG06(cp_mh_data_31_0) \ + ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \ + ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \ + mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg06_t f; +} mh_debug_reg06_u; + + +/* + * MH_DEBUG_REG07 struct + */ + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG07_MASK \ + (MH_DEBUG_REG07_CP_MH_data_63_32_MASK) + +#define MH_DEBUG_REG07(cp_mh_data_63_32) \ + ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \ + ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \ + mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg07_t f; +} mh_debug_reg07_u; + + +/* + * MH_DEBUG_REG08 struct + */ + +#define MH_DEBUG_REG08_CP_MH_be_SIZE 8 +#define MH_DEBUG_REG08_RB_MH_be_SIZE 8 +#define MH_DEBUG_REG08_PA_MH_be_SIZE 8 + +#define MH_DEBUG_REG08_CP_MH_be_SHIFT 0 +#define MH_DEBUG_REG08_RB_MH_be_SHIFT 8 +#define MH_DEBUG_REG08_PA_MH_be_SHIFT 16 + +#define MH_DEBUG_REG08_CP_MH_be_MASK 0x000000ff +#define MH_DEBUG_REG08_RB_MH_be_MASK 0x0000ff00 +#define MH_DEBUG_REG08_PA_MH_be_MASK 0x00ff0000 + +#define MH_DEBUG_REG08_MASK \ + (MH_DEBUG_REG08_CP_MH_be_MASK | \ + MH_DEBUG_REG08_RB_MH_be_MASK | \ + MH_DEBUG_REG08_PA_MH_be_MASK) + +#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \ + ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \ + (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \ + (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)) + +#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int : 8; + } mh_debug_reg08_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int : 8; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + } mh_debug_reg08_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg08_t f; +} mh_debug_reg08_u; + + +/* + * MH_DEBUG_REG09 struct + */ + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3 +#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007 +#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008 +#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG09_MASK \ + (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG09_VGT_MH_send_MASK | \ + MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \ + MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \ + ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \ + (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \ + (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \ + (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + } mh_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + } mh_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg09_t f; +} mh_debug_reg09_u; + + +/* + * MH_DEBUG_REG10 struct + */ + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2 +#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004 +#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG10_MASK \ + (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG10_TC_MH_send_MASK | \ + MH_DEBUG_REG10_TC_MH_mask_MASK | \ + MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \ + (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \ + (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + } mh_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + } mh_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg10_t f; +} mh_debug_reg10_u; + + +/* + * MH_DEBUG_REG11 struct + */ + +#define MH_DEBUG_REG11_TC_MH_info_SIZE 25 +#define MH_DEBUG_REG11_TC_MH_send_SIZE 1 + +#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0 +#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25 + +#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff +#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000 + +#define MH_DEBUG_REG11_MASK \ + (MH_DEBUG_REG11_TC_MH_info_MASK | \ + MH_DEBUG_REG11_TC_MH_send_MASK) + +#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \ + ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)) + +#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int : 6; + } mh_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int : 6; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + } mh_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg11_t f; +} mh_debug_reg11_u; + + +/* + * MH_DEBUG_REG12 struct + */ + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1 +#define MH_DEBUG_REG12_TC_MH_written_SIZE 1 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25 +#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000 +#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000 + +#define MH_DEBUG_REG12_MASK \ + (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \ + MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \ + MH_DEBUG_REG12_TC_MH_written_MASK) + +#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \ + ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \ + (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)) + +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int : 5; + } mh_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int : 5; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + } mh_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg12_t f; +} mh_debug_reg12_u; + + +/* + * MH_DEBUG_REG13 struct + */ + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004 +#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG13_MASK \ + (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \ + MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \ + MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) + +#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \ + ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \ + (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \ + (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)) + +#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + } mh_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + } mh_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg13_t f; +} mh_debug_reg13_u; + + +/* + * MH_DEBUG_REG14 struct + */ + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff +#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000 + +#define MH_DEBUG_REG14_MASK \ + (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \ + MH_DEBUG_REG14_TC_ROQ_SEND_MASK) + +#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \ + ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)) + +#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int : 6; + } mh_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int : 6; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + } mh_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg14_t f; +} mh_debug_reg14_u; + + +/* + * MH_DEBUG_REG15 struct + */ + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG15_RB_MH_send_SIZE 1 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG15_MASK \ + (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG15_RB_MH_send_MASK | \ + MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \ + (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \ + (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + } mh_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + } mh_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg15_t f; +} mh_debug_reg15_u; + + +/* + * MH_DEBUG_REG16 struct + */ + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG16_MASK \ + (MH_DEBUG_REG16_RB_MH_data_31_0_MASK) + +#define MH_DEBUG_REG16(rb_mh_data_31_0) \ + ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \ + ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \ + mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg16_t f; +} mh_debug_reg16_u; + + +/* + * MH_DEBUG_REG17 struct + */ + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG17_MASK \ + (MH_DEBUG_REG17_RB_MH_data_63_32_MASK) + +#define MH_DEBUG_REG17(rb_mh_data_63_32) \ + ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg17_t f; +} mh_debug_reg17_u; + + +/* + * MH_DEBUG_REG18 struct + */ + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG18_PA_MH_send_SIZE 1 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG18_MASK \ + (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG18_PA_MH_send_MASK | \ + MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \ + (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \ + (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + } mh_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + } mh_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg18_t f; +} mh_debug_reg18_u; + + +/* + * MH_DEBUG_REG19 struct + */ + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG19_MASK \ + (MH_DEBUG_REG19_PA_MH_data_31_0_MASK) + +#define MH_DEBUG_REG19(pa_mh_data_31_0) \ + ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg19_t f; +} mh_debug_reg19_u; + + +/* + * MH_DEBUG_REG20 struct + */ + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG20_MASK \ + (MH_DEBUG_REG20_PA_MH_data_63_32_MASK) + +#define MH_DEBUG_REG20(pa_mh_data_63_32) \ + ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg20_t f; +} mh_debug_reg20_u; + + +/* + * MH_DEBUG_REG21 struct + */ + +#define MH_DEBUG_REG21_AVALID_q_SIZE 1 +#define MH_DEBUG_REG21_AREADY_q_SIZE 1 +#define MH_DEBUG_REG21_AID_q_SIZE 3 +#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3 +#define MH_DEBUG_REG21_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG21_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG21_ARID_q_SIZE 3 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG21_RVALID_q_SIZE 1 +#define MH_DEBUG_REG21_RREADY_q_SIZE 1 +#define MH_DEBUG_REG21_RLAST_q_SIZE 1 +#define MH_DEBUG_REG21_RID_q_SIZE 3 +#define MH_DEBUG_REG21_WVALID_q_SIZE 1 +#define MH_DEBUG_REG21_WREADY_q_SIZE 1 +#define MH_DEBUG_REG21_WLAST_q_SIZE 1 +#define MH_DEBUG_REG21_WID_q_SIZE 3 +#define MH_DEBUG_REG21_BVALID_q_SIZE 1 +#define MH_DEBUG_REG21_BREADY_q_SIZE 1 +#define MH_DEBUG_REG21_BID_q_SIZE 3 + +#define MH_DEBUG_REG21_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG21_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG21_AID_q_SHIFT 2 +#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5 +#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8 +#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9 +#define MH_DEBUG_REG21_ARID_q_SHIFT 10 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13 +#define MH_DEBUG_REG21_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG21_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG21_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG21_RID_q_SHIFT 18 +#define MH_DEBUG_REG21_WVALID_q_SHIFT 21 +#define MH_DEBUG_REG21_WREADY_q_SHIFT 22 +#define MH_DEBUG_REG21_WLAST_q_SHIFT 23 +#define MH_DEBUG_REG21_WID_q_SHIFT 24 +#define MH_DEBUG_REG21_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG21_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG21_BID_q_SHIFT 29 + +#define MH_DEBUG_REG21_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG21_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG21_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0 +#define MH_DEBUG_REG21_ARVALID_q_MASK 0x00000100 +#define MH_DEBUG_REG21_ARREADY_q_MASK 0x00000200 +#define MH_DEBUG_REG21_ARID_q_MASK 0x00001c00 +#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000 +#define MH_DEBUG_REG21_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG21_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG21_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG21_RID_q_MASK 0x001c0000 +#define MH_DEBUG_REG21_WVALID_q_MASK 0x00200000 +#define MH_DEBUG_REG21_WREADY_q_MASK 0x00400000 +#define MH_DEBUG_REG21_WLAST_q_MASK 0x00800000 +#define MH_DEBUG_REG21_WID_q_MASK 0x07000000 +#define MH_DEBUG_REG21_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG21_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG21_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG21_MASK \ + (MH_DEBUG_REG21_AVALID_q_MASK | \ + MH_DEBUG_REG21_AREADY_q_MASK | \ + MH_DEBUG_REG21_AID_q_MASK | \ + MH_DEBUG_REG21_ALEN_q_2_0_MASK | \ + MH_DEBUG_REG21_ARVALID_q_MASK | \ + MH_DEBUG_REG21_ARREADY_q_MASK | \ + MH_DEBUG_REG21_ARID_q_MASK | \ + MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \ + MH_DEBUG_REG21_RVALID_q_MASK | \ + MH_DEBUG_REG21_RREADY_q_MASK | \ + MH_DEBUG_REG21_RLAST_q_MASK | \ + MH_DEBUG_REG21_RID_q_MASK | \ + MH_DEBUG_REG21_WVALID_q_MASK | \ + MH_DEBUG_REG21_WREADY_q_MASK | \ + MH_DEBUG_REG21_WLAST_q_MASK | \ + MH_DEBUG_REG21_WID_q_MASK | \ + MH_DEBUG_REG21_BVALID_q_MASK | \ + MH_DEBUG_REG21_BREADY_q_MASK | \ + MH_DEBUG_REG21_BID_q_MASK) + +#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \ + (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \ + (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \ + (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)) + +#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT) + +#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + } mh_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + } mh_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg21_t f; +} mh_debug_reg21_u; + + +/* + * MH_DEBUG_REG22 struct + */ + +#define MH_DEBUG_REG22_AVALID_q_SIZE 1 +#define MH_DEBUG_REG22_AREADY_q_SIZE 1 +#define MH_DEBUG_REG22_AID_q_SIZE 3 +#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG22_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG22_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG22_ARID_q_SIZE 3 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1 +#define MH_DEBUG_REG22_WVALID_q_SIZE 1 +#define MH_DEBUG_REG22_WREADY_q_SIZE 1 +#define MH_DEBUG_REG22_WLAST_q_SIZE 1 +#define MH_DEBUG_REG22_WID_q_SIZE 3 +#define MH_DEBUG_REG22_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG22_BVALID_q_SIZE 1 +#define MH_DEBUG_REG22_BREADY_q_SIZE 1 +#define MH_DEBUG_REG22_BID_q_SIZE 3 + +#define MH_DEBUG_REG22_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG22_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG22_AID_q_SHIFT 2 +#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5 +#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7 +#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8 +#define MH_DEBUG_REG22_ARID_q_SHIFT 9 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12 +#define MH_DEBUG_REG22_WVALID_q_SHIFT 13 +#define MH_DEBUG_REG22_WREADY_q_SHIFT 14 +#define MH_DEBUG_REG22_WLAST_q_SHIFT 15 +#define MH_DEBUG_REG22_WID_q_SHIFT 16 +#define MH_DEBUG_REG22_WSTRB_q_SHIFT 19 +#define MH_DEBUG_REG22_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG22_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG22_BID_q_SHIFT 29 + +#define MH_DEBUG_REG22_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG22_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG22_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060 +#define MH_DEBUG_REG22_ARVALID_q_MASK 0x00000080 +#define MH_DEBUG_REG22_ARREADY_q_MASK 0x00000100 +#define MH_DEBUG_REG22_ARID_q_MASK 0x00000e00 +#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000 +#define MH_DEBUG_REG22_WVALID_q_MASK 0x00002000 +#define MH_DEBUG_REG22_WREADY_q_MASK 0x00004000 +#define MH_DEBUG_REG22_WLAST_q_MASK 0x00008000 +#define MH_DEBUG_REG22_WID_q_MASK 0x00070000 +#define MH_DEBUG_REG22_WSTRB_q_MASK 0x07f80000 +#define MH_DEBUG_REG22_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG22_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG22_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG22_MASK \ + (MH_DEBUG_REG22_AVALID_q_MASK | \ + MH_DEBUG_REG22_AREADY_q_MASK | \ + MH_DEBUG_REG22_AID_q_MASK | \ + MH_DEBUG_REG22_ALEN_q_1_0_MASK | \ + MH_DEBUG_REG22_ARVALID_q_MASK | \ + MH_DEBUG_REG22_ARREADY_q_MASK | \ + MH_DEBUG_REG22_ARID_q_MASK | \ + MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \ + MH_DEBUG_REG22_WVALID_q_MASK | \ + MH_DEBUG_REG22_WREADY_q_MASK | \ + MH_DEBUG_REG22_WLAST_q_MASK | \ + MH_DEBUG_REG22_WID_q_MASK | \ + MH_DEBUG_REG22_WSTRB_q_MASK | \ + MH_DEBUG_REG22_BVALID_q_MASK | \ + MH_DEBUG_REG22_BREADY_q_MASK | \ + MH_DEBUG_REG22_BID_q_MASK) + +#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \ + (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \ + (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \ + (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)) + +#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT) + +#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + } mh_debug_reg22_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + } mh_debug_reg22_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg22_t f; +} mh_debug_reg22_u; + + +/* + * MH_DEBUG_REG23 struct + */ + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001 +#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e +#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG23_MASK \ + (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) + +#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \ + ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \ + (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \ + (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)) + +#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + } mh_debug_reg23_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + } mh_debug_reg23_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg23_t f; +} mh_debug_reg23_u; + + +/* + * MH_DEBUG_REG24 struct + */ + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG24_REG_A_SIZE 14 +#define MH_DEBUG_REG24_REG_RE_SIZE 1 +#define MH_DEBUG_REG24_REG_WE_SIZE 1 +#define MH_DEBUG_REG24_BLOCK_RS_SIZE 1 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG24_REG_A_SHIFT 2 +#define MH_DEBUG_REG24_REG_RE_SHIFT 16 +#define MH_DEBUG_REG24_REG_WE_SHIFT 17 +#define MH_DEBUG_REG24_BLOCK_RS_SHIFT 18 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG24_REG_A_MASK 0x0000fffc +#define MH_DEBUG_REG24_REG_RE_MASK 0x00010000 +#define MH_DEBUG_REG24_REG_WE_MASK 0x00020000 +#define MH_DEBUG_REG24_BLOCK_RS_MASK 0x00040000 + +#define MH_DEBUG_REG24_MASK \ + (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG24_REG_A_MASK | \ + MH_DEBUG_REG24_REG_RE_MASK | \ + MH_DEBUG_REG24_REG_WE_MASK | \ + MH_DEBUG_REG24_BLOCK_RS_MASK) + +#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \ + ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \ + (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \ + (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \ + (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \ + (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)) + +#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int : 13; + } mh_debug_reg24_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int : 13; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + } mh_debug_reg24_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg24_t f; +} mh_debug_reg24_u; + + +/* + * MH_DEBUG_REG25 struct + */ + +#define MH_DEBUG_REG25_REG_WD_SIZE 32 + +#define MH_DEBUG_REG25_REG_WD_SHIFT 0 + +#define MH_DEBUG_REG25_REG_WD_MASK 0xffffffff + +#define MH_DEBUG_REG25_MASK \ + (MH_DEBUG_REG25_REG_WD_MASK) + +#define MH_DEBUG_REG25(reg_wd) \ + ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)) + +#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT) + +#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg25_t f; +} mh_debug_reg25_u; + + +/* + * MH_DEBUG_REG26 struct + */ + +#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1 +#define MH_DEBUG_REG26_CNT_q_SIZE 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG26_MH_BUSY_d_SIZE 1 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 +#define MH_DEBUG_REG26_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG26_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_PA_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG26_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG26_BRC_VALID_SIZE 1 + +#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5 +#define MH_DEBUG_REG26_CNT_q_SHIFT 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13 +#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17 +#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18 +#define MH_DEBUG_REG26_CP_RTR_q_SHIFT 19 +#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20 +#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23 +#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24 +#define MH_DEBUG_REG26_RB_RTR_q_SHIFT 25 +#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26 +#define MH_DEBUG_REG26_PA_RTR_q_SHIFT 27 +#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28 +#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29 +#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30 +#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31 + +#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008 +#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020 +#define MH_DEBUG_REG26_CNT_q_MASK 0x00000fc0 +#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG26_MH_BUSY_d_MASK 0x00004000 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000 +#define MH_DEBUG_REG26_CP_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG26_CP_RTR_q_MASK 0x00080000 +#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000 +#define MH_DEBUG_REG26_VGT_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000 +#define MH_DEBUG_REG26_RB_SEND_q_MASK 0x01000000 +#define MH_DEBUG_REG26_RB_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG26_PA_SEND_q_MASK 0x04000000 +#define MH_DEBUG_REG26_PA_RTR_q_MASK 0x08000000 +#define MH_DEBUG_REG26_RDC_VALID_MASK 0x10000000 +#define MH_DEBUG_REG26_RDC_RLAST_MASK 0x20000000 +#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000 +#define MH_DEBUG_REG26_BRC_VALID_MASK 0x80000000 + +#define MH_DEBUG_REG26_MASK \ + (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \ + MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \ + MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \ + MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \ + MH_DEBUG_REG26_CNT_q_MASK | \ + MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG26_MH_BUSY_d_MASK | \ + MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \ + MH_DEBUG_REG26_CP_SEND_q_MASK | \ + MH_DEBUG_REG26_CP_RTR_q_MASK | \ + MH_DEBUG_REG26_VGT_SEND_q_MASK | \ + MH_DEBUG_REG26_VGT_RTR_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG26_RB_SEND_q_MASK | \ + MH_DEBUG_REG26_RB_RTR_q_MASK | \ + MH_DEBUG_REG26_PA_SEND_q_MASK | \ + MH_DEBUG_REG26_PA_RTR_q_MASK | \ + MH_DEBUG_REG26_RDC_VALID_MASK | \ + MH_DEBUG_REG26_RDC_RLAST_MASK | \ + MH_DEBUG_REG26_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG26_BRC_VALID_MASK) + +#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \ + ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \ + (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \ + (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \ + (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \ + (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \ + (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \ + (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \ + (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \ + (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \ + (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \ + (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \ + (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \ + (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)) + +#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + } mh_debug_reg26_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + } mh_debug_reg26_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg26_t f; +} mh_debug_reg26_u; + + +/* + * MH_DEBUG_REG27 struct + */ + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG27_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG27_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG27_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6 +#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9 +#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12 +#define MH_DEBUG_REG27_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16 +#define MH_DEBUG_REG27_ARB_HOLD_SHIFT 17 +#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24 +#define MH_DEBUG_REG27_ARB_QUAL_SHIFT 25 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038 +#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0 +#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00 +#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000 +#define MH_DEBUG_REG27_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG27_KILL_EFF1_MASK 0x00010000 +#define MH_DEBUG_REG27_ARB_HOLD_MASK 0x00020000 +#define MH_DEBUG_REG27_ARB_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000 +#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000 +#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000 +#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000 +#define MH_DEBUG_REG27_ARB_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000 +#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000 +#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000 +#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000 + +#define MH_DEBUG_REG27_MASK \ + (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \ + MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG27_EFF1_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_q_MASK | \ + MH_DEBUG_REG27_EFF1_WIN_MASK | \ + MH_DEBUG_REG27_KILL_EFF1_MASK | \ + MH_DEBUG_REG27_ARB_HOLD_MASK | \ + MH_DEBUG_REG27_ARB_RTR_q_MASK | \ + MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_ARB_QUAL_MASK | \ + MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG27_TCHOLD_IP_q_MASK) + +#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \ + ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \ + (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \ + (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \ + (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \ + (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)) + +#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + } mh_debug_reg27_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + } mh_debug_reg27_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg27_t f; +} mh_debug_reg27_u; + + +/* + * MH_DEBUG_REG28 struct + */ + +#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG28_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10 + +#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0 +#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10 +#define MH_DEBUG_REG28_ARB_QUAL_SHIFT 11 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15 +#define MH_DEBUG_REG28_EFF1_WIN_SHIFT 16 +#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19 +#define MH_DEBUG_REG28_ARB_HOLD_SHIFT 20 +#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22 + +#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080 +#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200 +#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400 +#define MH_DEBUG_REG28_ARB_QUAL_MASK 0x00000800 +#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000 +#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000 +#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000 +#define MH_DEBUG_REG28_EFF1_WIN_MASK 0x00010000 +#define MH_DEBUG_REG28_KILL_EFF1_MASK 0x00020000 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000 +#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000 +#define MH_DEBUG_REG28_ARB_HOLD_MASK 0x00100000 +#define MH_DEBUG_REG28_ARB_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000 + +#define MH_DEBUG_REG28_MASK \ + (MH_DEBUG_REG28_EFF1_WINNER_MASK | \ + MH_DEBUG_REG28_ARB_WINNER_MASK | \ + MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_ARB_QUAL_MASK | \ + MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_EFF1_WIN_MASK | \ + MH_DEBUG_REG28_KILL_EFF1_MASK | \ + MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_RTR_q_MASK | \ + MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) + +#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \ + ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \ + (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \ + (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \ + (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \ + (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)) + +#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + } mh_debug_reg28_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + } mh_debug_reg28_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg28_t f; +} mh_debug_reg28_u; + + +/* + * MH_DEBUG_REG29 struct + */ + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1 +#define MH_DEBUG_REG29_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG29_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG29_CLNT_REQ_SIZE 5 +#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9 +#define MH_DEBUG_REG29_ARB_HOLD_SHIFT 10 +#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11 +#define MH_DEBUG_REG29_CLNT_REQ_SHIFT 12 +#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17 +#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20 +#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23 +#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26 +#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038 +#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200 +#define MH_DEBUG_REG29_ARB_HOLD_MASK 0x00000400 +#define MH_DEBUG_REG29_ARB_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG29_CLNT_REQ_MASK 0x0001f000 +#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000 +#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000 +#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000 +#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000 +#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000 + +#define MH_DEBUG_REG29_MASK \ + (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \ + MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \ + MH_DEBUG_REG29_ARB_HOLD_MASK | \ + MH_DEBUG_REG29_ARB_RTR_q_MASK | \ + MH_DEBUG_REG29_CLNT_REQ_MASK | \ + MH_DEBUG_REG29_RECENT_d_0_MASK | \ + MH_DEBUG_REG29_RECENT_d_1_MASK | \ + MH_DEBUG_REG29_RECENT_d_2_MASK | \ + MH_DEBUG_REG29_RECENT_d_3_MASK | \ + MH_DEBUG_REG29_RECENT_d_4_MASK) + +#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \ + ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \ + (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \ + (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \ + (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \ + (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \ + (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \ + (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \ + (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \ + (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \ + (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \ + (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)) + +#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + } mh_debug_reg29_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + } mh_debug_reg29_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg29_t f; +} mh_debug_reg29_u; + + +/* + * MH_DEBUG_REG30 struct + */ + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG30_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1 +#define MH_DEBUG_REG30_WLAST_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10 +#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19 +#define MH_DEBUG_REG30_WLAST_q_SHIFT 20 +#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21 +#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25 +#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28 +#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008 +#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000 +#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000 +#define MH_DEBUG_REG30_WLAST_q_MASK 0x00100000 +#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000 +#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000 +#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000 +#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000 +#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000 +#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000 + +#define MH_DEBUG_REG30_MASK \ + (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \ + MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG30_TC_MH_written_MASK | \ + MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \ + MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \ + MH_DEBUG_REG30_WLAST_q_MASK | \ + MH_DEBUG_REG30_WBURST_IP_q_MASK | \ + MH_DEBUG_REG30_WBURST_CNT_q_MASK | \ + MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_CP_MH_write_MASK | \ + MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_ARB_WINNER_MASK) + +#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \ + ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \ + (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \ + (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \ + (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \ + (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \ + (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \ + (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \ + (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \ + (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \ + (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)) + +#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + } mh_debug_reg30_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + } mh_debug_reg30_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg30_t f; +} mh_debug_reg30_u; + + +/* + * MH_DEBUG_REG31 struct + */ + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000 + +#define MH_DEBUG_REG31_MASK \ + (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \ + MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \ + ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 3; + } mh_debug_reg31_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int : 3; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + } mh_debug_reg31_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg31_t f; +} mh_debug_reg31_u; + + +/* + * MH_DEBUG_REG32 struct + */ + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8 +#define MH_DEBUG_REG32_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG32_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16 +#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00 +#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000 +#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG32_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG32_MASK \ + (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG32_ROQ_MARK_q_MASK | \ + MH_DEBUG_REG32_ROQ_VALID_q_MASK | \ + MH_DEBUG_REG32_TC_MH_send_MASK | \ + MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG32_KILL_EFF1_MASK | \ + MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG32_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \ + (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + } mh_debug_reg32_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg32_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg32_t f; +} mh_debug_reg32_u; + + +/* + * MH_DEBUG_REG33 struct + */ + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8 +#define MH_DEBUG_REG33_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG33_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16 +#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00 +#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000 +#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG33_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG33_MASK \ + (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG33_ROQ_MARK_d_MASK | \ + MH_DEBUG_REG33_ROQ_VALID_d_MASK | \ + MH_DEBUG_REG33_TC_MH_send_MASK | \ + MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG33_KILL_EFF1_MASK | \ + MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG33_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \ + (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + } mh_debug_reg33_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg33_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg33_t f; +} mh_debug_reg33_u; + + +/* + * MH_DEBUG_REG34 struct + */ + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000 + +#define MH_DEBUG_REG34_MASK \ + (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) + +#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \ + ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \ + (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \ + (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \ + (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)) + +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + } mh_debug_reg34_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + } mh_debug_reg34_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg34_t f; +} mh_debug_reg34_u; + + +/* + * MH_DEBUG_REG35 struct + */ + +#define MH_DEBUG_REG35_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27 + +#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5 + +#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010 +#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0 + +#define MH_DEBUG_REG35_MASK \ + (MH_DEBUG_REG35_TC_MH_send_MASK | \ + MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \ + MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_ADDR_0_MASK) + +#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \ + ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \ + (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \ + (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \ + (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)) + +#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + } mh_debug_reg35_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + } mh_debug_reg35_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg35_t f; +} mh_debug_reg35_u; + + +/* + * MH_DEBUG_REG36 struct + */ + +#define MH_DEBUG_REG36_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27 + +#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5 + +#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010 +#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0 + +#define MH_DEBUG_REG36_MASK \ + (MH_DEBUG_REG36_TC_MH_send_MASK | \ + MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \ + MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_ADDR_1_MASK) + +#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \ + ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \ + (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \ + (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \ + (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)) + +#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + } mh_debug_reg36_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + } mh_debug_reg36_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg36_t f; +} mh_debug_reg36_u; + + +/* + * MH_DEBUG_REG37 struct + */ + +#define MH_DEBUG_REG37_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27 + +#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5 + +#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010 +#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0 + +#define MH_DEBUG_REG37_MASK \ + (MH_DEBUG_REG37_TC_MH_send_MASK | \ + MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \ + MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_ADDR_2_MASK) + +#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \ + ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \ + (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \ + (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \ + (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)) + +#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + } mh_debug_reg37_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + } mh_debug_reg37_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg37_t f; +} mh_debug_reg37_u; + + +/* + * MH_DEBUG_REG38 struct + */ + +#define MH_DEBUG_REG38_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27 + +#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5 + +#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010 +#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0 + +#define MH_DEBUG_REG38_MASK \ + (MH_DEBUG_REG38_TC_MH_send_MASK | \ + MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \ + MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_ADDR_3_MASK) + +#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \ + ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \ + (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \ + (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \ + (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)) + +#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + } mh_debug_reg38_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + } mh_debug_reg38_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg38_t f; +} mh_debug_reg38_u; + + +/* + * MH_DEBUG_REG39 struct + */ + +#define MH_DEBUG_REG39_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27 + +#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5 + +#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010 +#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0 + +#define MH_DEBUG_REG39_MASK \ + (MH_DEBUG_REG39_TC_MH_send_MASK | \ + MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \ + MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_ADDR_4_MASK) + +#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \ + ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \ + (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \ + (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \ + (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)) + +#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + } mh_debug_reg39_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + } mh_debug_reg39_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg39_t f; +} mh_debug_reg39_u; + + +/* + * MH_DEBUG_REG40 struct + */ + +#define MH_DEBUG_REG40_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27 + +#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5 + +#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010 +#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG40_MASK \ + (MH_DEBUG_REG40_TC_MH_send_MASK | \ + MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \ + MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_ADDR_5_MASK) + +#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \ + ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \ + (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \ + (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \ + (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)) + +#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + } mh_debug_reg40_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + } mh_debug_reg40_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg40_t f; +} mh_debug_reg40_u; + + +/* + * MH_DEBUG_REG41 struct + */ + +#define MH_DEBUG_REG41_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27 + +#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5 + +#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010 +#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0 + +#define MH_DEBUG_REG41_MASK \ + (MH_DEBUG_REG41_TC_MH_send_MASK | \ + MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \ + MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_ADDR_6_MASK) + +#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \ + ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \ + (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \ + (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \ + (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)) + +#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + } mh_debug_reg41_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + } mh_debug_reg41_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg41_t f; +} mh_debug_reg41_u; + + +/* + * MH_DEBUG_REG42 struct + */ + +#define MH_DEBUG_REG42_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27 + +#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5 + +#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010 +#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0 + +#define MH_DEBUG_REG42_MASK \ + (MH_DEBUG_REG42_TC_MH_send_MASK | \ + MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \ + MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_ADDR_7_MASK) + +#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \ + ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \ + (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \ + (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \ + (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)) + +#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + } mh_debug_reg42_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + } mh_debug_reg42_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg42_t f; +} mh_debug_reg42_u; + + +/* + * MH_DEBUG_REG43 struct + */ + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_WE_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG43_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3 +#define MH_DEBUG_REG43_MMU_WE_SIZE 1 +#define MH_DEBUG_REG43_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_ID_SIZE 3 +#define MH_DEBUG_REG43_MMU_WRITE_SIZE 1 +#define MH_DEBUG_REG43_MMU_BLEN_SIZE 1 +#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_WDB_WE_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG43_ARB_WE_SHIFT 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3 +#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5 +#define MH_DEBUG_REG43_MMU_RTR_SHIFT 6 +#define MH_DEBUG_REG43_ARB_ID_q_SHIFT 7 +#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10 +#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13 +#define MH_DEBUG_REG43_MMU_WE_SHIFT 16 +#define MH_DEBUG_REG43_ARQ_RTR_SHIFT 17 +#define MH_DEBUG_REG43_MMU_ID_SHIFT 18 +#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21 +#define MH_DEBUG_REG43_MMU_BLEN_SHIFT 22 +#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24 +#define MH_DEBUG_REG43_WDB_WE_SHIFT 25 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG43_ARB_WE_MASK 0x00000002 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG43_ARB_RTR_q_MASK 0x00000008 +#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020 +#define MH_DEBUG_REG43_MMU_RTR_MASK 0x00000040 +#define MH_DEBUG_REG43_ARB_ID_q_MASK 0x00000380 +#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400 +#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000 +#define MH_DEBUG_REG43_MMU_WE_MASK 0x00010000 +#define MH_DEBUG_REG43_ARQ_RTR_MASK 0x00020000 +#define MH_DEBUG_REG43_MMU_ID_MASK 0x001c0000 +#define MH_DEBUG_REG43_MMU_WRITE_MASK 0x00200000 +#define MH_DEBUG_REG43_MMU_BLEN_MASK 0x00400000 +#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000 +#define MH_DEBUG_REG43_WDB_WE_MASK 0x02000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000 + +#define MH_DEBUG_REG43_MASK \ + (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \ + MH_DEBUG_REG43_ARB_WE_MASK | \ + MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \ + MH_DEBUG_REG43_ARB_RTR_q_MASK | \ + MH_DEBUG_REG43_ARB_REG_RTR_MASK | \ + MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \ + MH_DEBUG_REG43_MMU_RTR_MASK | \ + MH_DEBUG_REG43_ARB_ID_q_MASK | \ + MH_DEBUG_REG43_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG43_ARB_BLEN_q_MASK | \ + MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG43_MMU_WE_MASK | \ + MH_DEBUG_REG43_ARQ_RTR_MASK | \ + MH_DEBUG_REG43_MMU_ID_MASK | \ + MH_DEBUG_REG43_MMU_WRITE_MASK | \ + MH_DEBUG_REG43_MMU_BLEN_MASK | \ + MH_DEBUG_REG43_WBURST_IP_q_MASK | \ + MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG43_WDB_WE_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) + +#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \ + ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \ + (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \ + (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \ + (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \ + (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \ + (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \ + (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \ + (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \ + (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \ + (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \ + (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \ + (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \ + (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)) + +#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int : 4; + } mh_debug_reg43_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int : 4; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + } mh_debug_reg43_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg43_t f; +} mh_debug_reg43_u; + + +/* + * MH_DEBUG_REG44 struct + */ + +#define MH_DEBUG_REG44_ARB_WE_SIZE 1 +#define MH_DEBUG_REG44_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG44_ARB_VAD_q_SIZE 28 + +#define MH_DEBUG_REG44_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG44_ARB_ID_q_SHIFT 1 +#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4 + +#define MH_DEBUG_REG44_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG44_ARB_ID_q_MASK 0x0000000e +#define MH_DEBUG_REG44_ARB_VAD_q_MASK 0xfffffff0 + +#define MH_DEBUG_REG44_MASK \ + (MH_DEBUG_REG44_ARB_WE_MASK | \ + MH_DEBUG_REG44_ARB_ID_q_MASK | \ + MH_DEBUG_REG44_ARB_VAD_q_MASK) + +#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \ + ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \ + (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)) + +#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + } mh_debug_reg44_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + } mh_debug_reg44_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg44_t f; +} mh_debug_reg44_u; + + +/* + * MH_DEBUG_REG45 struct + */ + +#define MH_DEBUG_REG45_MMU_WE_SIZE 1 +#define MH_DEBUG_REG45_MMU_ID_SIZE 3 +#define MH_DEBUG_REG45_MMU_PAD_SIZE 28 + +#define MH_DEBUG_REG45_MMU_WE_SHIFT 0 +#define MH_DEBUG_REG45_MMU_ID_SHIFT 1 +#define MH_DEBUG_REG45_MMU_PAD_SHIFT 4 + +#define MH_DEBUG_REG45_MMU_WE_MASK 0x00000001 +#define MH_DEBUG_REG45_MMU_ID_MASK 0x0000000e +#define MH_DEBUG_REG45_MMU_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG45_MASK \ + (MH_DEBUG_REG45_MMU_WE_MASK | \ + MH_DEBUG_REG45_MMU_ID_MASK | \ + MH_DEBUG_REG45_MMU_PAD_MASK) + +#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \ + ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \ + (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \ + (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)) + +#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + } mh_debug_reg45_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + } mh_debug_reg45_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg45_t f; +} mh_debug_reg45_u; + + +/* + * MH_DEBUG_REG46 struct + */ + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WE_SIZE 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG46_ARB_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG46_WDB_WE_SHIFT 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4 +#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19 +#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG46_WDB_WE_MASK 0x00000002 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008 +#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0 +#define MH_DEBUG_REG46_ARB_WLAST_MASK 0x00001000 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000 +#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000 + +#define MH_DEBUG_REG46_MASK \ + (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG46_WDB_WE_MASK | \ + MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \ + MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \ + MH_DEBUG_REG46_ARB_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WID_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) + +#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \ + ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \ + (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \ + (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \ + (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \ + (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \ + (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \ + (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \ + (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \ + (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \ + (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)) + +#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + } mh_debug_reg46_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + } mh_debug_reg46_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg46_t f; +} mh_debug_reg46_u; + + +/* + * MH_DEBUG_REG47 struct + */ + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG47_MASK \ + (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) + +#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \ + ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)) + +#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg47_t f; +} mh_debug_reg47_u; + + +/* + * MH_DEBUG_REG48 struct + */ + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG48_MASK \ + (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) + +#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \ + ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)) + +#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg48_t f; +} mh_debug_reg48_u; + + +/* + * MH_DEBUG_REG49 struct + */ + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RVALID_q_SIZE 1 +#define MH_DEBUG_REG49_RREADY_q_SIZE 1 +#define MH_DEBUG_REG49_RLAST_q_SIZE 1 +#define MH_DEBUG_REG49_BVALID_q_SIZE 1 +#define MH_DEBUG_REG49_BREADY_q_SIZE 1 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14 +#define MH_DEBUG_REG49_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG49_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG49_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG49_BVALID_q_SHIFT 18 +#define MH_DEBUG_REG49_BREADY_q_SHIFT 19 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000 +#define MH_DEBUG_REG49_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG49_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG49_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG49_BVALID_q_MASK 0x00040000 +#define MH_DEBUG_REG49_BREADY_q_MASK 0x00080000 + +#define MH_DEBUG_REG49_MASK \ + (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \ + MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \ + MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \ + MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RVALID_q_MASK | \ + MH_DEBUG_REG49_RREADY_q_MASK | \ + MH_DEBUG_REG49_RLAST_q_MASK | \ + MH_DEBUG_REG49_BVALID_q_MASK | \ + MH_DEBUG_REG49_BREADY_q_MASK) + +#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \ + ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \ + (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \ + (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \ + (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \ + (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \ + (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)) + +#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT) + +#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int : 12; + } mh_debug_reg49_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int : 12; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + } mh_debug_reg49_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg49_t f; +} mh_debug_reg49_u; + + +/* + * MH_DEBUG_REG50 struct + */ + +#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_RID_SIZE 3 +#define MH_DEBUG_REG50_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG50_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3 +#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4 +#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5 +#define MH_DEBUG_REG50_RDC_RID_SHIFT 6 +#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9 +#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29 + +#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008 +#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010 +#define MH_DEBUG_REG50_RDC_VALID_MASK 0x00000020 +#define MH_DEBUG_REG50_RDC_RID_MASK 0x000001c0 +#define MH_DEBUG_REG50_RDC_RLAST_MASK 0x00000200 +#define MH_DEBUG_REG50_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000 +#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000 + +#define MH_DEBUG_REG50_MASK \ + (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG50_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG50_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG50_RDC_VALID_MASK | \ + MH_DEBUG_REG50_RDC_RID_MASK | \ + MH_DEBUG_REG50_RDC_RLAST_MASK | \ + MH_DEBUG_REG50_RDC_RRESP_MASK | \ + MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \ + MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \ + MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \ + MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \ + MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \ + ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \ + (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \ + (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \ + (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \ + (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \ + (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + } mh_debug_reg50_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + } mh_debug_reg50_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg50_t f; +} mh_debug_reg50_u; + + +/* + * MH_DEBUG_REG51 struct + */ + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff + +#define MH_DEBUG_REG51_MASK \ + (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) + +#define MH_DEBUG_REG51(rf_mmu_page_fault) \ + ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)) + +#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg51_t f; +} mh_debug_reg51_u; + + +/* + * MH_DEBUG_REG52 struct + */ + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2 +#define MH_DEBUG_REG52_ARB_WE_SIZE 1 +#define MH_DEBUG_REG52_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22 +#define MH_DEBUG_REG52_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG52_client_behavior_q_SIZE 2 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0 +#define MH_DEBUG_REG52_ARB_WE_SHIFT 2 +#define MH_DEBUG_REG52_MMU_RTR_SHIFT 3 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4 +#define MH_DEBUG_REG52_ARB_ID_q_SHIFT 26 +#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29 +#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003 +#define MH_DEBUG_REG52_ARB_WE_MASK 0x00000004 +#define MH_DEBUG_REG52_MMU_RTR_MASK 0x00000008 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0 +#define MH_DEBUG_REG52_ARB_ID_q_MASK 0x1c000000 +#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000 +#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000 + +#define MH_DEBUG_REG52_MASK \ + (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \ + MH_DEBUG_REG52_ARB_WE_MASK | \ + MH_DEBUG_REG52_MMU_RTR_MASK | \ + MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \ + MH_DEBUG_REG52_ARB_ID_q_MASK | \ + MH_DEBUG_REG52_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG52_client_behavior_q_MASK) + +#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \ + ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \ + (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \ + (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)) + +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + } mh_debug_reg52_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + } mh_debug_reg52_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg52_t f; +} mh_debug_reg52_u; + + +/* + * MH_DEBUG_REG53 struct + */ + +#define MH_DEBUG_REG53_stage1_valid_SIZE 1 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG53_tag_match_q_SIZE 1 +#define MH_DEBUG_REG53_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG53_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG53_MMU_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16 + +#define MH_DEBUG_REG53_stage1_valid_SHIFT 0 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2 +#define MH_DEBUG_REG53_tag_match_q_SHIFT 3 +#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4 +#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5 +#define MH_DEBUG_REG53_MMU_MISS_SHIFT 6 +#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8 +#define MH_DEBUG_REG53_MMU_HIT_SHIFT 9 +#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16 + +#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002 +#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004 +#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008 +#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010 +#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020 +#define MH_DEBUG_REG53_MMU_MISS_MASK 0x00000040 +#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100 +#define MH_DEBUG_REG53_MMU_HIT_MASK 0x00000200 +#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000 + +#define MH_DEBUG_REG53_MASK \ + (MH_DEBUG_REG53_stage1_valid_MASK | \ + MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG53_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG53_tag_match_q_MASK | \ + MH_DEBUG_REG53_tag_miss_q_MASK | \ + MH_DEBUG_REG53_va_in_range_q_MASK | \ + MH_DEBUG_REG53_MMU_MISS_MASK | \ + MH_DEBUG_REG53_MMU_READ_MISS_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \ + MH_DEBUG_REG53_MMU_HIT_MASK | \ + MH_DEBUG_REG53_MMU_READ_HIT_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \ + MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) + +#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \ + ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \ + (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \ + (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \ + (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \ + (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \ + (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \ + (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \ + (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \ + (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \ + (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \ + (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \ + (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)) + +#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + } mh_debug_reg53_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + } mh_debug_reg53_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg53_t f; +} mh_debug_reg53_u; + + +/* + * MH_DEBUG_REG54 struct + */ + +#define MH_DEBUG_REG54_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG54_MMU_WE_SIZE 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1 +#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG54_stage1_valid_SIZE 1 +#define MH_DEBUG_REG54_stage2_valid_SIZE 1 +#define MH_DEBUG_REG54_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG54_tag_match_q_SIZE 1 +#define MH_DEBUG_REG54_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG54_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1 +#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16 + +#define MH_DEBUG_REG54_ARQ_RTR_SHIFT 0 +#define MH_DEBUG_REG54_MMU_WE_SHIFT 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5 +#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6 +#define MH_DEBUG_REG54_stage1_valid_SHIFT 7 +#define MH_DEBUG_REG54_stage2_valid_SHIFT 8 +#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11 +#define MH_DEBUG_REG54_tag_match_q_SHIFT 12 +#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13 +#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15 +#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16 + +#define MH_DEBUG_REG54_ARQ_RTR_MASK 0x00000001 +#define MH_DEBUG_REG54_MMU_WE_MASK 0x00000002 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020 +#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040 +#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080 +#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100 +#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800 +#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000 +#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000 +#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000 +#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000 + +#define MH_DEBUG_REG54_MASK \ + (MH_DEBUG_REG54_ARQ_RTR_MASK | \ + MH_DEBUG_REG54_MMU_WE_MASK | \ + MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \ + MH_DEBUG_REG54_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG54_stage1_valid_MASK | \ + MH_DEBUG_REG54_stage2_valid_MASK | \ + MH_DEBUG_REG54_client_behavior_q_MASK | \ + MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG54_tag_match_q_MASK | \ + MH_DEBUG_REG54_tag_miss_q_MASK | \ + MH_DEBUG_REG54_va_in_range_q_MASK | \ + MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_MASK) + +#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \ + ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \ + (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \ + (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \ + (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \ + (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \ + (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \ + (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)) + +#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + } mh_debug_reg54_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + } mh_debug_reg54_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg54_t f; +} mh_debug_reg54_u; + + +/* + * MH_DEBUG_REG55 struct + */ + +#define MH_DEBUG_REG55_TAG0_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG55_TAG1_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1 + +#define MH_DEBUG_REG55_TAG0_VA_SHIFT 0 +#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG55_TAG1_VA_SHIFT 16 +#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29 + +#define MH_DEBUG_REG55_TAG0_VA_MASK 0x00001fff +#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000 +#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG55_TAG1_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000 + +#define MH_DEBUG_REG55_MASK \ + (MH_DEBUG_REG55_TAG0_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_0_MASK | \ + MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG55_TAG1_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_1_MASK) + +#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \ + ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \ + (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \ + (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \ + (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \ + (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)) + +#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int : 2; + } mh_debug_reg55_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int : 2; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + } mh_debug_reg55_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg55_t f; +} mh_debug_reg55_u; + + +/* + * MH_DEBUG_REG56 struct + */ + +#define MH_DEBUG_REG56_TAG2_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG56_TAG3_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1 + +#define MH_DEBUG_REG56_TAG2_VA_SHIFT 0 +#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG56_TAG3_VA_SHIFT 16 +#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29 + +#define MH_DEBUG_REG56_TAG2_VA_MASK 0x00001fff +#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000 +#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG56_TAG3_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000 + +#define MH_DEBUG_REG56_MASK \ + (MH_DEBUG_REG56_TAG2_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_2_MASK | \ + MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG56_TAG3_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_3_MASK) + +#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \ + ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \ + (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \ + (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \ + (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \ + (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)) + +#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int : 2; + } mh_debug_reg56_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int : 2; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + } mh_debug_reg56_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg56_t f; +} mh_debug_reg56_u; + + +/* + * MH_DEBUG_REG57 struct + */ + +#define MH_DEBUG_REG57_TAG4_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG57_TAG5_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1 + +#define MH_DEBUG_REG57_TAG4_VA_SHIFT 0 +#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG57_TAG5_VA_SHIFT 16 +#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29 + +#define MH_DEBUG_REG57_TAG4_VA_MASK 0x00001fff +#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000 +#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG57_TAG5_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000 + +#define MH_DEBUG_REG57_MASK \ + (MH_DEBUG_REG57_TAG4_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_4_MASK | \ + MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG57_TAG5_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_5_MASK) + +#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \ + ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \ + (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \ + (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \ + (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \ + (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)) + +#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int : 2; + } mh_debug_reg57_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int : 2; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + } mh_debug_reg57_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg57_t f; +} mh_debug_reg57_u; + + +/* + * MH_DEBUG_REG58 struct + */ + +#define MH_DEBUG_REG58_TAG6_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG58_TAG7_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1 + +#define MH_DEBUG_REG58_TAG6_VA_SHIFT 0 +#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG58_TAG7_VA_SHIFT 16 +#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29 + +#define MH_DEBUG_REG58_TAG6_VA_MASK 0x00001fff +#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000 +#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG58_TAG7_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000 + +#define MH_DEBUG_REG58_MASK \ + (MH_DEBUG_REG58_TAG6_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_6_MASK | \ + MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG58_TAG7_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_7_MASK) + +#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \ + ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \ + (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \ + (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \ + (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \ + (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)) + +#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int : 2; + } mh_debug_reg58_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int : 2; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + } mh_debug_reg58_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg58_t f; +} mh_debug_reg58_u; + + +/* + * MH_DEBUG_REG59 struct + */ + +#define MH_DEBUG_REG59_TAG8_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG59_TAG9_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1 + +#define MH_DEBUG_REG59_TAG8_VA_SHIFT 0 +#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG59_TAG9_VA_SHIFT 16 +#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29 + +#define MH_DEBUG_REG59_TAG8_VA_MASK 0x00001fff +#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000 +#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG59_TAG9_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000 + +#define MH_DEBUG_REG59_MASK \ + (MH_DEBUG_REG59_TAG8_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_8_MASK | \ + MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG59_TAG9_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_9_MASK) + +#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \ + ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \ + (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \ + (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \ + (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \ + (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)) + +#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int : 2; + } mh_debug_reg59_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int : 2; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + } mh_debug_reg59_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg59_t f; +} mh_debug_reg59_u; + + +/* + * MH_DEBUG_REG60 struct + */ + +#define MH_DEBUG_REG60_TAG10_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG60_TAG11_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1 + +#define MH_DEBUG_REG60_TAG10_VA_SHIFT 0 +#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG60_TAG11_VA_SHIFT 16 +#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29 + +#define MH_DEBUG_REG60_TAG10_VA_MASK 0x00001fff +#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000 +#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG60_TAG11_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000 + +#define MH_DEBUG_REG60_MASK \ + (MH_DEBUG_REG60_TAG10_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_10_MASK | \ + MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG60_TAG11_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_11_MASK) + +#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \ + ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \ + (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \ + (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \ + (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \ + (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)) + +#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int : 2; + } mh_debug_reg60_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int : 2; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + } mh_debug_reg60_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg60_t f; +} mh_debug_reg60_u; + + +/* + * MH_DEBUG_REG61 struct + */ + +#define MH_DEBUG_REG61_TAG12_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG61_TAG13_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1 + +#define MH_DEBUG_REG61_TAG12_VA_SHIFT 0 +#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG61_TAG13_VA_SHIFT 16 +#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29 + +#define MH_DEBUG_REG61_TAG12_VA_MASK 0x00001fff +#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000 +#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG61_TAG13_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000 + +#define MH_DEBUG_REG61_MASK \ + (MH_DEBUG_REG61_TAG12_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_12_MASK | \ + MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG61_TAG13_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_13_MASK) + +#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \ + ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \ + (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \ + (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \ + (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \ + (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)) + +#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int : 2; + } mh_debug_reg61_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int : 2; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + } mh_debug_reg61_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg61_t f; +} mh_debug_reg61_u; + + +/* + * MH_DEBUG_REG62 struct + */ + +#define MH_DEBUG_REG62_TAG14_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG62_TAG15_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1 + +#define MH_DEBUG_REG62_TAG14_VA_SHIFT 0 +#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG62_TAG15_VA_SHIFT 16 +#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29 + +#define MH_DEBUG_REG62_TAG14_VA_MASK 0x00001fff +#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000 +#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG62_TAG15_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000 + +#define MH_DEBUG_REG62_MASK \ + (MH_DEBUG_REG62_TAG14_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_14_MASK | \ + MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG62_TAG15_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_15_MASK) + +#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \ + ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \ + (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \ + (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \ + (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \ + (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)) + +#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int : 2; + } mh_debug_reg62_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int : 2; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + } mh_debug_reg62_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg62_t f; +} mh_debug_reg62_u; + + +/* + * MH_DEBUG_REG63 struct + */ + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG63_MASK \ + (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG63(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \ + ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \ + mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg63_t f; +} mh_debug_reg63_u; + + +/* + * MH_MMU_CONFIG struct + */ + +#define MH_MMU_CONFIG_MMU_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_RESERVED1_SIZE 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2 + +#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1 +#define MH_MMU_CONFIG_RESERVED1_SHIFT 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24 + +#define MH_MMU_CONFIG_MMU_ENABLE_MASK 0x00000001 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002 +#define MH_MMU_CONFIG_RESERVED1_MASK 0x0000000c +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000 + +#define MH_MMU_CONFIG_MASK \ + (MH_MMU_CONFIG_MMU_ENABLE_MASK | \ + MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \ + MH_MMU_CONFIG_RESERVED1_MASK | \ + MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) + +#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \ + ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \ + (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \ + (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \ + (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \ + (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \ + (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)) + +#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int : 6; + } mh_mmu_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int : 6; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + } mh_mmu_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_config_t f; +} mh_mmu_config_u; + + +/* + * MH_MMU_VA_RANGE struct + */ + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12 +#define MH_MMU_VA_RANGE_VA_BASE_SIZE 20 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0 +#define MH_MMU_VA_RANGE_VA_BASE_SHIFT 12 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff +#define MH_MMU_VA_RANGE_VA_BASE_MASK 0xfffff000 + +#define MH_MMU_VA_RANGE_MASK \ + (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \ + MH_MMU_VA_RANGE_VA_BASE_MASK) + +#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \ + ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \ + (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)) + +#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + } mh_mmu_va_range_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + } mh_mmu_va_range_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_va_range_t f; +} mh_mmu_va_range_u; + + +/* + * MH_MMU_PT_BASE struct + */ + +#define MH_MMU_PT_BASE_PT_BASE_SIZE 20 + +#define MH_MMU_PT_BASE_PT_BASE_SHIFT 12 + +#define MH_MMU_PT_BASE_PT_BASE_MASK 0xfffff000 + +#define MH_MMU_PT_BASE_MASK \ + (MH_MMU_PT_BASE_PT_BASE_MASK) + +#define MH_MMU_PT_BASE(pt_base) \ + ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)) + +#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \ + ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \ + mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int : 12; + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + } mh_mmu_pt_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + unsigned int : 12; + } mh_mmu_pt_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_pt_base_t f; +} mh_mmu_pt_base_u; + + +/* + * MH_MMU_PAGE_FAULT struct + */ + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE 3 +#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE 20 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4 +#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11 +#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001 +#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c +#define MH_MMU_PAGE_FAULT_AXI_ID_MASK 0x00000070 +#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800 +#define MH_MMU_PAGE_FAULT_REQ_VA_MASK 0xfffff000 + +#define MH_MMU_PAGE_FAULT_MASK \ + (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \ + MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \ + MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \ + MH_MMU_PAGE_FAULT_AXI_ID_MASK | \ + MH_MMU_PAGE_FAULT_RESERVED1_MASK | \ + MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_REQ_VA_MASK) + +#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \ + ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \ + (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \ + (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \ + (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \ + (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \ + (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \ + (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \ + (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)) + +#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + } mh_mmu_page_fault_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + } mh_mmu_page_fault_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_page_fault_t f; +} mh_mmu_page_fault_u; + + +/* + * MH_MMU_TRAN_ERROR struct + */ + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0 + +#define MH_MMU_TRAN_ERROR_MASK \ + (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) + +#define MH_MMU_TRAN_ERROR(tran_error) \ + ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)) + +#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \ + ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \ + mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int : 5; + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + } mh_mmu_tran_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + unsigned int : 5; + } mh_mmu_tran_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_tran_error_t f; +} mh_mmu_tran_error_u; + + +/* + * MH_MMU_INVALIDATE struct + */ + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002 + +#define MH_MMU_INVALIDATE_MASK \ + (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) + +#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \ + ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)) + +#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int : 30; + } mh_mmu_invalidate_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int : 30; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + } mh_mmu_invalidate_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_invalidate_t f; +} mh_mmu_invalidate_u; + + +/* + * MH_MMU_MPU_BASE struct + */ + +#define MH_MMU_MPU_BASE_MPU_BASE_SIZE 20 + +#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12 + +#define MH_MMU_MPU_BASE_MPU_BASE_MASK 0xfffff000 + +#define MH_MMU_MPU_BASE_MASK \ + (MH_MMU_MPU_BASE_MPU_BASE_MASK) + +#define MH_MMU_MPU_BASE(mpu_base) \ + ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)) + +#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \ + ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \ + mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int : 12; + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + } mh_mmu_mpu_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + unsigned int : 12; + } mh_mmu_mpu_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_base_t f; +} mh_mmu_mpu_base_u; + + +/* + * MH_MMU_MPU_END struct + */ + +#define MH_MMU_MPU_END_MPU_END_SIZE 20 + +#define MH_MMU_MPU_END_MPU_END_SHIFT 12 + +#define MH_MMU_MPU_END_MPU_END_MASK 0xfffff000 + +#define MH_MMU_MPU_END_MASK \ + (MH_MMU_MPU_END_MPU_END_MASK) + +#define MH_MMU_MPU_END(mpu_end) \ + ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)) + +#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \ + ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT) + +#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \ + mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int : 12; + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + } mh_mmu_mpu_end_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + unsigned int : 12; + } mh_mmu_mpu_end_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_end_t f; +} mh_mmu_mpu_end_u; + + +#endif + + +#if !defined (_PA_FIDDLE_H) +#define _PA_FIDDLE_H + +/***************************************************************************************************************** + * + * pa_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * PA_CL_VPORT_XSCALE struct + */ + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_XSCALE_MASK \ + (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) + +#define PA_CL_VPORT_XSCALE(vport_xscale) \ + ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)) + +#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \ + ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \ + pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xscale_t f; +} pa_cl_vport_xscale_u; + + +/* + * PA_CL_VPORT_XOFFSET struct + */ + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_XOFFSET_MASK \ + (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) + +#define PA_CL_VPORT_XOFFSET(vport_xoffset) \ + ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)) + +#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \ + ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \ + pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xoffset_t f; +} pa_cl_vport_xoffset_u; + + +/* + * PA_CL_VPORT_YSCALE struct + */ + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_YSCALE_MASK \ + (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) + +#define PA_CL_VPORT_YSCALE(vport_yscale) \ + ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)) + +#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \ + ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \ + pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yscale_t f; +} pa_cl_vport_yscale_u; + + +/* + * PA_CL_VPORT_YOFFSET struct + */ + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_YOFFSET_MASK \ + (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) + +#define PA_CL_VPORT_YOFFSET(vport_yoffset) \ + ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)) + +#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \ + ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \ + pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yoffset_t f; +} pa_cl_vport_yoffset_u; + + +/* + * PA_CL_VPORT_ZSCALE struct + */ + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_ZSCALE_MASK \ + (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) + +#define PA_CL_VPORT_ZSCALE(vport_zscale) \ + ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)) + +#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \ + ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \ + pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zscale_t f; +} pa_cl_vport_zscale_u; + + +/* + * PA_CL_VPORT_ZOFFSET struct + */ + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_ZOFFSET_MASK \ + (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) + +#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \ + ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)) + +#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \ + ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \ + pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zoffset_t f; +} pa_cl_vport_zoffset_u; + + +/* + * PA_CL_VTE_CNTL struct + */ + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK 0x00000200 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800 + +#define PA_CL_VTE_CNTL_MASK \ + (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \ + PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) + +#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \ + ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \ + (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \ + (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \ + (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \ + (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \ + (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \ + (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \ + (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \ + (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \ + (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)) + +#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int : 2; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int : 20; + } pa_cl_vte_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int : 20; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int : 2; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + } pa_cl_vte_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vte_cntl_t f; +} pa_cl_vte_cntl_u; + + +/* + * PA_CL_CLIP_CNTL struct + */ + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000 + +#define PA_CL_CLIP_CNTL_MASK \ + (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \ + PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \ + PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \ + PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \ + PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \ + PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) + +#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \ + ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \ + (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \ + (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \ + (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \ + (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \ + (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \ + (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \ + (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)) + +#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 16; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 1; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int : 7; + } pa_cl_clip_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 7; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int : 1; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 16; + } pa_cl_clip_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_clip_cntl_t f; +} pa_cl_clip_cntl_u; + + +/* + * PA_CL_GB_VERT_CLIP_ADJ struct + */ + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_CLIP_ADJ_MASK \ + (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \ + ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \ + pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_clip_adj_t f; +} pa_cl_gb_vert_clip_adj_u; + + +/* + * PA_CL_GB_VERT_DISC_ADJ struct + */ + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_DISC_ADJ_MASK \ + (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \ + ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \ + pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_disc_adj_t f; +} pa_cl_gb_vert_disc_adj_u; + + +/* + * PA_CL_GB_HORZ_CLIP_ADJ struct + */ + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \ + (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \ + ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \ + pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_clip_adj_t f; +} pa_cl_gb_horz_clip_adj_u; + + +/* + * PA_CL_GB_HORZ_DISC_ADJ struct + */ + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_DISC_ADJ_MASK \ + (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \ + ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \ + pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_disc_adj_t f; +} pa_cl_gb_horz_disc_adj_u; + + +/* + * PA_CL_ENHANCE struct + */ + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0 +#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001 +#define PA_CL_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_CL_ENHANCE_MASK \ + (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \ + PA_CL_ENHANCE_ECO_SPARE3_MASK | \ + PA_CL_ENHANCE_ECO_SPARE2_MASK | \ + PA_CL_ENHANCE_ECO_SPARE1_MASK | \ + PA_CL_ENHANCE_ECO_SPARE0_MASK) + +#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \ + (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + unsigned int : 27; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + } pa_cl_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 27; + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + } pa_cl_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_enhance_t f; +} pa_cl_enhance_u; + + +/* + * PA_SC_ENHANCE struct + */ + +#define PA_SC_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_SC_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_SC_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_SC_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_SC_ENHANCE_MASK \ + (PA_SC_ENHANCE_ECO_SPARE3_MASK | \ + PA_SC_ENHANCE_ECO_SPARE2_MASK | \ + PA_SC_ENHANCE_ECO_SPARE1_MASK | \ + PA_SC_ENHANCE_ECO_SPARE0_MASK) + +#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int : 28; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + } pa_sc_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 28; + } pa_sc_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_enhance_t f; +} pa_sc_enhance_u; + + +/* + * PA_SU_VTX_CNTL struct + */ + +#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1 +#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2 +#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0 +#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1 +#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001 +#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006 +#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038 + +#define PA_SU_VTX_CNTL_MASK \ + (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \ + PA_SU_VTX_CNTL_ROUND_MODE_MASK | \ + PA_SU_VTX_CNTL_QUANT_MODE_MASK) + +#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \ + ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \ + (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \ + (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)) + +#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int : 26; + } pa_su_vtx_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int : 26; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + } pa_su_vtx_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_vtx_cntl_t f; +} pa_su_vtx_cntl_u; + + +/* + * PA_SU_POINT_SIZE struct + */ + +#define PA_SU_POINT_SIZE_HEIGHT_SIZE 16 +#define PA_SU_POINT_SIZE_WIDTH_SIZE 16 + +#define PA_SU_POINT_SIZE_HEIGHT_SHIFT 0 +#define PA_SU_POINT_SIZE_WIDTH_SHIFT 16 + +#define PA_SU_POINT_SIZE_HEIGHT_MASK 0x0000ffff +#define PA_SU_POINT_SIZE_WIDTH_MASK 0xffff0000 + +#define PA_SU_POINT_SIZE_MASK \ + (PA_SU_POINT_SIZE_HEIGHT_MASK | \ + PA_SU_POINT_SIZE_WIDTH_MASK) + +#define PA_SU_POINT_SIZE(height, width) \ + ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \ + (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)) + +#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + } pa_su_point_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + } pa_su_point_size_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_size_t f; +} pa_su_point_size_u; + + +/* + * PA_SU_POINT_MINMAX struct + */ + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff +#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000 + +#define PA_SU_POINT_MINMAX_MASK \ + (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \ + PA_SU_POINT_MINMAX_MAX_SIZE_MASK) + +#define PA_SU_POINT_MINMAX(min_size, max_size) \ + ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \ + (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)) + +#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + } pa_su_point_minmax_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + } pa_su_point_minmax_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_minmax_t f; +} pa_su_point_minmax_u; + + +/* + * PA_SU_LINE_CNTL struct + */ + +#define PA_SU_LINE_CNTL_WIDTH_SIZE 16 + +#define PA_SU_LINE_CNTL_WIDTH_SHIFT 0 + +#define PA_SU_LINE_CNTL_WIDTH_MASK 0x0000ffff + +#define PA_SU_LINE_CNTL_MASK \ + (PA_SU_LINE_CNTL_WIDTH_MASK) + +#define PA_SU_LINE_CNTL(width) \ + ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT)) + +#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \ + ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \ + pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + unsigned int : 16; + } pa_su_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int : 16; + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + } pa_su_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_line_cntl_t f; +} pa_su_line_cntl_u; + + +/* + * PA_SU_FACE_DATA struct + */ + +#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27 + +#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5 + +#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0 + +#define PA_SU_FACE_DATA_MASK \ + (PA_SU_FACE_DATA_BASE_ADDR_MASK) + +#define PA_SU_FACE_DATA(base_addr) \ + ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)) + +#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \ + ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \ + pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int : 5; + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + } pa_su_face_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + unsigned int : 5; + } pa_su_face_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_face_data_t f; +} pa_su_face_data_u; + + +/* + * PA_SU_SC_MODE_CNTL struct + */ + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1 +#define PA_SU_SC_MODE_CNTL_FACE_SHIFT 2 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002 +#define PA_SU_SC_MODE_CNTL_FACE_MASK 0x00000004 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000 + +#define PA_SU_SC_MODE_CNTL_MASK \ + (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \ + PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \ + PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \ + PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \ + PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \ + PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) + +#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, zero_area_faceness, face_kill_enable, face_write_enable) \ + ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \ + (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \ + (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \ + (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \ + (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \ + (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \ + (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \ + (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \ + (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \ + (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \ + (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \ + (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \ + (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \ + (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \ + (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \ + (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \ + (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \ + (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \ + (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \ + (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \ + (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)) + +#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int : 1; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int : 1; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int : 2; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + } pa_su_sc_mode_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int : 2; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int : 1; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int : 1; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + } pa_su_sc_mode_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_sc_mode_cntl_t f; +} pa_su_sc_mode_cntl_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \ + (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \ + ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \ + pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_scale_t f; +} pa_su_poly_offset_front_scale_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \ + ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \ + pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_offset_t f; +} pa_su_poly_offset_front_offset_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \ + (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \ + ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \ + pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_scale_t f; +} pa_su_poly_offset_back_scale_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \ + ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \ + pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_offset_t f; +} pa_su_poly_offset_back_offset_u; + + +/* + * PA_SU_PERFCOUNTER0_SELECT struct + */ + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER0_SELECT_MASK \ + (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \ + ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \ + pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_select_t f; +} pa_su_perfcounter0_select_u; + + +/* + * PA_SU_PERFCOUNTER1_SELECT struct + */ + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER1_SELECT_MASK \ + (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \ + ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \ + pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_select_t f; +} pa_su_perfcounter1_select_u; + + +/* + * PA_SU_PERFCOUNTER2_SELECT struct + */ + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER2_SELECT_MASK \ + (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \ + ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \ + pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_select_t f; +} pa_su_perfcounter2_select_u; + + +/* + * PA_SU_PERFCOUNTER3_SELECT struct + */ + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER3_SELECT_MASK \ + (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \ + ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \ + pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_select_t f; +} pa_su_perfcounter3_select_u; + + +/* + * PA_SU_PERFCOUNTER0_LOW struct + */ + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER0_LOW_MASK \ + (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \ + ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \ + pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_low_t f; +} pa_su_perfcounter0_low_u; + + +/* + * PA_SU_PERFCOUNTER0_HI struct + */ + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER0_HI_MASK \ + (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \ + ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \ + pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_hi_t f; +} pa_su_perfcounter0_hi_u; + + +/* + * PA_SU_PERFCOUNTER1_LOW struct + */ + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER1_LOW_MASK \ + (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \ + ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \ + pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_low_t f; +} pa_su_perfcounter1_low_u; + + +/* + * PA_SU_PERFCOUNTER1_HI struct + */ + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER1_HI_MASK \ + (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \ + ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \ + pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_hi_t f; +} pa_su_perfcounter1_hi_u; + + +/* + * PA_SU_PERFCOUNTER2_LOW struct + */ + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER2_LOW_MASK \ + (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \ + ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \ + pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_low_t f; +} pa_su_perfcounter2_low_u; + + +/* + * PA_SU_PERFCOUNTER2_HI struct + */ + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER2_HI_MASK \ + (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \ + ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \ + pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_hi_t f; +} pa_su_perfcounter2_hi_u; + + +/* + * PA_SU_PERFCOUNTER3_LOW struct + */ + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER3_LOW_MASK \ + (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \ + ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \ + pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_low_t f; +} pa_su_perfcounter3_low_u; + + +/* + * PA_SU_PERFCOUNTER3_HI struct + */ + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER3_HI_MASK \ + (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \ + ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \ + pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_hi_t f; +} pa_su_perfcounter3_hi_u; + + +/* + * PA_SC_WINDOW_OFFSET struct + */ + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000 + +#define PA_SC_WINDOW_OFFSET_MASK \ + (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \ + PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) + +#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \ + ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \ + (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)) + +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + } pa_sc_window_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + } pa_sc_window_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_offset_t f; +} pa_sc_window_offset_u; + + +/* + * PA_SC_AA_CONFIG struct + */ + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000 + +#define PA_SC_AA_CONFIG_MASK \ + (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \ + PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) + +#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \ + ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \ + (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)) + +#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + unsigned int : 10; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 15; + } pa_sc_aa_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int : 15; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 10; + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + } pa_sc_aa_config_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_config_t f; +} pa_sc_aa_config_u; + + +/* + * PA_SC_AA_MASK struct + */ + +#define PA_SC_AA_MASK_AA_MASK_SIZE 16 + +#define PA_SC_AA_MASK_AA_MASK_SHIFT 0 + +#define PA_SC_AA_MASK_AA_MASK_MASK 0x0000ffff + +#define PA_SC_AA_MASK_MASK \ + (PA_SC_AA_MASK_AA_MASK_MASK) + +#define PA_SC_AA_MASK(aa_mask) \ + ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)) + +#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \ + ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT) + +#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \ + pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + unsigned int : 16; + } pa_sc_aa_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int : 16; + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + } pa_sc_aa_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_mask_t f; +} pa_sc_aa_mask_u; + + +/* + * PA_SC_LINE_STIPPLE struct + */ + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000 + +#define PA_SC_LINE_STIPPLE_MASK \ + (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \ + PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \ + PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \ + PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) + +#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \ + ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \ + (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \ + (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \ + (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)) + +#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int : 4; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int : 1; + } pa_sc_line_stipple_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int : 1; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int : 4; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + } pa_sc_line_stipple_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_t f; +} pa_sc_line_stipple_u; + + +/* + * PA_SC_LINE_CNTL struct + */ + +#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1 + +#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10 + +#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200 +#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400 + +#define PA_SC_LINE_CNTL_MASK \ + (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \ + PA_SC_LINE_CNTL_LAST_PIXEL_MASK) + +#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \ + ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \ + (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \ + (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \ + (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)) + +#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int : 21; + } pa_sc_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int : 21; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + } pa_sc_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_cntl_t f; +} pa_sc_line_cntl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_TL struct + */ + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000 + +#define PA_SC_WINDOW_SCISSOR_TL_MASK \ + (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) + +#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \ + ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \ + (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + unsigned int : 2; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + } pa_sc_window_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 2; + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + } pa_sc_window_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_tl_t f; +} pa_sc_window_scissor_tl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_BR struct + */ + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000 + +#define PA_SC_WINDOW_SCISSOR_BR_MASK \ + (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \ + PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + } pa_sc_window_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + } pa_sc_window_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_br_t f; +} pa_sc_window_scissor_br_u; + + +/* + * PA_SC_SCREEN_SCISSOR_TL struct + */ + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_TL_MASK \ + (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \ + PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \ + ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + } pa_sc_screen_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_tl_t f; +} pa_sc_screen_scissor_tl_u; + + +/* + * PA_SC_SCREEN_SCISSOR_BR struct + */ + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_BR_MASK \ + (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \ + PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + } pa_sc_screen_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_br_t f; +} pa_sc_screen_scissor_br_u; + + +/* + * PA_SC_VIZ_QUERY struct + */ + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080 + +#define PA_SC_VIZ_QUERY_MASK \ + (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \ + PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \ + PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) + +#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \ + ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \ + (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \ + (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)) + +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int : 1; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 24; + } pa_sc_viz_query_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int : 24; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 1; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + } pa_sc_viz_query_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_t f; +} pa_sc_viz_query_u; + + +/* + * PA_SC_VIZ_QUERY_STATUS struct + */ + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff + +#define PA_SC_VIZ_QUERY_STATUS_MASK \ + (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) + +#define PA_SC_VIZ_QUERY_STATUS(status_bits) \ + ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)) + +#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \ + ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \ + pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_status_t f; +} pa_sc_viz_query_status_u; + + +/* + * PA_SC_LINE_STIPPLE_STATE struct + */ + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00 + +#define PA_SC_LINE_STIPPLE_STATE_MASK \ + (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \ + PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) + +#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \ + ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \ + (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)) + +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + unsigned int : 4; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 16; + } pa_sc_line_stipple_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int : 16; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 4; + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + } pa_sc_line_stipple_state_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_state_t f; +} pa_sc_line_stipple_state_u; + + +/* + * PA_SC_PERFCOUNTER0_SELECT struct + */ + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SC_PERFCOUNTER0_SELECT_MASK \ + (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \ + ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \ + pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_sc_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_sc_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_select_t f; +} pa_sc_perfcounter0_select_u; + + +/* + * PA_SC_PERFCOUNTER0_LOW struct + */ + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SC_PERFCOUNTER0_LOW_MASK \ + (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \ + ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \ + pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_low_t f; +} pa_sc_perfcounter0_low_u; + + +/* + * PA_SC_PERFCOUNTER0_HI struct + */ + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SC_PERFCOUNTER0_HI_MASK \ + (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \ + ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \ + pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_sc_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_hi_t f; +} pa_sc_perfcounter0_hi_u; + + +/* + * PA_CL_CNTL_STATUS struct + */ + +#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1 + +#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31 + +#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000 + +#define PA_CL_CNTL_STATUS_MASK \ + (PA_CL_CNTL_STATUS_CL_BUSY_MASK) + +#define PA_CL_CNTL_STATUS(cl_busy) \ + ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)) + +#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \ + ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \ + pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int : 31; + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + } pa_cl_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + unsigned int : 31; + } pa_cl_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_cntl_status_t f; +} pa_cl_cntl_status_u; + + +/* + * PA_SU_CNTL_STATUS struct + */ + +#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1 + +#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31 + +#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000 + +#define PA_SU_CNTL_STATUS_MASK \ + (PA_SU_CNTL_STATUS_SU_BUSY_MASK) + +#define PA_SU_CNTL_STATUS(su_busy) \ + ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)) + +#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \ + ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \ + pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int : 31; + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + } pa_su_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + unsigned int : 31; + } pa_su_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_cntl_status_t f; +} pa_su_cntl_status_u; + + +/* + * PA_SC_CNTL_STATUS struct + */ + +#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1 + +#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31 + +#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000 + +#define PA_SC_CNTL_STATUS_MASK \ + (PA_SC_CNTL_STATUS_SC_BUSY_MASK) + +#define PA_SC_CNTL_STATUS(sc_busy) \ + ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)) + +#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \ + ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \ + pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int : 31; + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + } pa_sc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + unsigned int : 31; + } pa_sc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_cntl_status_t f; +} pa_sc_cntl_status_u; + + +/* + * PA_SU_DEBUG_CNTL struct + */ + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f + +#define PA_SU_DEBUG_CNTL_MASK \ + (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) + +#define PA_SU_DEBUG_CNTL(su_debug_indx) \ + ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)) + +#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \ + ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \ + pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_su_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int : 27; + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + } pa_su_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_cntl_t f; +} pa_su_debug_cntl_u; + + +/* + * PA_SU_DEBUG_DATA struct + */ + +#define PA_SU_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SU_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SU_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SU_DEBUG_DATA_MASK \ + (PA_SU_DEBUG_DATA_DATA_MASK) + +#define PA_SU_DEBUG_DATA(data) \ + ((data << PA_SU_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \ + ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT) + +#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \ + pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_data_t f; +} pa_su_debug_data_u; + + +/* + * CLIPPER_DEBUG_REG00 struct + */ + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000 + +#define CLIPPER_DEBUG_REG00_MASK \ + (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \ + ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \ + (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \ + (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \ + (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \ + (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \ + (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \ + (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \ + (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \ + (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \ + (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \ + (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \ + (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \ + (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \ + (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \ + (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \ + (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \ + (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \ + (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \ + (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \ + (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + } clipper_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + } clipper_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg00_t f; +} clipper_debug_reg00_u; + + +/* + * CLIPPER_DEBUG_REG01 struct + */ + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000 + +#define CLIPPER_DEBUG_REG01_MASK \ + (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \ + CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \ + ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \ + (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \ + (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \ + (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \ + (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \ + (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \ + (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + } clipper_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + } clipper_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg01_t f; +} clipper_debug_reg01_u; + + +/* + * CLIPPER_DEBUG_REG02 struct + */ + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 + +#define CLIPPER_DEBUG_REG02_MASK \ + (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \ + CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) + +#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \ + ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \ + (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)) + +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + } clipper_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + } clipper_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg02_t f; +} clipper_debug_reg02_u; + + +/* + * CLIPPER_DEBUG_REG03 struct + */ + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG03_MASK \ + (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \ + ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + } clipper_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg03_t f; +} clipper_debug_reg03_u; + + +/* + * CLIPPER_DEBUG_REG04 struct + */ + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00 + +#define CLIPPER_DEBUG_REG04_MASK \ + (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \ + ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + } clipper_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg04_t f; +} clipper_debug_reg04_u; + + +/* + * CLIPPER_DEBUG_REG05 struct + */ + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000 + +#define CLIPPER_DEBUG_REG05_MASK \ + (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \ + ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \ + (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + } clipper_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg05_t f; +} clipper_debug_reg05_u; + + +/* + * CLIPPER_DEBUG_REG09 struct + */ + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000 +#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000 + +#define CLIPPER_DEBUG_REG09_MASK \ + (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \ + CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) + +#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \ + ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \ + (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \ + (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \ + (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \ + (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \ + (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \ + (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \ + (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \ + (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \ + (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \ + (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)) + +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + } clipper_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + } clipper_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg09_t f; +} clipper_debug_reg09_u; + + +/* + * CLIPPER_DEBUG_REG10 struct + */ + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG10_MASK \ + (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) + +#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \ + ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \ + (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \ + (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \ + (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \ + (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)) + +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + } clipper_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + } clipper_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg10_t f; +} clipper_debug_reg10_u; + + +/* + * CLIPPER_DEBUG_REG11 struct + */ + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0 + +#define CLIPPER_DEBUG_REG11_MASK \ + (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \ + CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \ + ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + } clipper_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + } clipper_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg11_t f; +} clipper_debug_reg11_u; + + +/* + * CLIPPER_DEBUG_REG12 struct + */ + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000 + +#define CLIPPER_DEBUG_REG12_MASK \ + (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \ + CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \ + ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \ + (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \ + (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \ + (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \ + (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \ + (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + } clipper_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg12_t f; +} clipper_debug_reg12_u; + + +/* + * CLIPPER_DEBUG_REG13 struct + */ + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000 +#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000 + +#define CLIPPER_DEBUG_REG13_MASK \ + (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \ + CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \ + ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \ + (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \ + (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \ + (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \ + (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \ + (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + } clipper_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg13_t f; +} clipper_debug_reg13_u; + + +/* + * SXIFCCG_DEBUG_REG0 struct + */ + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4 +#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3 +#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0 +#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380 +#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000 + +#define SXIFCCG_DEBUG_REG0_MASK \ + (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \ + SXIFCCG_DEBUG_REG0_position_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG0_point_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) + +#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \ + ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \ + (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \ + (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \ + (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \ + (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \ + (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \ + (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \ + (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)) + +#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + } sxifccg_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + } sxifccg_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg0_t f; +} sxifccg_debug_reg0_u; + + +/* + * SXIFCCG_DEBUG_REG1 struct + */ + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4 +#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c +#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000 +#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000 +#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000 + +#define SXIFCCG_DEBUG_REG1_MASK \ + (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \ + SXIFCCG_DEBUG_REG1_available_positions_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \ + SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \ + SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG1_aux_sel_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \ + SXIFCCG_DEBUG_REG1_param_cache_base_MASK) + +#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \ + ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \ + (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \ + (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \ + (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \ + (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \ + (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \ + (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \ + (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)) + +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + } sxifccg_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + } sxifccg_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg1_t f; +} sxifccg_debug_reg1_u; + + +/* + * SXIFCCG_DEBUG_REG2 struct + */ + +#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3 + +#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29 + +#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002 +#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8 +#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000 + +#define SXIFCCG_DEBUG_REG2_MASK \ + (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG2_sx_aux_MASK | \ + SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) + +#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \ + ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \ + (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \ + (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \ + (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \ + (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \ + (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \ + (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \ + (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \ + (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \ + (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)) + +#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + } sxifccg_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + } sxifccg_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg2_t f; +} sxifccg_debug_reg2_u; + + +/* + * SXIFCCG_DEBUG_REG3 struct + */ + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4 +#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8 +#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010 +#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00 +#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000 + +#define SXIFCCG_DEBUG_REG3_MASK \ + (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG3_available_positions_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG3_current_state_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) + +#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \ + ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \ + (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \ + (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \ + (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \ + (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \ + (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \ + (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \ + (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)) + +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + } sxifccg_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + } sxifccg_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg3_t f; +} sxifccg_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG0 struct + */ + +#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5 +#define SETUP_DEBUG_REG0_pmode_state_SIZE 6 +#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1 +#define SETUP_DEBUG_REG0_geom_enable_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1 +#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1 +#define SETUP_DEBUG_REG0_geom_busy_SIZE 1 + +#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0 +#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5 +#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11 +#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13 +#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14 +#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15 +#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16 +#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17 + +#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f +#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0 +#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800 +#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000 +#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000 +#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000 +#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000 +#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000 + +#define SETUP_DEBUG_REG0_MASK \ + (SETUP_DEBUG_REG0_su_cntl_state_MASK | \ + SETUP_DEBUG_REG0_pmode_state_MASK | \ + SETUP_DEBUG_REG0_ge_stallb_MASK | \ + SETUP_DEBUG_REG0_geom_enable_MASK | \ + SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \ + SETUP_DEBUG_REG0_su_clip_rtr_MASK | \ + SETUP_DEBUG_REG0_pfifo_busy_MASK | \ + SETUP_DEBUG_REG0_su_cntl_busy_MASK | \ + SETUP_DEBUG_REG0_geom_busy_MASK) + +#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \ + ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \ + (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \ + (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \ + (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \ + (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \ + (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \ + (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \ + (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \ + (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)) + +#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int : 14; + } setup_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int : 14; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + } setup_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg0_t f; +} setup_debug_reg0_u; + + +/* + * SETUP_DEBUG_REG1 struct + */ + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG1_MASK \ + (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \ + SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) + +#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \ + ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \ + (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + } setup_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg1_t f; +} setup_debug_reg1_u; + + +/* + * SETUP_DEBUG_REG2 struct + */ + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG2_MASK \ + (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \ + SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) + +#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \ + ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \ + (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + } setup_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg2_t f; +} setup_debug_reg2_u; + + +/* + * SETUP_DEBUG_REG3 struct + */ + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG3_MASK \ + (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \ + SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) + +#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \ + ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \ + (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + } setup_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg3_t f; +} setup_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG4 struct + */ + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11 +#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1 +#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3 +#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3 +#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2 +#define SETUP_DEBUG_REG4_type_gated_SIZE 3 +#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_event_gated_SIZE 1 +#define SETUP_DEBUG_REG4_eop_gated_SIZE 1 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0 +#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11 +#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12 +#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13 +#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17 +#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21 +#define SETUP_DEBUG_REG4_type_gated_SHIFT 23 +#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27 +#define SETUP_DEBUG_REG4_event_gated_SHIFT 28 +#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800 +#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000 +#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000 +#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000 +#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000 +#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000 +#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000 +#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000 +#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000 +#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000 + +#define SETUP_DEBUG_REG4_MASK \ + (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \ + SETUP_DEBUG_REG4_null_prim_gated_MASK | \ + SETUP_DEBUG_REG4_backfacing_gated_MASK | \ + SETUP_DEBUG_REG4_st_indx_gated_MASK | \ + SETUP_DEBUG_REG4_clipped_gated_MASK | \ + SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \ + SETUP_DEBUG_REG4_xmajor_gated_MASK | \ + SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \ + SETUP_DEBUG_REG4_type_gated_MASK | \ + SETUP_DEBUG_REG4_fpov_gated_MASK | \ + SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \ + SETUP_DEBUG_REG4_event_gated_MASK | \ + SETUP_DEBUG_REG4_eop_gated_MASK) + +#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \ + ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \ + (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \ + (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \ + (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \ + (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \ + (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \ + (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \ + (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \ + (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \ + (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \ + (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \ + (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \ + (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)) + +#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int : 2; + } setup_debug_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int : 2; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + } setup_debug_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg4_t f; +} setup_debug_reg4_u; + + +/* + * SETUP_DEBUG_REG5 struct + */ + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2 +#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22 +#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000 +#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000 + +#define SETUP_DEBUG_REG5_MASK \ + (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \ + SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \ + SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \ + SETUP_DEBUG_REG5_event_id_gated_MASK) + +#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \ + ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \ + (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \ + (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \ + (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)) + +#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int : 3; + } setup_debug_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int : 3; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + } setup_debug_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg5_t f; +} setup_debug_reg5_u; + + +/* + * PA_SC_DEBUG_CNTL struct + */ + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f + +#define PA_SC_DEBUG_CNTL_MASK \ + (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) + +#define PA_SC_DEBUG_CNTL(sc_debug_indx) \ + ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)) + +#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \ + ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \ + pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_sc_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int : 27; + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + } pa_sc_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_cntl_t f; +} pa_sc_debug_cntl_u; + + +/* + * PA_SC_DEBUG_DATA struct + */ + +#define PA_SC_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SC_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SC_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SC_DEBUG_DATA_MASK \ + (PA_SC_DEBUG_DATA_DATA_MASK) + +#define PA_SC_DEBUG_DATA(data) \ + ((data << PA_SC_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \ + ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT) + +#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \ + pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_data_t f; +} pa_sc_debug_data_u; + + +/* + * SC_DEBUG_0 struct + */ + +#define SC_DEBUG_0_pa_freeze_b1_SIZE 1 +#define SC_DEBUG_0_pa_sc_valid_SIZE 1 +#define SC_DEBUG_0_pa_sc_phase_SIZE 3 +#define SC_DEBUG_0_cntx_cnt_SIZE 7 +#define SC_DEBUG_0_decr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_incr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_trigger_SIZE 1 + +#define SC_DEBUG_0_pa_freeze_b1_SHIFT 0 +#define SC_DEBUG_0_pa_sc_valid_SHIFT 1 +#define SC_DEBUG_0_pa_sc_phase_SHIFT 2 +#define SC_DEBUG_0_cntx_cnt_SHIFT 5 +#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12 +#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13 +#define SC_DEBUG_0_trigger_SHIFT 31 + +#define SC_DEBUG_0_pa_freeze_b1_MASK 0x00000001 +#define SC_DEBUG_0_pa_sc_valid_MASK 0x00000002 +#define SC_DEBUG_0_pa_sc_phase_MASK 0x0000001c +#define SC_DEBUG_0_cntx_cnt_MASK 0x00000fe0 +#define SC_DEBUG_0_decr_cntx_cnt_MASK 0x00001000 +#define SC_DEBUG_0_incr_cntx_cnt_MASK 0x00002000 +#define SC_DEBUG_0_trigger_MASK 0x80000000 + +#define SC_DEBUG_0_MASK \ + (SC_DEBUG_0_pa_freeze_b1_MASK | \ + SC_DEBUG_0_pa_sc_valid_MASK | \ + SC_DEBUG_0_pa_sc_phase_MASK | \ + SC_DEBUG_0_cntx_cnt_MASK | \ + SC_DEBUG_0_decr_cntx_cnt_MASK | \ + SC_DEBUG_0_incr_cntx_cnt_MASK | \ + SC_DEBUG_0_trigger_MASK) + +#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \ + ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \ + (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \ + (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \ + (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \ + (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \ + (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \ + (trigger << SC_DEBUG_0_trigger_SHIFT)) + +#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_trigger(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT) + +#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int : 17; + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + } sc_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + unsigned int : 17; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + } sc_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_0_t f; +} sc_debug_0_u; + + +/* + * SC_DEBUG_1 struct + */ + +#define SC_DEBUG_1_em_state_SIZE 3 +#define SC_DEBUG_1_em1_data_ready_SIZE 1 +#define SC_DEBUG_1_em2_data_ready_SIZE 1 +#define SC_DEBUG_1_move_em1_to_em2_SIZE 1 +#define SC_DEBUG_1_ef_data_ready_SIZE 1 +#define SC_DEBUG_1_ef_state_SIZE 2 +#define SC_DEBUG_1_pipe_valid_SIZE 1 +#define SC_DEBUG_1_trigger_SIZE 1 + +#define SC_DEBUG_1_em_state_SHIFT 0 +#define SC_DEBUG_1_em1_data_ready_SHIFT 3 +#define SC_DEBUG_1_em2_data_ready_SHIFT 4 +#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5 +#define SC_DEBUG_1_ef_data_ready_SHIFT 6 +#define SC_DEBUG_1_ef_state_SHIFT 7 +#define SC_DEBUG_1_pipe_valid_SHIFT 9 +#define SC_DEBUG_1_trigger_SHIFT 31 + +#define SC_DEBUG_1_em_state_MASK 0x00000007 +#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008 +#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010 +#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020 +#define SC_DEBUG_1_ef_data_ready_MASK 0x00000040 +#define SC_DEBUG_1_ef_state_MASK 0x00000180 +#define SC_DEBUG_1_pipe_valid_MASK 0x00000200 +#define SC_DEBUG_1_trigger_MASK 0x80000000 + +#define SC_DEBUG_1_MASK \ + (SC_DEBUG_1_em_state_MASK | \ + SC_DEBUG_1_em1_data_ready_MASK | \ + SC_DEBUG_1_em2_data_ready_MASK | \ + SC_DEBUG_1_move_em1_to_em2_MASK | \ + SC_DEBUG_1_ef_data_ready_MASK | \ + SC_DEBUG_1_ef_state_MASK | \ + SC_DEBUG_1_pipe_valid_MASK | \ + SC_DEBUG_1_trigger_MASK) + +#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \ + ((em_state << SC_DEBUG_1_em_state_SHIFT) | \ + (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \ + (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \ + (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \ + (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \ + (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \ + (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \ + (trigger << SC_DEBUG_1_trigger_SHIFT)) + +#define SC_DEBUG_1_GET_em_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_GET_trigger(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT) + +#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int : 21; + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + } sc_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + unsigned int : 21; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + } sc_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_1_t f; +} sc_debug_1_u; + + +/* + * SC_DEBUG_2 struct + */ + +#define SC_DEBUG_2_rc_rtr_dly_SIZE 1 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1 +#define SC_DEBUG_2_pipe_freeze_b_SIZE 1 +#define SC_DEBUG_2_prim_rts_SIZE 1 +#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1 +#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1 +#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1 +#define SC_DEBUG_2_stage0_rts_SIZE 1 +#define SC_DEBUG_2_phase_rts_dly_SIZE 1 +#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1 +#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1 +#define SC_DEBUG_2_event_id_s1_SIZE 5 +#define SC_DEBUG_2_event_s1_SIZE 1 +#define SC_DEBUG_2_trigger_SIZE 1 + +#define SC_DEBUG_2_rc_rtr_dly_SHIFT 0 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1 +#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3 +#define SC_DEBUG_2_prim_rts_SHIFT 4 +#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5 +#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6 +#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7 +#define SC_DEBUG_2_stage0_rts_SHIFT 8 +#define SC_DEBUG_2_phase_rts_dly_SHIFT 9 +#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15 +#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16 +#define SC_DEBUG_2_event_id_s1_SHIFT 17 +#define SC_DEBUG_2_event_s1_SHIFT 22 +#define SC_DEBUG_2_trigger_SHIFT 31 + +#define SC_DEBUG_2_rc_rtr_dly_MASK 0x00000001 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002 +#define SC_DEBUG_2_pipe_freeze_b_MASK 0x00000008 +#define SC_DEBUG_2_prim_rts_MASK 0x00000010 +#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020 +#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040 +#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080 +#define SC_DEBUG_2_stage0_rts_MASK 0x00000100 +#define SC_DEBUG_2_phase_rts_dly_MASK 0x00000200 +#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000 +#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000 +#define SC_DEBUG_2_event_id_s1_MASK 0x003e0000 +#define SC_DEBUG_2_event_s1_MASK 0x00400000 +#define SC_DEBUG_2_trigger_MASK 0x80000000 + +#define SC_DEBUG_2_MASK \ + (SC_DEBUG_2_rc_rtr_dly_MASK | \ + SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \ + SC_DEBUG_2_pipe_freeze_b_MASK | \ + SC_DEBUG_2_prim_rts_MASK | \ + SC_DEBUG_2_next_prim_rts_dly_MASK | \ + SC_DEBUG_2_next_prim_rtr_dly_MASK | \ + SC_DEBUG_2_pre_stage1_rts_d1_MASK | \ + SC_DEBUG_2_stage0_rts_MASK | \ + SC_DEBUG_2_phase_rts_dly_MASK | \ + SC_DEBUG_2_end_of_prim_s1_dly_MASK | \ + SC_DEBUG_2_pass_empty_prim_s1_MASK | \ + SC_DEBUG_2_event_id_s1_MASK | \ + SC_DEBUG_2_event_s1_MASK | \ + SC_DEBUG_2_trigger_MASK) + +#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \ + ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \ + (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \ + (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \ + (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \ + (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \ + (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \ + (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \ + (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \ + (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \ + (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \ + (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \ + (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \ + (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \ + (trigger << SC_DEBUG_2_trigger_SHIFT)) + +#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_GET_trigger(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT) + +#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int : 1; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int : 8; + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + } sc_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + unsigned int : 8; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int : 5; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + } sc_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_2_t f; +} sc_debug_2_u; + + +/* + * SC_DEBUG_3 struct + */ + +#define SC_DEBUG_3_x_curr_s1_SIZE 11 +#define SC_DEBUG_3_y_curr_s1_SIZE 11 +#define SC_DEBUG_3_trigger_SIZE 1 + +#define SC_DEBUG_3_x_curr_s1_SHIFT 0 +#define SC_DEBUG_3_y_curr_s1_SHIFT 11 +#define SC_DEBUG_3_trigger_SHIFT 31 + +#define SC_DEBUG_3_x_curr_s1_MASK 0x000007ff +#define SC_DEBUG_3_y_curr_s1_MASK 0x003ff800 +#define SC_DEBUG_3_trigger_MASK 0x80000000 + +#define SC_DEBUG_3_MASK \ + (SC_DEBUG_3_x_curr_s1_MASK | \ + SC_DEBUG_3_y_curr_s1_MASK | \ + SC_DEBUG_3_trigger_MASK) + +#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \ + ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \ + (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \ + (trigger << SC_DEBUG_3_trigger_SHIFT)) + +#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_trigger(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT) + +#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int : 9; + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + } sc_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + unsigned int : 9; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + } sc_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_3_t f; +} sc_debug_3_u; + + +/* + * SC_DEBUG_4 struct + */ + +#define SC_DEBUG_4_y_end_s1_SIZE 14 +#define SC_DEBUG_4_y_start_s1_SIZE 14 +#define SC_DEBUG_4_y_dir_s1_SIZE 1 +#define SC_DEBUG_4_trigger_SIZE 1 + +#define SC_DEBUG_4_y_end_s1_SHIFT 0 +#define SC_DEBUG_4_y_start_s1_SHIFT 14 +#define SC_DEBUG_4_y_dir_s1_SHIFT 28 +#define SC_DEBUG_4_trigger_SHIFT 31 + +#define SC_DEBUG_4_y_end_s1_MASK 0x00003fff +#define SC_DEBUG_4_y_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_4_y_dir_s1_MASK 0x10000000 +#define SC_DEBUG_4_trigger_MASK 0x80000000 + +#define SC_DEBUG_4_MASK \ + (SC_DEBUG_4_y_end_s1_MASK | \ + SC_DEBUG_4_y_start_s1_MASK | \ + SC_DEBUG_4_y_dir_s1_MASK | \ + SC_DEBUG_4_trigger_MASK) + +#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \ + ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \ + (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \ + (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_4_trigger_SHIFT)) + +#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_GET_trigger(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT) + +#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + } sc_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + unsigned int : 2; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + } sc_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_4_t f; +} sc_debug_4_u; + + +/* + * SC_DEBUG_5 struct + */ + +#define SC_DEBUG_5_x_end_s1_SIZE 14 +#define SC_DEBUG_5_x_start_s1_SIZE 14 +#define SC_DEBUG_5_x_dir_s1_SIZE 1 +#define SC_DEBUG_5_trigger_SIZE 1 + +#define SC_DEBUG_5_x_end_s1_SHIFT 0 +#define SC_DEBUG_5_x_start_s1_SHIFT 14 +#define SC_DEBUG_5_x_dir_s1_SHIFT 28 +#define SC_DEBUG_5_trigger_SHIFT 31 + +#define SC_DEBUG_5_x_end_s1_MASK 0x00003fff +#define SC_DEBUG_5_x_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_5_x_dir_s1_MASK 0x10000000 +#define SC_DEBUG_5_trigger_MASK 0x80000000 + +#define SC_DEBUG_5_MASK \ + (SC_DEBUG_5_x_end_s1_MASK | \ + SC_DEBUG_5_x_start_s1_MASK | \ + SC_DEBUG_5_x_dir_s1_MASK | \ + SC_DEBUG_5_trigger_MASK) + +#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \ + ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \ + (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \ + (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_5_trigger_SHIFT)) + +#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_GET_trigger(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT) + +#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + } sc_debug_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + unsigned int : 2; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + } sc_debug_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_5_t f; +} sc_debug_5_u; + + +/* + * SC_DEBUG_6 struct + */ + +#define SC_DEBUG_6_z_ff_empty_SIZE 1 +#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1 +#define SC_DEBUG_6_xy_ff_empty_SIZE 1 +#define SC_DEBUG_6_event_flag_SIZE 1 +#define SC_DEBUG_6_z_mask_needed_SIZE 1 +#define SC_DEBUG_6_state_SIZE 3 +#define SC_DEBUG_6_state_delayed_SIZE 3 +#define SC_DEBUG_6_data_valid_SIZE 1 +#define SC_DEBUG_6_data_valid_d_SIZE 1 +#define SC_DEBUG_6_tilex_delayed_SIZE 9 +#define SC_DEBUG_6_tiley_delayed_SIZE 9 +#define SC_DEBUG_6_trigger_SIZE 1 + +#define SC_DEBUG_6_z_ff_empty_SHIFT 0 +#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1 +#define SC_DEBUG_6_xy_ff_empty_SHIFT 2 +#define SC_DEBUG_6_event_flag_SHIFT 3 +#define SC_DEBUG_6_z_mask_needed_SHIFT 4 +#define SC_DEBUG_6_state_SHIFT 5 +#define SC_DEBUG_6_state_delayed_SHIFT 8 +#define SC_DEBUG_6_data_valid_SHIFT 11 +#define SC_DEBUG_6_data_valid_d_SHIFT 12 +#define SC_DEBUG_6_tilex_delayed_SHIFT 13 +#define SC_DEBUG_6_tiley_delayed_SHIFT 22 +#define SC_DEBUG_6_trigger_SHIFT 31 + +#define SC_DEBUG_6_z_ff_empty_MASK 0x00000001 +#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002 +#define SC_DEBUG_6_xy_ff_empty_MASK 0x00000004 +#define SC_DEBUG_6_event_flag_MASK 0x00000008 +#define SC_DEBUG_6_z_mask_needed_MASK 0x00000010 +#define SC_DEBUG_6_state_MASK 0x000000e0 +#define SC_DEBUG_6_state_delayed_MASK 0x00000700 +#define SC_DEBUG_6_data_valid_MASK 0x00000800 +#define SC_DEBUG_6_data_valid_d_MASK 0x00001000 +#define SC_DEBUG_6_tilex_delayed_MASK 0x003fe000 +#define SC_DEBUG_6_tiley_delayed_MASK 0x7fc00000 +#define SC_DEBUG_6_trigger_MASK 0x80000000 + +#define SC_DEBUG_6_MASK \ + (SC_DEBUG_6_z_ff_empty_MASK | \ + SC_DEBUG_6_qmcntl_ff_empty_MASK | \ + SC_DEBUG_6_xy_ff_empty_MASK | \ + SC_DEBUG_6_event_flag_MASK | \ + SC_DEBUG_6_z_mask_needed_MASK | \ + SC_DEBUG_6_state_MASK | \ + SC_DEBUG_6_state_delayed_MASK | \ + SC_DEBUG_6_data_valid_MASK | \ + SC_DEBUG_6_data_valid_d_MASK | \ + SC_DEBUG_6_tilex_delayed_MASK | \ + SC_DEBUG_6_tiley_delayed_MASK | \ + SC_DEBUG_6_trigger_MASK) + +#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \ + ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \ + (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \ + (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \ + (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \ + (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \ + (state << SC_DEBUG_6_state_SHIFT) | \ + (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \ + (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \ + (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \ + (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \ + (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \ + (trigger << SC_DEBUG_6_trigger_SHIFT)) + +#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_GET_state(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_GET_trigger(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT) + +#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + } sc_debug_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + } sc_debug_6_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_6_t f; +} sc_debug_6_u; + + +/* + * SC_DEBUG_7 struct + */ + +#define SC_DEBUG_7_event_flag_SIZE 1 +#define SC_DEBUG_7_deallocate_SIZE 3 +#define SC_DEBUG_7_fposition_SIZE 1 +#define SC_DEBUG_7_sr_prim_we_SIZE 1 +#define SC_DEBUG_7_last_tile_SIZE 1 +#define SC_DEBUG_7_tile_ff_we_SIZE 1 +#define SC_DEBUG_7_qs_data_valid_SIZE 1 +#define SC_DEBUG_7_qs_q0_y_SIZE 2 +#define SC_DEBUG_7_qs_q0_x_SIZE 2 +#define SC_DEBUG_7_qs_q0_valid_SIZE 1 +#define SC_DEBUG_7_prim_ff_we_SIZE 1 +#define SC_DEBUG_7_tile_ff_re_SIZE 1 +#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_7_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_7_new_prim_SIZE 1 +#define SC_DEBUG_7_load_new_tile_data_SIZE 1 +#define SC_DEBUG_7_state_SIZE 2 +#define SC_DEBUG_7_fifos_ready_SIZE 1 +#define SC_DEBUG_7_trigger_SIZE 1 + +#define SC_DEBUG_7_event_flag_SHIFT 0 +#define SC_DEBUG_7_deallocate_SHIFT 1 +#define SC_DEBUG_7_fposition_SHIFT 4 +#define SC_DEBUG_7_sr_prim_we_SHIFT 5 +#define SC_DEBUG_7_last_tile_SHIFT 6 +#define SC_DEBUG_7_tile_ff_we_SHIFT 7 +#define SC_DEBUG_7_qs_data_valid_SHIFT 8 +#define SC_DEBUG_7_qs_q0_y_SHIFT 9 +#define SC_DEBUG_7_qs_q0_x_SHIFT 11 +#define SC_DEBUG_7_qs_q0_valid_SHIFT 13 +#define SC_DEBUG_7_prim_ff_we_SHIFT 14 +#define SC_DEBUG_7_tile_ff_re_SHIFT 15 +#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16 +#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17 +#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18 +#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19 +#define SC_DEBUG_7_new_prim_SHIFT 20 +#define SC_DEBUG_7_load_new_tile_data_SHIFT 21 +#define SC_DEBUG_7_state_SHIFT 22 +#define SC_DEBUG_7_fifos_ready_SHIFT 24 +#define SC_DEBUG_7_trigger_SHIFT 31 + +#define SC_DEBUG_7_event_flag_MASK 0x00000001 +#define SC_DEBUG_7_deallocate_MASK 0x0000000e +#define SC_DEBUG_7_fposition_MASK 0x00000010 +#define SC_DEBUG_7_sr_prim_we_MASK 0x00000020 +#define SC_DEBUG_7_last_tile_MASK 0x00000040 +#define SC_DEBUG_7_tile_ff_we_MASK 0x00000080 +#define SC_DEBUG_7_qs_data_valid_MASK 0x00000100 +#define SC_DEBUG_7_qs_q0_y_MASK 0x00000600 +#define SC_DEBUG_7_qs_q0_x_MASK 0x00001800 +#define SC_DEBUG_7_qs_q0_valid_MASK 0x00002000 +#define SC_DEBUG_7_prim_ff_we_MASK 0x00004000 +#define SC_DEBUG_7_tile_ff_re_MASK 0x00008000 +#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000 +#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000 +#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000 +#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000 +#define SC_DEBUG_7_new_prim_MASK 0x00100000 +#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000 +#define SC_DEBUG_7_state_MASK 0x00c00000 +#define SC_DEBUG_7_fifos_ready_MASK 0x01000000 +#define SC_DEBUG_7_trigger_MASK 0x80000000 + +#define SC_DEBUG_7_MASK \ + (SC_DEBUG_7_event_flag_MASK | \ + SC_DEBUG_7_deallocate_MASK | \ + SC_DEBUG_7_fposition_MASK | \ + SC_DEBUG_7_sr_prim_we_MASK | \ + SC_DEBUG_7_last_tile_MASK | \ + SC_DEBUG_7_tile_ff_we_MASK | \ + SC_DEBUG_7_qs_data_valid_MASK | \ + SC_DEBUG_7_qs_q0_y_MASK | \ + SC_DEBUG_7_qs_q0_x_MASK | \ + SC_DEBUG_7_qs_q0_valid_MASK | \ + SC_DEBUG_7_prim_ff_we_MASK | \ + SC_DEBUG_7_tile_ff_re_MASK | \ + SC_DEBUG_7_fw_prim_data_valid_MASK | \ + SC_DEBUG_7_last_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_prim_MASK | \ + SC_DEBUG_7_new_prim_MASK | \ + SC_DEBUG_7_load_new_tile_data_MASK | \ + SC_DEBUG_7_state_MASK | \ + SC_DEBUG_7_fifos_ready_MASK | \ + SC_DEBUG_7_trigger_MASK) + +#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \ + ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \ + (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \ + (fposition << SC_DEBUG_7_fposition_SHIFT) | \ + (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \ + (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \ + (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \ + (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \ + (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \ + (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \ + (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \ + (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \ + (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \ + (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \ + (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \ + (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \ + (state << SC_DEBUG_7_state_SHIFT) | \ + (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \ + (trigger << SC_DEBUG_7_trigger_SHIFT)) + +#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_GET_fposition(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_GET_state(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_GET_trigger(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT) + +#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int : 6; + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + } sc_debug_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + unsigned int : 6; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + } sc_debug_7_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_7_t f; +} sc_debug_7_u; + + +/* + * SC_DEBUG_8 struct + */ + +#define SC_DEBUG_8_sample_last_SIZE 1 +#define SC_DEBUG_8_sample_mask_SIZE 4 +#define SC_DEBUG_8_sample_y_SIZE 2 +#define SC_DEBUG_8_sample_x_SIZE 2 +#define SC_DEBUG_8_sample_send_SIZE 1 +#define SC_DEBUG_8_next_cycle_SIZE 2 +#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1 +#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1 +#define SC_DEBUG_8_num_samples_SIZE 2 +#define SC_DEBUG_8_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_8_last_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_sample_we_SIZE 1 +#define SC_DEBUG_8_fposition_SIZE 1 +#define SC_DEBUG_8_event_id_SIZE 5 +#define SC_DEBUG_8_event_flag_SIZE 1 +#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_8_trigger_SIZE 1 + +#define SC_DEBUG_8_sample_last_SHIFT 0 +#define SC_DEBUG_8_sample_mask_SHIFT 1 +#define SC_DEBUG_8_sample_y_SHIFT 5 +#define SC_DEBUG_8_sample_x_SHIFT 7 +#define SC_DEBUG_8_sample_send_SHIFT 9 +#define SC_DEBUG_8_next_cycle_SHIFT 10 +#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12 +#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13 +#define SC_DEBUG_8_num_samples_SHIFT 14 +#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16 +#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17 +#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18 +#define SC_DEBUG_8_sample_we_SHIFT 19 +#define SC_DEBUG_8_fposition_SHIFT 20 +#define SC_DEBUG_8_event_id_SHIFT 21 +#define SC_DEBUG_8_event_flag_SHIFT 26 +#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27 +#define SC_DEBUG_8_trigger_SHIFT 31 + +#define SC_DEBUG_8_sample_last_MASK 0x00000001 +#define SC_DEBUG_8_sample_mask_MASK 0x0000001e +#define SC_DEBUG_8_sample_y_MASK 0x00000060 +#define SC_DEBUG_8_sample_x_MASK 0x00000180 +#define SC_DEBUG_8_sample_send_MASK 0x00000200 +#define SC_DEBUG_8_next_cycle_MASK 0x00000c00 +#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000 +#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000 +#define SC_DEBUG_8_num_samples_MASK 0x0000c000 +#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000 +#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000 +#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000 +#define SC_DEBUG_8_sample_we_MASK 0x00080000 +#define SC_DEBUG_8_fposition_MASK 0x00100000 +#define SC_DEBUG_8_event_id_MASK 0x03e00000 +#define SC_DEBUG_8_event_flag_MASK 0x04000000 +#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000 +#define SC_DEBUG_8_trigger_MASK 0x80000000 + +#define SC_DEBUG_8_MASK \ + (SC_DEBUG_8_sample_last_MASK | \ + SC_DEBUG_8_sample_mask_MASK | \ + SC_DEBUG_8_sample_y_MASK | \ + SC_DEBUG_8_sample_x_MASK | \ + SC_DEBUG_8_sample_send_MASK | \ + SC_DEBUG_8_next_cycle_MASK | \ + SC_DEBUG_8_ez_sample_ff_full_MASK | \ + SC_DEBUG_8_rb_sc_samp_rtr_MASK | \ + SC_DEBUG_8_num_samples_MASK | \ + SC_DEBUG_8_last_quad_of_tile_MASK | \ + SC_DEBUG_8_last_quad_of_prim_MASK | \ + SC_DEBUG_8_first_quad_of_prim_MASK | \ + SC_DEBUG_8_sample_we_MASK | \ + SC_DEBUG_8_fposition_MASK | \ + SC_DEBUG_8_event_id_MASK | \ + SC_DEBUG_8_event_flag_MASK | \ + SC_DEBUG_8_fw_prim_data_valid_MASK | \ + SC_DEBUG_8_trigger_MASK) + +#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \ + ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \ + (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \ + (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \ + (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \ + (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \ + (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \ + (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \ + (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \ + (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \ + (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \ + (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \ + (fposition << SC_DEBUG_8_fposition_SHIFT) | \ + (event_id << SC_DEBUG_8_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \ + (trigger << SC_DEBUG_8_trigger_SHIFT)) + +#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_GET_fposition(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_GET_event_id(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_GET_trigger(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT) + +#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int : 3; + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + } sc_debug_8_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + unsigned int : 3; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + } sc_debug_8_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_8_t f; +} sc_debug_8_u; + + +/* + * SC_DEBUG_9 struct + */ + +#define SC_DEBUG_9_rb_sc_send_SIZE 1 +#define SC_DEBUG_9_rb_sc_ez_mask_SIZE 4 +#define SC_DEBUG_9_fifo_data_ready_SIZE 1 +#define SC_DEBUG_9_early_z_enable_SIZE 1 +#define SC_DEBUG_9_mask_state_SIZE 2 +#define SC_DEBUG_9_next_ez_mask_SIZE 16 +#define SC_DEBUG_9_mask_ready_SIZE 1 +#define SC_DEBUG_9_drop_sample_SIZE 1 +#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_9_trigger_SIZE 1 + +#define SC_DEBUG_9_rb_sc_send_SHIFT 0 +#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1 +#define SC_DEBUG_9_fifo_data_ready_SHIFT 5 +#define SC_DEBUG_9_early_z_enable_SHIFT 6 +#define SC_DEBUG_9_mask_state_SHIFT 7 +#define SC_DEBUG_9_next_ez_mask_SHIFT 9 +#define SC_DEBUG_9_mask_ready_SHIFT 25 +#define SC_DEBUG_9_drop_sample_SHIFT 26 +#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30 +#define SC_DEBUG_9_trigger_SHIFT 31 + +#define SC_DEBUG_9_rb_sc_send_MASK 0x00000001 +#define SC_DEBUG_9_rb_sc_ez_mask_MASK 0x0000001e +#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020 +#define SC_DEBUG_9_early_z_enable_MASK 0x00000040 +#define SC_DEBUG_9_mask_state_MASK 0x00000180 +#define SC_DEBUG_9_next_ez_mask_MASK 0x01fffe00 +#define SC_DEBUG_9_mask_ready_MASK 0x02000000 +#define SC_DEBUG_9_drop_sample_MASK 0x04000000 +#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000 +#define SC_DEBUG_9_trigger_MASK 0x80000000 + +#define SC_DEBUG_9_MASK \ + (SC_DEBUG_9_rb_sc_send_MASK | \ + SC_DEBUG_9_rb_sc_ez_mask_MASK | \ + SC_DEBUG_9_fifo_data_ready_MASK | \ + SC_DEBUG_9_early_z_enable_MASK | \ + SC_DEBUG_9_mask_state_MASK | \ + SC_DEBUG_9_next_ez_mask_MASK | \ + SC_DEBUG_9_mask_ready_MASK | \ + SC_DEBUG_9_drop_sample_MASK | \ + SC_DEBUG_9_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \ + SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_9_trigger_MASK) + +#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \ + ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \ + (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \ + (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \ + (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \ + (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \ + (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \ + (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \ + (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \ + (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \ + (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \ + (trigger << SC_DEBUG_9_trigger_SHIFT)) + +#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_GET_trigger(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT) + +#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + } sc_debug_9_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + } sc_debug_9_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_9_t f; +} sc_debug_9_u; + + +/* + * SC_DEBUG_10 struct + */ + +#define SC_DEBUG_10_combined_sample_mask_SIZE 16 +#define SC_DEBUG_10_trigger_SIZE 1 + +#define SC_DEBUG_10_combined_sample_mask_SHIFT 0 +#define SC_DEBUG_10_trigger_SHIFT 31 + +#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff +#define SC_DEBUG_10_trigger_MASK 0x80000000 + +#define SC_DEBUG_10_MASK \ + (SC_DEBUG_10_combined_sample_mask_MASK | \ + SC_DEBUG_10_trigger_MASK) + +#define SC_DEBUG_10(combined_sample_mask, trigger) \ + ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \ + (trigger << SC_DEBUG_10_trigger_SHIFT)) + +#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_GET_trigger(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT) + +#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + unsigned int : 15; + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + } sc_debug_10_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + unsigned int : 15; + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + } sc_debug_10_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_10_t f; +} sc_debug_10_u; + + +/* + * SC_DEBUG_11 struct + */ + +#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_11_iterator_input_fz_SIZE 1 +#define SC_DEBUG_11_packer_send_quads_SIZE 1 +#define SC_DEBUG_11_packer_send_cmd_SIZE 1 +#define SC_DEBUG_11_packer_send_event_SIZE 1 +#define SC_DEBUG_11_next_state_SIZE 3 +#define SC_DEBUG_11_state_SIZE 3 +#define SC_DEBUG_11_stall_SIZE 1 +#define SC_DEBUG_11_trigger_SIZE 1 + +#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1 +#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3 +#define SC_DEBUG_11_iterator_input_fz_SHIFT 4 +#define SC_DEBUG_11_packer_send_quads_SHIFT 5 +#define SC_DEBUG_11_packer_send_cmd_SHIFT 6 +#define SC_DEBUG_11_packer_send_event_SHIFT 7 +#define SC_DEBUG_11_next_state_SHIFT 8 +#define SC_DEBUG_11_state_SHIFT 11 +#define SC_DEBUG_11_stall_SHIFT 14 +#define SC_DEBUG_11_trigger_SHIFT 31 + +#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002 +#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008 +#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010 +#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020 +#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040 +#define SC_DEBUG_11_packer_send_event_MASK 0x00000080 +#define SC_DEBUG_11_next_state_MASK 0x00000700 +#define SC_DEBUG_11_state_MASK 0x00003800 +#define SC_DEBUG_11_stall_MASK 0x00004000 +#define SC_DEBUG_11_trigger_MASK 0x80000000 + +#define SC_DEBUG_11_MASK \ + (SC_DEBUG_11_ez_sample_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_11_ez_prim_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_11_iterator_input_fz_MASK | \ + SC_DEBUG_11_packer_send_quads_MASK | \ + SC_DEBUG_11_packer_send_cmd_MASK | \ + SC_DEBUG_11_packer_send_event_MASK | \ + SC_DEBUG_11_next_state_MASK | \ + SC_DEBUG_11_state_MASK | \ + SC_DEBUG_11_stall_MASK | \ + SC_DEBUG_11_trigger_MASK) + +#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \ + ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \ + (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \ + (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \ + (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \ + (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \ + (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \ + (next_state << SC_DEBUG_11_next_state_SHIFT) | \ + (state << SC_DEBUG_11_state_SHIFT) | \ + (stall << SC_DEBUG_11_stall_SHIFT) | \ + (trigger << SC_DEBUG_11_trigger_SHIFT)) + +#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_GET_next_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_GET_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_GET_stall(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_GET_trigger(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT) + +#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int : 16; + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + } sc_debug_11_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + unsigned int : 16; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + } sc_debug_11_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_11_t f; +} sc_debug_11_u; + + +/* + * SC_DEBUG_12 struct + */ + +#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1 +#define SC_DEBUG_12_event_id_SIZE 5 +#define SC_DEBUG_12_event_flag_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_full_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1 +#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1 +#define SC_DEBUG_12_iter_qdhit0_SIZE 1 +#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1 +#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1 +#define SC_DEBUG_12_iter_phase_out_SIZE 2 +#define SC_DEBUG_12_iter_phase_reg_SIZE 2 +#define SC_DEBUG_12_iterator_SP_valid_SIZE 1 +#define SC_DEBUG_12_eopv_reg_SIZE 1 +#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1 +#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1 +#define SC_DEBUG_12_trigger_SIZE 1 + +#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0 +#define SC_DEBUG_12_event_id_SHIFT 1 +#define SC_DEBUG_12_event_flag_SHIFT 6 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7 +#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8 +#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9 +#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11 +#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12 +#define SC_DEBUG_12_iter_qdhit0_SHIFT 13 +#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14 +#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15 +#define SC_DEBUG_12_iter_phase_out_SHIFT 16 +#define SC_DEBUG_12_iter_phase_reg_SHIFT 18 +#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20 +#define SC_DEBUG_12_eopv_reg_SHIFT 21 +#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22 +#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23 +#define SC_DEBUG_12_trigger_SHIFT 31 + +#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001 +#define SC_DEBUG_12_event_id_MASK 0x0000003e +#define SC_DEBUG_12_event_flag_MASK 0x00000040 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080 +#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100 +#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200 +#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400 +#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800 +#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000 +#define SC_DEBUG_12_iter_qdhit0_MASK 0x00002000 +#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000 +#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000 +#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000 +#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000 +#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000 +#define SC_DEBUG_12_eopv_reg_MASK 0x00200000 +#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000 +#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000 +#define SC_DEBUG_12_trigger_MASK 0x80000000 + +#define SC_DEBUG_12_MASK \ + (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \ + SC_DEBUG_12_event_id_MASK | \ + SC_DEBUG_12_event_flag_MASK | \ + SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \ + SC_DEBUG_12_itercmdfifo_full_MASK | \ + SC_DEBUG_12_itercmdfifo_empty_MASK | \ + SC_DEBUG_12_iter_ds_one_clk_command_MASK | \ + SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \ + SC_DEBUG_12_iter_ds_end_of_vector_MASK | \ + SC_DEBUG_12_iter_qdhit0_MASK | \ + SC_DEBUG_12_bc_use_centers_reg_MASK | \ + SC_DEBUG_12_bc_output_xy_reg_MASK | \ + SC_DEBUG_12_iter_phase_out_MASK | \ + SC_DEBUG_12_iter_phase_reg_MASK | \ + SC_DEBUG_12_iterator_SP_valid_MASK | \ + SC_DEBUG_12_eopv_reg_MASK | \ + SC_DEBUG_12_one_clk_cmd_reg_MASK | \ + SC_DEBUG_12_iter_dx_end_of_prim_MASK | \ + SC_DEBUG_12_trigger_MASK) + +#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \ + ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \ + (event_id << SC_DEBUG_12_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \ + (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \ + (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \ + (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \ + (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \ + (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \ + (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \ + (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \ + (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \ + (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \ + (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \ + (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \ + (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \ + (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \ + (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \ + (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \ + (trigger << SC_DEBUG_12_trigger_SHIFT)) + +#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_GET_event_id(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_GET_trigger(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT) + +#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int : 7; + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + } sc_debug_12_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + } sc_debug_12_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_12_t f; +} sc_debug_12_u; + + +#endif + + +#if !defined (_VGT_FIDDLE_H) +#define _VGT_FIDDLE_H + +/***************************************************************************************************************** + * + * vgt_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + +/* + * VGT_OUT_PRIM_TYPE enum + */ + +#define VGT_OUT_POINT 0x00000000 +#define VGT_OUT_LINE 0x00000001 +#define VGT_OUT_TRI 0x00000002 +#define VGT_OUT_RECT_V0 0x00000003 +#define VGT_OUT_RECT_V1 0x00000004 +#define VGT_OUT_RECT_V2 0x00000005 +#define VGT_OUT_RECT_V3 0x00000006 +#define VGT_OUT_RESERVED 0x00000007 +#define VGT_TE_QUAD 0x00000008 +#define VGT_TE_PRIM_INDEX_LINE 0x00000009 +#define VGT_TE_PRIM_INDEX_TRI 0x0000000a +#define VGT_TE_PRIM_INDEX_QUAD 0x0000000b + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * GFX_COPY_STATE struct + */ + +#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1 + +#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0 + +#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 + +#define GFX_COPY_STATE_MASK \ + (GFX_COPY_STATE_SRC_STATE_ID_MASK) + +#define GFX_COPY_STATE(src_state_id) \ + ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)) + +#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \ + ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \ + gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 31; + } gfx_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int : 31; + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + } gfx_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + gfx_copy_state_t f; +} gfx_copy_state_u; + + +/* + * VGT_DRAW_INITIATOR struct + */ + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1 +#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11 +#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800 +#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000 +#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000 + +#define VGT_DRAW_INITIATOR_MASK \ + (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \ + VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \ + VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \ + VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \ + VGT_DRAW_INITIATOR_NOT_EOP_MASK | \ + VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \ + VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_NUM_INDICES_MASK) + +#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \ + ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \ + (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \ + (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \ + (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \ + (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \ + (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \ + (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \ + (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \ + (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)) + +#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int : 1; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + } vgt_draw_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int : 1; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + } vgt_draw_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_draw_initiator_t f; +} vgt_draw_initiator_u; + + +/* + * VGT_EVENT_INITIATOR struct + */ + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f + +#define VGT_EVENT_INITIATOR_MASK \ + (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) + +#define VGT_EVENT_INITIATOR(event_type) \ + ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)) + +#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \ + ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \ + vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + unsigned int : 26; + } vgt_event_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int : 26; + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + } vgt_event_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_event_initiator_t f; +} vgt_event_initiator_u; + + +/* + * VGT_DMA_BASE struct + */ + +#define VGT_DMA_BASE_BASE_ADDR_SIZE 32 + +#define VGT_DMA_BASE_BASE_ADDR_SHIFT 0 + +#define VGT_DMA_BASE_BASE_ADDR_MASK 0xffffffff + +#define VGT_DMA_BASE_MASK \ + (VGT_DMA_BASE_BASE_ADDR_MASK) + +#define VGT_DMA_BASE(base_addr) \ + ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)) + +#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \ + ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \ + vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_base_t f; +} vgt_dma_base_u; + + +/* + * VGT_DMA_SIZE struct + */ + +#define VGT_DMA_SIZE_NUM_WORDS_SIZE 24 +#define VGT_DMA_SIZE_SWAP_MODE_SIZE 2 + +#define VGT_DMA_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_DMA_SIZE_SWAP_MODE_SHIFT 30 + +#define VGT_DMA_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_DMA_SIZE_SWAP_MODE_MASK 0xc0000000 + +#define VGT_DMA_SIZE_MASK \ + (VGT_DMA_SIZE_NUM_WORDS_MASK | \ + VGT_DMA_SIZE_SWAP_MODE_MASK) + +#define VGT_DMA_SIZE(num_words, swap_mode) \ + ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \ + (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)) + +#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + } vgt_dma_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + } vgt_dma_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_size_t f; +} vgt_dma_size_u; + + +/* + * VGT_BIN_BASE struct + */ + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff + +#define VGT_BIN_BASE_MASK \ + (VGT_BIN_BASE_BIN_BASE_ADDR_MASK) + +#define VGT_BIN_BASE(bin_base_addr) \ + ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)) + +#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \ + ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \ + vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_base_t f; +} vgt_bin_base_u; + + +/* + * VGT_BIN_SIZE struct + */ + +#define VGT_BIN_SIZE_NUM_WORDS_SIZE 24 +#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1 +#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1 + +#define VGT_BIN_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30 +#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31 + +#define VGT_BIN_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000 +#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000 + +#define VGT_BIN_SIZE_MASK \ + (VGT_BIN_SIZE_NUM_WORDS_MASK | \ + VGT_BIN_SIZE_FACENESS_FETCH_MASK | \ + VGT_BIN_SIZE_FACENESS_RESET_MASK) + +#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \ + ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \ + (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \ + (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)) + +#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + } vgt_bin_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + } vgt_bin_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_size_t f; +} vgt_bin_size_u; + + +/* + * VGT_CURRENT_BIN_ID_MIN struct + */ + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MIN_MASK \ + (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_min_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + } vgt_current_bin_id_min_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_min_t f; +} vgt_current_bin_id_min_u; + + +/* + * VGT_CURRENT_BIN_ID_MAX struct + */ + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MAX_MASK \ + (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_max_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + } vgt_current_bin_id_max_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_max_t f; +} vgt_current_bin_id_max_u; + + +/* + * VGT_IMMED_DATA struct + */ + +#define VGT_IMMED_DATA_DATA_SIZE 32 + +#define VGT_IMMED_DATA_DATA_SHIFT 0 + +#define VGT_IMMED_DATA_DATA_MASK 0xffffffff + +#define VGT_IMMED_DATA_MASK \ + (VGT_IMMED_DATA_DATA_MASK) + +#define VGT_IMMED_DATA(data) \ + ((data << VGT_IMMED_DATA_DATA_SHIFT)) + +#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \ + ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT) + +#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \ + vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_immed_data_t f; +} vgt_immed_data_u; + + +/* + * VGT_MAX_VTX_INDX struct + */ + +#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24 + +#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0 + +#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff + +#define VGT_MAX_VTX_INDX_MASK \ + (VGT_MAX_VTX_INDX_MAX_INDX_MASK) + +#define VGT_MAX_VTX_INDX(max_indx) \ + ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)) + +#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \ + ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \ + vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + unsigned int : 8; + } vgt_max_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int : 8; + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + } vgt_max_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_max_vtx_indx_t f; +} vgt_max_vtx_indx_u; + + +/* + * VGT_MIN_VTX_INDX struct + */ + +#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24 + +#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0 + +#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff + +#define VGT_MIN_VTX_INDX_MASK \ + (VGT_MIN_VTX_INDX_MIN_INDX_MASK) + +#define VGT_MIN_VTX_INDX(min_indx) \ + ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)) + +#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \ + ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \ + vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + unsigned int : 8; + } vgt_min_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int : 8; + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + } vgt_min_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_min_vtx_indx_t f; +} vgt_min_vtx_indx_u; + + +/* + * VGT_INDX_OFFSET struct + */ + +#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24 + +#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0 + +#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff + +#define VGT_INDX_OFFSET_MASK \ + (VGT_INDX_OFFSET_INDX_OFFSET_MASK) + +#define VGT_INDX_OFFSET(indx_offset) \ + ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)) + +#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \ + ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \ + vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + unsigned int : 8; + } vgt_indx_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int : 8; + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + } vgt_indx_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_indx_offset_t f; +} vgt_indx_offset_u; + + +/* + * VGT_VERTEX_REUSE_BLOCK_CNTL struct + */ + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \ + (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \ + ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \ + ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \ + vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + unsigned int : 29; + } vgt_vertex_reuse_block_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int : 29; + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + } vgt_vertex_reuse_block_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vertex_reuse_block_cntl_t f; +} vgt_vertex_reuse_block_cntl_u; + + +/* + * VGT_OUT_DEALLOC_CNTL struct + */ + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003 + +#define VGT_OUT_DEALLOC_CNTL_MASK \ + (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) + +#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \ + ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)) + +#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \ + ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \ + vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + unsigned int : 30; + } vgt_out_dealloc_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int : 30; + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + } vgt_out_dealloc_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_out_dealloc_cntl_t f; +} vgt_out_dealloc_cntl_u; + + +/* + * VGT_MULTI_PRIM_IB_RESET_INDX struct + */ + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff + +#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \ + (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) + +#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \ + ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \ + ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \ + vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + unsigned int : 8; + } vgt_multi_prim_ib_reset_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int : 8; + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + } vgt_multi_prim_ib_reset_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_multi_prim_ib_reset_indx_t f; +} vgt_multi_prim_ib_reset_indx_u; + + +/* + * VGT_ENHANCE struct + */ + +#define VGT_ENHANCE_MISC_SIZE 16 + +#define VGT_ENHANCE_MISC_SHIFT 0 + +#define VGT_ENHANCE_MISC_MASK 0x0000ffff + +#define VGT_ENHANCE_MASK \ + (VGT_ENHANCE_MISC_MASK) + +#define VGT_ENHANCE(misc) \ + ((misc << VGT_ENHANCE_MISC_SHIFT)) + +#define VGT_ENHANCE_GET_MISC(vgt_enhance) \ + ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT) + +#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \ + vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + unsigned int : 16; + } vgt_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int : 16; + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + } vgt_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_enhance_t f; +} vgt_enhance_u; + + +/* + * VGT_VTX_VECT_EJECT_REG struct + */ + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f + +#define VGT_VTX_VECT_EJECT_REG_MASK \ + (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) + +#define VGT_VTX_VECT_EJECT_REG(prim_count) \ + ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)) + +#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \ + ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \ + vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + unsigned int : 27; + } vgt_vtx_vect_eject_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int : 27; + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + } vgt_vtx_vect_eject_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vtx_vect_eject_reg_t f; +} vgt_vtx_vect_eject_reg_u; + + +/* + * VGT_LAST_COPY_STATE struct + */ + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000 + +#define VGT_LAST_COPY_STATE_MASK \ + (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \ + VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) + +#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \ + ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \ + (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)) + +#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + } vgt_last_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + } vgt_last_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_last_copy_state_t f; +} vgt_last_copy_state_u; + + +/* + * VGT_DEBUG_CNTL struct + */ + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f + +#define VGT_DEBUG_CNTL_MASK \ + (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) + +#define VGT_DEBUG_CNTL(vgt_debug_indx) \ + ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)) + +#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \ + ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \ + vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + unsigned int : 27; + } vgt_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int : 27; + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + } vgt_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_cntl_t f; +} vgt_debug_cntl_u; + + +/* + * VGT_DEBUG_DATA struct + */ + +#define VGT_DEBUG_DATA_DATA_SIZE 32 + +#define VGT_DEBUG_DATA_DATA_SHIFT 0 + +#define VGT_DEBUG_DATA_DATA_MASK 0xffffffff + +#define VGT_DEBUG_DATA_MASK \ + (VGT_DEBUG_DATA_DATA_MASK) + +#define VGT_DEBUG_DATA(data) \ + ((data << VGT_DEBUG_DATA_DATA_SHIFT)) + +#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \ + ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT) + +#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \ + vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_data_t f; +} vgt_debug_data_u; + + +/* + * VGT_CNTL_STATUS struct + */ + +#define VGT_CNTL_STATUS_VGT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1 + +#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8 + +#define VGT_CNTL_STATUS_VGT_BUSY_MASK 0x00000001 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100 + +#define VGT_CNTL_STATUS_MASK \ + (VGT_CNTL_STATUS_VGT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) + +#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \ + ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \ + (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \ + (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \ + (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \ + (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \ + (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \ + (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \ + (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \ + (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)) + +#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int : 23; + } vgt_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int : 23; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + } vgt_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_cntl_status_t f; +} vgt_cntl_status_u; + + +/* + * VGT_DEBUG_REG0 struct + */ + +#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_out_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1 + +#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0 +#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2 +#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3 +#define VGT_DEBUG_REG0_out_busy_SHIFT 4 +#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5 +#define VGT_DEBUG_REG0_grp_busy_SHIFT 6 +#define VGT_DEBUG_REG0_dma_busy_SHIFT 7 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8 +#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11 +#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12 +#define VGT_DEBUG_REG0_vgt_busy_SHIFT 13 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16 + +#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001 +#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002 +#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004 +#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008 +#define VGT_DEBUG_REG0_out_busy_MASK 0x00000010 +#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020 +#define VGT_DEBUG_REG0_grp_busy_MASK 0x00000040 +#define VGT_DEBUG_REG0_dma_busy_MASK 0x00000080 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100 +#define VGT_DEBUG_REG0_rbiu_busy_MASK 0x00000200 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800 +#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000 +#define VGT_DEBUG_REG0_vgt_busy_MASK 0x00002000 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000 + +#define VGT_DEBUG_REG0_MASK \ + (VGT_DEBUG_REG0_te_grp_busy_MASK | \ + VGT_DEBUG_REG0_pt_grp_busy_MASK | \ + VGT_DEBUG_REG0_vr_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_out_busy_MASK | \ + VGT_DEBUG_REG0_grp_backend_busy_MASK | \ + VGT_DEBUG_REG0_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_busy_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_vgt_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_busy_MASK | \ + VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) + +#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \ + ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \ + (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \ + (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \ + (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \ + (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \ + (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \ + (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \ + (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \ + (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \ + (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \ + (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \ + (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \ + (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \ + (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \ + (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \ + (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \ + (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)) + +#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int : 15; + } vgt_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int : 15; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + } vgt_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg0_t f; +} vgt_debug_reg0_u; + + +/* + * VGT_DEBUG_REG1 struct + */ + +#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1 +#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_te_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1 +#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1 +#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1 +#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1 + +#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0 +#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3 +#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5 +#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7 +#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9 +#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10 +#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11 +#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12 +#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13 +#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14 +#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15 +#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16 +#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20 +#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28 +#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30 + +#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001 +#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002 +#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004 +#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008 +#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010 +#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020 +#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040 +#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080 +#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100 +#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200 +#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400 +#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800 +#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000 +#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000 +#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000 +#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000 +#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000 +#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000 +#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000 +#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000 + +#define VGT_DEBUG_REG1_MASK \ + (VGT_DEBUG_REG1_out_te_data_read_MASK | \ + VGT_DEBUG_REG1_te_out_data_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_prim_read_MASK | \ + VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_data_read_MASK | \ + VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_prim_read_MASK | \ + VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_indx_read_MASK | \ + VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_te_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_te_valid_MASK | \ + VGT_DEBUG_REG1_pt_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_pt_valid_MASK | \ + VGT_DEBUG_REG1_vr_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_vr_valid_MASK | \ + VGT_DEBUG_REG1_grp_dma_read_MASK | \ + VGT_DEBUG_REG1_dma_grp_valid_MASK | \ + VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \ + VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \ + VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_MH_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \ + VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_SQ_send_MASK | \ + VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) + +#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \ + ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \ + (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \ + (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \ + (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \ + (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \ + (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \ + (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \ + (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \ + (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \ + (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \ + (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \ + (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \ + (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \ + (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \ + (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \ + (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \ + (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \ + (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \ + (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \ + (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \ + (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \ + (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \ + (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \ + (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \ + (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \ + (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \ + (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \ + (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \ + (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \ + (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \ + (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)) + +#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int : 1; + } vgt_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + } vgt_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg1_t f; +} vgt_debug_reg1_u; + + +/* + * VGT_DEBUG_REG3 struct + */ + +#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002 + +#define VGT_DEBUG_REG3_MASK \ + (VGT_DEBUG_REG3_vgt_clk_en_MASK | \ + VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) + +#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \ + ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \ + (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)) + +#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int : 30; + } vgt_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int : 30; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + } vgt_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg3_t f; +} vgt_debug_reg3_u; + + +/* + * VGT_DEBUG_REG6 struct + */ + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG6_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_extract_vector_SIZE 1 +#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG6_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG6_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG6_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG6_MASK \ + (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG6_right_word_indx_q_MASK | \ + VGT_DEBUG_REG6_input_data_valid_MASK | \ + VGT_DEBUG_REG6_input_data_xfer_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG6_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG6_shifter_first_load_MASK | \ + VGT_DEBUG_REG6_di_state_sel_q_MASK | \ + VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG6_di_event_flag_q_MASK | \ + VGT_DEBUG_REG6_read_draw_initiator_MASK | \ + VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG6_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG6_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG6_extract_vector_MASK | \ + VGT_DEBUG_REG6_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG6_destination_rtr_MASK | \ + VGT_DEBUG_REG6_grp_trigger_MASK) + +#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int : 3; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + } vgt_debug_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg6_t f; +} vgt_debug_reg6_u; + + +/* + * VGT_DEBUG_REG7 struct + */ + +#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG7_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG7_MASK \ + (VGT_DEBUG_REG7_di_index_counter_q_MASK | \ + VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG7_shift_amount_extract_MASK | \ + VGT_DEBUG_REG7_di_prim_type_q_MASK | \ + VGT_DEBUG_REG7_current_source_sel_MASK) + +#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + } vgt_debug_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + } vgt_debug_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg7_t f; +} vgt_debug_reg7_u; + + +/* + * VGT_DEBUG_REG8 struct + */ + +#define VGT_DEBUG_REG8_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG8_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG8_MASK \ + (VGT_DEBUG_REG8_current_source_sel_MASK | \ + VGT_DEBUG_REG8_left_word_indx_q_MASK | \ + VGT_DEBUG_REG8_input_data_cnt_MASK | \ + VGT_DEBUG_REG8_input_data_lsw_MASK | \ + VGT_DEBUG_REG8_input_data_msw_MASK | \ + VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg8_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + } vgt_debug_reg8_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg8_t f; +} vgt_debug_reg8_u; + + +/* + * VGT_DEBUG_REG9 struct + */ + +#define VGT_DEBUG_REG9_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG9_MASK \ + (VGT_DEBUG_REG9_next_stride_q_MASK | \ + VGT_DEBUG_REG9_next_stride_d_MASK | \ + VGT_DEBUG_REG9_current_shift_q_MASK | \ + VGT_DEBUG_REG9_current_shift_d_MASK | \ + VGT_DEBUG_REG9_current_stride_q_MASK | \ + VGT_DEBUG_REG9_current_stride_d_MASK | \ + VGT_DEBUG_REG9_grp_trigger_MASK) + +#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg9_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int : 1; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + } vgt_debug_reg9_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg9_t f; +} vgt_debug_reg9_u; + + +/* + * VGT_DEBUG_REG10 struct + */ + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG10_bin_valid_SIZE 1 +#define VGT_DEBUG_REG10_read_block_SIZE 1 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1 +#define VGT_DEBUG_REG10_selected_data_SIZE 8 +#define VGT_DEBUG_REG10_mask_input_data_SIZE 8 +#define VGT_DEBUG_REG10_gap_q_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1 +#define VGT_DEBUG_REG10_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3 +#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4 +#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5 +#define VGT_DEBUG_REG10_bin_valid_SHIFT 6 +#define VGT_DEBUG_REG10_read_block_SHIFT 7 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8 +#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10 +#define VGT_DEBUG_REG10_selected_data_SHIFT 11 +#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19 +#define VGT_DEBUG_REG10_gap_q_SHIFT 27 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30 +#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008 +#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010 +#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020 +#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040 +#define VGT_DEBUG_REG10_read_block_MASK 0x00000080 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100 +#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200 +#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400 +#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800 +#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000 +#define VGT_DEBUG_REG10_gap_q_MASK 0x08000000 +#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000 +#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000 +#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000 +#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG10_MASK \ + (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_di_state_sel_q_MASK | \ + VGT_DEBUG_REG10_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG10_bin_valid_MASK | \ + VGT_DEBUG_REG10_read_block_MASK | \ + VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \ + VGT_DEBUG_REG10_last_bit_enable_q_MASK | \ + VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \ + VGT_DEBUG_REG10_selected_data_MASK | \ + VGT_DEBUG_REG10_mask_input_data_MASK | \ + VGT_DEBUG_REG10_gap_q_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \ + VGT_DEBUG_REG10_grp_trigger_MASK) + +#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \ + ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \ + (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \ + (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \ + (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \ + (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \ + (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \ + (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \ + (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \ + (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \ + (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \ + (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \ + (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \ + (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \ + (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \ + (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + } vgt_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + } vgt_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg10_t f; +} vgt_debug_reg10_u; + + +/* + * VGT_DEBUG_REG12 struct + */ + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG12_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_extract_vector_SIZE 1 +#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG12_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG12_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG12_MASK \ + (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG12_right_word_indx_q_MASK | \ + VGT_DEBUG_REG12_input_data_valid_MASK | \ + VGT_DEBUG_REG12_input_data_xfer_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG12_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG12_shifter_first_load_MASK | \ + VGT_DEBUG_REG12_di_state_sel_q_MASK | \ + VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG12_di_event_flag_q_MASK | \ + VGT_DEBUG_REG12_read_draw_initiator_MASK | \ + VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG12_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG12_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG12_extract_vector_MASK | \ + VGT_DEBUG_REG12_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG12_destination_rtr_MASK | \ + VGT_DEBUG_REG12_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int : 3; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + } vgt_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg12_t f; +} vgt_debug_reg12_u; + + +/* + * VGT_DEBUG_REG13 struct + */ + +#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG13_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG13_MASK \ + (VGT_DEBUG_REG13_di_index_counter_q_MASK | \ + VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG13_shift_amount_extract_MASK | \ + VGT_DEBUG_REG13_di_prim_type_q_MASK | \ + VGT_DEBUG_REG13_current_source_sel_MASK) + +#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + } vgt_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + } vgt_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg13_t f; +} vgt_debug_reg13_u; + + +/* + * VGT_DEBUG_REG14 struct + */ + +#define VGT_DEBUG_REG14_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG14_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG14_MASK \ + (VGT_DEBUG_REG14_current_source_sel_MASK | \ + VGT_DEBUG_REG14_left_word_indx_q_MASK | \ + VGT_DEBUG_REG14_input_data_cnt_MASK | \ + VGT_DEBUG_REG14_input_data_lsw_MASK | \ + VGT_DEBUG_REG14_input_data_msw_MASK | \ + VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + } vgt_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg14_t f; +} vgt_debug_reg14_u; + + +/* + * VGT_DEBUG_REG15 struct + */ + +#define VGT_DEBUG_REG15_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG15_MASK \ + (VGT_DEBUG_REG15_next_stride_q_MASK | \ + VGT_DEBUG_REG15_next_stride_d_MASK | \ + VGT_DEBUG_REG15_current_shift_q_MASK | \ + VGT_DEBUG_REG15_current_shift_d_MASK | \ + VGT_DEBUG_REG15_current_stride_q_MASK | \ + VGT_DEBUG_REG15_current_stride_d_MASK | \ + VGT_DEBUG_REG15_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int : 1; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + } vgt_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg15_t f; +} vgt_debug_reg15_u; + + +/* + * VGT_DEBUG_REG16 struct + */ + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1 +#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1 +#define VGT_DEBUG_REG16_current_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_en_SIZE 1 +#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1 +#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9 +#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10 +#define VGT_DEBUG_REG16_current_state_q_SHIFT 11 +#define VGT_DEBUG_REG16_old_state_q_SHIFT 12 +#define VGT_DEBUG_REG16_old_state_en_SHIFT 13 +#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15 +#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17 +#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30 +#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200 +#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400 +#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800 +#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000 +#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000 +#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000 +#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000 +#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000 +#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000 +#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000 +#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG16_MASK \ + (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \ + VGT_DEBUG_REG16_rst_last_bit_MASK | \ + VGT_DEBUG_REG16_current_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_en_MASK | \ + VGT_DEBUG_REG16_prev_last_bit_q_MASK | \ + VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \ + VGT_DEBUG_REG16_last_bit_block_q_MASK | \ + VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \ + VGT_DEBUG_REG16_load_empty_reg_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \ + VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \ + VGT_DEBUG_REG16_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \ + ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \ + (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \ + (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \ + (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \ + (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \ + (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \ + (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \ + (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \ + (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \ + (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \ + (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \ + (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \ + (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \ + (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \ + (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \ + (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \ + (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \ + (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \ + (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \ + (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \ + (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + } vgt_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + } vgt_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg16_t f; +} vgt_debug_reg16_u; + + +/* + * VGT_DEBUG_REG17 struct + */ + +#define VGT_DEBUG_REG17_save_read_q_SIZE 1 +#define VGT_DEBUG_REG17_extend_read_q_SIZE 1 +#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2 +#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1 +#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1 +#define VGT_DEBUG_REG17_check_second_reg_SIZE 1 +#define VGT_DEBUG_REG17_check_first_reg_SIZE 1 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1 +#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG17_save_read_q_SHIFT 0 +#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1 +#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2 +#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4 +#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5 +#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6 +#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7 +#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8 +#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14 +#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15 +#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24 +#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001 +#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002 +#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c +#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010 +#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020 +#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040 +#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080 +#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100 +#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000 +#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000 +#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000 +#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000 +#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000 +#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG17_MASK \ + (VGT_DEBUG_REG17_save_read_q_MASK | \ + VGT_DEBUG_REG17_extend_read_q_MASK | \ + VGT_DEBUG_REG17_grp_indx_size_MASK | \ + VGT_DEBUG_REG17_cull_prim_true_MASK | \ + VGT_DEBUG_REG17_reset_bit2_q_MASK | \ + VGT_DEBUG_REG17_reset_bit1_q_MASK | \ + VGT_DEBUG_REG17_first_reg_first_q_MASK | \ + VGT_DEBUG_REG17_check_second_reg_MASK | \ + VGT_DEBUG_REG17_check_first_reg_MASK | \ + VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \ + VGT_DEBUG_REG17_to_second_reg_q_MASK | \ + VGT_DEBUG_REG17_roll_over_msk_q_MASK | \ + VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \ + ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \ + (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \ + (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \ + (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \ + (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \ + (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \ + (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \ + (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \ + (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \ + (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \ + (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \ + (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \ + (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \ + (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \ + (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \ + (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \ + (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \ + (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + } vgt_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + } vgt_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg17_t f; +} vgt_debug_reg17_u; + + +/* + * VGT_DEBUG_REG18 struct + */ + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_start_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1 +#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13 +#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15 +#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16 +#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17 +#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20 +#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21 +#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22 +#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23 +#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24 +#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26 +#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27 +#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28 +#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000 +#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000 +#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000 +#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000 +#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000 +#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000 +#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000 +#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000 +#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000 +#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000 +#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000 +#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000 +#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000 +#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000 + +#define VGT_DEBUG_REG18_MASK \ + (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG18_dma_mem_full_MASK | \ + VGT_DEBUG_REG18_dma_ram_re_MASK | \ + VGT_DEBUG_REG18_dma_ram_we_MASK | \ + VGT_DEBUG_REG18_dma_mem_empty_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \ + VGT_DEBUG_REG18_bin_mem_full_MASK | \ + VGT_DEBUG_REG18_bin_ram_we_MASK | \ + VGT_DEBUG_REG18_bin_ram_re_MASK | \ + VGT_DEBUG_REG18_bin_mem_empty_MASK | \ + VGT_DEBUG_REG18_start_bin_req_MASK | \ + VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \ + VGT_DEBUG_REG18_dma_req_xfer_MASK | \ + VGT_DEBUG_REG18_have_valid_bin_req_MASK | \ + VGT_DEBUG_REG18_have_valid_dma_req_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) + +#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \ + ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \ + (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \ + (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \ + (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \ + (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \ + (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \ + (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \ + (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \ + (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \ + (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \ + (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \ + (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \ + (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \ + (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \ + (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \ + (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \ + (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \ + (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \ + (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)) + +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + } vgt_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + } vgt_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg18_t f; +} vgt_debug_reg18_u; + + +/* + * VGT_DEBUG_REG20 struct + */ + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_sent_cnt_SIZE 4 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5 +#define VGT_DEBUG_REG20_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5 +#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6 +#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7 +#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8 +#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9 +#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10 +#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11 +#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12 +#define VGT_DEBUG_REG20_hold_prim_SHIFT 13 +#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21 +#define VGT_DEBUG_REG20_out_trigger_SHIFT 26 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004 +#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020 +#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040 +#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080 +#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100 +#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200 +#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400 +#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800 +#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000 +#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000 +#define VGT_DEBUG_REG20_sent_cnt_MASK 0x0003c000 +#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000 +#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000 +#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000 + +#define VGT_DEBUG_REG20_MASK \ + (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \ + VGT_DEBUG_REG20_prim_buffer_empty_MASK | \ + VGT_DEBUG_REG20_prim_buffer_re_MASK | \ + VGT_DEBUG_REG20_prim_buffer_we_MASK | \ + VGT_DEBUG_REG20_prim_buffer_full_MASK | \ + VGT_DEBUG_REG20_indx_buffer_empty_MASK | \ + VGT_DEBUG_REG20_indx_buffer_re_MASK | \ + VGT_DEBUG_REG20_indx_buffer_we_MASK | \ + VGT_DEBUG_REG20_indx_buffer_full_MASK | \ + VGT_DEBUG_REG20_hold_prim_MASK | \ + VGT_DEBUG_REG20_sent_cnt_MASK | \ + VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \ + VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \ + VGT_DEBUG_REG20_out_trigger_MASK) + +#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \ + ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \ + (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \ + (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \ + (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \ + (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \ + (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \ + (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \ + (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \ + (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \ + (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \ + (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \ + (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \ + (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \ + (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \ + (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \ + (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \ + (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \ + (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \ + (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT) + +#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int : 5; + } vgt_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int : 5; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + } vgt_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg20_t f; +} vgt_debug_reg20_u; + + +/* + * VGT_DEBUG_REG21 struct + */ + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3 +#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4 +#define VGT_DEBUG_REG21_new_packet_q_SIZE 1 +#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1 +#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1 +#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1 +#define VGT_DEBUG_REG21_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1 +#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14 +#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18 +#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22 +#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25 +#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26 +#define VGT_DEBUG_REG21_out_trigger_SHIFT 31 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e +#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380 +#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000 +#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000 +#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000 +#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000 +#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000 +#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000 +#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG21_MASK \ + (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \ + VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \ + VGT_DEBUG_REG21_alloc_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \ + VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \ + VGT_DEBUG_REG21_new_packet_q_MASK | \ + VGT_DEBUG_REG21_new_allocate_q_MASK | \ + VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \ + VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \ + VGT_DEBUG_REG21_insert_null_prim_MASK | \ + VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \ + VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \ + VGT_DEBUG_REG21_buffered_thread_size_MASK | \ + VGT_DEBUG_REG21_out_trigger_MASK) + +#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \ + ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \ + (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \ + (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \ + (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \ + (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \ + (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \ + (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \ + (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \ + (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \ + (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \ + (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \ + (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \ + (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \ + (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT) + +#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int : 4; + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + } vgt_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + unsigned int : 4; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + } vgt_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg21_t f; +} vgt_debug_reg21_u; + + +/* + * VGT_CRC_SQ_DATA struct + */ + +#define VGT_CRC_SQ_DATA_CRC_SIZE 32 + +#define VGT_CRC_SQ_DATA_CRC_SHIFT 0 + +#define VGT_CRC_SQ_DATA_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_DATA_MASK \ + (VGT_CRC_SQ_DATA_CRC_MASK) + +#define VGT_CRC_SQ_DATA(crc) \ + ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT)) + +#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \ + ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT) + +#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \ + vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_data_t f; +} vgt_crc_sq_data_u; + + +/* + * VGT_CRC_SQ_CTRL struct + */ + +#define VGT_CRC_SQ_CTRL_CRC_SIZE 32 + +#define VGT_CRC_SQ_CTRL_CRC_SHIFT 0 + +#define VGT_CRC_SQ_CTRL_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_CTRL_MASK \ + (VGT_CRC_SQ_CTRL_CRC_MASK) + +#define VGT_CRC_SQ_CTRL(crc) \ + ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)) + +#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \ + ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \ + vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_ctrl_t f; +} vgt_crc_sq_ctrl_u; + + +/* + * VGT_PERFCOUNTER0_SELECT struct + */ + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER0_SELECT_MASK \ + (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \ + ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \ + vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_select_t f; +} vgt_perfcounter0_select_u; + + +/* + * VGT_PERFCOUNTER1_SELECT struct + */ + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER1_SELECT_MASK \ + (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \ + ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \ + vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_select_t f; +} vgt_perfcounter1_select_u; + + +/* + * VGT_PERFCOUNTER2_SELECT struct + */ + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER2_SELECT_MASK \ + (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \ + ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \ + vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_select_t f; +} vgt_perfcounter2_select_u; + + +/* + * VGT_PERFCOUNTER3_SELECT struct + */ + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER3_SELECT_MASK \ + (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \ + ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \ + vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_select_t f; +} vgt_perfcounter3_select_u; + + +/* + * VGT_PERFCOUNTER0_LOW struct + */ + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER0_LOW_MASK \ + (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \ + ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \ + vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_low_t f; +} vgt_perfcounter0_low_u; + + +/* + * VGT_PERFCOUNTER1_LOW struct + */ + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER1_LOW_MASK \ + (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \ + ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \ + vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_low_t f; +} vgt_perfcounter1_low_u; + + +/* + * VGT_PERFCOUNTER2_LOW struct + */ + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER2_LOW_MASK \ + (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \ + ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \ + vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_low_t f; +} vgt_perfcounter2_low_u; + + +/* + * VGT_PERFCOUNTER3_LOW struct + */ + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER3_LOW_MASK \ + (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \ + ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \ + vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_low_t f; +} vgt_perfcounter3_low_u; + + +/* + * VGT_PERFCOUNTER0_HI struct + */ + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER0_HI_MASK \ + (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \ + ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \ + vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } vgt_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_hi_t f; +} vgt_perfcounter0_hi_u; + + +/* + * VGT_PERFCOUNTER1_HI struct + */ + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER1_HI_MASK \ + (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \ + ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \ + vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } vgt_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_hi_t f; +} vgt_perfcounter1_hi_u; + + +/* + * VGT_PERFCOUNTER2_HI struct + */ + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER2_HI_MASK \ + (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \ + ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \ + vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } vgt_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_hi_t f; +} vgt_perfcounter2_hi_u; + + +/* + * VGT_PERFCOUNTER3_HI struct + */ + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER3_HI_MASK \ + (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \ + ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \ + vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } vgt_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_hi_t f; +} vgt_perfcounter3_hi_u; + + +#endif + + +#if !defined (_SQ_FIDDLE_H) +#define _SQ_FIDDLE_H + +/***************************************************************************************************************** + * + * sq_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * SQ_GPR_MANAGEMENT struct + */ + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000 + +#define SQ_GPR_MANAGEMENT_MASK \ + (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) + +#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \ + ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \ + (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \ + (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)) + +#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + unsigned int : 3; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 1; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 13; + } sq_gpr_management_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int : 13; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 1; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 3; + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + } sq_gpr_management_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_gpr_management_t f; +} sq_gpr_management_u; + + +/* + * SQ_FLOW_CONTROL struct + */ + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1 +#define SQ_FLOW_CONTROL_ONE_ALU_SIZE 1 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4 +#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE 1 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0 +#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4 +#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT 8 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12 +#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003 +#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010 +#define SQ_FLOW_CONTROL_ONE_ALU_MASK 0x00000100 +#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000 +#define SQ_FLOW_CONTROL_NO_PV_PS_MASK 0x00010000 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000 + +#define SQ_FLOW_CONTROL_MASK \ + (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ONE_THREAD_MASK | \ + SQ_FLOW_CONTROL_ONE_ALU_MASK | \ + SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \ + SQ_FLOW_CONTROL_NO_PV_PS_MASK | \ + SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \ + SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \ + SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \ + SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \ + SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \ + SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \ + SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) + +#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \ + ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \ + (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \ + (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \ + (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \ + (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \ + (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \ + (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \ + (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \ + (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \ + (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \ + (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \ + (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \ + (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \ + (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \ + (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)) + +#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + unsigned int : 2; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int : 4; + } sq_flow_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int : 4; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 2; + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + } sq_flow_control_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_flow_control_t f; +} sq_flow_control_u; + + +/* + * SQ_INST_STORE_MANAGMENT struct + */ + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000 + +#define SQ_INST_STORE_MANAGMENT_MASK \ + (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \ + SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) + +#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \ + ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \ + (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)) + +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + } sq_inst_store_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + } sq_inst_store_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_inst_store_managment_t f; +} sq_inst_store_managment_u; + + +/* + * SQ_RESOURCE_MANAGMENT struct + */ + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000 + +#define SQ_RESOURCE_MANAGMENT_MASK \ + (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) + +#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \ + ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \ + (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \ + (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)) + +#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int : 7; + } sq_resource_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int : 7; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + } sq_resource_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_resource_managment_t f; +} sq_resource_managment_u; + + +/* + * SQ_EO_RT struct + */ + +#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE 8 +#define SQ_EO_RT_EO_TSTATE_RT_SIZE 8 + +#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0 +#define SQ_EO_RT_EO_TSTATE_RT_SHIFT 16 + +#define SQ_EO_RT_EO_CONSTANTS_RT_MASK 0x000000ff +#define SQ_EO_RT_EO_TSTATE_RT_MASK 0x00ff0000 + +#define SQ_EO_RT_MASK \ + (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \ + SQ_EO_RT_EO_TSTATE_RT_MASK) + +#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \ + ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \ + (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)) + +#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + } sq_eo_rt_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + } sq_eo_rt_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_eo_rt_t f; +} sq_eo_rt_u; + + +/* + * SQ_DEBUG_MISC struct + */ + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8 +#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1 +#define SQ_DEBUG_MISC_RESERVED_SIZE 2 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12 +#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20 +#define SQ_DEBUG_MISC_RESERVED_SHIFT 21 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000 +#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000 +#define SQ_DEBUG_MISC_RESERVED_MASK 0x00600000 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000 + +#define SQ_DEBUG_MISC_MASK \ + (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_READ_CTX_MASK | \ + SQ_DEBUG_MISC_RESERVED_MASK | \ + SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) + +#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \ + ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \ + (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \ + (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \ + (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \ + (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \ + (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \ + (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \ + (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \ + (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)) + +#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + unsigned int : 1; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int : 3; + } sq_debug_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int : 3; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int : 1; + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + } sq_debug_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_t f; +} sq_debug_misc_u; + + +/* + * SQ_ACTIVITY_METER_CNTL struct + */ + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000 +#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000 + +#define SQ_ACTIVITY_METER_CNTL_MASK \ + (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \ + SQ_ACTIVITY_METER_CNTL_SPARE_MASK) + +#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \ + ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \ + (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \ + (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \ + (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)) + +#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + } sq_activity_meter_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + } sq_activity_meter_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_cntl_t f; +} sq_activity_meter_cntl_u; + + +/* + * SQ_ACTIVITY_METER_STATUS struct + */ + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff + +#define SQ_ACTIVITY_METER_STATUS_MASK \ + (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) + +#define SQ_ACTIVITY_METER_STATUS(percent_busy) \ + ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)) + +#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \ + ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \ + sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + unsigned int : 24; + } sq_activity_meter_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int : 24; + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + } sq_activity_meter_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_status_t f; +} sq_activity_meter_status_u; + + +/* + * SQ_INPUT_ARB_PRIORITY struct + */ + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 + +#define SQ_INPUT_ARB_PRIORITY_MASK \ + (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) + +#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \ + ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)) + +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int : 14; + } sq_input_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int : 14; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_input_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_input_arb_priority_t f; +} sq_input_arb_priority_u; + + +/* + * SQ_THREAD_ARB_PRIORITY struct + */ + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000 + +#define SQ_THREAD_ARB_PRIORITY_MASK \ + (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \ + SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \ + SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) + +#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \ + ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \ + (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \ + (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \ + (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \ + (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)) + +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int : 9; + } sq_thread_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int : 9; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_thread_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_thread_arb_priority_t f; +} sq_thread_arb_priority_u; + + +/* + * SQ_VS_WATCHDOG_TIMER struct + */ + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_VS_WATCHDOG_TIMER_MASK \ + (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_vs_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_vs_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_watchdog_timer_t f; +} sq_vs_watchdog_timer_u; + + +/* + * SQ_PS_WATCHDOG_TIMER struct + */ + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_PS_WATCHDOG_TIMER_MASK \ + (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_ps_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_ps_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_watchdog_timer_t f; +} sq_ps_watchdog_timer_u; + + +/* + * SQ_INT_CNTL struct + */ + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002 + +#define SQ_INT_CNTL_MASK \ + (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \ + SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) + +#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \ + ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \ + (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)) + +#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int : 30; + } sq_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int : 30; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + } sq_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_cntl_t f; +} sq_int_cntl_u; + + +/* + * SQ_INT_STATUS struct + */ + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002 + +#define SQ_INT_STATUS_MASK \ + (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \ + SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) + +#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \ + ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \ + (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)) + +#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int : 30; + } sq_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int : 30; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + } sq_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_status_t f; +} sq_int_status_u; + + +/* + * SQ_INT_ACK struct + */ + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002 + +#define SQ_INT_ACK_MASK \ + (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \ + SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) + +#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \ + ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \ + (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)) + +#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int : 30; + } sq_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int : 30; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + } sq_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_ack_t f; +} sq_int_ack_u; + + +/* + * SQ_DEBUG_INPUT_FSM struct + */ + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007 +#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK 0x00007000 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000 + +#define SQ_DEBUG_INPUT_FSM_MASK \ + (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \ + SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) + +#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \ + ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \ + (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \ + (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \ + (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \ + (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \ + (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \ + (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \ + (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)) + +#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int : 4; + } sq_debug_input_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int : 4; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + } sq_debug_input_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_input_fsm_t f; +} sq_debug_input_fsm_u; + + +/* + * SQ_DEBUG_CONST_MGR_FSM struct + */ + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000 + +#define SQ_DEBUG_CONST_MGR_FSM_MASK \ + (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) + +#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \ + ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \ + (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \ + (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \ + (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \ + (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \ + (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \ + (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \ + (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \ + (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \ + (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)) + +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int : 8; + } sq_debug_const_mgr_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int : 8; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + } sq_debug_const_mgr_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_const_mgr_fsm_t f; +} sq_debug_const_mgr_fsm_u; + + +/* + * SQ_DEBUG_TP_FSM struct + */ + +#define SQ_DEBUG_TP_FSM_EX_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1 +#define SQ_DEBUG_TP_FSM_CF_TP_SIZE 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2 +#define SQ_DEBUG_TP_FSM_GS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3 + +#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT 0 +#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3 +#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT 8 +#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT 12 +#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14 +#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT 16 +#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18 +#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT 20 +#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22 +#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT 24 +#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28 + +#define SQ_DEBUG_TP_FSM_EX_TP_MASK 0x00000007 +#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_TP_FSM_CF_TP_MASK 0x000000f0 +#define SQ_DEBUG_TP_FSM_IF_TP_MASK 0x00000700 +#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_TP_FSM_TIS_TP_MASK 0x00003000 +#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000 +#define SQ_DEBUG_TP_FSM_GS_TP_MASK 0x00030000 +#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000 +#define SQ_DEBUG_TP_FSM_FCR_TP_MASK 0x00300000 +#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000 +#define SQ_DEBUG_TP_FSM_FCS_TP_MASK 0x03000000 +#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000 + +#define SQ_DEBUG_TP_FSM_MASK \ + (SQ_DEBUG_TP_FSM_EX_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED0_MASK | \ + SQ_DEBUG_TP_FSM_CF_TP_MASK | \ + SQ_DEBUG_TP_FSM_IF_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED1_MASK | \ + SQ_DEBUG_TP_FSM_TIS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED2_MASK | \ + SQ_DEBUG_TP_FSM_GS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED3_MASK | \ + SQ_DEBUG_TP_FSM_FCR_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED4_MASK | \ + SQ_DEBUG_TP_FSM_FCS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED5_MASK | \ + SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) + +#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \ + ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \ + (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \ + (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \ + (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \ + (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \ + (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \ + (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \ + (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \ + (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \ + (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \ + (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \ + (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \ + (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \ + (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)) + +#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int : 1; + } sq_debug_tp_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int : 1; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + } sq_debug_tp_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tp_fsm_t f; +} sq_debug_tp_fsm_u; + + +/* + * SQ_DEBUG_FSM_ALU_0 struct + */ + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_0_MASK \ + (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_0_t f; +} sq_debug_fsm_alu_0_u; + + +/* + * SQ_DEBUG_FSM_ALU_1 struct + */ + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_1_MASK \ + (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_1_t f; +} sq_debug_fsm_alu_1_u; + + +/* + * SQ_DEBUG_EXP_ALLOC struct + */ + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000 + +#define SQ_DEBUG_EXP_ALLOC_MASK \ + (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \ + SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) + +#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \ + ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \ + (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \ + (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \ + (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \ + (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)) + +#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int : 10; + } sq_debug_exp_alloc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int : 10; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + } sq_debug_exp_alloc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_exp_alloc_t f; +} sq_debug_exp_alloc_u; + + +/* + * SQ_DEBUG_PTR_BUFF struct + */ + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000 + +#define SQ_DEBUG_PTR_BUFF_MASK \ + (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \ + SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \ + SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \ + SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \ + SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \ + SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) + +#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \ + ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \ + (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \ + (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \ + (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \ + (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \ + (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \ + (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \ + (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \ + (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)) + +#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int : 4; + } sq_debug_ptr_buff_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int : 4; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + } sq_debug_ptr_buff_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_ptr_buff_t f; +} sq_debug_ptr_buff_u; + + +/* + * SQ_DEBUG_GPR_VTX struct + */ + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_VTX_MASK \ + (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) + +#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \ + ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \ + (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \ + (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \ + (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_vtx_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int : 1; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + } sq_debug_gpr_vtx_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_vtx_t f; +} sq_debug_gpr_vtx_u; + + +/* + * SQ_DEBUG_GPR_PIX struct + */ + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_PIX_MASK \ + (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) + +#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \ + ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \ + (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \ + (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \ + (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_pix_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int : 1; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + } sq_debug_gpr_pix_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_pix_t f; +} sq_debug_gpr_pix_u; + + +/* + * SQ_DEBUG_TB_STATUS_SEL struct + */ + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000 + +#define SQ_DEBUG_TB_STATUS_SEL_MASK \ + (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) + +#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \ + ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \ + (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \ + (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \ + (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \ + (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)) + +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int : 1; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + } sq_debug_tb_status_sel_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int : 1; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + } sq_debug_tb_status_sel_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tb_status_sel_t f; +} sq_debug_tb_status_sel_u; + + +/* + * SQ_DEBUG_VTX_TB_0 struct + */ + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE 1 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK 0x00200000 + +#define SQ_DEBUG_VTX_TB_0_MASK \ + (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \ + SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) + +#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \ + ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \ + (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \ + (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \ + (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \ + (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \ + (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \ + (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)) + +#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int : 10; + } sq_debug_vtx_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int : 10; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + } sq_debug_vtx_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_0_t f; +} sq_debug_vtx_tb_0_u; + + +/* + * SQ_DEBUG_VTX_TB_1 struct + */ + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff + +#define SQ_DEBUG_VTX_TB_1_MASK \ + (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) + +#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \ + ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)) + +#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \ + ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \ + sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + unsigned int : 16; + } sq_debug_vtx_tb_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int : 16; + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + } sq_debug_vtx_tb_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_1_t f; +} sq_debug_vtx_tb_1_u; + + +/* + * SQ_DEBUG_VTX_TB_STATUS_REG struct + */ + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \ + (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) + +#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \ + ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \ + ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \ + sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_status_reg_t f; +} sq_debug_vtx_tb_status_reg_u; + + +/* + * SQ_DEBUG_VTX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) + +#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \ + ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \ + ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \ + sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_state_mem_t f; +} sq_debug_vtx_tb_state_mem_u; + + +/* + * SQ_DEBUG_PIX_TB_0 struct + */ + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE 1 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25 +#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT 31 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000 +#define SQ_DEBUG_PIX_TB_0_BUSY_MASK 0x80000000 + +#define SQ_DEBUG_PIX_TB_0_MASK \ + (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_BUSY_MASK) + +#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \ + ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \ + (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \ + (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \ + (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \ + (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \ + (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)) + +#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + } sq_debug_pix_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + } sq_debug_pix_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_0_t f; +} sq_debug_pix_tb_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \ + ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \ + ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \ + sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_0_t f; +} sq_debug_pix_tb_status_reg_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \ + ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \ + ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \ + sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_1_t f; +} sq_debug_pix_tb_status_reg_1_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \ + ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \ + ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \ + sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_2_t f; +} sq_debug_pix_tb_status_reg_2_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \ + ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \ + ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \ + sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_3_t f; +} sq_debug_pix_tb_status_reg_3_u; + + +/* + * SQ_DEBUG_PIX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) + +#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \ + ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \ + ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \ + sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_state_mem_t f; +} sq_debug_pix_tb_state_mem_u; + + +/* + * SQ_PERFCOUNTER0_SELECT struct + */ + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER0_SELECT_MASK \ + (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \ + ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \ + sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sq_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_select_t f; +} sq_perfcounter0_select_u; + + +/* + * SQ_PERFCOUNTER1_SELECT struct + */ + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER1_SELECT_MASK \ + (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \ + ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \ + sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } sq_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_select_t f; +} sq_perfcounter1_select_u; + + +/* + * SQ_PERFCOUNTER2_SELECT struct + */ + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER2_SELECT_MASK \ + (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \ + ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \ + sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } sq_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_select_t f; +} sq_perfcounter2_select_u; + + +/* + * SQ_PERFCOUNTER3_SELECT struct + */ + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER3_SELECT_MASK \ + (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \ + ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \ + sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } sq_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_select_t f; +} sq_perfcounter3_select_u; + + +/* + * SQ_PERFCOUNTER0_LOW struct + */ + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER0_LOW_MASK \ + (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \ + ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \ + sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_low_t f; +} sq_perfcounter0_low_u; + + +/* + * SQ_PERFCOUNTER0_HI struct + */ + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER0_HI_MASK \ + (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \ + ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \ + sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sq_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_hi_t f; +} sq_perfcounter0_hi_u; + + +/* + * SQ_PERFCOUNTER1_LOW struct + */ + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER1_LOW_MASK \ + (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \ + ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \ + sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_low_t f; +} sq_perfcounter1_low_u; + + +/* + * SQ_PERFCOUNTER1_HI struct + */ + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER1_HI_MASK \ + (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \ + ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \ + sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } sq_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_hi_t f; +} sq_perfcounter1_hi_u; + + +/* + * SQ_PERFCOUNTER2_LOW struct + */ + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER2_LOW_MASK \ + (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \ + ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \ + sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_low_t f; +} sq_perfcounter2_low_u; + + +/* + * SQ_PERFCOUNTER2_HI struct + */ + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER2_HI_MASK \ + (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \ + ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \ + sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } sq_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_hi_t f; +} sq_perfcounter2_hi_u; + + +/* + * SQ_PERFCOUNTER3_LOW struct + */ + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER3_LOW_MASK \ + (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \ + ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \ + sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_low_t f; +} sq_perfcounter3_low_u; + + +/* + * SQ_PERFCOUNTER3_HI struct + */ + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER3_HI_MASK \ + (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \ + ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \ + sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } sq_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_hi_t f; +} sq_perfcounter3_hi_u; + + +/* + * SX_PERFCOUNTER0_SELECT struct + */ + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SX_PERFCOUNTER0_SELECT_MASK \ + (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SX_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \ + ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \ + sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sx_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sx_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_select_t f; +} sx_perfcounter0_select_u; + + +/* + * SX_PERFCOUNTER0_LOW struct + */ + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SX_PERFCOUNTER0_LOW_MASK \ + (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \ + ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \ + sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_low_t f; +} sx_perfcounter0_low_u; + + +/* + * SX_PERFCOUNTER0_HI struct + */ + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SX_PERFCOUNTER0_HI_MASK \ + (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \ + ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \ + sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sx_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sx_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_hi_t f; +} sx_perfcounter0_hi_u; + + +/* + * SQ_INSTRUCTION_ALU_0 struct + */ + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000 + +#define SQ_INSTRUCTION_ALU_0_MASK \ + (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) + +#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \ + ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \ + (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \ + (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \ + (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \ + (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \ + (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \ + (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \ + (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \ + (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \ + (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \ + (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + } sq_instruction_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + } sq_instruction_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_0_t f; +} sq_instruction_alu_0_u; + + +/* + * SQ_INSTRUCTION_ALU_1 struct + */ + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_1_MASK \ + (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \ + SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) + +#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \ + ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \ + (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \ + (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \ + (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \ + (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \ + (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \ + (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \ + (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \ + (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \ + (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \ + (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \ + (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \ + (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \ + (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \ + (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \ + (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \ + (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \ + (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)) + +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + } sq_instruction_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + } sq_instruction_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_1_t f; +} sq_instruction_alu_1_u; + + +/* + * SQ_INSTRUCTION_ALU_2 struct + */ + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_2_MASK \ + (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \ + SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) + +#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \ + ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \ + (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \ + (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \ + (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \ + (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \ + (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \ + (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \ + (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \ + (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \ + (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \ + (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \ + (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \ + (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)) + +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + } sq_instruction_alu_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + } sq_instruction_alu_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_2_t f; +} sq_instruction_alu_2_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_0 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_0_MASK \ + (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \ + ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \ + (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + } sq_instruction_cf_exec_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + } sq_instruction_cf_exec_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_0_t f; +} sq_instruction_cf_exec_0_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_1 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_1_MASK \ + (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \ + ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + } sq_instruction_cf_exec_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + } sq_instruction_cf_exec_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_1_t f; +} sq_instruction_cf_exec_1_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_2 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_EXEC_2_MASK \ + (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \ + ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \ + (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + } sq_instruction_cf_exec_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + } sq_instruction_cf_exec_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_2_t f; +} sq_instruction_cf_exec_2_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_0 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000 + +#define SQ_INSTRUCTION_CF_LOOP_0_MASK \ + (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \ + (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + } sq_instruction_cf_loop_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + } sq_instruction_cf_loop_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_0_t f; +} sq_instruction_cf_loop_0_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_1 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000 + +#define SQ_INSTRUCTION_CF_LOOP_1_MASK \ + (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + } sq_instruction_cf_loop_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + } sq_instruction_cf_loop_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_1_t f; +} sq_instruction_cf_loop_1_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_2 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_LOOP_2_MASK \ + (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \ + ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + } sq_instruction_cf_loop_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + } sq_instruction_cf_loop_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_2_t f; +} sq_instruction_cf_loop_2_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_0 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \ + (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_0_t f; +} sq_instruction_cf_jmp_call_0_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_1 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \ + ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \ + (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_1_t f; +} sq_instruction_cf_jmp_call_1_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_2 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_2_t f; +} sq_instruction_cf_jmp_call_2_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_0 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0 + +#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \ + ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + } sq_instruction_cf_alloc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + } sq_instruction_cf_alloc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_0_t f; +} sq_instruction_cf_alloc_0_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_1 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000 + +#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \ + (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + } sq_instruction_cf_alloc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + } sq_instruction_cf_alloc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_1_t f; +} sq_instruction_cf_alloc_1_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_2 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + } sq_instruction_cf_alloc_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + } sq_instruction_cf_alloc_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_2_t f; +} sq_instruction_cf_alloc_2_u; + + +/* + * SQ_INSTRUCTION_TFETCH_0 struct + */ + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000 + +#define SQ_INSTRUCTION_TFETCH_0_MASK \ + (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \ + SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) + +#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \ + ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \ + (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \ + (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \ + (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \ + (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \ + (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \ + (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + } sq_instruction_tfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + } sq_instruction_tfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_0_t f; +} sq_instruction_tfetch_0_u; + + +/* + * SQ_INSTRUCTION_TFETCH_1 struct + */ + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_1_MASK \ + (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \ + (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \ + (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \ + (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \ + (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \ + (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \ + (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \ + (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \ + (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \ + (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_tfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_tfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_1_t f; +} sq_instruction_tfetch_1_u; + + +/* + * SQ_INSTRUCTION_TFETCH_2 struct + */ + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_2_MASK \ + (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \ + SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \ + ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \ + (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \ + (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \ + (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \ + (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \ + (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \ + (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_tfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + } sq_instruction_tfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_2_t f; +} sq_instruction_tfetch_2_u; + + +/* + * SQ_INSTRUCTION_VFETCH_0 struct + */ + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000 + +#define SQ_INSTRUCTION_VFETCH_0_MASK \ + (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) + +#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \ + ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \ + (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \ + (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \ + (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \ + (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int : 3; + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + } sq_instruction_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + unsigned int : 3; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + } sq_instruction_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_0_t f; +} sq_instruction_vfetch_0_u; + + +/* + * SQ_INSTRUCTION_VFETCH_1 struct + */ + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_1_MASK \ + (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \ + SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \ + (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \ + (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \ + (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \ + (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \ + (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_1_t f; +} sq_instruction_vfetch_1_u; + + +/* + * SQ_INSTRUCTION_VFETCH_2 struct + */ + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_2_MASK \ + (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \ + SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \ + SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \ + ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \ + (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + unsigned int : 8; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 7; + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_vfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + unsigned int : 7; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 8; + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + } sq_instruction_vfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_2_t f; +} sq_instruction_vfetch_2_u; + + +/* + * SQ_CONSTANT_0 struct + */ + +#define SQ_CONSTANT_0_RED_SIZE 32 + +#define SQ_CONSTANT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_0_MASK \ + (SQ_CONSTANT_0_RED_MASK) + +#define SQ_CONSTANT_0(red) \ + ((red << SQ_CONSTANT_0_RED_SHIFT)) + +#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \ + ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT) + +#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \ + sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_0_t f; +} sq_constant_0_u; + + +/* + * SQ_CONSTANT_1 struct + */ + +#define SQ_CONSTANT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_1_MASK \ + (SQ_CONSTANT_1_GREEN_MASK) + +#define SQ_CONSTANT_1(green) \ + ((green << SQ_CONSTANT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \ + ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \ + sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_1_t f; +} sq_constant_1_u; + + +/* + * SQ_CONSTANT_2 struct + */ + +#define SQ_CONSTANT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_2_MASK \ + (SQ_CONSTANT_2_BLUE_MASK) + +#define SQ_CONSTANT_2(blue) \ + ((blue << SQ_CONSTANT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \ + ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \ + sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_2_t f; +} sq_constant_2_u; + + +/* + * SQ_CONSTANT_3 struct + */ + +#define SQ_CONSTANT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_3_MASK \ + (SQ_CONSTANT_3_ALPHA_MASK) + +#define SQ_CONSTANT_3(alpha) \ + ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \ + ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \ + sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_3_t f; +} sq_constant_3_u; + + +/* + * SQ_FETCH_0 struct + */ + +#define SQ_FETCH_0_VALUE_SIZE 32 + +#define SQ_FETCH_0_VALUE_SHIFT 0 + +#define SQ_FETCH_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_0_MASK \ + (SQ_FETCH_0_VALUE_MASK) + +#define SQ_FETCH_0(value) \ + ((value << SQ_FETCH_0_VALUE_SHIFT)) + +#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \ + ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT) + +#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \ + sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_0_t f; +} sq_fetch_0_u; + + +/* + * SQ_FETCH_1 struct + */ + +#define SQ_FETCH_1_VALUE_SIZE 32 + +#define SQ_FETCH_1_VALUE_SHIFT 0 + +#define SQ_FETCH_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_1_MASK \ + (SQ_FETCH_1_VALUE_MASK) + +#define SQ_FETCH_1(value) \ + ((value << SQ_FETCH_1_VALUE_SHIFT)) + +#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \ + ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT) + +#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \ + sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_1_t f; +} sq_fetch_1_u; + + +/* + * SQ_FETCH_2 struct + */ + +#define SQ_FETCH_2_VALUE_SIZE 32 + +#define SQ_FETCH_2_VALUE_SHIFT 0 + +#define SQ_FETCH_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_2_MASK \ + (SQ_FETCH_2_VALUE_MASK) + +#define SQ_FETCH_2(value) \ + ((value << SQ_FETCH_2_VALUE_SHIFT)) + +#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \ + ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT) + +#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \ + sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_2_t f; +} sq_fetch_2_u; + + +/* + * SQ_FETCH_3 struct + */ + +#define SQ_FETCH_3_VALUE_SIZE 32 + +#define SQ_FETCH_3_VALUE_SHIFT 0 + +#define SQ_FETCH_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_3_MASK \ + (SQ_FETCH_3_VALUE_MASK) + +#define SQ_FETCH_3(value) \ + ((value << SQ_FETCH_3_VALUE_SHIFT)) + +#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \ + ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT) + +#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \ + sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_3_t f; +} sq_fetch_3_u; + + +/* + * SQ_FETCH_4 struct + */ + +#define SQ_FETCH_4_VALUE_SIZE 32 + +#define SQ_FETCH_4_VALUE_SHIFT 0 + +#define SQ_FETCH_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_4_MASK \ + (SQ_FETCH_4_VALUE_MASK) + +#define SQ_FETCH_4(value) \ + ((value << SQ_FETCH_4_VALUE_SHIFT)) + +#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \ + ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT) + +#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \ + sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_4_t f; +} sq_fetch_4_u; + + +/* + * SQ_FETCH_5 struct + */ + +#define SQ_FETCH_5_VALUE_SIZE 32 + +#define SQ_FETCH_5_VALUE_SHIFT 0 + +#define SQ_FETCH_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_5_MASK \ + (SQ_FETCH_5_VALUE_MASK) + +#define SQ_FETCH_5(value) \ + ((value << SQ_FETCH_5_VALUE_SHIFT)) + +#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \ + ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT) + +#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \ + sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_5_t f; +} sq_fetch_5_u; + + +/* + * SQ_CONSTANT_VFETCH_0 struct + */ + +#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0 +#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001 +#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_0_MASK \ + (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \ + SQ_CONSTANT_VFETCH_0_STATE_MASK | \ + SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \ + ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \ + (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \ + (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + } sq_constant_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + } sq_constant_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_0_t f; +} sq_constant_vfetch_0_u; + + +/* + * SQ_CONSTANT_VFETCH_1 struct + */ + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_1_MASK \ + (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \ + SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \ + ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \ + (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + } sq_constant_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + } sq_constant_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_1_t f; +} sq_constant_vfetch_1_u; + + +/* + * SQ_CONSTANT_T2 struct + */ + +#define SQ_CONSTANT_T2_VALUE_SIZE 32 + +#define SQ_CONSTANT_T2_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T2_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T2_MASK \ + (SQ_CONSTANT_T2_VALUE_MASK) + +#define SQ_CONSTANT_T2(value) \ + ((value << SQ_CONSTANT_T2_VALUE_SHIFT)) + +#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \ + ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT) + +#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \ + sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t2_t f; +} sq_constant_t2_u; + + +/* + * SQ_CONSTANT_T3 struct + */ + +#define SQ_CONSTANT_T3_VALUE_SIZE 32 + +#define SQ_CONSTANT_T3_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T3_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T3_MASK \ + (SQ_CONSTANT_T3_VALUE_MASK) + +#define SQ_CONSTANT_T3(value) \ + ((value << SQ_CONSTANT_T3_VALUE_SHIFT)) + +#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \ + ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT) + +#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \ + sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t3_t f; +} sq_constant_t3_u; + + +/* + * SQ_CF_BOOLEANS struct + */ + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_BOOLEANS_MASK \ + (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_booleans_t f; +} sq_cf_booleans_u; + + +/* + * SQ_CF_LOOP struct + */ + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_LOOP_MASK \ + (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_loop_t f; +} sq_cf_loop_u; + + +/* + * SQ_CONSTANT_RT_0 struct + */ + +#define SQ_CONSTANT_RT_0_RED_SIZE 32 + +#define SQ_CONSTANT_RT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_RT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_RT_0_MASK \ + (SQ_CONSTANT_RT_0_RED_MASK) + +#define SQ_CONSTANT_RT_0(red) \ + ((red << SQ_CONSTANT_RT_0_RED_SHIFT)) + +#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \ + ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT) + +#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \ + sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_0_t f; +} sq_constant_rt_0_u; + + +/* + * SQ_CONSTANT_RT_1 struct + */ + +#define SQ_CONSTANT_RT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_RT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_RT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_RT_1_MASK \ + (SQ_CONSTANT_RT_1_GREEN_MASK) + +#define SQ_CONSTANT_RT_1(green) \ + ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \ + ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \ + sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_1_t f; +} sq_constant_rt_1_u; + + +/* + * SQ_CONSTANT_RT_2 struct + */ + +#define SQ_CONSTANT_RT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_RT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_RT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_RT_2_MASK \ + (SQ_CONSTANT_RT_2_BLUE_MASK) + +#define SQ_CONSTANT_RT_2(blue) \ + ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \ + ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \ + sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_2_t f; +} sq_constant_rt_2_u; + + +/* + * SQ_CONSTANT_RT_3 struct + */ + +#define SQ_CONSTANT_RT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_RT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_RT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_RT_3_MASK \ + (SQ_CONSTANT_RT_3_ALPHA_MASK) + +#define SQ_CONSTANT_RT_3(alpha) \ + ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \ + ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \ + sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_3_t f; +} sq_constant_rt_3_u; + + +/* + * SQ_FETCH_RT_0 struct + */ + +#define SQ_FETCH_RT_0_VALUE_SIZE 32 + +#define SQ_FETCH_RT_0_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_0_MASK \ + (SQ_FETCH_RT_0_VALUE_MASK) + +#define SQ_FETCH_RT_0(value) \ + ((value << SQ_FETCH_RT_0_VALUE_SHIFT)) + +#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \ + ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT) + +#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \ + sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_0_t f; +} sq_fetch_rt_0_u; + + +/* + * SQ_FETCH_RT_1 struct + */ + +#define SQ_FETCH_RT_1_VALUE_SIZE 32 + +#define SQ_FETCH_RT_1_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_1_MASK \ + (SQ_FETCH_RT_1_VALUE_MASK) + +#define SQ_FETCH_RT_1(value) \ + ((value << SQ_FETCH_RT_1_VALUE_SHIFT)) + +#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \ + ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT) + +#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \ + sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_1_t f; +} sq_fetch_rt_1_u; + + +/* + * SQ_FETCH_RT_2 struct + */ + +#define SQ_FETCH_RT_2_VALUE_SIZE 32 + +#define SQ_FETCH_RT_2_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_2_MASK \ + (SQ_FETCH_RT_2_VALUE_MASK) + +#define SQ_FETCH_RT_2(value) \ + ((value << SQ_FETCH_RT_2_VALUE_SHIFT)) + +#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \ + ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT) + +#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \ + sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_2_t f; +} sq_fetch_rt_2_u; + + +/* + * SQ_FETCH_RT_3 struct + */ + +#define SQ_FETCH_RT_3_VALUE_SIZE 32 + +#define SQ_FETCH_RT_3_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_3_MASK \ + (SQ_FETCH_RT_3_VALUE_MASK) + +#define SQ_FETCH_RT_3(value) \ + ((value << SQ_FETCH_RT_3_VALUE_SHIFT)) + +#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \ + ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT) + +#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \ + sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_3_t f; +} sq_fetch_rt_3_u; + + +/* + * SQ_FETCH_RT_4 struct + */ + +#define SQ_FETCH_RT_4_VALUE_SIZE 32 + +#define SQ_FETCH_RT_4_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_4_MASK \ + (SQ_FETCH_RT_4_VALUE_MASK) + +#define SQ_FETCH_RT_4(value) \ + ((value << SQ_FETCH_RT_4_VALUE_SHIFT)) + +#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \ + ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT) + +#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \ + sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_4_t f; +} sq_fetch_rt_4_u; + + +/* + * SQ_FETCH_RT_5 struct + */ + +#define SQ_FETCH_RT_5_VALUE_SIZE 32 + +#define SQ_FETCH_RT_5_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_5_MASK \ + (SQ_FETCH_RT_5_VALUE_MASK) + +#define SQ_FETCH_RT_5(value) \ + ((value << SQ_FETCH_RT_5_VALUE_SHIFT)) + +#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \ + ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT) + +#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \ + sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_5_t f; +} sq_fetch_rt_5_u; + + +/* + * SQ_CF_RT_BOOLEANS struct + */ + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_RT_BOOLEANS_MASK \ + (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_rt_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_rt_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_booleans_t f; +} sq_cf_rt_booleans_u; + + +/* + * SQ_CF_RT_LOOP struct + */ + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_RT_LOOP_MASK \ + (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_rt_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_rt_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_loop_t f; +} sq_cf_rt_loop_u; + + +/* + * SQ_VS_PROGRAM struct + */ + +#define SQ_VS_PROGRAM_BASE_SIZE 12 +#define SQ_VS_PROGRAM_SIZE_SIZE 12 + +#define SQ_VS_PROGRAM_BASE_SHIFT 0 +#define SQ_VS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_VS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_VS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_VS_PROGRAM_MASK \ + (SQ_VS_PROGRAM_BASE_MASK | \ + SQ_VS_PROGRAM_SIZE_MASK) + +#define SQ_VS_PROGRAM(base, size) \ + ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_VS_PROGRAM_SIZE_SHIFT)) + +#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT) + +#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_vs_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int : 8; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + } sq_vs_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_program_t f; +} sq_vs_program_u; + + +/* + * SQ_PS_PROGRAM struct + */ + +#define SQ_PS_PROGRAM_BASE_SIZE 12 +#define SQ_PS_PROGRAM_SIZE_SIZE 12 + +#define SQ_PS_PROGRAM_BASE_SHIFT 0 +#define SQ_PS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_PS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_PS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_PS_PROGRAM_MASK \ + (SQ_PS_PROGRAM_BASE_MASK | \ + SQ_PS_PROGRAM_SIZE_MASK) + +#define SQ_PS_PROGRAM(base, size) \ + ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_PS_PROGRAM_SIZE_SHIFT)) + +#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT) + +#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_ps_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int : 8; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + } sq_ps_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_program_t f; +} sq_ps_program_u; + + +/* + * SQ_CF_PROGRAM_SIZE struct + */ + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000 + +#define SQ_CF_PROGRAM_SIZE_MASK \ + (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \ + SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) + +#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \ + ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \ + (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)) + +#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 9; + } sq_cf_program_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int : 9; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + } sq_cf_program_size_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_program_size_t f; +} sq_cf_program_size_u; + + +/* + * SQ_INTERPOLATOR_CNTL struct + */ + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000 + +#define SQ_INTERPOLATOR_CNTL_MASK \ + (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \ + SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) + +#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \ + ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \ + (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)) + +#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + } sq_interpolator_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + } sq_interpolator_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_interpolator_cntl_t f; +} sq_interpolator_cntl_u; + + +/* + * SQ_PROGRAM_CNTL struct + */ + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f +#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000 +#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000 + +#define SQ_PROGRAM_CNTL_MASK \ + (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) + +#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \ + ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \ + (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \ + (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \ + (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \ + (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \ + (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \ + (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \ + (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \ + (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \ + (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)) + +#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + } sq_program_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + } sq_program_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_program_cntl_t f; +} sq_program_cntl_u; + + +/* + * SQ_WRAPPING_0 struct + */ + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f +#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0 +#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00 +#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000 +#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000 +#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000 +#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000 +#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000 + +#define SQ_WRAPPING_0_MASK \ + (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_7_MASK) + +#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \ + ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \ + (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \ + (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \ + (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \ + (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \ + (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \ + (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \ + (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)) + +#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + } sq_wrapping_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + } sq_wrapping_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_0_t f; +} sq_wrapping_0_u; + + +/* + * SQ_WRAPPING_1 struct + */ + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f +#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0 +#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00 +#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000 +#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000 +#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000 +#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000 +#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000 + +#define SQ_WRAPPING_1_MASK \ + (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_15_MASK) + +#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \ + ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \ + (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \ + (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \ + (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \ + (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \ + (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \ + (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \ + (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)) + +#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + } sq_wrapping_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + } sq_wrapping_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_1_t f; +} sq_wrapping_1_u; + + +/* + * SQ_VS_CONST struct + */ + +#define SQ_VS_CONST_BASE_SIZE 9 +#define SQ_VS_CONST_SIZE_SIZE 9 + +#define SQ_VS_CONST_BASE_SHIFT 0 +#define SQ_VS_CONST_SIZE_SHIFT 12 + +#define SQ_VS_CONST_BASE_MASK 0x000001ff +#define SQ_VS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_VS_CONST_MASK \ + (SQ_VS_CONST_BASE_MASK | \ + SQ_VS_CONST_SIZE_MASK) + +#define SQ_VS_CONST(base, size) \ + ((base << SQ_VS_CONST_BASE_SHIFT) | \ + (size << SQ_VS_CONST_SIZE_SHIFT)) + +#define SQ_VS_CONST_GET_BASE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT) + +#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int base : SQ_VS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_vs_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int : 11; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_VS_CONST_BASE_SIZE; + } sq_vs_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_const_t f; +} sq_vs_const_u; + + +/* + * SQ_PS_CONST struct + */ + +#define SQ_PS_CONST_BASE_SIZE 9 +#define SQ_PS_CONST_SIZE_SIZE 9 + +#define SQ_PS_CONST_BASE_SHIFT 0 +#define SQ_PS_CONST_SIZE_SHIFT 12 + +#define SQ_PS_CONST_BASE_MASK 0x000001ff +#define SQ_PS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_PS_CONST_MASK \ + (SQ_PS_CONST_BASE_MASK | \ + SQ_PS_CONST_SIZE_MASK) + +#define SQ_PS_CONST(base, size) \ + ((base << SQ_PS_CONST_BASE_SHIFT) | \ + (size << SQ_PS_CONST_SIZE_SHIFT)) + +#define SQ_PS_CONST_GET_BASE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT) + +#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int base : SQ_PS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_ps_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int : 11; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_PS_CONST_BASE_SIZE; + } sq_ps_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_const_t f; +} sq_ps_const_u; + + +/* + * SQ_CONTEXT_MISC struct + */ + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000 + +#define SQ_CONTEXT_MISC_MASK \ + (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \ + SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \ + SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \ + SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \ + SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) + +#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \ + ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \ + (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \ + (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \ + (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \ + (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \ + (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \ + (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)) + +#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int : 4; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int : 13; + } sq_context_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int : 13; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int : 4; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + } sq_context_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_context_misc_t f; +} sq_context_misc_u; + + +/* + * SQ_CF_RD_BASE struct + */ + +#define SQ_CF_RD_BASE_RD_BASE_SIZE 3 + +#define SQ_CF_RD_BASE_RD_BASE_SHIFT 0 + +#define SQ_CF_RD_BASE_RD_BASE_MASK 0x00000007 + +#define SQ_CF_RD_BASE_MASK \ + (SQ_CF_RD_BASE_RD_BASE_MASK) + +#define SQ_CF_RD_BASE(rd_base) \ + ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)) + +#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \ + ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \ + sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + unsigned int : 29; + } sq_cf_rd_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int : 29; + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + } sq_cf_rd_base_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rd_base_t f; +} sq_cf_rd_base_u; + + +/* + * SQ_DEBUG_MISC_0 struct + */ + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000 + +#define SQ_DEBUG_MISC_0_MASK \ + (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) + +#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \ + ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \ + (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \ + (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \ + (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)) + +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 5; + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + } sq_debug_misc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + unsigned int : 5; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + } sq_debug_misc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_0_t f; +} sq_debug_misc_0_u; + + +/* + * SQ_DEBUG_MISC_1 struct + */ + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000 + +#define SQ_DEBUG_MISC_1_MASK \ + (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \ + SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \ + SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \ + SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) + +#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \ + ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \ + (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \ + (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \ + (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)) + +#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int : 6; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int : 5; + } sq_debug_misc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int : 5; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int : 6; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + } sq_debug_misc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_1_t f; +} sq_debug_misc_1_u; + + +#endif + + +#if !defined (_SX_FIDDLE_H) +#define _SX_FIDDLE_H + +/***************************************************************************************************************** + * + * sx_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_TP_FIDDLE_H) +#define _TP_FIDDLE_H + +/***************************************************************************************************************** + * + * tp_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * TC_CNTL_STATUS struct + */ + +#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2 +#define TC_CNTL_STATUS_TC_BUSY_SIZE 1 + +#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18 +#define TC_CNTL_STATUS_TC_BUSY_SHIFT 31 + +#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000 +#define TC_CNTL_STATUS_TC_BUSY_MASK 0x80000000 + +#define TC_CNTL_STATUS_MASK \ + (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \ + TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \ + TC_CNTL_STATUS_TC_BUSY_MASK) + +#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \ + ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \ + (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \ + (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)) + +#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + unsigned int : 17; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 11; + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + } tc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + unsigned int : 11; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 17; + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + } tc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tc_cntl_status_t f; +} tc_cntl_status_u; + + +/* + * TCR_CHICKEN struct + */ + +#define TCR_CHICKEN_SPARE_SIZE 32 + +#define TCR_CHICKEN_SPARE_SHIFT 0 + +#define TCR_CHICKEN_SPARE_MASK 0xffffffff + +#define TCR_CHICKEN_MASK \ + (TCR_CHICKEN_SPARE_MASK) + +#define TCR_CHICKEN(spare) \ + ((spare << TCR_CHICKEN_SPARE_SHIFT)) + +#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \ + ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT) + +#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \ + tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_chicken_t f; +} tcr_chicken_u; + + +/* + * TCF_CHICKEN struct + */ + +#define TCF_CHICKEN_SPARE_SIZE 32 + +#define TCF_CHICKEN_SPARE_SHIFT 0 + +#define TCF_CHICKEN_SPARE_MASK 0xffffffff + +#define TCF_CHICKEN_MASK \ + (TCF_CHICKEN_SPARE_MASK) + +#define TCF_CHICKEN(spare) \ + ((spare << TCF_CHICKEN_SPARE_SHIFT)) + +#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \ + ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT) + +#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \ + tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_chicken_t f; +} tcf_chicken_u; + + +/* + * TCM_CHICKEN struct + */ + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1 +#define TCM_CHICKEN_SPARE_SIZE 23 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8 +#define TCM_CHICKEN_SPARE_SHIFT 9 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100 +#define TCM_CHICKEN_SPARE_MASK 0xfffffe00 + +#define TCM_CHICKEN_MASK \ + (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \ + TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \ + TCM_CHICKEN_SPARE_MASK) + +#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \ + ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \ + (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \ + (spare << TCM_CHICKEN_SPARE_SHIFT)) + +#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT) + +#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + } tcm_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + } tcm_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_chicken_t f; +} tcm_chicken_u; + + +/* + * TCR_PERFCOUNTER0_SELECT struct + */ + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER0_SELECT_MASK \ + (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \ + ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \ + tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_select_t f; +} tcr_perfcounter0_select_u; + + +/* + * TCR_PERFCOUNTER1_SELECT struct + */ + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER1_SELECT_MASK \ + (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \ + ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \ + tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_select_t f; +} tcr_perfcounter1_select_u; + + +/* + * TCR_PERFCOUNTER0_HI struct + */ + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER0_HI_MASK \ + (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \ + ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \ + tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_hi_t f; +} tcr_perfcounter0_hi_u; + + +/* + * TCR_PERFCOUNTER1_HI struct + */ + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER1_HI_MASK \ + (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \ + ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \ + tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_hi_t f; +} tcr_perfcounter1_hi_u; + + +/* + * TCR_PERFCOUNTER0_LOW struct + */ + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER0_LOW_MASK \ + (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \ + ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \ + tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_low_t f; +} tcr_perfcounter0_low_u; + + +/* + * TCR_PERFCOUNTER1_LOW struct + */ + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER1_LOW_MASK \ + (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \ + ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \ + tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_low_t f; +} tcr_perfcounter1_low_u; + + +/* + * TP_TC_CLKGATE_CNTL struct + */ + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038 + +#define TP_TC_CLKGATE_CNTL_MASK \ + (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \ + TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) + +#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \ + ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \ + (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)) + +#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int : 26; + } tp_tc_clkgate_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int : 26; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + } tp_tc_clkgate_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + tp_tc_clkgate_cntl_t f; +} tp_tc_clkgate_cntl_u; + + +/* + * TPC_CNTL_STATUS struct + */ + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BUSY_SIZE 1 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15 +#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17 +#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19 +#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22 +#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23 +#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25 +#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27 +#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30 +#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000 +#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000 +#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000 +#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000 +#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000 +#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000 +#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000 +#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000 +#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000 +#define TPC_CNTL_STATUS_TPC_BUSY_MASK 0x80000000 + +#define TPC_CNTL_STATUS_MASK \ + (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTR_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TF_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \ + TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \ + TPC_CNTL_STATUS_TPC_BUSY_MASK) + +#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \ + ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \ + (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \ + (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \ + (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \ + (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \ + (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \ + (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \ + (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \ + (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \ + (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \ + (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \ + (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \ + (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \ + (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \ + (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \ + (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \ + (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \ + (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \ + (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \ + (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \ + (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \ + (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \ + (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \ + (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \ + (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \ + (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \ + (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \ + (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)) + +#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int : 1; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int : 1; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + } tpc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int : 1; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int : 1; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + } tpc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_cntl_status_t f; +} tpc_cntl_status_u; + + +/* + * TPC_DEBUG0 struct + */ + +#define TPC_DEBUG0_LOD_CNTL_SIZE 2 +#define TPC_DEBUG0_IC_CTR_SIZE 2 +#define TPC_DEBUG0_WALKER_CNTL_SIZE 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SIZE 3 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1 +#define TPC_DEBUG0_WALKER_STATE_SIZE 10 +#define TPC_DEBUG0_ALIGNER_STATE_SIZE 2 +#define TPC_DEBUG0_REG_CLK_EN_SIZE 1 +#define TPC_DEBUG0_TPC_CLK_EN_SIZE 1 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE 1 + +#define TPC_DEBUG0_LOD_CNTL_SHIFT 0 +#define TPC_DEBUG0_IC_CTR_SHIFT 2 +#define TPC_DEBUG0_WALKER_CNTL_SHIFT 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT 8 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12 +#define TPC_DEBUG0_WALKER_STATE_SHIFT 16 +#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26 +#define TPC_DEBUG0_REG_CLK_EN_SHIFT 29 +#define TPC_DEBUG0_TPC_CLK_EN_SHIFT 30 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT 31 + +#define TPC_DEBUG0_LOD_CNTL_MASK 0x00000003 +#define TPC_DEBUG0_IC_CTR_MASK 0x0000000c +#define TPC_DEBUG0_WALKER_CNTL_MASK 0x000000f0 +#define TPC_DEBUG0_ALIGNER_CNTL_MASK 0x00000700 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000 +#define TPC_DEBUG0_WALKER_STATE_MASK 0x03ff0000 +#define TPC_DEBUG0_ALIGNER_STATE_MASK 0x0c000000 +#define TPC_DEBUG0_REG_CLK_EN_MASK 0x20000000 +#define TPC_DEBUG0_TPC_CLK_EN_MASK 0x40000000 +#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK 0x80000000 + +#define TPC_DEBUG0_MASK \ + (TPC_DEBUG0_LOD_CNTL_MASK | \ + TPC_DEBUG0_IC_CTR_MASK | \ + TPC_DEBUG0_WALKER_CNTL_MASK | \ + TPC_DEBUG0_ALIGNER_CNTL_MASK | \ + TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \ + TPC_DEBUG0_WALKER_STATE_MASK | \ + TPC_DEBUG0_ALIGNER_STATE_MASK | \ + TPC_DEBUG0_REG_CLK_EN_MASK | \ + TPC_DEBUG0_TPC_CLK_EN_MASK | \ + TPC_DEBUG0_SQ_TP_WAKEUP_MASK) + +#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \ + ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \ + (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \ + (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \ + (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \ + (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \ + (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \ + (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \ + (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \ + (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \ + (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)) + +#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int : 1; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 3; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int : 1; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + } tpc_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int : 1; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int : 3; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 1; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + } tpc_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug0_t f; +} tpc_debug0_u; + + +/* + * TPC_DEBUG1 struct + */ + +#define TPC_DEBUG1_UNUSED_SIZE 1 + +#define TPC_DEBUG1_UNUSED_SHIFT 0 + +#define TPC_DEBUG1_UNUSED_MASK 0x00000001 + +#define TPC_DEBUG1_MASK \ + (TPC_DEBUG1_UNUSED_MASK) + +#define TPC_DEBUG1(unused) \ + ((unused << TPC_DEBUG1_UNUSED_SHIFT)) + +#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \ + ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT) + +#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \ + tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + unsigned int : 31; + } tpc_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int : 31; + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + } tpc_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug1_t f; +} tpc_debug1_u; + + +/* + * TPC_CHICKEN struct + */ + +#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1 +#define TPC_CHICKEN_SPARE_SIZE 31 + +#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0 +#define TPC_CHICKEN_SPARE_SHIFT 1 + +#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001 +#define TPC_CHICKEN_SPARE_MASK 0xfffffffe + +#define TPC_CHICKEN_MASK \ + (TPC_CHICKEN_BLEND_PRECISION_MASK | \ + TPC_CHICKEN_SPARE_MASK) + +#define TPC_CHICKEN(blend_precision, spare) \ + ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \ + (spare << TPC_CHICKEN_SPARE_SHIFT)) + +#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT) + +#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + } tpc_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + } tpc_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_chicken_t f; +} tpc_chicken_u; + + +/* + * TP0_CNTL_STATUS struct + */ + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1 +#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TP_BUSY_SIZE 1 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14 +#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16 +#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17 +#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18 +#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19 +#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21 +#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23 +#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25 +#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27 +#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29 +#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30 +#define TP0_CNTL_STATUS_TP_BUSY_SHIFT 31 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200 +#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000 +#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000 +#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000 +#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000 +#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000 +#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000 +#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000 +#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000 +#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000 +#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000 +#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000 +#define TP0_CNTL_STATUS_TP_BUSY_MASK 0x80000000 + +#define TP0_CNTL_STATUS_MASK \ + (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_IN_LC_RTS_MASK | \ + TP0_CNTL_STATUS_LC_LA_RTS_MASK | \ + TP0_CNTL_STATUS_LA_FL_RTS_MASK | \ + TP0_CNTL_STATUS_FL_TA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \ + TP0_CNTL_STATUS_TB_TO_RTS_MASK | \ + TP0_CNTL_STATUS_TP_BUSY_MASK) + +#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \ + ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \ + (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \ + (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \ + (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \ + (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \ + (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \ + (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \ + (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \ + (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \ + (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \ + (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \ + (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \ + (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \ + (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \ + (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \ + (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \ + (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \ + (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \ + (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \ + (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \ + (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \ + (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \ + (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \ + (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \ + (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \ + (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \ + (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \ + (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \ + (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \ + (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \ + (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)) + +#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int : 1; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + } tp0_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int : 1; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + } tp0_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_cntl_status_t f; +} tp0_cntl_status_u; + + +/* + * TP0_DEBUG struct + */ + +#define TP0_DEBUG_Q_LOD_CNTL_SIZE 2 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE 1 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17 +#define TP0_DEBUG_REG_CLK_EN_SIZE 1 +#define TP0_DEBUG_PERF_CLK_EN_SIZE 1 +#define TP0_DEBUG_TP_CLK_EN_SIZE 1 +#define TP0_DEBUG_Q_WALKER_CNTL_SIZE 4 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE 3 + +#define TP0_DEBUG_Q_LOD_CNTL_SHIFT 0 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4 +#define TP0_DEBUG_REG_CLK_EN_SHIFT 21 +#define TP0_DEBUG_PERF_CLK_EN_SHIFT 22 +#define TP0_DEBUG_TP_CLK_EN_SHIFT 23 +#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT 24 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28 + +#define TP0_DEBUG_Q_LOD_CNTL_MASK 0x00000003 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK 0x00000008 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0 +#define TP0_DEBUG_REG_CLK_EN_MASK 0x00200000 +#define TP0_DEBUG_PERF_CLK_EN_MASK 0x00400000 +#define TP0_DEBUG_TP_CLK_EN_MASK 0x00800000 +#define TP0_DEBUG_Q_WALKER_CNTL_MASK 0x0f000000 +#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK 0x70000000 + +#define TP0_DEBUG_MASK \ + (TP0_DEBUG_Q_LOD_CNTL_MASK | \ + TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \ + TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \ + TP0_DEBUG_REG_CLK_EN_MASK | \ + TP0_DEBUG_PERF_CLK_EN_MASK | \ + TP0_DEBUG_TP_CLK_EN_MASK | \ + TP0_DEBUG_Q_WALKER_CNTL_MASK | \ + TP0_DEBUG_Q_ALIGNER_CNTL_MASK) + +#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \ + ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \ + (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \ + (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \ + (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \ + (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \ + (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \ + (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \ + (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)) + +#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + unsigned int : 1; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int : 1; + } tp0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int : 1; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int : 1; + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + } tp0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_debug_t f; +} tp0_debug_u; + + +/* + * TP0_CHICKEN struct + */ + +#define TP0_CHICKEN_TT_MODE_SIZE 1 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1 +#define TP0_CHICKEN_SPARE_SIZE 30 + +#define TP0_CHICKEN_TT_MODE_SHIFT 0 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1 +#define TP0_CHICKEN_SPARE_SHIFT 2 + +#define TP0_CHICKEN_TT_MODE_MASK 0x00000001 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002 +#define TP0_CHICKEN_SPARE_MASK 0xfffffffc + +#define TP0_CHICKEN_MASK \ + (TP0_CHICKEN_TT_MODE_MASK | \ + TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \ + TP0_CHICKEN_SPARE_MASK) + +#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \ + ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \ + (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \ + (spare << TP0_CHICKEN_SPARE_SHIFT)) + +#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT) + +#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + } tp0_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + } tp0_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_chicken_t f; +} tp0_chicken_u; + + +/* + * TP0_PERFCOUNTER0_SELECT struct + */ + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER0_SELECT_MASK \ + (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \ + ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \ + tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_select_t f; +} tp0_perfcounter0_select_u; + + +/* + * TP0_PERFCOUNTER0_HI struct + */ + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER0_HI_MASK \ + (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \ + ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \ + tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_hi_t f; +} tp0_perfcounter0_hi_u; + + +/* + * TP0_PERFCOUNTER0_LOW struct + */ + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER0_LOW_MASK \ + (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \ + ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \ + tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_low_t f; +} tp0_perfcounter0_low_u; + + +/* + * TP0_PERFCOUNTER1_SELECT struct + */ + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER1_SELECT_MASK \ + (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \ + ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \ + tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_select_t f; +} tp0_perfcounter1_select_u; + + +/* + * TP0_PERFCOUNTER1_HI struct + */ + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER1_HI_MASK \ + (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \ + ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \ + tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_hi_t f; +} tp0_perfcounter1_hi_u; + + +/* + * TP0_PERFCOUNTER1_LOW struct + */ + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER1_LOW_MASK \ + (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \ + ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \ + tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_low_t f; +} tp0_perfcounter1_low_u; + + +/* + * TCM_PERFCOUNTER0_SELECT struct + */ + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER0_SELECT_MASK \ + (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \ + ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \ + tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_select_t f; +} tcm_perfcounter0_select_u; + + +/* + * TCM_PERFCOUNTER1_SELECT struct + */ + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER1_SELECT_MASK \ + (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \ + ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \ + tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_select_t f; +} tcm_perfcounter1_select_u; + + +/* + * TCM_PERFCOUNTER0_HI struct + */ + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER0_HI_MASK \ + (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \ + ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \ + tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_hi_t f; +} tcm_perfcounter0_hi_u; + + +/* + * TCM_PERFCOUNTER1_HI struct + */ + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER1_HI_MASK \ + (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \ + ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \ + tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_hi_t f; +} tcm_perfcounter1_hi_u; + + +/* + * TCM_PERFCOUNTER0_LOW struct + */ + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER0_LOW_MASK \ + (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \ + ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \ + tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_low_t f; +} tcm_perfcounter0_low_u; + + +/* + * TCM_PERFCOUNTER1_LOW struct + */ + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER1_LOW_MASK \ + (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \ + ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \ + tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_low_t f; +} tcm_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER0_SELECT struct + */ + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER0_SELECT_MASK \ + (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \ + ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \ + tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_select_t f; +} tcf_perfcounter0_select_u; + + +/* + * TCF_PERFCOUNTER1_SELECT struct + */ + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER1_SELECT_MASK \ + (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \ + ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \ + tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_select_t f; +} tcf_perfcounter1_select_u; + + +/* + * TCF_PERFCOUNTER2_SELECT struct + */ + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER2_SELECT_MASK \ + (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \ + ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \ + tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_select_t f; +} tcf_perfcounter2_select_u; + + +/* + * TCF_PERFCOUNTER3_SELECT struct + */ + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER3_SELECT_MASK \ + (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \ + ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \ + tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_select_t f; +} tcf_perfcounter3_select_u; + + +/* + * TCF_PERFCOUNTER4_SELECT struct + */ + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER4_SELECT_MASK \ + (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \ + ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \ + tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter4_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter4_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_select_t f; +} tcf_perfcounter4_select_u; + + +/* + * TCF_PERFCOUNTER5_SELECT struct + */ + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER5_SELECT_MASK \ + (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \ + ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \ + tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter5_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter5_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_select_t f; +} tcf_perfcounter5_select_u; + + +/* + * TCF_PERFCOUNTER6_SELECT struct + */ + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER6_SELECT_MASK \ + (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \ + ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \ + tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter6_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter6_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_select_t f; +} tcf_perfcounter6_select_u; + + +/* + * TCF_PERFCOUNTER7_SELECT struct + */ + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER7_SELECT_MASK \ + (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \ + ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \ + tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter7_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter7_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_select_t f; +} tcf_perfcounter7_select_u; + + +/* + * TCF_PERFCOUNTER8_SELECT struct + */ + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER8_SELECT_MASK \ + (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \ + ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \ + tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter8_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter8_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_select_t f; +} tcf_perfcounter8_select_u; + + +/* + * TCF_PERFCOUNTER9_SELECT struct + */ + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER9_SELECT_MASK \ + (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \ + ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \ + tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter9_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter9_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_select_t f; +} tcf_perfcounter9_select_u; + + +/* + * TCF_PERFCOUNTER10_SELECT struct + */ + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER10_SELECT_MASK \ + (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \ + ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \ + tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter10_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter10_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_select_t f; +} tcf_perfcounter10_select_u; + + +/* + * TCF_PERFCOUNTER11_SELECT struct + */ + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER11_SELECT_MASK \ + (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \ + ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \ + tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter11_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter11_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_select_t f; +} tcf_perfcounter11_select_u; + + +/* + * TCF_PERFCOUNTER0_HI struct + */ + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER0_HI_MASK \ + (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \ + ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \ + tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_hi_t f; +} tcf_perfcounter0_hi_u; + + +/* + * TCF_PERFCOUNTER1_HI struct + */ + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER1_HI_MASK \ + (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \ + ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \ + tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_hi_t f; +} tcf_perfcounter1_hi_u; + + +/* + * TCF_PERFCOUNTER2_HI struct + */ + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER2_HI_MASK \ + (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \ + ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \ + tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_hi_t f; +} tcf_perfcounter2_hi_u; + + +/* + * TCF_PERFCOUNTER3_HI struct + */ + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER3_HI_MASK \ + (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \ + ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \ + tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_hi_t f; +} tcf_perfcounter3_hi_u; + + +/* + * TCF_PERFCOUNTER4_HI struct + */ + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER4_HI_MASK \ + (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \ + ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \ + tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter4_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter4_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_hi_t f; +} tcf_perfcounter4_hi_u; + + +/* + * TCF_PERFCOUNTER5_HI struct + */ + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER5_HI_MASK \ + (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \ + ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \ + tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter5_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter5_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_hi_t f; +} tcf_perfcounter5_hi_u; + + +/* + * TCF_PERFCOUNTER6_HI struct + */ + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER6_HI_MASK \ + (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \ + ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \ + tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter6_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter6_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_hi_t f; +} tcf_perfcounter6_hi_u; + + +/* + * TCF_PERFCOUNTER7_HI struct + */ + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER7_HI_MASK \ + (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \ + ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \ + tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter7_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter7_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_hi_t f; +} tcf_perfcounter7_hi_u; + + +/* + * TCF_PERFCOUNTER8_HI struct + */ + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER8_HI_MASK \ + (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \ + ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \ + tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter8_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter8_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_hi_t f; +} tcf_perfcounter8_hi_u; + + +/* + * TCF_PERFCOUNTER9_HI struct + */ + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER9_HI_MASK \ + (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \ + ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \ + tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter9_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter9_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_hi_t f; +} tcf_perfcounter9_hi_u; + + +/* + * TCF_PERFCOUNTER10_HI struct + */ + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER10_HI_MASK \ + (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \ + ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \ + tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter10_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter10_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_hi_t f; +} tcf_perfcounter10_hi_u; + + +/* + * TCF_PERFCOUNTER11_HI struct + */ + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER11_HI_MASK \ + (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \ + ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \ + tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter11_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter11_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_hi_t f; +} tcf_perfcounter11_hi_u; + + +/* + * TCF_PERFCOUNTER0_LOW struct + */ + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER0_LOW_MASK \ + (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \ + ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \ + tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_low_t f; +} tcf_perfcounter0_low_u; + + +/* + * TCF_PERFCOUNTER1_LOW struct + */ + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER1_LOW_MASK \ + (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \ + ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \ + tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_low_t f; +} tcf_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER2_LOW struct + */ + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER2_LOW_MASK \ + (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \ + ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \ + tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_low_t f; +} tcf_perfcounter2_low_u; + + +/* + * TCF_PERFCOUNTER3_LOW struct + */ + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER3_LOW_MASK \ + (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \ + ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \ + tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_low_t f; +} tcf_perfcounter3_low_u; + + +/* + * TCF_PERFCOUNTER4_LOW struct + */ + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER4_LOW_MASK \ + (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \ + ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \ + tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_low_t f; +} tcf_perfcounter4_low_u; + + +/* + * TCF_PERFCOUNTER5_LOW struct + */ + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER5_LOW_MASK \ + (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \ + ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \ + tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_low_t f; +} tcf_perfcounter5_low_u; + + +/* + * TCF_PERFCOUNTER6_LOW struct + */ + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER6_LOW_MASK \ + (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \ + ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \ + tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_low_t f; +} tcf_perfcounter6_low_u; + + +/* + * TCF_PERFCOUNTER7_LOW struct + */ + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER7_LOW_MASK \ + (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \ + ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \ + tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_low_t f; +} tcf_perfcounter7_low_u; + + +/* + * TCF_PERFCOUNTER8_LOW struct + */ + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER8_LOW_MASK \ + (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \ + ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \ + tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_low_t f; +} tcf_perfcounter8_low_u; + + +/* + * TCF_PERFCOUNTER9_LOW struct + */ + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER9_LOW_MASK \ + (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \ + ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \ + tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_low_t f; +} tcf_perfcounter9_low_u; + + +/* + * TCF_PERFCOUNTER10_LOW struct + */ + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER10_LOW_MASK \ + (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \ + ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \ + tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_low_t f; +} tcf_perfcounter10_low_u; + + +/* + * TCF_PERFCOUNTER11_LOW struct + */ + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER11_LOW_MASK \ + (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \ + ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \ + tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_low_t f; +} tcf_perfcounter11_low_u; + + +/* + * TCF_DEBUG struct + */ + +#define TCF_DEBUG_not_MH_TC_rtr_SIZE 1 +#define TCF_DEBUG_TC_MH_send_SIZE 1 +#define TCF_DEBUG_not_FG0_rtr_SIZE 1 +#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1 +#define TCF_DEBUG_TCB_ff_stall_SIZE 1 +#define TCF_DEBUG_TCB_miss_stall_SIZE 1 +#define TCF_DEBUG_TCA_TCB_stall_SIZE 1 +#define TCF_DEBUG_PF0_stall_SIZE 1 +#define TCF_DEBUG_TP0_full_SIZE 1 +#define TCF_DEBUG_TPC_full_SIZE 1 +#define TCF_DEBUG_not_TPC_rtr_SIZE 1 +#define TCF_DEBUG_tca_state_rts_SIZE 1 +#define TCF_DEBUG_tca_rts_SIZE 1 + +#define TCF_DEBUG_not_MH_TC_rtr_SHIFT 6 +#define TCF_DEBUG_TC_MH_send_SHIFT 7 +#define TCF_DEBUG_not_FG0_rtr_SHIFT 8 +#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12 +#define TCF_DEBUG_TCB_ff_stall_SHIFT 13 +#define TCF_DEBUG_TCB_miss_stall_SHIFT 14 +#define TCF_DEBUG_TCA_TCB_stall_SHIFT 15 +#define TCF_DEBUG_PF0_stall_SHIFT 16 +#define TCF_DEBUG_TP0_full_SHIFT 20 +#define TCF_DEBUG_TPC_full_SHIFT 24 +#define TCF_DEBUG_not_TPC_rtr_SHIFT 25 +#define TCF_DEBUG_tca_state_rts_SHIFT 26 +#define TCF_DEBUG_tca_rts_SHIFT 27 + +#define TCF_DEBUG_not_MH_TC_rtr_MASK 0x00000040 +#define TCF_DEBUG_TC_MH_send_MASK 0x00000080 +#define TCF_DEBUG_not_FG0_rtr_MASK 0x00000100 +#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000 +#define TCF_DEBUG_TCB_ff_stall_MASK 0x00002000 +#define TCF_DEBUG_TCB_miss_stall_MASK 0x00004000 +#define TCF_DEBUG_TCA_TCB_stall_MASK 0x00008000 +#define TCF_DEBUG_PF0_stall_MASK 0x00010000 +#define TCF_DEBUG_TP0_full_MASK 0x00100000 +#define TCF_DEBUG_TPC_full_MASK 0x01000000 +#define TCF_DEBUG_not_TPC_rtr_MASK 0x02000000 +#define TCF_DEBUG_tca_state_rts_MASK 0x04000000 +#define TCF_DEBUG_tca_rts_MASK 0x08000000 + +#define TCF_DEBUG_MASK \ + (TCF_DEBUG_not_MH_TC_rtr_MASK | \ + TCF_DEBUG_TC_MH_send_MASK | \ + TCF_DEBUG_not_FG0_rtr_MASK | \ + TCF_DEBUG_not_TCB_TCO_rtr_MASK | \ + TCF_DEBUG_TCB_ff_stall_MASK | \ + TCF_DEBUG_TCB_miss_stall_MASK | \ + TCF_DEBUG_TCA_TCB_stall_MASK | \ + TCF_DEBUG_PF0_stall_MASK | \ + TCF_DEBUG_TP0_full_MASK | \ + TCF_DEBUG_TPC_full_MASK | \ + TCF_DEBUG_not_TPC_rtr_MASK | \ + TCF_DEBUG_tca_state_rts_MASK | \ + TCF_DEBUG_tca_rts_MASK) + +#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \ + ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \ + (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \ + (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \ + (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \ + (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \ + (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \ + (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \ + (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \ + (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \ + (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \ + (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \ + (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \ + (tca_rts << TCF_DEBUG_tca_rts_SHIFT)) + +#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_GET_TP0_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_GET_TPC_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_GET_tca_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT) + +#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 6; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int : 3; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int : 4; + } tcf_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 4; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int : 3; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int : 6; + } tcf_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_debug_t f; +} tcf_debug_u; + + +/* + * TCA_FIFO_DEBUG struct + */ + +#define TCA_FIFO_DEBUG_tp0_full_SIZE 1 +#define TCA_FIFO_DEBUG_tpc_full_SIZE 1 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1 +#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1 +#define TCA_FIFO_DEBUG_FW_full_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1 +#define TCA_FIFO_DEBUG_FW_rts0_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1 + +#define TCA_FIFO_DEBUG_tp0_full_SHIFT 0 +#define TCA_FIFO_DEBUG_tpc_full_SHIFT 4 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5 +#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6 +#define TCA_FIFO_DEBUG_FW_full_SHIFT 7 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8 +#define TCA_FIFO_DEBUG_FW_rts0_SHIFT 12 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17 + +#define TCA_FIFO_DEBUG_tp0_full_MASK 0x00000001 +#define TCA_FIFO_DEBUG_tpc_full_MASK 0x00000010 +#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020 +#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040 +#define TCA_FIFO_DEBUG_FW_full_MASK 0x00000080 +#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100 +#define TCA_FIFO_DEBUG_FW_rts0_MASK 0x00001000 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000 +#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000 + +#define TCA_FIFO_DEBUG_MASK \ + (TCA_FIFO_DEBUG_tp0_full_MASK | \ + TCA_FIFO_DEBUG_tpc_full_MASK | \ + TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \ + TCA_FIFO_DEBUG_load_tp_fifos_MASK | \ + TCA_FIFO_DEBUG_FW_full_MASK | \ + TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \ + TCA_FIFO_DEBUG_FW_rts0_MASK | \ + TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \ + TCA_FIFO_DEBUG_FW_tpc_rts_MASK) + +#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \ + ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \ + (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \ + (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \ + (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \ + (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \ + (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \ + (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \ + (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \ + (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)) + +#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int : 14; + } tca_fifo_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int : 14; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + } tca_fifo_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_fifo_debug_t f; +} tca_fifo_debug_u; + + +/* + * TCA_PROBE_DEBUG struct + */ + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001 + +#define TCA_PROBE_DEBUG_MASK \ + (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) + +#define TCA_PROBE_DEBUG(probefilter_stall) \ + ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)) + +#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \ + ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \ + tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + unsigned int : 31; + } tca_probe_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int : 31; + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + } tca_probe_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_probe_debug_t f; +} tca_probe_debug_u; + + +/* + * TCA_TPC_DEBUG struct + */ + +#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1 +#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1 + +#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12 +#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13 + +#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000 +#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000 + +#define TCA_TPC_DEBUG_MASK \ + (TCA_TPC_DEBUG_captue_state_rts_MASK | \ + TCA_TPC_DEBUG_capture_tca_rts_MASK) + +#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \ + ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \ + (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)) + +#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 12; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int : 18; + } tca_tpc_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 18; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int : 12; + } tca_tpc_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_tpc_debug_t f; +} tca_tpc_debug_u; + + +/* + * TCB_CORE_DEBUG struct + */ + +#define TCB_CORE_DEBUG_access512_SIZE 1 +#define TCB_CORE_DEBUG_tiled_SIZE 1 +#define TCB_CORE_DEBUG_opcode_SIZE 3 +#define TCB_CORE_DEBUG_format_SIZE 6 +#define TCB_CORE_DEBUG_sector_format_SIZE 5 +#define TCB_CORE_DEBUG_sector_format512_SIZE 3 + +#define TCB_CORE_DEBUG_access512_SHIFT 0 +#define TCB_CORE_DEBUG_tiled_SHIFT 1 +#define TCB_CORE_DEBUG_opcode_SHIFT 4 +#define TCB_CORE_DEBUG_format_SHIFT 8 +#define TCB_CORE_DEBUG_sector_format_SHIFT 16 +#define TCB_CORE_DEBUG_sector_format512_SHIFT 24 + +#define TCB_CORE_DEBUG_access512_MASK 0x00000001 +#define TCB_CORE_DEBUG_tiled_MASK 0x00000002 +#define TCB_CORE_DEBUG_opcode_MASK 0x00000070 +#define TCB_CORE_DEBUG_format_MASK 0x00003f00 +#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000 +#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000 + +#define TCB_CORE_DEBUG_MASK \ + (TCB_CORE_DEBUG_access512_MASK | \ + TCB_CORE_DEBUG_tiled_MASK | \ + TCB_CORE_DEBUG_opcode_MASK | \ + TCB_CORE_DEBUG_format_MASK | \ + TCB_CORE_DEBUG_sector_format_MASK | \ + TCB_CORE_DEBUG_sector_format512_MASK) + +#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \ + ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \ + (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \ + (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \ + (format << TCB_CORE_DEBUG_format_SHIFT) | \ + (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \ + (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)) + +#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT) + +#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int : 2; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 1; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 2; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 3; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 5; + } tcb_core_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int : 5; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 3; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 2; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 1; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 2; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + } tcb_core_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_core_debug_t f; +} tcb_core_debug_u; + + +/* + * TCB_TAG0_DEBUG struct + */ + +#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG0_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG0_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG0_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG0_DEBUG_MASK \ + (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG0_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG0_DEBUG_miss_stall_MASK | \ + TCB_TAG0_DEBUG_num_feee_lines_MASK | \ + TCB_TAG0_DEBUG_max_misses_MASK) + +#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT) + +#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + } tcb_tag0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + } tcb_tag0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag0_debug_t f; +} tcb_tag0_debug_u; + + +/* + * TCB_TAG1_DEBUG struct + */ + +#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG1_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG1_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG1_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG1_DEBUG_MASK \ + (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG1_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG1_DEBUG_miss_stall_MASK | \ + TCB_TAG1_DEBUG_num_feee_lines_MASK | \ + TCB_TAG1_DEBUG_max_misses_MASK) + +#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT) + +#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + } tcb_tag1_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + } tcb_tag1_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag1_debug_t f; +} tcb_tag1_debug_u; + + +/* + * TCB_TAG2_DEBUG struct + */ + +#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG2_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG2_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG2_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG2_DEBUG_MASK \ + (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG2_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG2_DEBUG_miss_stall_MASK | \ + TCB_TAG2_DEBUG_num_feee_lines_MASK | \ + TCB_TAG2_DEBUG_max_misses_MASK) + +#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT) + +#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + } tcb_tag2_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + } tcb_tag2_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag2_debug_t f; +} tcb_tag2_debug_u; + + +/* + * TCB_TAG3_DEBUG struct + */ + +#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG3_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG3_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG3_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG3_DEBUG_MASK \ + (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG3_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG3_DEBUG_miss_stall_MASK | \ + TCB_TAG3_DEBUG_num_feee_lines_MASK | \ + TCB_TAG3_DEBUG_max_misses_MASK) + +#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT) + +#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + } tcb_tag3_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + } tcb_tag3_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag3_debug_t f; +} tcb_tag3_debug_u; + + +/* + * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct + */ + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \ + (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \ + ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \ + (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \ + (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \ + (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \ + (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \ + (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \ + (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \ + (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int : 3; + } tcb_fetch_gen_sector_walker0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int : 3; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + } tcb_fetch_gen_sector_walker0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_sector_walker0_debug_t f; +} tcb_fetch_gen_sector_walker0_debug_u; + + +/* + * TCB_FETCH_GEN_WALKER_DEBUG struct + */ + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000 + +#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \ + (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) + +#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \ + ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \ + (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \ + (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \ + (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \ + (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \ + (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)) + +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 4; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int : 3; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int : 12; + } tcb_fetch_gen_walker_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 12; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int : 3; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int : 4; + } tcb_fetch_gen_walker_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_walker_debug_t f; +} tcb_fetch_gen_walker_debug_u; + + +/* + * TCB_FETCH_GEN_PIPE0_DEBUG struct + */ + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \ + (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) + +#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \ + ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \ + (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \ + (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \ + (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \ + (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \ + (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \ + (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \ + (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \ + (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \ + (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \ + (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + } tcb_fetch_gen_pipe0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + } tcb_fetch_gen_pipe0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_pipe0_debug_t f; +} tcb_fetch_gen_pipe0_debug_u; + + +/* + * TCD_INPUT0_DEBUG struct + */ + +#define TCD_INPUT0_DEBUG_empty_SIZE 1 +#define TCD_INPUT0_DEBUG_full_SIZE 1 +#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_cnt_q1_SIZE 2 +#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_ip_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1 + +#define TCD_INPUT0_DEBUG_empty_SHIFT 16 +#define TCD_INPUT0_DEBUG_full_SHIFT 17 +#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20 +#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT 21 +#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23 +#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26 + +#define TCD_INPUT0_DEBUG_empty_MASK 0x00010000 +#define TCD_INPUT0_DEBUG_full_MASK 0x00020000 +#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000 +#define TCD_INPUT0_DEBUG_cnt_q1_MASK 0x00600000 +#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000 +#define TCD_INPUT0_DEBUG_ip_send_MASK 0x01000000 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000 +#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000 + +#define TCD_INPUT0_DEBUG_MASK \ + (TCD_INPUT0_DEBUG_empty_MASK | \ + TCD_INPUT0_DEBUG_full_MASK | \ + TCD_INPUT0_DEBUG_valid_q1_MASK | \ + TCD_INPUT0_DEBUG_cnt_q1_MASK | \ + TCD_INPUT0_DEBUG_last_send_q1_MASK | \ + TCD_INPUT0_DEBUG_ip_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_busy_MASK) + +#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \ + ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \ + (full << TCD_INPUT0_DEBUG_full_SHIFT) | \ + (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \ + (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \ + (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \ + (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \ + (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \ + (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)) + +#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 16; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int : 2; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int : 5; + } tcd_input0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 5; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int : 2; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int : 16; + } tcd_input0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_input0_debug_t f; +} tcd_input0_debug_u; + + +/* + * TCD_DEGAMMA_DEBUG struct + */ + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040 + +#define TCD_DEGAMMA_DEBUG_MASK \ + (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) + +#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \ + ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \ + (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \ + (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \ + (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \ + (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \ + (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)) + +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int : 25; + } tcd_degamma_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int : 25; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + } tcd_degamma_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_degamma_debug_t f; +} tcd_degamma_debug_u; + + +/* + * TCD_DXTMUX_SCTARB_DEBUG struct + */ + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000 + +#define TCD_DXTMUX_SCTARB_DEBUG_MASK \ + (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) + +#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \ + ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \ + (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \ + (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \ + (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \ + (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \ + (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \ + (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \ + (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \ + (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)) + +#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 9; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int : 2; + } tcd_dxtmux_sctarb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 2; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int : 3; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int : 9; + } tcd_dxtmux_sctarb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtmux_sctarb_debug_t f; +} tcd_dxtmux_sctarb_debug_u; + + +/* + * TCD_DXTC_ARB_DEBUG struct + */ + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4 +#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010 +#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000 + +#define TCD_DXTC_ARB_DEBUG_MASK \ + (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \ + TCD_DXTC_ARB_DEBUG_pstate_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \ + TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) + +#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \ + ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \ + (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \ + (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \ + (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \ + (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \ + (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \ + (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \ + (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \ + (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)) + +#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int : 4; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + } tcd_dxtc_arb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int : 4; + } tcd_dxtc_arb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtc_arb_debug_t f; +} tcd_dxtc_arb_debug_u; + + +/* + * TCD_STALLS_DEBUG struct + */ + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000 +#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000 + +#define TCD_STALLS_DEBUG_MASK \ + (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \ + TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \ + TCD_STALLS_DEBUG_not_incoming_rtr_MASK) + +#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \ + ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \ + (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \ + (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \ + (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \ + (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \ + (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)) + +#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int : 11; + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + } tcd_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int : 10; + } tcd_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_stalls_debug_t f; +} tcd_stalls_debug_u; + + +/* + * TCO_STALLS_DEBUG struct + */ + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080 + +#define TCO_STALLS_DEBUG_MASK \ + (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) + +#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \ + ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \ + (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \ + (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)) + +#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 5; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int : 24; + } tco_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 24; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int : 5; + } tco_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_stalls_debug_t f; +} tco_stalls_debug_u; + + +/* + * TCO_QUAD0_DEBUG0 struct + */ + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1 +#define TCO_QUAD0_DEBUG0_busy_SIZE 1 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16 +#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29 +#define TCO_QUAD0_DEBUG0_busy_SHIFT 30 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000 +#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000 +#define TCO_QUAD0_DEBUG0_busy_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG0_MASK \ + (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \ + TCO_QUAD0_DEBUG0_read_cache_q_MASK | \ + TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \ + TCO_QUAD0_DEBUG0_busy_MASK) + +#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \ + ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \ + (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \ + (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \ + (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \ + (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \ + (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \ + (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \ + (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \ + (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \ + (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \ + (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)) + +#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT) + +#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int : 2; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 7; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int : 1; + } tco_quad0_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int : 1; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int : 7; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 2; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + } tco_quad0_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug0_t f; +} tco_quad0_debug0_u; + + +/* + * TCO_QUAD0_DEBUG1 struct + */ + +#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_empty_SIZE 1 +#define TCO_QUAD0_DEBUG1_full_SIZE 1 +#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1 + +#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0 +#define TCO_QUAD0_DEBUG1_empty_SHIFT 1 +#define TCO_QUAD0_DEBUG1_full_SHIFT 2 +#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30 + +#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001 +#define TCO_QUAD0_DEBUG1_empty_MASK 0x00000002 +#define TCO_QUAD0_DEBUG1_full_MASK 0x00000004 +#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800 +#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000 +#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG1_MASK \ + (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_empty_MASK | \ + TCO_QUAD0_DEBUG1_full_MASK | \ + TCO_QUAD0_DEBUG1_write_enable_MASK | \ + TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \ + TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \ + TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \ + TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \ + TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) + +#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \ + ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \ + (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \ + (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \ + (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \ + (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \ + (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \ + (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \ + (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \ + (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \ + (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \ + (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \ + (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \ + (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)) + +#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int : 2; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int : 1; + } tco_quad0_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int : 1; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int : 2; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + } tco_quad0_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug1_t f; +} tco_quad0_debug1_u; + + +#endif + + +#if !defined (_TC_FIDDLE_H) +#define _TC_FIDDLE_H + +/***************************************************************************************************************** + * + * tc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_SC_FIDDLE_H) +#define _SC_FIDDLE_H + +/***************************************************************************************************************** + * + * sc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_BC_FIDDLE_H) +#define _BC_FIDDLE_H + +/***************************************************************************************************************** + * + * bc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * RB_SURFACE_INFO struct + */ + +#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2 + +#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14 + +#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff +#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000 + +#define RB_SURFACE_INFO_MASK \ + (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \ + RB_SURFACE_INFO_MSAA_SAMPLES_MASK) + +#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \ + ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \ + (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)) + +#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int : 16; + } rb_surface_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int : 16; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + } rb_surface_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_surface_info_t f; +} rb_surface_info_u; + + +/* + * RB_COLOR_INFO struct + */ + +#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2 +#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1 +#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2 +#define RB_COLOR_INFO_COLOR_SWAP_SIZE 2 +#define RB_COLOR_INFO_COLOR_BASE_SIZE 20 + +#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4 +#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6 +#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7 +#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9 +#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12 + +#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f +#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030 +#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040 +#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180 +#define RB_COLOR_INFO_COLOR_SWAP_MASK 0x00000600 +#define RB_COLOR_INFO_COLOR_BASE_MASK 0xfffff000 + +#define RB_COLOR_INFO_MASK \ + (RB_COLOR_INFO_COLOR_FORMAT_MASK | \ + RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \ + RB_COLOR_INFO_COLOR_LINEAR_MASK | \ + RB_COLOR_INFO_COLOR_ENDIAN_MASK | \ + RB_COLOR_INFO_COLOR_SWAP_MASK | \ + RB_COLOR_INFO_COLOR_BASE_MASK) + +#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \ + ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \ + (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \ + (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \ + (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \ + (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \ + (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)) + +#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int : 1; + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + } rb_color_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + unsigned int : 1; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + } rb_color_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_info_t f; +} rb_color_info_u; + + +/* + * RB_DEPTH_INFO struct + */ + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1 +#define RB_DEPTH_INFO_DEPTH_BASE_SIZE 20 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0 +#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001 +#define RB_DEPTH_INFO_DEPTH_BASE_MASK 0xfffff000 + +#define RB_DEPTH_INFO_MASK \ + (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \ + RB_DEPTH_INFO_DEPTH_BASE_MASK) + +#define RB_DEPTH_INFO(depth_format, depth_base) \ + ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \ + (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)) + +#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + unsigned int : 11; + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + } rb_depth_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + unsigned int : 11; + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + } rb_depth_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_info_t f; +} rb_depth_info_u; + + +/* + * RB_STENCILREFMASK struct + */ + +#define RB_STENCILREFMASK_STENCILREF_SIZE 8 +#define RB_STENCILREFMASK_STENCILMASK_SIZE 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8 +#define RB_STENCILREFMASK_RESERVED0_SIZE 1 +#define RB_STENCILREFMASK_RESERVED1_SIZE 1 + +#define RB_STENCILREFMASK_STENCILREF_SHIFT 0 +#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16 +#define RB_STENCILREFMASK_RESERVED0_SHIFT 24 +#define RB_STENCILREFMASK_RESERVED1_SHIFT 25 + +#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff +#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00 +#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000 +#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000 +#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000 + +#define RB_STENCILREFMASK_MASK \ + (RB_STENCILREFMASK_STENCILREF_MASK | \ + RB_STENCILREFMASK_STENCILMASK_MASK | \ + RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \ + RB_STENCILREFMASK_RESERVED0_MASK | \ + RB_STENCILREFMASK_RESERVED1_MASK) + +#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \ + ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \ + (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \ + (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \ + (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \ + (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)) + +#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT) + +#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int : 6; + } rb_stencilrefmask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int : 6; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + } rb_stencilrefmask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_t f; +} rb_stencilrefmask_u; + + +/* + * RB_ALPHA_REF struct + */ + +#define RB_ALPHA_REF_ALPHA_REF_SIZE 32 + +#define RB_ALPHA_REF_ALPHA_REF_SHIFT 0 + +#define RB_ALPHA_REF_ALPHA_REF_MASK 0xffffffff + +#define RB_ALPHA_REF_MASK \ + (RB_ALPHA_REF_ALPHA_REF_MASK) + +#define RB_ALPHA_REF(alpha_ref) \ + ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)) + +#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \ + ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \ + rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_alpha_ref_t f; +} rb_alpha_ref_u; + + +/* + * RB_COLOR_MASK struct + */ + +#define RB_COLOR_MASK_WRITE_RED_SIZE 1 +#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1 +#define RB_COLOR_MASK_WRITE_BLUE_SIZE 1 +#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1 +#define RB_COLOR_MASK_RESERVED2_SIZE 1 +#define RB_COLOR_MASK_RESERVED3_SIZE 1 + +#define RB_COLOR_MASK_WRITE_RED_SHIFT 0 +#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1 +#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2 +#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3 +#define RB_COLOR_MASK_RESERVED2_SHIFT 4 +#define RB_COLOR_MASK_RESERVED3_SHIFT 5 + +#define RB_COLOR_MASK_WRITE_RED_MASK 0x00000001 +#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002 +#define RB_COLOR_MASK_WRITE_BLUE_MASK 0x00000004 +#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008 +#define RB_COLOR_MASK_RESERVED2_MASK 0x00000010 +#define RB_COLOR_MASK_RESERVED3_MASK 0x00000020 + +#define RB_COLOR_MASK_MASK \ + (RB_COLOR_MASK_WRITE_RED_MASK | \ + RB_COLOR_MASK_WRITE_GREEN_MASK | \ + RB_COLOR_MASK_WRITE_BLUE_MASK | \ + RB_COLOR_MASK_WRITE_ALPHA_MASK | \ + RB_COLOR_MASK_RESERVED2_MASK | \ + RB_COLOR_MASK_RESERVED3_MASK) + +#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \ + ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \ + (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \ + (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \ + (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \ + (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \ + (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)) + +#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT) + +#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int : 26; + } rb_color_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int : 26; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + } rb_color_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_mask_t f; +} rb_color_mask_u; + + +/* + * RB_BLEND_RED struct + */ + +#define RB_BLEND_RED_BLEND_RED_SIZE 8 + +#define RB_BLEND_RED_BLEND_RED_SHIFT 0 + +#define RB_BLEND_RED_BLEND_RED_MASK 0x000000ff + +#define RB_BLEND_RED_MASK \ + (RB_BLEND_RED_BLEND_RED_MASK) + +#define RB_BLEND_RED(blend_red) \ + ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)) + +#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \ + ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT) + +#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \ + rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + unsigned int : 24; + } rb_blend_red_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int : 24; + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + } rb_blend_red_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_red_t f; +} rb_blend_red_u; + + +/* + * RB_BLEND_GREEN struct + */ + +#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8 + +#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0 + +#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff + +#define RB_BLEND_GREEN_MASK \ + (RB_BLEND_GREEN_BLEND_GREEN_MASK) + +#define RB_BLEND_GREEN(blend_green) \ + ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)) + +#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \ + ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \ + rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + unsigned int : 24; + } rb_blend_green_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int : 24; + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + } rb_blend_green_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_green_t f; +} rb_blend_green_u; + + +/* + * RB_BLEND_BLUE struct + */ + +#define RB_BLEND_BLUE_BLEND_BLUE_SIZE 8 + +#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0 + +#define RB_BLEND_BLUE_BLEND_BLUE_MASK 0x000000ff + +#define RB_BLEND_BLUE_MASK \ + (RB_BLEND_BLUE_BLEND_BLUE_MASK) + +#define RB_BLEND_BLUE(blend_blue) \ + ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)) + +#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \ + ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \ + rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + unsigned int : 24; + } rb_blend_blue_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int : 24; + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + } rb_blend_blue_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_blue_t f; +} rb_blend_blue_u; + + +/* + * RB_BLEND_ALPHA struct + */ + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff + +#define RB_BLEND_ALPHA_MASK \ + (RB_BLEND_ALPHA_BLEND_ALPHA_MASK) + +#define RB_BLEND_ALPHA(blend_alpha) \ + ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)) + +#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \ + ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \ + rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + unsigned int : 24; + } rb_blend_alpha_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int : 24; + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + } rb_blend_alpha_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_alpha_t f; +} rb_blend_alpha_u; + + +/* + * RB_FOG_COLOR struct + */ + +#define RB_FOG_COLOR_FOG_RED_SIZE 8 +#define RB_FOG_COLOR_FOG_GREEN_SIZE 8 +#define RB_FOG_COLOR_FOG_BLUE_SIZE 8 + +#define RB_FOG_COLOR_FOG_RED_SHIFT 0 +#define RB_FOG_COLOR_FOG_GREEN_SHIFT 8 +#define RB_FOG_COLOR_FOG_BLUE_SHIFT 16 + +#define RB_FOG_COLOR_FOG_RED_MASK 0x000000ff +#define RB_FOG_COLOR_FOG_GREEN_MASK 0x0000ff00 +#define RB_FOG_COLOR_FOG_BLUE_MASK 0x00ff0000 + +#define RB_FOG_COLOR_MASK \ + (RB_FOG_COLOR_FOG_RED_MASK | \ + RB_FOG_COLOR_FOG_GREEN_MASK | \ + RB_FOG_COLOR_FOG_BLUE_MASK) + +#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \ + ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \ + (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \ + (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)) + +#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int : 8; + } rb_fog_color_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int : 8; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + } rb_fog_color_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_fog_color_t f; +} rb_fog_color_u; + + +/* + * RB_STENCILREFMASK_BF struct + */ + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1 +#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16 +#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24 +#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000 +#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000 +#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000 + +#define RB_STENCILREFMASK_BF_MASK \ + (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_RESERVED4_MASK | \ + RB_STENCILREFMASK_BF_RESERVED5_MASK) + +#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \ + ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \ + (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \ + (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \ + (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \ + (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)) + +#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int : 6; + } rb_stencilrefmask_bf_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int : 6; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + } rb_stencilrefmask_bf_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_bf_t f; +} rb_stencilrefmask_bf_u; + + +/* + * RB_DEPTHCONTROL struct + */ + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_ZFUNC_SIZE 3 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0 +#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3 +#define RB_DEPTHCONTROL_ZFUNC_SHIFT 4 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7 +#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8 +#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11 +#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14 +#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001 +#define RB_DEPTHCONTROL_Z_ENABLE_MASK 0x00000002 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008 +#define RB_DEPTHCONTROL_ZFUNC_MASK 0x00000070 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080 +#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700 +#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800 +#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000 +#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000 + +#define RB_DEPTHCONTROL_MASK \ + (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \ + RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_ZFUNC_MASK | \ + RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) + +#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \ + ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \ + (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \ + (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \ + (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \ + (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \ + (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \ + (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \ + (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \ + (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \ + (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \ + (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \ + (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \ + (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \ + (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)) + +#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + } rb_depthcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + } rb_depthcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depthcontrol_t f; +} rb_depthcontrol_u; + + +/* + * RB_BLENDCONTROL struct + */ + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1 +#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29 +#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f +#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000 +#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000 + +#define RB_BLENDCONTROL_MASK \ + (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \ + RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \ + RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \ + RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_MASK) + +#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \ + ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \ + (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \ + (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \ + (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \ + (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \ + (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \ + (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \ + (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)) + +#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int : 3; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int : 1; + } rb_blendcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int : 1; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int : 3; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + } rb_blendcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blendcontrol_t f; +} rb_blendcontrol_u; + + +/* + * RB_COLORCONTROL struct + */ + +#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1 +#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1 +#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1 +#define RB_COLORCONTROL_ROP_CODE_SIZE 4 +#define RB_COLORCONTROL_DITHER_MODE_SIZE 2 +#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2 +#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2 + +#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4 +#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5 +#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7 +#define RB_COLORCONTROL_ROP_CODE_SHIFT 8 +#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12 +#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14 +#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30 + +#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010 +#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020 +#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080 +#define RB_COLORCONTROL_ROP_CODE_MASK 0x00000f00 +#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000 +#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000 +#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000 + +#define RB_COLORCONTROL_MASK \ + (RB_COLORCONTROL_ALPHA_FUNC_MASK | \ + RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \ + RB_COLORCONTROL_BLEND_DISABLE_MASK | \ + RB_COLORCONTROL_FOG_ENABLE_MASK | \ + RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \ + RB_COLORCONTROL_ROP_CODE_MASK | \ + RB_COLORCONTROL_DITHER_MODE_MASK | \ + RB_COLORCONTROL_DITHER_TYPE_MASK | \ + RB_COLORCONTROL_PIXEL_FOG_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) + +#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \ + ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \ + (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \ + (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \ + (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \ + (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \ + (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \ + (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \ + (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \ + (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \ + (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \ + (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \ + (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \ + (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \ + (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)) + +#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int : 7; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + } rb_colorcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int : 7; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + } rb_colorcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_colorcontrol_t f; +} rb_colorcontrol_u; + + +/* + * RB_MODECONTROL struct + */ + +#define RB_MODECONTROL_EDRAM_MODE_SIZE 3 + +#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0 + +#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007 + +#define RB_MODECONTROL_MASK \ + (RB_MODECONTROL_EDRAM_MODE_MASK) + +#define RB_MODECONTROL(edram_mode) \ + ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)) + +#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \ + ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \ + rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + unsigned int : 29; + } rb_modecontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int : 29; + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + } rb_modecontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_modecontrol_t f; +} rb_modecontrol_u; + + +/* + * RB_COLOR_DEST_MASK struct + */ + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff + +#define RB_COLOR_DEST_MASK_MASK \ + (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) + +#define RB_COLOR_DEST_MASK(color_dest_mask) \ + ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)) + +#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \ + ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \ + rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_dest_mask_t f; +} rb_color_dest_mask_u; + + +/* + * RB_COPY_CONTROL struct + */ + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1 +#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3 +#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008 +#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0 + +#define RB_COPY_CONTROL_MASK \ + (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \ + RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \ + RB_COPY_CONTROL_CLEAR_MASK_MASK) + +#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \ + ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \ + (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \ + (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)) + +#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int : 24; + } rb_copy_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int : 24; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + } rb_copy_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_control_t f; +} rb_copy_control_u; + + +/* + * RB_COPY_DEST_BASE struct + */ + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000 + +#define RB_COPY_DEST_BASE_MASK \ + (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) + +#define RB_COPY_DEST_BASE(copy_dest_base) \ + ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)) + +#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \ + ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \ + rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int : 12; + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + } rb_copy_dest_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + unsigned int : 12; + } rb_copy_dest_base_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_base_t f; +} rb_copy_dest_base_u; + + +/* + * RB_COPY_DEST_PITCH struct + */ + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff + +#define RB_COPY_DEST_PITCH_MASK \ + (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) + +#define RB_COPY_DEST_PITCH(copy_dest_pitch) \ + ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)) + +#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \ + ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \ + rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + unsigned int : 23; + } rb_copy_dest_pitch_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int : 23; + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + } rb_copy_dest_pitch_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pitch_t f; +} rb_copy_dest_pitch_u; + + +/* + * RB_COPY_DEST_INFO struct + */ + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000 + +#define RB_COPY_DEST_INFO_MASK \ + (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) + +#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \ + ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \ + (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \ + (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \ + (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \ + (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \ + (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \ + (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \ + (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \ + (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \ + (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int : 14; + } rb_copy_dest_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int : 14; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + } rb_copy_dest_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_info_t f; +} rb_copy_dest_info_u; + + +/* + * RB_COPY_DEST_PIXEL_OFFSET struct + */ + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000 + +#define RB_COPY_DEST_PIXEL_OFFSET_MASK \ + (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \ + RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) + +#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \ + ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \ + (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)) + +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int : 6; + } rb_copy_dest_pixel_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int : 6; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + } rb_copy_dest_pixel_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pixel_offset_t f; +} rb_copy_dest_pixel_offset_u; + + +/* + * RB_DEPTH_CLEAR struct + */ + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff + +#define RB_DEPTH_CLEAR_MASK \ + (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) + +#define RB_DEPTH_CLEAR(depth_clear) \ + ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)) + +#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \ + ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \ + rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_clear_t f; +} rb_depth_clear_u; + + +/* + * RB_SAMPLE_COUNT_CTL struct + */ + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002 + +#define RB_SAMPLE_COUNT_CTL_MASK \ + (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \ + RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) + +#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \ + ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \ + (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)) + +#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int : 30; + } rb_sample_count_ctl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int : 30; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + } rb_sample_count_ctl_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_ctl_t f; +} rb_sample_count_ctl_u; + + +/* + * RB_SAMPLE_COUNT_ADDR struct + */ + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff + +#define RB_SAMPLE_COUNT_ADDR_MASK \ + (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) + +#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \ + ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)) + +#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \ + ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \ + rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_addr_t f; +} rb_sample_count_addr_u; + + +/* + * RB_BC_CONTROL struct + */ + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1 +#define RB_BC_CONTROL_CRC_MODE_SIZE 1 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1 +#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_CRC_SYSTEM_SIZE 1 +#define RB_BC_CONTROL_RESERVED6_SIZE 1 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14 +#define RB_BC_CONTROL_CRC_MODE_SHIFT 15 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16 +#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29 +#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30 +#define RB_BC_CONTROL_RESERVED6_SHIFT 31 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000 +#define RB_BC_CONTROL_CRC_MODE_MASK 0x00008000 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000 +#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000 +#define RB_BC_CONTROL_CRC_SYSTEM_MASK 0x40000000 +#define RB_BC_CONTROL_RESERVED6_MASK 0x80000000 + +#define RB_BC_CONTROL_MASK \ + (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \ + RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \ + RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \ + RB_BC_CONTROL_CRC_MODE_MASK | \ + RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \ + RB_BC_CONTROL_DISABLE_ACCUM_MASK | \ + RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \ + RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_CRC_SYSTEM_MASK | \ + RB_BC_CONTROL_RESERVED6_MASK) + +#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \ + ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \ + (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \ + (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \ + (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \ + (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \ + (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \ + (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \ + (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \ + (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \ + (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \ + (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \ + (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \ + (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \ + (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \ + (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \ + (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \ + (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \ + (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \ + (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)) + +#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT) + +#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int : 1; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + } rb_bc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int : 1; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + } rb_bc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_control_t f; +} rb_bc_control_u; + + +/* + * RB_EDRAM_INFO struct + */ + +#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2 +#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18 + +#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4 +#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14 + +#define RB_EDRAM_INFO_EDRAM_SIZE_MASK 0x0000000f +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030 +#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000 + +#define RB_EDRAM_INFO_MASK \ + (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \ + RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \ + RB_EDRAM_INFO_EDRAM_RANGE_MASK) + +#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \ + ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \ + (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \ + (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)) + +#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int : 8; + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + } rb_edram_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + unsigned int : 8; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + } rb_edram_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_edram_info_t f; +} rb_edram_info_u; + + +/* + * RB_CRC_RD_PORT struct + */ + +#define RB_CRC_RD_PORT_CRC_DATA_SIZE 32 + +#define RB_CRC_RD_PORT_CRC_DATA_SHIFT 0 + +#define RB_CRC_RD_PORT_CRC_DATA_MASK 0xffffffff + +#define RB_CRC_RD_PORT_MASK \ + (RB_CRC_RD_PORT_CRC_DATA_MASK) + +#define RB_CRC_RD_PORT(crc_data) \ + ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)) + +#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \ + ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \ + rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_rd_port_t f; +} rb_crc_rd_port_u; + + +/* + * RB_CRC_CONTROL struct + */ + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001 + +#define RB_CRC_CONTROL_MASK \ + (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) + +#define RB_CRC_CONTROL(crc_rd_advance) \ + ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)) + +#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \ + ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \ + rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + unsigned int : 31; + } rb_crc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int : 31; + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + } rb_crc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_control_t f; +} rb_crc_control_u; + + +/* + * RB_CRC_MASK struct + */ + +#define RB_CRC_MASK_CRC_MASK_SIZE 32 + +#define RB_CRC_MASK_CRC_MASK_SHIFT 0 + +#define RB_CRC_MASK_CRC_MASK_MASK 0xffffffff + +#define RB_CRC_MASK_MASK \ + (RB_CRC_MASK_CRC_MASK_MASK) + +#define RB_CRC_MASK(crc_mask) \ + ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)) + +#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \ + ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT) + +#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \ + rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_mask_t f; +} rb_crc_mask_u; + + +/* + * RB_PERFCOUNTER0_SELECT struct + */ + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define RB_PERFCOUNTER0_SELECT_MASK \ + (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define RB_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \ + ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \ + rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } rb_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } rb_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_select_t f; +} rb_perfcounter0_select_u; + + +/* + * RB_PERFCOUNTER0_LOW struct + */ + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define RB_PERFCOUNTER0_LOW_MASK \ + (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \ + ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \ + rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_low_t f; +} rb_perfcounter0_low_u; + + +/* + * RB_PERFCOUNTER0_HI struct + */ + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define RB_PERFCOUNTER0_HI_MASK \ + (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \ + ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \ + rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } rb_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } rb_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_hi_t f; +} rb_perfcounter0_hi_u; + + +/* + * RB_TOTAL_SAMPLES struct + */ + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff + +#define RB_TOTAL_SAMPLES_MASK \ + (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) + +#define RB_TOTAL_SAMPLES(total_samples) \ + ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)) + +#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \ + ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \ + rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_total_samples_t f; +} rb_total_samples_u; + + +/* + * RB_ZPASS_SAMPLES struct + */ + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff + +#define RB_ZPASS_SAMPLES_MASK \ + (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) + +#define RB_ZPASS_SAMPLES(zpass_samples) \ + ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)) + +#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \ + ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \ + rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zpass_samples_t f; +} rb_zpass_samples_u; + + +/* + * RB_ZFAIL_SAMPLES struct + */ + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff + +#define RB_ZFAIL_SAMPLES_MASK \ + (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) + +#define RB_ZFAIL_SAMPLES(zfail_samples) \ + ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)) + +#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \ + ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \ + rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zfail_samples_t f; +} rb_zfail_samples_u; + + +/* + * RB_SFAIL_SAMPLES struct + */ + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff + +#define RB_SFAIL_SAMPLES_MASK \ + (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) + +#define RB_SFAIL_SAMPLES(sfail_samples) \ + ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)) + +#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \ + ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \ + rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sfail_samples_t f; +} rb_sfail_samples_u; + + +/* + * RB_DEBUG_0 struct + */ + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE 1 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1 +#define RB_DEBUG_0_C_REQ_FULL_SIZE 1 +#define RB_DEBUG_0_C_MASK_FULL_SIZE 1 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7 +#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8 +#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17 +#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18 +#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25 +#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26 +#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28 +#define RB_DEBUG_0_C_REQ_FULL_SHIFT 29 +#define RB_DEBUG_0_C_MASK_FULL_SHIFT 30 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020 +#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK 0x00000040 +#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK 0x00000080 +#define RB_DEBUG_0_RDREQ_C1_FULL_MASK 0x00000100 +#define RB_DEBUG_0_RDREQ_C0_FULL_MASK 0x00000200 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000 +#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK 0x00010000 +#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK 0x00020000 +#define RB_DEBUG_0_WRREQ_C1_FULL_MASK 0x00040000 +#define RB_DEBUG_0_WRREQ_C0_FULL_MASK 0x00080000 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000 +#define RB_DEBUG_0_C_SX_LAT_FULL_MASK 0x04000000 +#define RB_DEBUG_0_C_SX_CMD_FULL_MASK 0x08000000 +#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000 +#define RB_DEBUG_0_C_REQ_FULL_MASK 0x20000000 +#define RB_DEBUG_0_C_MASK_FULL_MASK 0x40000000 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000 + +#define RB_DEBUG_0_MASK \ + (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C0_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \ + RB_DEBUG_0_C_SX_LAT_FULL_MASK | \ + RB_DEBUG_0_C_SX_CMD_FULL_MASK | \ + RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \ + RB_DEBUG_0_C_REQ_FULL_MASK | \ + RB_DEBUG_0_C_MASK_FULL_MASK | \ + RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) + +#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \ + ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \ + (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \ + (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \ + (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \ + (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \ + (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \ + (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \ + (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \ + (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \ + (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \ + (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \ + (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \ + (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \ + (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \ + (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \ + (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \ + (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \ + (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \ + (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \ + (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \ + (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \ + (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \ + (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \ + (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \ + (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \ + (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \ + (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)) + +#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + } rb_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + } rb_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_0_t f; +} rb_debug_0_u; + + +/* + * RB_DEBUG_1 struct + */ + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28 +#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT 30 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000 +#define RB_DEBUG_1_C_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_1_C_MASK_EMPTY_MASK 0x40000000 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_1_MASK \ + (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \ + RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \ + RB_DEBUG_1_C_REQ_EMPTY_MASK | \ + RB_DEBUG_1_C_MASK_EMPTY_MASK | \ + RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) + +#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \ + ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \ + (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \ + (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \ + (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \ + (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \ + (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \ + (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \ + (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \ + (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \ + (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \ + (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \ + (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \ + (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \ + (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \ + (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \ + (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \ + (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \ + (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \ + (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \ + (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \ + (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \ + (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \ + (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \ + (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)) + +#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + } rb_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + } rb_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_1_t f; +} rb_debug_1_u; + + +/* + * RB_DEBUG_2 struct + */ + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_FULL_SIZE 1 +#define RB_DEBUG_2_Z_TILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE 1 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16 +#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT 17 +#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT 18 +#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT 19 +#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT 20 +#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT 21 +#define RB_DEBUG_2_Z_TILE_FULL_SHIFT 22 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT 28 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT 30 +#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT 31 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000 +#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000 +#define RB_DEBUG_2_Z0_MASK_FULL_MASK 0x00020000 +#define RB_DEBUG_2_Z1_MASK_FULL_MASK 0x00040000 +#define RB_DEBUG_2_Z0_REQ_FULL_MASK 0x00080000 +#define RB_DEBUG_2_Z1_REQ_FULL_MASK 0x00100000 +#define RB_DEBUG_2_Z_SAMP_FULL_MASK 0x00200000 +#define RB_DEBUG_2_Z_TILE_FULL_MASK 0x00400000 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK 0x04000000 +#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK 0x08000000 +#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK 0x10000000 +#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK 0x40000000 +#define RB_DEBUG_2_Z_TILE_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_2_MASK \ + (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \ + RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \ + RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \ + RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \ + RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \ + RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \ + RB_DEBUG_2_Z0_MASK_FULL_MASK | \ + RB_DEBUG_2_Z1_MASK_FULL_MASK | \ + RB_DEBUG_2_Z0_REQ_FULL_MASK | \ + RB_DEBUG_2_Z1_REQ_FULL_MASK | \ + RB_DEBUG_2_Z_SAMP_FULL_MASK | \ + RB_DEBUG_2_Z_TILE_FULL_MASK | \ + RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \ + RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \ + RB_DEBUG_2_Z_TILE_EMPTY_MASK) + +#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \ + ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \ + (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \ + (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \ + (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \ + (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \ + (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \ + (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \ + (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \ + (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \ + (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \ + (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \ + (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \ + (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \ + (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \ + (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \ + (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \ + (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \ + (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \ + (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \ + (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \ + (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \ + (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \ + (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)) + +#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + } rb_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + } rb_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_2_t f; +} rb_debug_2_u; + + +/* + * RB_DEBUG_3 struct + */ + +#define RB_DEBUG_3_ACCUM_VALID_SIZE 4 +#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4 +#define RB_DEBUG_3_SHD_FULL_SIZE 1 +#define RB_DEBUG_3_SHD_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1 + +#define RB_DEBUG_3_ACCUM_VALID_SHIFT 0 +#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15 +#define RB_DEBUG_3_SHD_FULL_SHIFT 19 +#define RB_DEBUG_3_SHD_EMPTY_SHIFT 20 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28 + +#define RB_DEBUG_3_ACCUM_VALID_MASK 0x0000000f +#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000 +#define RB_DEBUG_3_SHD_FULL_MASK 0x00080000 +#define RB_DEBUG_3_SHD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000 + +#define RB_DEBUG_3_MASK \ + (RB_DEBUG_3_ACCUM_VALID_MASK | \ + RB_DEBUG_3_ACCUM_FLUSHING_MASK | \ + RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \ + RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \ + RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \ + RB_DEBUG_3_SHD_FULL_MASK | \ + RB_DEBUG_3_SHD_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) + +#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \ + ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \ + (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \ + (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \ + (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \ + (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \ + (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \ + (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \ + (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \ + (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \ + (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \ + (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \ + (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \ + (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \ + (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \ + (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)) + +#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int : 3; + } rb_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int : 3; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + } rb_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_3_t f; +} rb_debug_3_u; + + +/* + * RB_DEBUG_4 struct + */ + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00 + +#define RB_DEBUG_4_MASK \ + (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \ + RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \ + RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) + +#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \ + ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \ + (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \ + (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \ + (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \ + (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \ + (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \ + (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \ + (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \ + (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \ + (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)) + +#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int : 19; + } rb_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int : 19; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + } rb_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_4_t f; +} rb_debug_4_u; + + +/* + * RB_FLAG_CONTROL struct + */ + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001 + +#define RB_FLAG_CONTROL_MASK \ + (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) + +#define RB_FLAG_CONTROL(debug_flag_clear) \ + ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)) + +#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \ + ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \ + rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + unsigned int : 31; + } rb_flag_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int : 31; + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + } rb_flag_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_flag_control_t f; +} rb_flag_control_u; + + +/* + * RB_BC_SPARES struct + */ + +#define RB_BC_SPARES_RESERVED_SIZE 32 + +#define RB_BC_SPARES_RESERVED_SHIFT 0 + +#define RB_BC_SPARES_RESERVED_MASK 0xffffffff + +#define RB_BC_SPARES_MASK \ + (RB_BC_SPARES_RESERVED_MASK) + +#define RB_BC_SPARES(reserved) \ + ((reserved << RB_BC_SPARES_RESERVED_SHIFT)) + +#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \ + ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT) + +#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \ + rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_spares_t f; +} rb_bc_spares_u; + + +/* + * BC_DUMMY_CRAYRB_ENUMS struct + */ + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000 + +#define BC_DUMMY_CRAYRB_ENUMS_MASK \ + (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) + +#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \ + ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \ + (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \ + (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \ + (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \ + (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \ + (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \ + (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)) + +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + } bc_dummy_crayrb_enums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + } bc_dummy_crayrb_enums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_enums_t f; +} bc_dummy_crayrb_enums_u; + + +/* + * BC_DUMMY_CRAYRB_MOREENUMS struct + */ + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003 + +#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \ + (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) + +#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \ + ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)) + +#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \ + ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \ + bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + unsigned int : 30; + } bc_dummy_crayrb_moreenums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int : 30; + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + } bc_dummy_crayrb_moreenums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_moreenums_t f; +} bc_dummy_crayrb_moreenums_u; + + +#endif + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h new file mode 100644 index 000000000000..6968abb48bd7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h @@ -0,0 +1,550 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_TYPEDEF_HEADER) +#define _yamato_TYPEDEF_HEADER + +#include "yamato_registers.h" + +typedef union PA_CL_VPORT_XSCALE regPA_CL_VPORT_XSCALE; +typedef union PA_CL_VPORT_XOFFSET regPA_CL_VPORT_XOFFSET; +typedef union PA_CL_VPORT_YSCALE regPA_CL_VPORT_YSCALE; +typedef union PA_CL_VPORT_YOFFSET regPA_CL_VPORT_YOFFSET; +typedef union PA_CL_VPORT_ZSCALE regPA_CL_VPORT_ZSCALE; +typedef union PA_CL_VPORT_ZOFFSET regPA_CL_VPORT_ZOFFSET; +typedef union PA_CL_VTE_CNTL regPA_CL_VTE_CNTL; +typedef union PA_CL_CLIP_CNTL regPA_CL_CLIP_CNTL; +typedef union PA_CL_GB_VERT_CLIP_ADJ regPA_CL_GB_VERT_CLIP_ADJ; +typedef union PA_CL_GB_VERT_DISC_ADJ regPA_CL_GB_VERT_DISC_ADJ; +typedef union PA_CL_GB_HORZ_CLIP_ADJ regPA_CL_GB_HORZ_CLIP_ADJ; +typedef union PA_CL_GB_HORZ_DISC_ADJ regPA_CL_GB_HORZ_DISC_ADJ; +typedef union PA_CL_ENHANCE regPA_CL_ENHANCE; +typedef union PA_SC_ENHANCE regPA_SC_ENHANCE; +typedef union PA_SU_VTX_CNTL regPA_SU_VTX_CNTL; +typedef union PA_SU_POINT_SIZE regPA_SU_POINT_SIZE; +typedef union PA_SU_POINT_MINMAX regPA_SU_POINT_MINMAX; +typedef union PA_SU_LINE_CNTL regPA_SU_LINE_CNTL; +typedef union PA_SU_FACE_DATA regPA_SU_FACE_DATA; +typedef union PA_SU_SC_MODE_CNTL regPA_SU_SC_MODE_CNTL; +typedef union PA_SU_POLY_OFFSET_FRONT_SCALE regPA_SU_POLY_OFFSET_FRONT_SCALE; +typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET regPA_SU_POLY_OFFSET_FRONT_OFFSET; +typedef union PA_SU_POLY_OFFSET_BACK_SCALE regPA_SU_POLY_OFFSET_BACK_SCALE; +typedef union PA_SU_POLY_OFFSET_BACK_OFFSET regPA_SU_POLY_OFFSET_BACK_OFFSET; +typedef union PA_SU_PERFCOUNTER0_SELECT regPA_SU_PERFCOUNTER0_SELECT; +typedef union PA_SU_PERFCOUNTER1_SELECT regPA_SU_PERFCOUNTER1_SELECT; +typedef union PA_SU_PERFCOUNTER2_SELECT regPA_SU_PERFCOUNTER2_SELECT; +typedef union PA_SU_PERFCOUNTER3_SELECT regPA_SU_PERFCOUNTER3_SELECT; +typedef union PA_SU_PERFCOUNTER0_LOW regPA_SU_PERFCOUNTER0_LOW; +typedef union PA_SU_PERFCOUNTER0_HI regPA_SU_PERFCOUNTER0_HI; +typedef union PA_SU_PERFCOUNTER1_LOW regPA_SU_PERFCOUNTER1_LOW; +typedef union PA_SU_PERFCOUNTER1_HI regPA_SU_PERFCOUNTER1_HI; +typedef union PA_SU_PERFCOUNTER2_LOW regPA_SU_PERFCOUNTER2_LOW; +typedef union PA_SU_PERFCOUNTER2_HI regPA_SU_PERFCOUNTER2_HI; +typedef union PA_SU_PERFCOUNTER3_LOW regPA_SU_PERFCOUNTER3_LOW; +typedef union PA_SU_PERFCOUNTER3_HI regPA_SU_PERFCOUNTER3_HI; +typedef union PA_SC_WINDOW_OFFSET regPA_SC_WINDOW_OFFSET; +typedef union PA_SC_AA_CONFIG regPA_SC_AA_CONFIG; +typedef union PA_SC_AA_MASK regPA_SC_AA_MASK; +typedef union PA_SC_LINE_STIPPLE regPA_SC_LINE_STIPPLE; +typedef union PA_SC_LINE_CNTL regPA_SC_LINE_CNTL; +typedef union PA_SC_WINDOW_SCISSOR_TL regPA_SC_WINDOW_SCISSOR_TL; +typedef union PA_SC_WINDOW_SCISSOR_BR regPA_SC_WINDOW_SCISSOR_BR; +typedef union PA_SC_SCREEN_SCISSOR_TL regPA_SC_SCREEN_SCISSOR_TL; +typedef union PA_SC_SCREEN_SCISSOR_BR regPA_SC_SCREEN_SCISSOR_BR; +typedef union PA_SC_VIZ_QUERY regPA_SC_VIZ_QUERY; +typedef union PA_SC_VIZ_QUERY_STATUS regPA_SC_VIZ_QUERY_STATUS; +typedef union PA_SC_LINE_STIPPLE_STATE regPA_SC_LINE_STIPPLE_STATE; +typedef union PA_SC_PERFCOUNTER0_SELECT regPA_SC_PERFCOUNTER0_SELECT; +typedef union PA_SC_PERFCOUNTER0_LOW regPA_SC_PERFCOUNTER0_LOW; +typedef union PA_SC_PERFCOUNTER0_HI regPA_SC_PERFCOUNTER0_HI; +typedef union PA_CL_CNTL_STATUS regPA_CL_CNTL_STATUS; +typedef union PA_SU_CNTL_STATUS regPA_SU_CNTL_STATUS; +typedef union PA_SC_CNTL_STATUS regPA_SC_CNTL_STATUS; +typedef union PA_SU_DEBUG_CNTL regPA_SU_DEBUG_CNTL; +typedef union PA_SU_DEBUG_DATA regPA_SU_DEBUG_DATA; +typedef union PA_SC_DEBUG_CNTL regPA_SC_DEBUG_CNTL; +typedef union PA_SC_DEBUG_DATA regPA_SC_DEBUG_DATA; +typedef union GFX_COPY_STATE regGFX_COPY_STATE; +typedef union VGT_DRAW_INITIATOR regVGT_DRAW_INITIATOR; +typedef union VGT_EVENT_INITIATOR regVGT_EVENT_INITIATOR; +typedef union VGT_DMA_BASE regVGT_DMA_BASE; +typedef union VGT_DMA_SIZE regVGT_DMA_SIZE; +typedef union VGT_BIN_BASE regVGT_BIN_BASE; +typedef union VGT_BIN_SIZE regVGT_BIN_SIZE; +typedef union VGT_CURRENT_BIN_ID_MIN regVGT_CURRENT_BIN_ID_MIN; +typedef union VGT_CURRENT_BIN_ID_MAX regVGT_CURRENT_BIN_ID_MAX; +typedef union VGT_IMMED_DATA regVGT_IMMED_DATA; +typedef union VGT_MAX_VTX_INDX regVGT_MAX_VTX_INDX; +typedef union VGT_MIN_VTX_INDX regVGT_MIN_VTX_INDX; +typedef union VGT_INDX_OFFSET regVGT_INDX_OFFSET; +typedef union VGT_VERTEX_REUSE_BLOCK_CNTL regVGT_VERTEX_REUSE_BLOCK_CNTL; +typedef union VGT_OUT_DEALLOC_CNTL regVGT_OUT_DEALLOC_CNTL; +typedef union VGT_MULTI_PRIM_IB_RESET_INDX regVGT_MULTI_PRIM_IB_RESET_INDX; +typedef union VGT_ENHANCE regVGT_ENHANCE; +typedef union VGT_VTX_VECT_EJECT_REG regVGT_VTX_VECT_EJECT_REG; +typedef union VGT_LAST_COPY_STATE regVGT_LAST_COPY_STATE; +typedef union VGT_DEBUG_CNTL regVGT_DEBUG_CNTL; +typedef union VGT_DEBUG_DATA regVGT_DEBUG_DATA; +typedef union VGT_CNTL_STATUS regVGT_CNTL_STATUS; +typedef union VGT_CRC_SQ_DATA regVGT_CRC_SQ_DATA; +typedef union VGT_CRC_SQ_CTRL regVGT_CRC_SQ_CTRL; +typedef union VGT_PERFCOUNTER0_SELECT regVGT_PERFCOUNTER0_SELECT; +typedef union VGT_PERFCOUNTER1_SELECT regVGT_PERFCOUNTER1_SELECT; +typedef union VGT_PERFCOUNTER2_SELECT regVGT_PERFCOUNTER2_SELECT; +typedef union VGT_PERFCOUNTER3_SELECT regVGT_PERFCOUNTER3_SELECT; +typedef union VGT_PERFCOUNTER0_LOW regVGT_PERFCOUNTER0_LOW; +typedef union VGT_PERFCOUNTER1_LOW regVGT_PERFCOUNTER1_LOW; +typedef union VGT_PERFCOUNTER2_LOW regVGT_PERFCOUNTER2_LOW; +typedef union VGT_PERFCOUNTER3_LOW regVGT_PERFCOUNTER3_LOW; +typedef union VGT_PERFCOUNTER0_HI regVGT_PERFCOUNTER0_HI; +typedef union VGT_PERFCOUNTER1_HI regVGT_PERFCOUNTER1_HI; +typedef union VGT_PERFCOUNTER2_HI regVGT_PERFCOUNTER2_HI; +typedef union VGT_PERFCOUNTER3_HI regVGT_PERFCOUNTER3_HI; +typedef union TC_CNTL_STATUS regTC_CNTL_STATUS; +typedef union TCR_CHICKEN regTCR_CHICKEN; +typedef union TCF_CHICKEN regTCF_CHICKEN; +typedef union TCM_CHICKEN regTCM_CHICKEN; +typedef union TCR_PERFCOUNTER0_SELECT regTCR_PERFCOUNTER0_SELECT; +typedef union TCR_PERFCOUNTER1_SELECT regTCR_PERFCOUNTER1_SELECT; +typedef union TCR_PERFCOUNTER0_HI regTCR_PERFCOUNTER0_HI; +typedef union TCR_PERFCOUNTER1_HI regTCR_PERFCOUNTER1_HI; +typedef union TCR_PERFCOUNTER0_LOW regTCR_PERFCOUNTER0_LOW; +typedef union TCR_PERFCOUNTER1_LOW regTCR_PERFCOUNTER1_LOW; +typedef union TP_TC_CLKGATE_CNTL regTP_TC_CLKGATE_CNTL; +typedef union TPC_CNTL_STATUS regTPC_CNTL_STATUS; +typedef union TPC_DEBUG0 regTPC_DEBUG0; +typedef union TPC_DEBUG1 regTPC_DEBUG1; +typedef union TPC_CHICKEN regTPC_CHICKEN; +typedef union TP0_CNTL_STATUS regTP0_CNTL_STATUS; +typedef union TP0_DEBUG regTP0_DEBUG; +typedef union TP0_CHICKEN regTP0_CHICKEN; +typedef union TP0_PERFCOUNTER0_SELECT regTP0_PERFCOUNTER0_SELECT; +typedef union TP0_PERFCOUNTER0_HI regTP0_PERFCOUNTER0_HI; +typedef union TP0_PERFCOUNTER0_LOW regTP0_PERFCOUNTER0_LOW; +typedef union TP0_PERFCOUNTER1_SELECT regTP0_PERFCOUNTER1_SELECT; +typedef union TP0_PERFCOUNTER1_HI regTP0_PERFCOUNTER1_HI; +typedef union TP0_PERFCOUNTER1_LOW regTP0_PERFCOUNTER1_LOW; +typedef union TCM_PERFCOUNTER0_SELECT regTCM_PERFCOUNTER0_SELECT; +typedef union TCM_PERFCOUNTER1_SELECT regTCM_PERFCOUNTER1_SELECT; +typedef union TCM_PERFCOUNTER0_HI regTCM_PERFCOUNTER0_HI; +typedef union TCM_PERFCOUNTER1_HI regTCM_PERFCOUNTER1_HI; +typedef union TCM_PERFCOUNTER0_LOW regTCM_PERFCOUNTER0_LOW; +typedef union TCM_PERFCOUNTER1_LOW regTCM_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER0_SELECT regTCF_PERFCOUNTER0_SELECT; +typedef union TCF_PERFCOUNTER1_SELECT regTCF_PERFCOUNTER1_SELECT; +typedef union TCF_PERFCOUNTER2_SELECT regTCF_PERFCOUNTER2_SELECT; +typedef union TCF_PERFCOUNTER3_SELECT regTCF_PERFCOUNTER3_SELECT; +typedef union TCF_PERFCOUNTER4_SELECT regTCF_PERFCOUNTER4_SELECT; +typedef union TCF_PERFCOUNTER5_SELECT regTCF_PERFCOUNTER5_SELECT; +typedef union TCF_PERFCOUNTER6_SELECT regTCF_PERFCOUNTER6_SELECT; +typedef union TCF_PERFCOUNTER7_SELECT regTCF_PERFCOUNTER7_SELECT; +typedef union TCF_PERFCOUNTER8_SELECT regTCF_PERFCOUNTER8_SELECT; +typedef union TCF_PERFCOUNTER9_SELECT regTCF_PERFCOUNTER9_SELECT; +typedef union TCF_PERFCOUNTER10_SELECT regTCF_PERFCOUNTER10_SELECT; +typedef union TCF_PERFCOUNTER11_SELECT regTCF_PERFCOUNTER11_SELECT; +typedef union TCF_PERFCOUNTER0_HI regTCF_PERFCOUNTER0_HI; +typedef union TCF_PERFCOUNTER1_HI regTCF_PERFCOUNTER1_HI; +typedef union TCF_PERFCOUNTER2_HI regTCF_PERFCOUNTER2_HI; +typedef union TCF_PERFCOUNTER3_HI regTCF_PERFCOUNTER3_HI; +typedef union TCF_PERFCOUNTER4_HI regTCF_PERFCOUNTER4_HI; +typedef union TCF_PERFCOUNTER5_HI regTCF_PERFCOUNTER5_HI; +typedef union TCF_PERFCOUNTER6_HI regTCF_PERFCOUNTER6_HI; +typedef union TCF_PERFCOUNTER7_HI regTCF_PERFCOUNTER7_HI; +typedef union TCF_PERFCOUNTER8_HI regTCF_PERFCOUNTER8_HI; +typedef union TCF_PERFCOUNTER9_HI regTCF_PERFCOUNTER9_HI; +typedef union TCF_PERFCOUNTER10_HI regTCF_PERFCOUNTER10_HI; +typedef union TCF_PERFCOUNTER11_HI regTCF_PERFCOUNTER11_HI; +typedef union TCF_PERFCOUNTER0_LOW regTCF_PERFCOUNTER0_LOW; +typedef union TCF_PERFCOUNTER1_LOW regTCF_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER2_LOW regTCF_PERFCOUNTER2_LOW; +typedef union TCF_PERFCOUNTER3_LOW regTCF_PERFCOUNTER3_LOW; +typedef union TCF_PERFCOUNTER4_LOW regTCF_PERFCOUNTER4_LOW; +typedef union TCF_PERFCOUNTER5_LOW regTCF_PERFCOUNTER5_LOW; +typedef union TCF_PERFCOUNTER6_LOW regTCF_PERFCOUNTER6_LOW; +typedef union TCF_PERFCOUNTER7_LOW regTCF_PERFCOUNTER7_LOW; +typedef union TCF_PERFCOUNTER8_LOW regTCF_PERFCOUNTER8_LOW; +typedef union TCF_PERFCOUNTER9_LOW regTCF_PERFCOUNTER9_LOW; +typedef union TCF_PERFCOUNTER10_LOW regTCF_PERFCOUNTER10_LOW; +typedef union TCF_PERFCOUNTER11_LOW regTCF_PERFCOUNTER11_LOW; +typedef union TCF_DEBUG regTCF_DEBUG; +typedef union TCA_FIFO_DEBUG regTCA_FIFO_DEBUG; +typedef union TCA_PROBE_DEBUG regTCA_PROBE_DEBUG; +typedef union TCA_TPC_DEBUG regTCA_TPC_DEBUG; +typedef union TCB_CORE_DEBUG regTCB_CORE_DEBUG; +typedef union TCB_TAG0_DEBUG regTCB_TAG0_DEBUG; +typedef union TCB_TAG1_DEBUG regTCB_TAG1_DEBUG; +typedef union TCB_TAG2_DEBUG regTCB_TAG2_DEBUG; +typedef union TCB_TAG3_DEBUG regTCB_TAG3_DEBUG; +typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG; +typedef union TCB_FETCH_GEN_WALKER_DEBUG regTCB_FETCH_GEN_WALKER_DEBUG; +typedef union TCB_FETCH_GEN_PIPE0_DEBUG regTCB_FETCH_GEN_PIPE0_DEBUG; +typedef union TCD_INPUT0_DEBUG regTCD_INPUT0_DEBUG; +typedef union TCD_DEGAMMA_DEBUG regTCD_DEGAMMA_DEBUG; +typedef union TCD_DXTMUX_SCTARB_DEBUG regTCD_DXTMUX_SCTARB_DEBUG; +typedef union TCD_DXTC_ARB_DEBUG regTCD_DXTC_ARB_DEBUG; +typedef union TCD_STALLS_DEBUG regTCD_STALLS_DEBUG; +typedef union TCO_STALLS_DEBUG regTCO_STALLS_DEBUG; +typedef union TCO_QUAD0_DEBUG0 regTCO_QUAD0_DEBUG0; +typedef union TCO_QUAD0_DEBUG1 regTCO_QUAD0_DEBUG1; +typedef union SQ_GPR_MANAGEMENT regSQ_GPR_MANAGEMENT; +typedef union SQ_FLOW_CONTROL regSQ_FLOW_CONTROL; +typedef union SQ_INST_STORE_MANAGMENT regSQ_INST_STORE_MANAGMENT; +typedef union SQ_RESOURCE_MANAGMENT regSQ_RESOURCE_MANAGMENT; +typedef union SQ_EO_RT regSQ_EO_RT; +typedef union SQ_DEBUG_MISC regSQ_DEBUG_MISC; +typedef union SQ_ACTIVITY_METER_CNTL regSQ_ACTIVITY_METER_CNTL; +typedef union SQ_ACTIVITY_METER_STATUS regSQ_ACTIVITY_METER_STATUS; +typedef union SQ_INPUT_ARB_PRIORITY regSQ_INPUT_ARB_PRIORITY; +typedef union SQ_THREAD_ARB_PRIORITY regSQ_THREAD_ARB_PRIORITY; +typedef union SQ_VS_WATCHDOG_TIMER regSQ_VS_WATCHDOG_TIMER; +typedef union SQ_PS_WATCHDOG_TIMER regSQ_PS_WATCHDOG_TIMER; +typedef union SQ_INT_CNTL regSQ_INT_CNTL; +typedef union SQ_INT_STATUS regSQ_INT_STATUS; +typedef union SQ_INT_ACK regSQ_INT_ACK; +typedef union SQ_DEBUG_INPUT_FSM regSQ_DEBUG_INPUT_FSM; +typedef union SQ_DEBUG_CONST_MGR_FSM regSQ_DEBUG_CONST_MGR_FSM; +typedef union SQ_DEBUG_TP_FSM regSQ_DEBUG_TP_FSM; +typedef union SQ_DEBUG_FSM_ALU_0 regSQ_DEBUG_FSM_ALU_0; +typedef union SQ_DEBUG_FSM_ALU_1 regSQ_DEBUG_FSM_ALU_1; +typedef union SQ_DEBUG_EXP_ALLOC regSQ_DEBUG_EXP_ALLOC; +typedef union SQ_DEBUG_PTR_BUFF regSQ_DEBUG_PTR_BUFF; +typedef union SQ_DEBUG_GPR_VTX regSQ_DEBUG_GPR_VTX; +typedef union SQ_DEBUG_GPR_PIX regSQ_DEBUG_GPR_PIX; +typedef union SQ_DEBUG_TB_STATUS_SEL regSQ_DEBUG_TB_STATUS_SEL; +typedef union SQ_DEBUG_VTX_TB_0 regSQ_DEBUG_VTX_TB_0; +typedef union SQ_DEBUG_VTX_TB_1 regSQ_DEBUG_VTX_TB_1; +typedef union SQ_DEBUG_VTX_TB_STATUS_REG regSQ_DEBUG_VTX_TB_STATUS_REG; +typedef union SQ_DEBUG_VTX_TB_STATE_MEM regSQ_DEBUG_VTX_TB_STATE_MEM; +typedef union SQ_DEBUG_PIX_TB_0 regSQ_DEBUG_PIX_TB_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0 regSQ_DEBUG_PIX_TB_STATUS_REG_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1 regSQ_DEBUG_PIX_TB_STATUS_REG_1; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2 regSQ_DEBUG_PIX_TB_STATUS_REG_2; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3 regSQ_DEBUG_PIX_TB_STATUS_REG_3; +typedef union SQ_DEBUG_PIX_TB_STATE_MEM regSQ_DEBUG_PIX_TB_STATE_MEM; +typedef union SQ_PERFCOUNTER0_SELECT regSQ_PERFCOUNTER0_SELECT; +typedef union SQ_PERFCOUNTER1_SELECT regSQ_PERFCOUNTER1_SELECT; +typedef union SQ_PERFCOUNTER2_SELECT regSQ_PERFCOUNTER2_SELECT; +typedef union SQ_PERFCOUNTER3_SELECT regSQ_PERFCOUNTER3_SELECT; +typedef union SQ_PERFCOUNTER0_LOW regSQ_PERFCOUNTER0_LOW; +typedef union SQ_PERFCOUNTER0_HI regSQ_PERFCOUNTER0_HI; +typedef union SQ_PERFCOUNTER1_LOW regSQ_PERFCOUNTER1_LOW; +typedef union SQ_PERFCOUNTER1_HI regSQ_PERFCOUNTER1_HI; +typedef union SQ_PERFCOUNTER2_LOW regSQ_PERFCOUNTER2_LOW; +typedef union SQ_PERFCOUNTER2_HI regSQ_PERFCOUNTER2_HI; +typedef union SQ_PERFCOUNTER3_LOW regSQ_PERFCOUNTER3_LOW; +typedef union SQ_PERFCOUNTER3_HI regSQ_PERFCOUNTER3_HI; +typedef union SX_PERFCOUNTER0_SELECT regSX_PERFCOUNTER0_SELECT; +typedef union SX_PERFCOUNTER0_LOW regSX_PERFCOUNTER0_LOW; +typedef union SX_PERFCOUNTER0_HI regSX_PERFCOUNTER0_HI; +typedef union SQ_INSTRUCTION_ALU_0 regSQ_INSTRUCTION_ALU_0; +typedef union SQ_INSTRUCTION_ALU_1 regSQ_INSTRUCTION_ALU_1; +typedef union SQ_INSTRUCTION_ALU_2 regSQ_INSTRUCTION_ALU_2; +typedef union SQ_INSTRUCTION_CF_EXEC_0 regSQ_INSTRUCTION_CF_EXEC_0; +typedef union SQ_INSTRUCTION_CF_EXEC_1 regSQ_INSTRUCTION_CF_EXEC_1; +typedef union SQ_INSTRUCTION_CF_EXEC_2 regSQ_INSTRUCTION_CF_EXEC_2; +typedef union SQ_INSTRUCTION_CF_LOOP_0 regSQ_INSTRUCTION_CF_LOOP_0; +typedef union SQ_INSTRUCTION_CF_LOOP_1 regSQ_INSTRUCTION_CF_LOOP_1; +typedef union SQ_INSTRUCTION_CF_LOOP_2 regSQ_INSTRUCTION_CF_LOOP_2; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_0 regSQ_INSTRUCTION_CF_JMP_CALL_0; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_1 regSQ_INSTRUCTION_CF_JMP_CALL_1; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_2 regSQ_INSTRUCTION_CF_JMP_CALL_2; +typedef union SQ_INSTRUCTION_CF_ALLOC_0 regSQ_INSTRUCTION_CF_ALLOC_0; +typedef union SQ_INSTRUCTION_CF_ALLOC_1 regSQ_INSTRUCTION_CF_ALLOC_1; +typedef union SQ_INSTRUCTION_CF_ALLOC_2 regSQ_INSTRUCTION_CF_ALLOC_2; +typedef union SQ_INSTRUCTION_TFETCH_0 regSQ_INSTRUCTION_TFETCH_0; +typedef union SQ_INSTRUCTION_TFETCH_1 regSQ_INSTRUCTION_TFETCH_1; +typedef union SQ_INSTRUCTION_TFETCH_2 regSQ_INSTRUCTION_TFETCH_2; +typedef union SQ_INSTRUCTION_VFETCH_0 regSQ_INSTRUCTION_VFETCH_0; +typedef union SQ_INSTRUCTION_VFETCH_1 regSQ_INSTRUCTION_VFETCH_1; +typedef union SQ_INSTRUCTION_VFETCH_2 regSQ_INSTRUCTION_VFETCH_2; +typedef union SQ_CONSTANT_0 regSQ_CONSTANT_0; +typedef union SQ_CONSTANT_1 regSQ_CONSTANT_1; +typedef union SQ_CONSTANT_2 regSQ_CONSTANT_2; +typedef union SQ_CONSTANT_3 regSQ_CONSTANT_3; +typedef union SQ_FETCH_0 regSQ_FETCH_0; +typedef union SQ_FETCH_1 regSQ_FETCH_1; +typedef union SQ_FETCH_2 regSQ_FETCH_2; +typedef union SQ_FETCH_3 regSQ_FETCH_3; +typedef union SQ_FETCH_4 regSQ_FETCH_4; +typedef union SQ_FETCH_5 regSQ_FETCH_5; +typedef union SQ_CONSTANT_VFETCH_0 regSQ_CONSTANT_VFETCH_0; +typedef union SQ_CONSTANT_VFETCH_1 regSQ_CONSTANT_VFETCH_1; +typedef union SQ_CONSTANT_T2 regSQ_CONSTANT_T2; +typedef union SQ_CONSTANT_T3 regSQ_CONSTANT_T3; +typedef union SQ_CF_BOOLEANS regSQ_CF_BOOLEANS; +typedef union SQ_CF_LOOP regSQ_CF_LOOP; +typedef union SQ_CONSTANT_RT_0 regSQ_CONSTANT_RT_0; +typedef union SQ_CONSTANT_RT_1 regSQ_CONSTANT_RT_1; +typedef union SQ_CONSTANT_RT_2 regSQ_CONSTANT_RT_2; +typedef union SQ_CONSTANT_RT_3 regSQ_CONSTANT_RT_3; +typedef union SQ_FETCH_RT_0 regSQ_FETCH_RT_0; +typedef union SQ_FETCH_RT_1 regSQ_FETCH_RT_1; +typedef union SQ_FETCH_RT_2 regSQ_FETCH_RT_2; +typedef union SQ_FETCH_RT_3 regSQ_FETCH_RT_3; +typedef union SQ_FETCH_RT_4 regSQ_FETCH_RT_4; +typedef union SQ_FETCH_RT_5 regSQ_FETCH_RT_5; +typedef union SQ_CF_RT_BOOLEANS regSQ_CF_RT_BOOLEANS; +typedef union SQ_CF_RT_LOOP regSQ_CF_RT_LOOP; +typedef union SQ_VS_PROGRAM regSQ_VS_PROGRAM; +typedef union SQ_PS_PROGRAM regSQ_PS_PROGRAM; +typedef union SQ_CF_PROGRAM_SIZE regSQ_CF_PROGRAM_SIZE; +typedef union SQ_INTERPOLATOR_CNTL regSQ_INTERPOLATOR_CNTL; +typedef union SQ_PROGRAM_CNTL regSQ_PROGRAM_CNTL; +typedef union SQ_WRAPPING_0 regSQ_WRAPPING_0; +typedef union SQ_WRAPPING_1 regSQ_WRAPPING_1; +typedef union SQ_VS_CONST regSQ_VS_CONST; +typedef union SQ_PS_CONST regSQ_PS_CONST; +typedef union SQ_CONTEXT_MISC regSQ_CONTEXT_MISC; +typedef union SQ_CF_RD_BASE regSQ_CF_RD_BASE; +typedef union SQ_DEBUG_MISC_0 regSQ_DEBUG_MISC_0; +typedef union SQ_DEBUG_MISC_1 regSQ_DEBUG_MISC_1; +typedef union MH_ARBITER_CONFIG regMH_ARBITER_CONFIG; +typedef union MH_CLNT_AXI_ID_REUSE regMH_CLNT_AXI_ID_REUSE; +typedef union MH_INTERRUPT_MASK regMH_INTERRUPT_MASK; +typedef union MH_INTERRUPT_STATUS regMH_INTERRUPT_STATUS; +typedef union MH_INTERRUPT_CLEAR regMH_INTERRUPT_CLEAR; +typedef union MH_AXI_ERROR regMH_AXI_ERROR; +typedef union MH_PERFCOUNTER0_SELECT regMH_PERFCOUNTER0_SELECT; +typedef union MH_PERFCOUNTER1_SELECT regMH_PERFCOUNTER1_SELECT; +typedef union MH_PERFCOUNTER0_CONFIG regMH_PERFCOUNTER0_CONFIG; +typedef union MH_PERFCOUNTER1_CONFIG regMH_PERFCOUNTER1_CONFIG; +typedef union MH_PERFCOUNTER0_LOW regMH_PERFCOUNTER0_LOW; +typedef union MH_PERFCOUNTER1_LOW regMH_PERFCOUNTER1_LOW; +typedef union MH_PERFCOUNTER0_HI regMH_PERFCOUNTER0_HI; +typedef union MH_PERFCOUNTER1_HI regMH_PERFCOUNTER1_HI; +typedef union MH_DEBUG_CTRL regMH_DEBUG_CTRL; +typedef union MH_DEBUG_DATA regMH_DEBUG_DATA; +typedef union MH_AXI_HALT_CONTROL regMH_AXI_HALT_CONTROL; +typedef union MH_MMU_CONFIG regMH_MMU_CONFIG; +typedef union MH_MMU_VA_RANGE regMH_MMU_VA_RANGE; +typedef union MH_MMU_PT_BASE regMH_MMU_PT_BASE; +typedef union MH_MMU_PAGE_FAULT regMH_MMU_PAGE_FAULT; +typedef union MH_MMU_TRAN_ERROR regMH_MMU_TRAN_ERROR; +typedef union MH_MMU_INVALIDATE regMH_MMU_INVALIDATE; +typedef union MH_MMU_MPU_BASE regMH_MMU_MPU_BASE; +typedef union MH_MMU_MPU_END regMH_MMU_MPU_END; +typedef union WAIT_UNTIL regWAIT_UNTIL; +typedef union RBBM_ISYNC_CNTL regRBBM_ISYNC_CNTL; +typedef union RBBM_STATUS regRBBM_STATUS; +typedef union RBBM_DSPLY regRBBM_DSPLY; +typedef union RBBM_RENDER_LATEST regRBBM_RENDER_LATEST; +typedef union RBBM_RTL_RELEASE regRBBM_RTL_RELEASE; +typedef union RBBM_PATCH_RELEASE regRBBM_PATCH_RELEASE; +typedef union RBBM_AUXILIARY_CONFIG regRBBM_AUXILIARY_CONFIG; +typedef union RBBM_PERIPHID0 regRBBM_PERIPHID0; +typedef union RBBM_PERIPHID1 regRBBM_PERIPHID1; +typedef union RBBM_PERIPHID2 regRBBM_PERIPHID2; +typedef union RBBM_PERIPHID3 regRBBM_PERIPHID3; +typedef union RBBM_CNTL regRBBM_CNTL; +typedef union RBBM_SKEW_CNTL regRBBM_SKEW_CNTL; +typedef union RBBM_SOFT_RESET regRBBM_SOFT_RESET; +typedef union RBBM_PM_OVERRIDE1 regRBBM_PM_OVERRIDE1; +typedef union RBBM_PM_OVERRIDE2 regRBBM_PM_OVERRIDE2; +typedef union GC_SYS_IDLE regGC_SYS_IDLE; +typedef union NQWAIT_UNTIL regNQWAIT_UNTIL; +typedef union RBBM_DEBUG_OUT regRBBM_DEBUG_OUT; +typedef union RBBM_DEBUG_CNTL regRBBM_DEBUG_CNTL; +typedef union RBBM_DEBUG regRBBM_DEBUG; +typedef union RBBM_READ_ERROR regRBBM_READ_ERROR; +typedef union RBBM_WAIT_IDLE_CLOCKS regRBBM_WAIT_IDLE_CLOCKS; +typedef union RBBM_INT_CNTL regRBBM_INT_CNTL; +typedef union RBBM_INT_STATUS regRBBM_INT_STATUS; +typedef union RBBM_INT_ACK regRBBM_INT_ACK; +typedef union MASTER_INT_SIGNAL regMASTER_INT_SIGNAL; +typedef union RBBM_PERFCOUNTER1_SELECT regRBBM_PERFCOUNTER1_SELECT; +typedef union RBBM_PERFCOUNTER1_LO regRBBM_PERFCOUNTER1_LO; +typedef union RBBM_PERFCOUNTER1_HI regRBBM_PERFCOUNTER1_HI; +typedef union CP_RB_BASE regCP_RB_BASE; +typedef union CP_RB_CNTL regCP_RB_CNTL; +typedef union CP_RB_RPTR_ADDR regCP_RB_RPTR_ADDR; +typedef union CP_RB_RPTR regCP_RB_RPTR; +typedef union CP_RB_RPTR_WR regCP_RB_RPTR_WR; +typedef union CP_RB_WPTR regCP_RB_WPTR; +typedef union CP_RB_WPTR_DELAY regCP_RB_WPTR_DELAY; +typedef union CP_RB_WPTR_BASE regCP_RB_WPTR_BASE; +typedef union CP_IB1_BASE regCP_IB1_BASE; +typedef union CP_IB1_BUFSZ regCP_IB1_BUFSZ; +typedef union CP_IB2_BASE regCP_IB2_BASE; +typedef union CP_IB2_BUFSZ regCP_IB2_BUFSZ; +typedef union CP_ST_BASE regCP_ST_BASE; +typedef union CP_ST_BUFSZ regCP_ST_BUFSZ; +typedef union CP_QUEUE_THRESHOLDS regCP_QUEUE_THRESHOLDS; +typedef union CP_MEQ_THRESHOLDS regCP_MEQ_THRESHOLDS; +typedef union CP_CSQ_AVAIL regCP_CSQ_AVAIL; +typedef union CP_STQ_AVAIL regCP_STQ_AVAIL; +typedef union CP_MEQ_AVAIL regCP_MEQ_AVAIL; +typedef union CP_CSQ_RB_STAT regCP_CSQ_RB_STAT; +typedef union CP_CSQ_IB1_STAT regCP_CSQ_IB1_STAT; +typedef union CP_CSQ_IB2_STAT regCP_CSQ_IB2_STAT; +typedef union CP_NON_PREFETCH_CNTRS regCP_NON_PREFETCH_CNTRS; +typedef union CP_STQ_ST_STAT regCP_STQ_ST_STAT; +typedef union CP_MEQ_STAT regCP_MEQ_STAT; +typedef union CP_MIU_TAG_STAT regCP_MIU_TAG_STAT; +typedef union CP_CMD_INDEX regCP_CMD_INDEX; +typedef union CP_CMD_DATA regCP_CMD_DATA; +typedef union CP_ME_CNTL regCP_ME_CNTL; +typedef union CP_ME_STATUS regCP_ME_STATUS; +typedef union CP_ME_RAM_WADDR regCP_ME_RAM_WADDR; +typedef union CP_ME_RAM_RADDR regCP_ME_RAM_RADDR; +typedef union CP_ME_RAM_DATA regCP_ME_RAM_DATA; +typedef union CP_ME_RDADDR regCP_ME_RDADDR; +typedef union CP_DEBUG regCP_DEBUG; +typedef union SCRATCH_REG0 regSCRATCH_REG0; +typedef union GUI_SCRATCH_REG0 regGUI_SCRATCH_REG0; +typedef union SCRATCH_REG1 regSCRATCH_REG1; +typedef union GUI_SCRATCH_REG1 regGUI_SCRATCH_REG1; +typedef union SCRATCH_REG2 regSCRATCH_REG2; +typedef union GUI_SCRATCH_REG2 regGUI_SCRATCH_REG2; +typedef union SCRATCH_REG3 regSCRATCH_REG3; +typedef union GUI_SCRATCH_REG3 regGUI_SCRATCH_REG3; +typedef union SCRATCH_REG4 regSCRATCH_REG4; +typedef union GUI_SCRATCH_REG4 regGUI_SCRATCH_REG4; +typedef union SCRATCH_REG5 regSCRATCH_REG5; +typedef union GUI_SCRATCH_REG5 regGUI_SCRATCH_REG5; +typedef union SCRATCH_REG6 regSCRATCH_REG6; +typedef union GUI_SCRATCH_REG6 regGUI_SCRATCH_REG6; +typedef union SCRATCH_REG7 regSCRATCH_REG7; +typedef union GUI_SCRATCH_REG7 regGUI_SCRATCH_REG7; +typedef union SCRATCH_UMSK regSCRATCH_UMSK; +typedef union SCRATCH_ADDR regSCRATCH_ADDR; +typedef union CP_ME_VS_EVENT_SRC regCP_ME_VS_EVENT_SRC; +typedef union CP_ME_VS_EVENT_ADDR regCP_ME_VS_EVENT_ADDR; +typedef union CP_ME_VS_EVENT_DATA regCP_ME_VS_EVENT_DATA; +typedef union CP_ME_VS_EVENT_ADDR_SWM regCP_ME_VS_EVENT_ADDR_SWM; +typedef union CP_ME_VS_EVENT_DATA_SWM regCP_ME_VS_EVENT_DATA_SWM; +typedef union CP_ME_PS_EVENT_SRC regCP_ME_PS_EVENT_SRC; +typedef union CP_ME_PS_EVENT_ADDR regCP_ME_PS_EVENT_ADDR; +typedef union CP_ME_PS_EVENT_DATA regCP_ME_PS_EVENT_DATA; +typedef union CP_ME_PS_EVENT_ADDR_SWM regCP_ME_PS_EVENT_ADDR_SWM; +typedef union CP_ME_PS_EVENT_DATA_SWM regCP_ME_PS_EVENT_DATA_SWM; +typedef union CP_ME_CF_EVENT_SRC regCP_ME_CF_EVENT_SRC; +typedef union CP_ME_CF_EVENT_ADDR regCP_ME_CF_EVENT_ADDR; +typedef union CP_ME_CF_EVENT_DATA regCP_ME_CF_EVENT_DATA; +typedef union CP_ME_NRT_ADDR regCP_ME_NRT_ADDR; +typedef union CP_ME_NRT_DATA regCP_ME_NRT_DATA; +typedef union CP_ME_VS_FETCH_DONE_SRC regCP_ME_VS_FETCH_DONE_SRC; +typedef union CP_ME_VS_FETCH_DONE_ADDR regCP_ME_VS_FETCH_DONE_ADDR; +typedef union CP_ME_VS_FETCH_DONE_DATA regCP_ME_VS_FETCH_DONE_DATA; +typedef union CP_INT_CNTL regCP_INT_CNTL; +typedef union CP_INT_STATUS regCP_INT_STATUS; +typedef union CP_INT_ACK regCP_INT_ACK; +typedef union CP_PFP_UCODE_ADDR regCP_PFP_UCODE_ADDR; +typedef union CP_PFP_UCODE_DATA regCP_PFP_UCODE_DATA; +typedef union CP_PERFMON_CNTL regCP_PERFMON_CNTL; +typedef union CP_PERFCOUNTER_SELECT regCP_PERFCOUNTER_SELECT; +typedef union CP_PERFCOUNTER_LO regCP_PERFCOUNTER_LO; +typedef union CP_PERFCOUNTER_HI regCP_PERFCOUNTER_HI; +typedef union CP_BIN_MASK_LO regCP_BIN_MASK_LO; +typedef union CP_BIN_MASK_HI regCP_BIN_MASK_HI; +typedef union CP_BIN_SELECT_LO regCP_BIN_SELECT_LO; +typedef union CP_BIN_SELECT_HI regCP_BIN_SELECT_HI; +typedef union CP_NV_FLAGS_0 regCP_NV_FLAGS_0; +typedef union CP_NV_FLAGS_1 regCP_NV_FLAGS_1; +typedef union CP_NV_FLAGS_2 regCP_NV_FLAGS_2; +typedef union CP_NV_FLAGS_3 regCP_NV_FLAGS_3; +typedef union CP_STATE_DEBUG_INDEX regCP_STATE_DEBUG_INDEX; +typedef union CP_STATE_DEBUG_DATA regCP_STATE_DEBUG_DATA; +typedef union CP_PROG_COUNTER regCP_PROG_COUNTER; +typedef union CP_STAT regCP_STAT; +typedef union BIOS_0_SCRATCH regBIOS_0_SCRATCH; +typedef union BIOS_1_SCRATCH regBIOS_1_SCRATCH; +typedef union BIOS_2_SCRATCH regBIOS_2_SCRATCH; +typedef union BIOS_3_SCRATCH regBIOS_3_SCRATCH; +typedef union BIOS_4_SCRATCH regBIOS_4_SCRATCH; +typedef union BIOS_5_SCRATCH regBIOS_5_SCRATCH; +typedef union BIOS_6_SCRATCH regBIOS_6_SCRATCH; +typedef union BIOS_7_SCRATCH regBIOS_7_SCRATCH; +typedef union BIOS_8_SCRATCH regBIOS_8_SCRATCH; +typedef union BIOS_9_SCRATCH regBIOS_9_SCRATCH; +typedef union BIOS_10_SCRATCH regBIOS_10_SCRATCH; +typedef union BIOS_11_SCRATCH regBIOS_11_SCRATCH; +typedef union BIOS_12_SCRATCH regBIOS_12_SCRATCH; +typedef union BIOS_13_SCRATCH regBIOS_13_SCRATCH; +typedef union BIOS_14_SCRATCH regBIOS_14_SCRATCH; +typedef union BIOS_15_SCRATCH regBIOS_15_SCRATCH; +typedef union COHER_SIZE_PM4 regCOHER_SIZE_PM4; +typedef union COHER_BASE_PM4 regCOHER_BASE_PM4; +typedef union COHER_STATUS_PM4 regCOHER_STATUS_PM4; +typedef union COHER_SIZE_HOST regCOHER_SIZE_HOST; +typedef union COHER_BASE_HOST regCOHER_BASE_HOST; +typedef union COHER_STATUS_HOST regCOHER_STATUS_HOST; +typedef union COHER_DEST_BASE_0 regCOHER_DEST_BASE_0; +typedef union COHER_DEST_BASE_1 regCOHER_DEST_BASE_1; +typedef union COHER_DEST_BASE_2 regCOHER_DEST_BASE_2; +typedef union COHER_DEST_BASE_3 regCOHER_DEST_BASE_3; +typedef union COHER_DEST_BASE_4 regCOHER_DEST_BASE_4; +typedef union COHER_DEST_BASE_5 regCOHER_DEST_BASE_5; +typedef union COHER_DEST_BASE_6 regCOHER_DEST_BASE_6; +typedef union COHER_DEST_BASE_7 regCOHER_DEST_BASE_7; +typedef union RB_SURFACE_INFO regRB_SURFACE_INFO; +typedef union RB_COLOR_INFO regRB_COLOR_INFO; +typedef union RB_DEPTH_INFO regRB_DEPTH_INFO; +typedef union RB_STENCILREFMASK regRB_STENCILREFMASK; +typedef union RB_ALPHA_REF regRB_ALPHA_REF; +typedef union RB_COLOR_MASK regRB_COLOR_MASK; +typedef union RB_BLEND_RED regRB_BLEND_RED; +typedef union RB_BLEND_GREEN regRB_BLEND_GREEN; +typedef union RB_BLEND_BLUE regRB_BLEND_BLUE; +typedef union RB_BLEND_ALPHA regRB_BLEND_ALPHA; +typedef union RB_FOG_COLOR regRB_FOG_COLOR; +typedef union RB_STENCILREFMASK_BF regRB_STENCILREFMASK_BF; +typedef union RB_DEPTHCONTROL regRB_DEPTHCONTROL; +typedef union RB_BLENDCONTROL regRB_BLENDCONTROL; +typedef union RB_COLORCONTROL regRB_COLORCONTROL; +typedef union RB_MODECONTROL regRB_MODECONTROL; +typedef union RB_COLOR_DEST_MASK regRB_COLOR_DEST_MASK; +typedef union RB_COPY_CONTROL regRB_COPY_CONTROL; +typedef union RB_COPY_DEST_BASE regRB_COPY_DEST_BASE; +typedef union RB_COPY_DEST_PITCH regRB_COPY_DEST_PITCH; +typedef union RB_COPY_DEST_INFO regRB_COPY_DEST_INFO; +typedef union RB_COPY_DEST_PIXEL_OFFSET regRB_COPY_DEST_PIXEL_OFFSET; +typedef union RB_DEPTH_CLEAR regRB_DEPTH_CLEAR; +typedef union RB_SAMPLE_COUNT_CTL regRB_SAMPLE_COUNT_CTL; +typedef union RB_SAMPLE_COUNT_ADDR regRB_SAMPLE_COUNT_ADDR; +typedef union RB_BC_CONTROL regRB_BC_CONTROL; +typedef union RB_EDRAM_INFO regRB_EDRAM_INFO; +typedef union RB_CRC_RD_PORT regRB_CRC_RD_PORT; +typedef union RB_CRC_CONTROL regRB_CRC_CONTROL; +typedef union RB_CRC_MASK regRB_CRC_MASK; +typedef union RB_PERFCOUNTER0_SELECT regRB_PERFCOUNTER0_SELECT; +typedef union RB_PERFCOUNTER0_LOW regRB_PERFCOUNTER0_LOW; +typedef union RB_PERFCOUNTER0_HI regRB_PERFCOUNTER0_HI; +typedef union RB_TOTAL_SAMPLES regRB_TOTAL_SAMPLES; +typedef union RB_ZPASS_SAMPLES regRB_ZPASS_SAMPLES; +typedef union RB_ZFAIL_SAMPLES regRB_ZFAIL_SAMPLES; +typedef union RB_SFAIL_SAMPLES regRB_SFAIL_SAMPLES; +typedef union RB_DEBUG_0 regRB_DEBUG_0; +typedef union RB_DEBUG_1 regRB_DEBUG_1; +typedef union RB_DEBUG_2 regRB_DEBUG_2; +typedef union RB_DEBUG_3 regRB_DEBUG_3; +typedef union RB_DEBUG_4 regRB_DEBUG_4; +typedef union RB_FLAG_CONTROL regRB_FLAG_CONTROL; +typedef union RB_BC_SPARES regRB_BC_SPARES; +typedef union BC_DUMMY_CRAYRB_ENUMS regBC_DUMMY_CRAYRB_ENUMS; +typedef union BC_DUMMY_CRAYRB_MOREENUMS regBC_DUMMY_CRAYRB_MOREENUMS; +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h new file mode 100644 index 000000000000..ba259a6c9d5f --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h @@ -0,0 +1,169 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamatoix_h +#define _yamatoix_h + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +// [SUDEBUGIND] : Indirect Registers + +#define ixCLIPPER_DEBUG_REG00 0x0000 +#define ixCLIPPER_DEBUG_REG01 0x0001 +#define ixCLIPPER_DEBUG_REG02 0x0002 +#define ixCLIPPER_DEBUG_REG03 0x0003 +#define ixCLIPPER_DEBUG_REG04 0x0004 +#define ixCLIPPER_DEBUG_REG05 0x0005 +#define ixCLIPPER_DEBUG_REG09 0x0009 +#define ixCLIPPER_DEBUG_REG10 0x000A +#define ixCLIPPER_DEBUG_REG11 0x000B +#define ixCLIPPER_DEBUG_REG12 0x000C +#define ixCLIPPER_DEBUG_REG13 0x000D +#define ixSXIFCCG_DEBUG_REG0 0x0011 +#define ixSXIFCCG_DEBUG_REG1 0x0012 +#define ixSXIFCCG_DEBUG_REG2 0x0013 +#define ixSXIFCCG_DEBUG_REG3 0x0014 +#define ixSETUP_DEBUG_REG0 0x0015 +#define ixSETUP_DEBUG_REG1 0x0016 +#define ixSETUP_DEBUG_REG2 0x0017 +#define ixSETUP_DEBUG_REG3 0x0018 +#define ixSETUP_DEBUG_REG4 0x0019 +#define ixSETUP_DEBUG_REG5 0x001A + +// [SCDEBUGIND] : Indirect Registers + +#define ixSC_DEBUG_0 0x0000 +#define ixSC_DEBUG_1 0x0001 +#define ixSC_DEBUG_2 0x0002 +#define ixSC_DEBUG_3 0x0003 +#define ixSC_DEBUG_4 0x0004 +#define ixSC_DEBUG_5 0x0005 +#define ixSC_DEBUG_6 0x0006 +#define ixSC_DEBUG_7 0x0007 +#define ixSC_DEBUG_8 0x0008 +#define ixSC_DEBUG_9 0x0009 +#define ixSC_DEBUG_10 0x000A +#define ixSC_DEBUG_11 0x000B +#define ixSC_DEBUG_12 0x000C + +// [VGTDEBUGIND] : Indirect Registers + +#define ixVGT_DEBUG_REG0 0x0000 +#define ixVGT_DEBUG_REG1 0x0001 +#define ixVGT_DEBUG_REG3 0x0003 +#define ixVGT_DEBUG_REG6 0x0006 +#define ixVGT_DEBUG_REG7 0x0007 +#define ixVGT_DEBUG_REG8 0x0008 +#define ixVGT_DEBUG_REG9 0x0009 +#define ixVGT_DEBUG_REG10 0x000A +#define ixVGT_DEBUG_REG12 0x000C +#define ixVGT_DEBUG_REG13 0x000D +#define ixVGT_DEBUG_REG14 0x000E +#define ixVGT_DEBUG_REG15 0x000F +#define ixVGT_DEBUG_REG16 0x0010 +#define ixVGT_DEBUG_REG17 0x0011 +#define ixVGT_DEBUG_REG18 0x0012 +#define ixVGT_DEBUG_REG20 0x0014 +#define ixVGT_DEBUG_REG21 0x0015 + +// [MHDEBUGIND] : Indirect Registers + +#define ixMH_DEBUG_REG00 0x0000 +#define ixMH_DEBUG_REG01 0x0001 +#define ixMH_DEBUG_REG02 0x0002 +#define ixMH_DEBUG_REG03 0x0003 +#define ixMH_DEBUG_REG04 0x0004 +#define ixMH_DEBUG_REG05 0x0005 +#define ixMH_DEBUG_REG06 0x0006 +#define ixMH_DEBUG_REG07 0x0007 +#define ixMH_DEBUG_REG08 0x0008 +#define ixMH_DEBUG_REG09 0x0009 +#define ixMH_DEBUG_REG10 0x000A +#define ixMH_DEBUG_REG11 0x000B +#define ixMH_DEBUG_REG12 0x000C +#define ixMH_DEBUG_REG13 0x000D +#define ixMH_DEBUG_REG14 0x000E +#define ixMH_DEBUG_REG15 0x000F +#define ixMH_DEBUG_REG16 0x0010 +#define ixMH_DEBUG_REG17 0x0011 +#define ixMH_DEBUG_REG18 0x0012 +#define ixMH_DEBUG_REG19 0x0013 +#define ixMH_DEBUG_REG20 0x0014 +#define ixMH_DEBUG_REG21 0x0015 +#define ixMH_DEBUG_REG22 0x0016 +#define ixMH_DEBUG_REG23 0x0017 +#define ixMH_DEBUG_REG24 0x0018 +#define ixMH_DEBUG_REG25 0x0019 +#define ixMH_DEBUG_REG26 0x001A +#define ixMH_DEBUG_REG27 0x001B +#define ixMH_DEBUG_REG28 0x001C +#define ixMH_DEBUG_REG29 0x001D +#define ixMH_DEBUG_REG30 0x001E +#define ixMH_DEBUG_REG31 0x001F +#define ixMH_DEBUG_REG32 0x0020 +#define ixMH_DEBUG_REG33 0x0021 +#define ixMH_DEBUG_REG34 0x0022 +#define ixMH_DEBUG_REG35 0x0023 +#define ixMH_DEBUG_REG36 0x0024 +#define ixMH_DEBUG_REG37 0x0025 +#define ixMH_DEBUG_REG38 0x0026 +#define ixMH_DEBUG_REG39 0x0027 +#define ixMH_DEBUG_REG40 0x0028 +#define ixMH_DEBUG_REG41 0x0029 +#define ixMH_DEBUG_REG42 0x002A +#define ixMH_DEBUG_REG43 0x002B +#define ixMH_DEBUG_REG44 0x002C +#define ixMH_DEBUG_REG45 0x002D +#define ixMH_DEBUG_REG46 0x002E +#define ixMH_DEBUG_REG47 0x002F +#define ixMH_DEBUG_REG48 0x0030 +#define ixMH_DEBUG_REG49 0x0031 +#define ixMH_DEBUG_REG50 0x0032 +#define ixMH_DEBUG_REG51 0x0033 +#define ixMH_DEBUG_REG52 0x0034 +#define ixMH_DEBUG_REG53 0x0035 +#define ixMH_DEBUG_REG54 0x0036 +#define ixMH_DEBUG_REG55 0x0037 +#define ixMH_DEBUG_REG56 0x0038 +#define ixMH_DEBUG_REG57 0x0039 +#define ixMH_DEBUG_REG58 0x003A +#define ixMH_DEBUG_REG59 0x003B +#define ixMH_DEBUG_REG60 0x003C +#define ixMH_DEBUG_REG61 0x003D +#define ixMH_DEBUG_REG62 0x003E +#define ixMH_DEBUG_REG63 0x003F + + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // _yamatob_h + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h new file mode 100644 index 000000000000..ab11205f1092 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h @@ -0,0 +1,1867 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_ENUM_HEADER) +#define _yamato_ENUM_HEADER + + + +#ifndef _DRIVER_BUILD +#ifndef GL_ZERO +#define GL__ZERO BLEND_ZERO +#define GL__ONE BLEND_ONE +#define GL__SRC_COLOR BLEND_SRC_COLOR +#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR +#define GL__DST_COLOR BLEND_DST_COLOR +#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR +#define GL__SRC_ALPHA BLEND_SRC_ALPHA +#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA +#define GL__DST_ALPHA BLEND_DST_ALPHA +#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA +#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE +#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR +#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR +#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA +#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA +#endif +#endif + +/******************************************************* + * PA Enums + *******************************************************/ +#ifndef ENUMS_SU_PERFCNT_SELECT_H +#define ENUMS_SU_PERFCNT_SELECT_H +typedef enum SU_PERFCNT_SELECT { + PERF_PAPC_PASX_REQ = 0, + UNUSED1 = 1, + PERF_PAPC_PASX_FIRST_VECTOR = 2, + PERF_PAPC_PASX_SECOND_VECTOR = 3, + PERF_PAPC_PASX_FIRST_DEAD = 4, + PERF_PAPC_PASX_SECOND_DEAD = 5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, + PERF_PAPC_PA_INPUT_PRIM = 8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, + PERF_PAPC_CLPR_CULL_PRIM = 13, + UNUSED2 = 14, + PERF_PAPC_CLPR_VV_CULL_PRIM = 15, + UNUSED3 = 16, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, + UNUSED4 = 20, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, + UNUSED5 = 22, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, + PERF_PAPC_CLSM_NULL_PRIM = 36, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, + PERF_PAPC_CLSM_CLIP_PRIM = 38, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, + PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, + PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, + PERF_PAPC_SU_INPUT_PRIM = 47, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, + PERF_PAPC_SU_INPUT_NULL_PRIM = 49, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, + PERF_PAPC_SU_OUTPUT_PRIM = 57, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, + PERF_PAPC_PASX_REQ_IDLE = 69, + PERF_PAPC_PASX_REQ_BUSY = 70, + PERF_PAPC_PASX_REQ_STALLED = 71, + PERF_PAPC_PASX_REC_IDLE = 72, + PERF_PAPC_PASX_REC_BUSY = 73, + PERF_PAPC_PASX_REC_STARVED_SX = 74, + PERF_PAPC_PASX_REC_STALLED = 75, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, + PERF_PAPC_CCGSM_IDLE = 78, + PERF_PAPC_CCGSM_BUSY = 79, + PERF_PAPC_CCGSM_STALLED = 80, + PERF_PAPC_CLPRIM_IDLE = 81, + PERF_PAPC_CLPRIM_BUSY = 82, + PERF_PAPC_CLPRIM_STALLED = 83, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, + PERF_PAPC_CLIPSM_IDLE = 85, + PERF_PAPC_CLIPSM_BUSY = 86, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, + PERF_PAPC_CLIPGA_IDLE = 92, + PERF_PAPC_CLIPGA_BUSY = 93, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, + PERF_PAPC_CLIPGA_STALLED = 95, + PERF_PAPC_CLIP_IDLE = 96, + PERF_PAPC_CLIP_BUSY = 97, + PERF_PAPC_SU_IDLE = 98, + PERF_PAPC_SU_BUSY = 99, + PERF_PAPC_SU_STARVED_CLIP = 100, + PERF_PAPC_SU_STALLED_SC = 101, +} SU_PERFCNT_SELECT; +#endif /*ENUMS_SU_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SC_PERFCNT_SELECT_H +#define ENUMS_SC_PERFCNT_SELECT_H +typedef enum SC_PERFCNT_SELECT { + SC_SR_WINDOW_VALID = 0, + SC_CW_WINDOW_VALID = 1, + SC_QM_WINDOW_VALID = 2, + SC_FW_WINDOW_VALID = 3, + SC_EZ_WINDOW_VALID = 4, + SC_IT_WINDOW_VALID = 5, + SC_STARVED_BY_PA = 6, + SC_STALLED_BY_RB_TILE = 7, + SC_STALLED_BY_RB_SAMP = 8, + SC_STARVED_BY_RB_EZ = 9, + SC_STALLED_BY_SAMPLE_FF = 10, + SC_STALLED_BY_SQ = 11, + SC_STALLED_BY_SP = 12, + SC_TOTAL_NO_PRIMS = 13, + SC_NON_EMPTY_PRIMS = 14, + SC_NO_TILES_PASSING_QM = 15, + SC_NO_PIXELS_PRE_EZ = 16, + SC_NO_PIXELS_POST_EZ = 17, +} SC_PERFCNT_SELECT; +#endif /*ENUMS_SC_PERFCNT_SELECT_H*/ + +/******************************************************* + * VGT Enums + *******************************************************/ +#ifndef ENUMS_VGT_DI_PRIM_TYPE_H +#define ENUMS_VGT_DI_PRIM_TYPE_H +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0, + DI_PT_POINTLIST = 1, + DI_PT_LINELIST = 2, + DI_PT_LINESTRIP = 3, + DI_PT_TRILIST = 4, + DI_PT_TRIFAN = 5, + DI_PT_TRISTRIP = 6, + DI_PT_UNUSED_1 = 7, + DI_PT_RECTLIST = 8, + DI_PT_UNUSED_2 = 9, + DI_PT_UNUSED_3 = 10, + DI_PT_UNUSED_4 = 11, + DI_PT_UNUSED_5 = 12, + DI_PT_QUADLIST = 13, + DI_PT_QUADSTRIP = 14, + DI_PT_POLYGON = 15, + DI_PT_2D_COPY_RECT_LIST_V0 = 16, + DI_PT_2D_COPY_RECT_LIST_V1 = 17, + DI_PT_2D_COPY_RECT_LIST_V2 = 18, + DI_PT_2D_COPY_RECT_LIST_V3 = 19, + DI_PT_2D_FILL_RECT_LIST = 20, + DI_PT_2D_LINE_STRIP = 21, + DI_PT_2D_TRI_STRIP = 22, +} VGT_DI_PRIM_TYPE; +#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/ + +#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H +#define ENUMS_VGT_DI_SOURCE_SELECT_H +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0, + DI_SRC_SEL_IMMEDIATE = 1, + DI_SRC_SEL_AUTO_INDEX = 2, + DI_SRC_SEL_RESERVED = 3 +} VGT_DI_SOURCE_SELECT; +#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_INDEX_SIZE_H +#define ENUMS_VGT_DI_INDEX_SIZE_H +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0, + DI_INDEX_SIZE_32_BIT = 1 +} VGT_DI_INDEX_SIZE; +#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/ + +#ifndef ENUMS_VGT_DI_SMALL_INDEX_H +#define ENUMS_VGT_DI_SMALL_INDEX_H +typedef enum VGT_DI_SMALL_INDEX { + DI_USE_INDEX_SIZE = 0, + DI_INDEX_SIZE_8_BIT = 1 +} VGT_DI_SMALL_INDEX; +#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/ + +#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE { + DISABLE_PRE_FETCH_CULL_ENABLE = 0, + PRE_FETCH_CULL_ENABLE = 1 +} VGT_DI_PRE_FETCH_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H +#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H +typedef enum VGT_DI_GRP_CULL_ENABLE { + DISABLE_GRP_CULL_ENABLE = 0, + GRP_CULL_ENABLE = 1 +} VGT_DI_GRP_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_EVENT_TYPE_H +#define ENUMS_VGT_EVENT_TYPE_H +typedef enum VGT_EVENT_TYPE { + VS_DEALLOC = 0, + PS_DEALLOC = 1, + VS_DONE_TS = 2, + PS_DONE_TS = 3, + CACHE_FLUSH_TS = 4, + CONTEXT_DONE = 5, + CACHE_FLUSH = 6, + VIZQUERY_START = 7, + VIZQUERY_END = 8, + SC_WAIT_WC = 9, + RST_PIX_CNT = 13, + RST_VTX_CNT = 14, + TILE_FLUSH = 15, + CACHE_FLUSH_AND_INV_TS_EVENT = 20, + ZPASS_DONE = 21, + CACHE_FLUSH_AND_INV_EVENT = 22, + PERFCOUNTER_START = 23, + PERFCOUNTER_STOP = 24, + VS_FETCH_DONE = 27, +} VGT_EVENT_TYPE; +#endif /*ENUMS_VGT_EVENT_TYPE_H*/ + +#ifndef ENUMS_VGT_DMA_SWAP_MODE_H +#define ENUMS_VGT_DMA_SWAP_MODE_H +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0, + VGT_DMA_SWAP_16_BIT = 1, + VGT_DMA_SWAP_32_BIT = 2, + VGT_DMA_SWAP_WORD = 3 +} VGT_DMA_SWAP_MODE; +#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/ + +#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H +#define ENUMS_VGT_PERFCOUNT_SELECT_H +typedef enum VGT_PERFCOUNT_SELECT { + VGT_SQ_EVENT_WINDOW_ACTIVE = 0, + VGT_SQ_SEND = 1, + VGT_SQ_STALLED = 2, + VGT_SQ_STARVED_BUSY = 3, + VGT_SQ_STARVED_IDLE = 4, + VGT_SQ_STATIC = 5, + VGT_PA_EVENT_WINDOW_ACTIVE = 6, + VGT_PA_CLIP_V_SEND = 7, + VGT_PA_CLIP_V_STALLED = 8, + VGT_PA_CLIP_V_STARVED_BUSY = 9, + VGT_PA_CLIP_V_STARVED_IDLE = 10, + VGT_PA_CLIP_V_STATIC = 11, + VGT_PA_CLIP_P_SEND = 12, + VGT_PA_CLIP_P_STALLED = 13, + VGT_PA_CLIP_P_STARVED_BUSY = 14, + VGT_PA_CLIP_P_STARVED_IDLE = 15, + VGT_PA_CLIP_P_STATIC = 16, + VGT_PA_CLIP_S_SEND = 17, + VGT_PA_CLIP_S_STALLED = 18, + VGT_PA_CLIP_S_STARVED_BUSY = 19, + VGT_PA_CLIP_S_STARVED_IDLE = 20, + VGT_PA_CLIP_S_STATIC = 21, + RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, + RBIU_IMMED_DATA_FIFO_STARVED = 23, + RBIU_IMMED_DATA_FIFO_STALLED = 24, + RBIU_DMA_REQUEST_FIFO_STARVED = 25, + RBIU_DMA_REQUEST_FIFO_STALLED = 26, + RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, + RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, + BIN_PRIM_NEAR_CULL = 29, + BIN_PRIM_ZERO_CULL = 30, + BIN_PRIM_FAR_CULL = 31, + BIN_PRIM_BIN_CULL = 32, + SPARE33 = 33, + SPARE34 = 34, + SPARE35 = 35, + SPARE36 = 36, + SPARE37 = 37, + SPARE38 = 38, + SPARE39 = 39, + TE_SU_IN_VALID = 40, + TE_SU_IN_READ = 41, + TE_SU_IN_PRIM = 42, + TE_SU_IN_EOP = 43, + TE_SU_IN_NULL_PRIM = 44, + TE_WK_IN_VALID = 45, + TE_WK_IN_READ = 46, + TE_OUT_PRIM_VALID = 47, + TE_OUT_PRIM_READ = 48, +} VGT_PERFCOUNT_SELECT; +#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TP Enums + *******************************************************/ +#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H +#define ENUMS_TCR_PERFCOUNT_SELECT_H +typedef enum TCR_PERFCOUNT_SELECT { + DGMMPD_IPMUX0_STALL = 0, + reserved_46 = 1, + reserved_47 = 2, + reserved_48 = 3, + DGMMPD_IPMUX_ALL_STALL = 4, + OPMUX0_L2_WRITES = 5, + reserved_49 = 6, + reserved_50 = 7, + reserved_51 = 8, +} TCR_PERFCOUNT_SELECT; +#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TP_PERFCOUNT_SELECT_H +#define ENUMS_TP_PERFCOUNT_SELECT_H +typedef enum TP_PERFCOUNT_SELECT { + POINT_QUADS = 0, + BILIN_QUADS = 1, + ANISO_QUADS = 2, + MIP_QUADS = 3, + VOL_QUADS = 4, + MIP_VOL_QUADS = 5, + MIP_ANISO_QUADS = 6, + VOL_ANISO_QUADS = 7, + ANISO_2_1_QUADS = 8, + ANISO_4_1_QUADS = 9, + ANISO_6_1_QUADS = 10, + ANISO_8_1_QUADS = 11, + ANISO_10_1_QUADS = 12, + ANISO_12_1_QUADS = 13, + ANISO_14_1_QUADS = 14, + ANISO_16_1_QUADS = 15, + MIP_VOL_ANISO_QUADS = 16, + ALIGN_2_QUADS = 17, + ALIGN_4_QUADS = 18, + PIX_0_QUAD = 19, + PIX_1_QUAD = 20, + PIX_2_QUAD = 21, + PIX_3_QUAD = 22, + PIX_4_QUAD = 23, + TP_MIPMAP_LOD0 = 24, + TP_MIPMAP_LOD1 = 25, + TP_MIPMAP_LOD2 = 26, + TP_MIPMAP_LOD3 = 27, + TP_MIPMAP_LOD4 = 28, + TP_MIPMAP_LOD5 = 29, + TP_MIPMAP_LOD6 = 30, + TP_MIPMAP_LOD7 = 31, + TP_MIPMAP_LOD8 = 32, + TP_MIPMAP_LOD9 = 33, + TP_MIPMAP_LOD10 = 34, + TP_MIPMAP_LOD11 = 35, + TP_MIPMAP_LOD12 = 36, + TP_MIPMAP_LOD13 = 37, + TP_MIPMAP_LOD14 = 38, +} TP_PERFCOUNT_SELECT; +#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H +#define ENUMS_TCM_PERFCOUNT_SELECT_H +typedef enum TCM_PERFCOUNT_SELECT { + QUAD0_RD_LAT_FIFO_EMPTY = 0, + reserved_01 = 1, + reserved_02 = 2, + QUAD0_RD_LAT_FIFO_4TH_FULL = 3, + QUAD0_RD_LAT_FIFO_HALF_FULL = 4, + QUAD0_RD_LAT_FIFO_FULL = 5, + QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, + reserved_07 = 7, + reserved_08 = 8, + reserved_09 = 9, + reserved_10 = 10, + reserved_11 = 11, + reserved_12 = 12, + reserved_13 = 13, + reserved_14 = 14, + reserved_15 = 15, + reserved_16 = 16, + reserved_17 = 17, + reserved_18 = 18, + reserved_19 = 19, + reserved_20 = 20, + reserved_21 = 21, + reserved_22 = 22, + reserved_23 = 23, + reserved_24 = 24, + reserved_25 = 25, + reserved_26 = 26, + reserved_27 = 27, + READ_STARVED_QUAD0 = 28, + reserved_29 = 29, + reserved_30 = 30, + reserved_31 = 31, + READ_STARVED = 32, + READ_STALLED_QUAD0 = 33, + reserved_34 = 34, + reserved_35 = 35, + reserved_36 = 36, + READ_STALLED = 37, + VALID_READ_QUAD0 = 38, + reserved_39 = 39, + reserved_40 = 40, + reserved_41 = 41, + TC_TP_STARVED_QUAD0 = 42, + reserved_43 = 43, + reserved_44 = 44, + reserved_45 = 45, + TC_TP_STARVED = 46, +} TCM_PERFCOUNT_SELECT; +#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H +#define ENUMS_TCF_PERFCOUNT_SELECT_H +typedef enum TCF_PERFCOUNT_SELECT { + VALID_CYCLES = 0, + SINGLE_PHASES = 1, + ANISO_PHASES = 2, + MIP_PHASES = 3, + VOL_PHASES = 4, + MIP_VOL_PHASES = 5, + MIP_ANISO_PHASES = 6, + VOL_ANISO_PHASES = 7, + ANISO_2_1_PHASES = 8, + ANISO_4_1_PHASES = 9, + ANISO_6_1_PHASES = 10, + ANISO_8_1_PHASES = 11, + ANISO_10_1_PHASES = 12, + ANISO_12_1_PHASES = 13, + ANISO_14_1_PHASES = 14, + ANISO_16_1_PHASES = 15, + MIP_VOL_ANISO_PHASES = 16, + ALIGN_2_PHASES = 17, + ALIGN_4_PHASES = 18, + TPC_BUSY = 19, + TPC_STALLED = 20, + TPC_STARVED = 21, + TPC_WORKING = 22, + TPC_WALKER_BUSY = 23, + TPC_WALKER_STALLED = 24, + TPC_WALKER_WORKING = 25, + TPC_ALIGNER_BUSY = 26, + TPC_ALIGNER_STALLED = 27, + TPC_ALIGNER_STALLED_BY_BLEND = 28, + TPC_ALIGNER_STALLED_BY_CACHE = 29, + TPC_ALIGNER_WORKING = 30, + TPC_BLEND_BUSY = 31, + TPC_BLEND_SYNC = 32, + TPC_BLEND_STARVED = 33, + TPC_BLEND_WORKING = 34, + OPCODE_0x00 = 35, + OPCODE_0x01 = 36, + OPCODE_0x04 = 37, + OPCODE_0x10 = 38, + OPCODE_0x11 = 39, + OPCODE_0x12 = 40, + OPCODE_0x13 = 41, + OPCODE_0x18 = 42, + OPCODE_0x19 = 43, + OPCODE_0x1A = 44, + OPCODE_OTHER = 45, + IN_FIFO_0_EMPTY = 56, + IN_FIFO_0_LT_HALF_FULL = 57, + IN_FIFO_0_HALF_FULL = 58, + IN_FIFO_0_FULL = 59, + IN_FIFO_TPC_EMPTY = 72, + IN_FIFO_TPC_LT_HALF_FULL = 73, + IN_FIFO_TPC_HALF_FULL = 74, + IN_FIFO_TPC_FULL = 75, + TPC_TC_XFC = 76, + TPC_TC_STATE = 77, + TC_STALL = 78, + QUAD0_TAPS = 79, + QUADS = 83, + TCA_SYNC_STALL = 84, + TAG_STALL = 85, + TCB_SYNC_STALL = 88, + TCA_VALID = 89, + PROBES_VALID = 90, + MISS_STALL = 91, + FETCH_FIFO_STALL = 92, + TCO_STALL = 93, + ANY_STALL = 94, + TAG_MISSES = 95, + TAG_HITS = 96, + SUB_TAG_MISSES = 97, + SET0_INVALIDATES = 98, + SET1_INVALIDATES = 99, + SET2_INVALIDATES = 100, + SET3_INVALIDATES = 101, + SET0_TAG_MISSES = 102, + SET1_TAG_MISSES = 103, + SET2_TAG_MISSES = 104, + SET3_TAG_MISSES = 105, + SET0_TAG_HITS = 106, + SET1_TAG_HITS = 107, + SET2_TAG_HITS = 108, + SET3_TAG_HITS = 109, + SET0_SUB_TAG_MISSES = 110, + SET1_SUB_TAG_MISSES = 111, + SET2_SUB_TAG_MISSES = 112, + SET3_SUB_TAG_MISSES = 113, + SET0_EVICT1 = 114, + SET0_EVICT2 = 115, + SET0_EVICT3 = 116, + SET0_EVICT4 = 117, + SET0_EVICT5 = 118, + SET0_EVICT6 = 119, + SET0_EVICT7 = 120, + SET0_EVICT8 = 121, + SET1_EVICT1 = 130, + SET1_EVICT2 = 131, + SET1_EVICT3 = 132, + SET1_EVICT4 = 133, + SET1_EVICT5 = 134, + SET1_EVICT6 = 135, + SET1_EVICT7 = 136, + SET1_EVICT8 = 137, + SET2_EVICT1 = 146, + SET2_EVICT2 = 147, + SET2_EVICT3 = 148, + SET2_EVICT4 = 149, + SET2_EVICT5 = 150, + SET2_EVICT6 = 151, + SET2_EVICT7 = 152, + SET2_EVICT8 = 153, + SET3_EVICT1 = 162, + SET3_EVICT2 = 163, + SET3_EVICT3 = 164, + SET3_EVICT4 = 165, + SET3_EVICT5 = 166, + SET3_EVICT6 = 167, + SET3_EVICT7 = 168, + SET3_EVICT8 = 169, + FF_EMPTY = 178, + FF_LT_HALF_FULL = 179, + FF_HALF_FULL = 180, + FF_FULL = 181, + FF_XFC = 182, + FF_STALLED = 183, + FG_MASKS = 184, + FG_LEFT_MASKS = 185, + FG_LEFT_MASK_STALLED = 186, + FG_LEFT_NOT_DONE_STALL = 187, + FG_LEFT_FG_STALL = 188, + FG_LEFT_SECTORS = 189, + FG0_REQUESTS = 195, + FG0_STALLED = 196, + MEM_REQ512 = 199, + MEM_REQ_SENT = 200, + MEM_LOCAL_READ_REQ = 202, + TC0_MH_STALLED = 203, +} TCF_PERFCOUNT_SELECT; +#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +#ifndef ENUMS_SQ_PERFCNT_SELECT_H +#define ENUMS_SQ_PERFCNT_SELECT_H +typedef enum SQ_PERFCNT_SELECT { + SQ_PIXEL_VECTORS_SUB = 0, + SQ_VERTEX_VECTORS_SUB = 1, + SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, + SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, + SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, + SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, + SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, + SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, + SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, + SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, + SQ_EXPORT_CYCLES = 10, + SQ_ALU_CST_WRITTEN = 11, + SQ_TEX_CST_WRITTEN = 12, + SQ_ALU_CST_STALL = 13, + SQ_ALU_TEX_STALL = 14, + SQ_INST_WRITTEN = 15, + SQ_BOOLEAN_WRITTEN = 16, + SQ_LOOPS_WRITTEN = 17, + SQ_PIXEL_SWAP_IN = 18, + SQ_PIXEL_SWAP_OUT = 19, + SQ_VERTEX_SWAP_IN = 20, + SQ_VERTEX_SWAP_OUT = 21, + SQ_ALU_VTX_INST_ISSUED = 22, + SQ_TEX_VTX_INST_ISSUED = 23, + SQ_VC_VTX_INST_ISSUED = 24, + SQ_CF_VTX_INST_ISSUED = 25, + SQ_ALU_PIX_INST_ISSUED = 26, + SQ_TEX_PIX_INST_ISSUED = 27, + SQ_VC_PIX_INST_ISSUED = 28, + SQ_CF_PIX_INST_ISSUED = 29, + SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, + SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, + SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, + SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, + SQ_ALU_NOPS = 34, + SQ_PRED_SKIP = 35, + SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, + SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, + SQ_SYNC_TEX_STALL_VTX = 38, + SQ_SYNC_VC_STALL_VTX = 39, + SQ_CONSTANTS_USED_SIMD0 = 40, + SQ_CONSTANTS_SENT_SP_SIMD0 = 41, + SQ_GPR_STALL_VTX = 42, + SQ_GPR_STALL_PIX = 43, + SQ_VTX_RS_STALL = 44, + SQ_PIX_RS_STALL = 45, + SQ_SX_PC_FULL = 46, + SQ_SX_EXP_BUFF_FULL = 47, + SQ_SX_POS_BUFF_FULL = 48, + SQ_INTERP_QUADS = 49, + SQ_INTERP_ACTIVE = 50, + SQ_IN_PIXEL_STALL = 51, + SQ_IN_VTX_STALL = 52, + SQ_VTX_CNT = 53, + SQ_VTX_VECTOR2 = 54, + SQ_VTX_VECTOR3 = 55, + SQ_VTX_VECTOR4 = 56, + SQ_PIXEL_VECTOR1 = 57, + SQ_PIXEL_VECTOR23 = 58, + SQ_PIXEL_VECTOR4 = 59, + SQ_CONSTANTS_USED_SIMD1 = 60, + SQ_CONSTANTS_SENT_SP_SIMD1 = 61, + SQ_SX_MEM_EXP_FULL = 62, + SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, + SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, + SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, + SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, + SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, + SQ_ALU1_ACTIVE_VTX_SIMD3 = 68, + SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, + SQ_ALU1_ACTIVE_PIX_SIMD3 = 70, + SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, + SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, + SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, + SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, + SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, + SQ_SYNC_ALU_STALL_SIMD3_VTX = 76, + SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, + SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, + SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, + SQ_SYNC_ALU_STALL_SIMD3_PIX = 80, + SQ_SYNC_TEX_STALL_PIX = 81, + SQ_SYNC_VC_STALL_PIX = 82, + SQ_CONSTANTS_USED_SIMD2 = 83, + SQ_CONSTANTS_SENT_SP_SIMD2 = 84, + SQ_CONSTANTS_USED_SIMD3 = 85, + SQ_CONSTANTS_SENT_SP_SIMD3 = 86, + SQ_ALU0_FIFO_FULL_SIMD0 = 87, + SQ_ALU1_FIFO_FULL_SIMD0 = 88, + SQ_ALU0_FIFO_FULL_SIMD1 = 89, + SQ_ALU1_FIFO_FULL_SIMD1 = 90, + SQ_ALU0_FIFO_FULL_SIMD2 = 91, + SQ_ALU1_FIFO_FULL_SIMD2 = 92, + SQ_ALU0_FIFO_FULL_SIMD3 = 93, + SQ_ALU1_FIFO_FULL_SIMD3 = 94, + VC_PERF_STATIC = 95, + VC_PERF_STALLED = 96, + VC_PERF_STARVED = 97, + VC_PERF_SEND = 98, + VC_PERF_ACTUAL_STARVED = 99, + PIXEL_THREAD_0_ACTIVE = 100, + VERTEX_THREAD_0_ACTIVE = 101, + PIXEL_THREAD_0_NUMBER = 102, + VERTEX_THREAD_0_NUMBER = 103, + VERTEX_EVENT_NUMBER = 104, + PIXEL_EVENT_NUMBER = 105, + PTRBUFF_EF_PUSH = 106, + PTRBUFF_EF_POP_EVENT = 107, + PTRBUFF_EF_POP_NEW_VTX = 108, + PTRBUFF_EF_POP_DEALLOC = 109, + PTRBUFF_EF_POP_PVECTOR = 110, + PTRBUFF_EF_POP_PVECTOR_X = 111, + PTRBUFF_EF_POP_PVECTOR_VNZ = 112, + PTRBUFF_PB_DEALLOC = 113, + PTRBUFF_PI_STATE_PPB_POP = 114, + PTRBUFF_PI_RTR = 115, + PTRBUFF_PI_READ_EN = 116, + PTRBUFF_PI_BUFF_SWAP = 117, + PTRBUFF_SQ_FREE_BUFF = 118, + PTRBUFF_SQ_DEC = 119, + PTRBUFF_SC_VALID_CNTL_EVENT = 120, + PTRBUFF_SC_VALID_IJ_XFER = 121, + PTRBUFF_SC_NEW_VECTOR_1_Q = 122, + PTRBUFF_QUAL_NEW_VECTOR = 123, + PTRBUFF_QUAL_EVENT = 124, + PTRBUFF_END_BUFFER = 125, + PTRBUFF_FILL_QUAD = 126, + VERTS_WRITTEN_SPI = 127, + TP_FETCH_INSTR_EXEC = 128, + TP_FETCH_INSTR_REQ = 129, + TP_DATA_RETURN = 130, + SPI_WRITE_CYCLES_SP = 131, + SPI_WRITES_SP = 132, + SP_ALU_INSTR_EXEC = 133, + SP_CONST_ADDR_TO_SQ = 134, + SP_PRED_KILLS_TO_SQ = 135, + SP_EXPORT_CYCLES_TO_SX = 136, + SP_EXPORTS_TO_SX = 137, + SQ_CYCLES_ELAPSED = 138, + SQ_TCFS_OPT_ALLOC_EXEC = 139, + SQ_TCFS_NO_OPT_ALLOC = 140, + SQ_ALU0_NO_OPT_ALLOC = 141, + SQ_ALU1_NO_OPT_ALLOC = 142, + SQ_TCFS_ARB_XFC_CNT = 143, + SQ_ALU0_ARB_XFC_CNT = 144, + SQ_ALU1_ARB_XFC_CNT = 145, + SQ_TCFS_CFS_UPDATE_CNT = 146, + SQ_ALU0_CFS_UPDATE_CNT = 147, + SQ_ALU1_CFS_UPDATE_CNT = 148, + SQ_VTX_PUSH_THREAD_CNT = 149, + SQ_VTX_POP_THREAD_CNT = 150, + SQ_PIX_PUSH_THREAD_CNT = 151, + SQ_PIX_POP_THREAD_CNT = 152, + SQ_PIX_TOTAL = 153, + SQ_PIX_KILLED = 154, +} SQ_PERFCNT_SELECT; +#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SX_PERFCNT_SELECT_H +#define ENUMS_SX_PERFCNT_SELECT_H +typedef enum SX_PERFCNT_SELECT { + SX_EXPORT_VECTORS = 0, + SX_DUMMY_QUADS = 1, + SX_ALPHA_FAIL = 2, + SX_RB_QUAD_BUSY = 3, + SX_RB_COLOR_BUSY = 4, + SX_RB_QUAD_STALL = 5, + SX_RB_COLOR_STALL = 6, +} SX_PERFCNT_SELECT; +#endif /*ENUMS_SX_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_Abs_modifier_H +#define ENUMS_Abs_modifier_H +typedef enum Abs_modifier { + NO_ABS_MOD = 0, + ABS_MOD = 1 +} Abs_modifier; +#endif /*ENUMS_Abs_modifier_H*/ + +#ifndef ENUMS_Exporting_H +#define ENUMS_Exporting_H +typedef enum Exporting { + NOT_EXPORTING = 0, + EXPORTING = 1 +} Exporting; +#endif /*ENUMS_Exporting_H*/ + +#ifndef ENUMS_ScalarOpcode_H +#define ENUMS_ScalarOpcode_H +typedef enum ScalarOpcode { + ADDs = 0, + ADD_PREVs = 1, + MULs = 2, + MUL_PREVs = 3, + MUL_PREV2s = 4, + MAXs = 5, + MINs = 6, + SETEs = 7, + SETGTs = 8, + SETGTEs = 9, + SETNEs = 10, + FRACs = 11, + TRUNCs = 12, + FLOORs = 13, + EXP_IEEE = 14, + LOG_CLAMP = 15, + LOG_IEEE = 16, + RECIP_CLAMP = 17, + RECIP_FF = 18, + RECIP_IEEE = 19, + RECIPSQ_CLAMP = 20, + RECIPSQ_FF = 21, + RECIPSQ_IEEE = 22, + MOVAs = 23, + MOVA_FLOORs = 24, + SUBs = 25, + SUB_PREVs = 26, + PRED_SETEs = 27, + PRED_SETNEs = 28, + PRED_SETGTs = 29, + PRED_SETGTEs = 30, + PRED_SET_INVs = 31, + PRED_SET_POPs = 32, + PRED_SET_CLRs = 33, + PRED_SET_RESTOREs = 34, + KILLEs = 35, + KILLGTs = 36, + KILLGTEs = 37, + KILLNEs = 38, + KILLONEs = 39, + SQRT_IEEE = 40, + MUL_CONST_0 = 42, + MUL_CONST_1 = 43, + ADD_CONST_0 = 44, + ADD_CONST_1 = 45, + SUB_CONST_0 = 46, + SUB_CONST_1 = 47, + SIN = 48, + COS = 49, + RETAIN_PREV = 50, +} ScalarOpcode; +#endif /*ENUMS_ScalarOpcode_H*/ + +#ifndef ENUMS_SwizzleType_H +#define ENUMS_SwizzleType_H +typedef enum SwizzleType { + NO_SWIZZLE = 0, + SHIFT_RIGHT_1 = 1, + SHIFT_RIGHT_2 = 2, + SHIFT_RIGHT_3 = 3 +} SwizzleType; +#endif /*ENUMS_SwizzleType_H*/ + +#ifndef ENUMS_InputModifier_H +#define ENUMS_InputModifier_H +typedef enum InputModifier { + NIL = 0, + NEGATE = 1 +} InputModifier; +#endif /*ENUMS_InputModifier_H*/ + +#ifndef ENUMS_PredicateSelect_H +#define ENUMS_PredicateSelect_H +typedef enum PredicateSelect { + NO_PREDICATION = 0, + PREDICATE_QUAD = 1, + PREDICATED_2 = 2, + PREDICATED_3 = 3 +} PredicateSelect; +#endif /*ENUMS_PredicateSelect_H*/ + +#ifndef ENUMS_OperandSelect1_H +#define ENUMS_OperandSelect1_H +typedef enum OperandSelect1 { + ABSOLUTE_REG = 0, + RELATIVE_REG = 1 +} OperandSelect1; +#endif /*ENUMS_OperandSelect1_H*/ + +#ifndef ENUMS_VectorOpcode_H +#define ENUMS_VectorOpcode_H +typedef enum VectorOpcode { + ADDv = 0, + MULv = 1, + MAXv = 2, + MINv = 3, + SETEv = 4, + SETGTv = 5, + SETGTEv = 6, + SETNEv = 7, + FRACv = 8, + TRUNCv = 9, + FLOORv = 10, + MULADDv = 11, + CNDEv = 12, + CNDGTEv = 13, + CNDGTv = 14, + DOT4v = 15, + DOT3v = 16, + DOT2ADDv = 17, + CUBEv = 18, + MAX4v = 19, + PRED_SETE_PUSHv = 20, + PRED_SETNE_PUSHv = 21, + PRED_SETGT_PUSHv = 22, + PRED_SETGTE_PUSHv = 23, + KILLEv = 24, + KILLGTv = 25, + KILLGTEv = 26, + KILLNEv = 27, + DSTv = 28, + MOVAv = 29, +} VectorOpcode; +#endif /*ENUMS_VectorOpcode_H*/ + +#ifndef ENUMS_OperandSelect0_H +#define ENUMS_OperandSelect0_H +typedef enum OperandSelect0 { + CONSTANT = 0, + NON_CONSTANT = 1 +} OperandSelect0; +#endif /*ENUMS_OperandSelect0_H*/ + +#ifndef ENUMS_Ressource_type_H +#define ENUMS_Ressource_type_H +typedef enum Ressource_type { + ALU = 0, + TEXTURE = 1 +} Ressource_type; +#endif /*ENUMS_Ressource_type_H*/ + +#ifndef ENUMS_Instruction_serial_H +#define ENUMS_Instruction_serial_H +typedef enum Instruction_serial { + NOT_SERIAL = 0, + SERIAL = 1 +} Instruction_serial; +#endif /*ENUMS_Instruction_serial_H*/ + +#ifndef ENUMS_VC_type_H +#define ENUMS_VC_type_H +typedef enum VC_type { + ALU_TP_REQUEST = 0, + VC_REQUEST = 1 +} VC_type; +#endif /*ENUMS_VC_type_H*/ + +#ifndef ENUMS_Addressing_H +#define ENUMS_Addressing_H +typedef enum Addressing { + RELATIVE_ADDR = 0, + ABSOLUTE_ADDR = 1 +} Addressing; +#endif /*ENUMS_Addressing_H*/ + +#ifndef ENUMS_CFOpcode_H +#define ENUMS_CFOpcode_H +typedef enum CFOpcode { + NOP = 0, + EXECUTE = 1, + EXECUTE_END = 2, + COND_EXECUTE = 3, + COND_EXECUTE_END = 4, + COND_PRED_EXECUTE = 5, + COND_PRED_EXECUTE_END = 6, + LOOP_START = 7, + LOOP_END = 8, + COND_CALL = 9, + RETURN = 10, + COND_JMP = 11, + ALLOCATE = 12, + COND_EXECUTE_PRED_CLEAN = 13, + COND_EXECUTE_PRED_CLEAN_END = 14, + MARK_VS_FETCH_DONE = 15 +} CFOpcode; +#endif /*ENUMS_CFOpcode_H*/ + +#ifndef ENUMS_Allocation_type_H +#define ENUMS_Allocation_type_H +typedef enum Allocation_type { + SQ_NO_ALLOC = 0, + SQ_POSITION = 1, + SQ_PARAMETER_PIXEL = 2, + SQ_MEMORY = 3 +} Allocation_type; +#endif /*ENUMS_Allocation_type_H*/ + +#ifndef ENUMS_TexInstOpcode_H +#define ENUMS_TexInstOpcode_H +typedef enum TexInstOpcode { + TEX_INST_FETCH = 1, + TEX_INST_RESERVED_1 = 2, + TEX_INST_RESERVED_2 = 3, + TEX_INST_RESERVED_3 = 4, + TEX_INST_GET_BORDER_COLOR_FRAC = 16, + TEX_INST_GET_COMP_TEX_LOD = 17, + TEX_INST_GET_GRADIENTS = 18, + TEX_INST_GET_WEIGHTS = 19, + TEX_INST_SET_TEX_LOD = 24, + TEX_INST_SET_GRADIENTS_H = 25, + TEX_INST_SET_GRADIENTS_V = 26, + TEX_INST_RESERVED_4 = 27, +} TexInstOpcode; +#endif /*ENUMS_TexInstOpcode_H*/ + +#ifndef ENUMS_Addressmode_H +#define ENUMS_Addressmode_H +typedef enum Addressmode { + LOGICAL = 0, + LOOP_RELATIVE = 1 +} Addressmode; +#endif /*ENUMS_Addressmode_H*/ + +#ifndef ENUMS_TexCoordDenorm_H +#define ENUMS_TexCoordDenorm_H +typedef enum TexCoordDenorm { + TEX_COORD_NORMALIZED = 0, + TEX_COORD_UNNORMALIZED = 1 +} TexCoordDenorm; +#endif /*ENUMS_TexCoordDenorm_H*/ + +#ifndef ENUMS_SrcSel_H +#define ENUMS_SrcSel_H +typedef enum SrcSel { + SRC_SEL_X = 0, + SRC_SEL_Y = 1, + SRC_SEL_Z = 2, + SRC_SEL_W = 3 +} SrcSel; +#endif /*ENUMS_SrcSel_H*/ + +#ifndef ENUMS_DstSel_H +#define ENUMS_DstSel_H +typedef enum DstSel { + DST_SEL_X = 0, + DST_SEL_Y = 1, + DST_SEL_Z = 2, + DST_SEL_W = 3, + DST_SEL_0 = 4, + DST_SEL_1 = 5, + DST_SEL_RSVD = 6, + DST_SEL_MASK = 7 +} DstSel; +#endif /*ENUMS_DstSel_H*/ + +#ifndef ENUMS_MagFilter_H +#define ENUMS_MagFilter_H +typedef enum MagFilter { + MAG_FILTER_POINT = 0, + MAG_FILTER_LINEAR = 1, + MAG_FILTER_RESERVED_0 = 2, + MAG_FILTER_USE_FETCH_CONST = 3 +} MagFilter; +#endif /*ENUMS_MagFilter_H*/ + +#ifndef ENUMS_MinFilter_H +#define ENUMS_MinFilter_H +typedef enum MinFilter { + MIN_FILTER_POINT = 0, + MIN_FILTER_LINEAR = 1, + MIN_FILTER_RESERVED_0 = 2, + MIN_FILTER_USE_FETCH_CONST = 3 +} MinFilter; +#endif /*ENUMS_MinFilter_H*/ + +#ifndef ENUMS_MipFilter_H +#define ENUMS_MipFilter_H +typedef enum MipFilter { + MIP_FILTER_POINT = 0, + MIP_FILTER_LINEAR = 1, + MIP_FILTER_BASEMAP = 2, + MIP_FILTER_USE_FETCH_CONST = 3 +} MipFilter; +#endif /*ENUMS_MipFilter_H*/ + +#ifndef ENUMS_AnisoFilter_H +#define ENUMS_AnisoFilter_H +typedef enum AnisoFilter { + ANISO_FILTER_DISABLED = 0, + ANISO_FILTER_MAX_1_1 = 1, + ANISO_FILTER_MAX_2_1 = 2, + ANISO_FILTER_MAX_4_1 = 3, + ANISO_FILTER_MAX_8_1 = 4, + ANISO_FILTER_MAX_16_1 = 5, + ANISO_FILTER_USE_FETCH_CONST = 7 +} AnisoFilter; +#endif /*ENUMS_AnisoFilter_H*/ + +#ifndef ENUMS_ArbitraryFilter_H +#define ENUMS_ArbitraryFilter_H +typedef enum ArbitraryFilter { + ARBITRARY_FILTER_2X4_SYM = 0, + ARBITRARY_FILTER_2X4_ASYM = 1, + ARBITRARY_FILTER_4X2_SYM = 2, + ARBITRARY_FILTER_4X2_ASYM = 3, + ARBITRARY_FILTER_4X4_SYM = 4, + ARBITRARY_FILTER_4X4_ASYM = 5, + ARBITRARY_FILTER_USE_FETCH_CONST = 7 +} ArbitraryFilter; +#endif /*ENUMS_ArbitraryFilter_H*/ + +#ifndef ENUMS_VolMagFilter_H +#define ENUMS_VolMagFilter_H +typedef enum VolMagFilter { + VOL_MAG_FILTER_POINT = 0, + VOL_MAG_FILTER_LINEAR = 1, + VOL_MAG_FILTER_USE_FETCH_CONST = 3 +} VolMagFilter; +#endif /*ENUMS_VolMagFilter_H*/ + +#ifndef ENUMS_VolMinFilter_H +#define ENUMS_VolMinFilter_H +typedef enum VolMinFilter { + VOL_MIN_FILTER_POINT = 0, + VOL_MIN_FILTER_LINEAR = 1, + VOL_MIN_FILTER_USE_FETCH_CONST = 3 +} VolMinFilter; +#endif /*ENUMS_VolMinFilter_H*/ + +#ifndef ENUMS_PredSelect_H +#define ENUMS_PredSelect_H +typedef enum PredSelect { + NOT_PREDICATED = 0, + PREDICATED = 1 +} PredSelect; +#endif /*ENUMS_PredSelect_H*/ + +#ifndef ENUMS_SampleLocation_H +#define ENUMS_SampleLocation_H +typedef enum SampleLocation { + SAMPLE_CENTROID = 0, + SAMPLE_CENTER = 1 +} SampleLocation; +#endif /*ENUMS_SampleLocation_H*/ + +#ifndef ENUMS_VertexMode_H +#define ENUMS_VertexMode_H +typedef enum VertexMode { + POSITION_1_VECTOR = 0, + POSITION_2_VECTORS_UNUSED = 1, + POSITION_2_VECTORS_SPRITE = 2, + POSITION_2_VECTORS_EDGE = 3, + POSITION_2_VECTORS_KILL = 4, + POSITION_2_VECTORS_SPRITE_KILL = 5, + POSITION_2_VECTORS_EDGE_KILL = 6, + MULTIPASS = 7 +} VertexMode; +#endif /*ENUMS_VertexMode_H*/ + +#ifndef ENUMS_Sample_Cntl_H +#define ENUMS_Sample_Cntl_H +typedef enum Sample_Cntl { + CENTROIDS_ONLY = 0, + CENTERS_ONLY = 1, + CENTROIDS_AND_CENTERS = 2, + UNDEF = 3 +} Sample_Cntl; +#endif /*ENUMS_Sample_Cntl_H*/ + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +#ifndef ENUMS_MhPerfEncode_H +#define ENUMS_MhPerfEncode_H +typedef enum MhPerfEncode { + CP_R0_REQUESTS = 0, + CP_R1_REQUESTS = 1, + CP_R2_REQUESTS = 2, + CP_R3_REQUESTS = 3, + CP_R4_REQUESTS = 4, + CP_TOTAL_READ_REQUESTS = 5, + CP_W_REQUESTS = 6, + CP_TOTAL_REQUESTS = 7, + CP_DATA_BYTES_WRITTEN = 8, + CP_WRITE_CLEAN_RESPONSES = 9, + CP_R0_READ_BURSTS_RECEIVED = 10, + CP_R1_READ_BURSTS_RECEIVED = 11, + CP_R2_READ_BURSTS_RECEIVED = 12, + CP_R3_READ_BURSTS_RECEIVED = 13, + CP_R4_READ_BURSTS_RECEIVED = 14, + CP_TOTAL_READ_BURSTS_RECEIVED = 15, + CP_R0_DATA_BEATS_READ = 16, + CP_R1_DATA_BEATS_READ = 17, + CP_R2_DATA_BEATS_READ = 18, + CP_R3_DATA_BEATS_READ = 19, + CP_R4_DATA_BEATS_READ = 20, + CP_TOTAL_DATA_BEATS_READ = 21, + VGT_R0_REQUESTS = 22, + VGT_R1_REQUESTS = 23, + VGT_TOTAL_REQUESTS = 24, + VGT_R0_READ_BURSTS_RECEIVED = 25, + VGT_R1_READ_BURSTS_RECEIVED = 26, + VGT_TOTAL_READ_BURSTS_RECEIVED = 27, + VGT_R0_DATA_BEATS_READ = 28, + VGT_R1_DATA_BEATS_READ = 29, + VGT_TOTAL_DATA_BEATS_READ = 30, + TC_REQUESTS = 31, + TC_ROQ_REQUESTS = 32, + TC_INFO_SENT = 33, + TC_READ_BURSTS_RECEIVED = 34, + TC_DATA_BEATS_READ = 35, + TCD_BURSTS_READ = 36, + RB_REQUESTS = 37, + RB_DATA_BYTES_WRITTEN = 38, + RB_WRITE_CLEAN_RESPONSES = 39, + AXI_READ_REQUESTS_ID_0 = 40, + AXI_READ_REQUESTS_ID_1 = 41, + AXI_READ_REQUESTS_ID_2 = 42, + AXI_READ_REQUESTS_ID_3 = 43, + AXI_READ_REQUESTS_ID_4 = 44, + AXI_READ_REQUESTS_ID_5 = 45, + AXI_READ_REQUESTS_ID_6 = 46, + AXI_READ_REQUESTS_ID_7 = 47, + AXI_TOTAL_READ_REQUESTS = 48, + AXI_WRITE_REQUESTS_ID_0 = 49, + AXI_WRITE_REQUESTS_ID_1 = 50, + AXI_WRITE_REQUESTS_ID_2 = 51, + AXI_WRITE_REQUESTS_ID_3 = 52, + AXI_WRITE_REQUESTS_ID_4 = 53, + AXI_WRITE_REQUESTS_ID_5 = 54, + AXI_WRITE_REQUESTS_ID_6 = 55, + AXI_WRITE_REQUESTS_ID_7 = 56, + AXI_TOTAL_WRITE_REQUESTS = 57, + AXI_TOTAL_REQUESTS_ID_0 = 58, + AXI_TOTAL_REQUESTS_ID_1 = 59, + AXI_TOTAL_REQUESTS_ID_2 = 60, + AXI_TOTAL_REQUESTS_ID_3 = 61, + AXI_TOTAL_REQUESTS_ID_4 = 62, + AXI_TOTAL_REQUESTS_ID_5 = 63, + AXI_TOTAL_REQUESTS_ID_6 = 64, + AXI_TOTAL_REQUESTS_ID_7 = 65, + AXI_TOTAL_REQUESTS = 66, + AXI_READ_CHANNEL_BURSTS_ID_0 = 67, + AXI_READ_CHANNEL_BURSTS_ID_1 = 68, + AXI_READ_CHANNEL_BURSTS_ID_2 = 69, + AXI_READ_CHANNEL_BURSTS_ID_3 = 70, + AXI_READ_CHANNEL_BURSTS_ID_4 = 71, + AXI_READ_CHANNEL_BURSTS_ID_5 = 72, + AXI_READ_CHANNEL_BURSTS_ID_6 = 73, + AXI_READ_CHANNEL_BURSTS_ID_7 = 74, + AXI_READ_CHANNEL_TOTAL_BURSTS = 75, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, + AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, + AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, + AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, + AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, + AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, + AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, + AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, + AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, + AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, + AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, + AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, + AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, + TOTAL_MMU_MISSES = 112, + MMU_READ_MISSES = 113, + MMU_WRITE_MISSES = 114, + TOTAL_MMU_HITS = 115, + MMU_READ_HITS = 116, + MMU_WRITE_HITS = 117, + SPLIT_MODE_TC_HITS = 118, + SPLIT_MODE_TC_MISSES = 119, + SPLIT_MODE_NON_TC_HITS = 120, + SPLIT_MODE_NON_TC_MISSES = 121, + STALL_AWAITING_TLB_MISS_FETCH = 122, + MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, + MMU_TLB_MISS_DATA_BEATS_READ = 124, + CP_CYCLES_HELD_OFF = 125, + VGT_CYCLES_HELD_OFF = 126, + TC_CYCLES_HELD_OFF = 127, + TC_ROQ_CYCLES_HELD_OFF = 128, + TC_CYCLES_HELD_OFF_TCD_FULL = 129, + RB_CYCLES_HELD_OFF = 130, + TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, + TLB_MISS_CYCLES_HELD_OFF = 132, + AXI_READ_REQUEST_HELD_OFF = 133, + AXI_WRITE_REQUEST_HELD_OFF = 134, + AXI_REQUEST_HELD_OFF = 135, + AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, + AXI_WRITE_DATA_HELD_OFF = 137, + CP_SAME_PAGE_BANK_REQUESTS = 138, + VGT_SAME_PAGE_BANK_REQUESTS = 139, + TC_SAME_PAGE_BANK_REQUESTS = 140, + TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, + RB_SAME_PAGE_BANK_REQUESTS = 142, + TOTAL_SAME_PAGE_BANK_REQUESTS = 143, + CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, + VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, + TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, + RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, + TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, + TOTAL_MH_READ_REQUESTS = 149, + TOTAL_MH_WRITE_REQUESTS = 150, + TOTAL_MH_REQUESTS = 151, + MH_BUSY = 152, + CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, + VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, + TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, + RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, + TC_ROQ_N_VALID_ENTRIES = 157, + ARQ_N_ENTRIES = 158, + WDB_N_ENTRIES = 159, + MH_READ_LATENCY_OUTST_REQ_SUM = 160, + MC_READ_LATENCY_OUTST_REQ_SUM = 161, + MC_TOTAL_READ_REQUESTS = 162, + ELAPSED_CYCLES_MH_GATED_CLK = 163, +} MhPerfEncode; +#endif /*ENUMS_MhPerfEncode_H*/ + +#ifndef ENUMS_MmuClntBeh_H +#define ENUMS_MmuClntBeh_H +typedef enum MmuClntBeh { + BEH_NEVR = 0, + BEH_TRAN_RNG = 1, + BEH_TRAN_FLT = 2, +} MmuClntBeh; +#endif /*ENUMS_MmuClntBeh_H*/ + +/******************************************************* + * RBBM Enums + *******************************************************/ +#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H +#define ENUMS_RBBM_PERFCOUNT1_SEL_H +typedef enum RBBM_PERFCOUNT1_SEL { + RBBM1_COUNT = 0, + RBBM1_NRT_BUSY = 1, + RBBM1_RB_BUSY = 2, + RBBM1_SQ_CNTX0_BUSY = 3, + RBBM1_SQ_CNTX17_BUSY = 4, + RBBM1_VGT_BUSY = 5, + RBBM1_VGT_NODMA_BUSY = 6, + RBBM1_PA_BUSY = 7, + RBBM1_SC_CNTX_BUSY = 8, + RBBM1_TPC_BUSY = 9, + RBBM1_TC_BUSY = 10, + RBBM1_SX_BUSY = 11, + RBBM1_CP_COHER_BUSY = 12, + RBBM1_CP_NRT_BUSY = 13, + RBBM1_GFX_IDLE_STALL = 14, + RBBM1_INTERRUPT = 15, +} RBBM_PERFCOUNT1_SEL; +#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/ + +/******************************************************* + * CP Enums + *******************************************************/ +#ifndef ENUMS_CP_PERFCOUNT_SEL_H +#define ENUMS_CP_PERFCOUNT_SEL_H +typedef enum CP_PERFCOUNT_SEL { + ALWAYS_COUNT = 0, + TRANS_FIFO_FULL = 1, + TRANS_FIFO_AF = 2, + RCIU_PFPTRANS_WAIT = 3, + Reserved_04 = 4, + Reserved_05 = 5, + RCIU_NRTTRANS_WAIT = 6, + Reserved_07 = 7, + CSF_NRT_READ_WAIT = 8, + CSF_I1_FIFO_FULL = 9, + CSF_I2_FIFO_FULL = 10, + CSF_ST_FIFO_FULL = 11, + Reserved_12 = 12, + CSF_RING_ROQ_FULL = 13, + CSF_I1_ROQ_FULL = 14, + CSF_I2_ROQ_FULL = 15, + CSF_ST_ROQ_FULL = 16, + Reserved_17 = 17, + MIU_TAG_MEM_FULL = 18, + MIU_WRITECLEAN = 19, + Reserved_20 = 20, + Reserved_21 = 21, + MIU_NRT_WRITE_STALLED = 22, + MIU_NRT_READ_STALLED = 23, + ME_WRITE_CONFIRM_FIFO_FULL = 24, + ME_VS_DEALLOC_FIFO_FULL = 25, + ME_PS_DEALLOC_FIFO_FULL = 26, + ME_REGS_VS_EVENT_FIFO_FULL = 27, + ME_REGS_PS_EVENT_FIFO_FULL = 28, + ME_REGS_CF_EVENT_FIFO_FULL = 29, + ME_MICRO_RB_STARVED = 30, + ME_MICRO_I1_STARVED = 31, + ME_MICRO_I2_STARVED = 32, + ME_MICRO_ST_STARVED = 33, + Reserved_34 = 34, + Reserved_35 = 35, + Reserved_36 = 36, + Reserved_37 = 37, + Reserved_38 = 38, + Reserved_39 = 39, + RCIU_RBBM_DWORD_SENT = 40, + ME_BUSY_CLOCKS = 41, + ME_WAIT_CONTEXT_AVAIL = 42, + PFP_TYPE0_PACKET = 43, + PFP_TYPE3_PACKET = 44, + CSF_RB_WPTR_NEQ_RPTR = 45, + CSF_I1_SIZE_NEQ_ZERO = 46, + CSF_I2_SIZE_NEQ_ZERO = 47, + CSF_RBI1I2_FETCHING = 48, + Reserved_49 = 49, + Reserved_50 = 50, + Reserved_51 = 51, + Reserved_52 = 52, + Reserved_53 = 53, + Reserved_54 = 54, + Reserved_55 = 55, + Reserved_56 = 56, + Reserved_57 = 57, + Reserved_58 = 58, + Reserved_59 = 59, + Reserved_60 = 60, + Reserved_61 = 61, + Reserved_62 = 62, + Reserved_63 = 63 +} CP_PERFCOUNT_SEL; +#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/ + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +#ifndef ENUMS_ColorformatX_H +#define ENUMS_ColorformatX_H +typedef enum ColorformatX { + COLORX_4_4_4_4 = 0, + COLORX_1_5_5_5 = 1, + COLORX_5_6_5 = 2, + COLORX_8 = 3, + COLORX_8_8 = 4, + COLORX_8_8_8_8 = 5, + COLORX_S8_8_8_8 = 6, + COLORX_16_FLOAT = 7, + COLORX_16_16_FLOAT = 8, + COLORX_16_16_16_16_FLOAT = 9, + COLORX_32_FLOAT = 10, + COLORX_32_32_FLOAT = 11, + COLORX_32_32_32_32_FLOAT = 12, + COLORX_2_3_3 = 13, + COLORX_8_8_8 = 14, +} ColorformatX; +#endif /*ENUMS_ColorformatX_H*/ + +#ifndef ENUMS_DepthformatX_H +#define ENUMS_DepthformatX_H +typedef enum DepthformatX { + DEPTHX_16 = 0, + DEPTHX_24_8 = 1 +} DepthformatX; +#endif /*ENUMS_DepthformatX_H*/ + +#ifndef ENUMS_CompareFrag_H +#define ENUMS_CompareFrag_H +typedef enum CompareFrag { + FRAG_NEVER = 0, + FRAG_LESS = 1, + FRAG_EQUAL = 2, + FRAG_LEQUAL = 3, + FRAG_GREATER = 4, + FRAG_NOTEQUAL = 5, + FRAG_GEQUAL = 6, + FRAG_ALWAYS = 7 +} CompareFrag; +#endif /*ENUMS_CompareFrag_H*/ + +#ifndef ENUMS_CompareRef_H +#define ENUMS_CompareRef_H +typedef enum CompareRef { + REF_NEVER = 0, + REF_LESS = 1, + REF_EQUAL = 2, + REF_LEQUAL = 3, + REF_GREATER = 4, + REF_NOTEQUAL = 5, + REF_GEQUAL = 6, + REF_ALWAYS = 7 +} CompareRef; +#endif /*ENUMS_CompareRef_H*/ + +#ifndef ENUMS_StencilOp_H +#define ENUMS_StencilOp_H +typedef enum StencilOp { + STENCIL_KEEP = 0, + STENCIL_ZERO = 1, + STENCIL_REPLACE = 2, + STENCIL_INCR_CLAMP = 3, + STENCIL_DECR_CLAMP = 4, + STENCIL_INVERT = 5, + STENCIL_INCR_WRAP = 6, + STENCIL_DECR_WRAP = 7 +} StencilOp; +#endif /*ENUMS_StencilOp_H*/ + +#ifndef ENUMS_BlendOpX_H +#define ENUMS_BlendOpX_H +typedef enum BlendOpX { + BLENDX_ZERO = 0, + BLENDX_ONE = 1, + BLENDX_SRC_COLOR = 4, + BLENDX_ONE_MINUS_SRC_COLOR = 5, + BLENDX_SRC_ALPHA = 6, + BLENDX_ONE_MINUS_SRC_ALPHA = 7, + BLENDX_DST_COLOR = 8, + BLENDX_ONE_MINUS_DST_COLOR = 9, + BLENDX_DST_ALPHA = 10, + BLENDX_ONE_MINUS_DST_ALPHA = 11, + BLENDX_CONSTANT_COLOR = 12, + BLENDX_ONE_MINUS_CONSTANT_COLOR = 13, + BLENDX_CONSTANT_ALPHA = 14, + BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15, + BLENDX_SRC_ALPHA_SATURATE = 16, +} BlendOpX; +#endif /*ENUMS_BlendOpX_H*/ + +#ifndef ENUMS_CombFuncX_H +#define ENUMS_CombFuncX_H +typedef enum CombFuncX { + COMB_DST_PLUS_SRC = 0, + COMB_SRC_MINUS_DST = 1, + COMB_MIN_DST_SRC = 2, + COMB_MAX_DST_SRC = 3, + COMB_DST_MINUS_SRC = 4, + COMB_DST_PLUS_SRC_BIAS = 5, +} CombFuncX; +#endif /*ENUMS_CombFuncX_H*/ + +#ifndef ENUMS_DitherModeX_H +#define ENUMS_DitherModeX_H +typedef enum DitherModeX { + DITHER_DISABLE = 0, + DITHER_ALWAYS = 1, + DITHER_IF_ALPHA_OFF = 2, +} DitherModeX; +#endif /*ENUMS_DitherModeX_H*/ + +#ifndef ENUMS_DitherTypeX_H +#define ENUMS_DitherTypeX_H +typedef enum DitherTypeX { + DITHER_PIXEL = 0, + DITHER_SUBPIXEL = 1, +} DitherTypeX; +#endif /*ENUMS_DitherTypeX_H*/ + +#ifndef ENUMS_EdramMode_H +#define ENUMS_EdramMode_H +typedef enum EdramMode { + EDRAM_NOP = 0, + COLOR_DEPTH = 4, + DEPTH_ONLY = 5, + EDRAM_COPY = 6, +} EdramMode; +#endif /*ENUMS_EdramMode_H*/ + +#ifndef ENUMS_SurfaceEndian_H +#define ENUMS_SurfaceEndian_H +typedef enum SurfaceEndian { + ENDIAN_NONE = 0, + ENDIAN_8IN16 = 1, + ENDIAN_8IN32 = 2, + ENDIAN_16IN32 = 3, + ENDIAN_8IN64 = 4, + ENDIAN_8IN128 = 5, +} SurfaceEndian; +#endif /*ENUMS_SurfaceEndian_H*/ + +#ifndef ENUMS_EdramSizeX_H +#define ENUMS_EdramSizeX_H +typedef enum EdramSizeX { + EDRAMSIZE_16KB = 0, + EDRAMSIZE_32KB = 1, + EDRAMSIZE_64KB = 2, + EDRAMSIZE_128KB = 3, + EDRAMSIZE_256KB = 4, + EDRAMSIZE_512KB = 5, + EDRAMSIZE_1MB = 6, + EDRAMSIZE_2MB = 7, + EDRAMSIZE_4MB = 8, + EDRAMSIZE_8MB = 9, + EDRAMSIZE_16MB = 10, +} EdramSizeX; +#endif /*ENUMS_EdramSizeX_H*/ + +#ifndef ENUMS_RB_PERFCNT_SELECT_H +#define ENUMS_RB_PERFCNT_SELECT_H +typedef enum RB_PERFCNT_SELECT { + RBPERF_CNTX_BUSY = 0, + RBPERF_CNTX_BUSY_MAX = 1, + RBPERF_SX_QUAD_STARVED = 2, + RBPERF_SX_QUAD_STARVED_MAX = 3, + RBPERF_GA_GC_CH0_SYS_REQ = 4, + RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, + RBPERF_GA_GC_CH1_SYS_REQ = 6, + RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, + RBPERF_MH_STARVED = 8, + RBPERF_MH_STARVED_MAX = 9, + RBPERF_AZ_BC_COLOR_BUSY = 10, + RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, + RBPERF_AZ_BC_Z_BUSY = 12, + RBPERF_AZ_BC_Z_BUSY_MAX = 13, + RBPERF_RB_SC_TILE_RTR_N = 14, + RBPERF_RB_SC_TILE_RTR_N_MAX = 15, + RBPERF_RB_SC_SAMP_RTR_N = 16, + RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, + RBPERF_RB_SX_QUAD_RTR_N = 18, + RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, + RBPERF_RB_SX_COLOR_RTR_N = 20, + RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, + RBPERF_RB_SC_SAMP_LZ_BUSY = 22, + RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, + RBPERF_ZXP_STALL = 24, + RBPERF_ZXP_STALL_MAX = 25, + RBPERF_EVENT_PENDING = 26, + RBPERF_EVENT_PENDING_MAX = 27, + RBPERF_RB_MH_VALID = 28, + RBPERF_RB_MH_VALID_MAX = 29, + RBPERF_SX_RB_QUAD_SEND = 30, + RBPERF_SX_RB_COLOR_SEND = 31, + RBPERF_SC_RB_TILE_SEND = 32, + RBPERF_SC_RB_SAMPLE_SEND = 33, + RBPERF_SX_RB_MEM_EXPORT = 34, + RBPERF_SX_RB_QUAD_EVENT = 35, + RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, + RBPERF_SC_RB_TILE_EVENT_ALL = 37, + RBPERF_RB_SC_EZ_SEND = 38, + RBPERF_RB_SX_INDEX_SEND = 39, + RBPERF_GMEM_INTFO_RD = 40, + RBPERF_GMEM_INTF1_RD = 41, + RBPERF_GMEM_INTFO_WR = 42, + RBPERF_GMEM_INTF1_WR = 43, + RBPERF_RB_CP_CONTEXT_DONE = 44, + RBPERF_RB_CP_CACHE_FLUSH = 45, + RBPERF_ZPASS_DONE = 46, + RBPERF_ZCMD_VALID = 47, + RBPERF_CCMD_VALID = 48, + RBPERF_ACCUM_GRANT = 49, + RBPERF_ACCUM_C0_GRANT = 50, + RBPERF_ACCUM_C1_GRANT = 51, + RBPERF_ACCUM_FULL_BE_WR = 52, + RBPERF_ACCUM_REQUEST_NO_GRANT = 53, + RBPERF_ACCUM_TIMEOUT_PULSE = 54, + RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, + RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, +} RB_PERFCNT_SELECT; +#endif /*ENUMS_RB_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_DepthFormat_H +#define ENUMS_DepthFormat_H +typedef enum DepthFormat { + DEPTH_24_8 = 22, + DEPTH_24_8_FLOAT = 23, + DEPTH_16 = 24, +} DepthFormat; +#endif /*ENUMS_DepthFormat_H*/ + +#ifndef ENUMS_SurfaceSwap_H +#define ENUMS_SurfaceSwap_H +typedef enum SurfaceSwap { + SWAP_LOWRED = 0, + SWAP_LOWBLUE = 1 +} SurfaceSwap; +#endif /*ENUMS_SurfaceSwap_H*/ + +#ifndef ENUMS_DepthArray_H +#define ENUMS_DepthArray_H +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0, + ARRAY_2D_DEPTH = 1, +} DepthArray; +#endif /*ENUMS_DepthArray_H*/ + +#ifndef ENUMS_ColorArray_H +#define ENUMS_ColorArray_H +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0, + ARRAY_2D_COLOR = 1, + ARRAY_3D_SLICE_COLOR = 3 +} ColorArray; +#endif /*ENUMS_ColorArray_H*/ + +#ifndef ENUMS_ColorFormat_H +#define ENUMS_ColorFormat_H +typedef enum ColorFormat { + COLOR_8 = 2, + COLOR_1_5_5_5 = 3, + COLOR_5_6_5 = 4, + COLOR_6_5_5 = 5, + COLOR_8_8_8_8 = 6, + COLOR_2_10_10_10 = 7, + COLOR_8_A = 8, + COLOR_8_B = 9, + COLOR_8_8 = 10, + COLOR_8_8_8 = 11, + COLOR_8_8_8_8_A = 14, + COLOR_4_4_4_4 = 15, + COLOR_10_11_11 = 16, + COLOR_11_11_10 = 17, + COLOR_16 = 24, + COLOR_16_16 = 25, + COLOR_16_16_16_16 = 26, + COLOR_16_FLOAT = 30, + COLOR_16_16_FLOAT = 31, + COLOR_16_16_16_16_FLOAT = 32, + COLOR_32_FLOAT = 36, + COLOR_32_32_FLOAT = 37, + COLOR_32_32_32_32_FLOAT = 38, + COLOR_2_3_3 = 39, +} ColorFormat; +#endif /*ENUMS_ColorFormat_H*/ + +#ifndef ENUMS_SurfaceNumber_H +#define ENUMS_SurfaceNumber_H +typedef enum SurfaceNumber { + NUMBER_UREPEAT = 0, + NUMBER_SREPEAT = 1, + NUMBER_UINTEGER = 2, + NUMBER_SINTEGER = 3, + NUMBER_GAMMA = 4, + NUMBER_FIXED = 5, + NUMBER_FLOAT = 7 +} SurfaceNumber; +#endif /*ENUMS_SurfaceNumber_H*/ + +#ifndef ENUMS_SurfaceFormat_H +#define ENUMS_SurfaceFormat_H +typedef enum SurfaceFormat { + FMT_1_REVERSE = 0, + FMT_1 = 1, + FMT_8 = 2, + FMT_1_5_5_5 = 3, + FMT_5_6_5 = 4, + FMT_6_5_5 = 5, + FMT_8_8_8_8 = 6, + FMT_2_10_10_10 = 7, + FMT_8_A = 8, + FMT_8_B = 9, + FMT_8_8 = 10, + FMT_Cr_Y1_Cb_Y0 = 11, + FMT_Y1_Cr_Y0_Cb = 12, + FMT_5_5_5_1 = 13, + FMT_8_8_8_8_A = 14, + FMT_4_4_4_4 = 15, + FMT_8_8_8 = 16, + FMT_DXT1 = 18, + FMT_DXT2_3 = 19, + FMT_DXT4_5 = 20, + FMT_10_10_10_2 = 21, + FMT_24_8 = 22, + FMT_16 = 24, + FMT_16_16 = 25, + FMT_16_16_16_16 = 26, + FMT_16_EXPAND = 27, + FMT_16_16_EXPAND = 28, + FMT_16_16_16_16_EXPAND = 29, + FMT_16_FLOAT = 30, + FMT_16_16_FLOAT = 31, + FMT_16_16_16_16_FLOAT = 32, + FMT_32 = 33, + FMT_32_32 = 34, + FMT_32_32_32_32 = 35, + FMT_32_FLOAT = 36, + FMT_32_32_FLOAT = 37, + FMT_32_32_32_32_FLOAT = 38, + FMT_ATI_TC_RGB = 39, + FMT_ATI_TC_RGBA = 40, + FMT_ATI_TC_555_565_RGB = 41, + FMT_ATI_TC_555_565_RGBA = 42, + FMT_ATI_TC_RGBA_INTERP = 43, + FMT_ATI_TC_555_565_RGBA_INTERP = 44, + FMT_ETC1_RGBA_INTERP = 46, + FMT_ETC1_RGB = 47, + FMT_ETC1_RGBA = 48, + FMT_DXN = 49, + FMT_2_3_3 = 51, + FMT_2_10_10_10_AS_16_16_16_16 = 54, + FMT_10_10_10_2_AS_16_16_16_16 = 55, + FMT_32_32_32_FLOAT = 57, + FMT_DXT3A = 58, + FMT_DXT5A = 59, + FMT_CTX1 = 60, +} SurfaceFormat; +#endif /*ENUMS_SurfaceFormat_H*/ + +#ifndef ENUMS_SurfaceTiling_H +#define ENUMS_SurfaceTiling_H +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0, + ARRAY_TILED = 1 +} SurfaceTiling; +#endif /*ENUMS_SurfaceTiling_H*/ + +#ifndef ENUMS_SurfaceArray_H +#define ENUMS_SurfaceArray_H +typedef enum SurfaceArray { + ARRAY_1D = 0, + ARRAY_2D = 1, + ARRAY_3D = 2, + ARRAY_3D_SLICE = 3 +} SurfaceArray; +#endif /*ENUMS_SurfaceArray_H*/ + +#ifndef ENUMS_SurfaceNumberX_H +#define ENUMS_SurfaceNumberX_H +typedef enum SurfaceNumberX { + NUMBERX_UREPEAT = 0, + NUMBERX_SREPEAT = 1, + NUMBERX_UINTEGER = 2, + NUMBERX_SINTEGER = 3, + NUMBERX_FLOAT = 7 +} SurfaceNumberX; +#endif /*ENUMS_SurfaceNumberX_H*/ + +#ifndef ENUMS_ColorArrayX_H +#define ENUMS_ColorArrayX_H +typedef enum ColorArrayX { + ARRAYX_2D_COLOR = 0, + ARRAYX_3D_SLICE_COLOR = 1, +} ColorArrayX; +#endif /*ENUMS_ColorArrayX_H*/ + +#endif /*_yamato_ENUM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h new file mode 100644 index 000000000000..f2f4dec63daa --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h @@ -0,0 +1,1674 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_ENUMTYPE(SU_PERFCNT_SELECT) + GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0) + GENERATE_ENUM(UNUSED1, 1) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13) + GENERATE_ENUM(UNUSED2, 14) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15) + GENERATE_ENUM(UNUSED3, 16) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19) + GENERATE_ENUM(UNUSED4, 20) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21) + GENERATE_ENUM(UNUSED5, 22) + GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35) + GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36) + GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37) + GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38) + GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45) + GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49) + GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50) + GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51) + GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71) + GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72) + GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77) + GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78) + GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79) + GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80) + GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81) + GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84) + GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85) + GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91) + GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92) + GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95) + GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96) + GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97) + GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98) + GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99) + GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100) + GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101) +END_ENUMTYPE(SU_PERFCNT_SELECT) + +START_ENUMTYPE(SC_PERFCNT_SELECT) + GENERATE_ENUM(SC_SR_WINDOW_VALID, 0) + GENERATE_ENUM(SC_CW_WINDOW_VALID, 1) + GENERATE_ENUM(SC_QM_WINDOW_VALID, 2) + GENERATE_ENUM(SC_FW_WINDOW_VALID, 3) + GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4) + GENERATE_ENUM(SC_IT_WINDOW_VALID, 5) + GENERATE_ENUM(SC_STARVED_BY_PA, 6) + GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7) + GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8) + GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9) + GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10) + GENERATE_ENUM(SC_STALLED_BY_SQ, 11) + GENERATE_ENUM(SC_STALLED_BY_SP, 12) + GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13) + GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14) + GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15) + GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16) + GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17) +END_ENUMTYPE(SC_PERFCNT_SELECT) + +START_ENUMTYPE(VGT_DI_PRIM_TYPE) + GENERATE_ENUM(DI_PT_NONE, 0) + GENERATE_ENUM(DI_PT_POINTLIST, 1) + GENERATE_ENUM(DI_PT_LINELIST, 2) + GENERATE_ENUM(DI_PT_LINESTRIP, 3) + GENERATE_ENUM(DI_PT_TRILIST, 4) + GENERATE_ENUM(DI_PT_TRIFAN, 5) + GENERATE_ENUM(DI_PT_TRISTRIP, 6) + GENERATE_ENUM(DI_PT_UNUSED_1, 7) + GENERATE_ENUM(DI_PT_RECTLIST, 8) + GENERATE_ENUM(DI_PT_UNUSED_2, 9) + GENERATE_ENUM(DI_PT_UNUSED_3, 10) + GENERATE_ENUM(DI_PT_UNUSED_4, 11) + GENERATE_ENUM(DI_PT_UNUSED_5, 12) + GENERATE_ENUM(DI_PT_QUADLIST, 13) + GENERATE_ENUM(DI_PT_QUADSTRIP, 14) + GENERATE_ENUM(DI_PT_POLYGON, 15) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19) + GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20) + GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21) + GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22) +END_ENUMTYPE(VGT_DI_PRIM_TYPE) + +START_ENUMTYPE(VGT_DI_SOURCE_SELECT) + GENERATE_ENUM(DI_SRC_SEL_DMA, 0) + GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1) + GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2) + GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3) +END_ENUMTYPE(VGT_DI_SOURCE_SELECT) + +START_ENUMTYPE(VGT_DI_INDEX_SIZE) + GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0) + GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1) +END_ENUMTYPE(VGT_DI_INDEX_SIZE) + +START_ENUMTYPE(VGT_DI_SMALL_INDEX) + GENERATE_ENUM(DI_USE_INDEX_SIZE, 0) + GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1) +END_ENUMTYPE(VGT_DI_SMALL_INDEX) + +START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0) + GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + +START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0) + GENERATE_ENUM(GRP_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + +START_ENUMTYPE(VGT_EVENT_TYPE) + GENERATE_ENUM(VS_DEALLOC, 0) + GENERATE_ENUM(PS_DEALLOC, 1) + GENERATE_ENUM(VS_DONE_TS, 2) + GENERATE_ENUM(PS_DONE_TS, 3) + GENERATE_ENUM(CACHE_FLUSH_TS, 4) + GENERATE_ENUM(CONTEXT_DONE, 5) + GENERATE_ENUM(CACHE_FLUSH, 6) + GENERATE_ENUM(VIZQUERY_START, 7) + GENERATE_ENUM(VIZQUERY_END, 8) + GENERATE_ENUM(SC_WAIT_WC, 9) + GENERATE_ENUM(RST_PIX_CNT, 13) + GENERATE_ENUM(RST_VTX_CNT, 14) + GENERATE_ENUM(TILE_FLUSH, 15) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20) + GENERATE_ENUM(ZPASS_DONE, 21) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22) + GENERATE_ENUM(PERFCOUNTER_START, 23) + GENERATE_ENUM(PERFCOUNTER_STOP, 24) + GENERATE_ENUM(VS_FETCH_DONE, 27) +END_ENUMTYPE(VGT_EVENT_TYPE) + +START_ENUMTYPE(VGT_DMA_SWAP_MODE) + GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0) + GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1) + GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2) + GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3) +END_ENUMTYPE(VGT_DMA_SWAP_MODE) + +START_ENUMTYPE(VGT_PERFCOUNT_SELECT) + GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0) + GENERATE_ENUM(VGT_SQ_SEND, 1) + GENERATE_ENUM(VGT_SQ_STALLED, 2) + GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3) + GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4) + GENERATE_ENUM(VGT_SQ_STATIC, 5) + GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6) + GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7) + GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10) + GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11) + GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12) + GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15) + GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16) + GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17) + GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20) + GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21) + GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28) + GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29) + GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30) + GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31) + GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32) + GENERATE_ENUM(SPARE33, 33) + GENERATE_ENUM(SPARE34, 34) + GENERATE_ENUM(SPARE35, 35) + GENERATE_ENUM(SPARE36, 36) + GENERATE_ENUM(SPARE37, 37) + GENERATE_ENUM(SPARE38, 38) + GENERATE_ENUM(SPARE39, 39) + GENERATE_ENUM(TE_SU_IN_VALID, 40) + GENERATE_ENUM(TE_SU_IN_READ, 41) + GENERATE_ENUM(TE_SU_IN_PRIM, 42) + GENERATE_ENUM(TE_SU_IN_EOP, 43) + GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44) + GENERATE_ENUM(TE_WK_IN_VALID, 45) + GENERATE_ENUM(TE_WK_IN_READ, 46) + GENERATE_ENUM(TE_OUT_PRIM_VALID, 47) + GENERATE_ENUM(TE_OUT_PRIM_READ, 48) +END_ENUMTYPE(VGT_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCR_PERFCOUNT_SELECT) + GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0) + GENERATE_ENUM(reserved_46, 1) + GENERATE_ENUM(reserved_47, 2) + GENERATE_ENUM(reserved_48, 3) + GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4) + GENERATE_ENUM(OPMUX0_L2_WRITES, 5) + GENERATE_ENUM(reserved_49, 6) + GENERATE_ENUM(reserved_50, 7) + GENERATE_ENUM(reserved_51, 8) +END_ENUMTYPE(TCR_PERFCOUNT_SELECT) + +START_ENUMTYPE(TP_PERFCOUNT_SELECT) + GENERATE_ENUM(POINT_QUADS, 0) + GENERATE_ENUM(BILIN_QUADS, 1) + GENERATE_ENUM(ANISO_QUADS, 2) + GENERATE_ENUM(MIP_QUADS, 3) + GENERATE_ENUM(VOL_QUADS, 4) + GENERATE_ENUM(MIP_VOL_QUADS, 5) + GENERATE_ENUM(MIP_ANISO_QUADS, 6) + GENERATE_ENUM(VOL_ANISO_QUADS, 7) + GENERATE_ENUM(ANISO_2_1_QUADS, 8) + GENERATE_ENUM(ANISO_4_1_QUADS, 9) + GENERATE_ENUM(ANISO_6_1_QUADS, 10) + GENERATE_ENUM(ANISO_8_1_QUADS, 11) + GENERATE_ENUM(ANISO_10_1_QUADS, 12) + GENERATE_ENUM(ANISO_12_1_QUADS, 13) + GENERATE_ENUM(ANISO_14_1_QUADS, 14) + GENERATE_ENUM(ANISO_16_1_QUADS, 15) + GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16) + GENERATE_ENUM(ALIGN_2_QUADS, 17) + GENERATE_ENUM(ALIGN_4_QUADS, 18) + GENERATE_ENUM(PIX_0_QUAD, 19) + GENERATE_ENUM(PIX_1_QUAD, 20) + GENERATE_ENUM(PIX_2_QUAD, 21) + GENERATE_ENUM(PIX_3_QUAD, 22) + GENERATE_ENUM(PIX_4_QUAD, 23) + GENERATE_ENUM(TP_MIPMAP_LOD0, 24) + GENERATE_ENUM(TP_MIPMAP_LOD1, 25) + GENERATE_ENUM(TP_MIPMAP_LOD2, 26) + GENERATE_ENUM(TP_MIPMAP_LOD3, 27) + GENERATE_ENUM(TP_MIPMAP_LOD4, 28) + GENERATE_ENUM(TP_MIPMAP_LOD5, 29) + GENERATE_ENUM(TP_MIPMAP_LOD6, 30) + GENERATE_ENUM(TP_MIPMAP_LOD7, 31) + GENERATE_ENUM(TP_MIPMAP_LOD8, 32) + GENERATE_ENUM(TP_MIPMAP_LOD9, 33) + GENERATE_ENUM(TP_MIPMAP_LOD10, 34) + GENERATE_ENUM(TP_MIPMAP_LOD11, 35) + GENERATE_ENUM(TP_MIPMAP_LOD12, 36) + GENERATE_ENUM(TP_MIPMAP_LOD13, 37) + GENERATE_ENUM(TP_MIPMAP_LOD14, 38) +END_ENUMTYPE(TP_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCM_PERFCOUNT_SELECT) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0) + GENERATE_ENUM(reserved_01, 1) + GENERATE_ENUM(reserved_02, 2) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6) + GENERATE_ENUM(reserved_07, 7) + GENERATE_ENUM(reserved_08, 8) + GENERATE_ENUM(reserved_09, 9) + GENERATE_ENUM(reserved_10, 10) + GENERATE_ENUM(reserved_11, 11) + GENERATE_ENUM(reserved_12, 12) + GENERATE_ENUM(reserved_13, 13) + GENERATE_ENUM(reserved_14, 14) + GENERATE_ENUM(reserved_15, 15) + GENERATE_ENUM(reserved_16, 16) + GENERATE_ENUM(reserved_17, 17) + GENERATE_ENUM(reserved_18, 18) + GENERATE_ENUM(reserved_19, 19) + GENERATE_ENUM(reserved_20, 20) + GENERATE_ENUM(reserved_21, 21) + GENERATE_ENUM(reserved_22, 22) + GENERATE_ENUM(reserved_23, 23) + GENERATE_ENUM(reserved_24, 24) + GENERATE_ENUM(reserved_25, 25) + GENERATE_ENUM(reserved_26, 26) + GENERATE_ENUM(reserved_27, 27) + GENERATE_ENUM(READ_STARVED_QUAD0, 28) + GENERATE_ENUM(reserved_29, 29) + GENERATE_ENUM(reserved_30, 30) + GENERATE_ENUM(reserved_31, 31) + GENERATE_ENUM(READ_STARVED, 32) + GENERATE_ENUM(READ_STALLED_QUAD0, 33) + GENERATE_ENUM(reserved_34, 34) + GENERATE_ENUM(reserved_35, 35) + GENERATE_ENUM(reserved_36, 36) + GENERATE_ENUM(READ_STALLED, 37) + GENERATE_ENUM(VALID_READ_QUAD0, 38) + GENERATE_ENUM(reserved_39, 39) + GENERATE_ENUM(reserved_40, 40) + GENERATE_ENUM(reserved_41, 41) + GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42) + GENERATE_ENUM(reserved_43, 43) + GENERATE_ENUM(reserved_44, 44) + GENERATE_ENUM(reserved_45, 45) + GENERATE_ENUM(TC_TP_STARVED, 46) +END_ENUMTYPE(TCM_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCF_PERFCOUNT_SELECT) + GENERATE_ENUM(VALID_CYCLES, 0) + GENERATE_ENUM(SINGLE_PHASES, 1) + GENERATE_ENUM(ANISO_PHASES, 2) + GENERATE_ENUM(MIP_PHASES, 3) + GENERATE_ENUM(VOL_PHASES, 4) + GENERATE_ENUM(MIP_VOL_PHASES, 5) + GENERATE_ENUM(MIP_ANISO_PHASES, 6) + GENERATE_ENUM(VOL_ANISO_PHASES, 7) + GENERATE_ENUM(ANISO_2_1_PHASES, 8) + GENERATE_ENUM(ANISO_4_1_PHASES, 9) + GENERATE_ENUM(ANISO_6_1_PHASES, 10) + GENERATE_ENUM(ANISO_8_1_PHASES, 11) + GENERATE_ENUM(ANISO_10_1_PHASES, 12) + GENERATE_ENUM(ANISO_12_1_PHASES, 13) + GENERATE_ENUM(ANISO_14_1_PHASES, 14) + GENERATE_ENUM(ANISO_16_1_PHASES, 15) + GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16) + GENERATE_ENUM(ALIGN_2_PHASES, 17) + GENERATE_ENUM(ALIGN_4_PHASES, 18) + GENERATE_ENUM(TPC_BUSY, 19) + GENERATE_ENUM(TPC_STALLED, 20) + GENERATE_ENUM(TPC_STARVED, 21) + GENERATE_ENUM(TPC_WORKING, 22) + GENERATE_ENUM(TPC_WALKER_BUSY, 23) + GENERATE_ENUM(TPC_WALKER_STALLED, 24) + GENERATE_ENUM(TPC_WALKER_WORKING, 25) + GENERATE_ENUM(TPC_ALIGNER_BUSY, 26) + GENERATE_ENUM(TPC_ALIGNER_STALLED, 27) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29) + GENERATE_ENUM(TPC_ALIGNER_WORKING, 30) + GENERATE_ENUM(TPC_BLEND_BUSY, 31) + GENERATE_ENUM(TPC_BLEND_SYNC, 32) + GENERATE_ENUM(TPC_BLEND_STARVED, 33) + GENERATE_ENUM(TPC_BLEND_WORKING, 34) + GENERATE_ENUM(OPCODE_0x00, 35) + GENERATE_ENUM(OPCODE_0x01, 36) + GENERATE_ENUM(OPCODE_0x04, 37) + GENERATE_ENUM(OPCODE_0x10, 38) + GENERATE_ENUM(OPCODE_0x11, 39) + GENERATE_ENUM(OPCODE_0x12, 40) + GENERATE_ENUM(OPCODE_0x13, 41) + GENERATE_ENUM(OPCODE_0x18, 42) + GENERATE_ENUM(OPCODE_0x19, 43) + GENERATE_ENUM(OPCODE_0x1A, 44) + GENERATE_ENUM(OPCODE_OTHER, 45) + GENERATE_ENUM(IN_FIFO_0_EMPTY, 56) + GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57) + GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58) + GENERATE_ENUM(IN_FIFO_0_FULL, 59) + GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72) + GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73) + GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74) + GENERATE_ENUM(IN_FIFO_TPC_FULL, 75) + GENERATE_ENUM(TPC_TC_XFC, 76) + GENERATE_ENUM(TPC_TC_STATE, 77) + GENERATE_ENUM(TC_STALL, 78) + GENERATE_ENUM(QUAD0_TAPS, 79) + GENERATE_ENUM(QUADS, 83) + GENERATE_ENUM(TCA_SYNC_STALL, 84) + GENERATE_ENUM(TAG_STALL, 85) + GENERATE_ENUM(TCB_SYNC_STALL, 88) + GENERATE_ENUM(TCA_VALID, 89) + GENERATE_ENUM(PROBES_VALID, 90) + GENERATE_ENUM(MISS_STALL, 91) + GENERATE_ENUM(FETCH_FIFO_STALL, 92) + GENERATE_ENUM(TCO_STALL, 93) + GENERATE_ENUM(ANY_STALL, 94) + GENERATE_ENUM(TAG_MISSES, 95) + GENERATE_ENUM(TAG_HITS, 96) + GENERATE_ENUM(SUB_TAG_MISSES, 97) + GENERATE_ENUM(SET0_INVALIDATES, 98) + GENERATE_ENUM(SET1_INVALIDATES, 99) + GENERATE_ENUM(SET2_INVALIDATES, 100) + GENERATE_ENUM(SET3_INVALIDATES, 101) + GENERATE_ENUM(SET0_TAG_MISSES, 102) + GENERATE_ENUM(SET1_TAG_MISSES, 103) + GENERATE_ENUM(SET2_TAG_MISSES, 104) + GENERATE_ENUM(SET3_TAG_MISSES, 105) + GENERATE_ENUM(SET0_TAG_HITS, 106) + GENERATE_ENUM(SET1_TAG_HITS, 107) + GENERATE_ENUM(SET2_TAG_HITS, 108) + GENERATE_ENUM(SET3_TAG_HITS, 109) + GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110) + GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111) + GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112) + GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113) + GENERATE_ENUM(SET0_EVICT1, 114) + GENERATE_ENUM(SET0_EVICT2, 115) + GENERATE_ENUM(SET0_EVICT3, 116) + GENERATE_ENUM(SET0_EVICT4, 117) + GENERATE_ENUM(SET0_EVICT5, 118) + GENERATE_ENUM(SET0_EVICT6, 119) + GENERATE_ENUM(SET0_EVICT7, 120) + GENERATE_ENUM(SET0_EVICT8, 121) + GENERATE_ENUM(SET1_EVICT1, 130) + GENERATE_ENUM(SET1_EVICT2, 131) + GENERATE_ENUM(SET1_EVICT3, 132) + GENERATE_ENUM(SET1_EVICT4, 133) + GENERATE_ENUM(SET1_EVICT5, 134) + GENERATE_ENUM(SET1_EVICT6, 135) + GENERATE_ENUM(SET1_EVICT7, 136) + GENERATE_ENUM(SET1_EVICT8, 137) + GENERATE_ENUM(SET2_EVICT1, 146) + GENERATE_ENUM(SET2_EVICT2, 147) + GENERATE_ENUM(SET2_EVICT3, 148) + GENERATE_ENUM(SET2_EVICT4, 149) + GENERATE_ENUM(SET2_EVICT5, 150) + GENERATE_ENUM(SET2_EVICT6, 151) + GENERATE_ENUM(SET2_EVICT7, 152) + GENERATE_ENUM(SET2_EVICT8, 153) + GENERATE_ENUM(SET3_EVICT1, 162) + GENERATE_ENUM(SET3_EVICT2, 163) + GENERATE_ENUM(SET3_EVICT3, 164) + GENERATE_ENUM(SET3_EVICT4, 165) + GENERATE_ENUM(SET3_EVICT5, 166) + GENERATE_ENUM(SET3_EVICT6, 167) + GENERATE_ENUM(SET3_EVICT7, 168) + GENERATE_ENUM(SET3_EVICT8, 169) + GENERATE_ENUM(FF_EMPTY, 178) + GENERATE_ENUM(FF_LT_HALF_FULL, 179) + GENERATE_ENUM(FF_HALF_FULL, 180) + GENERATE_ENUM(FF_FULL, 181) + GENERATE_ENUM(FF_XFC, 182) + GENERATE_ENUM(FF_STALLED, 183) + GENERATE_ENUM(FG_MASKS, 184) + GENERATE_ENUM(FG_LEFT_MASKS, 185) + GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186) + GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187) + GENERATE_ENUM(FG_LEFT_FG_STALL, 188) + GENERATE_ENUM(FG_LEFT_SECTORS, 189) + GENERATE_ENUM(FG0_REQUESTS, 195) + GENERATE_ENUM(FG0_STALLED, 196) + GENERATE_ENUM(MEM_REQ512, 199) + GENERATE_ENUM(MEM_REQ_SENT, 200) + GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202) + GENERATE_ENUM(TC0_MH_STALLED, 203) +END_ENUMTYPE(TCF_PERFCOUNT_SELECT) + +START_ENUMTYPE(SQ_PERFCNT_SELECT) + GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0) + GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9) + GENERATE_ENUM(SQ_EXPORT_CYCLES, 10) + GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11) + GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12) + GENERATE_ENUM(SQ_ALU_CST_STALL, 13) + GENERATE_ENUM(SQ_ALU_TEX_STALL, 14) + GENERATE_ENUM(SQ_INST_WRITTEN, 15) + GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16) + GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17) + GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18) + GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19) + GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20) + GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21) + GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22) + GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23) + GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24) + GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25) + GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26) + GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27) + GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28) + GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33) + GENERATE_ENUM(SQ_ALU_NOPS, 34) + GENERATE_ENUM(SQ_PRED_SKIP, 35) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38) + GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41) + GENERATE_ENUM(SQ_GPR_STALL_VTX, 42) + GENERATE_ENUM(SQ_GPR_STALL_PIX, 43) + GENERATE_ENUM(SQ_VTX_RS_STALL, 44) + GENERATE_ENUM(SQ_PIX_RS_STALL, 45) + GENERATE_ENUM(SQ_SX_PC_FULL, 46) + GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47) + GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48) + GENERATE_ENUM(SQ_INTERP_QUADS, 49) + GENERATE_ENUM(SQ_INTERP_ACTIVE, 50) + GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51) + GENERATE_ENUM(SQ_IN_VTX_STALL, 52) + GENERATE_ENUM(SQ_VTX_CNT, 53) + GENERATE_ENUM(SQ_VTX_VECTOR2, 54) + GENERATE_ENUM(SQ_VTX_VECTOR3, 55) + GENERATE_ENUM(SQ_VTX_VECTOR4, 56) + GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57) + GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58) + GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61) + GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD3, 68) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD3, 70) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_VTX, 76) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_PIX, 80) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81) + GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD3, 85) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD3, 86) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94) + GENERATE_ENUM(VC_PERF_STATIC, 95) + GENERATE_ENUM(VC_PERF_STALLED, 96) + GENERATE_ENUM(VC_PERF_STARVED, 97) + GENERATE_ENUM(VC_PERF_SEND, 98) + GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99) + GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100) + GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101) + GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102) + GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103) + GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104) + GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105) + GENERATE_ENUM(PTRBUFF_EF_PUSH, 106) + GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107) + GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108) + GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112) + GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113) + GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114) + GENERATE_ENUM(PTRBUFF_PI_RTR, 115) + GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116) + GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117) + GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118) + GENERATE_ENUM(PTRBUFF_SQ_DEC, 119) + GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120) + GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121) + GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122) + GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123) + GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124) + GENERATE_ENUM(PTRBUFF_END_BUFFER, 125) + GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126) + GENERATE_ENUM(VERTS_WRITTEN_SPI, 127) + GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128) + GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129) + GENERATE_ENUM(TP_DATA_RETURN, 130) + GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131) + GENERATE_ENUM(SPI_WRITES_SP, 132) + GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133) + GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134) + GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135) + GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136) + GENERATE_ENUM(SP_EXPORTS_TO_SX, 137) + GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138) + GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139) + GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140) + GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141) + GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142) + GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143) + GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144) + GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145) + GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146) + GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147) + GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148) + GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149) + GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150) + GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151) + GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152) + GENERATE_ENUM(SQ_PIX_TOTAL, 153) + GENERATE_ENUM(SQ_PIX_KILLED, 154) +END_ENUMTYPE(SQ_PERFCNT_SELECT) + +START_ENUMTYPE(SX_PERFCNT_SELECT) + GENERATE_ENUM(SX_EXPORT_VECTORS, 0) + GENERATE_ENUM(SX_DUMMY_QUADS, 1) + GENERATE_ENUM(SX_ALPHA_FAIL, 2) + GENERATE_ENUM(SX_RB_QUAD_BUSY, 3) + GENERATE_ENUM(SX_RB_COLOR_BUSY, 4) + GENERATE_ENUM(SX_RB_QUAD_STALL, 5) + GENERATE_ENUM(SX_RB_COLOR_STALL, 6) +END_ENUMTYPE(SX_PERFCNT_SELECT) + +START_ENUMTYPE(Abs_modifier) + GENERATE_ENUM(NO_ABS_MOD, 0) + GENERATE_ENUM(ABS_MOD, 1) +END_ENUMTYPE(Abs_modifier) + +START_ENUMTYPE(Exporting) + GENERATE_ENUM(NOT_EXPORTING, 0) + GENERATE_ENUM(EXPORTING, 1) +END_ENUMTYPE(Exporting) + +START_ENUMTYPE(ScalarOpcode) + GENERATE_ENUM(ADDs, 0) + GENERATE_ENUM(ADD_PREVs, 1) + GENERATE_ENUM(MULs, 2) + GENERATE_ENUM(MUL_PREVs, 3) + GENERATE_ENUM(MUL_PREV2s, 4) + GENERATE_ENUM(MAXs, 5) + GENERATE_ENUM(MINs, 6) + GENERATE_ENUM(SETEs, 7) + GENERATE_ENUM(SETGTs, 8) + GENERATE_ENUM(SETGTEs, 9) + GENERATE_ENUM(SETNEs, 10) + GENERATE_ENUM(FRACs, 11) + GENERATE_ENUM(TRUNCs, 12) + GENERATE_ENUM(FLOORs, 13) + GENERATE_ENUM(EXP_IEEE, 14) + GENERATE_ENUM(LOG_CLAMP, 15) + GENERATE_ENUM(LOG_IEEE, 16) + GENERATE_ENUM(RECIP_CLAMP, 17) + GENERATE_ENUM(RECIP_FF, 18) + GENERATE_ENUM(RECIP_IEEE, 19) + GENERATE_ENUM(RECIPSQ_CLAMP, 20) + GENERATE_ENUM(RECIPSQ_FF, 21) + GENERATE_ENUM(RECIPSQ_IEEE, 22) + GENERATE_ENUM(MOVAs, 23) + GENERATE_ENUM(MOVA_FLOORs, 24) + GENERATE_ENUM(SUBs, 25) + GENERATE_ENUM(SUB_PREVs, 26) + GENERATE_ENUM(PRED_SETEs, 27) + GENERATE_ENUM(PRED_SETNEs, 28) + GENERATE_ENUM(PRED_SETGTs, 29) + GENERATE_ENUM(PRED_SETGTEs, 30) + GENERATE_ENUM(PRED_SET_INVs, 31) + GENERATE_ENUM(PRED_SET_POPs, 32) + GENERATE_ENUM(PRED_SET_CLRs, 33) + GENERATE_ENUM(PRED_SET_RESTOREs, 34) + GENERATE_ENUM(KILLEs, 35) + GENERATE_ENUM(KILLGTs, 36) + GENERATE_ENUM(KILLGTEs, 37) + GENERATE_ENUM(KILLNEs, 38) + GENERATE_ENUM(KILLONEs, 39) + GENERATE_ENUM(SQRT_IEEE, 40) + GENERATE_ENUM(MUL_CONST_0, 42) + GENERATE_ENUM(MUL_CONST_1, 43) + GENERATE_ENUM(ADD_CONST_0, 44) + GENERATE_ENUM(ADD_CONST_1, 45) + GENERATE_ENUM(SUB_CONST_0, 46) + GENERATE_ENUM(SUB_CONST_1, 47) + GENERATE_ENUM(SIN, 48) + GENERATE_ENUM(COS, 49) + GENERATE_ENUM(RETAIN_PREV, 50) +END_ENUMTYPE(ScalarOpcode) + +START_ENUMTYPE(SwizzleType) + GENERATE_ENUM(NO_SWIZZLE, 0) + GENERATE_ENUM(SHIFT_RIGHT_1, 1) + GENERATE_ENUM(SHIFT_RIGHT_2, 2) + GENERATE_ENUM(SHIFT_RIGHT_3, 3) +END_ENUMTYPE(SwizzleType) + +START_ENUMTYPE(InputModifier) + GENERATE_ENUM(NIL, 0) + GENERATE_ENUM(NEGATE, 1) +END_ENUMTYPE(InputModifier) + +START_ENUMTYPE(PredicateSelect) + GENERATE_ENUM(NO_PREDICATION, 0) + GENERATE_ENUM(PREDICATE_QUAD, 1) + GENERATE_ENUM(PREDICATED_2, 2) + GENERATE_ENUM(PREDICATED_3, 3) +END_ENUMTYPE(PredicateSelect) + +START_ENUMTYPE(OperandSelect1) + GENERATE_ENUM(ABSOLUTE_REG, 0) + GENERATE_ENUM(RELATIVE_REG, 1) +END_ENUMTYPE(OperandSelect1) + +START_ENUMTYPE(VectorOpcode) + GENERATE_ENUM(ADDv, 0) + GENERATE_ENUM(MULv, 1) + GENERATE_ENUM(MAXv, 2) + GENERATE_ENUM(MINv, 3) + GENERATE_ENUM(SETEv, 4) + GENERATE_ENUM(SETGTv, 5) + GENERATE_ENUM(SETGTEv, 6) + GENERATE_ENUM(SETNEv, 7) + GENERATE_ENUM(FRACv, 8) + GENERATE_ENUM(TRUNCv, 9) + GENERATE_ENUM(FLOORv, 10) + GENERATE_ENUM(MULADDv, 11) + GENERATE_ENUM(CNDEv, 12) + GENERATE_ENUM(CNDGTEv, 13) + GENERATE_ENUM(CNDGTv, 14) + GENERATE_ENUM(DOT4v, 15) + GENERATE_ENUM(DOT3v, 16) + GENERATE_ENUM(DOT2ADDv, 17) + GENERATE_ENUM(CUBEv, 18) + GENERATE_ENUM(MAX4v, 19) + GENERATE_ENUM(PRED_SETE_PUSHv, 20) + GENERATE_ENUM(PRED_SETNE_PUSHv, 21) + GENERATE_ENUM(PRED_SETGT_PUSHv, 22) + GENERATE_ENUM(PRED_SETGTE_PUSHv, 23) + GENERATE_ENUM(KILLEv, 24) + GENERATE_ENUM(KILLGTv, 25) + GENERATE_ENUM(KILLGTEv, 26) + GENERATE_ENUM(KILLNEv, 27) + GENERATE_ENUM(DSTv, 28) + GENERATE_ENUM(MOVAv, 29) +END_ENUMTYPE(VectorOpcode) + +START_ENUMTYPE(OperandSelect0) + GENERATE_ENUM(CONSTANT, 0) + GENERATE_ENUM(NON_CONSTANT, 1) +END_ENUMTYPE(OperandSelect0) + +START_ENUMTYPE(Ressource_type) + GENERATE_ENUM(ALU, 0) + GENERATE_ENUM(TEXTURE, 1) +END_ENUMTYPE(Ressource_type) + +START_ENUMTYPE(Instruction_serial) + GENERATE_ENUM(NOT_SERIAL, 0) + GENERATE_ENUM(SERIAL, 1) +END_ENUMTYPE(Instruction_serial) + +START_ENUMTYPE(VC_type) + GENERATE_ENUM(ALU_TP_REQUEST, 0) + GENERATE_ENUM(VC_REQUEST, 1) +END_ENUMTYPE(VC_type) + +START_ENUMTYPE(Addressing) + GENERATE_ENUM(RELATIVE_ADDR, 0) + GENERATE_ENUM(ABSOLUTE_ADDR, 1) +END_ENUMTYPE(Addressing) + +START_ENUMTYPE(CFOpcode) + GENERATE_ENUM(NOP, 0) + GENERATE_ENUM(EXECUTE, 1) + GENERATE_ENUM(EXECUTE_END, 2) + GENERATE_ENUM(COND_EXECUTE, 3) + GENERATE_ENUM(COND_EXECUTE_END, 4) + GENERATE_ENUM(COND_PRED_EXECUTE, 5) + GENERATE_ENUM(COND_PRED_EXECUTE_END, 6) + GENERATE_ENUM(LOOP_START, 7) + GENERATE_ENUM(LOOP_END, 8) + GENERATE_ENUM(COND_CALL, 9) + GENERATE_ENUM(RETURN, 10) + GENERATE_ENUM(COND_JMP, 11) + GENERATE_ENUM(ALLOCATE, 12) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14) + GENERATE_ENUM(MARK_VS_FETCH_DONE, 15) +END_ENUMTYPE(CFOpcode) + +START_ENUMTYPE(Allocation_type) + GENERATE_ENUM(SQ_NO_ALLOC, 0) + GENERATE_ENUM(SQ_POSITION, 1) + GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2) + GENERATE_ENUM(SQ_MEMORY, 3) +END_ENUMTYPE(Allocation_type) + +START_ENUMTYPE(TexInstOpcode) + GENERATE_ENUM(TEX_INST_FETCH, 1) + GENERATE_ENUM(TEX_INST_RESERVED_1, 2) + GENERATE_ENUM(TEX_INST_RESERVED_2, 3) + GENERATE_ENUM(TEX_INST_RESERVED_3, 4) + GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16) + GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17) + GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18) + GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19) + GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26) + GENERATE_ENUM(TEX_INST_RESERVED_4, 27) +END_ENUMTYPE(TexInstOpcode) + +START_ENUMTYPE(Addressmode) + GENERATE_ENUM(LOGICAL, 0) + GENERATE_ENUM(LOOP_RELATIVE, 1) +END_ENUMTYPE(Addressmode) + +START_ENUMTYPE(TexCoordDenorm) + GENERATE_ENUM(TEX_COORD_NORMALIZED, 0) + GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1) +END_ENUMTYPE(TexCoordDenorm) + +START_ENUMTYPE(SrcSel) + GENERATE_ENUM(SRC_SEL_X, 0) + GENERATE_ENUM(SRC_SEL_Y, 1) + GENERATE_ENUM(SRC_SEL_Z, 2) + GENERATE_ENUM(SRC_SEL_W, 3) +END_ENUMTYPE(SrcSel) + +START_ENUMTYPE(DstSel) + GENERATE_ENUM(DST_SEL_X, 0) + GENERATE_ENUM(DST_SEL_Y, 1) + GENERATE_ENUM(DST_SEL_Z, 2) + GENERATE_ENUM(DST_SEL_W, 3) + GENERATE_ENUM(DST_SEL_0, 4) + GENERATE_ENUM(DST_SEL_1, 5) + GENERATE_ENUM(DST_SEL_RSVD, 6) + GENERATE_ENUM(DST_SEL_MASK, 7) +END_ENUMTYPE(DstSel) + +START_ENUMTYPE(MagFilter) + GENERATE_ENUM(MAG_FILTER_POINT, 0) + GENERATE_ENUM(MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MagFilter) + +START_ENUMTYPE(MinFilter) + GENERATE_ENUM(MIN_FILTER_POINT, 0) + GENERATE_ENUM(MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MinFilter) + +START_ENUMTYPE(MipFilter) + GENERATE_ENUM(MIP_FILTER_POINT, 0) + GENERATE_ENUM(MIP_FILTER_LINEAR, 1) + GENERATE_ENUM(MIP_FILTER_BASEMAP, 2) + GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MipFilter) + +START_ENUMTYPE(AnisoFilter) + GENERATE_ENUM(ANISO_FILTER_DISABLED, 0) + GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1) + GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2) + GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3) + GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4) + GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5) + GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(AnisoFilter) + +START_ENUMTYPE(ArbitraryFilter) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5) + GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(ArbitraryFilter) + +START_ENUMTYPE(VolMagFilter) + GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMagFilter) + +START_ENUMTYPE(VolMinFilter) + GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMinFilter) + +START_ENUMTYPE(PredSelect) + GENERATE_ENUM(NOT_PREDICATED, 0) + GENERATE_ENUM(PREDICATED, 1) +END_ENUMTYPE(PredSelect) + +START_ENUMTYPE(SampleLocation) + GENERATE_ENUM(SAMPLE_CENTROID, 0) + GENERATE_ENUM(SAMPLE_CENTER, 1) +END_ENUMTYPE(SampleLocation) + +START_ENUMTYPE(VertexMode) + GENERATE_ENUM(POSITION_1_VECTOR, 0) + GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3) + GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6) + GENERATE_ENUM(MULTIPASS, 7) +END_ENUMTYPE(VertexMode) + +START_ENUMTYPE(Sample_Cntl) + GENERATE_ENUM(CENTROIDS_ONLY, 0) + GENERATE_ENUM(CENTERS_ONLY, 1) + GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2) + GENERATE_ENUM(UNDEF, 3) +END_ENUMTYPE(Sample_Cntl) + +START_ENUMTYPE(MhPerfEncode) + GENERATE_ENUM(CP_R0_REQUESTS, 0) + GENERATE_ENUM(CP_R1_REQUESTS, 1) + GENERATE_ENUM(CP_R2_REQUESTS, 2) + GENERATE_ENUM(CP_R3_REQUESTS, 3) + GENERATE_ENUM(CP_R4_REQUESTS, 4) + GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5) + GENERATE_ENUM(CP_W_REQUESTS, 6) + GENERATE_ENUM(CP_TOTAL_REQUESTS, 7) + GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8) + GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9) + GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10) + GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11) + GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12) + GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13) + GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14) + GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15) + GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16) + GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17) + GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18) + GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19) + GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20) + GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21) + GENERATE_ENUM(VGT_R0_REQUESTS, 22) + GENERATE_ENUM(VGT_R1_REQUESTS, 23) + GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24) + GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25) + GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26) + GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27) + GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28) + GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29) + GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30) + GENERATE_ENUM(TC_REQUESTS, 31) + GENERATE_ENUM(TC_ROQ_REQUESTS, 32) + GENERATE_ENUM(TC_INFO_SENT, 33) + GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34) + GENERATE_ENUM(TC_DATA_BEATS_READ, 35) + GENERATE_ENUM(TCD_BURSTS_READ, 36) + GENERATE_ENUM(RB_REQUESTS, 37) + GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38) + GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47) + GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56) + GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65) + GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111) + GENERATE_ENUM(TOTAL_MMU_MISSES, 112) + GENERATE_ENUM(MMU_READ_MISSES, 113) + GENERATE_ENUM(MMU_WRITE_MISSES, 114) + GENERATE_ENUM(TOTAL_MMU_HITS, 115) + GENERATE_ENUM(MMU_READ_HITS, 116) + GENERATE_ENUM(MMU_WRITE_HITS, 117) + GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118) + GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119) + GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120) + GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121) + GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122) + GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123) + GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124) + GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125) + GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126) + GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127) + GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128) + GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129) + GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130) + GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131) + GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132) + GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133) + GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136) + GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140) + GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148) + GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149) + GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150) + GENERATE_ENUM(TOTAL_MH_REQUESTS, 151) + GENERATE_ENUM(MH_BUSY, 152) + GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153) + GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154) + GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155) + GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156) + GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157) + GENERATE_ENUM(ARQ_N_ENTRIES, 158) + GENERATE_ENUM(WDB_N_ENTRIES, 159) + GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160) + GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161) + GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162) + GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163) +END_ENUMTYPE(MhPerfEncode) + +START_ENUMTYPE(MmuClntBeh) + GENERATE_ENUM(BEH_NEVR, 0) + GENERATE_ENUM(BEH_TRAN_RNG, 1) + GENERATE_ENUM(BEH_TRAN_FLT, 2) +END_ENUMTYPE(MmuClntBeh) + +START_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + GENERATE_ENUM(RBBM1_COUNT, 0) + GENERATE_ENUM(RBBM1_NRT_BUSY, 1) + GENERATE_ENUM(RBBM1_RB_BUSY, 2) + GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3) + GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4) + GENERATE_ENUM(RBBM1_VGT_BUSY, 5) + GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6) + GENERATE_ENUM(RBBM1_PA_BUSY, 7) + GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8) + GENERATE_ENUM(RBBM1_TPC_BUSY, 9) + GENERATE_ENUM(RBBM1_TC_BUSY, 10) + GENERATE_ENUM(RBBM1_SX_BUSY, 11) + GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12) + GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13) + GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14) + GENERATE_ENUM(RBBM1_INTERRUPT, 15) +END_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + +START_ENUMTYPE(CP_PERFCOUNT_SEL) + GENERATE_ENUM(ALWAYS_COUNT, 0) + GENERATE_ENUM(TRANS_FIFO_FULL, 1) + GENERATE_ENUM(TRANS_FIFO_AF, 2) + GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3) + GENERATE_ENUM(Reserved_04, 4) + GENERATE_ENUM(Reserved_05, 5) + GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6) + GENERATE_ENUM(Reserved_07, 7) + GENERATE_ENUM(CSF_NRT_READ_WAIT, 8) + GENERATE_ENUM(CSF_I1_FIFO_FULL, 9) + GENERATE_ENUM(CSF_I2_FIFO_FULL, 10) + GENERATE_ENUM(CSF_ST_FIFO_FULL, 11) + GENERATE_ENUM(Reserved_12, 12) + GENERATE_ENUM(CSF_RING_ROQ_FULL, 13) + GENERATE_ENUM(CSF_I1_ROQ_FULL, 14) + GENERATE_ENUM(CSF_I2_ROQ_FULL, 15) + GENERATE_ENUM(CSF_ST_ROQ_FULL, 16) + GENERATE_ENUM(Reserved_17, 17) + GENERATE_ENUM(MIU_TAG_MEM_FULL, 18) + GENERATE_ENUM(MIU_WRITECLEAN, 19) + GENERATE_ENUM(Reserved_20, 20) + GENERATE_ENUM(Reserved_21, 21) + GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22) + GENERATE_ENUM(MIU_NRT_READ_STALLED, 23) + GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24) + GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25) + GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26) + GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27) + GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28) + GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29) + GENERATE_ENUM(ME_MICRO_RB_STARVED, 30) + GENERATE_ENUM(ME_MICRO_I1_STARVED, 31) + GENERATE_ENUM(ME_MICRO_I2_STARVED, 32) + GENERATE_ENUM(ME_MICRO_ST_STARVED, 33) + GENERATE_ENUM(Reserved_34, 34) + GENERATE_ENUM(Reserved_35, 35) + GENERATE_ENUM(Reserved_36, 36) + GENERATE_ENUM(Reserved_37, 37) + GENERATE_ENUM(Reserved_38, 38) + GENERATE_ENUM(Reserved_39, 39) + GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40) + GENERATE_ENUM(ME_BUSY_CLOCKS, 41) + GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42) + GENERATE_ENUM(PFP_TYPE0_PACKET, 43) + GENERATE_ENUM(PFP_TYPE3_PACKET, 44) + GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45) + GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46) + GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47) + GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48) + GENERATE_ENUM(Reserved_49, 49) + GENERATE_ENUM(Reserved_50, 50) + GENERATE_ENUM(Reserved_51, 51) + GENERATE_ENUM(Reserved_52, 52) + GENERATE_ENUM(Reserved_53, 53) + GENERATE_ENUM(Reserved_54, 54) + GENERATE_ENUM(Reserved_55, 55) + GENERATE_ENUM(Reserved_56, 56) + GENERATE_ENUM(Reserved_57, 57) + GENERATE_ENUM(Reserved_58, 58) + GENERATE_ENUM(Reserved_59, 59) + GENERATE_ENUM(Reserved_60, 60) + GENERATE_ENUM(Reserved_61, 61) + GENERATE_ENUM(Reserved_62, 62) + GENERATE_ENUM(Reserved_63, 63) +END_ENUMTYPE(CP_PERFCOUNT_SEL) + +START_ENUMTYPE(ColorformatX) + GENERATE_ENUM(COLORX_4_4_4_4, 0) + GENERATE_ENUM(COLORX_1_5_5_5, 1) + GENERATE_ENUM(COLORX_5_6_5, 2) + GENERATE_ENUM(COLORX_8, 3) + GENERATE_ENUM(COLORX_8_8, 4) + GENERATE_ENUM(COLORX_8_8_8_8, 5) + GENERATE_ENUM(COLORX_S8_8_8_8, 6) + GENERATE_ENUM(COLORX_16_FLOAT, 7) + GENERATE_ENUM(COLORX_16_16_FLOAT, 8) + GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9) + GENERATE_ENUM(COLORX_32_FLOAT, 10) + GENERATE_ENUM(COLORX_32_32_FLOAT, 11) + GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12) + GENERATE_ENUM(COLORX_2_3_3, 13) + GENERATE_ENUM(COLORX_8_8_8, 14) +END_ENUMTYPE(ColorformatX) + +START_ENUMTYPE(DepthformatX) + GENERATE_ENUM(DEPTHX_16, 0) + GENERATE_ENUM(DEPTHX_24_8, 1) +END_ENUMTYPE(DepthformatX) + +START_ENUMTYPE(CompareFrag) + GENERATE_ENUM(FRAG_NEVER, 0) + GENERATE_ENUM(FRAG_LESS, 1) + GENERATE_ENUM(FRAG_EQUAL, 2) + GENERATE_ENUM(FRAG_LEQUAL, 3) + GENERATE_ENUM(FRAG_GREATER, 4) + GENERATE_ENUM(FRAG_NOTEQUAL, 5) + GENERATE_ENUM(FRAG_GEQUAL, 6) + GENERATE_ENUM(FRAG_ALWAYS, 7) +END_ENUMTYPE(CompareFrag) + +START_ENUMTYPE(CompareRef) + GENERATE_ENUM(REF_NEVER, 0) + GENERATE_ENUM(REF_LESS, 1) + GENERATE_ENUM(REF_EQUAL, 2) + GENERATE_ENUM(REF_LEQUAL, 3) + GENERATE_ENUM(REF_GREATER, 4) + GENERATE_ENUM(REF_NOTEQUAL, 5) + GENERATE_ENUM(REF_GEQUAL, 6) + GENERATE_ENUM(REF_ALWAYS, 7) +END_ENUMTYPE(CompareRef) + +START_ENUMTYPE(StencilOp) + GENERATE_ENUM(STENCIL_KEEP, 0) + GENERATE_ENUM(STENCIL_ZERO, 1) + GENERATE_ENUM(STENCIL_REPLACE, 2) + GENERATE_ENUM(STENCIL_INCR_CLAMP, 3) + GENERATE_ENUM(STENCIL_DECR_CLAMP, 4) + GENERATE_ENUM(STENCIL_INVERT, 5) + GENERATE_ENUM(STENCIL_INCR_WRAP, 6) + GENERATE_ENUM(STENCIL_DECR_WRAP, 7) +END_ENUMTYPE(StencilOp) + +START_ENUMTYPE(BlendOpX) + GENERATE_ENUM(BLENDX_ZERO, 0) + GENERATE_ENUM(BLENDX_ONE, 1) + GENERATE_ENUM(BLENDX_SRC_COLOR, 4) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5) + GENERATE_ENUM(BLENDX_SRC_ALPHA, 6) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7) + GENERATE_ENUM(BLENDX_DST_COLOR, 8) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9) + GENERATE_ENUM(BLENDX_DST_ALPHA, 10) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11) + GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13) + GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15) + GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16) +END_ENUMTYPE(BlendOpX) + +START_ENUMTYPE(CombFuncX) + GENERATE_ENUM(COMB_DST_PLUS_SRC, 0) + GENERATE_ENUM(COMB_SRC_MINUS_DST, 1) + GENERATE_ENUM(COMB_MIN_DST_SRC, 2) + GENERATE_ENUM(COMB_MAX_DST_SRC, 3) + GENERATE_ENUM(COMB_DST_MINUS_SRC, 4) + GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5) +END_ENUMTYPE(CombFuncX) + +START_ENUMTYPE(DitherModeX) + GENERATE_ENUM(DITHER_DISABLE, 0) + GENERATE_ENUM(DITHER_ALWAYS, 1) + GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2) +END_ENUMTYPE(DitherModeX) + +START_ENUMTYPE(DitherTypeX) + GENERATE_ENUM(DITHER_PIXEL, 0) + GENERATE_ENUM(DITHER_SUBPIXEL, 1) +END_ENUMTYPE(DitherTypeX) + +START_ENUMTYPE(EdramMode) + GENERATE_ENUM(EDRAM_NOP, 0) + GENERATE_ENUM(COLOR_DEPTH, 4) + GENERATE_ENUM(DEPTH_ONLY, 5) + GENERATE_ENUM(EDRAM_COPY, 6) +END_ENUMTYPE(EdramMode) + +START_ENUMTYPE(SurfaceEndian) + GENERATE_ENUM(ENDIAN_NONE, 0) + GENERATE_ENUM(ENDIAN_8IN16, 1) + GENERATE_ENUM(ENDIAN_8IN32, 2) + GENERATE_ENUM(ENDIAN_16IN32, 3) + GENERATE_ENUM(ENDIAN_8IN64, 4) + GENERATE_ENUM(ENDIAN_8IN128, 5) +END_ENUMTYPE(SurfaceEndian) + +START_ENUMTYPE(EdramSizeX) + GENERATE_ENUM(EDRAMSIZE_16KB, 0) + GENERATE_ENUM(EDRAMSIZE_32KB, 1) + GENERATE_ENUM(EDRAMSIZE_64KB, 2) + GENERATE_ENUM(EDRAMSIZE_128KB, 3) + GENERATE_ENUM(EDRAMSIZE_256KB, 4) + GENERATE_ENUM(EDRAMSIZE_512KB, 5) + GENERATE_ENUM(EDRAMSIZE_1MB, 6) + GENERATE_ENUM(EDRAMSIZE_2MB, 7) + GENERATE_ENUM(EDRAMSIZE_4MB, 8) + GENERATE_ENUM(EDRAMSIZE_8MB, 9) + GENERATE_ENUM(EDRAMSIZE_16MB, 10) +END_ENUMTYPE(EdramSizeX) + +START_ENUMTYPE(RB_PERFCNT_SELECT) + GENERATE_ENUM(RBPERF_CNTX_BUSY, 0) + GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7) + GENERATE_ENUM(RBPERF_MH_STARVED, 8) + GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23) + GENERATE_ENUM(RBPERF_ZXP_STALL, 24) + GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25) + GENERATE_ENUM(RBPERF_EVENT_PENDING, 26) + GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27) + GENERATE_ENUM(RBPERF_RB_MH_VALID, 28) + GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30) + GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31) + GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32) + GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33) + GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37) + GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38) + GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39) + GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40) + GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41) + GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42) + GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43) + GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44) + GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45) + GENERATE_ENUM(RBPERF_ZPASS_DONE, 46) + GENERATE_ENUM(RBPERF_ZCMD_VALID, 47) + GENERATE_ENUM(RBPERF_CCMD_VALID, 48) + GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49) + GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50) + GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51) + GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52) + GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53) + GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54) + GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55) + GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56) +END_ENUMTYPE(RB_PERFCNT_SELECT) + +START_ENUMTYPE(DepthFormat) + GENERATE_ENUM(DEPTH_24_8, 22) + GENERATE_ENUM(DEPTH_24_8_FLOAT, 23) + GENERATE_ENUM(DEPTH_16, 24) +END_ENUMTYPE(DepthFormat) + +START_ENUMTYPE(SurfaceSwap) + GENERATE_ENUM(SWAP_LOWRED, 0) + GENERATE_ENUM(SWAP_LOWBLUE, 1) +END_ENUMTYPE(SurfaceSwap) + +START_ENUMTYPE(DepthArray) + GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0) + GENERATE_ENUM(ARRAY_2D_DEPTH, 1) +END_ENUMTYPE(DepthArray) + +START_ENUMTYPE(ColorArray) + GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0) + GENERATE_ENUM(ARRAY_2D_COLOR, 1) + GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3) +END_ENUMTYPE(ColorArray) + +START_ENUMTYPE(ColorFormat) + GENERATE_ENUM(COLOR_8, 2) + GENERATE_ENUM(COLOR_1_5_5_5, 3) + GENERATE_ENUM(COLOR_5_6_5, 4) + GENERATE_ENUM(COLOR_6_5_5, 5) + GENERATE_ENUM(COLOR_8_8_8_8, 6) + GENERATE_ENUM(COLOR_2_10_10_10, 7) + GENERATE_ENUM(COLOR_8_A, 8) + GENERATE_ENUM(COLOR_8_B, 9) + GENERATE_ENUM(COLOR_8_8, 10) + GENERATE_ENUM(COLOR_8_8_8, 11) + GENERATE_ENUM(COLOR_8_8_8_8_A, 14) + GENERATE_ENUM(COLOR_4_4_4_4, 15) + GENERATE_ENUM(COLOR_10_11_11, 16) + GENERATE_ENUM(COLOR_11_11_10, 17) + GENERATE_ENUM(COLOR_16, 24) + GENERATE_ENUM(COLOR_16_16, 25) + GENERATE_ENUM(COLOR_16_16_16_16, 26) + GENERATE_ENUM(COLOR_16_FLOAT, 30) + GENERATE_ENUM(COLOR_16_16_FLOAT, 31) + GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(COLOR_32_FLOAT, 36) + GENERATE_ENUM(COLOR_32_32_FLOAT, 37) + GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(COLOR_2_3_3, 39) +END_ENUMTYPE(ColorFormat) + +START_ENUMTYPE(SurfaceNumber) + GENERATE_ENUM(NUMBER_UREPEAT, 0) + GENERATE_ENUM(NUMBER_SREPEAT, 1) + GENERATE_ENUM(NUMBER_UINTEGER, 2) + GENERATE_ENUM(NUMBER_SINTEGER, 3) + GENERATE_ENUM(NUMBER_GAMMA, 4) + GENERATE_ENUM(NUMBER_FIXED, 5) + GENERATE_ENUM(NUMBER_FLOAT, 7) +END_ENUMTYPE(SurfaceNumber) + +START_ENUMTYPE(SurfaceFormat) + GENERATE_ENUM(FMT_1_REVERSE, 0) + GENERATE_ENUM(FMT_1, 1) + GENERATE_ENUM(FMT_8, 2) + GENERATE_ENUM(FMT_1_5_5_5, 3) + GENERATE_ENUM(FMT_5_6_5, 4) + GENERATE_ENUM(FMT_6_5_5, 5) + GENERATE_ENUM(FMT_8_8_8_8, 6) + GENERATE_ENUM(FMT_2_10_10_10, 7) + GENERATE_ENUM(FMT_8_A, 8) + GENERATE_ENUM(FMT_8_B, 9) + GENERATE_ENUM(FMT_8_8, 10) + GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11) + GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12) + GENERATE_ENUM(FMT_5_5_5_1, 13) + GENERATE_ENUM(FMT_8_8_8_8_A, 14) + GENERATE_ENUM(FMT_4_4_4_4, 15) + GENERATE_ENUM(FMT_8_8_8, 16) + GENERATE_ENUM(FMT_DXT1, 18) + GENERATE_ENUM(FMT_DXT2_3, 19) + GENERATE_ENUM(FMT_DXT4_5, 20) + GENERATE_ENUM(FMT_10_10_10_2, 21) + GENERATE_ENUM(FMT_24_8, 22) + GENERATE_ENUM(FMT_16, 24) + GENERATE_ENUM(FMT_16_16, 25) + GENERATE_ENUM(FMT_16_16_16_16, 26) + GENERATE_ENUM(FMT_16_EXPAND, 27) + GENERATE_ENUM(FMT_16_16_EXPAND, 28) + GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29) + GENERATE_ENUM(FMT_16_FLOAT, 30) + GENERATE_ENUM(FMT_16_16_FLOAT, 31) + GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(FMT_32, 33) + GENERATE_ENUM(FMT_32_32, 34) + GENERATE_ENUM(FMT_32_32_32_32, 35) + GENERATE_ENUM(FMT_32_FLOAT, 36) + GENERATE_ENUM(FMT_32_32_FLOAT, 37) + GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(FMT_ATI_TC_RGB, 39) + GENERATE_ENUM(FMT_ATI_TC_RGBA, 40) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42) + GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44) + GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46) + GENERATE_ENUM(FMT_ETC1_RGB, 47) + GENERATE_ENUM(FMT_ETC1_RGBA, 48) + GENERATE_ENUM(FMT_DXN, 49) + GENERATE_ENUM(FMT_2_3_3, 51) + GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54) + GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55) + GENERATE_ENUM(FMT_32_32_32_FLOAT, 57) + GENERATE_ENUM(FMT_DXT3A, 58) + GENERATE_ENUM(FMT_DXT5A, 59) + GENERATE_ENUM(FMT_CTX1, 60) +END_ENUMTYPE(SurfaceFormat) + +START_ENUMTYPE(SurfaceTiling) + GENERATE_ENUM(ARRAY_LINEAR, 0) + GENERATE_ENUM(ARRAY_TILED, 1) +END_ENUMTYPE(SurfaceTiling) + +START_ENUMTYPE(SurfaceArray) + GENERATE_ENUM(ARRAY_1D, 0) + GENERATE_ENUM(ARRAY_2D, 1) + GENERATE_ENUM(ARRAY_3D, 2) + GENERATE_ENUM(ARRAY_3D_SLICE, 3) +END_ENUMTYPE(SurfaceArray) + +START_ENUMTYPE(SurfaceNumberX) + GENERATE_ENUM(NUMBERX_UREPEAT, 0) + GENERATE_ENUM(NUMBERX_SREPEAT, 1) + GENERATE_ENUM(NUMBERX_UINTEGER, 2) + GENERATE_ENUM(NUMBERX_SINTEGER, 3) + GENERATE_ENUM(NUMBERX_FLOAT, 7) +END_ENUMTYPE(SurfaceNumberX) + +START_ENUMTYPE(ColorArrayX) + GENERATE_ENUM(ARRAYX_2D_COLOR, 0) + GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1) +END_ENUMTYPE(ColorArrayX) + + + + +// ************************************************************************** +// These are ones that had to be added in addition to what's generated +// by the autoreg (in CSIM) +// ************************************************************************** +START_ENUMTYPE(DXClipSpaceDef) + GENERATE_ENUM(DXCLIP_OPENGL, 0) + GENERATE_ENUM(DXCLIP_DIRECTX, 1) +END_ENUMTYPE(DXClipSpaceDef) + +START_ENUMTYPE(PixCenter) + GENERATE_ENUM(PIXCENTER_D3D, 0) + GENERATE_ENUM(PIXCENTER_OGL, 1) +END_ENUMTYPE(PixCenter) + +START_ENUMTYPE(RoundMode) + GENERATE_ENUM(TRUNCATE, 0) + GENERATE_ENUM(ROUND, 1) + GENERATE_ENUM(ROUNDTOEVEN, 2) + GENERATE_ENUM(ROUNDTOODD, 3) +END_ENUMTYPE(RoundMode) + +START_ENUMTYPE(QuantMode) + GENERATE_ENUM(ONE_SIXTEENTH, 0) + GENERATE_ENUM(ONE_EIGHTH, 1) + GENERATE_ENUM(ONE_QUARTER, 2) + GENERATE_ENUM(ONE_HALF, 3) + GENERATE_ENUM(ONE, 4) +END_ENUMTYPE(QuantMode) + +START_ENUMTYPE(FrontFace) + GENERATE_ENUM(FRONT_CCW, 0) + GENERATE_ENUM(FRONT_CW, 1) +END_ENUMTYPE(FrontFace) + +START_ENUMTYPE(PolyMode) + GENERATE_ENUM(DISABLED, 0) + GENERATE_ENUM(DUALMODE, 1) +END_ENUMTYPE(PolyMode) + +START_ENUMTYPE(PType) + GENERATE_ENUM(DRAW_POINTS, 0) + GENERATE_ENUM(DRAW_LINES, 1) + GENERATE_ENUM(DRAW_TRIANGLES, 2) +END_ENUMTYPE(PType) + +START_ENUMTYPE(MSAANumSamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 3) +END_ENUMTYPE(MSAANumSamples) + +START_ENUMTYPE(PatternBitOrder) + GENERATE_ENUM(LITTLE, 0) + GENERATE_ENUM(BIG, 1) +END_ENUMTYPE(PatternBitOrder) + +START_ENUMTYPE(AutoResetCntl) + GENERATE_ENUM(NEVER, 0) + GENERATE_ENUM(EACHPRIMITIVE, 1) + GENERATE_ENUM(EACHPACKET, 2) +END_ENUMTYPE(AutoResetCntl) + +START_ENUMTYPE(ParamShade) + GENERATE_ENUM(FLAT, 0) + GENERATE_ENUM(GOURAUD, 1) +END_ENUMTYPE(ParamShade) + +START_ENUMTYPE(SamplingPattern) + GENERATE_ENUM(CENTROID, 0) + GENERATE_ENUM(PIXCENTER, 1) +END_ENUMTYPE(SamplingPattern) + +START_ENUMTYPE(MSAASamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 2) +END_ENUMTYPE(MSAASamples) + +START_ENUMTYPE(CopySampleSelect) + GENERATE_ENUM(SAMPLE_0, 0) + GENERATE_ENUM(SAMPLE_1, 1) + GENERATE_ENUM(SAMPLE_2, 2) + GENERATE_ENUM(SAMPLE_3, 3) + GENERATE_ENUM(SAMPLE_01, 4) + GENERATE_ENUM(SAMPLE_23, 5) + GENERATE_ENUM(SAMPLE_0123, 6) +END_ENUMTYPE(CopySampleSelect) + + +#undef START_ENUMTYPE +#undef GENERATE_ENUM +#undef END_ENUMTYPE diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h new file mode 100644 index 000000000000..d44be483e953 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h @@ -0,0 +1,3310 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_REGISTER(PA_CL_VPORT_XSCALE) + GENERATE_FIELD(VPORT_XSCALE, float) +END_REGISTER(PA_CL_VPORT_XSCALE) + +START_REGISTER(PA_CL_VPORT_XOFFSET) + GENERATE_FIELD(VPORT_XOFFSET, float) +END_REGISTER(PA_CL_VPORT_XOFFSET) + +START_REGISTER(PA_CL_VPORT_YSCALE) + GENERATE_FIELD(VPORT_YSCALE, float) +END_REGISTER(PA_CL_VPORT_YSCALE) + +START_REGISTER(PA_CL_VPORT_YOFFSET) + GENERATE_FIELD(VPORT_YOFFSET, float) +END_REGISTER(PA_CL_VPORT_YOFFSET) + +START_REGISTER(PA_CL_VPORT_ZSCALE) + GENERATE_FIELD(VPORT_ZSCALE, float) +END_REGISTER(PA_CL_VPORT_ZSCALE) + +START_REGISTER(PA_CL_VPORT_ZOFFSET) + GENERATE_FIELD(VPORT_ZOFFSET, float) +END_REGISTER(PA_CL_VPORT_ZOFFSET) + +START_REGISTER(PA_CL_VTE_CNTL) + GENERATE_FIELD(VPORT_X_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool) + GENERATE_FIELD(VTX_XY_FMT, bool) + GENERATE_FIELD(VTX_Z_FMT, bool) + GENERATE_FIELD(VTX_W0_FMT, bool) + GENERATE_FIELD(PERFCOUNTER_REF, bool) +END_REGISTER(PA_CL_VTE_CNTL) + +START_REGISTER(PA_CL_CLIP_CNTL) + GENERATE_FIELD(CLIP_DISABLE, bool) + GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool) + GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef) + GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool) + GENERATE_FIELD(VTX_KILL_OR, bool) + GENERATE_FIELD(XY_NAN_RETAIN, bool) + GENERATE_FIELD(Z_NAN_RETAIN, bool) + GENERATE_FIELD(W_NAN_RETAIN, bool) +END_REGISTER(PA_CL_CLIP_CNTL) + +START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + +START_REGISTER(PA_CL_ENHANCE) + GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_CL_ENHANCE) + +START_REGISTER(PA_SC_ENHANCE) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_SC_ENHANCE) + +START_REGISTER(PA_SU_VTX_CNTL) + GENERATE_FIELD(PIX_CENTER, PixCenter) + GENERATE_FIELD(ROUND_MODE, RoundMode) + GENERATE_FIELD(QUANT_MODE, QuantMode) +END_REGISTER(PA_SU_VTX_CNTL) + +START_REGISTER(PA_SU_POINT_SIZE) + GENERATE_FIELD(HEIGHT, fixed12_4) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_POINT_SIZE) + +START_REGISTER(PA_SU_POINT_MINMAX) + GENERATE_FIELD(MIN_SIZE, fixed12_4) + GENERATE_FIELD(MAX_SIZE, fixed12_4) +END_REGISTER(PA_SU_POINT_MINMAX) + +START_REGISTER(PA_SU_LINE_CNTL) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_LINE_CNTL) + +START_REGISTER(PA_SU_SC_MODE_CNTL) + GENERATE_FIELD(CULL_FRONT, bool) + GENERATE_FIELD(CULL_BACK, bool) + GENERATE_FIELD(FACE, FrontFace) + GENERATE_FIELD(POLY_MODE, PolyMode) + GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType) + GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType) + GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool) + GENERATE_FIELD(MSAA_ENABLE, bool) + GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool) + GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool) + GENERATE_FIELD(PROVOKING_VTX_LAST, bool) + GENERATE_FIELD(PERSP_CORR_DIS, bool) + GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool) + GENERATE_FIELD(QUAD_ORDER_ENABLE, bool) + GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool) + GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool) +END_REGISTER(PA_SU_SC_MODE_CNTL) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + +START_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT) +END_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_HI) + +START_REGISTER(PA_SU_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_HI) + +START_REGISTER(PA_SU_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_HI) + +START_REGISTER(PA_SU_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_HI) + +START_REGISTER(PA_SC_WINDOW_OFFSET) + GENERATE_FIELD(WINDOW_X_OFFSET, signedint15) + GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15) +END_REGISTER(PA_SC_WINDOW_OFFSET) + +START_REGISTER(PA_SC_AA_CONFIG) + GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples) + GENERATE_FIELD(MAX_SAMPLE_DIST, int) +END_REGISTER(PA_SC_AA_CONFIG) + +START_REGISTER(PA_SC_AA_MASK) + GENERATE_FIELD(AA_MASK, hex) +END_REGISTER(PA_SC_AA_MASK) + +START_REGISTER(PA_SC_LINE_STIPPLE) + GENERATE_FIELD(LINE_PATTERN, hex) + GENERATE_FIELD(REPEAT_COUNT, intMinusOne) + GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder) + GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl) +END_REGISTER(PA_SC_LINE_STIPPLE) + +START_REGISTER(PA_SC_LINE_CNTL) + GENERATE_FIELD(BRES_CNTL, int) + GENERATE_FIELD(USE_BRES_CNTL, bool) + GENERATE_FIELD(EXPAND_LINE_WIDTH, bool) + GENERATE_FIELD(LAST_PIXEL, bool) +END_REGISTER(PA_SC_LINE_CNTL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool) +END_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + +START_REGISTER(PA_SC_VIZ_QUERY) + GENERATE_FIELD(VIZ_QUERY_ENA, bool) + GENERATE_FIELD(VIZ_QUERY_ID, int) + GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool) +END_REGISTER(PA_SC_VIZ_QUERY) + +START_REGISTER(PA_SC_VIZ_QUERY_STATUS) + GENERATE_FIELD(STATUS_BITS, hex) +END_REGISTER(PA_SC_VIZ_QUERY_STATUS) + +START_REGISTER(PA_SC_LINE_STIPPLE_STATE) + GENERATE_FIELD(CURRENT_PTR, int) + GENERATE_FIELD(CURRENT_COUNT, int) +END_REGISTER(PA_SC_LINE_STIPPLE_STATE) + +START_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT) +END_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SC_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SC_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_HI) + +START_REGISTER(PA_CL_CNTL_STATUS) + GENERATE_FIELD(CL_BUSY, int) +END_REGISTER(PA_CL_CNTL_STATUS) + +START_REGISTER(PA_SU_CNTL_STATUS) + GENERATE_FIELD(SU_BUSY, int) +END_REGISTER(PA_SU_CNTL_STATUS) + +START_REGISTER(PA_SC_CNTL_STATUS) + GENERATE_FIELD(SC_BUSY, int) +END_REGISTER(PA_SC_CNTL_STATUS) + +START_REGISTER(PA_SU_DEBUG_CNTL) + GENERATE_FIELD(SU_DEBUG_INDX, int) +END_REGISTER(PA_SU_DEBUG_CNTL) + +START_REGISTER(PA_SU_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(PA_SU_DEBUG_DATA) + +START_REGISTER(PA_SC_DEBUG_CNTL) + GENERATE_FIELD(SC_DEBUG_INDX, int) +END_REGISTER(PA_SC_DEBUG_CNTL) + +START_REGISTER(PA_SC_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(PA_SC_DEBUG_DATA) + +START_REGISTER(GFX_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(GFX_COPY_STATE) + +START_REGISTER(VGT_DRAW_INITIATOR) + GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE) + GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT) + GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE) + GENERATE_FIELD(NOT_EOP, bool) + GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX) + GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE) + GENERATE_FIELD(NUM_INDICES, uint) +END_REGISTER(VGT_DRAW_INITIATOR) + +START_REGISTER(VGT_EVENT_INITIATOR) + GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE) +END_REGISTER(VGT_EVENT_INITIATOR) + +START_REGISTER(VGT_DMA_BASE) + GENERATE_FIELD(BASE_ADDR, uint) +END_REGISTER(VGT_DMA_BASE) + +START_REGISTER(VGT_DMA_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) + GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE) +END_REGISTER(VGT_DMA_SIZE) + +START_REGISTER(VGT_BIN_BASE) + GENERATE_FIELD(BIN_BASE_ADDR, uint) +END_REGISTER(VGT_BIN_BASE) + +START_REGISTER(VGT_BIN_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) +END_REGISTER(VGT_BIN_SIZE) + +START_REGISTER(VGT_CURRENT_BIN_ID_MIN) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MIN) + +START_REGISTER(VGT_CURRENT_BIN_ID_MAX) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MAX) + +START_REGISTER(VGT_IMMED_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_IMMED_DATA) + +START_REGISTER(VGT_MAX_VTX_INDX) + GENERATE_FIELD(MAX_INDX, int) +END_REGISTER(VGT_MAX_VTX_INDX) + +START_REGISTER(VGT_MIN_VTX_INDX) + GENERATE_FIELD(MIN_INDX, int) +END_REGISTER(VGT_MIN_VTX_INDX) + +START_REGISTER(VGT_INDX_OFFSET) + GENERATE_FIELD(INDX_OFFSET, int) +END_REGISTER(VGT_INDX_OFFSET) + +START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + GENERATE_FIELD(VTX_REUSE_DEPTH, int) +END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + +START_REGISTER(VGT_OUT_DEALLOC_CNTL) + GENERATE_FIELD(DEALLOC_DIST, int) +END_REGISTER(VGT_OUT_DEALLOC_CNTL) + +START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + GENERATE_FIELD(RESET_INDX, int) +END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + +START_REGISTER(VGT_ENHANCE) + GENERATE_FIELD(MISC, hex) +END_REGISTER(VGT_ENHANCE) + +START_REGISTER(VGT_VTX_VECT_EJECT_REG) + GENERATE_FIELD(PRIM_COUNT, int) +END_REGISTER(VGT_VTX_VECT_EJECT_REG) + +START_REGISTER(VGT_LAST_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) + GENERATE_FIELD(DST_STATE_ID, int) +END_REGISTER(VGT_LAST_COPY_STATE) + +START_REGISTER(VGT_DEBUG_CNTL) + GENERATE_FIELD(VGT_DEBUG_INDX, int) +END_REGISTER(VGT_DEBUG_CNTL) + +START_REGISTER(VGT_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_DEBUG_DATA) + +START_REGISTER(VGT_CNTL_STATUS) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(VGT_DMA_BUSY, int) + GENERATE_FIELD(VGT_DMA_REQ_BUSY, int) + GENERATE_FIELD(VGT_GRP_BUSY, int) + GENERATE_FIELD(VGT_VR_BUSY, int) + GENERATE_FIELD(VGT_BIN_BUSY, int) + GENERATE_FIELD(VGT_PT_BUSY, int) + GENERATE_FIELD(VGT_OUT_BUSY, int) + GENERATE_FIELD(VGT_OUT_INDX_BUSY, int) +END_REGISTER(VGT_CNTL_STATUS) + +START_REGISTER(VGT_CRC_SQ_DATA) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_DATA) + +START_REGISTER(VGT_CRC_SQ_CTRL) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_CTRL) + +START_REGISTER(VGT_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER0_SELECT) + +START_REGISTER(VGT_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER1_SELECT) + +START_REGISTER(VGT_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER2_SELECT) + +START_REGISTER(VGT_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER3_SELECT) + +START_REGISTER(VGT_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_LOW) + +START_REGISTER(VGT_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_LOW) + +START_REGISTER(VGT_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_LOW) + +START_REGISTER(VGT_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_LOW) + +START_REGISTER(VGT_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_HI) + +START_REGISTER(VGT_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_HI) + +START_REGISTER(VGT_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_HI) + +START_REGISTER(VGT_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_HI) + +START_REGISTER(TC_CNTL_STATUS) + GENERATE_FIELD(L2_INVALIDATE, int) + GENERATE_FIELD(TC_L2_HIT_MISS, int) + GENERATE_FIELD(TC_BUSY, int) +END_REGISTER(TC_CNTL_STATUS) + +START_REGISTER(TCR_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCR_CHICKEN) + +START_REGISTER(TCF_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCF_CHICKEN) + +START_REGISTER(TCM_CHICKEN) + GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int) + GENERATE_FIELD(ETC_COLOR_ENDIAN, int) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCM_CHICKEN) + +START_REGISTER(TCR_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER0_SELECT) + +START_REGISTER(TCR_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER1_SELECT) + +START_REGISTER(TCR_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER0_HI) + +START_REGISTER(TCR_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER1_HI) + +START_REGISTER(TCR_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER0_LOW) + +START_REGISTER(TCR_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER1_LOW) + +START_REGISTER(TP_TC_CLKGATE_CNTL) + GENERATE_FIELD(TP_BUSY_EXTEND, int) + GENERATE_FIELD(TC_BUSY_EXTEND, int) +END_REGISTER(TP_TC_CLKGATE_CNTL) + +START_REGISTER(TPC_CNTL_STATUS) + GENERATE_FIELD(TPC_INPUT_BUSY, int) + GENERATE_FIELD(TPC_TC_FIFO_BUSY, int) + GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int) + GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_BUSY, int) + GENERATE_FIELD(TPC_RR_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int) + GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_BUSY, int) + GENERATE_FIELD(TF_TW_RTS, int) + GENERATE_FIELD(TF_TW_STATE_RTS, int) + GENERATE_FIELD(TF_TW_RTR, int) + GENERATE_FIELD(TW_TA_RTS, int) + GENERATE_FIELD(TW_TA_TT_RTS, int) + GENERATE_FIELD(TW_TA_LAST_RTS, int) + GENERATE_FIELD(TW_TA_RTR, int) + GENERATE_FIELD(TA_TB_RTS, int) + GENERATE_FIELD(TA_TB_TT_RTS, int) + GENERATE_FIELD(TA_TB_RTR, int) + GENERATE_FIELD(TA_TF_RTS, int) + GENERATE_FIELD(TA_TF_TC_FIFO_REN, int) + GENERATE_FIELD(TP_SQ_DEC, int) + GENERATE_FIELD(TPC_BUSY, int) +END_REGISTER(TPC_CNTL_STATUS) + +START_REGISTER(TPC_DEBUG0) + GENERATE_FIELD(LOD_CNTL, int) + GENERATE_FIELD(IC_CTR, int) + GENERATE_FIELD(WALKER_CNTL, int) + GENERATE_FIELD(ALIGNER_CNTL, int) + GENERATE_FIELD(PREV_TC_STATE_VALID, int) + GENERATE_FIELD(WALKER_STATE, int) + GENERATE_FIELD(ALIGNER_STATE, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(TPC_CLK_EN, int) + GENERATE_FIELD(SQ_TP_WAKEUP, int) +END_REGISTER(TPC_DEBUG0) + +START_REGISTER(TPC_DEBUG1) + GENERATE_FIELD(UNUSED, int) +END_REGISTER(TPC_DEBUG1) + +START_REGISTER(TPC_CHICKEN) + GENERATE_FIELD(BLEND_PRECISION, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TPC_CHICKEN) + +START_REGISTER(TP0_CNTL_STATUS) + GENERATE_FIELD(TP_INPUT_BUSY, int) + GENERATE_FIELD(TP_LOD_BUSY, int) + GENERATE_FIELD(TP_LOD_FIFO_BUSY, int) + GENERATE_FIELD(TP_ADDR_BUSY, int) + GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TP_ALIGNER_BUSY, int) + GENERATE_FIELD(TP_TC_FIFO_BUSY, int) + GENERATE_FIELD(TP_RR_FIFO_BUSY, int) + GENERATE_FIELD(TP_FETCH_BUSY, int) + GENERATE_FIELD(TP_CH_BLEND_BUSY, int) + GENERATE_FIELD(TP_TT_BUSY, int) + GENERATE_FIELD(TP_HICOLOR_BUSY, int) + GENERATE_FIELD(TP_BLEND_BUSY, int) + GENERATE_FIELD(TP_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TP_OUTPUT_BUSY, int) + GENERATE_FIELD(IN_LC_RTS, int) + GENERATE_FIELD(LC_LA_RTS, int) + GENERATE_FIELD(LA_FL_RTS, int) + GENERATE_FIELD(FL_TA_RTS, int) + GENERATE_FIELD(TA_FA_RTS, int) + GENERATE_FIELD(TA_FA_TT_RTS, int) + GENERATE_FIELD(FA_AL_RTS, int) + GENERATE_FIELD(FA_AL_TT_RTS, int) + GENERATE_FIELD(AL_TF_RTS, int) + GENERATE_FIELD(AL_TF_TT_RTS, int) + GENERATE_FIELD(TF_TB_RTS, int) + GENERATE_FIELD(TF_TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_TT_RESET, int) + GENERATE_FIELD(TB_TO_RTS, int) + GENERATE_FIELD(TP_BUSY, int) +END_REGISTER(TP0_CNTL_STATUS) + +START_REGISTER(TP0_DEBUG) + GENERATE_FIELD(Q_LOD_CNTL, int) + GENERATE_FIELD(Q_SQ_TP_WAKEUP, int) + GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(PERF_CLK_EN, int) + GENERATE_FIELD(TP_CLK_EN, int) + GENERATE_FIELD(Q_WALKER_CNTL, int) + GENERATE_FIELD(Q_ALIGNER_CNTL, int) +END_REGISTER(TP0_DEBUG) + +START_REGISTER(TP0_CHICKEN) + GENERATE_FIELD(TT_MODE, int) + GENERATE_FIELD(VFETCH_ADDRESS_MODE, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TP0_CHICKEN) + +START_REGISTER(TP0_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT) +END_REGISTER(TP0_PERFCOUNTER0_SELECT) + +START_REGISTER(TP0_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER0_HI) + +START_REGISTER(TP0_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER0_LOW) + +START_REGISTER(TP0_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, int) +END_REGISTER(TP0_PERFCOUNTER1_SELECT) + +START_REGISTER(TP0_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER1_HI) + +START_REGISTER(TP0_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER1_LOW) + +START_REGISTER(TCM_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER0_SELECT) + +START_REGISTER(TCM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER1_SELECT) + +START_REGISTER(TCM_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER0_HI) + +START_REGISTER(TCM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER1_HI) + +START_REGISTER(TCM_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER0_LOW) + +START_REGISTER(TCM_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER0_SELECT) + +START_REGISTER(TCF_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER1_SELECT) + +START_REGISTER(TCF_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER2_SELECT) + +START_REGISTER(TCF_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER3_SELECT) + +START_REGISTER(TCF_PERFCOUNTER4_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER4_SELECT) + +START_REGISTER(TCF_PERFCOUNTER5_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER5_SELECT) + +START_REGISTER(TCF_PERFCOUNTER6_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER6_SELECT) + +START_REGISTER(TCF_PERFCOUNTER7_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER7_SELECT) + +START_REGISTER(TCF_PERFCOUNTER8_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER8_SELECT) + +START_REGISTER(TCF_PERFCOUNTER9_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER9_SELECT) + +START_REGISTER(TCF_PERFCOUNTER10_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER10_SELECT) + +START_REGISTER(TCF_PERFCOUNTER11_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER11_SELECT) + +START_REGISTER(TCF_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER0_HI) + +START_REGISTER(TCF_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER1_HI) + +START_REGISTER(TCF_PERFCOUNTER2_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER2_HI) + +START_REGISTER(TCF_PERFCOUNTER3_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER3_HI) + +START_REGISTER(TCF_PERFCOUNTER4_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER4_HI) + +START_REGISTER(TCF_PERFCOUNTER5_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER5_HI) + +START_REGISTER(TCF_PERFCOUNTER6_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER6_HI) + +START_REGISTER(TCF_PERFCOUNTER7_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER7_HI) + +START_REGISTER(TCF_PERFCOUNTER8_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER8_HI) + +START_REGISTER(TCF_PERFCOUNTER9_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER9_HI) + +START_REGISTER(TCF_PERFCOUNTER10_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER10_HI) + +START_REGISTER(TCF_PERFCOUNTER11_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER11_HI) + +START_REGISTER(TCF_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER0_LOW) + +START_REGISTER(TCF_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER2_LOW) + +START_REGISTER(TCF_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER3_LOW) + +START_REGISTER(TCF_PERFCOUNTER4_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER4_LOW) + +START_REGISTER(TCF_PERFCOUNTER5_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER5_LOW) + +START_REGISTER(TCF_PERFCOUNTER6_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER6_LOW) + +START_REGISTER(TCF_PERFCOUNTER7_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER7_LOW) + +START_REGISTER(TCF_PERFCOUNTER8_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER8_LOW) + +START_REGISTER(TCF_PERFCOUNTER9_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER9_LOW) + +START_REGISTER(TCF_PERFCOUNTER10_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER10_LOW) + +START_REGISTER(TCF_PERFCOUNTER11_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER11_LOW) + +START_REGISTER(TCF_DEBUG) + GENERATE_FIELD(not_MH_TC_rtr, int) + GENERATE_FIELD(TC_MH_send, int) + GENERATE_FIELD(not_FG0_rtr, int) + GENERATE_FIELD(not_TCB_TCO_rtr, int) + GENERATE_FIELD(TCB_ff_stall, int) + GENERATE_FIELD(TCB_miss_stall, int) + GENERATE_FIELD(TCA_TCB_stall, int) + GENERATE_FIELD(PF0_stall, int) + GENERATE_FIELD(TP0_full, int) + GENERATE_FIELD(TPC_full, int) + GENERATE_FIELD(not_TPC_rtr, int) + GENERATE_FIELD(tca_state_rts, int) + GENERATE_FIELD(tca_rts, int) +END_REGISTER(TCF_DEBUG) + +START_REGISTER(TCA_FIFO_DEBUG) + GENERATE_FIELD(tp0_full, int) + GENERATE_FIELD(tpc_full, int) + GENERATE_FIELD(load_tpc_fifo, int) + GENERATE_FIELD(load_tp_fifos, int) + GENERATE_FIELD(FW_full, int) + GENERATE_FIELD(not_FW_rtr0, int) + GENERATE_FIELD(FW_rts0, int) + GENERATE_FIELD(not_FW_tpc_rtr, int) + GENERATE_FIELD(FW_tpc_rts, int) +END_REGISTER(TCA_FIFO_DEBUG) + +START_REGISTER(TCA_PROBE_DEBUG) + GENERATE_FIELD(ProbeFilter_stall, int) +END_REGISTER(TCA_PROBE_DEBUG) + +START_REGISTER(TCA_TPC_DEBUG) + GENERATE_FIELD(captue_state_rts, int) + GENERATE_FIELD(capture_tca_rts, int) +END_REGISTER(TCA_TPC_DEBUG) + +START_REGISTER(TCB_CORE_DEBUG) + GENERATE_FIELD(access512, int) + GENERATE_FIELD(tiled, int) + GENERATE_FIELD(opcode, int) + GENERATE_FIELD(format, int) + GENERATE_FIELD(sector_format, int) + GENERATE_FIELD(sector_format512, int) +END_REGISTER(TCB_CORE_DEBUG) + +START_REGISTER(TCB_TAG0_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG0_DEBUG) + +START_REGISTER(TCB_TAG1_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG1_DEBUG) + +START_REGISTER(TCB_TAG2_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG2_DEBUG) + +START_REGISTER(TCB_TAG3_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG3_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + GENERATE_FIELD(left_done, int) + GENERATE_FIELD(fg0_sends_left, int) + GENERATE_FIELD(one_sector_to_go_left_q, int) + GENERATE_FIELD(no_sectors_to_go, int) + GENERATE_FIELD(update_left, int) + GENERATE_FIELD(sector_mask_left_count_q, int) + GENERATE_FIELD(sector_mask_left_q, int) + GENERATE_FIELD(valid_left_q, int) +END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + GENERATE_FIELD(quad_sel_left, int) + GENERATE_FIELD(set_sel_left, int) + GENERATE_FIELD(right_eq_left, int) + GENERATE_FIELD(ff_fg_type512, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(setquads_to_send, int) +END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + GENERATE_FIELD(tc0_arb_rts, int) + GENERATE_FIELD(ga_out_rts, int) + GENERATE_FIELD(tc_arb_format, int) + GENERATE_FIELD(tc_arb_fmsopcode, int) + GENERATE_FIELD(tc_arb_request_type, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(fgo_busy, int) + GENERATE_FIELD(ga_busy, int) + GENERATE_FIELD(mc_sel_q, int) + GENERATE_FIELD(valid_q, int) + GENERATE_FIELD(arb_RTR, int) +END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + +START_REGISTER(TCD_INPUT0_DEBUG) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(valid_q1, int) + GENERATE_FIELD(cnt_q1, int) + GENERATE_FIELD(last_send_q1, int) + GENERATE_FIELD(ip_send, int) + GENERATE_FIELD(ipbuf_dxt_send, int) + GENERATE_FIELD(ipbuf_busy, int) +END_REGISTER(TCD_INPUT0_DEBUG) + +START_REGISTER(TCD_DEGAMMA_DEBUG) + GENERATE_FIELD(dgmm_ftfconv_dgmmen, int) + GENERATE_FIELD(dgmm_ctrl_dgmm8, int) + GENERATE_FIELD(dgmm_ctrl_last_send, int) + GENERATE_FIELD(dgmm_ctrl_send, int) + GENERATE_FIELD(dgmm_stall, int) + GENERATE_FIELD(dgmm_pstate, int) +END_REGISTER(TCD_DEGAMMA_DEBUG) + +START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(sctrmx_rtr, int) + GENERATE_FIELD(dxtc_rtr, int) + GENERATE_FIELD(sctrarb_multcyl_send, int) + GENERATE_FIELD(sctrmx0_sctrarb_rts, int) + GENERATE_FIELD(dxtc_sctrarb_send, int) + GENERATE_FIELD(dxtc_dgmmpd_last_send, int) + GENERATE_FIELD(dxtc_dgmmpd_send, int) + GENERATE_FIELD(dcmp_mux_send, int) +END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + +START_REGISTER(TCD_DXTC_ARB_DEBUG) + GENERATE_FIELD(n0_stall, int) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(arb_dcmp01_last_send, int) + GENERATE_FIELD(arb_dcmp01_cnt, int) + GENERATE_FIELD(arb_dcmp01_sector, int) + GENERATE_FIELD(arb_dcmp01_cacheline, int) + GENERATE_FIELD(arb_dcmp01_format, int) + GENERATE_FIELD(arb_dcmp01_send, int) + GENERATE_FIELD(n0_dxt2_4_types, int) +END_REGISTER(TCD_DXTC_ARB_DEBUG) + +START_REGISTER(TCD_STALLS_DEBUG) + GENERATE_FIELD(not_multcyl_sctrarb_rtr, int) + GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int) + GENERATE_FIELD(not_dcmp0_arb_rtr, int) + GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int) + GENERATE_FIELD(not_mux_dcmp_rtr, int) + GENERATE_FIELD(not_incoming_rtr, int) +END_REGISTER(TCD_STALLS_DEBUG) + +START_REGISTER(TCO_STALLS_DEBUG) + GENERATE_FIELD(quad0_sg_crd_RTR, int) + GENERATE_FIELD(quad0_rl_sg_RTR, int) + GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int) +END_REGISTER(TCO_STALLS_DEBUG) + +START_REGISTER(TCO_QUAD0_DEBUG0) + GENERATE_FIELD(rl_sg_sector_format, int) + GENERATE_FIELD(rl_sg_end_of_sample, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_end_of_sample, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(stageN1_valid_q, int) + GENERATE_FIELD(read_cache_q, int) + GENERATE_FIELD(cache_read_RTR, int) + GENERATE_FIELD(all_sectors_written_set3, int) + GENERATE_FIELD(all_sectors_written_set2, int) + GENERATE_FIELD(all_sectors_written_set1, int) + GENERATE_FIELD(all_sectors_written_set0, int) + GENERATE_FIELD(busy, int) +END_REGISTER(TCO_QUAD0_DEBUG0) + +START_REGISTER(TCO_QUAD0_DEBUG1) + GENERATE_FIELD(fifo_busy, int) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(write_enable, int) + GENERATE_FIELD(fifo_write_ptr, int) + GENERATE_FIELD(fifo_read_ptr, int) + GENERATE_FIELD(cache_read_busy, int) + GENERATE_FIELD(latency_fifo_busy, int) + GENERATE_FIELD(input_quad_busy, int) + GENERATE_FIELD(tco_quad_pipe_busy, int) + GENERATE_FIELD(TCB_TCO_rtr_d, int) + GENERATE_FIELD(TCB_TCO_xfc_q, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(TCO_TCB_read_xfc, int) +END_REGISTER(TCO_QUAD0_DEBUG1) + +START_REGISTER(SQ_GPR_MANAGEMENT) + GENERATE_FIELD(REG_DYNAMIC, int) + GENERATE_FIELD(REG_SIZE_PIX, int) + GENERATE_FIELD(REG_SIZE_VTX, int) +END_REGISTER(SQ_GPR_MANAGEMENT) + +START_REGISTER(SQ_FLOW_CONTROL) + GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int) + GENERATE_FIELD(ONE_THREAD, int) + GENERATE_FIELD(ONE_ALU, int) + GENERATE_FIELD(CF_WR_BASE, hex) + GENERATE_FIELD(NO_PV_PS, int) + GENERATE_FIELD(NO_LOOP_EXIT, int) + GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int) + GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int) + GENERATE_FIELD(VC_ARBITRATION_POLICY, int) + GENERATE_FIELD(ALU_ARBITRATION_POLICY, int) + GENERATE_FIELD(NO_ARB_EJECT, int) + GENERATE_FIELD(NO_CFS_EJECT, int) + GENERATE_FIELD(POS_EXP_PRIORITY, int) + GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int) + GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int) +END_REGISTER(SQ_FLOW_CONTROL) + +START_REGISTER(SQ_INST_STORE_MANAGMENT) + GENERATE_FIELD(INST_BASE_PIX, int) + GENERATE_FIELD(INST_BASE_VTX, int) +END_REGISTER(SQ_INST_STORE_MANAGMENT) + +START_REGISTER(SQ_RESOURCE_MANAGMENT) + GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(EXPORT_BUF_ENTRIES, int) +END_REGISTER(SQ_RESOURCE_MANAGMENT) + +START_REGISTER(SQ_EO_RT) + GENERATE_FIELD(EO_CONSTANTS_RT, int) + GENERATE_FIELD(EO_TSTATE_RT, int) +END_REGISTER(SQ_EO_RT) + +START_REGISTER(SQ_DEBUG_MISC) + GENERATE_FIELD(DB_ALUCST_SIZE, int) + GENERATE_FIELD(DB_TSTATE_SIZE, int) + GENERATE_FIELD(DB_READ_CTX, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DB_READ_MEMORY, int) + GENERATE_FIELD(DB_WEN_MEMORY_0, int) + GENERATE_FIELD(DB_WEN_MEMORY_1, int) + GENERATE_FIELD(DB_WEN_MEMORY_2, int) + GENERATE_FIELD(DB_WEN_MEMORY_3, int) +END_REGISTER(SQ_DEBUG_MISC) + +START_REGISTER(SQ_ACTIVITY_METER_CNTL) + GENERATE_FIELD(TIMEBASE, int) + GENERATE_FIELD(THRESHOLD_LOW, int) + GENERATE_FIELD(THRESHOLD_HIGH, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(SQ_ACTIVITY_METER_CNTL) + +START_REGISTER(SQ_ACTIVITY_METER_STATUS) + GENERATE_FIELD(PERCENT_BUSY, int) +END_REGISTER(SQ_ACTIVITY_METER_STATUS) + +START_REGISTER(SQ_INPUT_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) +END_REGISTER(SQ_INPUT_ARB_PRIORITY) + +START_REGISTER(SQ_THREAD_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int) +END_REGISTER(SQ_THREAD_ARB_PRIORITY) + +START_REGISTER(SQ_DEBUG_INPUT_FSM) + GENERATE_FIELD(VC_VSR_LD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VC_GPR_LD, int) + GENERATE_FIELD(PC_PISM, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PC_AS, int) + GENERATE_FIELD(PC_INTERP_CNT, int) + GENERATE_FIELD(PC_GPR_SIZE, int) +END_REGISTER(SQ_DEBUG_INPUT_FSM) + +START_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + GENERATE_FIELD(TEX_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(ALU_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(ALU_CONST_CNTX_VALID, int) + GENERATE_FIELD(TEX_CONST_CNTX_VALID, int) + GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int) +END_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + +START_REGISTER(SQ_DEBUG_TP_FSM) + GENERATE_FIELD(EX_TP, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_TP, int) + GENERATE_FIELD(IF_TP, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(TIS_TP, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(GS_TP, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(FCR_TP, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(FCS_TP, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_TP, int) +END_REGISTER(SQ_DEBUG_TP_FSM) + +START_REGISTER(SQ_DEBUG_FSM_ALU_0) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_0) + +START_REGISTER(SQ_DEBUG_FSM_ALU_1) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_1) + +START_REGISTER(SQ_DEBUG_EXP_ALLOC) + GENERATE_FIELD(POS_BUF_AVAIL, int) + GENERATE_FIELD(COLOR_BUF_AVAIL, int) + GENERATE_FIELD(EA_BUF_AVAIL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int) +END_REGISTER(SQ_DEBUG_EXP_ALLOC) + +START_REGISTER(SQ_DEBUG_PTR_BUFF) + GENERATE_FIELD(END_OF_BUFFER, int) + GENERATE_FIELD(DEALLOC_CNT, int) + GENERATE_FIELD(QUAL_NEW_VECTOR, int) + GENERATE_FIELD(EVENT_CONTEXT_ID, int) + GENERATE_FIELD(SC_EVENT_ID, int) + GENERATE_FIELD(QUAL_EVENT, int) + GENERATE_FIELD(PRIM_TYPE_POLYGON, int) + GENERATE_FIELD(EF_EMPTY, int) + GENERATE_FIELD(VTX_SYNC_CNT, int) +END_REGISTER(SQ_DEBUG_PTR_BUFF) + +START_REGISTER(SQ_DEBUG_GPR_VTX) + GENERATE_FIELD(VTX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VTX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(VTX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(VTX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_VTX) + +START_REGISTER(SQ_DEBUG_GPR_PIX) + GENERATE_FIELD(PIX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PIX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(PIX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_PIX) + +START_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int) + GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VC_THREAD_BUF_DLY, int) + GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int) +END_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + +START_REGISTER(SQ_DEBUG_VTX_TB_0) + GENERATE_FIELD(VTX_HEAD_PTR_Q, int) + GENERATE_FIELD(TAIL_PTR_Q, int) + GENERATE_FIELD(FULL_CNT_Q, int) + GENERATE_FIELD(NXT_POS_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PC_ALLOC_CNT, int) + GENERATE_FIELD(SX_EVENT_FULL, int) + GENERATE_FIELD(BUSY_Q, int) +END_REGISTER(SQ_DEBUG_VTX_TB_0) + +START_REGISTER(SQ_DEBUG_VTX_TB_1) + GENERATE_FIELD(VS_DONE_PTR, int) +END_REGISTER(SQ_DEBUG_VTX_TB_1) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + GENERATE_FIELD(VS_STATUS_REG, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + GENERATE_FIELD(VS_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + +START_REGISTER(SQ_DEBUG_PIX_TB_0) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(TAIL_PTR, int) + GENERATE_FIELD(FULL_CNT, int) + GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PIX_EXP_CNT, int) + GENERATE_FIELD(BUSY, int) +END_REGISTER(SQ_DEBUG_PIX_TB_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + GENERATE_FIELD(PIX_TB_STATUS_REG_0, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + GENERATE_FIELD(PIX_TB_STATUS_REG_1, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + GENERATE_FIELD(PIX_TB_STATUS_REG_2, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + GENERATE_FIELD(PIX_TB_STATUS_REG_3, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + GENERATE_FIELD(PIX_TB_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + +START_REGISTER(SQ_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT) +END_REGISTER(SQ_PERFCOUNTER0_SELECT) + +START_REGISTER(SQ_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER1_SELECT) + +START_REGISTER(SQ_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER2_SELECT) + +START_REGISTER(SQ_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER3_SELECT) + +START_REGISTER(SQ_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_LOW) + +START_REGISTER(SQ_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_HI) + +START_REGISTER(SQ_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_LOW) + +START_REGISTER(SQ_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_HI) + +START_REGISTER(SQ_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_LOW) + +START_REGISTER(SQ_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_HI) + +START_REGISTER(SQ_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_LOW) + +START_REGISTER(SQ_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_HI) + +START_REGISTER(SX_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT) +END_REGISTER(SX_PERFCOUNTER0_SELECT) + +START_REGISTER(SX_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_LOW) + +START_REGISTER(SX_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_HI) + +START_REGISTER(SQ_INSTRUCTION_ALU_0) + GENERATE_FIELD(VECTOR_RESULT, int) + GENERATE_FIELD(CST_0_ABS_MOD, Abs_modifier) + GENERATE_FIELD(LOW_PRECISION_16B_FP, int) + GENERATE_FIELD(SCALAR_RESULT, int) + GENERATE_FIELD(SST_0_ABS_MOD, int) + GENERATE_FIELD(EXPORT_DATA, Exporting) + GENERATE_FIELD(VECTOR_WRT_MSK, int) + GENERATE_FIELD(SCALAR_WRT_MSK, int) + GENERATE_FIELD(VECTOR_CLAMP, int) + GENERATE_FIELD(SCALAR_CLAMP, int) + GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode) +END_REGISTER(SQ_INSTRUCTION_ALU_0) + +START_REGISTER(SQ_INSTRUCTION_ALU_1) + GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier) + GENERATE_FIELD(PRED_SELECT, PredicateSelect) + GENERATE_FIELD(RELATIVE_ADDR, int) + GENERATE_FIELD(CONST_1_REL_ABS, int) + GENERATE_FIELD(CONST_0_REL_ABS, int) +END_REGISTER(SQ_INSTRUCTION_ALU_1) + +START_REGISTER(SQ_INSTRUCTION_ALU_2) + GENERATE_FIELD(SRC_C_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_C, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier) + GENERATE_FIELD(SRC_B_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_B, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier) + GENERATE_FIELD(SRC_A_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_A, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier) + GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode) + GENERATE_FIELD(SRC_C_SEL, OperandSelect0) + GENERATE_FIELD(SRC_B_SEL, OperandSelect0) + GENERATE_FIELD(SRC_A_SEL, OperandSelect0) +END_REGISTER(SQ_INSTRUCTION_ALU_2) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(PREDICATED_JMP, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_2, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_0) + GENERATE_FIELD(OPCODE, TexInstOpcode) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, Addressmode) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, Addressmode) + GENERATE_FIELD(FETCH_VALID_ONLY, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm) + GENERATE_FIELD(SRC_SEL_X, SrcSel) + GENERATE_FIELD(SRC_SEL_Y, SrcSel) + GENERATE_FIELD(SRC_SEL_Z, SrcSel) +END_REGISTER(SQ_INSTRUCTION_TFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_1) + GENERATE_FIELD(DST_SEL_X, DstSel) + GENERATE_FIELD(DST_SEL_Y, DstSel) + GENERATE_FIELD(DST_SEL_Z, DstSel) + GENERATE_FIELD(DST_SEL_W, DstSel) + GENERATE_FIELD(MAG_FILTER, MagFilter) + GENERATE_FIELD(MIN_FILTER, MinFilter) + GENERATE_FIELD(MIP_FILTER, MipFilter) + GENERATE_FIELD(ANISO_FILTER, AnisoFilter) + GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter) + GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter) + GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter) + GENERATE_FIELD(USE_COMP_LOD, int) + GENERATE_FIELD(USE_REG_LOD, int) + GENERATE_FIELD(PRED_SELECT, PredSelect) +END_REGISTER(SQ_INSTRUCTION_TFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_2) + GENERATE_FIELD(USE_REG_GRADIENTS, int) + GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation) + GENERATE_FIELD(LOD_BIAS, int) + GENERATE_FIELD(UNUSED, int) + GENERATE_FIELD(OFFSET_X, int) + GENERATE_FIELD(OFFSET_Y, int) + GENERATE_FIELD(OFFSET_Z, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_TFETCH_2) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_0) + GENERATE_FIELD(OPCODE, int) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, int) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, int) + GENERATE_FIELD(MUST_BE_ONE, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(CONST_INDEX_SEL, int) + GENERATE_FIELD(SRC_SEL, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_1) + GENERATE_FIELD(DST_SEL_X, int) + GENERATE_FIELD(DST_SEL_Y, int) + GENERATE_FIELD(DST_SEL_Z, int) + GENERATE_FIELD(DST_SEL_W, int) + GENERATE_FIELD(FORMAT_COMP_ALL, int) + GENERATE_FIELD(NUM_FORMAT_ALL, int) + GENERATE_FIELD(SIGNED_RF_MODE_ALL, int) + GENERATE_FIELD(DATA_FORMAT, int) + GENERATE_FIELD(EXP_ADJUST_ALL, int) + GENERATE_FIELD(PRED_SELECT, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_2) + GENERATE_FIELD(STRIDE, int) + GENERATE_FIELD(OFFSET, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_2) + +START_REGISTER(SQ_CONSTANT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_0) + +START_REGISTER(SQ_CONSTANT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_1) + +START_REGISTER(SQ_CONSTANT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_2) + +START_REGISTER(SQ_CONSTANT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_3) + +START_REGISTER(SQ_FETCH_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_0) + +START_REGISTER(SQ_FETCH_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_1) + +START_REGISTER(SQ_FETCH_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_2) + +START_REGISTER(SQ_FETCH_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_3) + +START_REGISTER(SQ_FETCH_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_4) + +START_REGISTER(SQ_FETCH_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_5) + +START_REGISTER(SQ_CONSTANT_VFETCH_0) + GENERATE_FIELD(TYPE, int) + GENERATE_FIELD(STATE, int) + GENERATE_FIELD(BASE_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_0) + +START_REGISTER(SQ_CONSTANT_VFETCH_1) + GENERATE_FIELD(ENDIAN_SWAP, int) + GENERATE_FIELD(LIMIT_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_1) + +START_REGISTER(SQ_CONSTANT_T2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T2) + +START_REGISTER(SQ_CONSTANT_T3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T3) + +START_REGISTER(SQ_CF_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_BOOLEANS) + +START_REGISTER(SQ_CF_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_LOOP) + +START_REGISTER(SQ_CONSTANT_RT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_RT_0) + +START_REGISTER(SQ_CONSTANT_RT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_RT_1) + +START_REGISTER(SQ_CONSTANT_RT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_RT_2) + +START_REGISTER(SQ_CONSTANT_RT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_RT_3) + +START_REGISTER(SQ_FETCH_RT_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_0) + +START_REGISTER(SQ_FETCH_RT_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_1) + +START_REGISTER(SQ_FETCH_RT_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_2) + +START_REGISTER(SQ_FETCH_RT_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_3) + +START_REGISTER(SQ_FETCH_RT_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_4) + +START_REGISTER(SQ_FETCH_RT_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_5) + +START_REGISTER(SQ_CF_RT_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_RT_BOOLEANS) + +START_REGISTER(SQ_CF_RT_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_RT_LOOP) + +START_REGISTER(SQ_VS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_PROGRAM) + +START_REGISTER(SQ_PS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_PROGRAM) + +START_REGISTER(SQ_CF_PROGRAM_SIZE) + GENERATE_FIELD(VS_CF_SIZE, int) + GENERATE_FIELD(PS_CF_SIZE, int) +END_REGISTER(SQ_CF_PROGRAM_SIZE) + +START_REGISTER(SQ_INTERPOLATOR_CNTL) + GENERATE_FIELD(PARAM_SHADE, ParamShade) + GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern) +END_REGISTER(SQ_INTERPOLATOR_CNTL) + +START_REGISTER(SQ_PROGRAM_CNTL) + GENERATE_FIELD(VS_NUM_REG, intMinusOne) + GENERATE_FIELD(PS_NUM_REG, intMinusOne) + GENERATE_FIELD(VS_RESOURCE, int) + GENERATE_FIELD(PS_RESOURCE, int) + GENERATE_FIELD(PARAM_GEN, int) + GENERATE_FIELD(GEN_INDEX_PIX, int) + GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne) + GENERATE_FIELD(VS_EXPORT_MODE, VertexMode) + GENERATE_FIELD(PS_EXPORT_MODE, int) + GENERATE_FIELD(GEN_INDEX_VTX, int) +END_REGISTER(SQ_PROGRAM_CNTL) + +START_REGISTER(SQ_WRAPPING_0) + GENERATE_FIELD(PARAM_WRAP_0, hex) + GENERATE_FIELD(PARAM_WRAP_1, hex) + GENERATE_FIELD(PARAM_WRAP_2, hex) + GENERATE_FIELD(PARAM_WRAP_3, hex) + GENERATE_FIELD(PARAM_WRAP_4, hex) + GENERATE_FIELD(PARAM_WRAP_5, hex) + GENERATE_FIELD(PARAM_WRAP_6, hex) + GENERATE_FIELD(PARAM_WRAP_7, hex) +END_REGISTER(SQ_WRAPPING_0) + +START_REGISTER(SQ_WRAPPING_1) + GENERATE_FIELD(PARAM_WRAP_8, hex) + GENERATE_FIELD(PARAM_WRAP_9, hex) + GENERATE_FIELD(PARAM_WRAP_10, hex) + GENERATE_FIELD(PARAM_WRAP_11, hex) + GENERATE_FIELD(PARAM_WRAP_12, hex) + GENERATE_FIELD(PARAM_WRAP_13, hex) + GENERATE_FIELD(PARAM_WRAP_14, hex) + GENERATE_FIELD(PARAM_WRAP_15, hex) +END_REGISTER(SQ_WRAPPING_1) + +START_REGISTER(SQ_VS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_CONST) + +START_REGISTER(SQ_PS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_CONST) + +START_REGISTER(SQ_CONTEXT_MISC) + GENERATE_FIELD(INST_PRED_OPTIMIZE, int) + GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int) + GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl) + GENERATE_FIELD(PARAM_GEN_POS, int) + GENERATE_FIELD(PERFCOUNTER_REF, int) + GENERATE_FIELD(YEILD_OPTIMIZE, int) + GENERATE_FIELD(TX_CACHE_SEL, int) +END_REGISTER(SQ_CONTEXT_MISC) + +START_REGISTER(SQ_CF_RD_BASE) + GENERATE_FIELD(RD_BASE, hex) +END_REGISTER(SQ_CF_RD_BASE) + +START_REGISTER(SQ_DEBUG_MISC_0) + GENERATE_FIELD(DB_PROB_ON, int) + GENERATE_FIELD(DB_PROB_BREAK, int) + GENERATE_FIELD(DB_PROB_ADDR, int) + GENERATE_FIELD(DB_PROB_COUNT, int) +END_REGISTER(SQ_DEBUG_MISC_0) + +START_REGISTER(SQ_DEBUG_MISC_1) + GENERATE_FIELD(DB_ON_PIX, int) + GENERATE_FIELD(DB_ON_VTX, int) + GENERATE_FIELD(DB_INST_COUNT, int) + GENERATE_FIELD(DB_BREAK_ADDR, int) +END_REGISTER(SQ_DEBUG_MISC_1) + +START_REGISTER(MH_ARBITER_CONFIG) + GENERATE_FIELD(SAME_PAGE_LIMIT, int) + GENERATE_FIELD(SAME_PAGE_GRANULARITY, int) + GENERATE_FIELD(L1_ARB_ENABLE, bool) + GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int) + GENERATE_FIELD(L2_ARB_CONTROL, int) + GENERATE_FIELD(PAGE_SIZE, int) + GENERATE_FIELD(TC_REORDER_ENABLE, bool) + GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT, int) + GENERATE_FIELD(CP_CLNT_ENABLE, bool) + GENERATE_FIELD(VGT_CLNT_ENABLE, bool) + GENERATE_FIELD(TC_CLNT_ENABLE, bool) + GENERATE_FIELD(RB_CLNT_ENABLE, bool) +END_REGISTER(MH_ARBITER_CONFIG) + +START_REGISTER(MH_CLNT_AXI_ID_REUSE) + GENERATE_FIELD(CPw_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RBw_ID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(MMUr_ID, int) +END_REGISTER(MH_CLNT_AXI_ID_REUSE) + +START_REGISTER(MH_INTERRUPT_MASK) + GENERATE_FIELD(AXI_READ_ERROR, bool) + GENERATE_FIELD(AXI_WRITE_ERROR, bool) + GENERATE_FIELD(MMU_PAGE_FAULT, bool) +END_REGISTER(MH_INTERRUPT_MASK) + +START_REGISTER(MH_INTERRUPT_STATUS) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_STATUS) + +START_REGISTER(MH_INTERRUPT_CLEAR) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_CLEAR) + +START_REGISTER(MH_AXI_ERROR) + GENERATE_FIELD(AXI_READ_ID, int) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ID, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) +END_REGISTER(MH_AXI_ERROR) + +START_REGISTER(MH_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER0_SELECT) + +START_REGISTER(MH_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER1_SELECT) + +START_REGISTER(MH_PERFCOUNTER0_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER0_CONFIG) + +START_REGISTER(MH_PERFCOUNTER1_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER1_CONFIG) + +START_REGISTER(MH_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER0_LOW) + +START_REGISTER(MH_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER1_LOW) + +START_REGISTER(MH_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER0_HI) + +START_REGISTER(MH_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER1_HI) + +START_REGISTER(MH_DEBUG_CTRL) + GENERATE_FIELD(INDEX, int) +END_REGISTER(MH_DEBUG_CTRL) + +START_REGISTER(MH_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(MH_DEBUG_DATA) + +START_REGISTER(MH_MMU_CONFIG) + GENERATE_FIELD(MMU_ENABLE, bool) + GENERATE_FIELD(SPLIT_MODE_ENABLE, bool) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh) +END_REGISTER(MH_MMU_CONFIG) + +START_REGISTER(MH_MMU_VA_RANGE) + GENERATE_FIELD(NUM_64KB_REGIONS, int) + GENERATE_FIELD(VA_BASE, int) +END_REGISTER(MH_MMU_VA_RANGE) + +START_REGISTER(MH_MMU_PT_BASE) + GENERATE_FIELD(PT_BASE, int) +END_REGISTER(MH_MMU_PT_BASE) + +START_REGISTER(MH_MMU_PAGE_FAULT) + GENERATE_FIELD(PAGE_FAULT, int) + GENERATE_FIELD(OP_TYPE, int) + GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(AXI_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(READ_PROTECTION_ERROR, int) + GENERATE_FIELD(WRITE_PROTECTION_ERROR, int) + GENERATE_FIELD(REQ_VA, int) +END_REGISTER(MH_MMU_PAGE_FAULT) + +START_REGISTER(MH_MMU_TRAN_ERROR) + GENERATE_FIELD(TRAN_ERROR, int) +END_REGISTER(MH_MMU_TRAN_ERROR) + +START_REGISTER(MH_MMU_INVALIDATE) + GENERATE_FIELD(INVALIDATE_ALL, int) + GENERATE_FIELD(INVALIDATE_TC, int) +END_REGISTER(MH_MMU_INVALIDATE) + +START_REGISTER(MH_MMU_MPU_BASE) + GENERATE_FIELD(MPU_BASE, int) +END_REGISTER(MH_MMU_MPU_BASE) + +START_REGISTER(MH_MMU_MPU_END) + GENERATE_FIELD(MPU_END, int) +END_REGISTER(MH_MMU_MPU_END) + +START_REGISTER(WAIT_UNTIL) + GENERATE_FIELD(WAIT_RE_VSYNC, int) + GENERATE_FIELD(WAIT_FE_VSYNC, int) + GENERATE_FIELD(WAIT_VSYNC, int) + GENERATE_FIELD(WAIT_DSPLY_ID0, int) + GENERATE_FIELD(WAIT_DSPLY_ID1, int) + GENERATE_FIELD(WAIT_DSPLY_ID2, int) + GENERATE_FIELD(WAIT_CMDFIFO, int) + GENERATE_FIELD(WAIT_2D_IDLE, int) + GENERATE_FIELD(WAIT_3D_IDLE, int) + GENERATE_FIELD(WAIT_2D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_3D_IDLECLEAN, int) + GENERATE_FIELD(CMDFIFO_ENTRIES, int) +END_REGISTER(WAIT_UNTIL) + +START_REGISTER(RBBM_ISYNC_CNTL) + GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int) + GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int) +END_REGISTER(RBBM_ISYNC_CNTL) + +START_REGISTER(RBBM_STATUS) + GENERATE_FIELD(CMDFIFO_AVAIL, int) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(HIRQ_PENDING, int) + GENERATE_FIELD(CPRQ_PENDING, int) + GENERATE_FIELD(CFRQ_PENDING, int) + GENERATE_FIELD(PFRQ_PENDING, int) + GENERATE_FIELD(VGT_BUSY_NO_DMA, int) + GENERATE_FIELD(RBBM_WU_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(MH_BUSY, int) + GENERATE_FIELD(MH_COHERENCY_BUSY, int) + GENERATE_FIELD(SX_BUSY, int) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(SC_CNTX_BUSY, int) + GENERATE_FIELD(PA_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(SQ_CNTX17_BUSY, int) + GENERATE_FIELD(SQ_CNTX0_BUSY, int) + GENERATE_FIELD(RB_CNTX_BUSY, int) + GENERATE_FIELD(GUI_ACTIVE, int) +END_REGISTER(RBBM_STATUS) + +START_REGISTER(RBBM_DSPLY) + GENERATE_FIELD(DISPLAY_ID0_ACTIVE, int) + GENERATE_FIELD(DISPLAY_ID1_ACTIVE, int) + GENERATE_FIELD(DISPLAY_ID2_ACTIVE, int) + GENERATE_FIELD(VSYNC_ACTIVE, int) + GENERATE_FIELD(USE_DISPLAY_ID0, int) + GENERATE_FIELD(USE_DISPLAY_ID1, int) + GENERATE_FIELD(USE_DISPLAY_ID2, int) + GENERATE_FIELD(SW_CNTL, int) + GENERATE_FIELD(NUM_BUFS, int) +END_REGISTER(RBBM_DSPLY) + +START_REGISTER(RBBM_RENDER_LATEST) + GENERATE_FIELD(BUFFER_ID, int) +END_REGISTER(RBBM_RENDER_LATEST) + +START_REGISTER(RBBM_RTL_RELEASE) + GENERATE_FIELD(CHANGELIST, int) +END_REGISTER(RBBM_RTL_RELEASE) + +START_REGISTER(RBBM_PATCH_RELEASE) + GENERATE_FIELD(PATCH_REVISION, int) + GENERATE_FIELD(PATCH_SELECTION, int) + GENERATE_FIELD(CUSTOMER_ID, int) +END_REGISTER(RBBM_PATCH_RELEASE) + +START_REGISTER(RBBM_AUXILIARY_CONFIG) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(RBBM_AUXILIARY_CONFIG) + +START_REGISTER(RBBM_PERIPHID0) + GENERATE_FIELD(PARTNUMBER0, int) +END_REGISTER(RBBM_PERIPHID0) + +START_REGISTER(RBBM_PERIPHID1) + GENERATE_FIELD(PARTNUMBER1, int) + GENERATE_FIELD(DESIGNER0, int) +END_REGISTER(RBBM_PERIPHID1) + +START_REGISTER(RBBM_PERIPHID2) + GENERATE_FIELD(DESIGNER1, int) + GENERATE_FIELD(REVISION, int) +END_REGISTER(RBBM_PERIPHID2) + +START_REGISTER(RBBM_PERIPHID3) + GENERATE_FIELD(RBBM_HOST_INTERFACE, int) + GENERATE_FIELD(GARB_SLAVE_INTERFACE, int) + GENERATE_FIELD(MH_INTERFACE, int) + GENERATE_FIELD(CONTINUATION, int) +END_REGISTER(RBBM_PERIPHID3) + +START_REGISTER(RBBM_CNTL) + GENERATE_FIELD(READ_TIMEOUT, int) + GENERATE_FIELD(REGCLK_DEASSERT_TIME, int) +END_REGISTER(RBBM_CNTL) + +START_REGISTER(RBBM_SKEW_CNTL) + GENERATE_FIELD(SKEW_TOP_THRESHOLD, int) + GENERATE_FIELD(SKEW_COUNT, int) +END_REGISTER(RBBM_SKEW_CNTL) + +START_REGISTER(RBBM_SOFT_RESET) + GENERATE_FIELD(SOFT_RESET_CP, int) + GENERATE_FIELD(SOFT_RESET_PA, int) + GENERATE_FIELD(SOFT_RESET_MH, int) + GENERATE_FIELD(SOFT_RESET_BC, int) + GENERATE_FIELD(SOFT_RESET_SQ, int) + GENERATE_FIELD(SOFT_RESET_SX, int) + GENERATE_FIELD(SOFT_RESET_CIB, int) + GENERATE_FIELD(SOFT_RESET_SC, int) + GENERATE_FIELD(SOFT_RESET_VGT, int) +END_REGISTER(RBBM_SOFT_RESET) + +START_REGISTER(RBBM_PM_OVERRIDE1) + GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE1) + +START_REGISTER(RBBM_PM_OVERRIDE2) + GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE2) + +START_REGISTER(GC_SYS_IDLE) + GENERATE_FIELD(GC_SYS_IDLE_DELAY, int) + GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int) +END_REGISTER(GC_SYS_IDLE) + +START_REGISTER(NQWAIT_UNTIL) + GENERATE_FIELD(WAIT_GUI_IDLE, int) +END_REGISTER(NQWAIT_UNTIL) + +START_REGISTER(RBBM_DEBUG) + GENERATE_FIELD(IGNORE_RTR, int) + GENERATE_FIELD(IGNORE_CP_SCHED_WU, int) + GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int) + GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int) + GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int) + GENERATE_FIELD(IGNORE_RTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(CP_RBBM_NRTRTR, int) + GENERATE_FIELD(VGT_RBBM_NRTRTR, int) + GENERATE_FIELD(SQ_RBBM_NRTRTR, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int) + GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int) +END_REGISTER(RBBM_DEBUG) + +START_REGISTER(RBBM_READ_ERROR) + GENERATE_FIELD(READ_ADDRESS, int) + GENERATE_FIELD(READ_REQUESTER, int) + GENERATE_FIELD(READ_ERROR, int) +END_REGISTER(RBBM_READ_ERROR) + +START_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int) +END_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + +START_REGISTER(RBBM_INT_CNTL) + GENERATE_FIELD(RDERR_INT_MASK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int) + GENERATE_FIELD(GUI_IDLE_INT_MASK, int) +END_REGISTER(RBBM_INT_CNTL) + +START_REGISTER(RBBM_INT_STATUS) + GENERATE_FIELD(RDERR_INT_STAT, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int) + GENERATE_FIELD(GUI_IDLE_INT_STAT, int) +END_REGISTER(RBBM_INT_STATUS) + +START_REGISTER(RBBM_INT_ACK) + GENERATE_FIELD(RDERR_INT_ACK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int) + GENERATE_FIELD(GUI_IDLE_INT_ACK, int) +END_REGISTER(RBBM_INT_ACK) + +START_REGISTER(MASTER_INT_SIGNAL) + GENERATE_FIELD(MH_INT_STAT, int) + GENERATE_FIELD(CP_INT_STAT, int) + GENERATE_FIELD(RBBM_INT_STAT, int) +END_REGISTER(MASTER_INT_SIGNAL) + +START_REGISTER(RBBM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL) +END_REGISTER(RBBM_PERFCOUNTER1_SELECT) + +START_REGISTER(RBBM_PERFCOUNTER1_LO) + GENERATE_FIELD(PERF_COUNT1_LO, int) +END_REGISTER(RBBM_PERFCOUNTER1_LO) + +START_REGISTER(RBBM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT1_HI, int) +END_REGISTER(RBBM_PERFCOUNTER1_HI) + +START_REGISTER(CP_RB_BASE) + GENERATE_FIELD(RB_BASE, int) +END_REGISTER(CP_RB_BASE) + +START_REGISTER(CP_RB_CNTL) + GENERATE_FIELD(RB_BUFSZ, int) + GENERATE_FIELD(RB_BLKSZ, int) + GENERATE_FIELD(BUF_SWAP, int) + GENERATE_FIELD(RB_POLL_EN, int) + GENERATE_FIELD(RB_NO_UPDATE, int) + GENERATE_FIELD(RB_RPTR_WR_ENA, int) +END_REGISTER(CP_RB_CNTL) + +START_REGISTER(CP_RB_RPTR_ADDR) + GENERATE_FIELD(RB_RPTR_SWAP, int) + GENERATE_FIELD(RB_RPTR_ADDR, int) +END_REGISTER(CP_RB_RPTR_ADDR) + +START_REGISTER(CP_RB_RPTR) + GENERATE_FIELD(RB_RPTR, int) +END_REGISTER(CP_RB_RPTR) + +START_REGISTER(CP_RB_RPTR_WR) + GENERATE_FIELD(RB_RPTR_WR, int) +END_REGISTER(CP_RB_RPTR_WR) + +START_REGISTER(CP_RB_WPTR) + GENERATE_FIELD(RB_WPTR, int) +END_REGISTER(CP_RB_WPTR) + +START_REGISTER(CP_RB_WPTR_DELAY) + GENERATE_FIELD(PRE_WRITE_TIMER, int) + GENERATE_FIELD(PRE_WRITE_LIMIT, int) +END_REGISTER(CP_RB_WPTR_DELAY) + +START_REGISTER(CP_RB_WPTR_BASE) + GENERATE_FIELD(RB_WPTR_SWAP, int) + GENERATE_FIELD(RB_WPTR_BASE, int) +END_REGISTER(CP_RB_WPTR_BASE) + +START_REGISTER(CP_IB1_BASE) + GENERATE_FIELD(IB1_BASE, int) +END_REGISTER(CP_IB1_BASE) + +START_REGISTER(CP_IB1_BUFSZ) + GENERATE_FIELD(IB1_BUFSZ, int) +END_REGISTER(CP_IB1_BUFSZ) + +START_REGISTER(CP_IB2_BASE) + GENERATE_FIELD(IB2_BASE, int) +END_REGISTER(CP_IB2_BASE) + +START_REGISTER(CP_IB2_BUFSZ) + GENERATE_FIELD(IB2_BUFSZ, int) +END_REGISTER(CP_IB2_BUFSZ) + +START_REGISTER(CP_ST_BASE) + GENERATE_FIELD(ST_BASE, int) +END_REGISTER(CP_ST_BASE) + +START_REGISTER(CP_ST_BUFSZ) + GENERATE_FIELD(ST_BUFSZ, int) +END_REGISTER(CP_ST_BUFSZ) + +START_REGISTER(CP_QUEUE_THRESHOLDS) + GENERATE_FIELD(CSQ_IB1_START, int) + GENERATE_FIELD(CSQ_IB2_START, int) + GENERATE_FIELD(CSQ_ST_START, int) +END_REGISTER(CP_QUEUE_THRESHOLDS) + +START_REGISTER(CP_MEQ_THRESHOLDS) + GENERATE_FIELD(MEQ_END, int) + GENERATE_FIELD(ROQ_END, int) +END_REGISTER(CP_MEQ_THRESHOLDS) + +START_REGISTER(CP_CSQ_AVAIL) + GENERATE_FIELD(CSQ_CNT_RING, int) + GENERATE_FIELD(CSQ_CNT_IB1, int) + GENERATE_FIELD(CSQ_CNT_IB2, int) +END_REGISTER(CP_CSQ_AVAIL) + +START_REGISTER(CP_STQ_AVAIL) + GENERATE_FIELD(STQ_CNT_ST, int) +END_REGISTER(CP_STQ_AVAIL) + +START_REGISTER(CP_MEQ_AVAIL) + GENERATE_FIELD(MEQ_CNT, int) +END_REGISTER(CP_MEQ_AVAIL) + +START_REGISTER(CP_CSQ_RB_STAT) + GENERATE_FIELD(CSQ_RPTR_PRIMARY, int) + GENERATE_FIELD(CSQ_WPTR_PRIMARY, int) +END_REGISTER(CP_CSQ_RB_STAT) + +START_REGISTER(CP_CSQ_IB1_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int) +END_REGISTER(CP_CSQ_IB1_STAT) + +START_REGISTER(CP_CSQ_IB2_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int) +END_REGISTER(CP_CSQ_IB2_STAT) + +START_REGISTER(CP_NON_PREFETCH_CNTRS) + GENERATE_FIELD(IB1_COUNTER, int) + GENERATE_FIELD(IB2_COUNTER, int) +END_REGISTER(CP_NON_PREFETCH_CNTRS) + +START_REGISTER(CP_STQ_ST_STAT) + GENERATE_FIELD(STQ_RPTR_ST, int) + GENERATE_FIELD(STQ_WPTR_ST, int) +END_REGISTER(CP_STQ_ST_STAT) + +START_REGISTER(CP_MEQ_STAT) + GENERATE_FIELD(MEQ_RPTR, int) + GENERATE_FIELD(MEQ_WPTR, int) +END_REGISTER(CP_MEQ_STAT) + +START_REGISTER(CP_MIU_TAG_STAT) + GENERATE_FIELD(TAG_0_STAT, int) + GENERATE_FIELD(TAG_1_STAT, int) + GENERATE_FIELD(TAG_2_STAT, int) + GENERATE_FIELD(TAG_3_STAT, int) + GENERATE_FIELD(TAG_4_STAT, int) + GENERATE_FIELD(TAG_5_STAT, int) + GENERATE_FIELD(TAG_6_STAT, int) + GENERATE_FIELD(TAG_7_STAT, int) + GENERATE_FIELD(TAG_8_STAT, int) + GENERATE_FIELD(TAG_9_STAT, int) + GENERATE_FIELD(TAG_10_STAT, int) + GENERATE_FIELD(TAG_11_STAT, int) + GENERATE_FIELD(TAG_12_STAT, int) + GENERATE_FIELD(TAG_13_STAT, int) + GENERATE_FIELD(TAG_14_STAT, int) + GENERATE_FIELD(TAG_15_STAT, int) + GENERATE_FIELD(TAG_16_STAT, int) + GENERATE_FIELD(TAG_17_STAT, int) + GENERATE_FIELD(INVALID_RETURN_TAG, int) +END_REGISTER(CP_MIU_TAG_STAT) + +START_REGISTER(CP_CMD_INDEX) + GENERATE_FIELD(CMD_INDEX, int) + GENERATE_FIELD(CMD_QUEUE_SEL, int) +END_REGISTER(CP_CMD_INDEX) + +START_REGISTER(CP_CMD_DATA) + GENERATE_FIELD(CMD_DATA, int) +END_REGISTER(CP_CMD_DATA) + +START_REGISTER(CP_ME_CNTL) + GENERATE_FIELD(ME_STATMUX, int) + GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(ME_HALT, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(PROG_CNT_SIZE, int) +END_REGISTER(CP_ME_CNTL) + +START_REGISTER(CP_ME_STATUS) + GENERATE_FIELD(ME_DEBUG_DATA, int) +END_REGISTER(CP_ME_STATUS) + +START_REGISTER(CP_ME_RAM_WADDR) + GENERATE_FIELD(ME_RAM_WADDR, int) +END_REGISTER(CP_ME_RAM_WADDR) + +START_REGISTER(CP_ME_RAM_RADDR) + GENERATE_FIELD(ME_RAM_RADDR, int) +END_REGISTER(CP_ME_RAM_RADDR) + +START_REGISTER(CP_ME_RAM_DATA) + GENERATE_FIELD(ME_RAM_DATA, int) +END_REGISTER(CP_ME_RAM_DATA) + +START_REGISTER(CP_ME_RDADDR) + GENERATE_FIELD(ME_RDADDR, int) +END_REGISTER(CP_ME_RDADDR) + +START_REGISTER(CP_DEBUG) + GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int) + GENERATE_FIELD(PREDICATE_DISABLE, int) + GENERATE_FIELD(PROG_END_PTR_ENABLE, int) + GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int) + GENERATE_FIELD(PREFETCH_PASS_NOPS, int) + GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int) + GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int) + GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int) + GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int) +END_REGISTER(CP_DEBUG) + +START_REGISTER(SCRATCH_REG0) + GENERATE_FIELD(SCRATCH_REG0, int) +END_REGISTER(SCRATCH_REG0) + +START_REGISTER(SCRATCH_REG1) + GENERATE_FIELD(SCRATCH_REG1, int) +END_REGISTER(SCRATCH_REG1) + +START_REGISTER(SCRATCH_REG2) + GENERATE_FIELD(SCRATCH_REG2, int) +END_REGISTER(SCRATCH_REG2) + +START_REGISTER(SCRATCH_REG3) + GENERATE_FIELD(SCRATCH_REG3, int) +END_REGISTER(SCRATCH_REG3) + +START_REGISTER(SCRATCH_REG4) + GENERATE_FIELD(SCRATCH_REG4, int) +END_REGISTER(SCRATCH_REG4) + +START_REGISTER(SCRATCH_REG5) + GENERATE_FIELD(SCRATCH_REG5, int) +END_REGISTER(SCRATCH_REG5) + +START_REGISTER(SCRATCH_REG6) + GENERATE_FIELD(SCRATCH_REG6, int) +END_REGISTER(SCRATCH_REG6) + +START_REGISTER(SCRATCH_REG7) + GENERATE_FIELD(SCRATCH_REG7, int) +END_REGISTER(SCRATCH_REG7) + +START_REGISTER(SCRATCH_UMSK) + GENERATE_FIELD(SCRATCH_UMSK, int) + GENERATE_FIELD(SCRATCH_SWAP, int) +END_REGISTER(SCRATCH_UMSK) + +START_REGISTER(SCRATCH_ADDR) + GENERATE_FIELD(SCRATCH_ADDR, hex) +END_REGISTER(SCRATCH_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_SRC) + GENERATE_FIELD(VS_DONE_SWM, int) + GENERATE_FIELD(VS_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_EVENT_SRC) + +START_REGISTER(CP_ME_VS_EVENT_ADDR) + GENERATE_FIELD(VS_DONE_SWAP, int) + GENERATE_FIELD(VS_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_DATA) + GENERATE_FIELD(VS_DONE_DATA, int) +END_REGISTER(CP_ME_VS_EVENT_DATA) + +START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + GENERATE_FIELD(VS_DONE_SWAP_SWM, int) + GENERATE_FIELD(VS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + GENERATE_FIELD(VS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_PS_EVENT_SRC) + GENERATE_FIELD(PS_DONE_SWM, int) + GENERATE_FIELD(PS_DONE_CNTR, int) +END_REGISTER(CP_ME_PS_EVENT_SRC) + +START_REGISTER(CP_ME_PS_EVENT_ADDR) + GENERATE_FIELD(PS_DONE_SWAP, int) + GENERATE_FIELD(PS_DONE_ADDR, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR) + +START_REGISTER(CP_ME_PS_EVENT_DATA) + GENERATE_FIELD(PS_DONE_DATA, int) +END_REGISTER(CP_ME_PS_EVENT_DATA) + +START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + GENERATE_FIELD(PS_DONE_SWAP_SWM, int) + GENERATE_FIELD(PS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + GENERATE_FIELD(PS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_CF_EVENT_SRC) + GENERATE_FIELD(CF_DONE_SRC, int) +END_REGISTER(CP_ME_CF_EVENT_SRC) + +START_REGISTER(CP_ME_CF_EVENT_ADDR) + GENERATE_FIELD(CF_DONE_SWAP, int) + GENERATE_FIELD(CF_DONE_ADDR, int) +END_REGISTER(CP_ME_CF_EVENT_ADDR) + +START_REGISTER(CP_ME_CF_EVENT_DATA) + GENERATE_FIELD(CF_DONE_DATA, int) +END_REGISTER(CP_ME_CF_EVENT_DATA) + +START_REGISTER(CP_ME_NRT_ADDR) + GENERATE_FIELD(NRT_WRITE_SWAP, int) + GENERATE_FIELD(NRT_WRITE_ADDR, int) +END_REGISTER(CP_ME_NRT_ADDR) + +START_REGISTER(CP_ME_NRT_DATA) + GENERATE_FIELD(NRT_WRITE_DATA, int) +END_REGISTER(CP_ME_NRT_DATA) + +START_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + GENERATE_FIELD(VS_FETCH_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + +START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + GENERATE_FIELD(VS_FETCH_DONE_SWAP, int) + GENERATE_FIELD(VS_FETCH_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + +START_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + GENERATE_FIELD(VS_FETCH_DONE_DATA, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + +START_REGISTER(CP_INT_CNTL) + GENERATE_FIELD(SW_INT_MASK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int) + GENERATE_FIELD(OPCODE_ERROR_MASK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int) + GENERATE_FIELD(IB_ERROR_MASK, int) + GENERATE_FIELD(IB2_INT_MASK, int) + GENERATE_FIELD(IB1_INT_MASK, int) + GENERATE_FIELD(RB_INT_MASK, int) +END_REGISTER(CP_INT_CNTL) + +START_REGISTER(CP_INT_STATUS) + GENERATE_FIELD(SW_INT_STAT, int) + GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int) + GENERATE_FIELD(OPCODE_ERROR_STAT, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int) + GENERATE_FIELD(IB_ERROR_STAT, int) + GENERATE_FIELD(IB2_INT_STAT, int) + GENERATE_FIELD(IB1_INT_STAT, int) + GENERATE_FIELD(RB_INT_STAT, int) +END_REGISTER(CP_INT_STATUS) + +START_REGISTER(CP_INT_ACK) + GENERATE_FIELD(SW_INT_ACK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int) + GENERATE_FIELD(OPCODE_ERROR_ACK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int) + GENERATE_FIELD(IB_ERROR_ACK, int) + GENERATE_FIELD(IB2_INT_ACK, int) + GENERATE_FIELD(IB1_INT_ACK, int) + GENERATE_FIELD(RB_INT_ACK, int) +END_REGISTER(CP_INT_ACK) + +START_REGISTER(CP_PFP_UCODE_ADDR) + GENERATE_FIELD(UCODE_ADDR, hex) +END_REGISTER(CP_PFP_UCODE_ADDR) + +START_REGISTER(CP_PFP_UCODE_DATA) + GENERATE_FIELD(UCODE_DATA, hex) +END_REGISTER(CP_PFP_UCODE_DATA) + +START_REGISTER(CP_PERFMON_CNTL) + GENERATE_FIELD(PERFMON_STATE, int) + GENERATE_FIELD(PERFMON_ENABLE_MODE, int) +END_REGISTER(CP_PERFMON_CNTL) + +START_REGISTER(CP_PERFCOUNTER_SELECT) + GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL) +END_REGISTER(CP_PERFCOUNTER_SELECT) + +START_REGISTER(CP_PERFCOUNTER_LO) + GENERATE_FIELD(PERFCOUNT_LO, int) +END_REGISTER(CP_PERFCOUNTER_LO) + +START_REGISTER(CP_PERFCOUNTER_HI) + GENERATE_FIELD(PERFCOUNT_HI, int) +END_REGISTER(CP_PERFCOUNTER_HI) + +START_REGISTER(CP_BIN_MASK_LO) + GENERATE_FIELD(BIN_MASK_LO, int) +END_REGISTER(CP_BIN_MASK_LO) + +START_REGISTER(CP_BIN_MASK_HI) + GENERATE_FIELD(BIN_MASK_HI, int) +END_REGISTER(CP_BIN_MASK_HI) + +START_REGISTER(CP_BIN_SELECT_LO) + GENERATE_FIELD(BIN_SELECT_LO, int) +END_REGISTER(CP_BIN_SELECT_LO) + +START_REGISTER(CP_BIN_SELECT_HI) + GENERATE_FIELD(BIN_SELECT_HI, int) +END_REGISTER(CP_BIN_SELECT_HI) + +START_REGISTER(CP_NV_FLAGS_0) + GENERATE_FIELD(DISCARD_0, int) + GENERATE_FIELD(END_RCVD_0, int) + GENERATE_FIELD(DISCARD_1, int) + GENERATE_FIELD(END_RCVD_1, int) + GENERATE_FIELD(DISCARD_2, int) + GENERATE_FIELD(END_RCVD_2, int) + GENERATE_FIELD(DISCARD_3, int) + GENERATE_FIELD(END_RCVD_3, int) + GENERATE_FIELD(DISCARD_4, int) + GENERATE_FIELD(END_RCVD_4, int) + GENERATE_FIELD(DISCARD_5, int) + GENERATE_FIELD(END_RCVD_5, int) + GENERATE_FIELD(DISCARD_6, int) + GENERATE_FIELD(END_RCVD_6, int) + GENERATE_FIELD(DISCARD_7, int) + GENERATE_FIELD(END_RCVD_7, int) + GENERATE_FIELD(DISCARD_8, int) + GENERATE_FIELD(END_RCVD_8, int) + GENERATE_FIELD(DISCARD_9, int) + GENERATE_FIELD(END_RCVD_9, int) + GENERATE_FIELD(DISCARD_10, int) + GENERATE_FIELD(END_RCVD_10, int) + GENERATE_FIELD(DISCARD_11, int) + GENERATE_FIELD(END_RCVD_11, int) + GENERATE_FIELD(DISCARD_12, int) + GENERATE_FIELD(END_RCVD_12, int) + GENERATE_FIELD(DISCARD_13, int) + GENERATE_FIELD(END_RCVD_13, int) + GENERATE_FIELD(DISCARD_14, int) + GENERATE_FIELD(END_RCVD_14, int) + GENERATE_FIELD(DISCARD_15, int) + GENERATE_FIELD(END_RCVD_15, int) +END_REGISTER(CP_NV_FLAGS_0) + +START_REGISTER(CP_NV_FLAGS_1) + GENERATE_FIELD(DISCARD_16, int) + GENERATE_FIELD(END_RCVD_16, int) + GENERATE_FIELD(DISCARD_17, int) + GENERATE_FIELD(END_RCVD_17, int) + GENERATE_FIELD(DISCARD_18, int) + GENERATE_FIELD(END_RCVD_18, int) + GENERATE_FIELD(DISCARD_19, int) + GENERATE_FIELD(END_RCVD_19, int) + GENERATE_FIELD(DISCARD_20, int) + GENERATE_FIELD(END_RCVD_20, int) + GENERATE_FIELD(DISCARD_21, int) + GENERATE_FIELD(END_RCVD_21, int) + GENERATE_FIELD(DISCARD_22, int) + GENERATE_FIELD(END_RCVD_22, int) + GENERATE_FIELD(DISCARD_23, int) + GENERATE_FIELD(END_RCVD_23, int) + GENERATE_FIELD(DISCARD_24, int) + GENERATE_FIELD(END_RCVD_24, int) + GENERATE_FIELD(DISCARD_25, int) + GENERATE_FIELD(END_RCVD_25, int) + GENERATE_FIELD(DISCARD_26, int) + GENERATE_FIELD(END_RCVD_26, int) + GENERATE_FIELD(DISCARD_27, int) + GENERATE_FIELD(END_RCVD_27, int) + GENERATE_FIELD(DISCARD_28, int) + GENERATE_FIELD(END_RCVD_28, int) + GENERATE_FIELD(DISCARD_29, int) + GENERATE_FIELD(END_RCVD_29, int) + GENERATE_FIELD(DISCARD_30, int) + GENERATE_FIELD(END_RCVD_30, int) + GENERATE_FIELD(DISCARD_31, int) + GENERATE_FIELD(END_RCVD_31, int) +END_REGISTER(CP_NV_FLAGS_1) + +START_REGISTER(CP_NV_FLAGS_2) + GENERATE_FIELD(DISCARD_32, int) + GENERATE_FIELD(END_RCVD_32, int) + GENERATE_FIELD(DISCARD_33, int) + GENERATE_FIELD(END_RCVD_33, int) + GENERATE_FIELD(DISCARD_34, int) + GENERATE_FIELD(END_RCVD_34, int) + GENERATE_FIELD(DISCARD_35, int) + GENERATE_FIELD(END_RCVD_35, int) + GENERATE_FIELD(DISCARD_36, int) + GENERATE_FIELD(END_RCVD_36, int) + GENERATE_FIELD(DISCARD_37, int) + GENERATE_FIELD(END_RCVD_37, int) + GENERATE_FIELD(DISCARD_38, int) + GENERATE_FIELD(END_RCVD_38, int) + GENERATE_FIELD(DISCARD_39, int) + GENERATE_FIELD(END_RCVD_39, int) + GENERATE_FIELD(DISCARD_40, int) + GENERATE_FIELD(END_RCVD_40, int) + GENERATE_FIELD(DISCARD_41, int) + GENERATE_FIELD(END_RCVD_41, int) + GENERATE_FIELD(DISCARD_42, int) + GENERATE_FIELD(END_RCVD_42, int) + GENERATE_FIELD(DISCARD_43, int) + GENERATE_FIELD(END_RCVD_43, int) + GENERATE_FIELD(DISCARD_44, int) + GENERATE_FIELD(END_RCVD_44, int) + GENERATE_FIELD(DISCARD_45, int) + GENERATE_FIELD(END_RCVD_45, int) + GENERATE_FIELD(DISCARD_46, int) + GENERATE_FIELD(END_RCVD_46, int) + GENERATE_FIELD(DISCARD_47, int) + GENERATE_FIELD(END_RCVD_47, int) +END_REGISTER(CP_NV_FLAGS_2) + +START_REGISTER(CP_NV_FLAGS_3) + GENERATE_FIELD(DISCARD_48, int) + GENERATE_FIELD(END_RCVD_48, int) + GENERATE_FIELD(DISCARD_49, int) + GENERATE_FIELD(END_RCVD_49, int) + GENERATE_FIELD(DISCARD_50, int) + GENERATE_FIELD(END_RCVD_50, int) + GENERATE_FIELD(DISCARD_51, int) + GENERATE_FIELD(END_RCVD_51, int) + GENERATE_FIELD(DISCARD_52, int) + GENERATE_FIELD(END_RCVD_52, int) + GENERATE_FIELD(DISCARD_53, int) + GENERATE_FIELD(END_RCVD_53, int) + GENERATE_FIELD(DISCARD_54, int) + GENERATE_FIELD(END_RCVD_54, int) + GENERATE_FIELD(DISCARD_55, int) + GENERATE_FIELD(END_RCVD_55, int) + GENERATE_FIELD(DISCARD_56, int) + GENERATE_FIELD(END_RCVD_56, int) + GENERATE_FIELD(DISCARD_57, int) + GENERATE_FIELD(END_RCVD_57, int) + GENERATE_FIELD(DISCARD_58, int) + GENERATE_FIELD(END_RCVD_58, int) + GENERATE_FIELD(DISCARD_59, int) + GENERATE_FIELD(END_RCVD_59, int) + GENERATE_FIELD(DISCARD_60, int) + GENERATE_FIELD(END_RCVD_60, int) + GENERATE_FIELD(DISCARD_61, int) + GENERATE_FIELD(END_RCVD_61, int) + GENERATE_FIELD(DISCARD_62, int) + GENERATE_FIELD(END_RCVD_62, int) + GENERATE_FIELD(DISCARD_63, int) + GENERATE_FIELD(END_RCVD_63, int) +END_REGISTER(CP_NV_FLAGS_3) + +START_REGISTER(CP_STATE_DEBUG_INDEX) + GENERATE_FIELD(STATE_DEBUG_INDEX, int) +END_REGISTER(CP_STATE_DEBUG_INDEX) + +START_REGISTER(CP_STATE_DEBUG_DATA) + GENERATE_FIELD(STATE_DEBUG_DATA, int) +END_REGISTER(CP_STATE_DEBUG_DATA) + +START_REGISTER(CP_PROG_COUNTER) + GENERATE_FIELD(COUNTER, int) +END_REGISTER(CP_PROG_COUNTER) + +START_REGISTER(CP_STAT) + GENERATE_FIELD(MIU_WR_BUSY, int) + GENERATE_FIELD(MIU_RD_REQ_BUSY, int) + GENERATE_FIELD(MIU_RD_RETURN_BUSY, int) + GENERATE_FIELD(RBIU_BUSY, int) + GENERATE_FIELD(RCIU_BUSY, int) + GENERATE_FIELD(CSF_RING_BUSY, int) + GENERATE_FIELD(CSF_INDIRECTS_BUSY, int) + GENERATE_FIELD(CSF_INDIRECT2_BUSY, int) + GENERATE_FIELD(CSF_ST_BUSY, int) + GENERATE_FIELD(CSF_BUSY, int) + GENERATE_FIELD(RING_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int) + GENERATE_FIELD(ST_QUEUE_BUSY, int) + GENERATE_FIELD(PFP_BUSY, int) + GENERATE_FIELD(MEQ_RING_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int) + GENERATE_FIELD(MIU_WC_STALL, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(_3D_BUSY, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(ME_WC_BUSY, int) + GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int) + GENERATE_FIELD(CP_BUSY, int) +END_REGISTER(CP_STAT) + +START_REGISTER(BIOS_0_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_0_SCRATCH) + +START_REGISTER(BIOS_1_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_1_SCRATCH) + +START_REGISTER(BIOS_2_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_2_SCRATCH) + +START_REGISTER(BIOS_3_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_3_SCRATCH) + +START_REGISTER(BIOS_4_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_4_SCRATCH) + +START_REGISTER(BIOS_5_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_5_SCRATCH) + +START_REGISTER(BIOS_6_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_6_SCRATCH) + +START_REGISTER(BIOS_7_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_7_SCRATCH) + +START_REGISTER(BIOS_8_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_8_SCRATCH) + +START_REGISTER(BIOS_9_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_9_SCRATCH) + +START_REGISTER(BIOS_10_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_10_SCRATCH) + +START_REGISTER(BIOS_11_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_11_SCRATCH) + +START_REGISTER(BIOS_12_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_12_SCRATCH) + +START_REGISTER(BIOS_13_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_13_SCRATCH) + +START_REGISTER(BIOS_14_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_14_SCRATCH) + +START_REGISTER(BIOS_15_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_15_SCRATCH) + +START_REGISTER(COHER_SIZE_PM4) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_PM4) + +START_REGISTER(COHER_BASE_PM4) + GENERATE_FIELD(BASE, int) +END_REGISTER(COHER_BASE_PM4) + +START_REGISTER(COHER_STATUS_PM4) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_PM4) + +START_REGISTER(COHER_SIZE_HOST) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_HOST) + +START_REGISTER(COHER_BASE_HOST) + GENERATE_FIELD(BASE, hex) +END_REGISTER(COHER_BASE_HOST) + +START_REGISTER(COHER_STATUS_HOST) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_HOST) + +START_REGISTER(COHER_DEST_BASE_0) + GENERATE_FIELD(DEST_BASE_0, hex) +END_REGISTER(COHER_DEST_BASE_0) + +START_REGISTER(COHER_DEST_BASE_1) + GENERATE_FIELD(DEST_BASE_1, hex) +END_REGISTER(COHER_DEST_BASE_1) + +START_REGISTER(COHER_DEST_BASE_2) + GENERATE_FIELD(DEST_BASE_2, hex) +END_REGISTER(COHER_DEST_BASE_2) + +START_REGISTER(COHER_DEST_BASE_3) + GENERATE_FIELD(DEST_BASE_3, hex) +END_REGISTER(COHER_DEST_BASE_3) + +START_REGISTER(COHER_DEST_BASE_4) + GENERATE_FIELD(DEST_BASE_4, hex) +END_REGISTER(COHER_DEST_BASE_4) + +START_REGISTER(COHER_DEST_BASE_5) + GENERATE_FIELD(DEST_BASE_5, hex) +END_REGISTER(COHER_DEST_BASE_5) + +START_REGISTER(COHER_DEST_BASE_6) + GENERATE_FIELD(DEST_BASE_6, hex) +END_REGISTER(COHER_DEST_BASE_6) + +START_REGISTER(COHER_DEST_BASE_7) + GENERATE_FIELD(DEST_BASE_7, hex) +END_REGISTER(COHER_DEST_BASE_7) + +START_REGISTER(RB_SURFACE_INFO) + GENERATE_FIELD(SURFACE_PITCH, uint) + GENERATE_FIELD(MSAA_SAMPLES, MSAASamples) +END_REGISTER(RB_SURFACE_INFO) + +START_REGISTER(RB_COLOR_INFO) + GENERATE_FIELD(COLOR_FORMAT, ColorformatX) + GENERATE_FIELD(COLOR_ROUND_MODE, uint) + GENERATE_FIELD(COLOR_LINEAR, bool) + GENERATE_FIELD(COLOR_ENDIAN, uint) + GENERATE_FIELD(COLOR_SWAP, uint) + GENERATE_FIELD(COLOR_BASE, uint) +END_REGISTER(RB_COLOR_INFO) + +START_REGISTER(RB_DEPTH_INFO) + GENERATE_FIELD(DEPTH_FORMAT, DepthformatX) + GENERATE_FIELD(DEPTH_BASE, uint) +END_REGISTER(RB_DEPTH_INFO) + +START_REGISTER(RB_STENCILREFMASK) + GENERATE_FIELD(STENCILREF, hex) + GENERATE_FIELD(STENCILMASK, hex) + GENERATE_FIELD(STENCILWRITEMASK, hex) +END_REGISTER(RB_STENCILREFMASK) + +START_REGISTER(RB_ALPHA_REF) + GENERATE_FIELD(ALPHA_REF, float) +END_REGISTER(RB_ALPHA_REF) + +START_REGISTER(RB_COLOR_MASK) + GENERATE_FIELD(WRITE_RED, bool) + GENERATE_FIELD(WRITE_GREEN, bool) + GENERATE_FIELD(WRITE_BLUE, bool) + GENERATE_FIELD(WRITE_ALPHA, bool) +END_REGISTER(RB_COLOR_MASK) + +START_REGISTER(RB_BLEND_RED) + GENERATE_FIELD(BLEND_RED, uint) +END_REGISTER(RB_BLEND_RED) + +START_REGISTER(RB_BLEND_GREEN) + GENERATE_FIELD(BLEND_GREEN, uint) +END_REGISTER(RB_BLEND_GREEN) + +START_REGISTER(RB_BLEND_BLUE) + GENERATE_FIELD(BLEND_BLUE, uint) +END_REGISTER(RB_BLEND_BLUE) + +START_REGISTER(RB_BLEND_ALPHA) + GENERATE_FIELD(BLEND_ALPHA, uint) +END_REGISTER(RB_BLEND_ALPHA) + +START_REGISTER(RB_FOG_COLOR) + GENERATE_FIELD(FOG_RED, uint) + GENERATE_FIELD(FOG_GREEN, uint) + GENERATE_FIELD(FOG_BLUE, uint) +END_REGISTER(RB_FOG_COLOR) + +START_REGISTER(RB_STENCILREFMASK_BF) + GENERATE_FIELD(STENCILREF_BF, hex) + GENERATE_FIELD(STENCILMASK_BF, hex) + GENERATE_FIELD(STENCILWRITEMASK_BF, hex) +END_REGISTER(RB_STENCILREFMASK_BF) + +START_REGISTER(RB_DEPTHCONTROL) + GENERATE_FIELD(STENCIL_ENABLE, bool) + GENERATE_FIELD(Z_ENABLE, bool) + GENERATE_FIELD(Z_WRITE_ENABLE, bool) + GENERATE_FIELD(EARLY_Z_ENABLE, bool) + GENERATE_FIELD(ZFUNC, CompareFrag) + GENERATE_FIELD(BACKFACE_ENABLE, bool) + GENERATE_FIELD(STENCILFUNC, CompareRef) + GENERATE_FIELD(STENCILFAIL, StencilOp) + GENERATE_FIELD(STENCILZPASS, StencilOp) + GENERATE_FIELD(STENCILZFAIL, StencilOp) + GENERATE_FIELD(STENCILFUNC_BF, CompareRef) + GENERATE_FIELD(STENCILFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILZPASS_BF, StencilOp) + GENERATE_FIELD(STENCILZFAIL_BF, StencilOp) +END_REGISTER(RB_DEPTHCONTROL) + +START_REGISTER(RB_BLENDCONTROL) + GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX) + GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX) + GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX) + GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX) + GENERATE_FIELD(BLEND_FORCE_ENABLE, bool) + GENERATE_FIELD(BLEND_FORCE, bool) +END_REGISTER(RB_BLENDCONTROL) + +START_REGISTER(RB_COLORCONTROL) + GENERATE_FIELD(ALPHA_FUNC, CompareRef) + GENERATE_FIELD(ALPHA_TEST_ENABLE, bool) + GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool) + GENERATE_FIELD(BLEND_DISABLE, bool) + GENERATE_FIELD(FOG_ENABLE, bool) + GENERATE_FIELD(VS_EXPORTS_FOG, bool) + GENERATE_FIELD(ROP_CODE, uint) + GENERATE_FIELD(DITHER_MODE, DitherModeX) + GENERATE_FIELD(DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(PIXEL_FOG, bool) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex) +END_REGISTER(RB_COLORCONTROL) + +START_REGISTER(RB_MODECONTROL) + GENERATE_FIELD(EDRAM_MODE, EdramMode) +END_REGISTER(RB_MODECONTROL) + +START_REGISTER(RB_COLOR_DEST_MASK) + GENERATE_FIELD(COLOR_DEST_MASK, uint) +END_REGISTER(RB_COLOR_DEST_MASK) + +START_REGISTER(RB_COPY_CONTROL) + GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect) + GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool) + GENERATE_FIELD(CLEAR_MASK, uint) +END_REGISTER(RB_COPY_CONTROL) + +START_REGISTER(RB_COPY_DEST_BASE) + GENERATE_FIELD(COPY_DEST_BASE, uint) +END_REGISTER(RB_COPY_DEST_BASE) + +START_REGISTER(RB_COPY_DEST_PITCH) + GENERATE_FIELD(COPY_DEST_PITCH, uint) +END_REGISTER(RB_COPY_DEST_PITCH) + +START_REGISTER(RB_COPY_DEST_INFO) + GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian) + GENERATE_FIELD(COPY_DEST_LINEAR, uint) + GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX) + GENERATE_FIELD(COPY_DEST_SWAP, uint) + GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX) + GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(COPY_MASK_WRITE_RED, hex) + GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex) + GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex) + GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex) +END_REGISTER(RB_COPY_DEST_INFO) + +START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + GENERATE_FIELD(OFFSET_X, uint) + GENERATE_FIELD(OFFSET_Y, uint) +END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + +START_REGISTER(RB_DEPTH_CLEAR) + GENERATE_FIELD(DEPTH_CLEAR, uint) +END_REGISTER(RB_DEPTH_CLEAR) + +START_REGISTER(RB_SAMPLE_COUNT_CTL) + GENERATE_FIELD(RESET_SAMPLE_COUNT, bool) + GENERATE_FIELD(COPY_SAMPLE_COUNT, bool) +END_REGISTER(RB_SAMPLE_COUNT_CTL) + +START_REGISTER(RB_SAMPLE_COUNT_ADDR) + GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint) +END_REGISTER(RB_SAMPLE_COUNT_ADDR) + +START_REGISTER(RB_BC_CONTROL) + GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint) + GENERATE_FIELD(DISABLE_EDRAM_CAM, bool) + GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool) + GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool) + GENERATE_FIELD(AZ_THROTTLE_COUNT, uint) + GENERATE_FIELD(ENABLE_CRC_UPDATE, bool) + GENERATE_FIELD(CRC_MODE, bool) + GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool) + GENERATE_FIELD(DISABLE_ACCUM, bool) + GENERATE_FIELD(ACCUM_ALLOC_MASK, uint) + GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool) + GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int) + GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(RESERVED9, bool) + GENERATE_FIELD(RESERVED10, bool) +END_REGISTER(RB_BC_CONTROL) + +START_REGISTER(RB_EDRAM_INFO) + GENERATE_FIELD(EDRAM_SIZE, EdramSizeX) + GENERATE_FIELD(EDRAM_MAPPING_MODE, uint) + GENERATE_FIELD(EDRAM_RANGE, hex) +END_REGISTER(RB_EDRAM_INFO) + +START_REGISTER(RB_CRC_RD_PORT) + GENERATE_FIELD(CRC_DATA, hex) +END_REGISTER(RB_CRC_RD_PORT) + +START_REGISTER(RB_CRC_CONTROL) + GENERATE_FIELD(CRC_RD_ADVANCE, bool) +END_REGISTER(RB_CRC_CONTROL) + +START_REGISTER(RB_CRC_MASK) + GENERATE_FIELD(CRC_MASK, hex) +END_REGISTER(RB_CRC_MASK) + +START_REGISTER(RB_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT) +END_REGISTER(RB_PERFCOUNTER0_SELECT) + +START_REGISTER(RB_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_LOW) + +START_REGISTER(RB_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_HI) + +START_REGISTER(RB_TOTAL_SAMPLES) + GENERATE_FIELD(TOTAL_SAMPLES, int) +END_REGISTER(RB_TOTAL_SAMPLES) + +START_REGISTER(RB_ZPASS_SAMPLES) + GENERATE_FIELD(ZPASS_SAMPLES, int) +END_REGISTER(RB_ZPASS_SAMPLES) + +START_REGISTER(RB_ZFAIL_SAMPLES) + GENERATE_FIELD(ZFAIL_SAMPLES, int) +END_REGISTER(RB_ZFAIL_SAMPLES) + +START_REGISTER(RB_SFAIL_SAMPLES) + GENERATE_FIELD(SFAIL_SAMPLES, int) +END_REGISTER(RB_SFAIL_SAMPLES) + +START_REGISTER(RB_DEBUG_0) + GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_Z1_FULL, bool) + GENERATE_FIELD(RDREQ_Z0_FULL, bool) + GENERATE_FIELD(RDREQ_C1_FULL, bool) + GENERATE_FIELD(RDREQ_C0_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool) + GENERATE_FIELD(WRREQ_Z1_FULL, bool) + GENERATE_FIELD(WRREQ_Z0_FULL, bool) + GENERATE_FIELD(WRREQ_C1_FULL, bool) + GENERATE_FIELD(WRREQ_C0_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool) + GENERATE_FIELD(C_SX_LAT_FULL, bool) + GENERATE_FIELD(C_SX_CMD_FULL, bool) + GENERATE_FIELD(C_EZ_TILE_FULL, bool) + GENERATE_FIELD(C_REQ_FULL, bool) + GENERATE_FIELD(C_MASK_FULL, bool) + GENERATE_FIELD(EZ_INFSAMP_FULL, bool) +END_REGISTER(RB_DEBUG_0) + +START_REGISTER(RB_DEBUG_1) + GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z1_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z0_EMPTY, bool) + GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool) + GENERATE_FIELD(C_SX_LAT_EMPTY, bool) + GENERATE_FIELD(C_SX_CMD_EMPTY, bool) + GENERATE_FIELD(C_EZ_TILE_EMPTY, bool) + GENERATE_FIELD(C_REQ_EMPTY, bool) + GENERATE_FIELD(C_MASK_EMPTY, bool) + GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool) +END_REGISTER(RB_DEBUG_1) + +START_REGISTER(RB_DEBUG_2) + GENERATE_FIELD(TILE_FIFO_COUNT, bool) + GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool) + GENERATE_FIELD(MEM_EXPORT_FLAG, bool) + GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool) + GENERATE_FIELD(CURRENT_TILE_EVENT, bool) + GENERATE_FIELD(EZ_INFTILE_FULL, bool) + GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool) + GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool) + GENERATE_FIELD(Z0_MASK_FULL, bool) + GENERATE_FIELD(Z1_MASK_FULL, bool) + GENERATE_FIELD(Z0_REQ_FULL, bool) + GENERATE_FIELD(Z1_REQ_FULL, bool) + GENERATE_FIELD(Z_SAMP_FULL, bool) + GENERATE_FIELD(Z_TILE_FULL, bool) + GENERATE_FIELD(EZ_INFTILE_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool) + GENERATE_FIELD(Z0_MASK_EMPTY, bool) + GENERATE_FIELD(Z1_MASK_EMPTY, bool) + GENERATE_FIELD(Z0_REQ_EMPTY, bool) + GENERATE_FIELD(Z1_REQ_EMPTY, bool) + GENERATE_FIELD(Z_SAMP_EMPTY, bool) + GENERATE_FIELD(Z_TILE_EMPTY, bool) +END_REGISTER(RB_DEBUG_2) + +START_REGISTER(RB_DEBUG_3) + GENERATE_FIELD(ACCUM_VALID, bool) + GENERATE_FIELD(ACCUM_FLUSHING, bool) + GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool) + GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool) + GENERATE_FIELD(SHD_FULL, bool) + GENERATE_FIELD(SHD_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool) + GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool) + GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool) + GENERATE_FIELD(ZEXP_LOWER_FULL, bool) + GENERATE_FIELD(ZEXP_UPPER_FULL, bool) +END_REGISTER(RB_DEBUG_3) + +START_REGISTER(RB_DEBUG_4) + GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool) + GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool) + GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool) +END_REGISTER(RB_DEBUG_4) + +START_REGISTER(RB_FLAG_CONTROL) + GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool) +END_REGISTER(RB_FLAG_CONTROL) + +START_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray) + GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray) + GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray) + GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX) +END_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + +START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX) +END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h new file mode 100644 index 000000000000..0e32e421d0a3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h @@ -0,0 +1,95 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _R400IPT_H_ +#define _R400IPT_H_ + +// Hand-generated list from Yamato_PM4_Spec.doc + +#define PM4_PACKET0_NOP 0x00000000 // Empty type-0 packet header +#define PM4_PACKET1_NOP 0x40000000 // Empty type-1 packet header +#define PM4_PACKET2_NOP 0x80000000 // Empty type-2 packet header (reserved) + +#define PM4_COUNT_SHIFT 16 +#define PM4_COUNT_MASK +#define PM4_PACKET_COUNT(__x) ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000) +// Type 3 packet headers + +#define PM4_PACKET3_NOP 0xC0001000 // Do nothing. +#define PM4_PACKET3_IB_PREFETCH_END 0xC0001700 // Internal Packet Used Only by CP +#define PM4_PACKET3_SUBBLK_PREFETCH 0xC0001F00 // Internal Packet Used Only by CP + +#define PM4_PACKET3_INSTR_PREFETCH 0xC0002000 // Internal Packet Used Only by CP +#define PM4_PACKET3_REG_RMW 0xC0002100 // Register Read-Modify-Write New for R400 +#define PM4_PACKET3_DRAW_INDX 0xC0002200 // Initiate fetch of index buffer New for R400 +#define PM4_PACKET3_VIZ_QUERY 0xC0002300 // Begin/End initiator for Viz Query extent processing New for R400 +#define PM4_PACKET3_SET_STATE 0xC0002500 // Fetch State Sub-Blocks and Initiate Shader Code DMAs New for R400 +#define PM4_PACKET3_WAIT_FOR_IDLE 0xC0002600 // Wait for the engine to be idle. +#define PM4_PACKET3_IM_LOAD 0xC0002700 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_IM_LOAD_IMMEDIATE 0xC0002B00 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_SET_CONSTANT 0xC0002D00 // Load Constant Into Chip & Shadow to Memory New for R400 +#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT 0xC0002E00 // Load All Constants from a Location in Memory New for R400 +#define PM4_PACKET3_LOAD_ALU_CONSTANT 0xC0002F00 // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants + +#define PM4_PACKET3_DRAW_INDX_BIN 0xC0003400 // Initiate fetch of index buffer and BIN info used for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2_BIN 0xC0003500 // Draw using supplied indices and initiate fetch of BIN info for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2 0xC0003600 // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt +#define PM4_PACKET3_INDIRECT_BUFFER_PFD 0xC0003700 +#define PM4_PACKET3_INVALIDATE_STATE 0xC0003B00 // Selective Invalidation of State Pointers New for R400 +#define PM4_PACKET3_WAIT_REG_MEM 0xC0003C00 // Wait Until a Register or Memory Location is a Specific Value. New for R400 +#define PM4_PACKET3_MEM_WRITE 0xC0003D00 // Write DWORD to Memory For Synchronization New for R400 +#define PM4_PACKET3_REG_TO_MEM 0xC0003E00 // Reads Register in Chip and Writes to Memory New for R400 +#define PM4_PACKET3_INDIRECT_BUFFER 0xC0003F00 // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer. Supported + +#define PM4_PACKET3_CP_INTERRUPT 0xC0004000 // Generate Interrupt from the Command Stream New for R400 +#define PM4_PACKET3_COND_EXEC 0xC0004400 // Conditional execution of a sequence of packets +#define PM4_PACKET3_COND_WRITE 0xC0004500 // Conditional Write to Memory New for R400 +#define PM4_PACKET3_EVENT_WRITE 0xC0004600 // Generate An Event that Creates a Write to Memory when Completed New for R400 +#define PM4_PACKET3_INSTR_MATCH 0xC0004700 // Internal Packet Used Only by CP +#define PM4_PACKET3_ME_INIT 0xC0004800 // Initialize CP's Micro Engine New for R400 +#define PM4_PACKET3_CONST_PREFETCH 0xC0004900 // Internal packet used only by CP +#define PM4_PACKET3_MEM_WRITE_CNTR 0xC0004F00 + +#define PM4_PACKET3_SET_BIN_MASK 0xC0005000 // Sets the 64-bit BIN_MASK register in the PFP +#define PM4_PACKET3_SET_BIN_SELECT 0xC0005100 // Sets the 64-bit BIN_SELECT register in the PFP +#define PM4_PACKET3_WAIT_REG_EQ 0xC0005200 // Wait until a register location is equal to a specific value +#define PM4_PACKET3_WAIT_REG_GTE 0xC0005300 // Wait until a register location is greater than or equal to a specific value +#define PM4_PACKET3_INCR_UPDT_STATE 0xC0005500 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_CONST 0xC0005600 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_INSTR 0xC0005700 // Internal Packet Used Only by CP +#define PM4_PACKET3_EVENT_WRITE_SHD 0xC0005800 // Generate a VS|PS_Done Event. +#define PM4_PACKET3_EVENT_WRITE_CFL 0xC0005900 // Generate a Cach Flush Done Event +#define PM4_PACKET3_EVENT_WRITE_ZPD 0xC0005B00 // Generate a Cach Flush Done Event +#define PM4_PACKET3_WAIT_UNTIL_READ 0xC0005C00 // Wait Until a Read completes. +#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE 0xC0005D00 // Wait Until all Base/Size writes from an IB_PFD packet have completed. +#define PM4_PACKET3_CONTEXT_UPDATE 0xC0005E00 // Updates the current context if needed. + + /****** New Opcodes For R400 (all decode values are TBD) ******/ + + +#endif // _R400IPT_H_ diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h new file mode 100644 index 000000000000..ad3d829bc94e --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h @@ -0,0 +1,5739 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_MASK_HEADER) +#define _yamato_MASK_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_XY_FMT 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_Z_FMT 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__VTX_W0_FMT 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF 0x00000800L + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE 0x00010000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR 0x00200000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN 0x00400000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK 0x00800000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN 0x00800000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN 0x01000000L + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA 0x00000001L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_CL_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_SC_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__PIX_CENTER 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_FRONT 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__CULL_BACK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__FACE 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE 0x00002000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK 0x00008000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE 0x00008000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE 0x00010000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK 0x00040000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE 0x00040000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA 0x00200000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK 0x00800000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE 0x00800000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x00007fffL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0x7fff0000L + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK_MASK 0x0000ffffL + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL_MASK 0x000000ffL +#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK 0x00000100L +#define PA_SC_LINE_CNTL__USE_BRES_CNTL 0x00000100L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__LAST_PIXEL 0x00000400L + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x3fff0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE 0x80000000L + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x3fff0000L + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0x7fff0000L + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0x7fff0000L + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK 0x0000003eL +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK 0x00000080L +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z 0x00000080L + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK 0xffffffffL + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +#define PA_CL_CNTL_STATUS__CL_BUSY 0x80000000L + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +#define PA_SU_CNTL_STATUS__SU_BUSY 0x80000000L + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY_MASK 0x80000000L +#define PA_SC_CNTL_STATUS__SC_BUSY 0x80000000L + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00000008L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full 0x00000008L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full 0x00000020L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00000080L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full 0x00000080L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00000800L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full 0x00000800L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00002000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full 0x00002000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full 0x00020000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full 0x00080000L +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xfff00000L + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00380000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff000000L + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK 0x001fffffL +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK 0x7f000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK 0x00000007L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK 0x00000070L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK 0x000fff00L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK 0x00000007L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK 0x00000070L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event 0x00000080L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK 0xffffff00L + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK 0x00000006L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK 0x00030000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK 0xf0000000L + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK 0x00000001L +#define CLIPPER_DEBUG_REG09__clprim_in_back_event 0x00000001L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK 0x000000c0L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK 0x00003000L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK 0x000c0000L +#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK 0x00100000L +#define CLIPPER_DEBUG_REG09__prim_back_valid 0x00100000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK 0x20000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full 0x20000000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK 0x00000030L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK 0x00000c00L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK 0x00030000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK 0x00180000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK 0xfffffff0L + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK 0x00200000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid 0x00200000L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK 0xffc00000L + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK 0x000007f0L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK 0x00003800L +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK 0xf8000000L + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK 0x00000380L +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x00001c00L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK 0x0000e000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx 0x00010000L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK 0x00060000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x00780000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3f800000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel 0x80000000L + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK 0x00000003L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK 0x0000000cL +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK 0x00000780L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00007000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector 0x00008000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK 0x000f0000L +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG1__aux_sel 0x00100000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK 0x00600000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK 0x01800000L +#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK 0xfe000000L + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent_MASK 0x00000001L +#define SXIFCCG_DEBUG_REG2__sx_sent 0x00000001L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK 0x00000002L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3 0x00000002L +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_aux 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x000001f8L +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x0000fe00L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2 0x00010000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx 0x00020000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK 0x000c0000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK 0x03c00000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x04000000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded 0x04000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK 0xe0000000L + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK 0x00000010L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3 0x00000010L +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x000000e0L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK 0x00000f00L +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00003000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full 0x00008000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK 0x00030000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x00080000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full 0x00080000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x00200000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full 0x00200000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK 0xffc00000L + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000001fL +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x000007e0L +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00000800L +#define SETUP_DEBUG_REG0__ge_stallb 0x00000800L +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00001000L +#define SETUP_DEBUG_REG0__geom_enable 0x00001000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00004000L +#define SETUP_DEBUG_REG0__su_clip_rtr 0x00004000L +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00008000L +#define SETUP_DEBUG_REG0__pfifo_busy 0x00008000L +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00010000L +#define SETUP_DEBUG_REG0__su_cntl_busy 0x00010000L +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00020000L +#define SETUP_DEBUG_REG0__geom_busy 0x00020000L + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00000800L +#define SETUP_DEBUG_REG4__null_prim_gated 0x00000800L +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00001000L +#define SETUP_DEBUG_REG4__backfacing_gated 0x00001000L +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x0000e000L +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00010000L +#define SETUP_DEBUG_REG4__clipped_gated 0x00010000L +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x000e0000L +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00100000L +#define SETUP_DEBUG_REG4__xmajor_gated 0x00100000L +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x00600000L +#define SETUP_DEBUG_REG4__type_gated_MASK 0x03800000L +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x04000000L +#define SETUP_DEBUG_REG4__fpov_gated 0x04000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK 0x08000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated 0x08000000L +#define SETUP_DEBUG_REG4__event_gated_MASK 0x10000000L +#define SETUP_DEBUG_REG4__event_gated 0x10000000L +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x20000000L +#define SETUP_DEBUG_REG4__eop_gated 0x20000000L + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x003ff800L +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x00c00000L +#define SETUP_DEBUG_REG5__event_id_gated_MASK 0x1f000000L + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000001fL + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1_MASK 0x00000001L +#define SC_DEBUG_0__pa_freeze_b1 0x00000001L +#define SC_DEBUG_0__pa_sc_valid_MASK 0x00000002L +#define SC_DEBUG_0__pa_sc_valid 0x00000002L +#define SC_DEBUG_0__pa_sc_phase_MASK 0x0000001cL +#define SC_DEBUG_0__cntx_cnt_MASK 0x00000fe0L +#define SC_DEBUG_0__decr_cntx_cnt_MASK 0x00001000L +#define SC_DEBUG_0__decr_cntx_cnt 0x00001000L +#define SC_DEBUG_0__incr_cntx_cnt_MASK 0x00002000L +#define SC_DEBUG_0__incr_cntx_cnt 0x00002000L +#define SC_DEBUG_0__trigger_MASK 0x80000000L +#define SC_DEBUG_0__trigger 0x80000000L + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state_MASK 0x00000007L +#define SC_DEBUG_1__em1_data_ready_MASK 0x00000008L +#define SC_DEBUG_1__em1_data_ready 0x00000008L +#define SC_DEBUG_1__em2_data_ready_MASK 0x00000010L +#define SC_DEBUG_1__em2_data_ready 0x00000010L +#define SC_DEBUG_1__move_em1_to_em2_MASK 0x00000020L +#define SC_DEBUG_1__move_em1_to_em2 0x00000020L +#define SC_DEBUG_1__ef_data_ready_MASK 0x00000040L +#define SC_DEBUG_1__ef_data_ready 0x00000040L +#define SC_DEBUG_1__ef_state_MASK 0x00000180L +#define SC_DEBUG_1__pipe_valid_MASK 0x00000200L +#define SC_DEBUG_1__pipe_valid 0x00000200L +#define SC_DEBUG_1__trigger_MASK 0x80000000L +#define SC_DEBUG_1__trigger 0x80000000L + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly_MASK 0x00000001L +#define SC_DEBUG_2__rc_rtr_dly 0x00000001L +#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK 0x00000002L +#define SC_DEBUG_2__qmask_ff_alm_full_d1 0x00000002L +#define SC_DEBUG_2__pipe_freeze_b_MASK 0x00000008L +#define SC_DEBUG_2__pipe_freeze_b 0x00000008L +#define SC_DEBUG_2__prim_rts_MASK 0x00000010L +#define SC_DEBUG_2__prim_rts 0x00000010L +#define SC_DEBUG_2__next_prim_rts_dly_MASK 0x00000020L +#define SC_DEBUG_2__next_prim_rts_dly 0x00000020L +#define SC_DEBUG_2__next_prim_rtr_dly_MASK 0x00000040L +#define SC_DEBUG_2__next_prim_rtr_dly 0x00000040L +#define SC_DEBUG_2__pre_stage1_rts_d1_MASK 0x00000080L +#define SC_DEBUG_2__pre_stage1_rts_d1 0x00000080L +#define SC_DEBUG_2__stage0_rts_MASK 0x00000100L +#define SC_DEBUG_2__stage0_rts 0x00000100L +#define SC_DEBUG_2__phase_rts_dly_MASK 0x00000200L +#define SC_DEBUG_2__phase_rts_dly 0x00000200L +#define SC_DEBUG_2__end_of_prim_s1_dly_MASK 0x00008000L +#define SC_DEBUG_2__end_of_prim_s1_dly 0x00008000L +#define SC_DEBUG_2__pass_empty_prim_s1_MASK 0x00010000L +#define SC_DEBUG_2__pass_empty_prim_s1 0x00010000L +#define SC_DEBUG_2__event_id_s1_MASK 0x003e0000L +#define SC_DEBUG_2__event_s1_MASK 0x00400000L +#define SC_DEBUG_2__event_s1 0x00400000L +#define SC_DEBUG_2__trigger_MASK 0x80000000L +#define SC_DEBUG_2__trigger 0x80000000L + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1_MASK 0x000007ffL +#define SC_DEBUG_3__y_curr_s1_MASK 0x003ff800L +#define SC_DEBUG_3__trigger_MASK 0x80000000L +#define SC_DEBUG_3__trigger 0x80000000L + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1_MASK 0x00003fffL +#define SC_DEBUG_4__y_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_4__y_dir_s1_MASK 0x10000000L +#define SC_DEBUG_4__y_dir_s1 0x10000000L +#define SC_DEBUG_4__trigger_MASK 0x80000000L +#define SC_DEBUG_4__trigger 0x80000000L + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1_MASK 0x00003fffL +#define SC_DEBUG_5__x_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_5__x_dir_s1_MASK 0x10000000L +#define SC_DEBUG_5__x_dir_s1 0x10000000L +#define SC_DEBUG_5__trigger_MASK 0x80000000L +#define SC_DEBUG_5__trigger 0x80000000L + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty_MASK 0x00000001L +#define SC_DEBUG_6__z_ff_empty 0x00000001L +#define SC_DEBUG_6__qmcntl_ff_empty_MASK 0x00000002L +#define SC_DEBUG_6__qmcntl_ff_empty 0x00000002L +#define SC_DEBUG_6__xy_ff_empty_MASK 0x00000004L +#define SC_DEBUG_6__xy_ff_empty 0x00000004L +#define SC_DEBUG_6__event_flag_MASK 0x00000008L +#define SC_DEBUG_6__event_flag 0x00000008L +#define SC_DEBUG_6__z_mask_needed_MASK 0x00000010L +#define SC_DEBUG_6__z_mask_needed 0x00000010L +#define SC_DEBUG_6__state_MASK 0x000000e0L +#define SC_DEBUG_6__state_delayed_MASK 0x00000700L +#define SC_DEBUG_6__data_valid_MASK 0x00000800L +#define SC_DEBUG_6__data_valid 0x00000800L +#define SC_DEBUG_6__data_valid_d_MASK 0x00001000L +#define SC_DEBUG_6__data_valid_d 0x00001000L +#define SC_DEBUG_6__tilex_delayed_MASK 0x003fe000L +#define SC_DEBUG_6__tiley_delayed_MASK 0x7fc00000L +#define SC_DEBUG_6__trigger_MASK 0x80000000L +#define SC_DEBUG_6__trigger 0x80000000L + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag_MASK 0x00000001L +#define SC_DEBUG_7__event_flag 0x00000001L +#define SC_DEBUG_7__deallocate_MASK 0x0000000eL +#define SC_DEBUG_7__fpos_MASK 0x00000010L +#define SC_DEBUG_7__fpos 0x00000010L +#define SC_DEBUG_7__sr_prim_we_MASK 0x00000020L +#define SC_DEBUG_7__sr_prim_we 0x00000020L +#define SC_DEBUG_7__last_tile_MASK 0x00000040L +#define SC_DEBUG_7__last_tile 0x00000040L +#define SC_DEBUG_7__tile_ff_we_MASK 0x00000080L +#define SC_DEBUG_7__tile_ff_we 0x00000080L +#define SC_DEBUG_7__qs_data_valid_MASK 0x00000100L +#define SC_DEBUG_7__qs_data_valid 0x00000100L +#define SC_DEBUG_7__qs_q0_y_MASK 0x00000600L +#define SC_DEBUG_7__qs_q0_x_MASK 0x00001800L +#define SC_DEBUG_7__qs_q0_valid_MASK 0x00002000L +#define SC_DEBUG_7__qs_q0_valid 0x00002000L +#define SC_DEBUG_7__prim_ff_we_MASK 0x00004000L +#define SC_DEBUG_7__prim_ff_we 0x00004000L +#define SC_DEBUG_7__tile_ff_re_MASK 0x00008000L +#define SC_DEBUG_7__tile_ff_re 0x00008000L +#define SC_DEBUG_7__fw_prim_data_valid_MASK 0x00010000L +#define SC_DEBUG_7__fw_prim_data_valid 0x00010000L +#define SC_DEBUG_7__last_quad_of_tile_MASK 0x00020000L +#define SC_DEBUG_7__last_quad_of_tile 0x00020000L +#define SC_DEBUG_7__first_quad_of_tile_MASK 0x00040000L +#define SC_DEBUG_7__first_quad_of_tile 0x00040000L +#define SC_DEBUG_7__first_quad_of_prim_MASK 0x00080000L +#define SC_DEBUG_7__first_quad_of_prim 0x00080000L +#define SC_DEBUG_7__new_prim_MASK 0x00100000L +#define SC_DEBUG_7__new_prim 0x00100000L +#define SC_DEBUG_7__load_new_tile_data_MASK 0x00200000L +#define SC_DEBUG_7__load_new_tile_data 0x00200000L +#define SC_DEBUG_7__state_MASK 0x00c00000L +#define SC_DEBUG_7__fifos_ready_MASK 0x01000000L +#define SC_DEBUG_7__fifos_ready 0x01000000L +#define SC_DEBUG_7__trigger_MASK 0x80000000L +#define SC_DEBUG_7__trigger 0x80000000L + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last_MASK 0x00000001L +#define SC_DEBUG_8__sample_last 0x00000001L +#define SC_DEBUG_8__sample_mask_MASK 0x0000001eL +#define SC_DEBUG_8__sample_y_MASK 0x00000060L +#define SC_DEBUG_8__sample_x_MASK 0x00000180L +#define SC_DEBUG_8__sample_send_MASK 0x00000200L +#define SC_DEBUG_8__sample_send 0x00000200L +#define SC_DEBUG_8__next_cycle_MASK 0x00000c00L +#define SC_DEBUG_8__ez_sample_ff_full_MASK 0x00001000L +#define SC_DEBUG_8__ez_sample_ff_full 0x00001000L +#define SC_DEBUG_8__rb_sc_samp_rtr_MASK 0x00002000L +#define SC_DEBUG_8__rb_sc_samp_rtr 0x00002000L +#define SC_DEBUG_8__num_samples_MASK 0x0000c000L +#define SC_DEBUG_8__last_quad_of_tile_MASK 0x00010000L +#define SC_DEBUG_8__last_quad_of_tile 0x00010000L +#define SC_DEBUG_8__last_quad_of_prim_MASK 0x00020000L +#define SC_DEBUG_8__last_quad_of_prim 0x00020000L +#define SC_DEBUG_8__first_quad_of_prim_MASK 0x00040000L +#define SC_DEBUG_8__first_quad_of_prim 0x00040000L +#define SC_DEBUG_8__sample_we_MASK 0x00080000L +#define SC_DEBUG_8__sample_we 0x00080000L +#define SC_DEBUG_8__fpos_MASK 0x00100000L +#define SC_DEBUG_8__fpos 0x00100000L +#define SC_DEBUG_8__event_id_MASK 0x03e00000L +#define SC_DEBUG_8__event_flag_MASK 0x04000000L +#define SC_DEBUG_8__event_flag 0x04000000L +#define SC_DEBUG_8__fw_prim_data_valid_MASK 0x08000000L +#define SC_DEBUG_8__fw_prim_data_valid 0x08000000L +#define SC_DEBUG_8__trigger_MASK 0x80000000L +#define SC_DEBUG_8__trigger 0x80000000L + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send_MASK 0x00000001L +#define SC_DEBUG_9__rb_sc_send 0x00000001L +#define SC_DEBUG_9__rb_sc_ez_mask_MASK 0x0000001eL +#define SC_DEBUG_9__fifo_data_ready_MASK 0x00000020L +#define SC_DEBUG_9__fifo_data_ready 0x00000020L +#define SC_DEBUG_9__early_z_enable_MASK 0x00000040L +#define SC_DEBUG_9__early_z_enable 0x00000040L +#define SC_DEBUG_9__mask_state_MASK 0x00000180L +#define SC_DEBUG_9__next_ez_mask_MASK 0x01fffe00L +#define SC_DEBUG_9__mask_ready_MASK 0x02000000L +#define SC_DEBUG_9__mask_ready 0x02000000L +#define SC_DEBUG_9__drop_sample_MASK 0x04000000L +#define SC_DEBUG_9__drop_sample 0x04000000L +#define SC_DEBUG_9__fetch_new_sample_data_MASK 0x08000000L +#define SC_DEBUG_9__fetch_new_sample_data 0x08000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK 0x10000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask 0x10000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK 0x40000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data 0x40000000L +#define SC_DEBUG_9__trigger_MASK 0x80000000L +#define SC_DEBUG_9__trigger 0x80000000L + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask_MASK 0x0000ffffL +#define SC_DEBUG_10__trigger_MASK 0x80000000L +#define SC_DEBUG_10__trigger 0x80000000L + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready_MASK 0x00000001L +#define SC_DEBUG_11__ez_sample_data_ready 0x00000001L +#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK 0x00000002L +#define SC_DEBUG_11__pkr_fetch_new_sample_data 0x00000002L +#define SC_DEBUG_11__ez_prim_data_ready_MASK 0x00000004L +#define SC_DEBUG_11__ez_prim_data_ready 0x00000004L +#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK 0x00000008L +#define SC_DEBUG_11__pkr_fetch_new_prim_data 0x00000008L +#define SC_DEBUG_11__iterator_input_fz_MASK 0x00000010L +#define SC_DEBUG_11__iterator_input_fz 0x00000010L +#define SC_DEBUG_11__packer_send_quads_MASK 0x00000020L +#define SC_DEBUG_11__packer_send_quads 0x00000020L +#define SC_DEBUG_11__packer_send_cmd_MASK 0x00000040L +#define SC_DEBUG_11__packer_send_cmd 0x00000040L +#define SC_DEBUG_11__packer_send_event_MASK 0x00000080L +#define SC_DEBUG_11__packer_send_event 0x00000080L +#define SC_DEBUG_11__next_state_MASK 0x00000700L +#define SC_DEBUG_11__state_MASK 0x00003800L +#define SC_DEBUG_11__stall_MASK 0x00004000L +#define SC_DEBUG_11__stall 0x00004000L +#define SC_DEBUG_11__trigger_MASK 0x80000000L +#define SC_DEBUG_11__trigger 0x80000000L + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff_MASK 0x00000001L +#define SC_DEBUG_12__SQ_iterator_free_buff 0x00000001L +#define SC_DEBUG_12__event_id_MASK 0x0000003eL +#define SC_DEBUG_12__event_flag_MASK 0x00000040L +#define SC_DEBUG_12__event_flag 0x00000040L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK 0x00000080L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly 0x00000080L +#define SC_DEBUG_12__itercmdfifo_full_MASK 0x00000100L +#define SC_DEBUG_12__itercmdfifo_full 0x00000100L +#define SC_DEBUG_12__itercmdfifo_empty_MASK 0x00000200L +#define SC_DEBUG_12__itercmdfifo_empty 0x00000200L +#define SC_DEBUG_12__iter_ds_one_clk_command_MASK 0x00000400L +#define SC_DEBUG_12__iter_ds_one_clk_command 0x00000400L +#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_prim0 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_vector_MASK 0x00001000L +#define SC_DEBUG_12__iter_ds_end_of_vector 0x00001000L +#define SC_DEBUG_12__iter_qdhit0_MASK 0x00002000L +#define SC_DEBUG_12__iter_qdhit0 0x00002000L +#define SC_DEBUG_12__bc_use_centers_reg_MASK 0x00004000L +#define SC_DEBUG_12__bc_use_centers_reg 0x00004000L +#define SC_DEBUG_12__bc_output_xy_reg_MASK 0x00008000L +#define SC_DEBUG_12__bc_output_xy_reg 0x00008000L +#define SC_DEBUG_12__iter_phase_out_MASK 0x00030000L +#define SC_DEBUG_12__iter_phase_reg_MASK 0x000c0000L +#define SC_DEBUG_12__iterator_SP_valid_MASK 0x00100000L +#define SC_DEBUG_12__iterator_SP_valid 0x00100000L +#define SC_DEBUG_12__eopv_reg_MASK 0x00200000L +#define SC_DEBUG_12__eopv_reg 0x00200000L +#define SC_DEBUG_12__one_clk_cmd_reg_MASK 0x00400000L +#define SC_DEBUG_12__one_clk_cmd_reg 0x00400000L +#define SC_DEBUG_12__iter_dx_end_of_prim_MASK 0x00800000L +#define SC_DEBUG_12__iter_dx_end_of_prim 0x00800000L +#define SC_DEBUG_12__trigger_MASK 0x80000000L +#define SC_DEBUG_12__trigger 0x80000000L + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define GFX_COPY_STATE__SRC_STATE_ID 0x00000001L + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK 0x0000003fL +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x000000c0L +#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK 0x00000800L +#define VGT_DRAW_INITIATOR__INDEX_SIZE 0x00000800L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00001000L +#define VGT_DRAW_INITIATOR__NOT_EOP 0x00001000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK 0x00002000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX 0x00002000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK 0x00004000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE 0x00004000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK 0x00008000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE 0x00008000L +#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK 0xffff0000L + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_DMA_SIZE__SWAP_MODE_MASK 0xc0000000L + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK 0xffffffffL + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS_MASK 0x00ffffffL + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK 0x000001c0L + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK 0x000001c0L + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0x00ffffffL + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0x00ffffffL + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0x00ffffffL + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x00000007L + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x00000003L + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0x00ffffffL + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC_MASK 0x0000ffffL + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000001fL + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define VGT_LAST_COPY_STATE__SRC_STATE_ID 0x00000001L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00010000L +#define VGT_LAST_COPY_STATE__DST_STATE_ID 0x00010000L + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000001fL + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_BUSY 0x00000001L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY 0x00000004L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY 0x00000008L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY 0x00000010L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY 0x00000020L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_PT_BUSY 0x00000040L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY 0x00000100L + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy_MASK 0x00000001L +#define VGT_DEBUG_REG0__te_grp_busy 0x00000001L +#define VGT_DEBUG_REG0__pt_grp_busy_MASK 0x00000002L +#define VGT_DEBUG_REG0__pt_grp_busy 0x00000002L +#define VGT_DEBUG_REG0__vr_grp_busy_MASK 0x00000004L +#define VGT_DEBUG_REG0__vr_grp_busy 0x00000004L +#define VGT_DEBUG_REG0__dma_request_busy_MASK 0x00000008L +#define VGT_DEBUG_REG0__dma_request_busy 0x00000008L +#define VGT_DEBUG_REG0__out_busy_MASK 0x00000010L +#define VGT_DEBUG_REG0__out_busy 0x00000010L +#define VGT_DEBUG_REG0__grp_backend_busy_MASK 0x00000020L +#define VGT_DEBUG_REG0__grp_backend_busy 0x00000020L +#define VGT_DEBUG_REG0__grp_busy_MASK 0x00000040L +#define VGT_DEBUG_REG0__grp_busy 0x00000040L +#define VGT_DEBUG_REG0__dma_busy_MASK 0x00000080L +#define VGT_DEBUG_REG0__dma_busy 0x00000080L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK 0x00000100L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy 0x00000100L +#define VGT_DEBUG_REG0__rbiu_busy_MASK 0x00000200L +#define VGT_DEBUG_REG0__rbiu_busy 0x00000200L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK 0x00000800L +#define VGT_DEBUG_REG0__vgt_no_dma_busy 0x00000800L +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_extended 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00002000L +#define VGT_DEBUG_REG0__vgt_busy 0x00002000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK 0x00004000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out 0x00004000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK 0x00010000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy 0x00010000L + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read_MASK 0x00000001L +#define VGT_DEBUG_REG1__out_te_data_read 0x00000001L +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x00000002L +#define VGT_DEBUG_REG1__te_out_data_valid 0x00000002L +#define VGT_DEBUG_REG1__out_pt_prim_read_MASK 0x00000004L +#define VGT_DEBUG_REG1__out_pt_prim_read 0x00000004L +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00000008L +#define VGT_DEBUG_REG1__pt_out_prim_valid 0x00000008L +#define VGT_DEBUG_REG1__out_pt_data_read_MASK 0x00000010L +#define VGT_DEBUG_REG1__out_pt_data_read 0x00000010L +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00000020L +#define VGT_DEBUG_REG1__pt_out_indx_valid 0x00000020L +#define VGT_DEBUG_REG1__out_vr_prim_read_MASK 0x00000040L +#define VGT_DEBUG_REG1__out_vr_prim_read 0x00000040L +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00000080L +#define VGT_DEBUG_REG1__vr_out_prim_valid 0x00000080L +#define VGT_DEBUG_REG1__out_vr_indx_read_MASK 0x00000100L +#define VGT_DEBUG_REG1__out_vr_indx_read 0x00000100L +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00000200L +#define VGT_DEBUG_REG1__vr_out_indx_valid 0x00000200L +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00000400L +#define VGT_DEBUG_REG1__te_grp_read 0x00000400L +#define VGT_DEBUG_REG1__grp_te_valid_MASK 0x00000800L +#define VGT_DEBUG_REG1__grp_te_valid 0x00000800L +#define VGT_DEBUG_REG1__pt_grp_read_MASK 0x00001000L +#define VGT_DEBUG_REG1__pt_grp_read 0x00001000L +#define VGT_DEBUG_REG1__grp_pt_valid_MASK 0x00002000L +#define VGT_DEBUG_REG1__grp_pt_valid 0x00002000L +#define VGT_DEBUG_REG1__vr_grp_read_MASK 0x00004000L +#define VGT_DEBUG_REG1__vr_grp_read 0x00004000L +#define VGT_DEBUG_REG1__grp_vr_valid_MASK 0x00008000L +#define VGT_DEBUG_REG1__grp_vr_valid 0x00008000L +#define VGT_DEBUG_REG1__grp_dma_read_MASK 0x00010000L +#define VGT_DEBUG_REG1__grp_dma_read 0x00010000L +#define VGT_DEBUG_REG1__dma_grp_valid_MASK 0x00020000L +#define VGT_DEBUG_REG1__dma_grp_valid 0x00020000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK 0x00040000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read 0x00040000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK 0x00080000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid 0x00080000L +#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG1__MH_VGT_rtr 0x00100000L +#define VGT_DEBUG_REG1__VGT_MH_send_MASK 0x00200000L +#define VGT_DEBUG_REG1__VGT_MH_send 0x00200000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK 0x00400000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr 0x00400000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK 0x00800000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send 0x00800000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr 0x01000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK 0x02000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send 0x02000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr 0x04000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK 0x08000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send 0x08000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr 0x10000000L +#define VGT_DEBUG_REG1__VGT_SQ_send_MASK 0x20000000L +#define VGT_DEBUG_REG1__VGT_SQ_send 0x20000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK 0x40000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q 0x40000000L + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en_MASK 0x00000001L +#define VGT_DEBUG_REG3__vgt_clk_en 0x00000001L +#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK 0x00000002L +#define VGT_DEBUG_REG3__reg_fifos_clk_en 0x00000002L + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG6__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG6__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG6__input_data_valid 0x00000400L +#define VGT_DEBUG_REG6__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG6__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG6__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG6__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG6__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG6__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG6__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG6__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG6__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG6__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG6__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG6__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG6__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG6__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG6__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG6__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG6__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG6__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG6__extract_vector 0x02000000L +#define VGT_DEBUG_REG6__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG6__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG6__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG6__destination_rtr 0x08000000L +#define VGT_DEBUG_REG6__grp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG6__grp_trigger 0x10000000L + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG7__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG7__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG7__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG8__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG8__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG8__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG8__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG9__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG9__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG9__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG9__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG9__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG9__grp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG9__grp_trigger 0x40000000L + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L +#define VGT_DEBUG_REG10__di_state_sel_q_MASK 0x00000010L +#define VGT_DEBUG_REG10__di_state_sel_q 0x00000010L +#define VGT_DEBUG_REG10__last_decr_of_packet_MASK 0x00000020L +#define VGT_DEBUG_REG10__last_decr_of_packet 0x00000020L +#define VGT_DEBUG_REG10__bin_valid_MASK 0x00000040L +#define VGT_DEBUG_REG10__bin_valid 0x00000040L +#define VGT_DEBUG_REG10__read_block_MASK 0x00000080L +#define VGT_DEBUG_REG10__read_block 0x00000080L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK 0x00000100L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read 0x00000100L +#define VGT_DEBUG_REG10__last_bit_enable_q_MASK 0x00000200L +#define VGT_DEBUG_REG10__last_bit_enable_q 0x00000200L +#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK 0x00000400L +#define VGT_DEBUG_REG10__last_bit_end_di_q 0x00000400L +#define VGT_DEBUG_REG10__selected_data_MASK 0x0007f800L +#define VGT_DEBUG_REG10__mask_input_data_MASK 0x07f80000L +#define VGT_DEBUG_REG10__gap_q_MASK 0x08000000L +#define VGT_DEBUG_REG10__gap_q 0x08000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK 0x40000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x 0x40000000L +#define VGT_DEBUG_REG10__grp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG10__grp_trigger 0x80000000L + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG12__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG12__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG12__input_data_valid 0x00000400L +#define VGT_DEBUG_REG12__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG12__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG12__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG12__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG12__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG12__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG12__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG12__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG12__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG12__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG12__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG12__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG12__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG12__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG12__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG12__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG12__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG12__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG12__extract_vector 0x02000000L +#define VGT_DEBUG_REG12__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG12__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG12__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG12__destination_rtr 0x08000000L +#define VGT_DEBUG_REG12__bgrp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG12__bgrp_trigger 0x10000000L + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG13__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG13__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG13__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG14__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG14__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG14__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG14__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG15__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG15__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG15__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG15__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG15__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG15__bgrp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG15__bgrp_trigger 0x40000000L + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty 0x00000002L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK 0x00000004L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read 0x00000004L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we 0x00000008L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK 0x00000080L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we 0x00000080L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK 0x00000100L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill 0x00000100L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK 0x00000200L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid 0x00000200L +#define VGT_DEBUG_REG16__rst_last_bit_MASK 0x00000400L +#define VGT_DEBUG_REG16__rst_last_bit 0x00000400L +#define VGT_DEBUG_REG16__current_state_q_MASK 0x00000800L +#define VGT_DEBUG_REG16__current_state_q 0x00000800L +#define VGT_DEBUG_REG16__old_state_q_MASK 0x00001000L +#define VGT_DEBUG_REG16__old_state_q 0x00001000L +#define VGT_DEBUG_REG16__old_state_en_MASK 0x00002000L +#define VGT_DEBUG_REG16__old_state_en 0x00002000L +#define VGT_DEBUG_REG16__prev_last_bit_q_MASK 0x00004000L +#define VGT_DEBUG_REG16__prev_last_bit_q 0x00004000L +#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK 0x00008000L +#define VGT_DEBUG_REG16__dbl_last_bit_q 0x00008000L +#define VGT_DEBUG_REG16__last_bit_block_q_MASK 0x00010000L +#define VGT_DEBUG_REG16__last_bit_block_q 0x00010000L +#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK 0x00020000L +#define VGT_DEBUG_REG16__ast_bit_block2_q 0x00020000L +#define VGT_DEBUG_REG16__load_empty_reg_MASK 0x00040000L +#define VGT_DEBUG_REG16__load_empty_reg 0x00040000L +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK 0x07f80000L +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable 0x20000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK 0x40000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q 0x40000000L +#define VGT_DEBUG_REG16__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG16__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q_MASK 0x00000001L +#define VGT_DEBUG_REG17__save_read_q 0x00000001L +#define VGT_DEBUG_REG17__extend_read_q_MASK 0x00000002L +#define VGT_DEBUG_REG17__extend_read_q 0x00000002L +#define VGT_DEBUG_REG17__grp_indx_size_MASK 0x0000000cL +#define VGT_DEBUG_REG17__cull_prim_true_MASK 0x00000010L +#define VGT_DEBUG_REG17__cull_prim_true 0x00000010L +#define VGT_DEBUG_REG17__reset_bit2_q_MASK 0x00000020L +#define VGT_DEBUG_REG17__reset_bit2_q 0x00000020L +#define VGT_DEBUG_REG17__reset_bit1_q_MASK 0x00000040L +#define VGT_DEBUG_REG17__reset_bit1_q 0x00000040L +#define VGT_DEBUG_REG17__first_reg_first_q_MASK 0x00000080L +#define VGT_DEBUG_REG17__first_reg_first_q 0x00000080L +#define VGT_DEBUG_REG17__check_second_reg_MASK 0x00000100L +#define VGT_DEBUG_REG17__check_second_reg 0x00000100L +#define VGT_DEBUG_REG17__check_first_reg_MASK 0x00000200L +#define VGT_DEBUG_REG17__check_first_reg 0x00000200L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK 0x00000400L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata 0x00000400L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK 0x00001000L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q 0x00001000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK 0x00004000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q 0x00004000L +#define VGT_DEBUG_REG17__to_second_reg_q_MASK 0x00008000L +#define VGT_DEBUG_REG17__to_second_reg_q 0x00008000L +#define VGT_DEBUG_REG17__roll_over_msk_q_MASK 0x00010000L +#define VGT_DEBUG_REG17__roll_over_msk_q 0x00010000L +#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK 0x00fe0000L +#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK 0x7f000000L +#define VGT_DEBUG_REG17__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG17__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK 0x0000003fL +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK 0x00000fc0L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000L +#define VGT_DEBUG_REG18__dma_mem_full_MASK 0x00008000L +#define VGT_DEBUG_REG18__dma_mem_full 0x00008000L +#define VGT_DEBUG_REG18__dma_ram_re_MASK 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_re 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_we_MASK 0x00020000L +#define VGT_DEBUG_REG18__dma_ram_we 0x00020000L +#define VGT_DEBUG_REG18__dma_mem_empty_MASK 0x00040000L +#define VGT_DEBUG_REG18__dma_mem_empty 0x00040000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK 0x00100000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we 0x00100000L +#define VGT_DEBUG_REG18__bin_mem_full_MASK 0x00200000L +#define VGT_DEBUG_REG18__bin_mem_full 0x00200000L +#define VGT_DEBUG_REG18__bin_ram_we_MASK 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_we 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_re_MASK 0x00800000L +#define VGT_DEBUG_REG18__bin_ram_re 0x00800000L +#define VGT_DEBUG_REG18__bin_mem_empty_MASK 0x01000000L +#define VGT_DEBUG_REG18__bin_mem_empty 0x01000000L +#define VGT_DEBUG_REG18__start_bin_req_MASK 0x02000000L +#define VGT_DEBUG_REG18__start_bin_req 0x02000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK 0x04000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used 0x04000000L +#define VGT_DEBUG_REG18__dma_req_xfer_MASK 0x08000000L +#define VGT_DEBUG_REG18__dma_req_xfer 0x08000000L +#define VGT_DEBUG_REG18__have_valid_bin_req_MASK 0x10000000L +#define VGT_DEBUG_REG18__have_valid_bin_req 0x10000000L +#define VGT_DEBUG_REG18__have_valid_dma_req_MASK 0x20000000L +#define VGT_DEBUG_REG18__have_valid_dma_req 0x20000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK 0x00000001L +#define VGT_DEBUG_REG20__prim_side_indx_valid 0x00000001L +#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_empty 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_re 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_we 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG20__indx_side_fifo_full 0x00000010L +#define VGT_DEBUG_REG20__prim_buffer_empty_MASK 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_empty 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_re_MASK 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_re 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_we_MASK 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_we 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_full_MASK 0x00000100L +#define VGT_DEBUG_REG20__prim_buffer_full 0x00000100L +#define VGT_DEBUG_REG20__indx_buffer_empty_MASK 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_empty 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_re_MASK 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_re 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_we_MASK 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_we 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_full_MASK 0x00001000L +#define VGT_DEBUG_REG20__indx_buffer_full 0x00001000L +#define VGT_DEBUG_REG20__hold_prim_MASK 0x00002000L +#define VGT_DEBUG_REG20__hold_prim 0x00002000L +#define VGT_DEBUG_REG20__sent_cnt_MASK 0x0003c000L +#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK 0x00040000L +#define VGT_DEBUG_REG20__start_of_vtx_vector 0x00040000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK 0x00080000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim 0x00080000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK 0x00100000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim 0x00100000L +#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK 0x03e00000L +#define VGT_DEBUG_REG20__out_trigger_MASK 0x04000000L +#define VGT_DEBUG_REG20__out_trigger 0x04000000L + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK 0x00000001L +#define VGT_DEBUG_REG21__null_terminate_vtx_vector 0x00000001L +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK 0x0000000eL +#define VGT_DEBUG_REG21__alloc_counter_q_MASK 0x00000070L +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK 0x00000380L +#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK 0x00003c00L +#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK 0x0003c000L +#define VGT_DEBUG_REG21__new_packet_q_MASK 0x00040000L +#define VGT_DEBUG_REG21__new_packet_q 0x00040000L +#define VGT_DEBUG_REG21__new_allocate_q_MASK 0x00080000L +#define VGT_DEBUG_REG21__new_allocate_q 0x00080000L +#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK 0x00300000L +#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK 0x00400000L +#define VGT_DEBUG_REG21__inserted_null_prim_q 0x00400000L +#define VGT_DEBUG_REG21__insert_null_prim_MASK 0x00800000L +#define VGT_DEBUG_REG21__insert_null_prim 0x00800000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK 0x01000000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux 0x01000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK 0x02000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux 0x02000000L +#define VGT_DEBUG_REG21__buffered_thread_size_MASK 0x04000000L +#define VGT_DEBUG_REG21__buffered_thread_size 0x04000000L +#define VGT_DEBUG_REG21__out_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG21__out_trigger 0x80000000L + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC_MASK 0xffffffffL + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE_MASK 0x00000001L +#define TC_CNTL_STATUS__L2_INVALIDATE 0x00000001L +#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK 0x000c0000L +#define TC_CNTL_STATUS__TC_BUSY_MASK 0x80000000L +#define TC_CNTL_STATUS__TC_BUSY 0x80000000L + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE_MASK 0xffffffffL + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE_MASK 0xffffffffL + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL +#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK 0x00000100L +#define TCM_CHICKEN__ETC_COLOR_ENDIAN 0x00000100L +#define TCM_CHICKEN__SPARE_MASK 0xfffffe00L + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK 0x00000007L +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK 0x00000038L + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK 0x00000001L +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY 0x00000001L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK 0x00000002L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY 0x00000002L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK 0x00000004L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY 0x00000004L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK 0x00000008L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY 0x00000008L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK 0x00000040L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY 0x00000040L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK 0x00000400L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY 0x00000400L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK 0x00001000L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY 0x00001000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK 0x00002000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY 0x00002000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK 0x00004000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY 0x00004000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK 0x00008000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY 0x00008000L +#define TPC_CNTL_STATUS__TF_TW_RTS_MASK 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_RTS 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_RTR_MASK 0x00080000L +#define TPC_CNTL_STATUS__TF_TW_RTR 0x00080000L +#define TPC_CNTL_STATUS__TW_TA_RTS_MASK 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_RTS 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_RTR_MASK 0x00800000L +#define TPC_CNTL_STATUS__TW_TA_RTR 0x00800000L +#define TPC_CNTL_STATUS__TA_TB_RTS_MASK 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_RTS 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_RTR_MASK 0x08000000L +#define TPC_CNTL_STATUS__TA_TB_RTR 0x08000000L +#define TPC_CNTL_STATUS__TA_TF_RTS_MASK 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_RTS 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK 0x20000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN 0x20000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK 0x40000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC 0x40000000L +#define TPC_CNTL_STATUS__TPC_BUSY_MASK 0x80000000L +#define TPC_CNTL_STATUS__TPC_BUSY 0x80000000L + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL_MASK 0x00000003L +#define TPC_DEBUG0__IC_CTR_MASK 0x0000000cL +#define TPC_DEBUG0__WALKER_CNTL_MASK 0x000000f0L +#define TPC_DEBUG0__ALIGNER_CNTL_MASK 0x00000700L +#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK 0x00001000L +#define TPC_DEBUG0__PREV_TC_STATE_VALID 0x00001000L +#define TPC_DEBUG0__WALKER_STATE_MASK 0x03ff0000L +#define TPC_DEBUG0__ALIGNER_STATE_MASK 0x0c000000L +#define TPC_DEBUG0__REG_CLK_EN_MASK 0x20000000L +#define TPC_DEBUG0__REG_CLK_EN 0x20000000L +#define TPC_DEBUG0__TPC_CLK_EN_MASK 0x40000000L +#define TPC_DEBUG0__TPC_CLK_EN 0x40000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK 0x80000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP 0x80000000L + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED_MASK 0x00000001L +#define TPC_DEBUG1__UNUSED 0x00000001L + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION_MASK 0x00000001L +#define TPC_CHICKEN__BLEND_PRECISION 0x00000001L +#define TPC_CHICKEN__SPARE_MASK 0xfffffffeL + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK 0x00000001L +#define TP0_CNTL_STATUS__TP_INPUT_BUSY 0x00000001L +#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_BUSY 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK 0x00000004L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY 0x00000004L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK 0x00000008L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY 0x00000008L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK 0x00000020L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY 0x00000020L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK 0x00000040L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY 0x00000040L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK 0x00000080L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY 0x00000080L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK 0x00000100L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY 0x00000100L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK 0x00000200L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY 0x00000200L +#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK 0x00000400L +#define TP0_CNTL_STATUS__TP_TT_BUSY 0x00000400L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK 0x00000800L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY 0x00000800L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK 0x00001000L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY 0x00001000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK 0x00002000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY 0x00002000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK 0x00004000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY 0x00004000L +#define TP0_CNTL_STATUS__IN_LC_RTS_MASK 0x00010000L +#define TP0_CNTL_STATUS__IN_LC_RTS 0x00010000L +#define TP0_CNTL_STATUS__LC_LA_RTS_MASK 0x00020000L +#define TP0_CNTL_STATUS__LC_LA_RTS 0x00020000L +#define TP0_CNTL_STATUS__LA_FL_RTS_MASK 0x00040000L +#define TP0_CNTL_STATUS__LA_FL_RTS 0x00040000L +#define TP0_CNTL_STATUS__FL_TA_RTS_MASK 0x00080000L +#define TP0_CNTL_STATUS__FL_TA_RTS 0x00080000L +#define TP0_CNTL_STATUS__TA_FA_RTS_MASK 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_RTS 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK 0x00200000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS 0x00200000L +#define TP0_CNTL_STATUS__FA_AL_RTS_MASK 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_RTS 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK 0x00800000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS 0x00800000L +#define TP0_CNTL_STATUS__AL_TF_RTS_MASK 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_RTS 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK 0x02000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS 0x02000000L +#define TP0_CNTL_STATUS__TF_TB_RTS_MASK 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_RTS 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK 0x08000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS 0x08000000L +#define TP0_CNTL_STATUS__TB_TT_RTS_MASK 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_RTS 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK 0x20000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET 0x20000000L +#define TP0_CNTL_STATUS__TB_TO_RTS_MASK 0x40000000L +#define TP0_CNTL_STATUS__TB_TO_RTS 0x40000000L +#define TP0_CNTL_STATUS__TP_BUSY_MASK 0x80000000L +#define TP0_CNTL_STATUS__TP_BUSY 0x80000000L + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL_MASK 0x00000003L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK 0x00000008L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP 0x00000008L +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0L +#define TP0_DEBUG__REG_CLK_EN_MASK 0x00200000L +#define TP0_DEBUG__REG_CLK_EN 0x00200000L +#define TP0_DEBUG__PERF_CLK_EN_MASK 0x00400000L +#define TP0_DEBUG__PERF_CLK_EN 0x00400000L +#define TP0_DEBUG__TP_CLK_EN_MASK 0x00800000L +#define TP0_DEBUG__TP_CLK_EN 0x00800000L +#define TP0_DEBUG__Q_WALKER_CNTL_MASK 0x0f000000L +#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK 0x70000000L + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE_MASK 0x00000001L +#define TP0_CHICKEN__TT_MODE 0x00000001L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK 0x00000002L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE 0x00000002L +#define TP0_CHICKEN__SPARE_MASK 0xfffffffcL + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr_MASK 0x00000040L +#define TCF_DEBUG__not_MH_TC_rtr 0x00000040L +#define TCF_DEBUG__TC_MH_send_MASK 0x00000080L +#define TCF_DEBUG__TC_MH_send 0x00000080L +#define TCF_DEBUG__not_FG0_rtr_MASK 0x00000100L +#define TCF_DEBUG__not_FG0_rtr 0x00000100L +#define TCF_DEBUG__not_TCB_TCO_rtr_MASK 0x00001000L +#define TCF_DEBUG__not_TCB_TCO_rtr 0x00001000L +#define TCF_DEBUG__TCB_ff_stall_MASK 0x00002000L +#define TCF_DEBUG__TCB_ff_stall 0x00002000L +#define TCF_DEBUG__TCB_miss_stall_MASK 0x00004000L +#define TCF_DEBUG__TCB_miss_stall 0x00004000L +#define TCF_DEBUG__TCA_TCB_stall_MASK 0x00008000L +#define TCF_DEBUG__TCA_TCB_stall 0x00008000L +#define TCF_DEBUG__PF0_stall_MASK 0x00010000L +#define TCF_DEBUG__PF0_stall 0x00010000L +#define TCF_DEBUG__TP0_full_MASK 0x00100000L +#define TCF_DEBUG__TP0_full 0x00100000L +#define TCF_DEBUG__TPC_full_MASK 0x01000000L +#define TCF_DEBUG__TPC_full 0x01000000L +#define TCF_DEBUG__not_TPC_rtr_MASK 0x02000000L +#define TCF_DEBUG__not_TPC_rtr 0x02000000L +#define TCF_DEBUG__tca_state_rts_MASK 0x04000000L +#define TCF_DEBUG__tca_state_rts 0x04000000L +#define TCF_DEBUG__tca_rts_MASK 0x08000000L +#define TCF_DEBUG__tca_rts 0x08000000L + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full_MASK 0x00000001L +#define TCA_FIFO_DEBUG__tp0_full 0x00000001L +#define TCA_FIFO_DEBUG__tpc_full_MASK 0x00000010L +#define TCA_FIFO_DEBUG__tpc_full 0x00000010L +#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK 0x00000020L +#define TCA_FIFO_DEBUG__load_tpc_fifo 0x00000020L +#define TCA_FIFO_DEBUG__load_tp_fifos_MASK 0x00000040L +#define TCA_FIFO_DEBUG__load_tp_fifos 0x00000040L +#define TCA_FIFO_DEBUG__FW_full_MASK 0x00000080L +#define TCA_FIFO_DEBUG__FW_full 0x00000080L +#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK 0x00000100L +#define TCA_FIFO_DEBUG__not_FW_rtr0 0x00000100L +#define TCA_FIFO_DEBUG__FW_rts0_MASK 0x00001000L +#define TCA_FIFO_DEBUG__FW_rts0 0x00001000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK 0x00010000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr 0x00010000L +#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK 0x00020000L +#define TCA_FIFO_DEBUG__FW_tpc_rts 0x00020000L + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK 0x00000001L +#define TCA_PROBE_DEBUG__ProbeFilter_stall 0x00000001L + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts_MASK 0x00001000L +#define TCA_TPC_DEBUG__captue_state_rts 0x00001000L +#define TCA_TPC_DEBUG__capture_tca_rts_MASK 0x00002000L +#define TCA_TPC_DEBUG__capture_tca_rts 0x00002000L + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512_MASK 0x00000001L +#define TCB_CORE_DEBUG__access512 0x00000001L +#define TCB_CORE_DEBUG__tiled_MASK 0x00000002L +#define TCB_CORE_DEBUG__tiled 0x00000002L +#define TCB_CORE_DEBUG__opcode_MASK 0x00000070L +#define TCB_CORE_DEBUG__format_MASK 0x00003f00L +#define TCB_CORE_DEBUG__sector_format_MASK 0x001f0000L +#define TCB_CORE_DEBUG__sector_format512_MASK 0x07000000L + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG0_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG0_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG0_DEBUG__miss_stall 0x00800000L +#define TCB_TAG0_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG0_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG1_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG1_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG1_DEBUG__miss_stall 0x00800000L +#define TCB_TAG1_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG1_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG2_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG2_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG2_DEBUG__miss_stall 0x00800000L +#define TCB_TAG2_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG2_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG3_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG3_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG3_DEBUG__miss_stall 0x00800000L +#define TCB_TAG3_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG3_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q 0x10000000L + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK 0x00000030L +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK 0x000000c0L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK 0x00007000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK 0x000f0000L + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK 0x0000fff0L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK 0x001f0000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK 0x0c000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK 0x40000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR 0x40000000L + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty_MASK 0x00010000L +#define TCD_INPUT0_DEBUG__empty 0x00010000L +#define TCD_INPUT0_DEBUG__full_MASK 0x00020000L +#define TCD_INPUT0_DEBUG__full 0x00020000L +#define TCD_INPUT0_DEBUG__valid_q1_MASK 0x00100000L +#define TCD_INPUT0_DEBUG__valid_q1 0x00100000L +#define TCD_INPUT0_DEBUG__cnt_q1_MASK 0x00600000L +#define TCD_INPUT0_DEBUG__last_send_q1_MASK 0x00800000L +#define TCD_INPUT0_DEBUG__last_send_q1 0x00800000L +#define TCD_INPUT0_DEBUG__ip_send_MASK 0x01000000L +#define TCD_INPUT0_DEBUG__ip_send 0x01000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK 0x04000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy 0x04000000L + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK 0x00000003L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_stall 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK 0x00000040L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate 0x00000040L + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__pstate 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK 0x20000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send 0x20000000L + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK 0x00000010L +#define TCD_DXTC_ARB_DEBUG__n0_stall 0x00000010L +#define TCD_DXTC_ARB_DEBUG__pstate_MASK 0x00000020L +#define TCD_DXTC_ARB_DEBUG__pstate 0x00000020L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK 0x00000180L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK 0x00000e00L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK 0x0003f000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK 0x3ffc0000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK 0x40000000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send 0x40000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK 0x80000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types 0x80000000L + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK 0x00000400L +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr 0x00000400L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK 0x00000800L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr 0x00000800L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK 0x00020000L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr 0x00020000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK 0x00040000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr 0x00040000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK 0x00080000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr 0x00080000L +#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK 0x80000000L +#define TCD_STALLS_DEBUG__not_incoming_rtr 0x80000000L + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK 0x00000020L +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR 0x00000020L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK 0x00000040L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR 0x00000040L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK 0x00000080L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d 0x00000080L + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK 0x000000ffL +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK 0x00000400L +#define TCO_QUAD0_DEBUG0__rl_sg_rts 0x00000400L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK 0x00002000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts 0x00002000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK 0x00010000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q 0x00010000L +#define TCO_QUAD0_DEBUG0__read_cache_q_MASK 0x01000000L +#define TCO_QUAD0_DEBUG0__read_cache_q 0x01000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK 0x02000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR 0x02000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK 0x20000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0 0x20000000L +#define TCO_QUAD0_DEBUG0__busy_MASK 0x40000000L +#define TCO_QUAD0_DEBUG0__busy 0x40000000L + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy_MASK 0x00000001L +#define TCO_QUAD0_DEBUG1__fifo_busy 0x00000001L +#define TCO_QUAD0_DEBUG1__empty_MASK 0x00000002L +#define TCO_QUAD0_DEBUG1__empty 0x00000002L +#define TCO_QUAD0_DEBUG1__full_MASK 0x00000004L +#define TCO_QUAD0_DEBUG1__full 0x00000004L +#define TCO_QUAD0_DEBUG1__write_enable_MASK 0x00000008L +#define TCO_QUAD0_DEBUG1__write_enable 0x00000008L +#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK 0x000007f0L +#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK 0x0003f800L +#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK 0x00100000L +#define TCO_QUAD0_DEBUG1__cache_read_busy 0x00100000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK 0x00200000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy 0x00200000L +#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK 0x00400000L +#define TCO_QUAD0_DEBUG1__input_quad_busy 0x00400000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK 0x00800000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy 0x00800000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK 0x02000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q 0x02000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK 0x08000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts 0x08000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK 0x20000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts 0x20000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK 0x40000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc 0x40000000L + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK 0x000007f0L +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK 0x0007f000L + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK 0x00000003L +#define SQ_FLOW_CONTROL__ONE_THREAD_MASK 0x00000010L +#define SQ_FLOW_CONTROL__ONE_THREAD 0x00000010L +#define SQ_FLOW_CONTROL__ONE_ALU_MASK 0x00000100L +#define SQ_FLOW_CONTROL__ONE_ALU 0x00000100L +#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK 0x0000f000L +#define SQ_FLOW_CONTROL__NO_PV_PS_MASK 0x00010000L +#define SQ_FLOW_CONTROL__NO_PV_PS 0x00010000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK 0x00020000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT 0x00020000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK 0x00040000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE 0x00040000L +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK 0x00180000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK 0x00200000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY 0x00200000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK 0x00400000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY 0x00400000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK 0x00800000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT 0x00800000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK 0x01000000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT 0x01000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK 0x02000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY 0x02000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK 0x04000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION 0x04000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC 0x08000000L + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK 0x00000fffL +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK 0x0fff0000L + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK 0x01ff0000L + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT_MASK 0x000000ffL +#define SQ_EO_RT__EO_TSTATE_RT_MASK 0x00ff0000L + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK 0x000007ffL +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK 0x000ff000L +#define SQ_DEBUG_MISC__DB_READ_CTX_MASK 0x00100000L +#define SQ_DEBUG_MISC__DB_READ_CTX 0x00100000L +#define SQ_DEBUG_MISC__RESERVED_MASK 0x00600000L +#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK 0x01800000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK 0x10000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3 0x10000000L + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK 0x000000ffL +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK 0x0000ff00L +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK 0x00ff0000L +#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK 0xff000000L + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK 0x000000ffL + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L +#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK 0x000c0000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK 0x00000007L +#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK 0x00000008L +#define SQ_DEBUG_INPUT_FSM__RESERVED 0x00000008L +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK 0x000000f0L +#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK 0x00000700L +#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_INPUT_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK 0x00007000L +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK 0x000f8000L +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK 0x0ff00000L + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK 0x000000e0L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK 0x0000e000L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK 0x00030000L +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK 0x000c0000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK 0x00800000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE 0x00800000L + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP_MASK 0x00000007L +#define SQ_DEBUG_TP_FSM__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_TP_FSM__RESERVED0 0x00000008L +#define SQ_DEBUG_TP_FSM__CF_TP_MASK 0x000000f0L +#define SQ_DEBUG_TP_FSM__IF_TP_MASK 0x00000700L +#define SQ_DEBUG_TP_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_TP_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_TP_FSM__TIS_TP_MASK 0x00003000L +#define SQ_DEBUG_TP_FSM__RESERVED2_MASK 0x0000c000L +#define SQ_DEBUG_TP_FSM__GS_TP_MASK 0x00030000L +#define SQ_DEBUG_TP_FSM__RESERVED3_MASK 0x000c0000L +#define SQ_DEBUG_TP_FSM__FCR_TP_MASK 0x00300000L +#define SQ_DEBUG_TP_FSM__RESERVED4_MASK 0x00c00000L +#define SQ_DEBUG_TP_FSM__FCS_TP_MASK 0x03000000L +#define SQ_DEBUG_TP_FSM__RESERVED5_MASK 0x0c000000L +#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK 0x0000000fL +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK 0x00000ff0L +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK 0x00007000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000L + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK 0x00000001L +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER 0x00000001L +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK 0x0000001eL +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK 0x00000020L +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR 0x00000020L +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK 0x000001c0L +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK 0x00003e00L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK 0x00004000L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT 0x00004000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK 0x00008000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON 0x00008000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK 0x00010000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY 0x00010000L +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK 0x0ffe0000L + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_VTX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_VTX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_VTX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_VTX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_PIX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_PIX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_PIX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_PIX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK 0x60000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC 0x80000000L + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK 0x0000000fL +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK 0x000000f0L +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK 0x00000f00L +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK 0x0000f000L +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK 0x000f0000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK 0x00100000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL 0x00100000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK 0x00200000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q 0x00200000L + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK 0x0000ffffL + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK 0xffffffffL + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK 0x0000003fL +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK 0x00000fc0L +#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK 0x0007f000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK 0x01f80000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK 0x7e000000L +#define SQ_DEBUG_PIX_TB_0__BUSY_MASK 0x80000000L +#define SQ_DEBUG_PIX_TB_0__BUSY 0x80000000L + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD 0x00000040L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP 0x00000080L +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD 0x00004000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA 0x00008000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK 0x000f0000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK 0x00f00000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP 0x01000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK 0xfc000000L + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK 0x00000003L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK 0x0000000cL +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK 0x00000030L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK 0x000000c0L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK 0x00000300L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK 0x00000c00L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK 0x00003000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK 0x0000c000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK 0x00030000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK 0x000c0000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK 0x00300000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK 0x00c00000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK 0x04000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD 0x04000000L +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK 0x18000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR 0x20000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS 0x80000000L + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C 0x00000080L +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B 0x00008000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK 0x003f0000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK 0x00800000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A 0x00800000L +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK 0x1f000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK 0x000001ffL +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK 0x00000e00L +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK 0x00007000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK 0x01ff0000L +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK 0x0e000000L +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK 0x70000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK 0x0000fc00L +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK 0x001f0000L +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK 0xffe00000L + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK 0x000007ffL +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK 0xfc000000L + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK 0x0000001fL +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK 0x07ffffe0L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK 0x00001c00L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK 0xffff8000L + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK 0x1c000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK 0xc0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK 0x0001ffffL +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK 0x0000000fL +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK 0xfffffff0L + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK 0x000000ffL +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK 0x00000600L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK 0x000f0000L +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK 0xfff00000L + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK 0x00ffffffL +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK 0x06000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK 0x30000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK 0xc0000000L + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK 0x00003000L +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK 0x0000c000L +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK 0x00030000L +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK 0x001c0000L +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK 0x00e00000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK 0x03000000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK 0x60000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK 0x000001fcL +#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK 0x0000fe00L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK 0x001f0000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK 0x03e00000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK 0x7c000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK 0x06000000L +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK 0xc0000000L + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK 0x003f0000L +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK 0x3f800000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK 0x000000ffL +#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK 0x00ff0000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE_MASK 0x00000001L +#define SQ_CONSTANT_VFETCH_0__TYPE 0x00000001L +#define SQ_CONSTANT_VFETCH_0__STATE_MASK 0x00000002L +#define SQ_CONSTANT_VFETCH_0__STATE 0x00000002L +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK 0x00000003L +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE_MASK 0xffffffffL + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE_MASK 0xffffffffL + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_VS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_PS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK 0x000007ffL +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK 0x007ff000L + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK 0x0000ffffL +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK 0xffff0000L + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK 0x0000003fL +#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK 0x00003f00L +#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK 0x00010000L +#define SQ_PROGRAM_CNTL__VS_RESOURCE 0x00010000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK 0x00020000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE 0x00020000L +#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK 0x00040000L +#define SQ_PROGRAM_CNTL__PARAM_GEN 0x00040000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK 0x00080000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX 0x00080000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK 0x00f00000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK 0x07000000L +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK 0x78000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK 0x80000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX 0x80000000L + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK 0x0000000fL +#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK 0x000000f0L +#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK 0x00000f00L +#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK 0x0000f000L +#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK 0x000f0000L +#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK 0x00f00000L +#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK 0x0f000000L +#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK 0xf0000000L + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK 0x0000000fL +#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK 0x000000f0L +#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK 0x00000f00L +#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK 0x0000f000L +#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK 0x000f0000L +#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK 0x00f00000L +#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK 0x0f000000L +#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK 0xf0000000L + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE_MASK 0x000001ffL +#define SQ_VS_CONST__SIZE_MASK 0x001ff000L + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE_MASK 0x000001ffL +#define SQ_PS_CONST__SIZE_MASK 0x001ff000L + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK 0x00000001L +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE 0x00000001L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK 0x00000002L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY 0x00000002L +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK 0x0000000cL +#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK 0x0000ff00L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK 0x00010000L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF 0x00010000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK 0x00020000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE 0x00020000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK 0x00040000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL 0x00040000L + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE_MASK 0x00000007L + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_ON 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK 0x0007ff00L +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK 0xff000000L + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_PIX 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK 0x00000002L +#define SQ_DEBUG_MISC_1__DB_ON_VTX 0x00000002L +#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK 0x0000ff00L +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK 0x07ff0000L + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK 0x0000003fL +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK 0x00000040L +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY 0x00000040L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK 0x00000100L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE 0x00000100L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK 0x00000200L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL 0x00000200L +#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK 0x00001c00L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK 0x00002000L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE 0x00002000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK 0x00004000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE 0x00004000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK 0x003f0000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK 0x00400000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE 0x00400000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK 0x00800000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE 0x00800000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK 0x01000000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE 0x01000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK 0x02000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE 0x02000000L + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK 0x00000007L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK 0x00000070L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK 0x00000700L + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_MASK__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT 0x00000004L + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID_MASK 0x00000007L +#define MH_AXI_ERROR__AXI_READ_ERROR_MASK 0x00000008L +#define MH_AXI_ERROR__AXI_READ_ERROR 0x00000008L +#define MH_AXI_ERROR__AXI_WRITE_ID_MASK 0x00000070L +#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK 0x00000080L +#define MH_AXI_ERROR__AXI_WRITE_ERROR 0x00000080L + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX_MASK 0x0000003fL + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA_MASK 0xffffffffL + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY_MASK 0x00000001L +#define MH_DEBUG_REG00__MH_BUSY 0x00000001L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK 0x00000002L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING 0x00000002L +#define MH_DEBUG_REG00__CP_REQUEST_MASK 0x00000004L +#define MH_DEBUG_REG00__CP_REQUEST 0x00000004L +#define MH_DEBUG_REG00__VGT_REQUEST_MASK 0x00000008L +#define MH_DEBUG_REG00__VGT_REQUEST 0x00000008L +#define MH_DEBUG_REG00__TC_REQUEST_MASK 0x00000010L +#define MH_DEBUG_REG00__TC_REQUEST 0x00000010L +#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_EMPTY 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_FULL_MASK 0x00000040L +#define MH_DEBUG_REG00__TC_CAM_FULL 0x00000040L +#define MH_DEBUG_REG00__TCD_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG00__TCD_EMPTY 0x00000080L +#define MH_DEBUG_REG00__TCD_FULL_MASK 0x00000100L +#define MH_DEBUG_REG00__TCD_FULL 0x00000100L +#define MH_DEBUG_REG00__RB_REQUEST_MASK 0x00000200L +#define MH_DEBUG_REG00__RB_REQUEST 0x00000200L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK 0x00000400L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE 0x00000400L +#define MH_DEBUG_REG00__ARQ_EMPTY_MASK 0x00000800L +#define MH_DEBUG_REG00__ARQ_EMPTY 0x00000800L +#define MH_DEBUG_REG00__ARQ_FULL_MASK 0x00001000L +#define MH_DEBUG_REG00__ARQ_FULL 0x00001000L +#define MH_DEBUG_REG00__WDB_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG00__WDB_EMPTY 0x00002000L +#define MH_DEBUG_REG00__WDB_FULL_MASK 0x00004000L +#define MH_DEBUG_REG00__WDB_FULL 0x00004000L +#define MH_DEBUG_REG00__AXI_AVALID_MASK 0x00008000L +#define MH_DEBUG_REG00__AXI_AVALID 0x00008000L +#define MH_DEBUG_REG00__AXI_AREADY_MASK 0x00010000L +#define MH_DEBUG_REG00__AXI_AREADY 0x00010000L +#define MH_DEBUG_REG00__AXI_ARVALID_MASK 0x00020000L +#define MH_DEBUG_REG00__AXI_ARVALID 0x00020000L +#define MH_DEBUG_REG00__AXI_ARREADY_MASK 0x00040000L +#define MH_DEBUG_REG00__AXI_ARREADY 0x00040000L +#define MH_DEBUG_REG00__AXI_WVALID_MASK 0x00080000L +#define MH_DEBUG_REG00__AXI_WVALID 0x00080000L +#define MH_DEBUG_REG00__AXI_WREADY_MASK 0x00100000L +#define MH_DEBUG_REG00__AXI_WREADY 0x00100000L +#define MH_DEBUG_REG00__AXI_RVALID_MASK 0x00200000L +#define MH_DEBUG_REG00__AXI_RVALID 0x00200000L +#define MH_DEBUG_REG00__AXI_RREADY_MASK 0x00400000L +#define MH_DEBUG_REG00__AXI_RREADY 0x00400000L +#define MH_DEBUG_REG00__AXI_BVALID_MASK 0x00800000L +#define MH_DEBUG_REG00__AXI_BVALID 0x00800000L +#define MH_DEBUG_REG00__AXI_BREADY_MASK 0x01000000L +#define MH_DEBUG_REG00__AXI_BREADY 0x01000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK 0x04000000L + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q_MASK 0x00000001L +#define MH_DEBUG_REG01__CP_SEND_q 0x00000001L +#define MH_DEBUG_REG01__CP_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG01__CP_RTR_q 0x00000002L +#define MH_DEBUG_REG01__CP_WRITE_q_MASK 0x00000004L +#define MH_DEBUG_REG01__CP_WRITE_q 0x00000004L +#define MH_DEBUG_REG01__CP_TAG_q_MASK 0x00000038L +#define MH_DEBUG_REG01__CP_BE_q_MASK 0x00003fc0L +#define MH_DEBUG_REG01__VGT_SEND_q_MASK 0x00004000L +#define MH_DEBUG_REG01__VGT_SEND_q 0x00004000L +#define MH_DEBUG_REG01__VGT_RTR_q_MASK 0x00008000L +#define MH_DEBUG_REG01__VGT_RTR_q 0x00008000L +#define MH_DEBUG_REG01__VGT_TAG_q_MASK 0x00010000L +#define MH_DEBUG_REG01__VGT_TAG_q 0x00010000L +#define MH_DEBUG_REG01__TC_SEND_q_MASK 0x00020000L +#define MH_DEBUG_REG01__TC_SEND_q 0x00020000L +#define MH_DEBUG_REG01__TC_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG01__TC_RTR_q 0x00040000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK 0x00080000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q 0x00080000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK 0x00100000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q 0x00100000L +#define MH_DEBUG_REG01__TC_MH_written_MASK 0x00200000L +#define MH_DEBUG_REG01__TC_MH_written 0x00200000L +#define MH_DEBUG_REG01__RB_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG01__RB_SEND_q 0x00400000L +#define MH_DEBUG_REG01__RB_RTR_q_MASK 0x00800000L +#define MH_DEBUG_REG01__RB_RTR_q 0x00800000L +#define MH_DEBUG_REG01__RB_BE_q_MASK 0xff000000L + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG02__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG02__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG02__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG02__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_rlast 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_tag_MASK 0x00000070L +#define MH_DEBUG_REG02__RDC_RID_MASK 0x00000380L +#define MH_DEBUG_REG02__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG02__MH_CP_writeclean_MASK 0x00001000L +#define MH_DEBUG_REG02__MH_CP_writeclean 0x00001000L +#define MH_DEBUG_REG02__MH_RB_writeclean_MASK 0x00002000L +#define MH_DEBUG_REG02__MH_RB_writeclean 0x00002000L +#define MH_DEBUG_REG02__BRC_BID_MASK 0x0001c000L +#define MH_DEBUG_REG02__BRC_BRESP_MASK 0x00060000L + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG05__CP_MH_send 0x00000001L +#define MH_DEBUG_REG05__CP_MH_write_MASK 0x00000002L +#define MH_DEBUG_REG05__CP_MH_write 0x00000002L +#define MH_DEBUG_REG05__CP_MH_tag_MASK 0x0000001cL +#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__ALWAYS_ZERO_MASK 0x00000007L +#define MH_DEBUG_REG08__VGT_MH_send_MASK 0x00000008L +#define MH_DEBUG_REG08__VGT_MH_send 0x00000008L +#define MH_DEBUG_REG08__VGT_MH_tagbe_MASK 0x00000010L +#define MH_DEBUG_REG08__VGT_MH_tagbe 0x00000010L +#define MH_DEBUG_REG08__VGT_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG09__TC_MH_send_MASK 0x00000004L +#define MH_DEBUG_REG09__TC_MH_send 0x00000004L +#define MH_DEBUG_REG09__TC_MH_mask_MASK 0x00000018L +#define MH_DEBUG_REG09__TC_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__TC_MH_info_MASK 0x01ffffffL +#define MH_DEBUG_REG10__TC_MH_send_MASK 0x02000000L +#define MH_DEBUG_REG10__TC_MH_send 0x02000000L + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__MH_TC_mcinfo_MASK 0x01ffffffL +#define MH_DEBUG_REG11__MH_TC_mcinfo_send_MASK 0x02000000L +#define MH_DEBUG_REG11__MH_TC_mcinfo_send 0x02000000L +#define MH_DEBUG_REG11__TC_MH_written_MASK 0x04000000L +#define MH_DEBUG_REG11__TC_MH_written 0x04000000L + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG12__TC_ROQ_SEND_MASK 0x00000004L +#define MH_DEBUG_REG12__TC_ROQ_SEND 0x00000004L +#define MH_DEBUG_REG12__TC_ROQ_MASK_MASK 0x00000018L +#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__TC_ROQ_INFO_MASK 0x01ffffffL +#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK 0x02000000L +#define MH_DEBUG_REG13__TC_ROQ_SEND 0x02000000L + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG14__RB_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG14__RB_MH_send 0x00000010L +#define MH_DEBUG_REG14__RB_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__RB_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG17__AVALID_q 0x00000001L +#define MH_DEBUG_REG17__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG17__AREADY_q 0x00000002L +#define MH_DEBUG_REG17__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG17__ALEN_q_2_0_MASK 0x000000e0L +#define MH_DEBUG_REG17__ARVALID_q_MASK 0x00000100L +#define MH_DEBUG_REG17__ARVALID_q 0x00000100L +#define MH_DEBUG_REG17__ARREADY_q_MASK 0x00000200L +#define MH_DEBUG_REG17__ARREADY_q 0x00000200L +#define MH_DEBUG_REG17__ARID_q_MASK 0x00001c00L +#define MH_DEBUG_REG17__ARLEN_q_1_0_MASK 0x00006000L +#define MH_DEBUG_REG17__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG17__RVALID_q 0x00008000L +#define MH_DEBUG_REG17__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG17__RREADY_q 0x00010000L +#define MH_DEBUG_REG17__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG17__RLAST_q 0x00020000L +#define MH_DEBUG_REG17__RID_q_MASK 0x001c0000L +#define MH_DEBUG_REG17__WVALID_q_MASK 0x00200000L +#define MH_DEBUG_REG17__WVALID_q 0x00200000L +#define MH_DEBUG_REG17__WREADY_q_MASK 0x00400000L +#define MH_DEBUG_REG17__WREADY_q 0x00400000L +#define MH_DEBUG_REG17__WLAST_q_MASK 0x00800000L +#define MH_DEBUG_REG17__WLAST_q 0x00800000L +#define MH_DEBUG_REG17__WID_q_MASK 0x07000000L +#define MH_DEBUG_REG17__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG17__BVALID_q 0x08000000L +#define MH_DEBUG_REG17__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG17__BREADY_q 0x10000000L +#define MH_DEBUG_REG17__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG18__AVALID_q 0x00000001L +#define MH_DEBUG_REG18__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG18__AREADY_q 0x00000002L +#define MH_DEBUG_REG18__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG18__ALEN_q_1_0_MASK 0x00000060L +#define MH_DEBUG_REG18__ARVALID_q_MASK 0x00000080L +#define MH_DEBUG_REG18__ARVALID_q 0x00000080L +#define MH_DEBUG_REG18__ARREADY_q_MASK 0x00000100L +#define MH_DEBUG_REG18__ARREADY_q 0x00000100L +#define MH_DEBUG_REG18__ARID_q_MASK 0x00000e00L +#define MH_DEBUG_REG18__ARLEN_q_1_1_MASK 0x00001000L +#define MH_DEBUG_REG18__ARLEN_q_1_1 0x00001000L +#define MH_DEBUG_REG18__WVALID_q_MASK 0x00002000L +#define MH_DEBUG_REG18__WVALID_q 0x00002000L +#define MH_DEBUG_REG18__WREADY_q_MASK 0x00004000L +#define MH_DEBUG_REG18__WREADY_q 0x00004000L +#define MH_DEBUG_REG18__WLAST_q_MASK 0x00008000L +#define MH_DEBUG_REG18__WLAST_q 0x00008000L +#define MH_DEBUG_REG18__WID_q_MASK 0x00070000L +#define MH_DEBUG_REG18__WSTRB_q_MASK 0x07f80000L +#define MH_DEBUG_REG18__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG18__BVALID_q 0x08000000L +#define MH_DEBUG_REG18__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG18__BREADY_q 0x10000000L +#define MH_DEBUG_REG18__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__ARC_CTRL_RE_q_MASK 0x00000001L +#define MH_DEBUG_REG19__ARC_CTRL_RE_q 0x00000001L +#define MH_DEBUG_REG19__CTRL_ARC_ID_MASK 0x0000000eL +#define MH_DEBUG_REG19__CTRL_ARC_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG20__REG_A_MASK 0x0000fffcL +#define MH_DEBUG_REG20__REG_RE_MASK 0x00010000L +#define MH_DEBUG_REG20__REG_RE 0x00010000L +#define MH_DEBUG_REG20__REG_WE_MASK 0x00020000L +#define MH_DEBUG_REG20__REG_WE 0x00020000L +#define MH_DEBUG_REG20__BLOCK_RS_MASK 0x00040000L +#define MH_DEBUG_REG20__BLOCK_RS 0x00040000L + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__REG_WD_MASK 0xffffffffL + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__CIB_MH_axi_halt_req_MASK 0x00000001L +#define MH_DEBUG_REG22__CIB_MH_axi_halt_req 0x00000001L +#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack_MASK 0x00000002L +#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack 0x00000002L +#define MH_DEBUG_REG22__MH_RBBM_busy_MASK 0x00000004L +#define MH_DEBUG_REG22__MH_RBBM_busy 0x00000004L +#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int_MASK 0x00000008L +#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int 0x00000008L +#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int_MASK 0x00000010L +#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int 0x00000010L +#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int_MASK 0x00000020L +#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int 0x00000020L +#define MH_DEBUG_REG22__GAT_CLK_ENA_MASK 0x00000040L +#define MH_DEBUG_REG22__GAT_CLK_ENA 0x00000040L +#define MH_DEBUG_REG22__AXI_RDY_ENA_MASK 0x00000080L +#define MH_DEBUG_REG22__AXI_RDY_ENA 0x00000080L +#define MH_DEBUG_REG22__RBBM_MH_clk_en_override_MASK 0x00000100L +#define MH_DEBUG_REG22__RBBM_MH_clk_en_override 0x00000100L +#define MH_DEBUG_REG22__CNT_q_MASK 0x00007e00L +#define MH_DEBUG_REG22__TCD_EMPTY_q_MASK 0x00008000L +#define MH_DEBUG_REG22__TCD_EMPTY_q 0x00008000L +#define MH_DEBUG_REG22__TC_ROQ_EMPTY_MASK 0x00010000L +#define MH_DEBUG_REG22__TC_ROQ_EMPTY 0x00010000L +#define MH_DEBUG_REG22__MH_BUSY_d_MASK 0x00020000L +#define MH_DEBUG_REG22__MH_BUSY_d 0x00020000L +#define MH_DEBUG_REG22__ANY_CLNT_BUSY_MASK 0x00040000L +#define MH_DEBUG_REG22__ANY_CLNT_BUSY 0x00040000L +#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000L +#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00080000L +#define MH_DEBUG_REG22__CP_SEND_q_MASK 0x00100000L +#define MH_DEBUG_REG22__CP_SEND_q 0x00100000L +#define MH_DEBUG_REG22__CP_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG22__CP_RTR_q 0x00200000L +#define MH_DEBUG_REG22__VGT_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG22__VGT_SEND_q 0x00400000L +#define MH_DEBUG_REG22__VGT_RTR_q_MASK 0x00800000L +#define MH_DEBUG_REG22__VGT_RTR_q 0x00800000L +#define MH_DEBUG_REG22__TC_ROQ_SEND_q_MASK 0x01000000L +#define MH_DEBUG_REG22__TC_ROQ_SEND_q 0x01000000L +#define MH_DEBUG_REG22__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG22__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG22__RB_SEND_q_MASK 0x04000000L +#define MH_DEBUG_REG22__RB_SEND_q 0x04000000L +#define MH_DEBUG_REG22__RB_RTR_q_MASK 0x08000000L +#define MH_DEBUG_REG22__RB_RTR_q 0x08000000L +#define MH_DEBUG_REG22__RDC_VALID_MASK 0x10000000L +#define MH_DEBUG_REG22__RDC_VALID 0x10000000L +#define MH_DEBUG_REG22__RDC_RLAST_MASK 0x20000000L +#define MH_DEBUG_REG22__RDC_RLAST 0x20000000L +#define MH_DEBUG_REG22__TLBMISS_VALID_MASK 0x40000000L +#define MH_DEBUG_REG22__TLBMISS_VALID 0x40000000L +#define MH_DEBUG_REG22__BRC_VALID_MASK 0x80000000L +#define MH_DEBUG_REG22__BRC_VALID 0x80000000L + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__EFF2_FP_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out_MASK 0x00000038L +#define MH_DEBUG_REG23__EFF1_WINNER_MASK 0x000001c0L +#define MH_DEBUG_REG23__ARB_WINNER_MASK 0x00000e00L +#define MH_DEBUG_REG23__ARB_WINNER_q_MASK 0x00007000L +#define MH_DEBUG_REG23__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG23__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG23__KILL_EFF1_MASK 0x00010000L +#define MH_DEBUG_REG23__KILL_EFF1 0x00010000L +#define MH_DEBUG_REG23__ARB_HOLD_MASK 0x00020000L +#define MH_DEBUG_REG23__ARB_HOLD 0x00020000L +#define MH_DEBUG_REG23__ARB_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG23__ARB_RTR_q 0x00040000L +#define MH_DEBUG_REG23__CP_SEND_QUAL_MASK 0x00080000L +#define MH_DEBUG_REG23__CP_SEND_QUAL 0x00080000L +#define MH_DEBUG_REG23__VGT_SEND_QUAL_MASK 0x00100000L +#define MH_DEBUG_REG23__VGT_SEND_QUAL 0x00100000L +#define MH_DEBUG_REG23__TC_SEND_QUAL_MASK 0x00200000L +#define MH_DEBUG_REG23__TC_SEND_QUAL 0x00200000L +#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL_MASK 0x00400000L +#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL 0x00400000L +#define MH_DEBUG_REG23__RB_SEND_QUAL_MASK 0x00800000L +#define MH_DEBUG_REG23__RB_SEND_QUAL 0x00800000L +#define MH_DEBUG_REG23__ARB_QUAL_MASK 0x01000000L +#define MH_DEBUG_REG23__ARB_QUAL 0x01000000L +#define MH_DEBUG_REG23__CP_EFF1_REQ_MASK 0x02000000L +#define MH_DEBUG_REG23__CP_EFF1_REQ 0x02000000L +#define MH_DEBUG_REG23__VGT_EFF1_REQ_MASK 0x04000000L +#define MH_DEBUG_REG23__VGT_EFF1_REQ 0x04000000L +#define MH_DEBUG_REG23__TC_EFF1_REQ_MASK 0x08000000L +#define MH_DEBUG_REG23__TC_EFF1_REQ 0x08000000L +#define MH_DEBUG_REG23__RB_EFF1_REQ_MASK 0x10000000L +#define MH_DEBUG_REG23__RB_EFF1_REQ 0x10000000L +#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK_MASK 0x20000000L +#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK 0x20000000L +#define MH_DEBUG_REG23__TCD_NEARFULL_q_MASK 0x40000000L +#define MH_DEBUG_REG23__TCD_NEARFULL_q 0x40000000L +#define MH_DEBUG_REG23__TCHOLD_IP_q_MASK 0x80000000L +#define MH_DEBUG_REG23__TCHOLD_IP_q 0x80000000L + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__EFF1_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG24__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG24__CP_SEND_QUAL_MASK 0x00000040L +#define MH_DEBUG_REG24__CP_SEND_QUAL 0x00000040L +#define MH_DEBUG_REG24__VGT_SEND_QUAL_MASK 0x00000080L +#define MH_DEBUG_REG24__VGT_SEND_QUAL 0x00000080L +#define MH_DEBUG_REG24__TC_SEND_QUAL_MASK 0x00000100L +#define MH_DEBUG_REG24__TC_SEND_QUAL 0x00000100L +#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL_MASK 0x00000200L +#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL 0x00000200L +#define MH_DEBUG_REG24__RB_SEND_QUAL_MASK 0x00000400L +#define MH_DEBUG_REG24__RB_SEND_QUAL 0x00000400L +#define MH_DEBUG_REG24__ARB_QUAL_MASK 0x00000800L +#define MH_DEBUG_REG24__ARB_QUAL 0x00000800L +#define MH_DEBUG_REG24__CP_EFF1_REQ_MASK 0x00001000L +#define MH_DEBUG_REG24__CP_EFF1_REQ 0x00001000L +#define MH_DEBUG_REG24__VGT_EFF1_REQ_MASK 0x00002000L +#define MH_DEBUG_REG24__VGT_EFF1_REQ 0x00002000L +#define MH_DEBUG_REG24__TC_EFF1_REQ_MASK 0x00004000L +#define MH_DEBUG_REG24__TC_EFF1_REQ 0x00004000L +#define MH_DEBUG_REG24__RB_EFF1_REQ_MASK 0x00008000L +#define MH_DEBUG_REG24__RB_EFF1_REQ 0x00008000L +#define MH_DEBUG_REG24__EFF1_WIN_MASK 0x00010000L +#define MH_DEBUG_REG24__EFF1_WIN 0x00010000L +#define MH_DEBUG_REG24__KILL_EFF1_MASK 0x00020000L +#define MH_DEBUG_REG24__KILL_EFF1 0x00020000L +#define MH_DEBUG_REG24__TCD_NEARFULL_q_MASK 0x00040000L +#define MH_DEBUG_REG24__TCD_NEARFULL_q 0x00040000L +#define MH_DEBUG_REG24__TC_ARB_HOLD_MASK 0x00080000L +#define MH_DEBUG_REG24__TC_ARB_HOLD 0x00080000L +#define MH_DEBUG_REG24__ARB_HOLD_MASK 0x00100000L +#define MH_DEBUG_REG24__ARB_HOLD 0x00100000L +#define MH_DEBUG_REG24__ARB_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG24__ARB_RTR_q 0x00200000L +#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000L + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out_MASK 0x00000007L +#define MH_DEBUG_REG25__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d_MASK 0x000001c0L +#define MH_DEBUG_REG25__LEAST_RECENT_d_MASK 0x00000e00L +#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d_MASK 0x00001000L +#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d 0x00001000L +#define MH_DEBUG_REG25__ARB_HOLD_MASK 0x00002000L +#define MH_DEBUG_REG25__ARB_HOLD 0x00002000L +#define MH_DEBUG_REG25__ARB_RTR_q_MASK 0x00004000L +#define MH_DEBUG_REG25__ARB_RTR_q 0x00004000L +#define MH_DEBUG_REG25__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG25__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG25__CLNT_REQ_MASK 0x000f0000L +#define MH_DEBUG_REG25__RECENT_d_0_MASK 0x00700000L +#define MH_DEBUG_REG25__RECENT_d_1_MASK 0x03800000L +#define MH_DEBUG_REG25__RECENT_d_2_MASK 0x1c000000L +#define MH_DEBUG_REG25__RECENT_d_3_MASK 0xe0000000L + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__TC_ARB_HOLD_MASK 0x00000001L +#define MH_DEBUG_REG26__TC_ARB_HOLD 0x00000001L +#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002L +#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK 0x00000002L +#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK_MASK 0x00000004L +#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK 0x00000004L +#define MH_DEBUG_REG26__TCD_NEARFULL_q_MASK 0x00000008L +#define MH_DEBUG_REG26__TCD_NEARFULL_q 0x00000008L +#define MH_DEBUG_REG26__TCHOLD_IP_q_MASK 0x00000010L +#define MH_DEBUG_REG26__TCHOLD_IP_q 0x00000010L +#define MH_DEBUG_REG26__TCHOLD_CNT_q_MASK 0x000000e0L +#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L +#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK 0x00000200L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q 0x00000200L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q 0x00000400L +#define MH_DEBUG_REG26__TC_MH_written_MASK 0x00000800L +#define MH_DEBUG_REG26__TC_MH_written 0x00000800L +#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q_MASK 0x0007f000L +#define MH_DEBUG_REG26__WBURST_ACTIVE_MASK 0x00080000L +#define MH_DEBUG_REG26__WBURST_ACTIVE 0x00080000L +#define MH_DEBUG_REG26__WLAST_q_MASK 0x00100000L +#define MH_DEBUG_REG26__WLAST_q 0x00100000L +#define MH_DEBUG_REG26__WBURST_IP_q_MASK 0x00200000L +#define MH_DEBUG_REG26__WBURST_IP_q 0x00200000L +#define MH_DEBUG_REG26__WBURST_CNT_q_MASK 0x01c00000L +#define MH_DEBUG_REG26__CP_SEND_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG26__CP_SEND_QUAL 0x02000000L +#define MH_DEBUG_REG26__CP_MH_write_MASK 0x04000000L +#define MH_DEBUG_REG26__CP_MH_write 0x04000000L +#define MH_DEBUG_REG26__RB_SEND_QUAL_MASK 0x08000000L +#define MH_DEBUG_REG26__RB_SEND_QUAL 0x08000000L +#define MH_DEBUG_REG26__ARB_WINNER_MASK 0x70000000L + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q_MASK 0x03ffffffL +#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000L + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG28__ROQ_MARK_q_MASK 0x0000ff00L +#define MH_DEBUG_REG28__ROQ_VALID_q_MASK 0x00ff0000L +#define MH_DEBUG_REG28__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG28__TC_MH_send 0x01000000L +#define MH_DEBUG_REG28__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG28__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG28__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG28__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG28__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG28__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG28__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG28__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG28__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG28__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG29__ROQ_MARK_d_MASK 0x0000ff00L +#define MH_DEBUG_REG29__ROQ_VALID_d_MASK 0x00ff0000L +#define MH_DEBUG_REG29__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG29__TC_MH_send 0x01000000L +#define MH_DEBUG_REG29__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG29__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG29__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG29__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG29__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG29__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG29__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG29__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG29__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG29__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN_MASK 0x000000ffL +#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ_MASK 0x0000ff00L +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000L +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ_MASK 0xff000000L + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG31__TC_MH_send 0x00000001L +#define MH_DEBUG_REG31__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG31__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG31__ROQ_MARK_q_0_MASK 0x00000004L +#define MH_DEBUG_REG31__ROQ_MARK_q_0 0x00000004L +#define MH_DEBUG_REG31__ROQ_VALID_q_0_MASK 0x00000008L +#define MH_DEBUG_REG31__ROQ_VALID_q_0 0x00000008L +#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0_MASK 0x00000010L +#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0 0x00000010L +#define MH_DEBUG_REG31__ROQ_ADDR_0_MASK 0xffffffe0L + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG32__TC_MH_send 0x00000001L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG32__ROQ_MARK_q_1_MASK 0x00000004L +#define MH_DEBUG_REG32__ROQ_MARK_q_1 0x00000004L +#define MH_DEBUG_REG32__ROQ_VALID_q_1_MASK 0x00000008L +#define MH_DEBUG_REG32__ROQ_VALID_q_1 0x00000008L +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1_MASK 0x00000010L +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1 0x00000010L +#define MH_DEBUG_REG32__ROQ_ADDR_1_MASK 0xffffffe0L + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG33__TC_MH_send 0x00000001L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG33__ROQ_MARK_q_2_MASK 0x00000004L +#define MH_DEBUG_REG33__ROQ_MARK_q_2 0x00000004L +#define MH_DEBUG_REG33__ROQ_VALID_q_2_MASK 0x00000008L +#define MH_DEBUG_REG33__ROQ_VALID_q_2 0x00000008L +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2_MASK 0x00000010L +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2 0x00000010L +#define MH_DEBUG_REG33__ROQ_ADDR_2_MASK 0xffffffe0L + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG34__TC_MH_send 0x00000001L +#define MH_DEBUG_REG34__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG34__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG34__ROQ_MARK_q_3_MASK 0x00000004L +#define MH_DEBUG_REG34__ROQ_MARK_q_3 0x00000004L +#define MH_DEBUG_REG34__ROQ_VALID_q_3_MASK 0x00000008L +#define MH_DEBUG_REG34__ROQ_VALID_q_3 0x00000008L +#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3_MASK 0x00000010L +#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3 0x00000010L +#define MH_DEBUG_REG34__ROQ_ADDR_3_MASK 0xffffffe0L + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG35__TC_MH_send 0x00000001L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG35__ROQ_MARK_q_4_MASK 0x00000004L +#define MH_DEBUG_REG35__ROQ_MARK_q_4 0x00000004L +#define MH_DEBUG_REG35__ROQ_VALID_q_4_MASK 0x00000008L +#define MH_DEBUG_REG35__ROQ_VALID_q_4 0x00000008L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4_MASK 0x00000010L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4 0x00000010L +#define MH_DEBUG_REG35__ROQ_ADDR_4_MASK 0xffffffe0L + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG36__TC_MH_send 0x00000001L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG36__ROQ_MARK_q_5_MASK 0x00000004L +#define MH_DEBUG_REG36__ROQ_MARK_q_5 0x00000004L +#define MH_DEBUG_REG36__ROQ_VALID_q_5_MASK 0x00000008L +#define MH_DEBUG_REG36__ROQ_VALID_q_5 0x00000008L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5_MASK 0x00000010L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5 0x00000010L +#define MH_DEBUG_REG36__ROQ_ADDR_5_MASK 0xffffffe0L + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG37__TC_MH_send 0x00000001L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG37__ROQ_MARK_q_6_MASK 0x00000004L +#define MH_DEBUG_REG37__ROQ_MARK_q_6 0x00000004L +#define MH_DEBUG_REG37__ROQ_VALID_q_6_MASK 0x00000008L +#define MH_DEBUG_REG37__ROQ_VALID_q_6 0x00000008L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6_MASK 0x00000010L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6 0x00000010L +#define MH_DEBUG_REG37__ROQ_ADDR_6_MASK 0xffffffe0L + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG38__TC_MH_send 0x00000001L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG38__ROQ_MARK_q_7_MASK 0x00000004L +#define MH_DEBUG_REG38__ROQ_MARK_q_7 0x00000004L +#define MH_DEBUG_REG38__ROQ_VALID_q_7_MASK 0x00000008L +#define MH_DEBUG_REG38__ROQ_VALID_q_7 0x00000008L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7_MASK 0x00000010L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7 0x00000010L +#define MH_DEBUG_REG38__ROQ_ADDR_7_MASK 0xffffffe0L + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG39__ARB_WE 0x00000001L +#define MH_DEBUG_REG39__MMU_RTR_MASK 0x00000002L +#define MH_DEBUG_REG39__MMU_RTR 0x00000002L +#define MH_DEBUG_REG39__ARB_ID_q_MASK 0x0000001cL +#define MH_DEBUG_REG39__ARB_WRITE_q_MASK 0x00000020L +#define MH_DEBUG_REG39__ARB_WRITE_q 0x00000020L +#define MH_DEBUG_REG39__ARB_BLEN_q_MASK 0x00000040L +#define MH_DEBUG_REG39__ARB_BLEN_q 0x00000040L +#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY 0x00000080L +#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q_MASK 0x00000700L +#define MH_DEBUG_REG39__MMU_WE_MASK 0x00000800L +#define MH_DEBUG_REG39__MMU_WE 0x00000800L +#define MH_DEBUG_REG39__ARQ_RTR_MASK 0x00001000L +#define MH_DEBUG_REG39__ARQ_RTR 0x00001000L +#define MH_DEBUG_REG39__MMU_ID_MASK 0x0000e000L +#define MH_DEBUG_REG39__MMU_WRITE_MASK 0x00010000L +#define MH_DEBUG_REG39__MMU_WRITE 0x00010000L +#define MH_DEBUG_REG39__MMU_BLEN_MASK 0x00020000L +#define MH_DEBUG_REG39__MMU_BLEN 0x00020000L + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG40__ARB_WE 0x00000001L +#define MH_DEBUG_REG40__ARB_ID_q_MASK 0x0000000eL +#define MH_DEBUG_REG40__ARB_VAD_q_MASK 0xfffffff0L + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__MMU_WE_MASK 0x00000001L +#define MH_DEBUG_REG41__MMU_WE 0x00000001L +#define MH_DEBUG_REG41__MMU_ID_MASK 0x0000000eL +#define MH_DEBUG_REG41__MMU_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__WDB_WE_MASK 0x00000001L +#define MH_DEBUG_REG42__WDB_WE 0x00000001L +#define MH_DEBUG_REG42__WDB_RTR_SKID_MASK 0x00000002L +#define MH_DEBUG_REG42__WDB_RTR_SKID 0x00000002L +#define MH_DEBUG_REG42__ARB_WSTRB_q_MASK 0x000003fcL +#define MH_DEBUG_REG42__ARB_WLAST_MASK 0x00000400L +#define MH_DEBUG_REG42__ARB_WLAST 0x00000400L +#define MH_DEBUG_REG42__WDB_CTRL_EMPTY_MASK 0x00000800L +#define MH_DEBUG_REG42__WDB_CTRL_EMPTY 0x00000800L +#define MH_DEBUG_REG42__WDB_FIFO_CNT_q_MASK 0x0001f000L +#define MH_DEBUG_REG42__WDC_WDB_RE_q_MASK 0x00020000L +#define MH_DEBUG_REG42__WDC_WDB_RE_q 0x00020000L +#define MH_DEBUG_REG42__WDB_WDC_WID_MASK 0x001c0000L +#define MH_DEBUG_REG42__WDB_WDC_WLAST_MASK 0x00200000L +#define MH_DEBUG_REG42__WDB_WDC_WLAST 0x00200000L +#define MH_DEBUG_REG42__WDB_WDC_WSTRB_MASK 0x3fc00000L + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_WDATA_q_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WDATA_q_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__CTRL_ARC_EMPTY_MASK 0x00000001L +#define MH_DEBUG_REG47__CTRL_ARC_EMPTY 0x00000001L +#define MH_DEBUG_REG47__CTRL_RARC_EMPTY_MASK 0x00000002L +#define MH_DEBUG_REG47__CTRL_RARC_EMPTY 0x00000002L +#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY_MASK 0x00000004L +#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY 0x00000004L +#define MH_DEBUG_REG47__ARQ_CTRL_WRITE_MASK 0x00000008L +#define MH_DEBUG_REG47__ARQ_CTRL_WRITE 0x00000008L +#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS_MASK 0x00000010L +#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS 0x00000010L +#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q_MASK 0x00000020L +#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q 0x00000020L +#define MH_DEBUG_REG47__INFLT_LIMIT_q_MASK 0x00000040L +#define MH_DEBUG_REG47__INFLT_LIMIT_q 0x00000040L +#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q_MASK 0x00001f80L +#define MH_DEBUG_REG47__ARC_CTRL_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG47__ARC_CTRL_RE_q 0x00002000L +#define MH_DEBUG_REG47__RARC_CTRL_RE_q_MASK 0x00004000L +#define MH_DEBUG_REG47__RARC_CTRL_RE_q 0x00004000L +#define MH_DEBUG_REG47__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG47__RVALID_q 0x00008000L +#define MH_DEBUG_REG47__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG47__RREADY_q 0x00010000L +#define MH_DEBUG_REG47__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG47__RLAST_q 0x00020000L +#define MH_DEBUG_REG47__BVALID_q_MASK 0x00040000L +#define MH_DEBUG_REG47__BVALID_q 0x00040000L +#define MH_DEBUG_REG47__BREADY_q_MASK 0x00080000L +#define MH_DEBUG_REG47__BREADY_q 0x00080000L + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG48__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG48__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG48__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG48__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG48__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG48__MH_TLBMISS_SEND_MASK 0x00000008L +#define MH_DEBUG_REG48__MH_TLBMISS_SEND 0x00000008L +#define MH_DEBUG_REG48__TLBMISS_VALID_MASK 0x00000010L +#define MH_DEBUG_REG48__TLBMISS_VALID 0x00000010L +#define MH_DEBUG_REG48__RDC_VALID_MASK 0x00000020L +#define MH_DEBUG_REG48__RDC_VALID 0x00000020L +#define MH_DEBUG_REG48__RDC_RID_MASK 0x000001c0L +#define MH_DEBUG_REG48__RDC_RLAST_MASK 0x00000200L +#define MH_DEBUG_REG48__RDC_RLAST 0x00000200L +#define MH_DEBUG_REG48__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS_MASK 0x00001000L +#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS 0x00001000L +#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q 0x00002000L +#define MH_DEBUG_REG48__MMU_ID_REQUEST_q_MASK 0x00004000L +#define MH_DEBUG_REG48__MMU_ID_REQUEST_q 0x00004000L +#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000L +#define MH_DEBUG_REG48__MMU_ID_RESPONSE_MASK 0x00200000L +#define MH_DEBUG_REG48__MMU_ID_RESPONSE 0x00200000L +#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q_MASK 0x0fc00000L +#define MH_DEBUG_REG48__CNT_HOLD_q1_MASK 0x10000000L +#define MH_DEBUG_REG48__CNT_HOLD_q1 0x10000000L +#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000L + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT_MASK 0xffffffffL + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__RF_MMU_CONFIG_q_MASK 0x00ffffffL +#define MH_DEBUG_REG50__ARB_ID_q_MASK 0x07000000L +#define MH_DEBUG_REG50__ARB_WRITE_q_MASK 0x08000000L +#define MH_DEBUG_REG50__ARB_WRITE_q 0x08000000L +#define MH_DEBUG_REG50__client_behavior_q_MASK 0x30000000L +#define MH_DEBUG_REG50__ARB_WE_MASK 0x40000000L +#define MH_DEBUG_REG50__ARB_WE 0x40000000L +#define MH_DEBUG_REG50__MMU_RTR_MASK 0x80000000L +#define MH_DEBUG_REG50__MMU_RTR 0x80000000L + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__stage1_valid_MASK 0x00000001L +#define MH_DEBUG_REG51__stage1_valid 0x00000001L +#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q_MASK 0x00000002L +#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q 0x00000002L +#define MH_DEBUG_REG51__pa_in_mpu_range_MASK 0x00000004L +#define MH_DEBUG_REG51__pa_in_mpu_range 0x00000004L +#define MH_DEBUG_REG51__tag_match_q_MASK 0x00000008L +#define MH_DEBUG_REG51__tag_match_q 0x00000008L +#define MH_DEBUG_REG51__tag_miss_q_MASK 0x00000010L +#define MH_DEBUG_REG51__tag_miss_q 0x00000010L +#define MH_DEBUG_REG51__va_in_range_q_MASK 0x00000020L +#define MH_DEBUG_REG51__va_in_range_q 0x00000020L +#define MH_DEBUG_REG51__MMU_MISS_MASK 0x00000040L +#define MH_DEBUG_REG51__MMU_MISS 0x00000040L +#define MH_DEBUG_REG51__MMU_READ_MISS_MASK 0x00000080L +#define MH_DEBUG_REG51__MMU_READ_MISS 0x00000080L +#define MH_DEBUG_REG51__MMU_WRITE_MISS_MASK 0x00000100L +#define MH_DEBUG_REG51__MMU_WRITE_MISS 0x00000100L +#define MH_DEBUG_REG51__MMU_HIT_MASK 0x00000200L +#define MH_DEBUG_REG51__MMU_HIT 0x00000200L +#define MH_DEBUG_REG51__MMU_READ_HIT_MASK 0x00000400L +#define MH_DEBUG_REG51__MMU_READ_HIT 0x00000400L +#define MH_DEBUG_REG51__MMU_WRITE_HIT_MASK 0x00000800L +#define MH_DEBUG_REG51__MMU_WRITE_HIT 0x00000800L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS 0x00001000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT 0x00002000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS 0x00004000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT 0x00008000L +#define MH_DEBUG_REG51__REQ_VA_OFFSET_q_MASK 0xffff0000L + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__ARQ_RTR_MASK 0x00000001L +#define MH_DEBUG_REG52__ARQ_RTR 0x00000001L +#define MH_DEBUG_REG52__MMU_WE_MASK 0x00000002L +#define MH_DEBUG_REG52__MMU_WE 0x00000002L +#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q_MASK 0x00000004L +#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q 0x00000004L +#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS_MASK 0x00000008L +#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS 0x00000008L +#define MH_DEBUG_REG52__MH_TLBMISS_SEND_MASK 0x00000010L +#define MH_DEBUG_REG52__MH_TLBMISS_SEND 0x00000010L +#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L +#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH 0x00000020L +#define MH_DEBUG_REG52__pa_in_mpu_range_MASK 0x00000040L +#define MH_DEBUG_REG52__pa_in_mpu_range 0x00000040L +#define MH_DEBUG_REG52__stage1_valid_MASK 0x00000080L +#define MH_DEBUG_REG52__stage1_valid 0x00000080L +#define MH_DEBUG_REG52__stage2_valid_MASK 0x00000100L +#define MH_DEBUG_REG52__stage2_valid 0x00000100L +#define MH_DEBUG_REG52__client_behavior_q_MASK 0x00000600L +#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q_MASK 0x00000800L +#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q 0x00000800L +#define MH_DEBUG_REG52__tag_match_q_MASK 0x00001000L +#define MH_DEBUG_REG52__tag_match_q 0x00001000L +#define MH_DEBUG_REG52__tag_miss_q_MASK 0x00002000L +#define MH_DEBUG_REG52__tag_miss_q 0x00002000L +#define MH_DEBUG_REG52__va_in_range_q_MASK 0x00004000L +#define MH_DEBUG_REG52__va_in_range_q 0x00004000L +#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q_MASK 0x00008000L +#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q 0x00008000L +#define MH_DEBUG_REG52__TAG_valid_q_MASK 0xffff0000L + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__TAG0_VA_MASK 0x00001fffL +#define MH_DEBUG_REG53__TAG_valid_q_0_MASK 0x00002000L +#define MH_DEBUG_REG53__TAG_valid_q_0 0x00002000L +#define MH_DEBUG_REG53__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG53__TAG1_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG53__TAG_valid_q_1_MASK 0x20000000L +#define MH_DEBUG_REG53__TAG_valid_q_1 0x20000000L + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__TAG2_VA_MASK 0x00001fffL +#define MH_DEBUG_REG54__TAG_valid_q_2_MASK 0x00002000L +#define MH_DEBUG_REG54__TAG_valid_q_2 0x00002000L +#define MH_DEBUG_REG54__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG54__TAG3_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG54__TAG_valid_q_3_MASK 0x20000000L +#define MH_DEBUG_REG54__TAG_valid_q_3 0x20000000L + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG4_VA_MASK 0x00001fffL +#define MH_DEBUG_REG55__TAG_valid_q_4_MASK 0x00002000L +#define MH_DEBUG_REG55__TAG_valid_q_4 0x00002000L +#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG55__TAG5_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG55__TAG_valid_q_5_MASK 0x20000000L +#define MH_DEBUG_REG55__TAG_valid_q_5 0x20000000L + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG6_VA_MASK 0x00001fffL +#define MH_DEBUG_REG56__TAG_valid_q_6_MASK 0x00002000L +#define MH_DEBUG_REG56__TAG_valid_q_6 0x00002000L +#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG56__TAG7_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG56__TAG_valid_q_7_MASK 0x20000000L +#define MH_DEBUG_REG56__TAG_valid_q_7 0x20000000L + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG8_VA_MASK 0x00001fffL +#define MH_DEBUG_REG57__TAG_valid_q_8_MASK 0x00002000L +#define MH_DEBUG_REG57__TAG_valid_q_8 0x00002000L +#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG57__TAG9_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG57__TAG_valid_q_9_MASK 0x20000000L +#define MH_DEBUG_REG57__TAG_valid_q_9 0x20000000L + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG10_VA_MASK 0x00001fffL +#define MH_DEBUG_REG58__TAG_valid_q_10_MASK 0x00002000L +#define MH_DEBUG_REG58__TAG_valid_q_10 0x00002000L +#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG58__TAG11_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG58__TAG_valid_q_11_MASK 0x20000000L +#define MH_DEBUG_REG58__TAG_valid_q_11 0x20000000L + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG12_VA_MASK 0x00001fffL +#define MH_DEBUG_REG59__TAG_valid_q_12_MASK 0x00002000L +#define MH_DEBUG_REG59__TAG_valid_q_12 0x00002000L +#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG59__TAG13_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG59__TAG_valid_q_13_MASK 0x20000000L +#define MH_DEBUG_REG59__TAG_valid_q_13 0x20000000L + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG14_VA_MASK 0x00001fffL +#define MH_DEBUG_REG60__TAG_valid_q_14_MASK 0x00002000L +#define MH_DEBUG_REG60__TAG_valid_q_14 0x00002000L +#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG60__TAG15_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG60__TAG_valid_q_15_MASK 0x20000000L +#define MH_DEBUG_REG60__TAG_valid_q_15 0x20000000L + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE_MASK 0x00000001L +#define MH_MMU_CONFIG__MMU_ENABLE 0x00000001L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK 0x00000002L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE 0x00000002L +#define MH_MMU_CONFIG__RESERVED1_MASK 0x0000000cL +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK 0x00000030L +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK 0x000000c0L +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK 0x00000300L +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00L +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK 0x00003000L +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000L +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK 0x00030000L +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000L +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000L +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK 0x00c00000L + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK 0x00000fffL +#define MH_MMU_VA_RANGE__VA_BASE_MASK 0xfffff000L + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE_MASK 0xfffff000L + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK 0x00000001L +#define MH_MMU_PAGE_FAULT__PAGE_FAULT 0x00000001L +#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK 0x00000002L +#define MH_MMU_PAGE_FAULT__OP_TYPE 0x00000002L +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK 0x0000000cL +#define MH_MMU_PAGE_FAULT__AXI_ID_MASK 0x00000070L +#define MH_MMU_PAGE_FAULT__RESERVED1_MASK 0x00000080L +#define MH_MMU_PAGE_FAULT__RESERVED1 0x00000080L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE 0x00000100L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK 0x00000200L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE 0x00000200L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK 0x00000400L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR 0x00000400L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK 0x00000800L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR 0x00000800L +#define MH_MMU_PAGE_FAULT__REQ_VA_MASK 0xfffff000L + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK 0xffffffe0L + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_ALL 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK 0x00000002L +#define MH_MMU_INVALIDATE__INVALIDATE_TC 0x00000002L + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE_MASK 0xfffff000L + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END_MASK 0xfffff000L + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK 0x00000002L +#define WAIT_UNTIL__WAIT_RE_VSYNC 0x00000002L +#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK 0x00000004L +#define WAIT_UNTIL__WAIT_FE_VSYNC 0x00000004L +#define WAIT_UNTIL__WAIT_VSYNC_MASK 0x00000008L +#define WAIT_UNTIL__WAIT_VSYNC 0x00000008L +#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID0 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID1 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK 0x00000040L +#define WAIT_UNTIL__WAIT_DSPLY_ID2 0x00000040L +#define WAIT_UNTIL__WAIT_CMDFIFO_MASK 0x00000400L +#define WAIT_UNTIL__WAIT_CMDFIFO 0x00000400L +#define WAIT_UNTIL__WAIT_2D_IDLE_MASK 0x00004000L +#define WAIT_UNTIL__WAIT_2D_IDLE 0x00004000L +#define WAIT_UNTIL__WAIT_3D_IDLE_MASK 0x00008000L +#define WAIT_UNTIL__WAIT_3D_IDLE 0x00008000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK 0x00010000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN 0x00010000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK 0x00020000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN 0x00020000L +#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK 0x00f00000L + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020L + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL +#define RBBM_STATUS__TC_BUSY_MASK 0x00000020L +#define RBBM_STATUS__TC_BUSY 0x00000020L +#define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L +#define RBBM_STATUS__HIRQ_PENDING 0x00000100L +#define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L +#define RBBM_STATUS__CPRQ_PENDING 0x00000200L +#define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L +#define RBBM_STATUS__CFRQ_PENDING 0x00000400L +#define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L +#define RBBM_STATUS__PFRQ_PENDING 0x00000800L +#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L +#define RBBM_STATUS__VGT_BUSY_NO_DMA 0x00001000L +#define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L +#define RBBM_STATUS__RBBM_WU_BUSY 0x00004000L +#define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L +#define RBBM_STATUS__CP_NRT_BUSY 0x00010000L +#define RBBM_STATUS__MH_BUSY_MASK 0x00040000L +#define RBBM_STATUS__MH_BUSY 0x00040000L +#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L +#define RBBM_STATUS__MH_COHERENCY_BUSY 0x00080000L +#define RBBM_STATUS__SX_BUSY_MASK 0x00200000L +#define RBBM_STATUS__SX_BUSY 0x00200000L +#define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L +#define RBBM_STATUS__TPC_BUSY 0x00400000L +#define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L +#define RBBM_STATUS__SC_CNTX_BUSY 0x01000000L +#define RBBM_STATUS__PA_BUSY_MASK 0x02000000L +#define RBBM_STATUS__PA_BUSY 0x02000000L +#define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L +#define RBBM_STATUS__VGT_BUSY 0x04000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY 0x08000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY 0x10000000L +#define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L +#define RBBM_STATUS__RB_CNTX_BUSY 0x40000000L +#define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +#define RBBM_STATUS__GUI_ACTIVE 0x80000000L + +// RBBM_DSPLY +#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE_MASK 0x00000001L +#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE 0x00000001L +#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE_MASK 0x00000002L +#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE 0x00000002L +#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE_MASK 0x00000004L +#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE 0x00000004L +#define RBBM_DSPLY__VSYNC_ACTIVE_MASK 0x00000008L +#define RBBM_DSPLY__VSYNC_ACTIVE 0x00000008L +#define RBBM_DSPLY__USE_DISPLAY_ID0_MASK 0x00000010L +#define RBBM_DSPLY__USE_DISPLAY_ID0 0x00000010L +#define RBBM_DSPLY__USE_DISPLAY_ID1_MASK 0x00000020L +#define RBBM_DSPLY__USE_DISPLAY_ID1 0x00000020L +#define RBBM_DSPLY__USE_DISPLAY_ID2_MASK 0x00000040L +#define RBBM_DSPLY__USE_DISPLAY_ID2 0x00000040L +#define RBBM_DSPLY__SW_CNTL_MASK 0x00000080L +#define RBBM_DSPLY__SW_CNTL 0x00000080L +#define RBBM_DSPLY__NUM_BUFS_MASK 0x00000300L + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__BUFFER_ID_MASK 0x00000003L + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST_MASK 0xffffffffL + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK 0x0000ffffL +#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK 0x00ff0000L +#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK 0xff000000L + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK 0xffffffffL + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0_MASK 0x000000ffL + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1_MASK 0x0000000fL +#define RBBM_PERIPHID1__DESIGNER0_MASK 0x000000f0L + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1_MASK 0x0000000fL +#define RBBM_PERIPHID2__REVISION_MASK 0x000000f0L + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK 0x00000003L +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK 0x0000000cL +#define RBBM_PERIPHID3__MH_INTERFACE_MASK 0x00000030L +#define RBBM_PERIPHID3__CONTINUATION_MASK 0x00000080L +#define RBBM_PERIPHID3__CONTINUATION 0x00000080L + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL +#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK 0x0001ff00L + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000001fL +#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK 0x000003e0L + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_PA 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_MH 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_BC 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_SX 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK 0x00010000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT 0x00010000L + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE 0x00004000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE 0x00010000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE 0x00200000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE 0x01000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK 0x02000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE 0x02000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK 0x08000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE 0x08000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000L + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE 0x00000800L + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK 0x0000ffffL +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK 0x80000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE 0x80000000L + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK 0x00000001L +#define NQWAIT_UNTIL__WAIT_GUI_IDLE 0x00000001L + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR_MASK 0x00000002L +#define RBBM_DEBUG__IGNORE_RTR 0x00000002L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI 0x00000010L +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK 0x00010000L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI 0x00010000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI 0x00020000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI 0x00040000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI 0x00080000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK 0x00100000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR 0x00100000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK 0x00200000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR 0x00200000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK 0x00400000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR 0x00400000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK 0x01000000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR 0x01000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK 0x80000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY 0x80000000L + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS_MASK 0x0001fffcL +#define RBBM_READ_ERROR__READ_REQUESTER_MASK 0x40000000L +#define RBBM_READ_ERROR__READ_REQUESTER 0x40000000L +#define RBBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define RBBM_READ_ERROR__READ_ERROR 0x80000000L + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ffL + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L +#define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK 0x00000002L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK 0x00080000L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L +#define RBBM_INT_STATUS__RDERR_INT_STAT 0x00000001L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK 0x00000002L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT 0x00000002L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK 0x00080000L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT 0x00080000L + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L +#define RBBM_INT_ACK__RDERR_INT_ACK 0x00000001L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK 0x00000002L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK 0x00000002L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK 0x00080000L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK 0x00080000L + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK 0x00000020L +#define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L +#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK 0x40000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK 0x80000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK 0x0000003fL + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0x0000ffffL + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE_MASK 0xffffffe0L + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB_CNTL__RB_POLL_EN_MASK 0x00100000L +#define CP_RB_CNTL__RB_POLL_EN 0x00100000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_NO_UPDATE 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA 0x80000000L + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK 0x00000003L +#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK 0xfffffffcL + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE_MASK 0xfffffffcL + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE_MASK 0xfffffffcL + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE_MASK 0xfffffffcL + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK 0x0000000fL +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK 0x00000f00L +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK 0x000f0000L + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END_MASK 0x001f0000L +#define CP_MEQ_THRESHOLDS__ROQ_END_MASK 0x1f000000L + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK 0x0000007fL +#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK 0x00007f00L +#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK 0x007f0000L + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST_MASK 0x0000007fL + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x0000001fL + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK 0x0000007fL +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK 0x007f0000L + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK 0x0000007fL +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK 0x007f0000L + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK 0x0000007fL +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK 0x007f0000L + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK 0x00000007L +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK 0x00000700L + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK 0x0000007fL +#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK 0x007f0000L + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK 0x00000001L +#define CP_MIU_TAG_STAT__TAG_0_STAT 0x00000001L +#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK 0x00000002L +#define CP_MIU_TAG_STAT__TAG_1_STAT 0x00000002L +#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK 0x00000004L +#define CP_MIU_TAG_STAT__TAG_2_STAT 0x00000004L +#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK 0x00000008L +#define CP_MIU_TAG_STAT__TAG_3_STAT 0x00000008L +#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK 0x00000010L +#define CP_MIU_TAG_STAT__TAG_4_STAT 0x00000010L +#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK 0x00000020L +#define CP_MIU_TAG_STAT__TAG_5_STAT 0x00000020L +#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK 0x00000040L +#define CP_MIU_TAG_STAT__TAG_6_STAT 0x00000040L +#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK 0x00000080L +#define CP_MIU_TAG_STAT__TAG_7_STAT 0x00000080L +#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK 0x00000100L +#define CP_MIU_TAG_STAT__TAG_8_STAT 0x00000100L +#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK 0x00000200L +#define CP_MIU_TAG_STAT__TAG_9_STAT 0x00000200L +#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK 0x00000400L +#define CP_MIU_TAG_STAT__TAG_10_STAT 0x00000400L +#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK 0x00000800L +#define CP_MIU_TAG_STAT__TAG_11_STAT 0x00000800L +#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK 0x00001000L +#define CP_MIU_TAG_STAT__TAG_12_STAT 0x00001000L +#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK 0x00002000L +#define CP_MIU_TAG_STAT__TAG_13_STAT 0x00002000L +#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK 0x00004000L +#define CP_MIU_TAG_STAT__TAG_14_STAT 0x00004000L +#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK 0x00008000L +#define CP_MIU_TAG_STAT__TAG_15_STAT 0x00008000L +#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK 0x00010000L +#define CP_MIU_TAG_STAT__TAG_16_STAT 0x00010000L +#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK 0x00020000L +#define CP_MIU_TAG_STAT__TAG_17_STAT 0x00020000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK 0x80000000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG 0x80000000L + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x0000007fL +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX_MASK 0x0000ffffL +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000L +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY 0x02000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY 0x04000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_HALT 0x10000000L +#define CP_ME_CNTL__ME_BUSY_MASK 0x20000000L +#define CP_ME_CNTL__ME_BUSY 0x20000000L +#define CP_ME_CNTL__PROG_CNT_SIZE_MASK 0x80000000L +#define CP_ME_CNTL__PROG_CNT_SIZE 0x80000000L + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA_MASK 0xffffffffL + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x000003ffL + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000003ffL + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR_MASK 0xffffffffL + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffffL +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__PREDICATE_DISABLE 0x00800000L +#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK 0x01000000L +#define CP_DEBUG__PROG_END_PTR_ENABLE 0x01000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK 0x02000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE 0x02000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK 0x04000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS 0x04000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK 0x08000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE 0x08000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK 0x10000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE 0x10000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL 0x40000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK 0x80000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE 0x80000000L + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK_MASK 0x000000ffL +#define SCRATCH_UMSK__SCRATCH_SWAP_MASK 0x00030000L + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR_MASK 0xffffffe0L + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR 0x00000002L + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR 0x00000002L + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK 0x00000001L +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC 0x00000001L + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK 0x00000003L +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK 0xffffffffL + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK 0x00000003L +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK 0xfffffffcL + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK 0xffffffffL + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK 0x00000001L +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR 0x00000001L + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK 0xffffffffL + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK_MASK 0x00080000L +#define CP_INT_CNTL__SW_INT_MASK 0x00080000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK 0x00800000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK 0x01000000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK 0x02000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L +#define CP_INT_CNTL__IB_ERROR_MASK_MASK 0x08000000L +#define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L +#define CP_INT_CNTL__IB2_INT_MASK_MASK 0x20000000L +#define CP_INT_CNTL__IB2_INT_MASK 0x20000000L +#define CP_INT_CNTL__IB1_INT_MASK_MASK 0x40000000L +#define CP_INT_CNTL__IB1_INT_MASK 0x40000000L +#define CP_INT_CNTL__RB_INT_MASK_MASK 0x80000000L +#define CP_INT_CNTL__RB_INT_MASK 0x80000000L + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__SW_INT_STAT 0x00080000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK 0x00800000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK 0x01000000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT 0x01000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK 0x02000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT 0x02000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT 0x04000000L +#define CP_INT_STATUS__IB_ERROR_STAT_MASK 0x08000000L +#define CP_INT_STATUS__IB_ERROR_STAT 0x08000000L +#define CP_INT_STATUS__IB2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__IB2_INT_STAT 0x20000000L +#define CP_INT_STATUS__IB1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__IB1_INT_STAT 0x40000000L +#define CP_INT_STATUS__RB_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS__RB_INT_STAT 0x80000000L + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK_MASK 0x00080000L +#define CP_INT_ACK__SW_INT_ACK 0x00080000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK 0x00800000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK 0x00800000L +#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK 0x01000000L +#define CP_INT_ACK__OPCODE_ERROR_ACK 0x01000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK 0x02000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK 0x02000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK 0x04000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK 0x04000000L +#define CP_INT_ACK__IB_ERROR_ACK_MASK 0x08000000L +#define CP_INT_ACK__IB_ERROR_ACK 0x08000000L +#define CP_INT_ACK__IB2_INT_ACK_MASK 0x20000000L +#define CP_INT_ACK__IB2_INT_ACK 0x20000000L +#define CP_INT_ACK__IB1_INT_ACK_MASK 0x40000000L +#define CP_INT_ACK__IB1_INT_ACK 0x40000000L +#define CP_INT_ACK__RB_INT_ACK_MASK 0x80000000L +#define CP_INT_ACK__RB_INT_ACK 0x80000000L + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000001ffL + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0x00ffffffL + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK 0x0000003fL + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK 0xffffffffL + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK 0x0000ffffL + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK 0xffffffffL + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK 0xffffffffL + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK 0xffffffffL + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK 0xffffffffL + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0_MASK 0x00000001L +#define CP_NV_FLAGS_0__DISCARD_0 0x00000001L +#define CP_NV_FLAGS_0__END_RCVD_0_MASK 0x00000002L +#define CP_NV_FLAGS_0__END_RCVD_0 0x00000002L +#define CP_NV_FLAGS_0__DISCARD_1_MASK 0x00000004L +#define CP_NV_FLAGS_0__DISCARD_1 0x00000004L +#define CP_NV_FLAGS_0__END_RCVD_1_MASK 0x00000008L +#define CP_NV_FLAGS_0__END_RCVD_1 0x00000008L +#define CP_NV_FLAGS_0__DISCARD_2_MASK 0x00000010L +#define CP_NV_FLAGS_0__DISCARD_2 0x00000010L +#define CP_NV_FLAGS_0__END_RCVD_2_MASK 0x00000020L +#define CP_NV_FLAGS_0__END_RCVD_2 0x00000020L +#define CP_NV_FLAGS_0__DISCARD_3_MASK 0x00000040L +#define CP_NV_FLAGS_0__DISCARD_3 0x00000040L +#define CP_NV_FLAGS_0__END_RCVD_3_MASK 0x00000080L +#define CP_NV_FLAGS_0__END_RCVD_3 0x00000080L +#define CP_NV_FLAGS_0__DISCARD_4_MASK 0x00000100L +#define CP_NV_FLAGS_0__DISCARD_4 0x00000100L +#define CP_NV_FLAGS_0__END_RCVD_4_MASK 0x00000200L +#define CP_NV_FLAGS_0__END_RCVD_4 0x00000200L +#define CP_NV_FLAGS_0__DISCARD_5_MASK 0x00000400L +#define CP_NV_FLAGS_0__DISCARD_5 0x00000400L +#define CP_NV_FLAGS_0__END_RCVD_5_MASK 0x00000800L +#define CP_NV_FLAGS_0__END_RCVD_5 0x00000800L +#define CP_NV_FLAGS_0__DISCARD_6_MASK 0x00001000L +#define CP_NV_FLAGS_0__DISCARD_6 0x00001000L +#define CP_NV_FLAGS_0__END_RCVD_6_MASK 0x00002000L +#define CP_NV_FLAGS_0__END_RCVD_6 0x00002000L +#define CP_NV_FLAGS_0__DISCARD_7_MASK 0x00004000L +#define CP_NV_FLAGS_0__DISCARD_7 0x00004000L +#define CP_NV_FLAGS_0__END_RCVD_7_MASK 0x00008000L +#define CP_NV_FLAGS_0__END_RCVD_7 0x00008000L +#define CP_NV_FLAGS_0__DISCARD_8_MASK 0x00010000L +#define CP_NV_FLAGS_0__DISCARD_8 0x00010000L +#define CP_NV_FLAGS_0__END_RCVD_8_MASK 0x00020000L +#define CP_NV_FLAGS_0__END_RCVD_8 0x00020000L +#define CP_NV_FLAGS_0__DISCARD_9_MASK 0x00040000L +#define CP_NV_FLAGS_0__DISCARD_9 0x00040000L +#define CP_NV_FLAGS_0__END_RCVD_9_MASK 0x00080000L +#define CP_NV_FLAGS_0__END_RCVD_9 0x00080000L +#define CP_NV_FLAGS_0__DISCARD_10_MASK 0x00100000L +#define CP_NV_FLAGS_0__DISCARD_10 0x00100000L +#define CP_NV_FLAGS_0__END_RCVD_10_MASK 0x00200000L +#define CP_NV_FLAGS_0__END_RCVD_10 0x00200000L +#define CP_NV_FLAGS_0__DISCARD_11_MASK 0x00400000L +#define CP_NV_FLAGS_0__DISCARD_11 0x00400000L +#define CP_NV_FLAGS_0__END_RCVD_11_MASK 0x00800000L +#define CP_NV_FLAGS_0__END_RCVD_11 0x00800000L +#define CP_NV_FLAGS_0__DISCARD_12_MASK 0x01000000L +#define CP_NV_FLAGS_0__DISCARD_12 0x01000000L +#define CP_NV_FLAGS_0__END_RCVD_12_MASK 0x02000000L +#define CP_NV_FLAGS_0__END_RCVD_12 0x02000000L +#define CP_NV_FLAGS_0__DISCARD_13_MASK 0x04000000L +#define CP_NV_FLAGS_0__DISCARD_13 0x04000000L +#define CP_NV_FLAGS_0__END_RCVD_13_MASK 0x08000000L +#define CP_NV_FLAGS_0__END_RCVD_13 0x08000000L +#define CP_NV_FLAGS_0__DISCARD_14_MASK 0x10000000L +#define CP_NV_FLAGS_0__DISCARD_14 0x10000000L +#define CP_NV_FLAGS_0__END_RCVD_14_MASK 0x20000000L +#define CP_NV_FLAGS_0__END_RCVD_14 0x20000000L +#define CP_NV_FLAGS_0__DISCARD_15_MASK 0x40000000L +#define CP_NV_FLAGS_0__DISCARD_15 0x40000000L +#define CP_NV_FLAGS_0__END_RCVD_15_MASK 0x80000000L +#define CP_NV_FLAGS_0__END_RCVD_15 0x80000000L + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16_MASK 0x00000001L +#define CP_NV_FLAGS_1__DISCARD_16 0x00000001L +#define CP_NV_FLAGS_1__END_RCVD_16_MASK 0x00000002L +#define CP_NV_FLAGS_1__END_RCVD_16 0x00000002L +#define CP_NV_FLAGS_1__DISCARD_17_MASK 0x00000004L +#define CP_NV_FLAGS_1__DISCARD_17 0x00000004L +#define CP_NV_FLAGS_1__END_RCVD_17_MASK 0x00000008L +#define CP_NV_FLAGS_1__END_RCVD_17 0x00000008L +#define CP_NV_FLAGS_1__DISCARD_18_MASK 0x00000010L +#define CP_NV_FLAGS_1__DISCARD_18 0x00000010L +#define CP_NV_FLAGS_1__END_RCVD_18_MASK 0x00000020L +#define CP_NV_FLAGS_1__END_RCVD_18 0x00000020L +#define CP_NV_FLAGS_1__DISCARD_19_MASK 0x00000040L +#define CP_NV_FLAGS_1__DISCARD_19 0x00000040L +#define CP_NV_FLAGS_1__END_RCVD_19_MASK 0x00000080L +#define CP_NV_FLAGS_1__END_RCVD_19 0x00000080L +#define CP_NV_FLAGS_1__DISCARD_20_MASK 0x00000100L +#define CP_NV_FLAGS_1__DISCARD_20 0x00000100L +#define CP_NV_FLAGS_1__END_RCVD_20_MASK 0x00000200L +#define CP_NV_FLAGS_1__END_RCVD_20 0x00000200L +#define CP_NV_FLAGS_1__DISCARD_21_MASK 0x00000400L +#define CP_NV_FLAGS_1__DISCARD_21 0x00000400L +#define CP_NV_FLAGS_1__END_RCVD_21_MASK 0x00000800L +#define CP_NV_FLAGS_1__END_RCVD_21 0x00000800L +#define CP_NV_FLAGS_1__DISCARD_22_MASK 0x00001000L +#define CP_NV_FLAGS_1__DISCARD_22 0x00001000L +#define CP_NV_FLAGS_1__END_RCVD_22_MASK 0x00002000L +#define CP_NV_FLAGS_1__END_RCVD_22 0x00002000L +#define CP_NV_FLAGS_1__DISCARD_23_MASK 0x00004000L +#define CP_NV_FLAGS_1__DISCARD_23 0x00004000L +#define CP_NV_FLAGS_1__END_RCVD_23_MASK 0x00008000L +#define CP_NV_FLAGS_1__END_RCVD_23 0x00008000L +#define CP_NV_FLAGS_1__DISCARD_24_MASK 0x00010000L +#define CP_NV_FLAGS_1__DISCARD_24 0x00010000L +#define CP_NV_FLAGS_1__END_RCVD_24_MASK 0x00020000L +#define CP_NV_FLAGS_1__END_RCVD_24 0x00020000L +#define CP_NV_FLAGS_1__DISCARD_25_MASK 0x00040000L +#define CP_NV_FLAGS_1__DISCARD_25 0x00040000L +#define CP_NV_FLAGS_1__END_RCVD_25_MASK 0x00080000L +#define CP_NV_FLAGS_1__END_RCVD_25 0x00080000L +#define CP_NV_FLAGS_1__DISCARD_26_MASK 0x00100000L +#define CP_NV_FLAGS_1__DISCARD_26 0x00100000L +#define CP_NV_FLAGS_1__END_RCVD_26_MASK 0x00200000L +#define CP_NV_FLAGS_1__END_RCVD_26 0x00200000L +#define CP_NV_FLAGS_1__DISCARD_27_MASK 0x00400000L +#define CP_NV_FLAGS_1__DISCARD_27 0x00400000L +#define CP_NV_FLAGS_1__END_RCVD_27_MASK 0x00800000L +#define CP_NV_FLAGS_1__END_RCVD_27 0x00800000L +#define CP_NV_FLAGS_1__DISCARD_28_MASK 0x01000000L +#define CP_NV_FLAGS_1__DISCARD_28 0x01000000L +#define CP_NV_FLAGS_1__END_RCVD_28_MASK 0x02000000L +#define CP_NV_FLAGS_1__END_RCVD_28 0x02000000L +#define CP_NV_FLAGS_1__DISCARD_29_MASK 0x04000000L +#define CP_NV_FLAGS_1__DISCARD_29 0x04000000L +#define CP_NV_FLAGS_1__END_RCVD_29_MASK 0x08000000L +#define CP_NV_FLAGS_1__END_RCVD_29 0x08000000L +#define CP_NV_FLAGS_1__DISCARD_30_MASK 0x10000000L +#define CP_NV_FLAGS_1__DISCARD_30 0x10000000L +#define CP_NV_FLAGS_1__END_RCVD_30_MASK 0x20000000L +#define CP_NV_FLAGS_1__END_RCVD_30 0x20000000L +#define CP_NV_FLAGS_1__DISCARD_31_MASK 0x40000000L +#define CP_NV_FLAGS_1__DISCARD_31 0x40000000L +#define CP_NV_FLAGS_1__END_RCVD_31_MASK 0x80000000L +#define CP_NV_FLAGS_1__END_RCVD_31 0x80000000L + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32_MASK 0x00000001L +#define CP_NV_FLAGS_2__DISCARD_32 0x00000001L +#define CP_NV_FLAGS_2__END_RCVD_32_MASK 0x00000002L +#define CP_NV_FLAGS_2__END_RCVD_32 0x00000002L +#define CP_NV_FLAGS_2__DISCARD_33_MASK 0x00000004L +#define CP_NV_FLAGS_2__DISCARD_33 0x00000004L +#define CP_NV_FLAGS_2__END_RCVD_33_MASK 0x00000008L +#define CP_NV_FLAGS_2__END_RCVD_33 0x00000008L +#define CP_NV_FLAGS_2__DISCARD_34_MASK 0x00000010L +#define CP_NV_FLAGS_2__DISCARD_34 0x00000010L +#define CP_NV_FLAGS_2__END_RCVD_34_MASK 0x00000020L +#define CP_NV_FLAGS_2__END_RCVD_34 0x00000020L +#define CP_NV_FLAGS_2__DISCARD_35_MASK 0x00000040L +#define CP_NV_FLAGS_2__DISCARD_35 0x00000040L +#define CP_NV_FLAGS_2__END_RCVD_35_MASK 0x00000080L +#define CP_NV_FLAGS_2__END_RCVD_35 0x00000080L +#define CP_NV_FLAGS_2__DISCARD_36_MASK 0x00000100L +#define CP_NV_FLAGS_2__DISCARD_36 0x00000100L +#define CP_NV_FLAGS_2__END_RCVD_36_MASK 0x00000200L +#define CP_NV_FLAGS_2__END_RCVD_36 0x00000200L +#define CP_NV_FLAGS_2__DISCARD_37_MASK 0x00000400L +#define CP_NV_FLAGS_2__DISCARD_37 0x00000400L +#define CP_NV_FLAGS_2__END_RCVD_37_MASK 0x00000800L +#define CP_NV_FLAGS_2__END_RCVD_37 0x00000800L +#define CP_NV_FLAGS_2__DISCARD_38_MASK 0x00001000L +#define CP_NV_FLAGS_2__DISCARD_38 0x00001000L +#define CP_NV_FLAGS_2__END_RCVD_38_MASK 0x00002000L +#define CP_NV_FLAGS_2__END_RCVD_38 0x00002000L +#define CP_NV_FLAGS_2__DISCARD_39_MASK 0x00004000L +#define CP_NV_FLAGS_2__DISCARD_39 0x00004000L +#define CP_NV_FLAGS_2__END_RCVD_39_MASK 0x00008000L +#define CP_NV_FLAGS_2__END_RCVD_39 0x00008000L +#define CP_NV_FLAGS_2__DISCARD_40_MASK 0x00010000L +#define CP_NV_FLAGS_2__DISCARD_40 0x00010000L +#define CP_NV_FLAGS_2__END_RCVD_40_MASK 0x00020000L +#define CP_NV_FLAGS_2__END_RCVD_40 0x00020000L +#define CP_NV_FLAGS_2__DISCARD_41_MASK 0x00040000L +#define CP_NV_FLAGS_2__DISCARD_41 0x00040000L +#define CP_NV_FLAGS_2__END_RCVD_41_MASK 0x00080000L +#define CP_NV_FLAGS_2__END_RCVD_41 0x00080000L +#define CP_NV_FLAGS_2__DISCARD_42_MASK 0x00100000L +#define CP_NV_FLAGS_2__DISCARD_42 0x00100000L +#define CP_NV_FLAGS_2__END_RCVD_42_MASK 0x00200000L +#define CP_NV_FLAGS_2__END_RCVD_42 0x00200000L +#define CP_NV_FLAGS_2__DISCARD_43_MASK 0x00400000L +#define CP_NV_FLAGS_2__DISCARD_43 0x00400000L +#define CP_NV_FLAGS_2__END_RCVD_43_MASK 0x00800000L +#define CP_NV_FLAGS_2__END_RCVD_43 0x00800000L +#define CP_NV_FLAGS_2__DISCARD_44_MASK 0x01000000L +#define CP_NV_FLAGS_2__DISCARD_44 0x01000000L +#define CP_NV_FLAGS_2__END_RCVD_44_MASK 0x02000000L +#define CP_NV_FLAGS_2__END_RCVD_44 0x02000000L +#define CP_NV_FLAGS_2__DISCARD_45_MASK 0x04000000L +#define CP_NV_FLAGS_2__DISCARD_45 0x04000000L +#define CP_NV_FLAGS_2__END_RCVD_45_MASK 0x08000000L +#define CP_NV_FLAGS_2__END_RCVD_45 0x08000000L +#define CP_NV_FLAGS_2__DISCARD_46_MASK 0x10000000L +#define CP_NV_FLAGS_2__DISCARD_46 0x10000000L +#define CP_NV_FLAGS_2__END_RCVD_46_MASK 0x20000000L +#define CP_NV_FLAGS_2__END_RCVD_46 0x20000000L +#define CP_NV_FLAGS_2__DISCARD_47_MASK 0x40000000L +#define CP_NV_FLAGS_2__DISCARD_47 0x40000000L +#define CP_NV_FLAGS_2__END_RCVD_47_MASK 0x80000000L +#define CP_NV_FLAGS_2__END_RCVD_47 0x80000000L + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48_MASK 0x00000001L +#define CP_NV_FLAGS_3__DISCARD_48 0x00000001L +#define CP_NV_FLAGS_3__END_RCVD_48_MASK 0x00000002L +#define CP_NV_FLAGS_3__END_RCVD_48 0x00000002L +#define CP_NV_FLAGS_3__DISCARD_49_MASK 0x00000004L +#define CP_NV_FLAGS_3__DISCARD_49 0x00000004L +#define CP_NV_FLAGS_3__END_RCVD_49_MASK 0x00000008L +#define CP_NV_FLAGS_3__END_RCVD_49 0x00000008L +#define CP_NV_FLAGS_3__DISCARD_50_MASK 0x00000010L +#define CP_NV_FLAGS_3__DISCARD_50 0x00000010L +#define CP_NV_FLAGS_3__END_RCVD_50_MASK 0x00000020L +#define CP_NV_FLAGS_3__END_RCVD_50 0x00000020L +#define CP_NV_FLAGS_3__DISCARD_51_MASK 0x00000040L +#define CP_NV_FLAGS_3__DISCARD_51 0x00000040L +#define CP_NV_FLAGS_3__END_RCVD_51_MASK 0x00000080L +#define CP_NV_FLAGS_3__END_RCVD_51 0x00000080L +#define CP_NV_FLAGS_3__DISCARD_52_MASK 0x00000100L +#define CP_NV_FLAGS_3__DISCARD_52 0x00000100L +#define CP_NV_FLAGS_3__END_RCVD_52_MASK 0x00000200L +#define CP_NV_FLAGS_3__END_RCVD_52 0x00000200L +#define CP_NV_FLAGS_3__DISCARD_53_MASK 0x00000400L +#define CP_NV_FLAGS_3__DISCARD_53 0x00000400L +#define CP_NV_FLAGS_3__END_RCVD_53_MASK 0x00000800L +#define CP_NV_FLAGS_3__END_RCVD_53 0x00000800L +#define CP_NV_FLAGS_3__DISCARD_54_MASK 0x00001000L +#define CP_NV_FLAGS_3__DISCARD_54 0x00001000L +#define CP_NV_FLAGS_3__END_RCVD_54_MASK 0x00002000L +#define CP_NV_FLAGS_3__END_RCVD_54 0x00002000L +#define CP_NV_FLAGS_3__DISCARD_55_MASK 0x00004000L +#define CP_NV_FLAGS_3__DISCARD_55 0x00004000L +#define CP_NV_FLAGS_3__END_RCVD_55_MASK 0x00008000L +#define CP_NV_FLAGS_3__END_RCVD_55 0x00008000L +#define CP_NV_FLAGS_3__DISCARD_56_MASK 0x00010000L +#define CP_NV_FLAGS_3__DISCARD_56 0x00010000L +#define CP_NV_FLAGS_3__END_RCVD_56_MASK 0x00020000L +#define CP_NV_FLAGS_3__END_RCVD_56 0x00020000L +#define CP_NV_FLAGS_3__DISCARD_57_MASK 0x00040000L +#define CP_NV_FLAGS_3__DISCARD_57 0x00040000L +#define CP_NV_FLAGS_3__END_RCVD_57_MASK 0x00080000L +#define CP_NV_FLAGS_3__END_RCVD_57 0x00080000L +#define CP_NV_FLAGS_3__DISCARD_58_MASK 0x00100000L +#define CP_NV_FLAGS_3__DISCARD_58 0x00100000L +#define CP_NV_FLAGS_3__END_RCVD_58_MASK 0x00200000L +#define CP_NV_FLAGS_3__END_RCVD_58 0x00200000L +#define CP_NV_FLAGS_3__DISCARD_59_MASK 0x00400000L +#define CP_NV_FLAGS_3__DISCARD_59 0x00400000L +#define CP_NV_FLAGS_3__END_RCVD_59_MASK 0x00800000L +#define CP_NV_FLAGS_3__END_RCVD_59 0x00800000L +#define CP_NV_FLAGS_3__DISCARD_60_MASK 0x01000000L +#define CP_NV_FLAGS_3__DISCARD_60 0x01000000L +#define CP_NV_FLAGS_3__END_RCVD_60_MASK 0x02000000L +#define CP_NV_FLAGS_3__END_RCVD_60 0x02000000L +#define CP_NV_FLAGS_3__DISCARD_61_MASK 0x04000000L +#define CP_NV_FLAGS_3__DISCARD_61 0x04000000L +#define CP_NV_FLAGS_3__END_RCVD_61_MASK 0x08000000L +#define CP_NV_FLAGS_3__END_RCVD_61 0x08000000L +#define CP_NV_FLAGS_3__DISCARD_62_MASK 0x10000000L +#define CP_NV_FLAGS_3__DISCARD_62 0x10000000L +#define CP_NV_FLAGS_3__END_RCVD_62_MASK 0x20000000L +#define CP_NV_FLAGS_3__END_RCVD_62 0x20000000L +#define CP_NV_FLAGS_3__DISCARD_63_MASK 0x40000000L +#define CP_NV_FLAGS_3__DISCARD_63 0x40000000L +#define CP_NV_FLAGS_3__END_RCVD_63_MASK 0x80000000L +#define CP_NV_FLAGS_3__END_RCVD_63 0x80000000L + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK 0x0000001fL + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK 0xffffffffL + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER_MASK 0xffffffffL + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY_MASK 0x00000001L +#define CP_STAT__MIU_WR_BUSY 0x00000001L +#define CP_STAT__MIU_RD_REQ_BUSY_MASK 0x00000002L +#define CP_STAT__MIU_RD_REQ_BUSY 0x00000002L +#define CP_STAT__MIU_RD_RETURN_BUSY_MASK 0x00000004L +#define CP_STAT__MIU_RD_RETURN_BUSY 0x00000004L +#define CP_STAT__RBIU_BUSY_MASK 0x00000008L +#define CP_STAT__RBIU_BUSY 0x00000008L +#define CP_STAT__RCIU_BUSY_MASK 0x00000010L +#define CP_STAT__RCIU_BUSY 0x00000010L +#define CP_STAT__CSF_RING_BUSY_MASK 0x00000020L +#define CP_STAT__CSF_RING_BUSY 0x00000020L +#define CP_STAT__CSF_INDIRECTS_BUSY_MASK 0x00000040L +#define CP_STAT__CSF_INDIRECTS_BUSY 0x00000040L +#define CP_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_STAT__CSF_INDIRECT2_BUSY 0x00000080L +#define CP_STAT__CSF_ST_BUSY_MASK 0x00000200L +#define CP_STAT__CSF_ST_BUSY 0x00000200L +#define CP_STAT__CSF_BUSY_MASK 0x00000400L +#define CP_STAT__CSF_BUSY 0x00000400L +#define CP_STAT__RING_QUEUE_BUSY_MASK 0x00000800L +#define CP_STAT__RING_QUEUE_BUSY 0x00000800L +#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK 0x00001000L +#define CP_STAT__INDIRECTS_QUEUE_BUSY 0x00001000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK 0x00002000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY 0x00002000L +#define CP_STAT__ST_QUEUE_BUSY_MASK 0x00010000L +#define CP_STAT__ST_QUEUE_BUSY 0x00010000L +#define CP_STAT__PFP_BUSY_MASK 0x00020000L +#define CP_STAT__PFP_BUSY 0x00020000L +#define CP_STAT__MEQ_RING_BUSY_MASK 0x00040000L +#define CP_STAT__MEQ_RING_BUSY 0x00040000L +#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK 0x00080000L +#define CP_STAT__MEQ_INDIRECTS_BUSY 0x00080000L +#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK 0x00100000L +#define CP_STAT__MEQ_INDIRECT2_BUSY 0x00100000L +#define CP_STAT__MIU_WC_STALL_MASK 0x00200000L +#define CP_STAT__MIU_WC_STALL 0x00200000L +#define CP_STAT__CP_NRT_BUSY_MASK 0x00400000L +#define CP_STAT__CP_NRT_BUSY 0x00400000L +#define CP_STAT___3D_BUSY_MASK 0x00800000L +#define CP_STAT___3D_BUSY 0x00800000L +#define CP_STAT__ME_BUSY_MASK 0x04000000L +#define CP_STAT__ME_BUSY 0x04000000L +#define CP_STAT__ME_WC_BUSY_MASK 0x20000000L +#define CP_STAT__ME_WC_BUSY 0x20000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +#define CP_STAT__CP_BUSY 0x80000000L + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE_MASK 0xffffffffL + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE_MASK 0xffffffffL + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_PM4__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_PM4__STATUS_MASK 0x80000000L +#define COHER_STATUS_PM4__STATUS 0x80000000L + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE_MASK 0xffffffffL + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE_MASK 0xffffffffL + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_HOST__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_HOST__STATUS_MASK 0x80000000L +#define COHER_STATUS_HOST__STATUS 0x80000000L + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0_MASK 0xfffff000L + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1_MASK 0xfffff000L + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2_MASK 0xfffff000L + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3_MASK 0xfffff000L + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4_MASK 0xfffff000L + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5_MASK 0xfffff000L + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6_MASK 0xfffff000L + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7_MASK 0xfffff000L + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH_MASK 0x00003fffL +#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK 0x0000c000L + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL +#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK 0x00000030L +#define RB_COLOR_INFO__COLOR_LINEAR_MASK 0x00000040L +#define RB_COLOR_INFO__COLOR_LINEAR 0x00000040L +#define RB_COLOR_INFO__COLOR_ENDIAN_MASK 0x00000180L +#define RB_COLOR_INFO__COLOR_SWAP_MASK 0x00000600L +#define RB_COLOR_INFO__COLOR_BASE_MASK 0xfffff000L + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK 0x00000001L +#define RB_DEPTH_INFO__DEPTH_FORMAT 0x00000001L +#define RB_DEPTH_INFO__DEPTH_BASE_MASK 0xfffff000L + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF_MASK 0x000000ffL +#define RB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L +#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF_MASK 0xffffffffL + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED_MASK 0x00000001L +#define RB_COLOR_MASK__WRITE_RED 0x00000001L +#define RB_COLOR_MASK__WRITE_GREEN_MASK 0x00000002L +#define RB_COLOR_MASK__WRITE_GREEN 0x00000002L +#define RB_COLOR_MASK__WRITE_BLUE_MASK 0x00000004L +#define RB_COLOR_MASK__WRITE_BLUE 0x00000004L +#define RB_COLOR_MASK__WRITE_ALPHA_MASK 0x00000008L +#define RB_COLOR_MASK__WRITE_ALPHA 0x00000008L + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED_MASK 0x000000ffL + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN_MASK 0x000000ffL + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE_MASK 0x000000ffL + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK 0x000000ffL + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED_MASK 0x000000ffL +#define RB_FOG_COLOR__FOG_GREEN_MASK 0x0000ff00L +#define RB_FOG_COLOR__FOG_BLUE_MASK 0x00ff0000L + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK 0x000000ffL +#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define RB_DEPTHCONTROL__STENCIL_ENABLE 0x00000001L +#define RB_DEPTHCONTROL__Z_ENABLE_MASK 0x00000002L +#define RB_DEPTHCONTROL__Z_ENABLE 0x00000002L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE 0x00000004L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK 0x00000008L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE 0x00000008L +#define RB_DEPTHCONTROL__ZFUNC_MASK 0x00000070L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE 0x00000080L +#define RB_DEPTHCONTROL__STENCILFUNC_MASK 0x00000700L +#define RB_DEPTHCONTROL__STENCILFAIL_MASK 0x00003800L +#define RB_DEPTHCONTROL__STENCILZPASS_MASK 0x0001c000L +#define RB_DEPTHCONTROL__STENCILZFAIL_MASK 0x000e0000L +#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK 0x03800000L +#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK 0x1c000000L +#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK 0xe0000000L + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_MASK 0x40000000L +#define RB_BLENDCONTROL__BLEND_FORCE 0x40000000L + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC_MASK 0x00000007L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK 0x00000008L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE 0x00000008L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK 0x00000010L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE 0x00000010L +#define RB_COLORCONTROL__BLEND_DISABLE_MASK 0x00000020L +#define RB_COLORCONTROL__BLEND_DISABLE 0x00000020L +#define RB_COLORCONTROL__FOG_ENABLE_MASK 0x00000040L +#define RB_COLORCONTROL__FOG_ENABLE 0x00000040L +#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK 0x00000080L +#define RB_COLORCONTROL__VS_EXPORTS_FOG 0x00000080L +#define RB_COLORCONTROL__ROP_CODE_MASK 0x00000f00L +#define RB_COLORCONTROL__DITHER_MODE_MASK 0x00003000L +#define RB_COLORCONTROL__DITHER_TYPE_MASK 0x0000c000L +#define RB_COLORCONTROL__PIXEL_FOG_MASK 0x00010000L +#define RB_COLORCONTROL__PIXEL_FOG 0x00010000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK 0x03000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK 0x30000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000L + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE_MASK 0x00000007L + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK 0xffffffffL + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK 0x00000007L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000008L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE 0x00000008L +#define RB_COPY_CONTROL__CLEAR_MASK_MASK 0x000000f0L + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK 0xfffff000L + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK 0x000001ffL + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK 0x00000007L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK 0x000000f0L +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK 0x00000300L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK 0x00000c00L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK 0x00003000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK 0x00020000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA 0x00020000L + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK 0x00001fffL +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK 0x03ffe000L + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK 0x00000001L +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT 0x00000001L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK 0x00000002L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT 0x00000002L + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK 0xffffffffL + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001L +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE 0x00000001L +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK 0x00000006L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK 0x00000008L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM 0x00000008L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP 0x00000020L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP 0x00000040L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK 0x00000080L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE 0x00000080L +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK 0x00001f00L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK 0x00004000L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE 0x00004000L +#define RB_BC_CONTROL__CRC_MODE_MASK 0x00008000L +#define RB_BC_CONTROL__CRC_MODE 0x00008000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK 0x00010000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS 0x00010000L +#define RB_BC_CONTROL__DISABLE_ACCUM_MASK 0x00020000L +#define RB_BC_CONTROL__DISABLE_ACCUM 0x00020000L +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK 0x003c0000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE 0x00400000L +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000L +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000L +#define RB_BC_CONTROL__RESERVED9_MASK 0x40000000L +#define RB_BC_CONTROL__RESERVED9 0x40000000L +#define RB_BC_CONTROL__RESERVED10_MASK 0x80000000L +#define RB_BC_CONTROL__RESERVED10 0x80000000L + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK 0x00000030L +#define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA_MASK 0xffffffffL + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK 0x00000001L +#define RB_CRC_CONTROL__CRC_RD_ADVANCE 0x00000001L + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK_MASK 0xffffffffL + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK 0xffffffffL + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK 0xffffffffL + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK 0xffffffffL + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK 0xffffffffL + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL 0x00000008L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK 0x00000010L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL 0x00000010L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK 0x00000020L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL 0x00000020L +#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK 0x00000040L +#define RB_DEBUG_0__RDREQ_Z1_FULL 0x00000040L +#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK 0x00000080L +#define RB_DEBUG_0__RDREQ_Z0_FULL 0x00000080L +#define RB_DEBUG_0__RDREQ_C1_FULL_MASK 0x00000100L +#define RB_DEBUG_0__RDREQ_C1_FULL 0x00000100L +#define RB_DEBUG_0__RDREQ_C0_FULL_MASK 0x00000200L +#define RB_DEBUG_0__RDREQ_C0_FULL 0x00000200L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL 0x00000800L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL 0x00002000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK 0x00008000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL 0x00008000L +#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK 0x00010000L +#define RB_DEBUG_0__WRREQ_Z1_FULL 0x00010000L +#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK 0x00020000L +#define RB_DEBUG_0__WRREQ_Z0_FULL 0x00020000L +#define RB_DEBUG_0__WRREQ_C1_FULL_MASK 0x00040000L +#define RB_DEBUG_0__WRREQ_C1_FULL 0x00040000L +#define RB_DEBUG_0__WRREQ_C0_FULL_MASK 0x00080000L +#define RB_DEBUG_0__WRREQ_C0_FULL 0x00080000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL 0x00200000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK 0x00800000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL 0x00800000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL 0x01000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK 0x02000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL 0x02000000L +#define RB_DEBUG_0__C_SX_LAT_FULL_MASK 0x04000000L +#define RB_DEBUG_0__C_SX_LAT_FULL 0x04000000L +#define RB_DEBUG_0__C_SX_CMD_FULL_MASK 0x08000000L +#define RB_DEBUG_0__C_SX_CMD_FULL 0x08000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK 0x10000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL 0x10000000L +#define RB_DEBUG_0__C_REQ_FULL_MASK 0x20000000L +#define RB_DEBUG_0__C_REQ_FULL 0x20000000L +#define RB_DEBUG_0__C_MASK_FULL_MASK 0x40000000L +#define RB_DEBUG_0__C_MASK_FULL 0x40000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK 0x80000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL 0x80000000L + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK 0x00000001L +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY 0x00000001L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK 0x00000002L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY 0x00000002L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK 0x00000004L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY 0x00000004L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK 0x00000008L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY 0x00000008L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY 0x00000010L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY 0x00000020L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK 0x00000040L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY 0x00000040L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK 0x00000080L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY 0x00000080L +#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK 0x00000100L +#define RB_DEBUG_1__RDREQ_C1_EMPTY 0x00000100L +#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK 0x00000200L +#define RB_DEBUG_1__RDREQ_C0_EMPTY 0x00000200L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY 0x00000800L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY 0x00002000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK 0x00008000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY 0x00008000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK 0x00010000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY 0x00010000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK 0x00020000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY 0x00020000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK 0x00040000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY 0x00040000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK 0x00080000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY 0x00080000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY 0x00200000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY 0x00800000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY 0x01000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY 0x02000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK 0x04000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY 0x04000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK 0x08000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY 0x08000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK 0x10000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY 0x10000000L +#define RB_DEBUG_1__C_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_1__C_REQ_EMPTY 0x20000000L +#define RB_DEBUG_1__C_MASK_EMPTY_MASK 0x40000000L +#define RB_DEBUG_1__C_MASK_EMPTY 0x40000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK 0x80000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY 0x80000000L + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK 0x0000000fL +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK 0x000007f0L +#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK 0x00000800L +#define RB_DEBUG_2__MEM_EXPORT_FLAG 0x00000800L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK 0x00001000L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG 0x00001000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK 0x00002000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT 0x00002000L +#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK 0x00004000L +#define RB_DEBUG_2__EZ_INFTILE_FULL 0x00004000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK 0x00008000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL 0x00008000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK 0x00010000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL 0x00010000L +#define RB_DEBUG_2__Z0_MASK_FULL_MASK 0x00020000L +#define RB_DEBUG_2__Z0_MASK_FULL 0x00020000L +#define RB_DEBUG_2__Z1_MASK_FULL_MASK 0x00040000L +#define RB_DEBUG_2__Z1_MASK_FULL 0x00040000L +#define RB_DEBUG_2__Z0_REQ_FULL_MASK 0x00080000L +#define RB_DEBUG_2__Z0_REQ_FULL 0x00080000L +#define RB_DEBUG_2__Z1_REQ_FULL_MASK 0x00100000L +#define RB_DEBUG_2__Z1_REQ_FULL 0x00100000L +#define RB_DEBUG_2__Z_SAMP_FULL_MASK 0x00200000L +#define RB_DEBUG_2__Z_SAMP_FULL 0x00200000L +#define RB_DEBUG_2__Z_TILE_FULL_MASK 0x00400000L +#define RB_DEBUG_2__Z_TILE_FULL 0x00400000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK 0x00800000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY 0x00800000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK 0x01000000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY 0x01000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY 0x02000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK 0x04000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY 0x04000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK 0x08000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY 0x08000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK 0x10000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY 0x10000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY 0x20000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK 0x40000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY 0x40000000L +#define RB_DEBUG_2__Z_TILE_EMPTY_MASK 0x80000000L +#define RB_DEBUG_2__Z_TILE_EMPTY 0x80000000L + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID_MASK 0x0000000fL +#define RB_DEBUG_3__ACCUM_FLUSHING_MASK 0x000000f0L +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK 0x00004000L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID 0x00004000L +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK 0x00078000L +#define RB_DEBUG_3__SHD_FULL_MASK 0x00080000L +#define RB_DEBUG_3__SHD_FULL 0x00080000L +#define RB_DEBUG_3__SHD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_3__SHD_EMPTY 0x00100000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK 0x01000000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL 0x01000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY 0x02000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK 0x04000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY 0x04000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK 0x08000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL 0x08000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK 0x10000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL 0x10000000L + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK 0x00000001L +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG 0x00000001L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK 0x00000002L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG 0x00000002L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG 0x00000004L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG 0x00000008L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY 0x00000010L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY 0x00000020L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK 0x00000040L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL 0x00000040L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK 0x00000080L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL 0x00000080L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW 0x00000100L +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK 0x00001e00L + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK 0x00000001L +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR 0x00000001L + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK 0x00000600L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h new file mode 100644 index 000000000000..6a229a8e79e2 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h @@ -0,0 +1,581 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamato_OFFSET_HEADER +#define _yamato_OFFSET_HEADER + + +// Registers from PA block + +#define mmPA_CL_VPORT_XSCALE 0x210F +#define mmPA_CL_VPORT_XOFFSET 0x2110 +#define mmPA_CL_VPORT_YSCALE 0x2111 +#define mmPA_CL_VPORT_YOFFSET 0x2112 +#define mmPA_CL_VPORT_ZSCALE 0x2113 +#define mmPA_CL_VPORT_ZOFFSET 0x2114 +#define mmPA_CL_VTE_CNTL 0x2206 +#define mmPA_CL_CLIP_CNTL 0x2204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0x2303 +#define mmPA_CL_GB_VERT_DISC_ADJ 0x2304 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x2305 +#define mmPA_CL_GB_HORZ_DISC_ADJ 0x2306 +#define mmPA_CL_ENHANCE 0x0C85 +#define mmPA_SC_ENHANCE 0x0CA5 +#define mmPA_SU_VTX_CNTL 0x2302 +#define mmPA_SU_POINT_SIZE 0x2280 +#define mmPA_SU_POINT_MINMAX 0x2281 +#define mmPA_SU_LINE_CNTL 0x2282 +#define mmPA_SU_SC_MODE_CNTL 0x2205 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 +#define mmPA_SU_PERFCOUNTER0_SELECT 0x0C88 +#define mmPA_SU_PERFCOUNTER1_SELECT 0x0C89 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x0C8A +#define mmPA_SU_PERFCOUNTER3_SELECT 0x0C8B +#define mmPA_SU_PERFCOUNTER0_LOW 0x0C8C +#define mmPA_SU_PERFCOUNTER0_HI 0x0C8D +#define mmPA_SU_PERFCOUNTER1_LOW 0x0C8E +#define mmPA_SU_PERFCOUNTER1_HI 0x0C8F +#define mmPA_SU_PERFCOUNTER2_LOW 0x0C90 +#define mmPA_SU_PERFCOUNTER2_HI 0x0C91 +#define mmPA_SU_PERFCOUNTER3_LOW 0x0C92 +#define mmPA_SU_PERFCOUNTER3_HI 0x0C93 +#define mmPA_SC_WINDOW_OFFSET 0x2080 +#define mmPA_SC_AA_CONFIG 0x2301 +#define mmPA_SC_AA_MASK 0x2312 +#define mmPA_SC_LINE_STIPPLE 0x2283 +#define mmPA_SC_LINE_CNTL 0x2300 +#define mmPA_SC_WINDOW_SCISSOR_TL 0x2081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0x2082 +#define mmPA_SC_SCREEN_SCISSOR_TL 0x200E +#define mmPA_SC_SCREEN_SCISSOR_BR 0x200F +#define mmPA_SC_VIZ_QUERY 0x2293 +#define mmPA_SC_VIZ_QUERY_STATUS 0x0C44 +#define mmPA_SC_LINE_STIPPLE_STATE 0x0C40 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x0C98 +#define mmPA_SC_PERFCOUNTER0_LOW 0x0C99 +#define mmPA_SC_PERFCOUNTER0_HI 0x0C9A +#define mmPA_CL_CNTL_STATUS 0x0C84 +#define mmPA_SU_CNTL_STATUS 0x0C94 +#define mmPA_SC_CNTL_STATUS 0x0CA4 +#define mmPA_SU_DEBUG_CNTL 0x0C80 +#define mmPA_SU_DEBUG_DATA 0x0C81 +#define mmPA_SC_DEBUG_CNTL 0x0C82 +#define mmPA_SC_DEBUG_DATA 0x0C83 + + +// Registers from VGT block + +#define mmGFX_COPY_STATE 0x21F4 +#define mmVGT_DRAW_INITIATOR 0x21FC +#define mmVGT_EVENT_INITIATOR 0x21F9 +#define mmVGT_DMA_BASE 0x21FA +#define mmVGT_DMA_SIZE 0x21FB +#define mmVGT_BIN_BASE 0x21FE +#define mmVGT_BIN_SIZE 0x21FF +#define mmVGT_CURRENT_BIN_ID_MIN 0x2207 +#define mmVGT_CURRENT_BIN_ID_MAX 0x2203 +#define mmVGT_IMMED_DATA 0x21FD +#define mmVGT_MAX_VTX_INDX 0x2100 +#define mmVGT_MIN_VTX_INDX 0x2101 +#define mmVGT_INDX_OFFSET 0x2102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 +#define mmVGT_OUT_DEALLOC_CNTL 0x2317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103 +#define mmVGT_ENHANCE 0x2294 +#define mmVGT_VTX_VECT_EJECT_REG 0x0C2C +#define mmVGT_LAST_COPY_STATE 0x0C30 +#define mmVGT_DEBUG_CNTL 0x0C38 +#define mmVGT_DEBUG_DATA 0x0C39 +#define mmVGT_CNTL_STATUS 0x0C3C +#define mmVGT_CRC_SQ_DATA 0x0C3A +#define mmVGT_CRC_SQ_CTRL 0x0C3B +#define mmVGT_PERFCOUNTER0_SELECT 0x0C48 +#define mmVGT_PERFCOUNTER1_SELECT 0x0C49 +#define mmVGT_PERFCOUNTER2_SELECT 0x0C4A +#define mmVGT_PERFCOUNTER3_SELECT 0x0C4B +#define mmVGT_PERFCOUNTER0_LOW 0x0C4C +#define mmVGT_PERFCOUNTER1_LOW 0x0C4E +#define mmVGT_PERFCOUNTER2_LOW 0x0C50 +#define mmVGT_PERFCOUNTER3_LOW 0x0C52 +#define mmVGT_PERFCOUNTER0_HI 0x0C4D +#define mmVGT_PERFCOUNTER1_HI 0x0C4F +#define mmVGT_PERFCOUNTER2_HI 0x0C51 +#define mmVGT_PERFCOUNTER3_HI 0x0C53 + + +// Registers from TP block + +#define mmTC_CNTL_STATUS 0x0E00 +#define mmTCR_CHICKEN 0x0E02 +#define mmTCF_CHICKEN 0x0E03 +#define mmTCM_CHICKEN 0x0E04 +#define mmTCR_PERFCOUNTER0_SELECT 0x0E05 +#define mmTCR_PERFCOUNTER1_SELECT 0x0E08 +#define mmTCR_PERFCOUNTER0_HI 0x0E06 +#define mmTCR_PERFCOUNTER1_HI 0x0E09 +#define mmTCR_PERFCOUNTER0_LOW 0x0E07 +#define mmTCR_PERFCOUNTER1_LOW 0x0E0A +#define mmTP_TC_CLKGATE_CNTL 0x0E17 +#define mmTPC_CNTL_STATUS 0x0E18 +#define mmTPC_DEBUG0 0x0E19 +#define mmTPC_DEBUG1 0x0E1A +#define mmTPC_CHICKEN 0x0E1B +#define mmTP0_CNTL_STATUS 0x0E1C +#define mmTP0_DEBUG 0x0E1D +#define mmTP0_CHICKEN 0x0E1E +#define mmTP0_PERFCOUNTER0_SELECT 0x0E1F +#define mmTP0_PERFCOUNTER0_HI 0x0E20 +#define mmTP0_PERFCOUNTER0_LOW 0x0E21 +#define mmTP0_PERFCOUNTER1_SELECT 0x0E22 +#define mmTP0_PERFCOUNTER1_HI 0x0E23 +#define mmTP0_PERFCOUNTER1_LOW 0x0E24 +#define mmTCM_PERFCOUNTER0_SELECT 0x0E54 +#define mmTCM_PERFCOUNTER1_SELECT 0x0E57 +#define mmTCM_PERFCOUNTER0_HI 0x0E55 +#define mmTCM_PERFCOUNTER1_HI 0x0E58 +#define mmTCM_PERFCOUNTER0_LOW 0x0E56 +#define mmTCM_PERFCOUNTER1_LOW 0x0E59 +#define mmTCF_PERFCOUNTER0_SELECT 0x0E5A +#define mmTCF_PERFCOUNTER1_SELECT 0x0E5D +#define mmTCF_PERFCOUNTER2_SELECT 0x0E60 +#define mmTCF_PERFCOUNTER3_SELECT 0x0E63 +#define mmTCF_PERFCOUNTER4_SELECT 0x0E66 +#define mmTCF_PERFCOUNTER5_SELECT 0x0E69 +#define mmTCF_PERFCOUNTER6_SELECT 0x0E6C +#define mmTCF_PERFCOUNTER7_SELECT 0x0E6F +#define mmTCF_PERFCOUNTER8_SELECT 0x0E72 +#define mmTCF_PERFCOUNTER9_SELECT 0x0E75 +#define mmTCF_PERFCOUNTER10_SELECT 0x0E78 +#define mmTCF_PERFCOUNTER11_SELECT 0x0E7B +#define mmTCF_PERFCOUNTER0_HI 0x0E5B +#define mmTCF_PERFCOUNTER1_HI 0x0E5E +#define mmTCF_PERFCOUNTER2_HI 0x0E61 +#define mmTCF_PERFCOUNTER3_HI 0x0E64 +#define mmTCF_PERFCOUNTER4_HI 0x0E67 +#define mmTCF_PERFCOUNTER5_HI 0x0E6A +#define mmTCF_PERFCOUNTER6_HI 0x0E6D +#define mmTCF_PERFCOUNTER7_HI 0x0E70 +#define mmTCF_PERFCOUNTER8_HI 0x0E73 +#define mmTCF_PERFCOUNTER9_HI 0x0E76 +#define mmTCF_PERFCOUNTER10_HI 0x0E79 +#define mmTCF_PERFCOUNTER11_HI 0x0E7C +#define mmTCF_PERFCOUNTER0_LOW 0x0E5C +#define mmTCF_PERFCOUNTER1_LOW 0x0E5F +#define mmTCF_PERFCOUNTER2_LOW 0x0E62 +#define mmTCF_PERFCOUNTER3_LOW 0x0E65 +#define mmTCF_PERFCOUNTER4_LOW 0x0E68 +#define mmTCF_PERFCOUNTER5_LOW 0x0E6B +#define mmTCF_PERFCOUNTER6_LOW 0x0E6E +#define mmTCF_PERFCOUNTER7_LOW 0x0E71 +#define mmTCF_PERFCOUNTER8_LOW 0x0E74 +#define mmTCF_PERFCOUNTER9_LOW 0x0E77 +#define mmTCF_PERFCOUNTER10_LOW 0x0E7A +#define mmTCF_PERFCOUNTER11_LOW 0x0E7D +#define mmTCF_DEBUG 0x0EC0 +#define mmTCA_FIFO_DEBUG 0x0EC1 +#define mmTCA_PROBE_DEBUG 0x0EC2 +#define mmTCA_TPC_DEBUG 0x0EC3 +#define mmTCB_CORE_DEBUG 0x0EC4 +#define mmTCB_TAG0_DEBUG 0x0EC5 +#define mmTCB_TAG1_DEBUG 0x0EC6 +#define mmTCB_TAG2_DEBUG 0x0EC7 +#define mmTCB_TAG3_DEBUG 0x0EC8 +#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9 +#define mmTCB_FETCH_GEN_WALKER_DEBUG 0x0ECB +#define mmTCB_FETCH_GEN_PIPE0_DEBUG 0x0ECC +#define mmTCD_INPUT0_DEBUG 0x0ED0 +#define mmTCD_DEGAMMA_DEBUG 0x0ED4 +#define mmTCD_DXTMUX_SCTARB_DEBUG 0x0ED5 +#define mmTCD_DXTC_ARB_DEBUG 0x0ED6 +#define mmTCD_STALLS_DEBUG 0x0ED7 +#define mmTCO_STALLS_DEBUG 0x0EE0 +#define mmTCO_QUAD0_DEBUG0 0x0EE1 +#define mmTCO_QUAD0_DEBUG1 0x0EE2 + + +// Registers from TC block + + + +// Registers from SQ block + +#define mmSQ_GPR_MANAGEMENT 0x0D00 +#define mmSQ_FLOW_CONTROL 0x0D01 +#define mmSQ_INST_STORE_MANAGMENT 0x0D02 +#define mmSQ_RESOURCE_MANAGMENT 0x0D03 +#define mmSQ_EO_RT 0x0D04 +#define mmSQ_DEBUG_MISC 0x0D05 +#define mmSQ_ACTIVITY_METER_CNTL 0x0D06 +#define mmSQ_ACTIVITY_METER_STATUS 0x0D07 +#define mmSQ_INPUT_ARB_PRIORITY 0x0D08 +#define mmSQ_THREAD_ARB_PRIORITY 0x0D09 +#define mmSQ_DEBUG_INPUT_FSM 0x0DAE +#define mmSQ_DEBUG_CONST_MGR_FSM 0x0DAF +#define mmSQ_DEBUG_TP_FSM 0x0DB0 +#define mmSQ_DEBUG_FSM_ALU_0 0x0DB1 +#define mmSQ_DEBUG_FSM_ALU_1 0x0DB2 +#define mmSQ_DEBUG_EXP_ALLOC 0x0DB3 +#define mmSQ_DEBUG_PTR_BUFF 0x0DB4 +#define mmSQ_DEBUG_GPR_VTX 0x0DB5 +#define mmSQ_DEBUG_GPR_PIX 0x0DB6 +#define mmSQ_DEBUG_TB_STATUS_SEL 0x0DB7 +#define mmSQ_DEBUG_VTX_TB_0 0x0DB8 +#define mmSQ_DEBUG_VTX_TB_1 0x0DB9 +#define mmSQ_DEBUG_VTX_TB_STATUS_REG 0x0DBA +#define mmSQ_DEBUG_VTX_TB_STATE_MEM 0x0DBB +#define mmSQ_DEBUG_PIX_TB_0 0x0DBC +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0 +#define mmSQ_DEBUG_PIX_TB_STATE_MEM 0x0DC1 +#define mmSQ_PERFCOUNTER0_SELECT 0x0DC8 +#define mmSQ_PERFCOUNTER1_SELECT 0x0DC9 +#define mmSQ_PERFCOUNTER2_SELECT 0x0DCA +#define mmSQ_PERFCOUNTER3_SELECT 0x0DCB +#define mmSQ_PERFCOUNTER0_LOW 0x0DCC +#define mmSQ_PERFCOUNTER0_HI 0x0DCD +#define mmSQ_PERFCOUNTER1_LOW 0x0DCE +#define mmSQ_PERFCOUNTER1_HI 0x0DCF +#define mmSQ_PERFCOUNTER2_LOW 0x0DD0 +#define mmSQ_PERFCOUNTER2_HI 0x0DD1 +#define mmSQ_PERFCOUNTER3_LOW 0x0DD2 +#define mmSQ_PERFCOUNTER3_HI 0x0DD3 +#define mmSX_PERFCOUNTER0_SELECT 0x0DD4 +#define mmSX_PERFCOUNTER0_LOW 0x0DD8 +#define mmSX_PERFCOUNTER0_HI 0x0DD9 +#define mmSQ_INSTRUCTION_ALU_0 0x5000 +#define mmSQ_INSTRUCTION_ALU_1 0x5001 +#define mmSQ_INSTRUCTION_ALU_2 0x5002 +#define mmSQ_INSTRUCTION_CF_EXEC_0 0x5080 +#define mmSQ_INSTRUCTION_CF_EXEC_1 0x5081 +#define mmSQ_INSTRUCTION_CF_EXEC_2 0x5082 +#define mmSQ_INSTRUCTION_CF_LOOP_0 0x5083 +#define mmSQ_INSTRUCTION_CF_LOOP_1 0x5084 +#define mmSQ_INSTRUCTION_CF_LOOP_2 0x5085 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088 +#define mmSQ_INSTRUCTION_CF_ALLOC_0 0x5089 +#define mmSQ_INSTRUCTION_CF_ALLOC_1 0x508A +#define mmSQ_INSTRUCTION_CF_ALLOC_2 0x508B +#define mmSQ_INSTRUCTION_TFETCH_0 0x5043 +#define mmSQ_INSTRUCTION_TFETCH_1 0x5044 +#define mmSQ_INSTRUCTION_TFETCH_2 0x5045 +#define mmSQ_INSTRUCTION_VFETCH_0 0x5040 +#define mmSQ_INSTRUCTION_VFETCH_1 0x5041 +#define mmSQ_INSTRUCTION_VFETCH_2 0x5042 +#define mmSQ_CONSTANT_0 0x4000 +#define mmSQ_CONSTANT_1 0x4001 +#define mmSQ_CONSTANT_2 0x4002 +#define mmSQ_CONSTANT_3 0x4003 +#define mmSQ_FETCH_0 0x4800 +#define mmSQ_FETCH_1 0x4801 +#define mmSQ_FETCH_2 0x4802 +#define mmSQ_FETCH_3 0x4803 +#define mmSQ_FETCH_4 0x4804 +#define mmSQ_FETCH_5 0x4805 +#define mmSQ_CONSTANT_VFETCH_0 0x4806 +#define mmSQ_CONSTANT_VFETCH_1 0x4808 +#define mmSQ_CONSTANT_T2 0x480C +#define mmSQ_CONSTANT_T3 0x4812 +#define mmSQ_CF_BOOLEANS 0x4900 +#define mmSQ_CF_LOOP 0x4908 +#define mmSQ_CONSTANT_RT_0 0x4940 +#define mmSQ_CONSTANT_RT_1 0x4941 +#define mmSQ_CONSTANT_RT_2 0x4942 +#define mmSQ_CONSTANT_RT_3 0x4943 +#define mmSQ_FETCH_RT_0 0x4D40 +#define mmSQ_FETCH_RT_1 0x4D41 +#define mmSQ_FETCH_RT_2 0x4D42 +#define mmSQ_FETCH_RT_3 0x4D43 +#define mmSQ_FETCH_RT_4 0x4D44 +#define mmSQ_FETCH_RT_5 0x4D45 +#define mmSQ_CF_RT_BOOLEANS 0x4E00 +#define mmSQ_CF_RT_LOOP 0x4E14 +#define mmSQ_VS_PROGRAM 0x21F7 +#define mmSQ_PS_PROGRAM 0x21F6 +#define mmSQ_CF_PROGRAM_SIZE 0x2315 +#define mmSQ_INTERPOLATOR_CNTL 0x2182 +#define mmSQ_PROGRAM_CNTL 0x2180 +#define mmSQ_WRAPPING_0 0x2183 +#define mmSQ_WRAPPING_1 0x2184 +#define mmSQ_VS_CONST 0x2307 +#define mmSQ_PS_CONST 0x2308 +#define mmSQ_CONTEXT_MISC 0x2181 +#define mmSQ_CF_RD_BASE 0x21F5 +#define mmSQ_DEBUG_MISC_0 0x2309 +#define mmSQ_DEBUG_MISC_1 0x230A + + +// Registers from SX block + + + +// Registers from MH block + +#define mmMH_ARBITER_CONFIG 0x0A40 +#define mmMH_CLNT_AXI_ID_REUSE 0x0A41 +#define mmMH_INTERRUPT_MASK 0x0A42 +#define mmMH_INTERRUPT_STATUS 0x0A43 +#define mmMH_INTERRUPT_CLEAR 0x0A44 +#define mmMH_AXI_ERROR 0x0A45 +#define mmMH_PERFCOUNTER0_SELECT 0x0A46 +#define mmMH_PERFCOUNTER1_SELECT 0x0A4A +#define mmMH_PERFCOUNTER0_CONFIG 0x0A47 +#define mmMH_PERFCOUNTER1_CONFIG 0x0A4B +#define mmMH_PERFCOUNTER0_LOW 0x0A48 +#define mmMH_PERFCOUNTER1_LOW 0x0A4C +#define mmMH_PERFCOUNTER0_HI 0x0A49 +#define mmMH_PERFCOUNTER1_HI 0x0A4D +#define mmMH_DEBUG_CTRL 0x0A4E +#define mmMH_DEBUG_DATA 0x0A4F +#define mmMH_MMU_CONFIG 0x0040 +#define mmMH_MMU_VA_RANGE 0x0041 +#define mmMH_MMU_PT_BASE 0x0042 +#define mmMH_MMU_PAGE_FAULT 0x0043 +#define mmMH_MMU_TRAN_ERROR 0x0044 +#define mmMH_MMU_INVALIDATE 0x0045 +#define mmMH_MMU_MPU_BASE 0x0046 +#define mmMH_MMU_MPU_END 0x0047 + + +// Registers from RBBM block + +#define mmWAIT_UNTIL 0x05C8 +#define mmRBBM_ISYNC_CNTL 0x05C9 +#define mmRBBM_STATUS 0x05D0 +#define mmRBBM_DSPLY 0x0391 +#define mmRBBM_RENDER_LATEST 0x0392 +#define mmRBBM_RTL_RELEASE 0x0000 +#define mmRBBM_PATCH_RELEASE 0x0001 +#define mmRBBM_AUXILIARY_CONFIG 0x0002 +#define mmRBBM_PERIPHID0 0x03F8 +#define mmRBBM_PERIPHID1 0x03F9 +#define mmRBBM_PERIPHID2 0x03FA +#define mmRBBM_PERIPHID3 0x03FB +#define mmRBBM_CNTL 0x003B +#define mmRBBM_SKEW_CNTL 0x003D +#define mmRBBM_SOFT_RESET 0x003C +#define mmRBBM_PM_OVERRIDE1 0x039C +#define mmRBBM_PM_OVERRIDE2 0x039D +#define mmGC_SYS_IDLE 0x039E +#define mmNQWAIT_UNTIL 0x0394 +#define mmRBBM_DEBUG 0x039B +#define mmRBBM_READ_ERROR 0x03B3 +#define mmRBBM_WAIT_IDLE_CLOCKS 0x03B2 +#define mmRBBM_INT_CNTL 0x03B4 +#define mmRBBM_INT_STATUS 0x03B5 +#define mmRBBM_INT_ACK 0x03B6 +#define mmMASTER_INT_SIGNAL 0x03B7 +#define mmRBBM_PERFCOUNTER1_SELECT 0x0395 +#define mmRBBM_PERFCOUNTER1_LO 0x0397 +#define mmRBBM_PERFCOUNTER1_HI 0x0398 + + +// Registers from CP block + +#define mmCP_RB_BASE 0x01C0 +#define mmCP_RB_CNTL 0x01C1 +#define mmCP_RB_RPTR_ADDR 0x01C3 +#define mmCP_RB_RPTR 0x01C4 +#define mmCP_RB_RPTR_WR 0x01C7 +#define mmCP_RB_WPTR 0x01C5 +#define mmCP_RB_WPTR_DELAY 0x01C6 +#define mmCP_RB_WPTR_BASE 0x01C8 +#define mmCP_IB1_BASE 0x01CC +#define mmCP_IB1_BUFSZ 0x01CD +#define mmCP_IB2_BASE 0x01CE +#define mmCP_IB2_BUFSZ 0x01CF +#define mmCP_ST_BASE 0x044D +#define mmCP_ST_BUFSZ 0x044E +#define mmCP_QUEUE_THRESHOLDS 0x01D5 +#define mmCP_MEQ_THRESHOLDS 0x01D6 +#define mmCP_CSQ_AVAIL 0x01D7 +#define mmCP_STQ_AVAIL 0x01D8 +#define mmCP_MEQ_AVAIL 0x01D9 +#define mmCP_CSQ_RB_STAT 0x01FD +#define mmCP_CSQ_IB1_STAT 0x01FE +#define mmCP_CSQ_IB2_STAT 0x01FF +#define mmCP_NON_PREFETCH_CNTRS 0x0440 +#define mmCP_STQ_ST_STAT 0x0443 +#define mmCP_MEQ_STAT 0x044F +#define mmCP_MIU_TAG_STAT 0x0452 +#define mmCP_CMD_INDEX 0x01DA +#define mmCP_CMD_DATA 0x01DB +#define mmCP_ME_CNTL 0x01F6 +#define mmCP_ME_STATUS 0x01F7 +#define mmCP_ME_RAM_WADDR 0x01F8 +#define mmCP_ME_RAM_RADDR 0x01F9 +#define mmCP_ME_RAM_DATA 0x01FA +#define mmCP_ME_RDADDR 0x01EA +#define mmCP_DEBUG 0x01FC +#define mmSCRATCH_REG0 0x0578 +#define mmGUI_SCRATCH_REG0 0x0578 +#define mmSCRATCH_REG1 0x0579 +#define mmGUI_SCRATCH_REG1 0x0579 +#define mmSCRATCH_REG2 0x057A +#define mmGUI_SCRATCH_REG2 0x057A +#define mmSCRATCH_REG3 0x057B +#define mmGUI_SCRATCH_REG3 0x057B +#define mmSCRATCH_REG4 0x057C +#define mmGUI_SCRATCH_REG4 0x057C +#define mmSCRATCH_REG5 0x057D +#define mmGUI_SCRATCH_REG5 0x057D +#define mmSCRATCH_REG6 0x057E +#define mmGUI_SCRATCH_REG6 0x057E +#define mmSCRATCH_REG7 0x057F +#define mmGUI_SCRATCH_REG7 0x057F +#define mmSCRATCH_UMSK 0x01DC +#define mmSCRATCH_ADDR 0x01DD +#define mmCP_ME_VS_EVENT_SRC 0x0600 +#define mmCP_ME_VS_EVENT_ADDR 0x0601 +#define mmCP_ME_VS_EVENT_DATA 0x0602 +#define mmCP_ME_VS_EVENT_ADDR_SWM 0x0603 +#define mmCP_ME_VS_EVENT_DATA_SWM 0x0604 +#define mmCP_ME_PS_EVENT_SRC 0x0605 +#define mmCP_ME_PS_EVENT_ADDR 0x0606 +#define mmCP_ME_PS_EVENT_DATA 0x0607 +#define mmCP_ME_PS_EVENT_ADDR_SWM 0x0608 +#define mmCP_ME_PS_EVENT_DATA_SWM 0x0609 +#define mmCP_ME_CF_EVENT_SRC 0x060A +#define mmCP_ME_CF_EVENT_ADDR 0x060B +#define mmCP_ME_CF_EVENT_DATA 0x060C +#define mmCP_ME_NRT_ADDR 0x060D +#define mmCP_ME_NRT_DATA 0x060E +#define mmCP_ME_VS_FETCH_DONE_SRC 0x0612 +#define mmCP_ME_VS_FETCH_DONE_ADDR 0x0613 +#define mmCP_ME_VS_FETCH_DONE_DATA 0x0614 +#define mmCP_INT_CNTL 0x01F2 +#define mmCP_INT_STATUS 0x01F3 +#define mmCP_INT_ACK 0x01F4 +#define mmCP_PFP_UCODE_ADDR 0x045F +#define mmCP_PFP_UCODE_DATA 0x0460 +#define mmCP_PERFMON_CNTL 0x01F5 +#define mmCP_PERFCOUNTER_SELECT 0x01E6 +#define mmCP_PERFCOUNTER_LO 0x01E7 +#define mmCP_PERFCOUNTER_HI 0x01E8 +#define mmCP_BIN_MASK_LO 0x0454 +#define mmCP_BIN_MASK_HI 0x0455 +#define mmCP_BIN_SELECT_LO 0x0456 +#define mmCP_BIN_SELECT_HI 0x0457 +#define mmCP_NV_FLAGS_0 0x01EE +#define mmCP_NV_FLAGS_1 0x01EF +#define mmCP_NV_FLAGS_2 0x01F0 +#define mmCP_NV_FLAGS_3 0x01F1 +#define mmCP_STATE_DEBUG_INDEX 0x01EC +#define mmCP_STATE_DEBUG_DATA 0x01ED +#define mmCP_PROG_COUNTER 0x044B +#define mmCP_STAT 0x047F +#define mmBIOS_0_SCRATCH 0x0004 +#define mmBIOS_1_SCRATCH 0x0005 +#define mmBIOS_2_SCRATCH 0x0006 +#define mmBIOS_3_SCRATCH 0x0007 +#define mmBIOS_4_SCRATCH 0x0008 +#define mmBIOS_5_SCRATCH 0x0009 +#define mmBIOS_6_SCRATCH 0x000A +#define mmBIOS_7_SCRATCH 0x000B +#define mmBIOS_8_SCRATCH 0x0580 +#define mmBIOS_9_SCRATCH 0x0581 +#define mmBIOS_10_SCRATCH 0x0582 +#define mmBIOS_11_SCRATCH 0x0583 +#define mmBIOS_12_SCRATCH 0x0584 +#define mmBIOS_13_SCRATCH 0x0585 +#define mmBIOS_14_SCRATCH 0x0586 +#define mmBIOS_15_SCRATCH 0x0587 +#define mmCOHER_SIZE_PM4 0x0A29 +#define mmCOHER_BASE_PM4 0x0A2A +#define mmCOHER_STATUS_PM4 0x0A2B +#define mmCOHER_SIZE_HOST 0x0A2F +#define mmCOHER_BASE_HOST 0x0A30 +#define mmCOHER_STATUS_HOST 0x0A31 +#define mmCOHER_DEST_BASE_0 0x2006 +#define mmCOHER_DEST_BASE_1 0x2007 +#define mmCOHER_DEST_BASE_2 0x2008 +#define mmCOHER_DEST_BASE_3 0x2009 +#define mmCOHER_DEST_BASE_4 0x200A +#define mmCOHER_DEST_BASE_5 0x200B +#define mmCOHER_DEST_BASE_6 0x200C +#define mmCOHER_DEST_BASE_7 0x200D + + +// Registers from SC block + + + +// Registers from BC block + +#define mmRB_SURFACE_INFO 0x2000 +#define mmRB_COLOR_INFO 0x2001 +#define mmRB_DEPTH_INFO 0x2002 +#define mmRB_STENCILREFMASK 0x210D +#define mmRB_ALPHA_REF 0x210E +#define mmRB_COLOR_MASK 0x2104 +#define mmRB_BLEND_RED 0x2105 +#define mmRB_BLEND_GREEN 0x2106 +#define mmRB_BLEND_BLUE 0x2107 +#define mmRB_BLEND_ALPHA 0x2108 +#define mmRB_FOG_COLOR 0x2109 +#define mmRB_STENCILREFMASK_BF 0x210C +#define mmRB_DEPTHCONTROL 0x2200 +#define mmRB_BLENDCONTROL 0x2201 +#define mmRB_COLORCONTROL 0x2202 +#define mmRB_MODECONTROL 0x2208 +#define mmRB_COLOR_DEST_MASK 0x2326 +#define mmRB_COPY_CONTROL 0x2318 +#define mmRB_COPY_DEST_BASE 0x2319 +#define mmRB_COPY_DEST_PITCH 0x231A +#define mmRB_COPY_DEST_INFO 0x231B +#define mmRB_COPY_DEST_PIXEL_OFFSET 0x231C +#define mmRB_DEPTH_CLEAR 0x231D +#define mmRB_SAMPLE_COUNT_CTL 0x2324 +#define mmRB_SAMPLE_COUNT_ADDR 0x2325 +#define mmRB_BC_CONTROL 0x0F01 +#define mmRB_EDRAM_INFO 0x0F02 +#define mmRB_CRC_RD_PORT 0x0F0C +#define mmRB_CRC_CONTROL 0x0F0D +#define mmRB_CRC_MASK 0x0F0E +#define mmRB_PERFCOUNTER0_SELECT 0x0F04 +#define mmRB_PERFCOUNTER0_LOW 0x0F08 +#define mmRB_PERFCOUNTER0_HI 0x0F09 +#define mmRB_TOTAL_SAMPLES 0x0F0F +#define mmRB_ZPASS_SAMPLES 0x0F10 +#define mmRB_ZFAIL_SAMPLES 0x0F11 +#define mmRB_SFAIL_SAMPLES 0x0F12 +#define mmRB_DEBUG_0 0x0F26 +#define mmRB_DEBUG_1 0x0F27 +#define mmRB_DEBUG_2 0x0F28 +#define mmRB_DEBUG_3 0x0F29 +#define mmRB_DEBUG_4 0x0F2A +#define mmRB_FLAG_CONTROL 0x0F2B +#define mmBC_DUMMY_CRAYRB_ENUMS 0x0F15 +#define mmBC_DUMMY_CRAYRB_MOREENUMS 0x0F16 +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h new file mode 100644 index 000000000000..7e293b371bcd --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h @@ -0,0 +1,221 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_RANDOM_HEADER) +#define _yamato_RANDOM_HEADER + +/************************************************************* + * THIS FILE IS AUTOMATICALLY CREATED. DO NOT EDIT THIS FILE. + *************************************************************/ +/******************************************************* + * PA Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * VGT Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * RBBM Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * CP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +#endif /*_yamato_RANDOM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h new file mode 100644 index 000000000000..b021d446a229 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h @@ -0,0 +1,13962 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_REG_HEADER) +#define _yamato_REG_HEADER + + union PA_CL_VPORT_XSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_XOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VTE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_X_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int : 2; + unsigned int VTX_XY_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int PERFCOUNTER_REF : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_XY_FMT : 1; + unsigned int : 2; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_X_SCALE_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CLIP_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int CLIP_DISABLE : 1; + unsigned int : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int W_NAN_RETAIN : 1; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int W_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int : 1; + unsigned int CLIP_DISABLE : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int CLIP_VTX_REORDER_ENA : 1; + unsigned int : 27; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 27; + unsigned int CLIP_VTX_REORDER_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int : 28; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_VTX_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PIX_CENTER : 1; + unsigned int ROUND_MODE : 2; + unsigned int QUANT_MODE : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int QUANT_MODE : 3; + unsigned int ROUND_MODE : 2; + unsigned int PIX_CENTER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int HEIGHT : 16; + unsigned int WIDTH : 16; +#else /* !defined(qLittleEndian) */ + unsigned int WIDTH : 16; + unsigned int HEIGHT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_MINMAX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_SIZE : 16; + unsigned int MAX_SIZE : 16; +#else /* !defined(qLittleEndian) */ + unsigned int MAX_SIZE : 16; + unsigned int MIN_SIZE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int WIDTH : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int WIDTH : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_SC_MODE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int CULL_FRONT : 1; + unsigned int CULL_BACK : 1; + unsigned int FACE : 1; + unsigned int POLY_MODE : 2; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLY_MODE : 2; + unsigned int FACE : 1; + unsigned int CULL_BACK : 1; + unsigned int CULL_FRONT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int WINDOW_X_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_X_OFFSET : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MSAA_NUM_SAMPLES : 3; + unsigned int : 10; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 10; + unsigned int MSAA_NUM_SAMPLES : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AA_MASK : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int AA_MASK : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE { + struct { +#if defined(qLittleEndian) + unsigned int LINE_PATTERN : 16; + unsigned int REPEAT_COUNT : 8; + unsigned int : 4; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int : 4; + unsigned int REPEAT_COUNT : 8; + unsigned int LINE_PATTERN : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int BRES_CNTL : 8; + unsigned int USE_BRES_CNTL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int LAST_PIXEL : 1; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int LAST_PIXEL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int USE_BRES_CNTL : 1; + unsigned int BRES_CNTL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 14; + unsigned int : 2; + unsigned int TL_Y : 14; + unsigned int : 1; + unsigned int WINDOW_OFFSET_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int WINDOW_OFFSET_DISABLE : 1; + unsigned int : 1; + unsigned int TL_Y : 14; + unsigned int : 2; + unsigned int TL_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 14; + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; + unsigned int BR_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 15; + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; + unsigned int TL_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 15; + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; + unsigned int BR_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY { + struct { +#if defined(qLittleEndian) + unsigned int VIZ_QUERY_ENA : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int : 1; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int VIZ_QUERY_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int STATUS_BITS : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS_BITS : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE_STATE { + struct { +#if defined(qLittleEndian) + unsigned int CURRENT_PTR : 4; + unsigned int : 4; + unsigned int CURRENT_COUNT : 8; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int CURRENT_COUNT : 8; + unsigned int : 4; + unsigned int CURRENT_PTR : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int CL_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CL_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SU_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SU_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SC_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SU_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SU_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int clip_ga_bc_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ALWAYS_ZERO : 12; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 12; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_ga_bc_fifo_write : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int clip_to_outsm_end_of_packet : 1; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_vert_vte_valid : 3; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int ALWAYS_ZERO : 8; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 8; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int clip_vert_vte_valid : 3; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_end_of_packet : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO1 : 21; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; +#else /* !defined(qLittleEndian) */ + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO1 : 21; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO0 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 6; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO3 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO0 : 24; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 24; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO2 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 4; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int clprim_in_back_event : 1; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int prim_back_valid : 1; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_fifo_full : 1; + unsigned int clip_priority_seq_indx_load : 2; +#else /* !defined(qLittleEndian) */ + unsigned int clip_priority_seq_indx_load : 2; + unsigned int outsm_clr_fifo_full : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int prim_back_valid : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_event : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_event_id : 6; +#else /* !defined(qLittleEndian) */ + unsigned int clprim_in_back_event_id : 6; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int vertval_bits_vertex_vertex_store_msb : 4; + unsigned int ALWAYS_ZERO : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 28; + unsigned int vertval_bits_vertex_vertex_store_msb : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int clip_priority_available_vte_out_clip : 2; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int primic_to_clprim_valid : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int primic_to_clprim_valid : 1; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_priority_available_vte_out_clip : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int sm0_clip_vert_cnt : 4; + unsigned int sm0_prim_end_state : 7; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_current_state : 7; + unsigned int ALWAYS_ZERO0 : 5; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 5; + unsigned int sm0_current_state : 7; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_prim_end_state : 7; + unsigned int sm0_clip_vert_cnt : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int nan_kill_flag : 4; + unsigned int position_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_aux_sel : 1; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_rd_aux_sel : 1; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int position_address : 3; + unsigned int nan_kill_flag : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 2; + unsigned int sx_to_pa_empty : 2; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int sx_pending_advance : 1; + unsigned int sx_receive_indx : 3; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int pasx_req_cnt : 2; + unsigned int param_cache_base : 7; +#else /* !defined(qLittleEndian) */ + unsigned int param_cache_base : 7; + unsigned int pasx_req_cnt : 2; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int sx_receive_indx : 3; + unsigned int sx_pending_advance : 1; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int sx_to_pa_empty : 2; + unsigned int ALWAYS_ZERO3 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int sx_sent : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_aux : 1; + unsigned int sx_request_indx : 6; + unsigned int req_active_verts : 7; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int req_active_verts_loaded : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_contents : 3; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_fifo_contents : 3; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int req_active_verts_loaded : 1; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int req_active_verts : 7; + unsigned int sx_request_indx : 6; + unsigned int sx_aux : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_sent : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vertex_fifo_entriesavailable : 4; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int current_state : 2; + unsigned int vertex_fifo_empty : 1; + unsigned int vertex_fifo_full : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vertex_fifo_full : 1; + unsigned int vertex_fifo_empty : 1; + unsigned int current_state : 2; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int vertex_fifo_entriesavailable : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int su_cntl_state : 5; + unsigned int pmode_state : 6; + unsigned int ge_stallb : 1; + unsigned int geom_enable : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int su_clip_rtr : 1; + unsigned int pfifo_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int geom_busy : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int geom_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int pfifo_busy : 1; + unsigned int su_clip_rtr : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int geom_enable : 1; + unsigned int ge_stallb : 1; + unsigned int pmode_state : 6; + unsigned int su_cntl_state : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort0_gated_17_4 : 14; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int y_sort0_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort1_gated_17_4 : 14; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int y_sort1_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort2_gated_17_4 : 14; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int y_sort2_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort0_gated : 11; + unsigned int null_prim_gated : 1; + unsigned int backfacing_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int clipped_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int xmajor_gated : 1; + unsigned int diamond_rule_gated : 2; + unsigned int type_gated : 3; + unsigned int fpov_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int event_gated : 1; + unsigned int eop_gated : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int eop_gated : 1; + unsigned int event_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int fpov_gated : 1; + unsigned int type_gated : 3; + unsigned int diamond_rule_gated : 2; + unsigned int xmajor_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int clipped_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int backfacing_gated : 1; + unsigned int null_prim_gated : 1; + unsigned int attr_indx_sort0_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort2_gated : 11; + unsigned int attr_indx_sort1_gated : 11; + unsigned int provoking_vtx_gated : 2; + unsigned int event_id_gated : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int event_id_gated : 5; + unsigned int provoking_vtx_gated : 2; + unsigned int attr_indx_sort1_gated : 11; + unsigned int attr_indx_sort2_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SC_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SC_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int pa_freeze_b1 : 1; + unsigned int pa_sc_valid : 1; + unsigned int pa_sc_phase : 3; + unsigned int cntx_cnt : 7; + unsigned int decr_cntx_cnt : 1; + unsigned int incr_cntx_cnt : 1; + unsigned int : 17; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 17; + unsigned int incr_cntx_cnt : 1; + unsigned int decr_cntx_cnt : 1; + unsigned int cntx_cnt : 7; + unsigned int pa_sc_phase : 3; + unsigned int pa_sc_valid : 1; + unsigned int pa_freeze_b1 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int em_state : 3; + unsigned int em1_data_ready : 1; + unsigned int em2_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int ef_data_ready : 1; + unsigned int ef_state : 2; + unsigned int pipe_valid : 1; + unsigned int : 21; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 21; + unsigned int pipe_valid : 1; + unsigned int ef_state : 2; + unsigned int ef_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int em2_data_ready : 1; + unsigned int em1_data_ready : 1; + unsigned int em_state : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int rc_rtr_dly : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int : 1; + unsigned int pipe_freeze_b : 1; + unsigned int prim_rts : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int stage0_rts : 1; + unsigned int phase_rts_dly : 1; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : 1; + unsigned int pass_empty_prim_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int event_s1 : 1; + unsigned int : 8; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 8; + unsigned int event_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int pass_empty_prim_s1 : 1; + unsigned int end_of_prim_s1_dly : 1; + unsigned int : 5; + unsigned int phase_rts_dly : 1; + unsigned int stage0_rts : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int prim_rts : 1; + unsigned int pipe_freeze_b : 1; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int rc_rtr_dly : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int x_curr_s1 : 11; + unsigned int y_curr_s1 : 11; + unsigned int : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 9; + unsigned int y_curr_s1 : 11; + unsigned int x_curr_s1 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int y_end_s1 : 14; + unsigned int y_start_s1 : 14; + unsigned int y_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int y_dir_s1 : 1; + unsigned int y_start_s1 : 14; + unsigned int y_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_5 { + struct { +#if defined(qLittleEndian) + unsigned int x_end_s1 : 14; + unsigned int x_start_s1 : 14; + unsigned int x_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int x_dir_s1 : 1; + unsigned int x_start_s1 : 14; + unsigned int x_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_6 { + struct { +#if defined(qLittleEndian) + unsigned int z_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int xy_ff_empty : 1; + unsigned int event_flag : 1; + unsigned int z_mask_needed : 1; + unsigned int state : 3; + unsigned int state_delayed : 3; + unsigned int data_valid : 1; + unsigned int data_valid_d : 1; + unsigned int tilex_delayed : 9; + unsigned int tiley_delayed : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int tiley_delayed : 9; + unsigned int tilex_delayed : 9; + unsigned int data_valid_d : 1; + unsigned int data_valid : 1; + unsigned int state_delayed : 3; + unsigned int state : 3; + unsigned int z_mask_needed : 1; + unsigned int event_flag : 1; + unsigned int xy_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int z_ff_empty : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_7 { + struct { +#if defined(qLittleEndian) + unsigned int event_flag : 1; + unsigned int deallocate : 3; + unsigned int fpos : 1; + unsigned int sr_prim_we : 1; + unsigned int last_tile : 1; + unsigned int tile_ff_we : 1; + unsigned int qs_data_valid : 1; + unsigned int qs_q0_y : 2; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_valid : 1; + unsigned int prim_ff_we : 1; + unsigned int tile_ff_re : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int last_quad_of_tile : 1; + unsigned int first_quad_of_tile : 1; + unsigned int first_quad_of_prim : 1; + unsigned int new_prim : 1; + unsigned int load_new_tile_data : 1; + unsigned int state : 2; + unsigned int fifos_ready : 1; + unsigned int : 6; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 6; + unsigned int fifos_ready : 1; + unsigned int state : 2; + unsigned int load_new_tile_data : 1; + unsigned int new_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int first_quad_of_tile : 1; + unsigned int last_quad_of_tile : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int tile_ff_re : 1; + unsigned int prim_ff_we : 1; + unsigned int qs_q0_valid : 1; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_y : 2; + unsigned int qs_data_valid : 1; + unsigned int tile_ff_we : 1; + unsigned int last_tile : 1; + unsigned int sr_prim_we : 1; + unsigned int fpos : 1; + unsigned int deallocate : 3; + unsigned int event_flag : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_8 { + struct { +#if defined(qLittleEndian) + unsigned int sample_last : 1; + unsigned int sample_mask : 4; + unsigned int sample_y : 2; + unsigned int sample_x : 2; + unsigned int sample_send : 1; + unsigned int next_cycle : 2; + unsigned int ez_sample_ff_full : 1; + unsigned int rb_sc_samp_rtr : 1; + unsigned int num_samples : 2; + unsigned int last_quad_of_tile : 1; + unsigned int last_quad_of_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int sample_we : 1; + unsigned int fpos : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int : 3; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 3; + unsigned int fw_prim_data_valid : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int fpos : 1; + unsigned int sample_we : 1; + unsigned int first_quad_of_prim : 1; + unsigned int last_quad_of_prim : 1; + unsigned int last_quad_of_tile : 1; + unsigned int num_samples : 2; + unsigned int rb_sc_samp_rtr : 1; + unsigned int ez_sample_ff_full : 1; + unsigned int next_cycle : 2; + unsigned int sample_send : 1; + unsigned int sample_x : 2; + unsigned int sample_y : 2; + unsigned int sample_mask : 4; + unsigned int sample_last : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_9 { + struct { +#if defined(qLittleEndian) + unsigned int rb_sc_send : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int fifo_data_ready : 1; + unsigned int early_z_enable : 1; + unsigned int mask_state : 2; + unsigned int next_ez_mask : 16; + unsigned int mask_ready : 1; + unsigned int drop_sample : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int drop_sample : 1; + unsigned int mask_ready : 1; + unsigned int next_ez_mask : 16; + unsigned int mask_state : 2; + unsigned int early_z_enable : 1; + unsigned int fifo_data_ready : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int rb_sc_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_10 { + struct { +#if defined(qLittleEndian) + unsigned int combined_sample_mask : 16; + unsigned int : 15; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 15; + unsigned int combined_sample_mask : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_11 { + struct { +#if defined(qLittleEndian) + unsigned int ez_sample_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int iterator_input_fz : 1; + unsigned int packer_send_quads : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_event : 1; + unsigned int next_state : 3; + unsigned int state : 3; + unsigned int stall : 1; + unsigned int : 16; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 16; + unsigned int stall : 1; + unsigned int state : 3; + unsigned int next_state : 3; + unsigned int packer_send_event : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_quads : 1; + unsigned int iterator_input_fz : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_sample_data_ready : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_12 { + struct { +#if defined(qLittleEndian) + unsigned int SQ_iterator_free_buff : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_qdhit0 : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int bc_output_xy_reg : 1; + unsigned int iter_phase_out : 2; + unsigned int iter_phase_reg : 2; + unsigned int iterator_SP_valid : 1; + unsigned int eopv_reg : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int iter_dx_end_of_prim : 1; + unsigned int : 7; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int eopv_reg : 1; + unsigned int iterator_SP_valid : 1; + unsigned int iter_phase_reg : 2; + unsigned int iter_phase_out : 2; + unsigned int bc_output_xy_reg : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int iter_qdhit0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int SQ_iterator_free_buff : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GFX_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DRAW_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_TYPE : 6; + unsigned int SOURCE_SELECT : 2; + unsigned int : 3; + unsigned int INDEX_SIZE : 1; + unsigned int NOT_EOP : 1; + unsigned int SMALL_INDEX : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int NUM_INDICES : 16; +#else /* !defined(qLittleEndian) */ + unsigned int NUM_INDICES : 16; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int SMALL_INDEX : 1; + unsigned int NOT_EOP : 1; + unsigned int INDEX_SIZE : 1; + unsigned int : 3; + unsigned int SOURCE_SELECT : 2; + unsigned int PRIM_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_EVENT_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int EVENT_TYPE : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int EVENT_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int SWAP_MODE : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SWAP_MODE : 2; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BIN_BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MIN { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MAX { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_IMMED_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MAX_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MAX_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MAX_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MIN_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MIN_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_INDX_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int INDX_OFFSET : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int INDX_OFFSET : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VERTEX_REUSE_BLOCK_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_REUSE_DEPTH : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int VTX_REUSE_DEPTH : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_OUT_DEALLOC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int DEALLOC_DIST : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DEALLOC_DIST : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MULTI_PRIM_IB_RESET_INDX { + struct { +#if defined(qLittleEndian) + unsigned int RESET_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int RESET_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int MISC : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MISC : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VTX_VECT_EJECT_REG { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_COUNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int PRIM_COUNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_LAST_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VGT_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int VGT_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int VGT_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int te_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int out_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int grp_busy : 1; + unsigned int dma_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int rbiu_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int VGT_RBBM_busy : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int VGT_RBBM_busy : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int vgt_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int rbiu_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int dma_busy : 1; + unsigned int grp_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int out_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int te_grp_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int out_te_data_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int te_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_SQ_send : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int VGT_SQ_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int te_grp_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_te_data_read : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vgt_clk_en : 1; + unsigned int reg_fifos_clk_en : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int reg_fifos_clk_en : 1; + unsigned int vgt_clk_en : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int grp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int grp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG8 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG9 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int grp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int grp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int temp_derived_di_prim_type_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int di_state_sel_q : 1; + unsigned int last_decr_of_packet : 1; + unsigned int bin_valid : 1; + unsigned int read_block : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int last_bit_enable_q : 1; + unsigned int last_bit_end_di_q : 1; + unsigned int selected_data : 8; + unsigned int mask_input_data : 8; + unsigned int gap_q : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int grp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int grp_trigger : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int gap_q : 1; + unsigned int mask_input_data : 8; + unsigned int selected_data : 8; + unsigned int last_bit_end_di_q : 1; + unsigned int last_bit_enable_q : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int read_block : 1; + unsigned int bin_valid : 1; + unsigned int last_decr_of_packet : 1; + unsigned int di_state_sel_q : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_prim_type_t0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int bgrp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int bgrp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int bgrp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int bgrp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int bgrp_cull_fetch_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int rst_last_bit : 1; + unsigned int current_state_q : 1; + unsigned int old_state_q : 1; + unsigned int old_state_en : 1; + unsigned int prev_last_bit_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int load_empty_reg : 1; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int load_empty_reg : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int prev_last_bit_q : 1; + unsigned int old_state_en : 1; + unsigned int old_state_q : 1; + unsigned int current_state_q : 1; + unsigned int rst_last_bit : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int bgrp_cull_fetch_fifo_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int save_read_q : 1; + unsigned int extend_read_q : 1; + unsigned int grp_indx_size : 2; + unsigned int cull_prim_true : 1; + unsigned int reset_bit2_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int first_reg_first_q : 1; + unsigned int check_second_reg : 1; + unsigned int check_first_reg : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int roll_over_msk_q : 1; + unsigned int max_msk_ptr_q : 7; + unsigned int min_msk_ptr_q : 7; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int min_msk_ptr_q : 7; + unsigned int max_msk_ptr_q : 7; + unsigned int roll_over_msk_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int check_first_reg : 1; + unsigned int check_second_reg : 1; + unsigned int first_reg_first_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int reset_bit2_q : 1; + unsigned int cull_prim_true : 1; + unsigned int grp_indx_size : 2; + unsigned int extend_read_q : 1; + unsigned int save_read_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int dma_data_fifo_mem_raddr : 6; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_mem_full : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int bin_mem_full : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_mem_empty : 1; + unsigned int start_bin_req : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int dma_req_xfer : 1; + unsigned int have_valid_bin_req : 1; + unsigned int have_valid_dma_req : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int have_valid_dma_req : 1; + unsigned int have_valid_bin_req : 1; + unsigned int dma_req_xfer : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int start_bin_req : 1; + unsigned int bin_mem_empty : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_mem_full : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_mem_full : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_data_fifo_mem_raddr : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int prim_side_indx_valid : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int prim_buffer_empty : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_full : 1; + unsigned int indx_buffer_empty : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_full : 1; + unsigned int hold_prim : 1; + unsigned int sent_cnt : 4; + unsigned int start_of_vtx_vector : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int out_trigger : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int out_trigger : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int start_of_vtx_vector : 1; + unsigned int sent_cnt : 4; + unsigned int hold_prim : 1; + unsigned int indx_buffer_full : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_empty : 1; + unsigned int prim_buffer_full : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_empty : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int prim_side_indx_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int null_terminate_vtx_vector : 1; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int alloc_counter_q : 3; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_dealloc_distance_q : 4; + unsigned int new_packet_q : 1; + unsigned int new_allocate_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int inserted_null_prim_q : 1; + unsigned int insert_null_prim : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_thread_size : 1; + unsigned int : 4; + unsigned int out_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int out_trigger : 1; + unsigned int : 4; + unsigned int buffered_thread_size : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int insert_null_prim : 1; + unsigned int inserted_null_prim_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int new_allocate_q : 1; + unsigned int new_packet_q : 1; + unsigned int curr_dealloc_distance_q : 4; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int alloc_counter_q : 3; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int null_terminate_vtx_vector : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int L2_INVALIDATE : 1; + unsigned int : 17; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 11; + unsigned int TC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_BUSY : 1; + unsigned int : 11; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 17; + unsigned int L2_INVALIDATE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int SPARE : 23; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 23; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP_TC_CLKGATE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TP_BUSY_EXTEND : 3; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int TP_BUSY_EXTEND : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TPC_INPUT_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int : 1; + unsigned int TF_TW_RTR : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int : 1; + unsigned int TA_TB_RTR : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TPC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TPC_BUSY : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TB_RTR : 1; + unsigned int : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TF_TW_RTR : 1; + unsigned int : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int LOD_CNTL : 2; + unsigned int IC_CTR : 2; + unsigned int WALKER_CNTL : 4; + unsigned int ALIGNER_CNTL : 3; + unsigned int : 1; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 3; + unsigned int WALKER_STATE : 10; + unsigned int ALIGNER_STATE : 2; + unsigned int : 1; + unsigned int REG_CLK_EN : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int SQ_TP_WAKEUP : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SQ_TP_WAKEUP : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int : 1; + unsigned int ALIGNER_STATE : 2; + unsigned int WALKER_STATE : 10; + unsigned int : 3; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 1; + unsigned int ALIGNER_CNTL : 3; + unsigned int WALKER_CNTL : 4; + unsigned int IC_CTR : 2; + unsigned int LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int UNUSED : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int UNUSED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_PRECISION : 1; + unsigned int SPARE : 31; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 31; + unsigned int BLEND_PRECISION : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TP_INPUT_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int : 1; + unsigned int IN_LC_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TP_BUSY : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int IN_LC_RTS : 1; + unsigned int : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int Q_LOD_CNTL : 2; + unsigned int : 1; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int REG_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int TP_CLK_EN : 1; + unsigned int Q_WALKER_CNTL : 4; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int Q_WALKER_CNTL : 4; + unsigned int TP_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int : 1; + unsigned int Q_LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TT_MODE : 1; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int SPARE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 30; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int TT_MODE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 6; + unsigned int not_MH_TC_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_FG0_rtr : 1; + unsigned int : 3; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int TCB_ff_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int PF0_stall : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int TPC_full : 1; + unsigned int not_TPC_rtr : 1; + unsigned int tca_state_rts : 1; + unsigned int tca_rts : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int tca_rts : 1; + unsigned int tca_state_rts : 1; + unsigned int not_TPC_rtr : 1; + unsigned int TPC_full : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int PF0_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCB_ff_stall : 1; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int : 3; + unsigned int not_FG0_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_MH_TC_rtr : 1; + unsigned int : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_FIFO_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tp0_full : 1; + unsigned int : 3; + unsigned int tpc_full : 1; + unsigned int load_tpc_fifo : 1; + unsigned int load_tp_fifos : 1; + unsigned int FW_full : 1; + unsigned int not_FW_rtr0 : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_tpc_rtr : 1; + unsigned int FW_tpc_rts : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int FW_tpc_rts : 1; + unsigned int not_FW_tpc_rtr : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_rtr0 : 1; + unsigned int FW_full : 1; + unsigned int load_tp_fifos : 1; + unsigned int load_tpc_fifo : 1; + unsigned int tpc_full : 1; + unsigned int : 3; + unsigned int tp0_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_PROBE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int ProbeFilter_stall : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int ProbeFilter_stall : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_TPC_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int captue_state_rts : 1; + unsigned int capture_tca_rts : 1; + unsigned int : 18; +#else /* !defined(qLittleEndian) */ + unsigned int : 18; + unsigned int capture_tca_rts : 1; + unsigned int captue_state_rts : 1; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_CORE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int access512 : 1; + unsigned int tiled : 1; + unsigned int : 2; + unsigned int opcode : 3; + unsigned int : 1; + unsigned int format : 6; + unsigned int : 2; + unsigned int sector_format : 5; + unsigned int : 3; + unsigned int sector_format512 : 3; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int sector_format512 : 3; + unsigned int : 3; + unsigned int sector_format : 5; + unsigned int : 2; + unsigned int format : 6; + unsigned int : 1; + unsigned int opcode : 3; + unsigned int : 2; + unsigned int tiled : 1; + unsigned int access512 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG1_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG2_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG3_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int left_done : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int no_sectors_to_go : 1; + unsigned int update_left : 1; + unsigned int sector_mask_left_count_q : 5; + unsigned int sector_mask_left_q : 16; + unsigned int valid_left_q : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int valid_left_q : 1; + unsigned int sector_mask_left_q : 16; + unsigned int sector_mask_left_count_q : 5; + unsigned int update_left : 1; + unsigned int no_sectors_to_go : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int left_done : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_WALKER_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int quad_sel_left : 2; + unsigned int set_sel_left : 2; + unsigned int : 3; + unsigned int right_eq_left : 1; + unsigned int ff_fg_type512 : 3; + unsigned int busy : 1; + unsigned int setquads_to_send : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int setquads_to_send : 4; + unsigned int busy : 1; + unsigned int ff_fg_type512 : 3; + unsigned int right_eq_left : 1; + unsigned int : 3; + unsigned int set_sel_left : 2; + unsigned int quad_sel_left : 2; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_PIPE0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tc0_arb_rts : 1; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc_arb_format : 12; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_request_type : 2; + unsigned int busy : 1; + unsigned int fgo_busy : 1; + unsigned int ga_busy : 1; + unsigned int mc_sel_q : 2; + unsigned int valid_q : 1; + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; + unsigned int valid_q : 1; + unsigned int mc_sel_q : 2; + unsigned int ga_busy : 1; + unsigned int fgo_busy : 1; + unsigned int busy : 1; + unsigned int tc_arb_request_type : 2; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_format : 12; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc0_arb_rts : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_INPUT0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int : 2; + unsigned int valid_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int last_send_q1 : 1; + unsigned int ip_send : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ipbuf_busy : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int ipbuf_busy : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ip_send : 1; + unsigned int last_send_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int valid_q1 : 1; + unsigned int : 2; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DEGAMMA_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int dgmm_ftfconv_dgmmen : 2; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_pstate : 1; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int dgmm_pstate : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ftfconv_dgmmen : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTMUX_SCTARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 9; + unsigned int pstate : 1; + unsigned int sctrmx_rtr : 1; + unsigned int dxtc_rtr : 1; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : 1; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dcmp_mux_send : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int dcmp_mux_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int sctrarb_multcyl_send : 1; + unsigned int : 3; + unsigned int dxtc_rtr : 1; + unsigned int sctrmx_rtr : 1; + unsigned int pstate : 1; + unsigned int : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTC_ARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int n0_stall : 1; + unsigned int pstate : 1; + unsigned int arb_dcmp01_last_send : 1; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_send : 1; + unsigned int n0_dxt2_4_types : 1; +#else /* !defined(qLittleEndian) */ + unsigned int n0_dxt2_4_types : 1; + unsigned int arb_dcmp01_send : 1; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_last_send : 1; + unsigned int pstate : 1; + unsigned int n0_stall : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int : 11; + unsigned int not_incoming_rtr : 1; +#else /* !defined(qLittleEndian) */ + unsigned int not_incoming_rtr : 1; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int rl_sg_sector_format : 8; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int : 2; + unsigned int stageN1_valid_q : 1; + unsigned int : 7; + unsigned int read_cache_q : 1; + unsigned int cache_read_RTR : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int busy : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int busy : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int cache_read_RTR : 1; + unsigned int read_cache_q : 1; + unsigned int : 7; + unsigned int stageN1_valid_q : 1; + unsigned int : 2; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_sector_format : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int fifo_busy : 1; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int write_enable : 1; + unsigned int fifo_write_ptr : 7; + unsigned int fifo_read_ptr : 7; + unsigned int : 2; + unsigned int cache_read_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int cache_read_busy : 1; + unsigned int : 2; + unsigned int fifo_read_ptr : 7; + unsigned int fifo_write_ptr : 7; + unsigned int write_enable : 1; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int fifo_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_GPR_MANAGEMENT { + struct { +#if defined(qLittleEndian) + unsigned int REG_DYNAMIC : 1; + unsigned int : 3; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 1; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 1; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 3; + unsigned int REG_DYNAMIC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FLOW_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int INPUT_ARBITRATION_POLICY : 2; + unsigned int : 2; + unsigned int ONE_THREAD : 1; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int CF_WR_BASE : 4; + unsigned int NO_PV_PS : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_PV_PS : 1; + unsigned int CF_WR_BASE : 4; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int ONE_THREAD : 1; + unsigned int : 2; + unsigned int INPUT_ARBITRATION_POLICY : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INST_STORE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int INST_BASE_PIX : 12; + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; + unsigned int INST_BASE_PIX : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_RESOURCE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int VTX_THREAD_BUF_ENTRIES : 8; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int VTX_THREAD_BUF_ENTRIES : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_EO_RT { + struct { +#if defined(qLittleEndian) + unsigned int EO_CONSTANTS_RT : 8; + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; + unsigned int EO_CONSTANTS_RT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC { + struct { +#if defined(qLittleEndian) + unsigned int DB_ALUCST_SIZE : 11; + unsigned int : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int DB_READ_CTX : 1; + unsigned int RESERVED : 2; + unsigned int DB_READ_MEMORY : 2; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_READ_MEMORY : 2; + unsigned int RESERVED : 2; + unsigned int DB_READ_CTX : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int : 1; + unsigned int DB_ALUCST_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TIMEBASE : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int SPARE : 8; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int TIMEBASE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PERCENT_BUSY : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERCENT_BUSY : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INPUT_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_THREAD_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int RESERVED : 2; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int RESERVED : 2; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_INPUT_FSM { + struct { +#if defined(qLittleEndian) + unsigned int VC_VSR_LD : 3; + unsigned int RESERVED : 1; + unsigned int VC_GPR_LD : 4; + unsigned int PC_PISM : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_AS : 3; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_GPR_SIZE : 8; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PC_GPR_SIZE : 8; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_AS : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_PISM : 3; + unsigned int VC_GPR_LD : 4; + unsigned int RESERVED : 1; + unsigned int VC_VSR_LD : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_CONST_MGR_FSM { + struct { +#if defined(qLittleEndian) + unsigned int TEX_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int TEX_CONST_EVENT_STATE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TP_FSM { + struct { +#if defined(qLittleEndian) + unsigned int EX_TP : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_TP : 4; + unsigned int IF_TP : 3; + unsigned int RESERVED1 : 1; + unsigned int TIS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED5 : 2; + unsigned int ARB_TR_TP : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_TP : 3; + unsigned int RESERVED5 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int TIS_TP : 2; + unsigned int RESERVED1 : 1; + unsigned int IF_TP : 3; + unsigned int CF_TP : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_TP : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_EXP_ALLOC { + struct { +#if defined(qLittleEndian) + unsigned int POS_BUF_AVAIL : 4; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int EA_BUF_AVAIL : 3; + unsigned int RESERVED : 1; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int RESERVED : 1; + unsigned int EA_BUF_AVAIL : 3; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int POS_BUF_AVAIL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PTR_BUFF { + struct { +#if defined(qLittleEndian) + unsigned int END_OF_BUFFER : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int SC_EVENT_ID : 5; + unsigned int QUAL_EVENT : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int EF_EMPTY : 1; + unsigned int VTX_SYNC_CNT : 11; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int VTX_SYNC_CNT : 11; + unsigned int EF_EMPTY : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int QUAL_EVENT : 1; + unsigned int SC_EVENT_ID : 5; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int END_OF_BUFFER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_VTX { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int VTX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_PIX { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int PIX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TB_STATUS_SEL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TB_STATUS_REG_SEL : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int : 1; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int DISABLE_STRICT_CTX_SYNC : 1; +#else /* !defined(qLittleEndian) */ + unsigned int DISABLE_STRICT_CTX_SYNC : 1; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATUS_REG_SEL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int VTX_HEAD_PTR_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int SX_EVENT_FULL : 1; + unsigned int BUSY_Q : 1; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int BUSY_Q : 1; + unsigned int SX_EVENT_FULL : 1; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int VTX_HEAD_PTR_Q : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_1 { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_PTR : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int VS_DONE_PTR : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATUS_REG { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATUS_REG : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATUS_REG : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_HEAD_PTR : 6; + unsigned int TAIL_PTR : 6; + unsigned int FULL_CNT : 7; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BUSY : 1; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int FULL_CNT : 7; + unsigned int TAIL_PTR : 6; + unsigned int PIX_HEAD_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_1 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_2 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_3 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int VECTOR_RESULT : 6; + unsigned int CST_0_ABS_MOD : 1; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int SST_0_ABS_MOD : 1; + unsigned int EXPORT_DATA : 1; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_CLAMP : 1; + unsigned int SCALAR_OPCODE : 6; +#else /* !defined(qLittleEndian) */ + unsigned int SCALAR_OPCODE : 6; + unsigned int SCALAR_CLAMP : 1; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int EXPORT_DATA : 1; + unsigned int SST_0_ABS_MOD : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int CST_0_ABS_MOD : 1; + unsigned int VECTOR_RESULT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int PRED_SELECT : 2; + unsigned int RELATIVE_ADDR : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int CONST_0_REL_ABS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CONST_0_REL_ABS : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int RELATIVE_ADDR : 1; + unsigned int PRED_SELECT : 2; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_R : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_2 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_REG_PTR : 6; + unsigned int REG_SELECT_C : 1; + unsigned int REG_ABS_MOD_C : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_SELECT_B : 1; + unsigned int REG_ABS_MOD_B : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_SELECT_A : 1; + unsigned int REG_ABS_MOD_A : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int SRC_C_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_A_SEL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_A_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_C_SEL : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int REG_ABS_MOD_A : 1; + unsigned int REG_SELECT_A : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_ABS_MOD_B : 1; + unsigned int REG_SELECT_B : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_ABS_MOD_C : 1; + unsigned int REG_SELECT_C : 1; + unsigned int SRC_C_REG_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_1 { + struct { +#if defined(qLittleEndian) + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; +#else /* !defined(qLittleEndian) */ + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_2 { + struct { +#if defined(qLittleEndian) + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 6; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_1 : 11; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 11; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_0 : 6; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 11; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 6; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED_0 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_2 { + struct { +#if defined(qLittleEndian) + unsigned int LOOP_ID : 5; + unsigned int RESERVED : 22; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED : 22; + unsigned int LOOP_ID : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 3; + unsigned int FORCE_CALL : 1; + unsigned int PREDICATED_JMP : 1; + unsigned int RESERVED_1 : 17; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 17; + unsigned int PREDICATED_JMP : 1; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_0 : 3; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 1; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 3; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_2 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_2 : 2; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_1 : 3; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 17; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED : 17; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_0 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 4; + unsigned int RESERVED : 28; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 28; + unsigned int SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 8; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; + unsigned int SIZE : 4; + unsigned int RESERVED_1 : 12; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 12; + unsigned int SIZE : 4; + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 24; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int CONST_INDEX : 5; + unsigned int TX_COORD_DENORM : 1; + unsigned int SRC_SEL_X : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_Z : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL_Z : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_X : 2; + unsigned int TX_COORD_DENORM : 1; + unsigned int CONST_INDEX : 5; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int MAG_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MIP_FILTER : 2; + unsigned int ANISO_FILTER : 3; + unsigned int ARBITRARY_FILTER : 3; + unsigned int VOL_MAG_FILTER : 2; + unsigned int VOL_MIN_FILTER : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int USE_REG_LOD : 2; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int USE_REG_LOD : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int VOL_MIN_FILTER : 2; + unsigned int VOL_MAG_FILTER : 2; + unsigned int ARBITRARY_FILTER : 3; + unsigned int ANISO_FILTER : 3; + unsigned int MIP_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MAG_FILTER : 2; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int USE_REG_GRADIENTS : 1; + unsigned int SAMPLE_LOCATION : 1; + unsigned int LOD_BIAS : 7; + unsigned int UNUSED : 7; + unsigned int OFFSET_X : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_Z : 5; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int OFFSET_Z : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_X : 5; + unsigned int UNUSED : 7; + unsigned int LOD_BIAS : 7; + unsigned int SAMPLE_LOCATION : 1; + unsigned int USE_REG_GRADIENTS : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int MUST_BE_ONE : 1; + unsigned int CONST_INDEX : 5; + unsigned int CONST_INDEX_SEL : 2; + unsigned int : 3; + unsigned int SRC_SEL : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL : 2; + unsigned int : 3; + unsigned int CONST_INDEX_SEL : 2; + unsigned int CONST_INDEX : 5; + unsigned int MUST_BE_ONE : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int STRIDE : 8; + unsigned int : 8; + unsigned int OFFSET : 8; + unsigned int : 7; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int : 7; + unsigned int OFFSET : 8; + unsigned int : 8; + unsigned int STRIDE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int TYPE : 1; + unsigned int STATE : 1; + unsigned int BASE_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDRESS : 30; + unsigned int STATE : 1; + unsigned int TYPE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int ENDIAN_SWAP : 2; + unsigned int LIMIT_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int LIMIT_ADDRESS : 30; + unsigned int ENDIAN_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_PROGRAM_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int VS_CF_SIZE : 11; + unsigned int : 1; + unsigned int PS_CF_SIZE : 11; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int PS_CF_SIZE : 11; + unsigned int : 1; + unsigned int VS_CF_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INTERPOLATOR_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_SHADE : 16; + unsigned int SAMPLING_PATTERN : 16; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLING_PATTERN : 16; + unsigned int PARAM_SHADE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PROGRAM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VS_NUM_REG : 6; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_RESOURCE : 1; + unsigned int PS_RESOURCE : 1; + unsigned int PARAM_GEN : 1; + unsigned int GEN_INDEX_PIX : 1; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int PS_EXPORT_MODE : 4; + unsigned int GEN_INDEX_VTX : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GEN_INDEX_VTX : 1; + unsigned int PS_EXPORT_MODE : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int GEN_INDEX_PIX : 1; + unsigned int PARAM_GEN : 1; + unsigned int PS_RESOURCE : 1; + unsigned int VS_RESOURCE : 1; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_NUM_REG : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_0 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_0 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_7 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_7 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_0 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_1 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_8 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_15 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_15 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_8 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONTEXT_MISC { + struct { +#if defined(qLittleEndian) + unsigned int INST_PRED_OPTIMIZE : 1; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int : 4; + unsigned int PARAM_GEN_POS : 8; + unsigned int PERFCOUNTER_REF : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int TX_CACHE_SEL : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int TX_CACHE_SEL : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int PARAM_GEN_POS : 8; + unsigned int : 4; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int INST_PRED_OPTIMIZE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RD_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RD_BASE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int RD_BASE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_0 { + struct { +#if defined(qLittleEndian) + unsigned int DB_PROB_ON : 1; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 5; + unsigned int DB_PROB_COUNT : 8; +#else /* !defined(qLittleEndian) */ + unsigned int DB_PROB_COUNT : 8; + unsigned int : 5; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ON : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_1 { + struct { +#if defined(qLittleEndian) + unsigned int DB_ON_PIX : 1; + unsigned int DB_ON_VTX : 1; + unsigned int : 6; + unsigned int DB_INST_COUNT : 8; + unsigned int DB_BREAK_ADDR : 11; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int DB_BREAK_ADDR : 11; + unsigned int DB_INST_COUNT : 8; + unsigned int : 6; + unsigned int DB_ON_VTX : 1; + unsigned int DB_ON_PIX : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_ARBITER_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int SAME_PAGE_LIMIT : 6; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L2_ARB_CONTROL : 1; + unsigned int PAGE_SIZE : 3; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int PAGE_SIZE : 3; + unsigned int L2_ARB_CONTROL : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int SAME_PAGE_LIMIT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_CLNT_AXI_ID_REUSE { + struct { +#if defined(qLittleEndian) + unsigned int CPw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int MMUr_ID : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int MMUr_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int CPw_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_READ_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int INDEX : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int INDEX : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int MH_BUSY : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int CP_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int TC_REQUEST : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TCD_FULL : 1; + unsigned int RB_REQUEST : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int WDB_FULL : 1; + unsigned int AXI_AVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_AVALID : 1; + unsigned int WDB_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int RB_REQUEST : 1; + unsigned int TCD_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int CP_REQUEST : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int MH_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_WRITE_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_BE_q : 8; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_written : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_BE_q : 8; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BE_q : 8; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_BE_q : 8; + unsigned int CP_TAG_q : 3; + unsigned int CP_WRITE_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_CLNT_tag : 3; + unsigned int RDC_RID : 3; + unsigned int RDC_RRESP : 2; + unsigned int MH_CP_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int BRC_BID : 3; + unsigned int BRC_BRESP : 2; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BRC_BRESP : 2; + unsigned int BRC_BID : 3; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_CP_writeclean : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RID : 3; + unsigned int MH_CLNT_tag : 3; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_send : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_ad_31_5 : 27; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG06 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG07 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG08 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 3; + unsigned int VGT_MH_send : 1; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int VGT_MH_ad_31_5 : 27; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_send : 1; + unsigned int ALWAYS_ZERO : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_MH_addr_31_5 : 27; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_send : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_info : 25; + unsigned int TC_MH_send : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_info : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int MH_TC_mcinfo : 25; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int TC_MH_written : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int TC_MH_written : 1; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int MH_TC_mcinfo : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_ADDR_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_ADDR_31_5 : 27; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ROQ_INFO : 25; + unsigned int TC_ROQ_SEND : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_INFO : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int RB_MH_send : 1; + unsigned int RB_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_addr_31_5 : 27; + unsigned int RB_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_2_0 : 3; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_0 : 2; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int RID_q : 3; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int RID_q : 3; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int ARLEN_q_1_0 : 2; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_2_0 : 3; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_1_0 : 2; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_1 : 1; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int WSTRB_q : 8; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WSTRB_q : 8; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int ARLEN_q_1_1 : 1; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_1_0 : 2; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG19 { + struct { +#if defined(qLittleEndian) + unsigned int ARC_CTRL_RE_q : 1; + unsigned int CTRL_ARC_ID : 3; + unsigned int CTRL_ARC_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int CTRL_ARC_PAD : 28; + unsigned int CTRL_ARC_ID : 3; + unsigned int ARC_CTRL_RE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int REG_A : 14; + unsigned int REG_RE : 1; + unsigned int REG_WE : 1; + unsigned int BLOCK_RS : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BLOCK_RS : 1; + unsigned int REG_WE : 1; + unsigned int REG_RE : 1; + unsigned int REG_A : 14; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int REG_WD : 32; +#else /* !defined(qLittleEndian) */ + unsigned int REG_WD : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG22 { + struct { +#if defined(qLittleEndian) + unsigned int CIB_MH_axi_halt_req : 1; + unsigned int MH_CIB_axi_halt_ack : 1; + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int CNT_q : 6; + unsigned int TCD_EMPTY_q : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int BRC_VALID : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BRC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int RDC_VALID : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TCD_EMPTY_q : 1; + unsigned int CNT_q : 6; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_axi_halt_ack : 1; + unsigned int CIB_MH_axi_halt_req : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG23 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_FP_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int ARB_WINNER_q : 3; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int ARB_WINNER_q : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF2_FP_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG24 { + struct { +#if defined(qLittleEndian) + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; +#else /* !defined(qLittleEndian) */ + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG25 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int ARB_WINNER : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int LEAST_RECENT_d : 3; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int EFF1_WIN : 1; + unsigned int CLNT_REQ : 4; + unsigned int RECENT_d_0 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_3 : 3; +#else /* !defined(qLittleEndian) */ + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_0 : 3; + unsigned int CLNT_REQ : 4; + unsigned int EFF1_WIN : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int LEAST_RECENT_d : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG26 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ARB_HOLD : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int WBURST_ACTIVE : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_WINNER : 3; + unsigned int RB_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int WBURST_IP_q : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_ACTIVE : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ARB_HOLD : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG27 { + struct { +#if defined(qLittleEndian) + unsigned int RF_ARBITER_CONFIG_q : 26; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int RF_ARBITER_CONFIG_q : 26; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG28 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int ROQ_VALID_q : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG29 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int ROQ_VALID_d : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_d : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG30 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int NON_SAME_ROW_BANK_REQ : 8; +#else /* !defined(qLittleEndian) */ + unsigned int NON_SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int SAME_ROW_BANK_WIN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG31 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_ADDR_0 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_0 : 27; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG32 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_ADDR_1 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_1 : 27; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG33 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_ADDR_2 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_2 : 27; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG34 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_ADDR_3 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_3 : 27; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG35 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_ADDR_4 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_4 : 27; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG36 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_ADDR_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_5 : 27; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG37 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_ADDR_6 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_6 : 27; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG38 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_ADDR_7 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_7 : 27; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG39 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_WRITE : 1; + unsigned int MMU_BLEN : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int MMU_BLEN : 1; + unsigned int MMU_WRITE : 1; + unsigned int MMU_ID : 3; + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG40 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_VAD_q : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_VAD_q : 28; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG41 { + struct { +#if defined(qLittleEndian) + unsigned int MMU_WE : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_PAD : 28; + unsigned int MMU_ID : 3; + unsigned int MMU_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG42 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WE : 1; + unsigned int WDB_RTR_SKID : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int ARB_WLAST : 1; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WSTRB : 8; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int WDB_WDC_WSTRB : 8; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int ARB_WLAST : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int WDB_RTR_SKID : 1; + unsigned int WDB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG43 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WDATA_q_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WDATA_q_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG44 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WDATA_q_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WDATA_q_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG45 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG46 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG47 { + struct { +#if defined(qLittleEndian) + unsigned int CTRL_ARC_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int INFLT_LIMIT_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int INFLT_LIMIT_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int CTRL_ARC_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG48 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RRESP : 2; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int CNT_HOLD_q1 : 1; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int CNT_HOLD_q1 : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG49 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_PAGE_FAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RF_MMU_PAGE_FAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG50 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_CONFIG_q : 24; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int client_behavior_q : 2; + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; + unsigned int client_behavior_q : 2; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int RF_MMU_CONFIG_q : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG51 { + struct { +#if defined(qLittleEndian) + unsigned int stage1_valid : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int MMU_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int REQ_VA_OFFSET_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA_OFFSET_q : 16; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_MISS : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int stage1_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG52 { + struct { +#if defined(qLittleEndian) + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int stage1_valid : 1; + unsigned int stage2_valid : 1; + unsigned int client_behavior_q : 2; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int TAG_valid_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int TAG_valid_q : 16; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int client_behavior_q : 2; + unsigned int stage2_valid : 1; + unsigned int stage1_valid : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG53 { + struct { +#if defined(qLittleEndian) + unsigned int TAG0_VA : 13; + unsigned int TAG_valid_q_0 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG1_VA : 13; + unsigned int TAG_valid_q_1 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_1 : 1; + unsigned int TAG1_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_0 : 1; + unsigned int TAG0_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG54 { + struct { +#if defined(qLittleEndian) + unsigned int TAG2_VA : 13; + unsigned int TAG_valid_q_2 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG3_VA : 13; + unsigned int TAG_valid_q_3 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_3 : 1; + unsigned int TAG3_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_2 : 1; + unsigned int TAG2_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG55 { + struct { +#if defined(qLittleEndian) + unsigned int TAG4_VA : 13; + unsigned int TAG_valid_q_4 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG5_VA : 13; + unsigned int TAG_valid_q_5 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_5 : 1; + unsigned int TAG5_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_4 : 1; + unsigned int TAG4_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG56 { + struct { +#if defined(qLittleEndian) + unsigned int TAG6_VA : 13; + unsigned int TAG_valid_q_6 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG7_VA : 13; + unsigned int TAG_valid_q_7 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_7 : 1; + unsigned int TAG7_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_6 : 1; + unsigned int TAG6_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG57 { + struct { +#if defined(qLittleEndian) + unsigned int TAG8_VA : 13; + unsigned int TAG_valid_q_8 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG9_VA : 13; + unsigned int TAG_valid_q_9 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_9 : 1; + unsigned int TAG9_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_8 : 1; + unsigned int TAG8_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG58 { + struct { +#if defined(qLittleEndian) + unsigned int TAG10_VA : 13; + unsigned int TAG_valid_q_10 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG11_VA : 13; + unsigned int TAG_valid_q_11 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_11 : 1; + unsigned int TAG11_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_10 : 1; + unsigned int TAG10_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG59 { + struct { +#if defined(qLittleEndian) + unsigned int TAG12_VA : 13; + unsigned int TAG_valid_q_12 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG13_VA : 13; + unsigned int TAG_valid_q_13 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_13 : 1; + unsigned int TAG13_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_12 : 1; + unsigned int TAG12_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG60 { + struct { +#if defined(qLittleEndian) + unsigned int TAG14_VA : 13; + unsigned int TAG_valid_q_14 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG15_VA : 13; + unsigned int TAG_valid_q_15 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_15 : 1; + unsigned int TAG15_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_14 : 1; + unsigned int TAG14_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG61 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG62 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG63 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MMU_ENABLE : 1; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int RESERVED1 : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int RESERVED1 : 2; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int MMU_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_VA_RANGE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_64KB_REGIONS : 12; + unsigned int VA_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int VA_BASE : 20; + unsigned int NUM_64KB_REGIONS : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PT_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int PT_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int PT_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PAGE_FAULT { + struct { +#if defined(qLittleEndian) + unsigned int PAGE_FAULT : 1; + unsigned int OP_TYPE : 1; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int AXI_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int REQ_VA : 20; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA : 20; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int RESERVED1 : 1; + unsigned int AXI_ID : 3; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int OP_TYPE : 1; + unsigned int PAGE_FAULT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_TRAN_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int TRAN_ERROR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TRAN_ERROR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_INVALIDATE { + struct { +#if defined(qLittleEndian) + unsigned int INVALIDATE_ALL : 1; + unsigned int INVALIDATE_TC : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int INVALIDATE_TC : 1; + unsigned int INVALIDATE_ALL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_END { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_END : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_END : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union WAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_2D_IDLE : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int : 2; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 2; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLE : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_ISYNC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int CMDFIFO_AVAIL : 5; + unsigned int TC_BUSY : 1; + unsigned int : 2; + unsigned int HIRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int MH_BUSY : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int : 1; + unsigned int SX_BUSY : 1; + unsigned int TPC_BUSY : 1; + unsigned int : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int GUI_ACTIVE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GUI_ACTIVE : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int TPC_BUSY : 1; + unsigned int SX_BUSY : 1; + unsigned int : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int MH_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int HIRQ_PENDING : 1; + unsigned int : 2; + unsigned int TC_BUSY : 1; + unsigned int CMDFIFO_AVAIL : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DSPLY { + struct { +#if defined(qLittleEndian) + unsigned int DISPLAY_ID0_ACTIVE : 1; + unsigned int DISPLAY_ID1_ACTIVE : 1; + unsigned int DISPLAY_ID2_ACTIVE : 1; + unsigned int VSYNC_ACTIVE : 1; + unsigned int USE_DISPLAY_ID0 : 1; + unsigned int USE_DISPLAY_ID1 : 1; + unsigned int USE_DISPLAY_ID2 : 1; + unsigned int SW_CNTL : 1; + unsigned int NUM_BUFS : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int NUM_BUFS : 2; + unsigned int SW_CNTL : 1; + unsigned int USE_DISPLAY_ID2 : 1; + unsigned int USE_DISPLAY_ID1 : 1; + unsigned int USE_DISPLAY_ID0 : 1; + unsigned int VSYNC_ACTIVE : 1; + unsigned int DISPLAY_ID2_ACTIVE : 1; + unsigned int DISPLAY_ID1_ACTIVE : 1; + unsigned int DISPLAY_ID0_ACTIVE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RENDER_LATEST { + struct { +#if defined(qLittleEndian) + unsigned int BUFFER_ID : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int BUFFER_ID : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RTL_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int CHANGELIST : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CHANGELIST : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PATCH_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int PATCH_REVISION : 16; + unsigned int PATCH_SELECTION : 8; + unsigned int CUSTOMER_ID : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CUSTOMER_ID : 8; + unsigned int PATCH_SELECTION : 8; + unsigned int PATCH_REVISION : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_AUXILIARY_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID0 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER0 : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PARTNUMBER0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID1 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER1 : 4; + unsigned int DESIGNER0 : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int DESIGNER0 : 4; + unsigned int PARTNUMBER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID2 { + struct { +#if defined(qLittleEndian) + unsigned int DESIGNER1 : 4; + unsigned int REVISION : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int REVISION : 4; + unsigned int DESIGNER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID3 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_HOST_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int MH_INTERFACE : 2; + unsigned int : 1; + unsigned int CONTINUATION : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CONTINUATION : 1; + unsigned int : 1; + unsigned int MH_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int RBBM_HOST_INTERFACE : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int READ_TIMEOUT : 8; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int READ_TIMEOUT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SKEW_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SKEW_TOP_THRESHOLD : 5; + unsigned int SKEW_COUNT : 5; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int SKEW_COUNT : 5; + unsigned int SKEW_TOP_THRESHOLD : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SOFT_RESET { + struct { +#if defined(qLittleEndian) + unsigned int SOFT_RESET_CP : 1; + unsigned int : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_SX : 1; + unsigned int : 5; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 2; + unsigned int SOFT_RESET_SC : 1; + unsigned int SOFT_RESET_VGT : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int SOFT_RESET_VGT : 1; + unsigned int SOFT_RESET_SC : 1; + unsigned int : 2; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 5; + unsigned int SOFT_RESET_SX : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int : 1; + unsigned int SOFT_RESET_CP : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE1 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE2 { + struct { +#if defined(qLittleEndian) + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GC_SYS_IDLE { + struct { +#if defined(qLittleEndian) + unsigned int GC_SYS_IDLE_DELAY : 16; + unsigned int : 15; + unsigned int GC_SYS_IDLE_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GC_SYS_IDLE_OVERRIDE : 1; + unsigned int : 15; + unsigned int GC_SYS_IDLE_DELAY : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union NQWAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_GUI_IDLE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int WAIT_GUI_IDLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int IGNORE_RTR : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int : 3; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 4; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int : 6; + unsigned int IGNORE_SX_RBBM_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int IGNORE_SX_RBBM_BUSY : 1; + unsigned int : 6; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int : 4; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 3; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_RTR : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_READ_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int READ_ADDRESS : 15; + unsigned int : 13; + unsigned int READ_REQUESTER : 1; + unsigned int READ_ERROR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int READ_ERROR : 1; + unsigned int READ_REQUESTER : 1; + unsigned int : 13; + unsigned int READ_ADDRESS : 15; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_WAIT_IDLE_CLOCKS { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_MASK : 1; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int RDERR_INT_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_STAT : 1; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int RDERR_INT_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_ACK : 1; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int RDERR_INT_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MASTER_INT_SIGNAL { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int MH_INT_STAT : 1; + unsigned int : 24; + unsigned int CP_INT_STAT : 1; + unsigned int RBBM_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RBBM_INT_STAT : 1; + unsigned int CP_INT_STAT : 1; + unsigned int : 24; + unsigned int MH_INT_STAT : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERF_COUNT1_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT1_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT1_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int RB_BASE : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BASE : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RB_BUFSZ : 6; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_POLL_EN : 1; + unsigned int : 6; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 3; + unsigned int RB_RPTR_WR_ENA : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_WR_ENA : 1; + unsigned int : 3; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 6; + unsigned int RB_POLL_EN : 1; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int RB_BUFSZ : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_SWAP : 2; + unsigned int RB_RPTR_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_ADDR : 30; + unsigned int RB_RPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_WR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_WR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR_WR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_WPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_DELAY { + struct { +#if defined(qLittleEndian) + unsigned int PRE_WRITE_TIMER : 28; + unsigned int PRE_WRITE_LIMIT : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PRE_WRITE_LIMIT : 4; + unsigned int PRE_WRITE_TIMER : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR_SWAP : 2; + unsigned int RB_WPTR_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_WPTR_BASE : 30; + unsigned int RB_WPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB1_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB1_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB1_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB1_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB2_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB2_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB2_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB2_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int ST_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int ST_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int ST_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int ST_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_QUEUE_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_IB1_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_ST_START : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int CSQ_ST_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_IB1_START : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int MEQ_END : 5; + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; + unsigned int MEQ_END : 5; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_CNT_RING : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_RING : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int STQ_CNT_ST : 7; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int STQ_CNT_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_CNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int MEQ_CNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_RB_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_PRIMARY : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB1_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT1 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB2_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT2 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NON_PREFETCH_CNTRS { + struct { +#if defined(qLittleEndian) + unsigned int IB1_COUNTER : 3; + unsigned int : 5; + unsigned int IB2_COUNTER : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int IB2_COUNTER : 3; + unsigned int : 5; + unsigned int IB1_COUNTER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_ST_STAT { + struct { +#if defined(qLittleEndian) + unsigned int STQ_RPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_RPTR_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_RPTR : 10; + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; + unsigned int MEQ_RPTR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MIU_TAG_STAT { + struct { +#if defined(qLittleEndian) + unsigned int TAG_0_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_17_STAT : 1; + unsigned int : 13; + unsigned int INVALID_RETURN_TAG : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INVALID_RETURN_TAG : 1; + unsigned int : 13; + unsigned int TAG_17_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_0_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int CMD_INDEX : 7; + unsigned int : 9; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 9; + unsigned int CMD_INDEX : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CMD_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CMD_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int ME_STATMUX : 16; + unsigned int : 9; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 1; + unsigned int ME_HALT : 1; + unsigned int ME_BUSY : 1; + unsigned int : 1; + unsigned int PROG_CNT_SIZE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PROG_CNT_SIZE : 1; + unsigned int : 1; + unsigned int ME_BUSY : 1; + unsigned int ME_HALT : 1; + unsigned int : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 9; + unsigned int ME_STATMUX : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int ME_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_WADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_WADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_WADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_RADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_RADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_RADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_DATA { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RAM_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RDADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RDADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RDADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; + unsigned int PREDICATE_DISABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int MIU_WRITE_PACK_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MIU_WRITE_PACK_DISABLE : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int PREDICATE_DISABLE : 1; + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG4 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG4 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG5 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG5 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG6 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG6 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG7 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG7 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_UMSK { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_UMSK : 8; + unsigned int : 8; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 8; + unsigned int SCRATCH_UMSK : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int SCRATCH_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWM : 1; + unsigned int VS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_DONE_CNTR : 1; + unsigned int VS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP : 2; + unsigned int VS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR : 30; + unsigned int VS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP_SWM : 2; + unsigned int VS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR_SWM : 30; + unsigned int VS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWM : 1; + unsigned int PS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int PS_DONE_CNTR : 1; + unsigned int PS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP : 2; + unsigned int PS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR : 30; + unsigned int PS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP_SWM : 2; + unsigned int PS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR_SWM : 30; + unsigned int PS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SRC : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CF_DONE_SRC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SWAP : 2; + unsigned int CF_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_ADDR : 30; + unsigned int CF_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_SWAP : 2; + unsigned int NRT_WRITE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_ADDR : 30; + unsigned int NRT_WRITE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_CNTR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int VS_FETCH_DONE_CNTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_SWAP : 2; + unsigned int VS_FETCH_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_ADDR : 30; + unsigned int VS_FETCH_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_MASK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int RB_INT_MASK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int : 3; + unsigned int SW_INT_MASK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_STAT : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int RB_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int : 3; + unsigned int SW_INT_STAT : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_ACK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int RB_INT_ACK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int : 3; + unsigned int SW_INT_ACK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_ADDR : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int UCODE_ADDR : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_DATA : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int UCODE_DATA : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFMON_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PERFMON_STATE : 4; + unsigned int : 4; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 4; + unsigned int PERFMON_STATE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERFCOUNT_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNT_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_0 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_0 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_15 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_15 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_1 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_16 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_31 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_31 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_16 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_2 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_32 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_47 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_47 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_32 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_3 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_48 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_63 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_63 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_48 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_INDEX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int STATE_DEBUG_INDEX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATE_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PROG_COUNTER { + struct { +#if defined(qLittleEndian) + unsigned int COUNTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COUNTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MIU_WR_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int _3D_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int ME_WC_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int CP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CP_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int ME_WC_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int _3D_BUSY : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_WR_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_0_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_1_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_2_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_3_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_4_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_5_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_6_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_7_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_8_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_9_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_10_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_11_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_12_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_13_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_14_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_15_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int : 8; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 8; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_HOST { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int : 8; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 8; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_0 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_0 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_0 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_1 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_1 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_1 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_2 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_2 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_2 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_3 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_3 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_3 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_4 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_4 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_4 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_5 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_5 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_5 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_6 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_6 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_6 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_7 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_7 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_7 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SURFACE_INFO { + struct { +#if defined(qLittleEndian) + unsigned int SURFACE_PITCH : 14; + unsigned int MSAA_SAMPLES : 2; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MSAA_SAMPLES : 2; + unsigned int SURFACE_PITCH : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_FORMAT : 4; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_SWAP : 2; + unsigned int : 1; + unsigned int COLOR_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_BASE : 20; + unsigned int : 1; + unsigned int COLOR_SWAP : 2; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_FORMAT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_INFO { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_FORMAT : 1; + unsigned int : 11; + unsigned int DEPTH_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_BASE : 20; + unsigned int : 11; + unsigned int DEPTH_FORMAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILREF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ALPHA_REF { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_REF : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_REF : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_MASK { + struct { +#if defined(qLittleEndian) + unsigned int WRITE_RED : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int : 28; +#else /* !defined(qLittleEndian) */ + unsigned int : 28; + unsigned int WRITE_ALPHA : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_RED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_RED { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_RED : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_GREEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_GREEN : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_GREEN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_BLUE { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_BLUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_BLUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_ALPHA { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_ALPHA : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_ALPHA : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FOG_COLOR { + struct { +#if defined(qLittleEndian) + unsigned int FOG_RED : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_BLUE : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int FOG_BLUE : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK_BF { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILREF_BF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTHCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int STENCIL_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int STENCILFUNC : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILZFAIL_BF : 3; +#else /* !defined(qLittleEndian) */ + unsigned int STENCILZFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int STENCIL_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLENDCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_SRCBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int BLEND_FORCE : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BLEND_FORCE : 1; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_SRCBLEND : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLORCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_FUNC : 3; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int FOG_ENABLE : 1; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int ROP_CODE : 4; + unsigned int DITHER_MODE : 2; + unsigned int DITHER_TYPE : 2; + unsigned int PIXEL_FOG : 1; + unsigned int : 7; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int : 7; + unsigned int PIXEL_FOG : 1; + unsigned int DITHER_TYPE : 2; + unsigned int DITHER_MODE : 2; + unsigned int ROP_CODE : 4; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int FOG_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_FUNC : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_MODECONTROL { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_MODE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int EDRAM_MODE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_DEST_MASK { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_DEST_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_DEST_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COPY_SAMPLE_SELECT : 3; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int CLEAR_MASK : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CLEAR_MASK : 4; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int COPY_SAMPLE_SELECT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int COPY_DEST_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COPY_DEST_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PITCH { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_PITCH : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int COPY_DEST_PITCH : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_ENDIAN : 3; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_ENDIAN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PIXEL_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET_X : 13; + unsigned int OFFSET_Y : 13; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int OFFSET_Y : 13; + unsigned int OFFSET_X : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_CLEAR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_CLEAR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_CTL { + struct { +#if defined(qLittleEndian) + unsigned int RESET_SAMPLE_COUNT : 1; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int RESET_SAMPLE_COUNT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int SAMPLE_COUNT_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLE_COUNT_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int CRC_MODE : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int DISABLE_ACCUM : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int RESERVED9 : 1; + unsigned int RESERVED10 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED10 : 1; + unsigned int RESERVED9 : 1; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int DISABLE_ACCUM : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int CRC_MODE : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_EDRAM_INFO { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_SIZE : 4; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int : 8; + unsigned int EDRAM_RANGE : 18; +#else /* !defined(qLittleEndian) */ + unsigned int EDRAM_RANGE : 18; + unsigned int : 8; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int EDRAM_SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_RD_PORT { + struct { +#if defined(qLittleEndian) + unsigned int CRC_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int CRC_RD_ADVANCE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CRC_RD_ADVANCE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_MASK { + struct { +#if defined(qLittleEndian) + unsigned int CRC_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_TOTAL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int TOTAL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int TOTAL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZPASS_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZPASS_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZPASS_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int SFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int EZ_INFSAMP_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_Z1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int EZ_INFSAMP_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_Z1_CMD_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int TILE_FIFO_COUNT : 4; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z_TILE_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int Z_TILE_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int TILE_FIFO_COUNT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_VALID : 4; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int SHD_FULL : 1; + unsigned int SHD_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int SHD_EMPTY : 1; + unsigned int SHD_FULL : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_VALID : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int GMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int : 19; +#else /* !defined(qLittleEndian) */ + unsigned int : 19; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int GMEM_RD_ACCESS_FLAG : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FLAG_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_FLAG_CLEAR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int DEBUG_FLAG_CLEAR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_ENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_MOREENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h new file mode 100644 index 000000000000..2049d0f7bd14 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h @@ -0,0 +1,4078 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_SHIFT_HEADER) +#define _yamato_SHIFT_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT 0x00000016 +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT 0x00000017 +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT 0x00000018 + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT 0x0000000f +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT 0x00000012 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT 0x00000017 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT 0x00000019 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT 0x00000000 +#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT 0x00000008 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT 0x00000000 +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT 0x00000001 +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT 0x00000007 + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT 0x0000001f + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000014 + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000018 + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT 0x00000008 + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT 0x0000001c + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT 0x00000004 + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT 0x00000016 + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT 0x0000001b + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x0000000a +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT 0x0000000d +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001f + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT 0x0000000b +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT 0x00000019 + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT 0x00000001 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000003 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT 0x00000016 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT 0x0000001b +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x00000005 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT 0x00000008 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x0000000e +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT 0x00000016 + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000005 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000b +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000c +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT 0x0000000d +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x0000000e +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x0000000f +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000010 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000011 + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000c +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x0000000d +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000010 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000011 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000014 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000015 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x00000017 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001a +#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT 0x0000001b +#define SETUP_DEBUG_REG4__event_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001d + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x00000016 +#define SETUP_DEBUG_REG5__event_id_gated__SHIFT 0x00000018 + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1__SHIFT 0x00000000 +#define SC_DEBUG_0__pa_sc_valid__SHIFT 0x00000001 +#define SC_DEBUG_0__pa_sc_phase__SHIFT 0x00000002 +#define SC_DEBUG_0__cntx_cnt__SHIFT 0x00000005 +#define SC_DEBUG_0__decr_cntx_cnt__SHIFT 0x0000000c +#define SC_DEBUG_0__incr_cntx_cnt__SHIFT 0x0000000d +#define SC_DEBUG_0__trigger__SHIFT 0x0000001f + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state__SHIFT 0x00000000 +#define SC_DEBUG_1__em1_data_ready__SHIFT 0x00000003 +#define SC_DEBUG_1__em2_data_ready__SHIFT 0x00000004 +#define SC_DEBUG_1__move_em1_to_em2__SHIFT 0x00000005 +#define SC_DEBUG_1__ef_data_ready__SHIFT 0x00000006 +#define SC_DEBUG_1__ef_state__SHIFT 0x00000007 +#define SC_DEBUG_1__pipe_valid__SHIFT 0x00000009 +#define SC_DEBUG_1__trigger__SHIFT 0x0000001f + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly__SHIFT 0x00000000 +#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT 0x00000001 +#define SC_DEBUG_2__pipe_freeze_b__SHIFT 0x00000003 +#define SC_DEBUG_2__prim_rts__SHIFT 0x00000004 +#define SC_DEBUG_2__next_prim_rts_dly__SHIFT 0x00000005 +#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT 0x00000006 +#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT 0x00000007 +#define SC_DEBUG_2__stage0_rts__SHIFT 0x00000008 +#define SC_DEBUG_2__phase_rts_dly__SHIFT 0x00000009 +#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT 0x0000000f +#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT 0x00000010 +#define SC_DEBUG_2__event_id_s1__SHIFT 0x00000011 +#define SC_DEBUG_2__event_s1__SHIFT 0x00000016 +#define SC_DEBUG_2__trigger__SHIFT 0x0000001f + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1__SHIFT 0x00000000 +#define SC_DEBUG_3__y_curr_s1__SHIFT 0x0000000b +#define SC_DEBUG_3__trigger__SHIFT 0x0000001f + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_4__y_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_4__y_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_4__trigger__SHIFT 0x0000001f + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_5__x_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_5__x_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_5__trigger__SHIFT 0x0000001f + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty__SHIFT 0x00000000 +#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT 0x00000001 +#define SC_DEBUG_6__xy_ff_empty__SHIFT 0x00000002 +#define SC_DEBUG_6__event_flag__SHIFT 0x00000003 +#define SC_DEBUG_6__z_mask_needed__SHIFT 0x00000004 +#define SC_DEBUG_6__state__SHIFT 0x00000005 +#define SC_DEBUG_6__state_delayed__SHIFT 0x00000008 +#define SC_DEBUG_6__data_valid__SHIFT 0x0000000b +#define SC_DEBUG_6__data_valid_d__SHIFT 0x0000000c +#define SC_DEBUG_6__tilex_delayed__SHIFT 0x0000000d +#define SC_DEBUG_6__tiley_delayed__SHIFT 0x00000016 +#define SC_DEBUG_6__trigger__SHIFT 0x0000001f + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag__SHIFT 0x00000000 +#define SC_DEBUG_7__deallocate__SHIFT 0x00000001 +#define SC_DEBUG_7__fpos__SHIFT 0x00000004 +#define SC_DEBUG_7__sr_prim_we__SHIFT 0x00000005 +#define SC_DEBUG_7__last_tile__SHIFT 0x00000006 +#define SC_DEBUG_7__tile_ff_we__SHIFT 0x00000007 +#define SC_DEBUG_7__qs_data_valid__SHIFT 0x00000008 +#define SC_DEBUG_7__qs_q0_y__SHIFT 0x00000009 +#define SC_DEBUG_7__qs_q0_x__SHIFT 0x0000000b +#define SC_DEBUG_7__qs_q0_valid__SHIFT 0x0000000d +#define SC_DEBUG_7__prim_ff_we__SHIFT 0x0000000e +#define SC_DEBUG_7__tile_ff_re__SHIFT 0x0000000f +#define SC_DEBUG_7__fw_prim_data_valid__SHIFT 0x00000010 +#define SC_DEBUG_7__last_quad_of_tile__SHIFT 0x00000011 +#define SC_DEBUG_7__first_quad_of_tile__SHIFT 0x00000012 +#define SC_DEBUG_7__first_quad_of_prim__SHIFT 0x00000013 +#define SC_DEBUG_7__new_prim__SHIFT 0x00000014 +#define SC_DEBUG_7__load_new_tile_data__SHIFT 0x00000015 +#define SC_DEBUG_7__state__SHIFT 0x00000016 +#define SC_DEBUG_7__fifos_ready__SHIFT 0x00000018 +#define SC_DEBUG_7__trigger__SHIFT 0x0000001f + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last__SHIFT 0x00000000 +#define SC_DEBUG_8__sample_mask__SHIFT 0x00000001 +#define SC_DEBUG_8__sample_y__SHIFT 0x00000005 +#define SC_DEBUG_8__sample_x__SHIFT 0x00000007 +#define SC_DEBUG_8__sample_send__SHIFT 0x00000009 +#define SC_DEBUG_8__next_cycle__SHIFT 0x0000000a +#define SC_DEBUG_8__ez_sample_ff_full__SHIFT 0x0000000c +#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT 0x0000000d +#define SC_DEBUG_8__num_samples__SHIFT 0x0000000e +#define SC_DEBUG_8__last_quad_of_tile__SHIFT 0x00000010 +#define SC_DEBUG_8__last_quad_of_prim__SHIFT 0x00000011 +#define SC_DEBUG_8__first_quad_of_prim__SHIFT 0x00000012 +#define SC_DEBUG_8__sample_we__SHIFT 0x00000013 +#define SC_DEBUG_8__fpos__SHIFT 0x00000014 +#define SC_DEBUG_8__event_id__SHIFT 0x00000015 +#define SC_DEBUG_8__event_flag__SHIFT 0x0000001a +#define SC_DEBUG_8__fw_prim_data_valid__SHIFT 0x0000001b +#define SC_DEBUG_8__trigger__SHIFT 0x0000001f + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send__SHIFT 0x00000000 +#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT 0x00000001 +#define SC_DEBUG_9__fifo_data_ready__SHIFT 0x00000005 +#define SC_DEBUG_9__early_z_enable__SHIFT 0x00000006 +#define SC_DEBUG_9__mask_state__SHIFT 0x00000007 +#define SC_DEBUG_9__next_ez_mask__SHIFT 0x00000009 +#define SC_DEBUG_9__mask_ready__SHIFT 0x00000019 +#define SC_DEBUG_9__drop_sample__SHIFT 0x0000001a +#define SC_DEBUG_9__fetch_new_sample_data__SHIFT 0x0000001b +#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT 0x0000001c +#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT 0x0000001d +#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT 0x0000001e +#define SC_DEBUG_9__trigger__SHIFT 0x0000001f + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask__SHIFT 0x00000000 +#define SC_DEBUG_10__trigger__SHIFT 0x0000001f + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready__SHIFT 0x00000000 +#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT 0x00000001 +#define SC_DEBUG_11__ez_prim_data_ready__SHIFT 0x00000002 +#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT 0x00000003 +#define SC_DEBUG_11__iterator_input_fz__SHIFT 0x00000004 +#define SC_DEBUG_11__packer_send_quads__SHIFT 0x00000005 +#define SC_DEBUG_11__packer_send_cmd__SHIFT 0x00000006 +#define SC_DEBUG_11__packer_send_event__SHIFT 0x00000007 +#define SC_DEBUG_11__next_state__SHIFT 0x00000008 +#define SC_DEBUG_11__state__SHIFT 0x0000000b +#define SC_DEBUG_11__stall__SHIFT 0x0000000e +#define SC_DEBUG_11__trigger__SHIFT 0x0000001f + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT 0x00000000 +#define SC_DEBUG_12__event_id__SHIFT 0x00000001 +#define SC_DEBUG_12__event_flag__SHIFT 0x00000006 +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT 0x00000007 +#define SC_DEBUG_12__itercmdfifo_full__SHIFT 0x00000008 +#define SC_DEBUG_12__itercmdfifo_empty__SHIFT 0x00000009 +#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT 0x0000000a +#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT 0x0000000b +#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT 0x0000000c +#define SC_DEBUG_12__iter_qdhit0__SHIFT 0x0000000d +#define SC_DEBUG_12__bc_use_centers_reg__SHIFT 0x0000000e +#define SC_DEBUG_12__bc_output_xy_reg__SHIFT 0x0000000f +#define SC_DEBUG_12__iter_phase_out__SHIFT 0x00000010 +#define SC_DEBUG_12__iter_phase_reg__SHIFT 0x00000012 +#define SC_DEBUG_12__iterator_SP_valid__SHIFT 0x00000014 +#define SC_DEBUG_12__eopv_reg__SHIFT 0x00000015 +#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT 0x00000016 +#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT 0x00000017 +#define SC_DEBUG_12__trigger__SHIFT 0x0000001f + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000006 +#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT 0x0000000b +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x0000000c +#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT 0x0000000d +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT 0x0000000e +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT 0x0000000f +#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT 0x00000010 + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_DMA_SIZE__SWAP_MODE__SHIFT 0x0000001e + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT 0x00000000 + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS__SHIFT 0x00000000 + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT 0x00000006 + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT 0x00000006 + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x00000000 + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 +#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT 0x00000001 +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT 0x00000002 +#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT 0x00000003 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000004 +#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT 0x00000005 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000006 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000007 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000008 + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT 0x00000001 +#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT 0x00000002 +#define VGT_DEBUG_REG0__dma_request_busy__SHIFT 0x00000003 +#define VGT_DEBUG_REG0__out_busy__SHIFT 0x00000004 +#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT 0x00000005 +#define VGT_DEBUG_REG0__grp_busy__SHIFT 0x00000006 +#define VGT_DEBUG_REG0__dma_busy__SHIFT 0x00000007 +#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT 0x00000008 +#define VGT_DEBUG_REG0__rbiu_busy__SHIFT 0x00000009 +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT 0x0000000a +#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT 0x0000000b +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0000000c +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x0000000d +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT 0x0000000e +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT 0x0000000f +#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT 0x00000010 + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read__SHIFT 0x00000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000001 +#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000003 +#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT 0x00000004 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000005 +#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT 0x00000006 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000007 +#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000a +#define VGT_DEBUG_REG1__grp_te_valid__SHIFT 0x0000000b +#define VGT_DEBUG_REG1__pt_grp_read__SHIFT 0x0000000c +#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__vr_grp_read__SHIFT 0x0000000e +#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT 0x0000000f +#define VGT_DEBUG_REG1__grp_dma_read__SHIFT 0x00000010 +#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT 0x00000011 +#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT 0x00000012 +#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT 0x00000013 +#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT 0x00000015 +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT 0x00000016 +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT 0x00000017 +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT 0x00000019 +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT 0x0000001b +#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT 0x0000001d +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT 0x0000001e + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT 0x00000000 +#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT 0x00000001 + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG6__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG6__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG6__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG6__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG6__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG6__grp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG7__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG8__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG8__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG8__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG9__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG9__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG9__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG9__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG9__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG9__grp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000 +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001 +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002 +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003 +#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT 0x00000005 +#define VGT_DEBUG_REG10__bin_valid__SHIFT 0x00000006 +#define VGT_DEBUG_REG10__read_block__SHIFT 0x00000007 +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG10__selected_data__SHIFT 0x0000000b +#define VGT_DEBUG_REG10__mask_input_data__SHIFT 0x00000013 +#define VGT_DEBUG_REG10__gap_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT 0x0000001c +#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT 0x0000001d +#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT 0x0000001e +#define VGT_DEBUG_REG10__grp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG12__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG12__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG12__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG12__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG12__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG13__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG14__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG14__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG14__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG15__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG15__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG15__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG15__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG15__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT 0x00000000 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT 0x00000008 +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG16__rst_last_bit__SHIFT 0x0000000a +#define VGT_DEBUG_REG16__current_state_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG16__old_state_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG16__old_state_en__SHIFT 0x0000000d +#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG16__load_empty_reg__SHIFT 0x00000012 +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT 0x00000013 +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG17__extend_read_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG17__grp_indx_size__SHIFT 0x00000002 +#define VGT_DEBUG_REG17__cull_prim_true__SHIFT 0x00000004 +#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG17__check_second_reg__SHIFT 0x00000008 +#define VGT_DEBUG_REG17__check_first_reg__SHIFT 0x00000009 +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT 0x00000006 +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d +#define VGT_DEBUG_REG18__dma_mem_full__SHIFT 0x0000000f +#define VGT_DEBUG_REG18__dma_ram_re__SHIFT 0x00000010 +#define VGT_DEBUG_REG18__dma_ram_we__SHIFT 0x00000011 +#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT 0x00000013 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT 0x00000014 +#define VGT_DEBUG_REG18__bin_mem_full__SHIFT 0x00000015 +#define VGT_DEBUG_REG18__bin_ram_we__SHIFT 0x00000016 +#define VGT_DEBUG_REG18__bin_ram_re__SHIFT 0x00000017 +#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT 0x00000018 +#define VGT_DEBUG_REG18__start_bin_req__SHIFT 0x00000019 +#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT 0x0000001a +#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT 0x0000001b +#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT 0x0000001c +#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT 0x0000001d +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT 0x00000000 +#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT 0x00000002 +#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT 0x00000006 +#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT 0x00000008 +#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT 0x0000000a +#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT 0x0000000b +#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT 0x0000000c +#define VGT_DEBUG_REG20__hold_prim__SHIFT 0x0000000d +#define VGT_DEBUG_REG20__sent_cnt__SHIFT 0x0000000e +#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT 0x00000012 +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT 0x00000013 +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT 0x00000014 +#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT 0x00000015 +#define VGT_DEBUG_REG20__out_trigger__SHIFT 0x0000001a + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT 0x00000000 +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001 +#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG21__new_packet_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG21__new_allocate_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT 0x00000014 +#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG21__insert_null_prim__SHIFT 0x00000017 +#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT 0x00000018 +#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT 0x00000019 +#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT 0x0000001a +#define VGT_DEBUG_REG21__out_trigger__SHIFT 0x0000001f + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC__SHIFT 0x00000000 + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT 0x00000000 +#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT 0x00000012 +#define TC_CNTL_STATUS__TC_BUSY__SHIFT 0x0000001f + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000 +#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT 0x00000008 +#define TCM_CHICKEN__SPARE__SHIFT 0x00000009 + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT 0x00000000 +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT 0x00000003 + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT 0x00000000 +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT 0x00000001 +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT 0x00000002 +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT 0x00000003 +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT 0x00000004 +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT 0x00000005 +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT 0x00000006 +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT 0x00000008 +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT 0x00000009 +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT 0x0000000a +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT 0x0000000c +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT 0x0000000d +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT 0x0000000e +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT 0x0000000f +#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT 0x00000010 +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT 0x00000011 +#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT 0x00000013 +#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT 0x00000014 +#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT 0x00000015 +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT 0x00000016 +#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT 0x00000017 +#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT 0x00000018 +#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT 0x00000019 +#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT 0x0000001b +#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT 0x0000001c +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT 0x0000001d +#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT 0x0000001e +#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT 0x0000001f + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL__SHIFT 0x00000000 +#define TPC_DEBUG0__IC_CTR__SHIFT 0x00000002 +#define TPC_DEBUG0__WALKER_CNTL__SHIFT 0x00000004 +#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT 0x00000008 +#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT 0x0000000c +#define TPC_DEBUG0__WALKER_STATE__SHIFT 0x00000010 +#define TPC_DEBUG0__ALIGNER_STATE__SHIFT 0x0000001a +#define TPC_DEBUG0__REG_CLK_EN__SHIFT 0x0000001d +#define TPC_DEBUG0__TPC_CLK_EN__SHIFT 0x0000001e +#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT 0x0000001f + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED__SHIFT 0x00000000 + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION__SHIFT 0x00000000 +#define TPC_CHICKEN__SPARE__SHIFT 0x00000001 + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT 0x00000000 +#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT 0x00000001 +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT 0x00000002 +#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT 0x00000003 +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT 0x00000004 +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT 0x00000005 +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT 0x00000006 +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT 0x00000007 +#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT 0x00000008 +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT 0x00000009 +#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT 0x0000000a +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT 0x0000000b +#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT 0x0000000c +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT 0x0000000d +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT 0x0000000e +#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT 0x00000010 +#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT 0x00000011 +#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT 0x00000012 +#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT 0x00000013 +#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT 0x00000014 +#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT 0x00000015 +#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT 0x00000016 +#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT 0x00000017 +#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT 0x00000018 +#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT 0x00000019 +#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT 0x0000001a +#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT 0x0000001b +#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT 0x0000001c +#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT 0x0000001d +#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT 0x0000001e +#define TP0_CNTL_STATUS__TP_BUSY__SHIFT 0x0000001f + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL__SHIFT 0x00000000 +#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT 0x00000003 +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT 0x00000004 +#define TP0_DEBUG__REG_CLK_EN__SHIFT 0x00000015 +#define TP0_DEBUG__PERF_CLK_EN__SHIFT 0x00000016 +#define TP0_DEBUG__TP_CLK_EN__SHIFT 0x00000017 +#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT 0x00000018 +#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT 0x0000001c + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE__SHIFT 0x00000000 +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT 0x00000001 +#define TP0_CHICKEN__SPARE__SHIFT 0x00000002 + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr__SHIFT 0x00000006 +#define TCF_DEBUG__TC_MH_send__SHIFT 0x00000007 +#define TCF_DEBUG__not_FG0_rtr__SHIFT 0x00000008 +#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT 0x0000000c +#define TCF_DEBUG__TCB_ff_stall__SHIFT 0x0000000d +#define TCF_DEBUG__TCB_miss_stall__SHIFT 0x0000000e +#define TCF_DEBUG__TCA_TCB_stall__SHIFT 0x0000000f +#define TCF_DEBUG__PF0_stall__SHIFT 0x00000010 +#define TCF_DEBUG__TP0_full__SHIFT 0x00000014 +#define TCF_DEBUG__TPC_full__SHIFT 0x00000018 +#define TCF_DEBUG__not_TPC_rtr__SHIFT 0x00000019 +#define TCF_DEBUG__tca_state_rts__SHIFT 0x0000001a +#define TCF_DEBUG__tca_rts__SHIFT 0x0000001b + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full__SHIFT 0x00000000 +#define TCA_FIFO_DEBUG__tpc_full__SHIFT 0x00000004 +#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT 0x00000005 +#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT 0x00000006 +#define TCA_FIFO_DEBUG__FW_full__SHIFT 0x00000007 +#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT 0x00000008 +#define TCA_FIFO_DEBUG__FW_rts0__SHIFT 0x0000000c +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT 0x00000010 +#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT 0x00000011 + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT 0x00000000 + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts__SHIFT 0x0000000c +#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT 0x0000000d + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512__SHIFT 0x00000000 +#define TCB_CORE_DEBUG__tiled__SHIFT 0x00000001 +#define TCB_CORE_DEBUG__opcode__SHIFT 0x00000004 +#define TCB_CORE_DEBUG__format__SHIFT 0x00000008 +#define TCB_CORE_DEBUG__sector_format__SHIFT 0x00000010 +#define TCB_CORE_DEBUG__sector_format512__SHIFT 0x00000018 + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG0_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG0_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG1_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG1_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG2_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG2_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG3_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG3_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT 0x00000004 +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT 0x0000000b +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT 0x0000000c +#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT 0x0000000f +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010 + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT 0x00000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT 0x00000002 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015 +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT 0x00000017 +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT 0x00000018 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT 0x00000019 +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT 0x0000001a +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT 0x0000001c +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT 0x0000001e + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty__SHIFT 0x00000010 +#define TCD_INPUT0_DEBUG__full__SHIFT 0x00000011 +#define TCD_INPUT0_DEBUG__valid_q1__SHIFT 0x00000014 +#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT 0x00000015 +#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT 0x00000017 +#define TCD_INPUT0_DEBUG__ip_send__SHIFT 0x00000018 +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT 0x00000019 +#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT 0x0000001a + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT 0x00000000 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT 0x00000002 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT 0x00000003 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT 0x00000004 +#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT 0x00000005 +#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT 0x00000006 + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT 0x00000009 +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT 0x0000000a +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT 0x0000000b +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT 0x00000014 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT 0x0000001c +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT 0x0000001d + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT 0x00000004 +#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT 0x00000005 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT 0x00000006 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT 0x00000007 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT 0x00000009 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT 0x0000000c +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT 0x00000012 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT 0x0000001e +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT 0x0000001f + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT 0x0000000a +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT 0x0000000b +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT 0x00000011 +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT 0x00000012 +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT 0x00000013 +#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT 0x0000001f + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT 0x00000005 +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT 0x00000006 +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT 0x00000007 + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT 0x00000008 +#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT 0x00000009 +#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT 0x0000000a +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT 0x0000000c +#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT 0x0000000d +#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT 0x00000010 +#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG0__busy__SHIFT 0x0000001e + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG1__empty__SHIFT 0x00000001 +#define TCO_QUAD0_DEBUG1__full__SHIFT 0x00000002 +#define TCO_QUAD0_DEBUG1__write_enable__SHIFT 0x00000003 +#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT 0x00000004 +#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT 0x00000014 +#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT 0x00000015 +#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT 0x00000016 +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT 0x00000017 +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT 0x0000001e + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT 0x00000000 +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT 0x00000004 +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT 0x0000000c + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT 0x00000000 +#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT 0x00000004 +#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT 0x00000008 +#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT 0x0000000c +#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT 0x00000010 +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT 0x00000011 +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT 0x00000012 +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013 +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT 0x00000015 +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT 0x00000016 +#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT 0x00000017 +#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT 0x00000018 +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT 0x00000019 +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT 0x0000001b + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT 0x00000000 +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT 0x00000010 + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000 +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008 +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT 0x00000010 + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT 0x00000000 +#define SQ_EO_RT__EO_TSTATE_RT__SHIFT 0x00000010 + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT 0x00000000 +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT 0x0000000c +#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT 0x00000014 +#define SQ_DEBUG_MISC__RESERVED__SHIFT 0x00000015 +#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT 0x00000017 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT 0x00000019 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT 0x0000001a +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT 0x0000001b +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT 0x0000001c + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT 0x00000000 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT 0x00000008 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT 0x00000010 +#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT 0x00000018 + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT 0x00000000 + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 +#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT 0x00000012 +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014 +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015 +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016 + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT 0x00000000 +#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT 0x00000003 +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT 0x00000004 +#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT 0x00000008 +#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT 0x0000000c +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT 0x0000000f +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT 0x00000014 + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT 0x00000005 +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT 0x0000000d +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010 +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017 + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT 0x00000000 +#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT 0x00000004 +#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT 0x00000008 +#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT 0x0000000c +#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT 0x0000000e +#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT 0x00000010 +#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT 0x00000012 +#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT 0x00000014 +#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT 0x00000016 +#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT 0x00000018 +#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT 0x0000001a +#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT 0x00000000 +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT 0x00000004 +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT 0x0000000c +#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT 0x0000000f +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT 0x00000010 + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT 0x00000000 +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT 0x00000001 +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT 0x00000005 +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT 0x00000006 +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT 0x00000009 +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT 0x0000000e +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT 0x0000000f +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT 0x00000010 +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT 0x00000011 + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017 +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT 0x0000001d +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT 0x00000000 +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT 0x00000004 +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT 0x00000008 +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT 0x00000010 +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT 0x00000014 +#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT 0x00000015 + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT 0x00000006 +#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT 0x00000013 +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT 0x00000019 +#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT 0x0000001f + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT 0x0000001a + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT 0x00000002 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT 0x00000004 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT 0x0000000a +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT 0x0000000c +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT 0x00000012 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT 0x0000001a +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT 0x0000001b +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT 0x0000001f + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT 0x00000017 +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT 0x00000013 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT 0x00000014 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT 0x00000015 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT 0x00000016 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT 0x00000017 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT 0x0000001e +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT 0x00000003 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT 0x00000006 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT 0x00000007 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT 0x00000015 + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT 0x0000001a + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT 0x0000000f + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT 0x0000001e + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT 0x00000004 + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT 0x00000014 + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT 0x00000013 +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT 0x00000019 +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT 0x0000001e + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT 0x0000000e +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT 0x00000018 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT 0x0000001d +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT 0x00000013 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT 0x00000019 +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT 0x0000001e + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT 0x00000017 +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT 0x00000001 +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE__SHIFT 0x00000000 + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE__SHIFT 0x00000000 + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_VS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_PS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT 0x00000000 +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT 0x0000000c + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT 0x00000000 +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT 0x00000010 + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT 0x00000000 +#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT 0x00000008 +#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT 0x00000010 +#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT 0x00000011 +#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT 0x00000012 +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT 0x00000013 +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT 0x00000014 +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT 0x00000018 +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT 0x0000001b +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT 0x0000001f + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT 0x00000000 +#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT 0x00000004 +#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT 0x00000008 +#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT 0x0000000c +#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT 0x00000010 +#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT 0x00000014 +#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT 0x00000018 +#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT 0x0000001c + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT 0x00000000 +#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT 0x00000004 +#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT 0x00000008 +#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT 0x0000000c +#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT 0x00000010 +#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT 0x00000014 +#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT 0x00000018 +#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT 0x0000001c + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE__SHIFT 0x00000000 +#define SQ_VS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE__SHIFT 0x00000000 +#define SQ_PS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT 0x00000000 +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT 0x00000001 +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT 0x00000002 +#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT 0x00000008 +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT 0x00000010 +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT 0x00000011 +#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT 0x00000012 + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE__SHIFT 0x00000000 + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT 0x00000004 +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT 0x00000018 + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT 0x00000001 +#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT 0x00000010 + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT 0x00000000 +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 +#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT 0x00000000 +#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT 0x00000003 +#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT 0x00000004 +#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT 0x00000007 +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT 0x00000008 + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID__SHIFT 0x00000000 +#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT 0x00000003 +#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT 0x00000004 +#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT 0x00000007 + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX__SHIFT 0x00000000 + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY__SHIFT 0x00000000 +#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT 0x00000001 +#define MH_DEBUG_REG00__CP_REQUEST__SHIFT 0x00000002 +#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT 0x00000003 +#define MH_DEBUG_REG00__TC_REQUEST__SHIFT 0x00000004 +#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT 0x00000005 +#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT 0x00000006 +#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG00__TCD_FULL__SHIFT 0x00000008 +#define MH_DEBUG_REG00__RB_REQUEST__SHIFT 0x00000009 +#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT 0x0000000a +#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT 0x0000000b +#define MH_DEBUG_REG00__ARQ_FULL__SHIFT 0x0000000c +#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG00__WDB_FULL__SHIFT 0x0000000e +#define MH_DEBUG_REG00__AXI_AVALID__SHIFT 0x0000000f +#define MH_DEBUG_REG00__AXI_AREADY__SHIFT 0x00000010 +#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT 0x00000011 +#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT 0x00000012 +#define MH_DEBUG_REG00__AXI_WVALID__SHIFT 0x00000013 +#define MH_DEBUG_REG00__AXI_WREADY__SHIFT 0x00000014 +#define MH_DEBUG_REG00__AXI_RVALID__SHIFT 0x00000015 +#define MH_DEBUG_REG00__AXI_RREADY__SHIFT 0x00000016 +#define MH_DEBUG_REG00__AXI_BVALID__SHIFT 0x00000017 +#define MH_DEBUG_REG00__AXI_BREADY__SHIFT 0x00000018 +#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT 0x00000019 +#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT 0x0000001a + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q__SHIFT 0x00000000 +#define MH_DEBUG_REG01__CP_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG01__CP_TAG_q__SHIFT 0x00000003 +#define MH_DEBUG_REG01__CP_BE_q__SHIFT 0x00000006 +#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT 0x0000000e +#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT 0x0000000f +#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT 0x00000010 +#define MH_DEBUG_REG01__TC_SEND_q__SHIFT 0x00000011 +#define MH_DEBUG_REG01__TC_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT 0x00000013 +#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT 0x00000014 +#define MH_DEBUG_REG01__TC_MH_written__SHIFT 0x00000015 +#define MH_DEBUG_REG01__RB_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG01__RB_RTR_q__SHIFT 0x00000017 +#define MH_DEBUG_REG01__RB_BE_q__SHIFT 0x00000018 + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT 0x00000003 +#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT 0x00000004 +#define MH_DEBUG_REG02__RDC_RID__SHIFT 0x00000007 +#define MH_DEBUG_REG02__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT 0x0000000c +#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT 0x0000000d +#define MH_DEBUG_REG02__BRC_BID__SHIFT 0x0000000e +#define MH_DEBUG_REG02__BRC_BRESP__SHIFT 0x00000011 + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG05__CP_MH_write__SHIFT 0x00000001 +#define MH_DEBUG_REG05__CP_MH_tag__SHIFT 0x00000002 +#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG08__VGT_MH_send__SHIFT 0x00000003 +#define MH_DEBUG_REG08__VGT_MH_tagbe__SHIFT 0x00000004 +#define MH_DEBUG_REG08__VGT_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG09__TC_MH_send__SHIFT 0x00000002 +#define MH_DEBUG_REG09__TC_MH_mask__SHIFT 0x00000003 +#define MH_DEBUG_REG09__TC_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__TC_MH_info__SHIFT 0x00000000 +#define MH_DEBUG_REG10__TC_MH_send__SHIFT 0x00000019 + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__MH_TC_mcinfo__SHIFT 0x00000000 +#define MH_DEBUG_REG11__MH_TC_mcinfo_send__SHIFT 0x00000019 +#define MH_DEBUG_REG11__TC_MH_written__SHIFT 0x0000001a + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG12__TC_ROQ_SEND__SHIFT 0x00000002 +#define MH_DEBUG_REG12__TC_ROQ_MASK__SHIFT 0x00000003 +#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__TC_ROQ_INFO__SHIFT 0x00000000 +#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT 0x00000019 + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG14__RB_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG14__RB_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__RB_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG17__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG17__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG17__ALEN_q_2_0__SHIFT 0x00000005 +#define MH_DEBUG_REG17__ARVALID_q__SHIFT 0x00000008 +#define MH_DEBUG_REG17__ARREADY_q__SHIFT 0x00000009 +#define MH_DEBUG_REG17__ARID_q__SHIFT 0x0000000a +#define MH_DEBUG_REG17__ARLEN_q_1_0__SHIFT 0x0000000d +#define MH_DEBUG_REG17__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG17__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG17__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG17__RID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG17__WVALID_q__SHIFT 0x00000015 +#define MH_DEBUG_REG17__WREADY_q__SHIFT 0x00000016 +#define MH_DEBUG_REG17__WLAST_q__SHIFT 0x00000017 +#define MH_DEBUG_REG17__WID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG17__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG17__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG17__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG18__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG18__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG18__ALEN_q_1_0__SHIFT 0x00000005 +#define MH_DEBUG_REG18__ARVALID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG18__ARREADY_q__SHIFT 0x00000008 +#define MH_DEBUG_REG18__ARID_q__SHIFT 0x00000009 +#define MH_DEBUG_REG18__ARLEN_q_1_1__SHIFT 0x0000000c +#define MH_DEBUG_REG18__WVALID_q__SHIFT 0x0000000d +#define MH_DEBUG_REG18__WREADY_q__SHIFT 0x0000000e +#define MH_DEBUG_REG18__WLAST_q__SHIFT 0x0000000f +#define MH_DEBUG_REG18__WID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG18__WSTRB_q__SHIFT 0x00000013 +#define MH_DEBUG_REG18__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG18__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG18__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__ARC_CTRL_RE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG19__CTRL_ARC_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG19__CTRL_ARC_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG20__REG_A__SHIFT 0x00000002 +#define MH_DEBUG_REG20__REG_RE__SHIFT 0x00000010 +#define MH_DEBUG_REG20__REG_WE__SHIFT 0x00000011 +#define MH_DEBUG_REG20__BLOCK_RS__SHIFT 0x00000012 + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__REG_WD__SHIFT 0x00000000 + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__CIB_MH_axi_halt_req__SHIFT 0x00000000 +#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack__SHIFT 0x00000001 +#define MH_DEBUG_REG22__MH_RBBM_busy__SHIFT 0x00000002 +#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int__SHIFT 0x00000003 +#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int__SHIFT 0x00000004 +#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int__SHIFT 0x00000005 +#define MH_DEBUG_REG22__GAT_CLK_ENA__SHIFT 0x00000006 +#define MH_DEBUG_REG22__AXI_RDY_ENA__SHIFT 0x00000007 +#define MH_DEBUG_REG22__RBBM_MH_clk_en_override__SHIFT 0x00000008 +#define MH_DEBUG_REG22__CNT_q__SHIFT 0x00000009 +#define MH_DEBUG_REG22__TCD_EMPTY_q__SHIFT 0x0000000f +#define MH_DEBUG_REG22__TC_ROQ_EMPTY__SHIFT 0x00000010 +#define MH_DEBUG_REG22__MH_BUSY_d__SHIFT 0x00000011 +#define MH_DEBUG_REG22__ANY_CLNT_BUSY__SHIFT 0x00000012 +#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000013 +#define MH_DEBUG_REG22__CP_SEND_q__SHIFT 0x00000014 +#define MH_DEBUG_REG22__CP_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG22__VGT_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG22__VGT_RTR_q__SHIFT 0x00000017 +#define MH_DEBUG_REG22__TC_ROQ_SEND_q__SHIFT 0x00000018 +#define MH_DEBUG_REG22__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG22__RB_SEND_q__SHIFT 0x0000001a +#define MH_DEBUG_REG22__RB_RTR_q__SHIFT 0x0000001b +#define MH_DEBUG_REG22__RDC_VALID__SHIFT 0x0000001c +#define MH_DEBUG_REG22__RDC_RLAST__SHIFT 0x0000001d +#define MH_DEBUG_REG22__TLBMISS_VALID__SHIFT 0x0000001e +#define MH_DEBUG_REG22__BRC_VALID__SHIFT 0x0000001f + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__EFF2_FP_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out__SHIFT 0x00000003 +#define MH_DEBUG_REG23__EFF1_WINNER__SHIFT 0x00000006 +#define MH_DEBUG_REG23__ARB_WINNER__SHIFT 0x00000009 +#define MH_DEBUG_REG23__ARB_WINNER_q__SHIFT 0x0000000c +#define MH_DEBUG_REG23__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG23__KILL_EFF1__SHIFT 0x00000010 +#define MH_DEBUG_REG23__ARB_HOLD__SHIFT 0x00000011 +#define MH_DEBUG_REG23__ARB_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG23__CP_SEND_QUAL__SHIFT 0x00000013 +#define MH_DEBUG_REG23__VGT_SEND_QUAL__SHIFT 0x00000014 +#define MH_DEBUG_REG23__TC_SEND_QUAL__SHIFT 0x00000015 +#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL__SHIFT 0x00000016 +#define MH_DEBUG_REG23__RB_SEND_QUAL__SHIFT 0x00000017 +#define MH_DEBUG_REG23__ARB_QUAL__SHIFT 0x00000018 +#define MH_DEBUG_REG23__CP_EFF1_REQ__SHIFT 0x00000019 +#define MH_DEBUG_REG23__VGT_EFF1_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG23__TC_EFF1_REQ__SHIFT 0x0000001b +#define MH_DEBUG_REG23__RB_EFF1_REQ__SHIFT 0x0000001c +#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK__SHIFT 0x0000001d +#define MH_DEBUG_REG23__TCD_NEARFULL_q__SHIFT 0x0000001e +#define MH_DEBUG_REG23__TCHOLD_IP_q__SHIFT 0x0000001f + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__EFF1_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG24__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG24__CP_SEND_QUAL__SHIFT 0x00000006 +#define MH_DEBUG_REG24__VGT_SEND_QUAL__SHIFT 0x00000007 +#define MH_DEBUG_REG24__TC_SEND_QUAL__SHIFT 0x00000008 +#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL__SHIFT 0x00000009 +#define MH_DEBUG_REG24__RB_SEND_QUAL__SHIFT 0x0000000a +#define MH_DEBUG_REG24__ARB_QUAL__SHIFT 0x0000000b +#define MH_DEBUG_REG24__CP_EFF1_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG24__VGT_EFF1_REQ__SHIFT 0x0000000d +#define MH_DEBUG_REG24__TC_EFF1_REQ__SHIFT 0x0000000e +#define MH_DEBUG_REG24__RB_EFF1_REQ__SHIFT 0x0000000f +#define MH_DEBUG_REG24__EFF1_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG24__KILL_EFF1__SHIFT 0x00000011 +#define MH_DEBUG_REG24__TCD_NEARFULL_q__SHIFT 0x00000012 +#define MH_DEBUG_REG24__TC_ARB_HOLD__SHIFT 0x00000013 +#define MH_DEBUG_REG24__ARB_HOLD__SHIFT 0x00000014 +#define MH_DEBUG_REG24__ARB_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q__SHIFT 0x00000016 + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out__SHIFT 0x00000000 +#define MH_DEBUG_REG25__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d__SHIFT 0x00000006 +#define MH_DEBUG_REG25__LEAST_RECENT_d__SHIFT 0x00000009 +#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d__SHIFT 0x0000000c +#define MH_DEBUG_REG25__ARB_HOLD__SHIFT 0x0000000d +#define MH_DEBUG_REG25__ARB_RTR_q__SHIFT 0x0000000e +#define MH_DEBUG_REG25__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG25__CLNT_REQ__SHIFT 0x00000010 +#define MH_DEBUG_REG25__RECENT_d_0__SHIFT 0x00000014 +#define MH_DEBUG_REG25__RECENT_d_1__SHIFT 0x00000017 +#define MH_DEBUG_REG25__RECENT_d_2__SHIFT 0x0000001a +#define MH_DEBUG_REG25__RECENT_d_3__SHIFT 0x0000001d + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__TC_ARB_HOLD__SHIFT 0x00000000 +#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK__SHIFT 0x00000001 +#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK__SHIFT 0x00000002 +#define MH_DEBUG_REG26__TCD_NEARFULL_q__SHIFT 0x00000003 +#define MH_DEBUG_REG26__TCHOLD_IP_q__SHIFT 0x00000004 +#define MH_DEBUG_REG26__TCHOLD_CNT_q__SHIFT 0x00000005 +#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008 +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG26__TC_MH_written__SHIFT 0x0000000b +#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG26__WBURST_ACTIVE__SHIFT 0x00000013 +#define MH_DEBUG_REG26__WLAST_q__SHIFT 0x00000014 +#define MH_DEBUG_REG26__WBURST_IP_q__SHIFT 0x00000015 +#define MH_DEBUG_REG26__WBURST_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG26__CP_SEND_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG26__CP_MH_write__SHIFT 0x0000001a +#define MH_DEBUG_REG26__RB_SEND_QUAL__SHIFT 0x0000001b +#define MH_DEBUG_REG26__ARB_WINNER__SHIFT 0x0000001c + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG28__ROQ_MARK_q__SHIFT 0x00000008 +#define MH_DEBUG_REG28__ROQ_VALID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG28__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG28__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG28__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG28__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG28__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG28__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG29__ROQ_MARK_d__SHIFT 0x00000008 +#define MH_DEBUG_REG29__ROQ_VALID_d__SHIFT 0x00000010 +#define MH_DEBUG_REG29__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG29__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG29__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG29__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG29__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG29__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN__SHIFT 0x00000000 +#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ__SHIFT 0x00000008 +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ__SHIFT 0x00000018 + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG31__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG31__ROQ_MARK_q_0__SHIFT 0x00000002 +#define MH_DEBUG_REG31__ROQ_VALID_q_0__SHIFT 0x00000003 +#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0__SHIFT 0x00000004 +#define MH_DEBUG_REG31__ROQ_ADDR_0__SHIFT 0x00000005 + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG32__ROQ_MARK_q_1__SHIFT 0x00000002 +#define MH_DEBUG_REG32__ROQ_VALID_q_1__SHIFT 0x00000003 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1__SHIFT 0x00000004 +#define MH_DEBUG_REG32__ROQ_ADDR_1__SHIFT 0x00000005 + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG33__ROQ_MARK_q_2__SHIFT 0x00000002 +#define MH_DEBUG_REG33__ROQ_VALID_q_2__SHIFT 0x00000003 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2__SHIFT 0x00000004 +#define MH_DEBUG_REG33__ROQ_ADDR_2__SHIFT 0x00000005 + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG34__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG34__ROQ_MARK_q_3__SHIFT 0x00000002 +#define MH_DEBUG_REG34__ROQ_VALID_q_3__SHIFT 0x00000003 +#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3__SHIFT 0x00000004 +#define MH_DEBUG_REG34__ROQ_ADDR_3__SHIFT 0x00000005 + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG35__ROQ_MARK_q_4__SHIFT 0x00000002 +#define MH_DEBUG_REG35__ROQ_VALID_q_4__SHIFT 0x00000003 +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4__SHIFT 0x00000004 +#define MH_DEBUG_REG35__ROQ_ADDR_4__SHIFT 0x00000005 + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG36__ROQ_MARK_q_5__SHIFT 0x00000002 +#define MH_DEBUG_REG36__ROQ_VALID_q_5__SHIFT 0x00000003 +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5__SHIFT 0x00000004 +#define MH_DEBUG_REG36__ROQ_ADDR_5__SHIFT 0x00000005 + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG37__ROQ_MARK_q_6__SHIFT 0x00000002 +#define MH_DEBUG_REG37__ROQ_VALID_q_6__SHIFT 0x00000003 +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6__SHIFT 0x00000004 +#define MH_DEBUG_REG37__ROQ_ADDR_6__SHIFT 0x00000005 + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG38__ROQ_MARK_q_7__SHIFT 0x00000002 +#define MH_DEBUG_REG38__ROQ_VALID_q_7__SHIFT 0x00000003 +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7__SHIFT 0x00000004 +#define MH_DEBUG_REG38__ROQ_ADDR_7__SHIFT 0x00000005 + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG39__MMU_RTR__SHIFT 0x00000001 +#define MH_DEBUG_REG39__ARB_ID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG39__ARB_WRITE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG39__ARB_BLEN_q__SHIFT 0x00000006 +#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q__SHIFT 0x00000008 +#define MH_DEBUG_REG39__MMU_WE__SHIFT 0x0000000b +#define MH_DEBUG_REG39__ARQ_RTR__SHIFT 0x0000000c +#define MH_DEBUG_REG39__MMU_ID__SHIFT 0x0000000d +#define MH_DEBUG_REG39__MMU_WRITE__SHIFT 0x00000010 +#define MH_DEBUG_REG39__MMU_BLEN__SHIFT 0x00000011 + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG40__ARB_ID_q__SHIFT 0x00000001 +#define MH_DEBUG_REG40__ARB_VAD_q__SHIFT 0x00000004 + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__MMU_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG41__MMU_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG41__MMU_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__WDB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG42__WDB_RTR_SKID__SHIFT 0x00000001 +#define MH_DEBUG_REG42__ARB_WSTRB_q__SHIFT 0x00000002 +#define MH_DEBUG_REG42__ARB_WLAST__SHIFT 0x0000000a +#define MH_DEBUG_REG42__WDB_CTRL_EMPTY__SHIFT 0x0000000b +#define MH_DEBUG_REG42__WDB_FIFO_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG42__WDC_WDB_RE_q__SHIFT 0x00000011 +#define MH_DEBUG_REG42__WDB_WDC_WID__SHIFT 0x00000012 +#define MH_DEBUG_REG42__WDB_WDC_WLAST__SHIFT 0x00000015 +#define MH_DEBUG_REG42__WDB_WDC_WSTRB__SHIFT 0x00000016 + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_WDATA_q_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WDATA_q_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__CTRL_ARC_EMPTY__SHIFT 0x00000000 +#define MH_DEBUG_REG47__CTRL_RARC_EMPTY__SHIFT 0x00000001 +#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY__SHIFT 0x00000002 +#define MH_DEBUG_REG47__ARQ_CTRL_WRITE__SHIFT 0x00000003 +#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS__SHIFT 0x00000004 +#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG47__INFLT_LIMIT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q__SHIFT 0x00000007 +#define MH_DEBUG_REG47__ARC_CTRL_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG47__RARC_CTRL_RE_q__SHIFT 0x0000000e +#define MH_DEBUG_REG47__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG47__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG47__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG47__BVALID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG47__BREADY_q__SHIFT 0x00000013 + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG48__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG48__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG48__MH_TLBMISS_SEND__SHIFT 0x00000003 +#define MH_DEBUG_REG48__TLBMISS_VALID__SHIFT 0x00000004 +#define MH_DEBUG_REG48__RDC_VALID__SHIFT 0x00000005 +#define MH_DEBUG_REG48__RDC_RID__SHIFT 0x00000006 +#define MH_DEBUG_REG48__RDC_RLAST__SHIFT 0x00000009 +#define MH_DEBUG_REG48__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS__SHIFT 0x0000000c +#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG48__MMU_ID_REQUEST_q__SHIFT 0x0000000e +#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q__SHIFT 0x0000000f +#define MH_DEBUG_REG48__MMU_ID_RESPONSE__SHIFT 0x00000015 +#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG48__CNT_HOLD_q1__SHIFT 0x0000001c +#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__RF_MMU_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG50__ARB_ID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG50__ARB_WRITE_q__SHIFT 0x0000001b +#define MH_DEBUG_REG50__client_behavior_q__SHIFT 0x0000001c +#define MH_DEBUG_REG50__ARB_WE__SHIFT 0x0000001e +#define MH_DEBUG_REG50__MMU_RTR__SHIFT 0x0000001f + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__stage1_valid__SHIFT 0x00000000 +#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q__SHIFT 0x00000001 +#define MH_DEBUG_REG51__pa_in_mpu_range__SHIFT 0x00000002 +#define MH_DEBUG_REG51__tag_match_q__SHIFT 0x00000003 +#define MH_DEBUG_REG51__tag_miss_q__SHIFT 0x00000004 +#define MH_DEBUG_REG51__va_in_range_q__SHIFT 0x00000005 +#define MH_DEBUG_REG51__MMU_MISS__SHIFT 0x00000006 +#define MH_DEBUG_REG51__MMU_READ_MISS__SHIFT 0x00000007 +#define MH_DEBUG_REG51__MMU_WRITE_MISS__SHIFT 0x00000008 +#define MH_DEBUG_REG51__MMU_HIT__SHIFT 0x00000009 +#define MH_DEBUG_REG51__MMU_READ_HIT__SHIFT 0x0000000a +#define MH_DEBUG_REG51__MMU_WRITE_HIT__SHIFT 0x0000000b +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS__SHIFT 0x0000000c +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT__SHIFT 0x0000000d +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS__SHIFT 0x0000000e +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT__SHIFT 0x0000000f +#define MH_DEBUG_REG51__REQ_VA_OFFSET_q__SHIFT 0x00000010 + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__ARQ_RTR__SHIFT 0x00000000 +#define MH_DEBUG_REG52__MMU_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS__SHIFT 0x00000003 +#define MH_DEBUG_REG52__MH_TLBMISS_SEND__SHIFT 0x00000004 +#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005 +#define MH_DEBUG_REG52__pa_in_mpu_range__SHIFT 0x00000006 +#define MH_DEBUG_REG52__stage1_valid__SHIFT 0x00000007 +#define MH_DEBUG_REG52__stage2_valid__SHIFT 0x00000008 +#define MH_DEBUG_REG52__client_behavior_q__SHIFT 0x00000009 +#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q__SHIFT 0x0000000b +#define MH_DEBUG_REG52__tag_match_q__SHIFT 0x0000000c +#define MH_DEBUG_REG52__tag_miss_q__SHIFT 0x0000000d +#define MH_DEBUG_REG52__va_in_range_q__SHIFT 0x0000000e +#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q__SHIFT 0x0000000f +#define MH_DEBUG_REG52__TAG_valid_q__SHIFT 0x00000010 + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__TAG0_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG53__TAG_valid_q_0__SHIFT 0x0000000d +#define MH_DEBUG_REG53__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG53__TAG1_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG53__TAG_valid_q_1__SHIFT 0x0000001d + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__TAG2_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG54__TAG_valid_q_2__SHIFT 0x0000000d +#define MH_DEBUG_REG54__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG54__TAG3_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG54__TAG_valid_q_3__SHIFT 0x0000001d + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG4_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG55__TAG_valid_q_4__SHIFT 0x0000000d +#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG55__TAG5_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG55__TAG_valid_q_5__SHIFT 0x0000001d + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG6_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG56__TAG_valid_q_6__SHIFT 0x0000000d +#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG56__TAG7_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG56__TAG_valid_q_7__SHIFT 0x0000001d + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG8_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG57__TAG_valid_q_8__SHIFT 0x0000000d +#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG57__TAG9_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG57__TAG_valid_q_9__SHIFT 0x0000001d + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG10_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG58__TAG_valid_q_10__SHIFT 0x0000000d +#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG58__TAG11_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG58__TAG_valid_q_11__SHIFT 0x0000001d + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG12_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG59__TAG_valid_q_12__SHIFT 0x0000000d +#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG59__TAG13_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG59__TAG_valid_q_13__SHIFT 0x0000001d + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG14_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG60__TAG_valid_q_14__SHIFT 0x0000000d +#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG60__TAG15_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG60__TAG_valid_q_15__SHIFT 0x0000001d + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT 0x00000000 +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT 0x00000001 +#define MH_MMU_CONFIG__RESERVED1__SHIFT 0x00000002 +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004 +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006 +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008 +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010 +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012 +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014 +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016 + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT 0x00000000 +#define MH_MMU_VA_RANGE__VA_BASE__SHIFT 0x0000000c + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE__SHIFT 0x0000000c + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT 0x00000000 +#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT 0x00000001 +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT 0x00000002 +#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT 0x00000004 +#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT 0x00000007 +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008 +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT 0x00000009 +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT 0x0000000a +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT 0x0000000b +#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT 0x0000000c + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT 0x00000005 + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT 0x00000000 +#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT 0x00000001 + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT 0x0000000c + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END__SHIFT 0x0000000c + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT 0x00000001 +#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT 0x00000002 +#define WAIT_UNTIL__WAIT_VSYNC__SHIFT 0x00000003 +#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT 0x00000004 +#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT 0x00000005 +#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT 0x00000006 +#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT 0x0000000a +#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT 0x0000000e +#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT 0x0000000f +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT 0x00000010 +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT 0x00000011 +#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT 0x00000014 + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT 0x00000004 +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT 0x00000005 + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0x00000000 +#define RBBM_STATUS__TC_BUSY__SHIFT 0x00000005 +#define RBBM_STATUS__HIRQ_PENDING__SHIFT 0x00000008 +#define RBBM_STATUS__CPRQ_PENDING__SHIFT 0x00000009 +#define RBBM_STATUS__CFRQ_PENDING__SHIFT 0x0000000a +#define RBBM_STATUS__PFRQ_PENDING__SHIFT 0x0000000b +#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT 0x0000000c +#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT 0x0000000e +#define RBBM_STATUS__CP_NRT_BUSY__SHIFT 0x00000010 +#define RBBM_STATUS__MH_BUSY__SHIFT 0x00000012 +#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT 0x00000013 +#define RBBM_STATUS__SX_BUSY__SHIFT 0x00000015 +#define RBBM_STATUS__TPC_BUSY__SHIFT 0x00000016 +#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT 0x00000018 +#define RBBM_STATUS__PA_BUSY__SHIFT 0x00000019 +#define RBBM_STATUS__VGT_BUSY__SHIFT 0x0000001a +#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT 0x0000001b +#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT 0x0000001c +#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT 0x0000001e +#define RBBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f + +// RBBM_DSPLY +#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE__SHIFT 0x00000000 +#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE__SHIFT 0x00000001 +#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE__SHIFT 0x00000002 +#define RBBM_DSPLY__VSYNC_ACTIVE__SHIFT 0x00000003 +#define RBBM_DSPLY__USE_DISPLAY_ID0__SHIFT 0x00000004 +#define RBBM_DSPLY__USE_DISPLAY_ID1__SHIFT 0x00000005 +#define RBBM_DSPLY__USE_DISPLAY_ID2__SHIFT 0x00000006 +#define RBBM_DSPLY__SW_CNTL__SHIFT 0x00000007 +#define RBBM_DSPLY__NUM_BUFS__SHIFT 0x00000008 + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__BUFFER_ID__SHIFT 0x00000000 + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT 0x00000000 + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT 0x00000000 +#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT 0x00000010 +#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT 0x00000018 + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT 0x00000000 + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT 0x00000000 + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT 0x00000000 +#define RBBM_PERIPHID1__DESIGNER0__SHIFT 0x00000004 + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1__SHIFT 0x00000000 +#define RBBM_PERIPHID2__REVISION__SHIFT 0x00000004 + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT 0x00000000 +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT 0x00000002 +#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT 0x00000004 +#define RBBM_PERIPHID3__CONTINUATION__SHIFT 0x00000007 + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT 0x00000008 + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 +#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000005 + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 +#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT 0x00000002 +#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT 0x00000003 +#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT 0x00000004 +#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT 0x00000005 +#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT 0x00000006 +#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT 0x0000000c +#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT 0x0000000f +#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT 0x00000010 + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010 +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011 +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012 +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013 +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT 0x00000014 +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000015 +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT 0x00000016 +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000017 +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018 +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT 0x00000019 +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001a +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT 0x0000001b +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT 0x0000001c +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001d +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT 0x0000001e +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT 0x0000000b + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT 0x00000000 +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT 0x0000001f + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT 0x00000000 + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR__SHIFT 0x00000001 +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT 0x00000002 +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT 0x00000003 +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT 0x00000004 +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT 0x00000008 +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT 0x00000010 +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000011 +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000012 +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000013 +#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT 0x00000014 +#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT 0x00000015 +#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT 0x00000016 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT 0x00000017 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT 0x00000018 +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT 0x0000001f + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT 0x0000001e +#define RBBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000 + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT 0x00000001 +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT 0x00000013 + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT 0x00000001 +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT 0x00000013 + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT 0x00000001 +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT 0x00000013 + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT 0x00000005 +#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT 0x0000001e +#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT 0x0000001f + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x00000005 + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT 0x00000002 + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE__SHIFT 0x00000002 + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE__SHIFT 0x00000002 + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE__SHIFT 0x00000002 + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT 0x00000008 +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT 0x00000010 + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT 0x00000010 +#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT 0x00000018 + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT 0x00000000 +#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT 0x00000008 +#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT 0x00000010 + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT 0x00000000 + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT 0x00000010 + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT 0x00000010 + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT 0x00000010 + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT 0x00000000 +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT 0x00000008 + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT 0x00000000 +#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT 0x00000010 + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT 0x00000000 +#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT 0x00000001 +#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT 0x00000002 +#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT 0x00000003 +#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT 0x00000004 +#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT 0x00000005 +#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT 0x00000006 +#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT 0x00000007 +#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT 0x00000008 +#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT 0x00000009 +#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT 0x0000000a +#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT 0x0000000b +#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT 0x0000000c +#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT 0x0000000d +#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT 0x0000000e +#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT 0x0000000f +#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT 0x00000010 +#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT 0x00000011 +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT 0x0000001f + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX__SHIFT 0x00000000 +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT 0x00000019 +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT 0x0000001a +#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c +#define CP_ME_CNTL__ME_BUSY__SHIFT 0x0000001d +#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT 0x0000001f + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT 0x00000000 + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR__SHIFT 0x00000000 + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT 0x00000000 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x00000017 +#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT 0x00000018 +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT 0x00000019 +#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT 0x0000001a +#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT 0x0000001b +#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT 0x0000001c +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT 0x0000001e +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT 0x0000001f + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT 0x00000000 +#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT 0x00000010 + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT 0x00000005 + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT 0x00000000 +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT 0x00000002 + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000 + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK__SHIFT 0x00000013 +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT 0x00000017 +#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT 0x00000018 +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT 0x00000019 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT 0x0000001a +#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT 0x0000001b +#define CP_INT_CNTL__IB2_INT_MASK__SHIFT 0x0000001d +#define CP_INT_CNTL__IB1_INT_MASK__SHIFT 0x0000001e +#define CP_INT_CNTL__RB_INT_MASK__SHIFT 0x0000001f + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT 0x00000019 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS__IB2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS__IB1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS__RB_INT_STAT__SHIFT 0x0000001f + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK__SHIFT 0x00000013 +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT 0x00000017 +#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT 0x00000018 +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT 0x00000019 +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT 0x0000001a +#define CP_INT_ACK__IB_ERROR_ACK__SHIFT 0x0000001b +#define CP_INT_ACK__IB2_INT_ACK__SHIFT 0x0000001d +#define CP_INT_ACK__IB1_INT_ACK__SHIFT 0x0000001e +#define CP_INT_ACK__RB_INT_ACK__SHIFT 0x0000001f + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT 0x00000000 + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT 0x00000000 + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT 0x00000000 + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT 0x00000000 + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT 0x00000000 + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT 0x00000000 + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT 0x00000000 + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0__SHIFT 0x00000000 +#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT 0x00000001 +#define CP_NV_FLAGS_0__DISCARD_1__SHIFT 0x00000002 +#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT 0x00000003 +#define CP_NV_FLAGS_0__DISCARD_2__SHIFT 0x00000004 +#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT 0x00000005 +#define CP_NV_FLAGS_0__DISCARD_3__SHIFT 0x00000006 +#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT 0x00000007 +#define CP_NV_FLAGS_0__DISCARD_4__SHIFT 0x00000008 +#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT 0x00000009 +#define CP_NV_FLAGS_0__DISCARD_5__SHIFT 0x0000000a +#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT 0x0000000b +#define CP_NV_FLAGS_0__DISCARD_6__SHIFT 0x0000000c +#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT 0x0000000d +#define CP_NV_FLAGS_0__DISCARD_7__SHIFT 0x0000000e +#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT 0x0000000f +#define CP_NV_FLAGS_0__DISCARD_8__SHIFT 0x00000010 +#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT 0x00000011 +#define CP_NV_FLAGS_0__DISCARD_9__SHIFT 0x00000012 +#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT 0x00000013 +#define CP_NV_FLAGS_0__DISCARD_10__SHIFT 0x00000014 +#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT 0x00000015 +#define CP_NV_FLAGS_0__DISCARD_11__SHIFT 0x00000016 +#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT 0x00000017 +#define CP_NV_FLAGS_0__DISCARD_12__SHIFT 0x00000018 +#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT 0x00000019 +#define CP_NV_FLAGS_0__DISCARD_13__SHIFT 0x0000001a +#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT 0x0000001b +#define CP_NV_FLAGS_0__DISCARD_14__SHIFT 0x0000001c +#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT 0x0000001d +#define CP_NV_FLAGS_0__DISCARD_15__SHIFT 0x0000001e +#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT 0x0000001f + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16__SHIFT 0x00000000 +#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT 0x00000001 +#define CP_NV_FLAGS_1__DISCARD_17__SHIFT 0x00000002 +#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT 0x00000003 +#define CP_NV_FLAGS_1__DISCARD_18__SHIFT 0x00000004 +#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT 0x00000005 +#define CP_NV_FLAGS_1__DISCARD_19__SHIFT 0x00000006 +#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT 0x00000007 +#define CP_NV_FLAGS_1__DISCARD_20__SHIFT 0x00000008 +#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT 0x00000009 +#define CP_NV_FLAGS_1__DISCARD_21__SHIFT 0x0000000a +#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT 0x0000000b +#define CP_NV_FLAGS_1__DISCARD_22__SHIFT 0x0000000c +#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT 0x0000000d +#define CP_NV_FLAGS_1__DISCARD_23__SHIFT 0x0000000e +#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT 0x0000000f +#define CP_NV_FLAGS_1__DISCARD_24__SHIFT 0x00000010 +#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT 0x00000011 +#define CP_NV_FLAGS_1__DISCARD_25__SHIFT 0x00000012 +#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT 0x00000013 +#define CP_NV_FLAGS_1__DISCARD_26__SHIFT 0x00000014 +#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT 0x00000015 +#define CP_NV_FLAGS_1__DISCARD_27__SHIFT 0x00000016 +#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT 0x00000017 +#define CP_NV_FLAGS_1__DISCARD_28__SHIFT 0x00000018 +#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT 0x00000019 +#define CP_NV_FLAGS_1__DISCARD_29__SHIFT 0x0000001a +#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT 0x0000001b +#define CP_NV_FLAGS_1__DISCARD_30__SHIFT 0x0000001c +#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT 0x0000001d +#define CP_NV_FLAGS_1__DISCARD_31__SHIFT 0x0000001e +#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT 0x0000001f + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32__SHIFT 0x00000000 +#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT 0x00000001 +#define CP_NV_FLAGS_2__DISCARD_33__SHIFT 0x00000002 +#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT 0x00000003 +#define CP_NV_FLAGS_2__DISCARD_34__SHIFT 0x00000004 +#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT 0x00000005 +#define CP_NV_FLAGS_2__DISCARD_35__SHIFT 0x00000006 +#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT 0x00000007 +#define CP_NV_FLAGS_2__DISCARD_36__SHIFT 0x00000008 +#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT 0x00000009 +#define CP_NV_FLAGS_2__DISCARD_37__SHIFT 0x0000000a +#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT 0x0000000b +#define CP_NV_FLAGS_2__DISCARD_38__SHIFT 0x0000000c +#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT 0x0000000d +#define CP_NV_FLAGS_2__DISCARD_39__SHIFT 0x0000000e +#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT 0x0000000f +#define CP_NV_FLAGS_2__DISCARD_40__SHIFT 0x00000010 +#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT 0x00000011 +#define CP_NV_FLAGS_2__DISCARD_41__SHIFT 0x00000012 +#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT 0x00000013 +#define CP_NV_FLAGS_2__DISCARD_42__SHIFT 0x00000014 +#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT 0x00000015 +#define CP_NV_FLAGS_2__DISCARD_43__SHIFT 0x00000016 +#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT 0x00000017 +#define CP_NV_FLAGS_2__DISCARD_44__SHIFT 0x00000018 +#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT 0x00000019 +#define CP_NV_FLAGS_2__DISCARD_45__SHIFT 0x0000001a +#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT 0x0000001b +#define CP_NV_FLAGS_2__DISCARD_46__SHIFT 0x0000001c +#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT 0x0000001d +#define CP_NV_FLAGS_2__DISCARD_47__SHIFT 0x0000001e +#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT 0x0000001f + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48__SHIFT 0x00000000 +#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT 0x00000001 +#define CP_NV_FLAGS_3__DISCARD_49__SHIFT 0x00000002 +#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT 0x00000003 +#define CP_NV_FLAGS_3__DISCARD_50__SHIFT 0x00000004 +#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT 0x00000005 +#define CP_NV_FLAGS_3__DISCARD_51__SHIFT 0x00000006 +#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT 0x00000007 +#define CP_NV_FLAGS_3__DISCARD_52__SHIFT 0x00000008 +#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT 0x00000009 +#define CP_NV_FLAGS_3__DISCARD_53__SHIFT 0x0000000a +#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT 0x0000000b +#define CP_NV_FLAGS_3__DISCARD_54__SHIFT 0x0000000c +#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT 0x0000000d +#define CP_NV_FLAGS_3__DISCARD_55__SHIFT 0x0000000e +#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT 0x0000000f +#define CP_NV_FLAGS_3__DISCARD_56__SHIFT 0x00000010 +#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT 0x00000011 +#define CP_NV_FLAGS_3__DISCARD_57__SHIFT 0x00000012 +#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT 0x00000013 +#define CP_NV_FLAGS_3__DISCARD_58__SHIFT 0x00000014 +#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT 0x00000015 +#define CP_NV_FLAGS_3__DISCARD_59__SHIFT 0x00000016 +#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT 0x00000017 +#define CP_NV_FLAGS_3__DISCARD_60__SHIFT 0x00000018 +#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT 0x00000019 +#define CP_NV_FLAGS_3__DISCARD_61__SHIFT 0x0000001a +#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT 0x0000001b +#define CP_NV_FLAGS_3__DISCARD_62__SHIFT 0x0000001c +#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT 0x0000001d +#define CP_NV_FLAGS_3__DISCARD_63__SHIFT 0x0000001e +#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT 0x0000001f + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT 0x00000000 + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT 0x00000000 + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER__SHIFT 0x00000000 + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY__SHIFT 0x00000000 +#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT 0x00000001 +#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT 0x00000002 +#define CP_STAT__RBIU_BUSY__SHIFT 0x00000003 +#define CP_STAT__RCIU_BUSY__SHIFT 0x00000004 +#define CP_STAT__CSF_RING_BUSY__SHIFT 0x00000005 +#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT 0x00000006 +#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x00000007 +#define CP_STAT__CSF_ST_BUSY__SHIFT 0x00000009 +#define CP_STAT__CSF_BUSY__SHIFT 0x0000000a +#define CP_STAT__RING_QUEUE_BUSY__SHIFT 0x0000000b +#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT 0x0000000c +#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT 0x0000000d +#define CP_STAT__ST_QUEUE_BUSY__SHIFT 0x00000010 +#define CP_STAT__PFP_BUSY__SHIFT 0x00000011 +#define CP_STAT__MEQ_RING_BUSY__SHIFT 0x00000012 +#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT 0x00000013 +#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT 0x00000014 +#define CP_STAT__MIU_WC_STALL__SHIFT 0x00000015 +#define CP_STAT__CP_NRT_BUSY__SHIFT 0x00000016 +#define CP_STAT___3D_BUSY__SHIFT 0x00000017 +#define CP_STAT__ME_BUSY__SHIFT 0x0000001a +#define CP_STAT__ME_WC_BUSY__SHIFT 0x0000001d +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT 0x0000001e +#define CP_STAT__CP_BUSY__SHIFT 0x0000001f + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE__SHIFT 0x00000000 + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE__SHIFT 0x00000000 + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_PM4__STATUS__SHIFT 0x0000001f + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE__SHIFT 0x00000000 + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE__SHIFT 0x00000000 + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_HOST__STATUS__SHIFT 0x0000001f + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT 0x0000000c + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT 0x0000000c + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT 0x0000000c + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT 0x0000000c + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT 0x0000000c + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT 0x0000000c + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT 0x0000000c + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT 0x0000000c + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT 0x00000000 +#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT 0x0000000e + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000 +#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT 0x00000004 +#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT 0x00000006 +#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT 0x00000007 +#define RB_COLOR_INFO__COLOR_SWAP__SHIFT 0x00000009 +#define RB_COLOR_INFO__COLOR_BASE__SHIFT 0x0000000c + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT 0x00000000 +#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT 0x0000000c + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF__SHIFT 0x00000000 +#define RB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 +#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF__SHIFT 0x00000000 + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED__SHIFT 0x00000000 +#define RB_COLOR_MASK__WRITE_GREEN__SHIFT 0x00000001 +#define RB_COLOR_MASK__WRITE_BLUE__SHIFT 0x00000002 +#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT 0x00000003 + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED__SHIFT 0x00000000 +#define RB_FOG_COLOR__FOG_GREEN__SHIFT 0x00000008 +#define RB_FOG_COLOR__FOG_BLUE__SHIFT 0x00000010 + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT 0x00000000 +#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT 0x00000000 +#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT 0x00000001 +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT 0x00000003 +#define RB_DEPTHCONTROL__ZFUNC__SHIFT 0x00000004 +#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 +#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT 0x00000008 +#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT 0x0000000b +#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT 0x0000000e +#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT 0x00000011 +#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT 0x00000014 +#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT 0x00000017 +#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT 0x0000001a +#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT 0x0000001d + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT 0x0000001d +#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT 0x0000001e + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT 0x00000000 +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT 0x00000003 +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000004 +#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT 0x00000005 +#define RB_COLORCONTROL__FOG_ENABLE__SHIFT 0x00000006 +#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT 0x00000007 +#define RB_COLORCONTROL__ROP_CODE__SHIFT 0x00000008 +#define RB_COLORCONTROL__DITHER_MODE__SHIFT 0x0000000c +#define RB_COLORCONTROL__DITHER_TYPE__SHIFT 0x0000000e +#define RB_COLORCONTROL__PIXEL_FOG__SHIFT 0x00000010 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000018 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000001a +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000001c +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000001e + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE__SHIFT 0x00000000 + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT 0x00000000 + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT 0x00000000 +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000003 +#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT 0x00000004 + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT 0x0000000c + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT 0x00000000 + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT 0x00000000 +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT 0x00000003 +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004 +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT 0x00000008 +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT 0x0000000a +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT 0x0000000c +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT 0x0000000e +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT 0x0000000f +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT 0x00000010 +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT 0x00000011 + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT 0x00000000 +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT 0x0000000d + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT 0x00000000 +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT 0x00000001 + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT 0x00000000 + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT 0x00000000 +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT 0x00000001 +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT 0x00000003 +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004 +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT 0x00000005 +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT 0x00000006 +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT 0x00000007 +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT 0x00000008 +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT 0x0000000e +#define RB_BC_CONTROL__CRC_MODE__SHIFT 0x0000000f +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT 0x00000010 +#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT 0x00000011 +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT 0x00000012 +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT 0x00000016 +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT 0x00000017 +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT 0x0000001b +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d +#define RB_BC_CONTROL__RESERVED9__SHIFT 0x0000001e +#define RB_BC_CONTROL__RESERVED10__SHIFT 0x0000001f + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT 0x00000000 +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004 +#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA__SHIFT 0x00000000 + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT 0x00000000 + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT 0x00000000 + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT 0x00000000 + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT 0x00000000 +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT 0x00000001 +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT 0x00000002 +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT 0x00000003 +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT 0x00000004 +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT 0x00000005 +#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT 0x00000006 +#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT 0x00000007 +#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT 0x00000008 +#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT 0x00000009 +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT 0x0000000a +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT 0x0000000b +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT 0x0000000c +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT 0x0000000d +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT 0x0000000e +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT 0x0000000f +#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT 0x00000010 +#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT 0x00000011 +#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT 0x00000012 +#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT 0x00000013 +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT 0x00000014 +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT 0x00000015 +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT 0x00000016 +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT 0x00000017 +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT 0x00000018 +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT 0x00000019 +#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT 0x0000001a +#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT 0x0000001b +#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT 0x0000001c +#define RB_DEBUG_0__C_REQ_FULL__SHIFT 0x0000001d +#define RB_DEBUG_0__C_MASK_FULL__SHIFT 0x0000001e +#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT 0x0000001f + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT 0x00000000 +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT 0x00000001 +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT 0x00000002 +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT 0x00000003 +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT 0x00000006 +#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT 0x00000007 +#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT 0x00000008 +#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT 0x00000009 +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT 0x0000000a +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT 0x0000000b +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT 0x0000000c +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT 0x0000000d +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT 0x0000000e +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT 0x0000000f +#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT 0x00000010 +#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT 0x00000011 +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT 0x00000012 +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT 0x00000013 +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT 0x00000000 +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT 0x00000004 +#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT 0x0000000b +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT 0x0000000c +#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT 0x0000000d +#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT 0x0000000e +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT 0x0000000f +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT 0x00000010 +#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT 0x00000011 +#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT 0x00000012 +#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT 0x00000013 +#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT 0x00000014 +#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT 0x00000015 +#define RB_DEBUG_2__Z_TILE_FULL__SHIFT 0x00000016 +#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID__SHIFT 0x00000000 +#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT 0x00000004 +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT 0x00000008 +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT 0x0000000e +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT 0x0000000f +#define RB_DEBUG_3__SHD_FULL__SHIFT 0x00000013 +#define RB_DEBUG_3__SHD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT 0x00000017 +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT 0x00000018 +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT 0x0000001b +#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT 0x0000001c + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT 0x00000000 +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT 0x00000001 +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT 0x00000002 +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT 0x00000003 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT 0x00000006 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT 0x00000007 +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT 0x00000008 +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT 0x00000009 + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT 0x00000000 + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT 0x00000009 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000 + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h new file mode 100644 index 000000000000..80b9106759e3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h @@ -0,0 +1,51301 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_CP_FIDDLE_H) +#define _CP_FIDDLE_H + + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * CP_RB_BASE struct + */ + +#define CP_RB_BASE_RB_BASE_SIZE 27 + +#define CP_RB_BASE_RB_BASE_SHIFT 5 + +#define CP_RB_BASE_RB_BASE_MASK 0xffffffe0 + +#define CP_RB_BASE_MASK \ + (CP_RB_BASE_RB_BASE_MASK) + +#define CP_RB_BASE(rb_base) \ + ((rb_base << CP_RB_BASE_RB_BASE_SHIFT)) + +#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \ + ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT) + +#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \ + cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int : 5; + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + } cp_rb_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + unsigned int : 5; + } cp_rb_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_base_t f; +} cp_rb_base_u; + + +/* + * CP_RB_CNTL struct + */ + +#define CP_RB_CNTL_RB_BUFSZ_SIZE 6 +#define CP_RB_CNTL_RB_BLKSZ_SIZE 6 +#define CP_RB_CNTL_BUF_SWAP_SIZE 2 +#define CP_RB_CNTL_RB_POLL_EN_SIZE 1 +#define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1 + +#define CP_RB_CNTL_RB_BUFSZ_SHIFT 0 +#define CP_RB_CNTL_RB_BLKSZ_SHIFT 8 +#define CP_RB_CNTL_BUF_SWAP_SHIFT 16 +#define CP_RB_CNTL_RB_POLL_EN_SHIFT 20 +#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT 27 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31 + +#define CP_RB_CNTL_RB_BUFSZ_MASK 0x0000003f +#define CP_RB_CNTL_RB_BLKSZ_MASK 0x00003f00 +#define CP_RB_CNTL_BUF_SWAP_MASK 0x00030000 +#define CP_RB_CNTL_RB_POLL_EN_MASK 0x00100000 +#define CP_RB_CNTL_RB_NO_UPDATE_MASK 0x08000000 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000 + +#define CP_RB_CNTL_MASK \ + (CP_RB_CNTL_RB_BUFSZ_MASK | \ + CP_RB_CNTL_RB_BLKSZ_MASK | \ + CP_RB_CNTL_BUF_SWAP_MASK | \ + CP_RB_CNTL_RB_POLL_EN_MASK | \ + CP_RB_CNTL_RB_NO_UPDATE_MASK | \ + CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) + +#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \ + ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \ + (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \ + (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \ + (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \ + (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \ + (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)) + +#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 6; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 3; + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + } cp_rb_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + unsigned int : 3; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 6; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + } cp_rb_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_cntl_t f; +} cp_rb_cntl_u; + + +/* + * CP_RB_RPTR_ADDR struct + */ + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc + +#define CP_RB_RPTR_ADDR_MASK \ + (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \ + CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) + +#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \ + ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \ + (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)) + +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + } cp_rb_rptr_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + } cp_rb_rptr_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_addr_t f; +} cp_rb_rptr_addr_u; + + +/* + * CP_RB_RPTR struct + */ + +#define CP_RB_RPTR_RB_RPTR_SIZE 20 + +#define CP_RB_RPTR_RB_RPTR_SHIFT 0 + +#define CP_RB_RPTR_RB_RPTR_MASK 0x000fffff + +#define CP_RB_RPTR_MASK \ + (CP_RB_RPTR_RB_RPTR_MASK) + +#define CP_RB_RPTR(rb_rptr) \ + ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)) + +#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \ + ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT) + +#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \ + cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + unsigned int : 12; + } cp_rb_rptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int : 12; + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + } cp_rb_rptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_t f; +} cp_rb_rptr_u; + + +/* + * CP_RB_RPTR_WR struct + */ + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE 20 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK 0x000fffff + +#define CP_RB_RPTR_WR_MASK \ + (CP_RB_RPTR_WR_RB_RPTR_WR_MASK) + +#define CP_RB_RPTR_WR(rb_rptr_wr) \ + ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)) + +#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \ + ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \ + cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + unsigned int : 12; + } cp_rb_rptr_wr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int : 12; + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + } cp_rb_rptr_wr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_wr_t f; +} cp_rb_rptr_wr_u; + + +/* + * CP_RB_WPTR struct + */ + +#define CP_RB_WPTR_RB_WPTR_SIZE 20 + +#define CP_RB_WPTR_RB_WPTR_SHIFT 0 + +#define CP_RB_WPTR_RB_WPTR_MASK 0x000fffff + +#define CP_RB_WPTR_MASK \ + (CP_RB_WPTR_RB_WPTR_MASK) + +#define CP_RB_WPTR(rb_wptr) \ + ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)) + +#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \ + ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT) + +#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \ + cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + unsigned int : 12; + } cp_rb_wptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int : 12; + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + } cp_rb_wptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_t f; +} cp_rb_wptr_u; + + +/* + * CP_RB_WPTR_DELAY struct + */ + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000 + +#define CP_RB_WPTR_DELAY_MASK \ + (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \ + CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) + +#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \ + ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \ + (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)) + +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + } cp_rb_wptr_delay_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + } cp_rb_wptr_delay_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_delay_t f; +} cp_rb_wptr_delay_u; + + +/* + * CP_RB_WPTR_BASE struct + */ + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc + +#define CP_RB_WPTR_BASE_MASK \ + (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \ + CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) + +#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \ + ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \ + (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)) + +#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + } cp_rb_wptr_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + } cp_rb_wptr_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_base_t f; +} cp_rb_wptr_base_u; + + +/* + * CP_IB1_BASE struct + */ + +#define CP_IB1_BASE_IB1_BASE_SIZE 30 + +#define CP_IB1_BASE_IB1_BASE_SHIFT 2 + +#define CP_IB1_BASE_IB1_BASE_MASK 0xfffffffc + +#define CP_IB1_BASE_MASK \ + (CP_IB1_BASE_IB1_BASE_MASK) + +#define CP_IB1_BASE(ib1_base) \ + ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)) + +#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \ + ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT) + +#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \ + cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int : 2; + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + } cp_ib1_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + unsigned int : 2; + } cp_ib1_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_base_t f; +} cp_ib1_base_u; + + +/* + * CP_IB1_BUFSZ struct + */ + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE 20 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT 0 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK 0x000fffff + +#define CP_IB1_BUFSZ_MASK \ + (CP_IB1_BUFSZ_IB1_BUFSZ_MASK) + +#define CP_IB1_BUFSZ(ib1_bufsz) \ + ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)) + +#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \ + ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \ + cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib1_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int : 12; + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + } cp_ib1_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_bufsz_t f; +} cp_ib1_bufsz_u; + + +/* + * CP_IB2_BASE struct + */ + +#define CP_IB2_BASE_IB2_BASE_SIZE 30 + +#define CP_IB2_BASE_IB2_BASE_SHIFT 2 + +#define CP_IB2_BASE_IB2_BASE_MASK 0xfffffffc + +#define CP_IB2_BASE_MASK \ + (CP_IB2_BASE_IB2_BASE_MASK) + +#define CP_IB2_BASE(ib2_base) \ + ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)) + +#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \ + ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT) + +#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \ + cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int : 2; + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + } cp_ib2_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + unsigned int : 2; + } cp_ib2_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_base_t f; +} cp_ib2_base_u; + + +/* + * CP_IB2_BUFSZ struct + */ + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE 20 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT 0 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK 0x000fffff + +#define CP_IB2_BUFSZ_MASK \ + (CP_IB2_BUFSZ_IB2_BUFSZ_MASK) + +#define CP_IB2_BUFSZ(ib2_bufsz) \ + ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)) + +#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \ + ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \ + cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib2_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int : 12; + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + } cp_ib2_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_bufsz_t f; +} cp_ib2_bufsz_u; + + +/* + * CP_ST_BASE struct + */ + +#define CP_ST_BASE_ST_BASE_SIZE 30 + +#define CP_ST_BASE_ST_BASE_SHIFT 2 + +#define CP_ST_BASE_ST_BASE_MASK 0xfffffffc + +#define CP_ST_BASE_MASK \ + (CP_ST_BASE_ST_BASE_MASK) + +#define CP_ST_BASE(st_base) \ + ((st_base << CP_ST_BASE_ST_BASE_SHIFT)) + +#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \ + ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT) + +#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \ + cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int : 2; + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + } cp_st_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + unsigned int : 2; + } cp_st_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_base_t f; +} cp_st_base_u; + + +/* + * CP_ST_BUFSZ struct + */ + +#define CP_ST_BUFSZ_ST_BUFSZ_SIZE 20 + +#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT 0 + +#define CP_ST_BUFSZ_ST_BUFSZ_MASK 0x000fffff + +#define CP_ST_BUFSZ_MASK \ + (CP_ST_BUFSZ_ST_BUFSZ_MASK) + +#define CP_ST_BUFSZ(st_bufsz) \ + ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)) + +#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \ + ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \ + cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + unsigned int : 12; + } cp_st_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int : 12; + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + } cp_st_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_bufsz_t f; +} cp_st_bufsz_u; + + +/* + * CP_QUEUE_THRESHOLDS struct + */ + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000 + +#define CP_QUEUE_THRESHOLDS_MASK \ + (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) + +#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \ + ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \ + (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \ + (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)) + +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 12; + } cp_queue_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int : 12; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + } cp_queue_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_queue_thresholds_t f; +} cp_queue_thresholds_u; + + +/* + * CP_MEQ_THRESHOLDS struct + */ + +#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5 +#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5 + +#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16 +#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24 + +#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000 +#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000 + +#define CP_MEQ_THRESHOLDS_MASK \ + (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \ + CP_MEQ_THRESHOLDS_ROQ_END_MASK) + +#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \ + ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \ + (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)) + +#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 16; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + } cp_meq_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 16; + } cp_meq_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_thresholds_t f; +} cp_meq_thresholds_u; + + +/* + * CP_CSQ_AVAIL struct + */ + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE 7 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK 0x00007f00 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK 0x007f0000 + +#define CP_CSQ_AVAIL_MASK \ + (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) + +#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \ + ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \ + (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \ + (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)) + +#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 9; + } cp_csq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int : 9; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + } cp_csq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_avail_t f; +} cp_csq_avail_u; + + +/* + * CP_STQ_AVAIL struct + */ + +#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE 7 + +#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT 0 + +#define CP_STQ_AVAIL_STQ_CNT_ST_MASK 0x0000007f + +#define CP_STQ_AVAIL_MASK \ + (CP_STQ_AVAIL_STQ_CNT_ST_MASK) + +#define CP_STQ_AVAIL(stq_cnt_st) \ + ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)) + +#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \ + ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \ + cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + unsigned int : 25; + } cp_stq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int : 25; + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + } cp_stq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_avail_t f; +} cp_stq_avail_u; + + +/* + * CP_MEQ_AVAIL struct + */ + +#define CP_MEQ_AVAIL_MEQ_CNT_SIZE 5 + +#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT 0 + +#define CP_MEQ_AVAIL_MEQ_CNT_MASK 0x0000001f + +#define CP_MEQ_AVAIL_MASK \ + (CP_MEQ_AVAIL_MEQ_CNT_MASK) + +#define CP_MEQ_AVAIL(meq_cnt) \ + ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)) + +#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \ + ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \ + cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + unsigned int : 27; + } cp_meq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int : 27; + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + } cp_meq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_avail_t f; +} cp_meq_avail_u; + + +/* + * CP_CSQ_RB_STAT struct + */ + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000 + +#define CP_CSQ_RB_STAT_MASK \ + (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \ + CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) + +#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \ + ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \ + (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)) + +#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + } cp_csq_rb_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + } cp_csq_rb_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_rb_stat_t f; +} cp_csq_rb_stat_u; + + +/* + * CP_CSQ_IB1_STAT struct + */ + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000 + +#define CP_CSQ_IB1_STAT_MASK \ + (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \ + CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) + +#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \ + ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \ + (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)) + +#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + } cp_csq_ib1_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + } cp_csq_ib1_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib1_stat_t f; +} cp_csq_ib1_stat_u; + + +/* + * CP_CSQ_IB2_STAT struct + */ + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000 + +#define CP_CSQ_IB2_STAT_MASK \ + (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \ + CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) + +#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \ + ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \ + (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)) + +#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + } cp_csq_ib2_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + } cp_csq_ib2_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib2_stat_t f; +} cp_csq_ib2_stat_u; + + +/* + * CP_NON_PREFETCH_CNTRS struct + */ + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700 + +#define CP_NON_PREFETCH_CNTRS_MASK \ + (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \ + CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) + +#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \ + ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \ + (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)) + +#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 21; + } cp_non_prefetch_cntrs_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int : 21; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + } cp_non_prefetch_cntrs_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_non_prefetch_cntrs_t f; +} cp_non_prefetch_cntrs_u; + + +/* + * CP_STQ_ST_STAT struct + */ + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f +#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000 + +#define CP_STQ_ST_STAT_MASK \ + (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \ + CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) + +#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \ + ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \ + (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)) + +#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + } cp_stq_st_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + } cp_stq_st_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_st_stat_t f; +} cp_stq_st_stat_u; + + +/* + * CP_MEQ_STAT struct + */ + +#define CP_MEQ_STAT_MEQ_RPTR_SIZE 10 +#define CP_MEQ_STAT_MEQ_WPTR_SIZE 10 + +#define CP_MEQ_STAT_MEQ_RPTR_SHIFT 0 +#define CP_MEQ_STAT_MEQ_WPTR_SHIFT 16 + +#define CP_MEQ_STAT_MEQ_RPTR_MASK 0x000003ff +#define CP_MEQ_STAT_MEQ_WPTR_MASK 0x03ff0000 + +#define CP_MEQ_STAT_MASK \ + (CP_MEQ_STAT_MEQ_RPTR_MASK | \ + CP_MEQ_STAT_MEQ_WPTR_MASK) + +#define CP_MEQ_STAT(meq_rptr, meq_wptr) \ + ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \ + (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)) + +#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + } cp_meq_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + } cp_meq_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_stat_t f; +} cp_meq_stat_u; + + +/* + * CP_MIU_TAG_STAT struct + */ + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001 +#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002 +#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004 +#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008 +#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010 +#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020 +#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040 +#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080 +#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100 +#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200 +#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400 +#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800 +#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000 +#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000 +#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000 +#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000 +#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000 +#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000 + +#define CP_MIU_TAG_STAT_MASK \ + (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \ + CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) + +#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \ + ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \ + (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \ + (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \ + (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \ + (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \ + (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \ + (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \ + (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \ + (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \ + (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \ + (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \ + (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \ + (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \ + (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \ + (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \ + (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \ + (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \ + (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \ + (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)) + +#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int : 13; + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + } cp_miu_tag_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + unsigned int : 13; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + } cp_miu_tag_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_miu_tag_stat_t f; +} cp_miu_tag_stat_u; + + +/* + * CP_CMD_INDEX struct + */ + +#define CP_CMD_INDEX_CMD_INDEX_SIZE 7 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2 + +#define CP_CMD_INDEX_CMD_INDEX_SHIFT 0 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16 + +#define CP_CMD_INDEX_CMD_INDEX_MASK 0x0000007f +#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000 + +#define CP_CMD_INDEX_MASK \ + (CP_CMD_INDEX_CMD_INDEX_MASK | \ + CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) + +#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \ + ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \ + (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)) + +#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + unsigned int : 9; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 14; + } cp_cmd_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int : 14; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 9; + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + } cp_cmd_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_index_t f; +} cp_cmd_index_u; + + +/* + * CP_CMD_DATA struct + */ + +#define CP_CMD_DATA_CMD_DATA_SIZE 32 + +#define CP_CMD_DATA_CMD_DATA_SHIFT 0 + +#define CP_CMD_DATA_CMD_DATA_MASK 0xffffffff + +#define CP_CMD_DATA_MASK \ + (CP_CMD_DATA_CMD_DATA_MASK) + +#define CP_CMD_DATA(cmd_data) \ + ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)) + +#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \ + ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT) + +#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \ + cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_data_t f; +} cp_cmd_data_u; + + +/* + * CP_ME_CNTL struct + */ + +#define CP_ME_CNTL_ME_STATMUX_SIZE 16 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_ME_HALT_SIZE 1 +#define CP_ME_CNTL_ME_BUSY_SIZE 1 +#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE 1 + +#define CP_ME_CNTL_ME_STATMUX_SHIFT 0 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26 +#define CP_ME_CNTL_ME_HALT_SHIFT 28 +#define CP_ME_CNTL_ME_BUSY_SHIFT 29 +#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31 + +#define CP_ME_CNTL_ME_STATMUX_MASK 0x0000ffff +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000 +#define CP_ME_CNTL_ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL_ME_BUSY_MASK 0x20000000 +#define CP_ME_CNTL_PROG_CNT_SIZE_MASK 0x80000000 + +#define CP_ME_CNTL_MASK \ + (CP_ME_CNTL_ME_STATMUX_MASK | \ + CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_ME_HALT_MASK | \ + CP_ME_CNTL_ME_BUSY_MASK | \ + CP_ME_CNTL_PROG_CNT_SIZE_MASK) + +#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \ + ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \ + (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \ + (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \ + (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)) + +#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + unsigned int : 9; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 1; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int : 1; + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + } cp_me_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + unsigned int : 1; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int : 1; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 9; + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + } cp_me_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cntl_t f; +} cp_me_cntl_u; + + +/* + * CP_ME_STATUS struct + */ + +#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32 + +#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0 + +#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff + +#define CP_ME_STATUS_MASK \ + (CP_ME_STATUS_ME_DEBUG_DATA_MASK) + +#define CP_ME_STATUS(me_debug_data) \ + ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)) + +#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \ + ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \ + cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_status_t f; +} cp_me_status_u; + + +/* + * CP_ME_RAM_WADDR struct + */ + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff + +#define CP_ME_RAM_WADDR_MASK \ + (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) + +#define CP_ME_RAM_WADDR(me_ram_waddr) \ + ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)) + +#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \ + ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \ + cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + unsigned int : 22; + } cp_me_ram_waddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int : 22; + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + } cp_me_ram_waddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_waddr_t f; +} cp_me_ram_waddr_u; + + +/* + * CP_ME_RAM_RADDR struct + */ + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff + +#define CP_ME_RAM_RADDR_MASK \ + (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) + +#define CP_ME_RAM_RADDR(me_ram_raddr) \ + ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)) + +#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \ + ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \ + cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + unsigned int : 22; + } cp_me_ram_raddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int : 22; + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + } cp_me_ram_raddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_raddr_t f; +} cp_me_ram_raddr_u; + + +/* + * CP_ME_RAM_DATA struct + */ + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff + +#define CP_ME_RAM_DATA_MASK \ + (CP_ME_RAM_DATA_ME_RAM_DATA_MASK) + +#define CP_ME_RAM_DATA(me_ram_data) \ + ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)) + +#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \ + ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \ + cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_data_t f; +} cp_me_ram_data_u; + + +/* + * CP_ME_RDADDR struct + */ + +#define CP_ME_RDADDR_ME_RDADDR_SIZE 32 + +#define CP_ME_RDADDR_ME_RDADDR_SHIFT 0 + +#define CP_ME_RDADDR_ME_RDADDR_MASK 0xffffffff + +#define CP_ME_RDADDR_MASK \ + (CP_ME_RDADDR_ME_RDADDR_MASK) + +#define CP_ME_RDADDR(me_rdaddr) \ + ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)) + +#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \ + ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \ + cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_rdaddr_t f; +} cp_me_rdaddr_u; + + +/* + * CP_DEBUG struct + */ + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23 +#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0 +#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff +#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000 +#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000 +#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000 + +#define CP_DEBUG_MASK \ + (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \ + CP_DEBUG_PREDICATE_DISABLE_MASK | \ + CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \ + CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \ + CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \ + CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \ + CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \ + CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \ + CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) + +#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \ + ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \ + (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \ + (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \ + (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \ + (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \ + (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \ + (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \ + (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \ + (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)) + +#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \ + ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \ + ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int : 1; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + } cp_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int : 1; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + } cp_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_debug_t f; +} cp_debug_u; + + +/* + * SCRATCH_REG0 struct + */ + +#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32 + +#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0 + +#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff + +#define SCRATCH_REG0_MASK \ + (SCRATCH_REG0_SCRATCH_REG0_MASK) + +#define SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)) + +#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \ + scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg0_t f; +} scratch_reg0_u; + + +/* + * SCRATCH_REG1 struct + */ + +#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32 + +#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0 + +#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff + +#define SCRATCH_REG1_MASK \ + (SCRATCH_REG1_SCRATCH_REG1_MASK) + +#define SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)) + +#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \ + scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg1_t f; +} scratch_reg1_u; + + +/* + * SCRATCH_REG2 struct + */ + +#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32 + +#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0 + +#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff + +#define SCRATCH_REG2_MASK \ + (SCRATCH_REG2_SCRATCH_REG2_MASK) + +#define SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)) + +#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \ + scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg2_t f; +} scratch_reg2_u; + + +/* + * SCRATCH_REG3 struct + */ + +#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32 + +#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0 + +#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff + +#define SCRATCH_REG3_MASK \ + (SCRATCH_REG3_SCRATCH_REG3_MASK) + +#define SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)) + +#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \ + scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg3_t f; +} scratch_reg3_u; + + +/* + * SCRATCH_REG4 struct + */ + +#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32 + +#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0 + +#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff + +#define SCRATCH_REG4_MASK \ + (SCRATCH_REG4_SCRATCH_REG4_MASK) + +#define SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)) + +#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \ + scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg4_t f; +} scratch_reg4_u; + + +/* + * SCRATCH_REG5 struct + */ + +#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32 + +#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0 + +#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff + +#define SCRATCH_REG5_MASK \ + (SCRATCH_REG5_SCRATCH_REG5_MASK) + +#define SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)) + +#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \ + scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg5_t f; +} scratch_reg5_u; + + +/* + * SCRATCH_REG6 struct + */ + +#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32 + +#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0 + +#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff + +#define SCRATCH_REG6_MASK \ + (SCRATCH_REG6_SCRATCH_REG6_MASK) + +#define SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)) + +#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \ + scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg6_t f; +} scratch_reg6_u; + + +/* + * SCRATCH_REG7 struct + */ + +#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32 + +#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0 + +#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff + +#define SCRATCH_REG7_MASK \ + (SCRATCH_REG7_SCRATCH_REG7_MASK) + +#define SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)) + +#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \ + scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg7_t f; +} scratch_reg7_u; + + +/* + * SCRATCH_UMSK struct + */ + +#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8 +#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2 + +#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0 +#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16 + +#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff +#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000 + +#define SCRATCH_UMSK_MASK \ + (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \ + SCRATCH_UMSK_SCRATCH_SWAP_MASK) + +#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \ + ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \ + (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)) + +#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + unsigned int : 8; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 14; + } scratch_umsk_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int : 14; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 8; + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + } scratch_umsk_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_umsk_t f; +} scratch_umsk_u; + + +/* + * SCRATCH_ADDR struct + */ + +#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27 + +#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5 + +#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0 + +#define SCRATCH_ADDR_MASK \ + (SCRATCH_ADDR_SCRATCH_ADDR_MASK) + +#define SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)) + +#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \ + scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int : 5; + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + } scratch_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + unsigned int : 5; + } scratch_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_addr_t f; +} scratch_addr_u; + + +/* + * CP_ME_VS_EVENT_SRC struct + */ + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_VS_EVENT_SRC_MASK \ + (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \ + CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) + +#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \ + ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \ + (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_vs_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int : 30; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + } cp_me_vs_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_src_t f; +} cp_me_vs_event_src_u; + + +/* + * CP_ME_VS_EVENT_ADDR struct + */ + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_MASK \ + (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \ + CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) + +#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \ + ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \ + (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + } cp_me_vs_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + } cp_me_vs_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_t f; +} cp_me_vs_event_addr_u; + + +/* + * CP_ME_VS_EVENT_DATA struct + */ + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_MASK \ + (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) + +#define CP_ME_VS_EVENT_DATA(vs_done_data) \ + ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \ + ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \ + cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_t f; +} cp_me_vs_event_data_u; + + +/* + * CP_ME_VS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_SWM_MASK \ + (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \ + CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) + +#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \ + ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \ + (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_swm_t f; +} cp_me_vs_event_addr_swm_u; + + +/* + * CP_ME_VS_EVENT_DATA_SWM struct + */ + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_SWM_MASK \ + (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) + +#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \ + ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \ + ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \ + cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_swm_t f; +} cp_me_vs_event_data_swm_u; + + +/* + * CP_ME_PS_EVENT_SRC struct + */ + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_PS_EVENT_SRC_MASK \ + (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \ + CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) + +#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \ + ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \ + (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)) + +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_ps_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int : 30; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + } cp_me_ps_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_src_t f; +} cp_me_ps_event_src_u; + + +/* + * CP_ME_PS_EVENT_ADDR struct + */ + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_MASK \ + (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \ + CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) + +#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \ + ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \ + (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + } cp_me_ps_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + } cp_me_ps_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_t f; +} cp_me_ps_event_addr_u; + + +/* + * CP_ME_PS_EVENT_DATA struct + */ + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_MASK \ + (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) + +#define CP_ME_PS_EVENT_DATA(ps_done_data) \ + ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \ + ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \ + cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_t f; +} cp_me_ps_event_data_u; + + +/* + * CP_ME_PS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_SWM_MASK \ + (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \ + CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) + +#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \ + ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \ + (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_swm_t f; +} cp_me_ps_event_addr_swm_u; + + +/* + * CP_ME_PS_EVENT_DATA_SWM struct + */ + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_SWM_MASK \ + (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) + +#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \ + ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \ + ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \ + cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_swm_t f; +} cp_me_ps_event_data_swm_u; + + +/* + * CP_ME_CF_EVENT_SRC struct + */ + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001 + +#define CP_ME_CF_EVENT_SRC_MASK \ + (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) + +#define CP_ME_CF_EVENT_SRC(cf_done_src) \ + ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)) + +#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \ + ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \ + cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + unsigned int : 31; + } cp_me_cf_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int : 31; + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + } cp_me_cf_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_src_t f; +} cp_me_cf_event_src_u; + + +/* + * CP_ME_CF_EVENT_ADDR struct + */ + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_CF_EVENT_ADDR_MASK \ + (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \ + CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) + +#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \ + ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \ + (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)) + +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + } cp_me_cf_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + } cp_me_cf_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_addr_t f; +} cp_me_cf_event_addr_u; + + +/* + * CP_ME_CF_EVENT_DATA struct + */ + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff + +#define CP_ME_CF_EVENT_DATA_MASK \ + (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) + +#define CP_ME_CF_EVENT_DATA(cf_done_data) \ + ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)) + +#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \ + ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \ + cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_data_t f; +} cp_me_cf_event_data_u; + + +/* + * CP_ME_NRT_ADDR struct + */ + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc + +#define CP_ME_NRT_ADDR_MASK \ + (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \ + CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) + +#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \ + ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \ + (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)) + +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + } cp_me_nrt_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + } cp_me_nrt_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_addr_t f; +} cp_me_nrt_addr_u; + + +/* + * CP_ME_NRT_DATA struct + */ + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff + +#define CP_ME_NRT_DATA_MASK \ + (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) + +#define CP_ME_NRT_DATA(nrt_write_data) \ + ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)) + +#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \ + ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \ + cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_data_t f; +} cp_me_nrt_data_u; + + +/* + * CP_ME_VS_FETCH_DONE_SRC struct + */ + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001 + +#define CP_ME_VS_FETCH_DONE_SRC_MASK \ + (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) + +#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \ + ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \ + ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \ + cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + unsigned int : 31; + } cp_me_vs_fetch_done_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int : 31; + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + } cp_me_vs_fetch_done_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_src_t f; +} cp_me_vs_fetch_done_src_u; + + +/* + * CP_ME_VS_FETCH_DONE_ADDR struct + */ + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_FETCH_DONE_ADDR_MASK \ + (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \ + CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) + +#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \ + ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \ + (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_addr_t f; +} cp_me_vs_fetch_done_addr_u; + + +/* + * CP_ME_VS_FETCH_DONE_DATA struct + */ + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_FETCH_DONE_DATA_MASK \ + (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) + +#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \ + ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \ + ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \ + cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_data_t f; +} cp_me_vs_fetch_done_data_u; + + +/* + * CP_INT_CNTL struct + */ + +#define CP_INT_CNTL_SW_INT_MASK_SIZE 1 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB2_INT_MASK_SIZE 1 +#define CP_INT_CNTL_IB1_INT_MASK_SIZE 1 +#define CP_INT_CNTL_RB_INT_MASK_SIZE 1 + +#define CP_INT_CNTL_SW_INT_MASK_SHIFT 19 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26 +#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27 +#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29 +#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30 +#define CP_INT_CNTL_RB_INT_MASK_SHIFT 31 + +#define CP_INT_CNTL_SW_INT_MASK_MASK 0x00080000 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000 +#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000 +#define CP_INT_CNTL_IB2_INT_MASK_MASK 0x20000000 +#define CP_INT_CNTL_IB1_INT_MASK_MASK 0x40000000 +#define CP_INT_CNTL_RB_INT_MASK_MASK 0x80000000 + +#define CP_INT_CNTL_MASK \ + (CP_INT_CNTL_SW_INT_MASK_MASK | \ + CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \ + CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB2_INT_MASK_MASK | \ + CP_INT_CNTL_IB1_INT_MASK_MASK | \ + CP_INT_CNTL_RB_INT_MASK_MASK) + +#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \ + ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \ + (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \ + (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \ + (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \ + (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \ + (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \ + (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \ + (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \ + (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)) + +#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int : 19; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int : 1; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + } cp_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int : 1; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int : 3; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 19; + } cp_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_cntl_t f; +} cp_int_cntl_u; + + +/* + * CP_INT_STATUS struct + */ + +#define CP_INT_STATUS_SW_INT_STAT_SIZE 1 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1 +#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1 +#define CP_INT_STATUS_RB_INT_STAT_SIZE 1 + +#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26 +#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27 +#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29 +#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30 +#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31 + +#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000 +#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000 +#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000 + +#define CP_INT_STATUS_MASK \ + (CP_INT_STATUS_SW_INT_STAT_MASK | \ + CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \ + CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB2_INT_STAT_MASK | \ + CP_INT_STATUS_IB1_INT_STAT_MASK | \ + CP_INT_STATUS_RB_INT_STAT_MASK) + +#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \ + ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \ + (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \ + (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \ + (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \ + (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \ + (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \ + (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \ + (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \ + (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)) + +#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int : 19; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int : 1; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + } cp_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int : 1; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int : 3; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 19; + } cp_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_status_t f; +} cp_int_status_u; + + +/* + * CP_INT_ACK struct + */ + +#define CP_INT_ACK_SW_INT_ACK_SIZE 1 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB2_INT_ACK_SIZE 1 +#define CP_INT_ACK_IB1_INT_ACK_SIZE 1 +#define CP_INT_ACK_RB_INT_ACK_SIZE 1 + +#define CP_INT_ACK_SW_INT_ACK_SHIFT 19 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26 +#define CP_INT_ACK_IB_ERROR_ACK_SHIFT 27 +#define CP_INT_ACK_IB2_INT_ACK_SHIFT 29 +#define CP_INT_ACK_IB1_INT_ACK_SHIFT 30 +#define CP_INT_ACK_RB_INT_ACK_SHIFT 31 + +#define CP_INT_ACK_SW_INT_ACK_MASK 0x00080000 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000 +#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000 +#define CP_INT_ACK_IB_ERROR_ACK_MASK 0x08000000 +#define CP_INT_ACK_IB2_INT_ACK_MASK 0x20000000 +#define CP_INT_ACK_IB1_INT_ACK_MASK 0x40000000 +#define CP_INT_ACK_RB_INT_ACK_MASK 0x80000000 + +#define CP_INT_ACK_MASK \ + (CP_INT_ACK_SW_INT_ACK_MASK | \ + CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \ + CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \ + CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \ + CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \ + CP_INT_ACK_IB_ERROR_ACK_MASK | \ + CP_INT_ACK_IB2_INT_ACK_MASK | \ + CP_INT_ACK_IB1_INT_ACK_MASK | \ + CP_INT_ACK_RB_INT_ACK_MASK) + +#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \ + ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \ + (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \ + (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \ + (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \ + (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \ + (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \ + (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \ + (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \ + (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)) + +#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT) + +#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int : 19; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int : 1; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + } cp_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int : 1; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int : 3; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 19; + } cp_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_ack_t f; +} cp_int_ack_u; + + +/* + * CP_PFP_UCODE_ADDR struct + */ + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff + +#define CP_PFP_UCODE_ADDR_MASK \ + (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) + +#define CP_PFP_UCODE_ADDR(ucode_addr) \ + ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)) + +#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \ + ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \ + cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + unsigned int : 23; + } cp_pfp_ucode_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int : 23; + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + } cp_pfp_ucode_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_addr_t f; +} cp_pfp_ucode_addr_u; + + +/* + * CP_PFP_UCODE_DATA struct + */ + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff + +#define CP_PFP_UCODE_DATA_MASK \ + (CP_PFP_UCODE_DATA_UCODE_DATA_MASK) + +#define CP_PFP_UCODE_DATA(ucode_data) \ + ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)) + +#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \ + ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \ + cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + unsigned int : 8; + } cp_pfp_ucode_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int : 8; + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + } cp_pfp_ucode_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_data_t f; +} cp_pfp_ucode_data_u; + + +/* + * CP_PERFMON_CNTL struct + */ + +#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2 + +#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8 + +#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300 + +#define CP_PERFMON_CNTL_MASK \ + (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \ + CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) + +#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \ + ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \ + (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)) + +#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + unsigned int : 4; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 22; + } cp_perfmon_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int : 22; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 4; + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + } cp_perfmon_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfmon_cntl_t f; +} cp_perfmon_cntl_u; + + +/* + * CP_PERFCOUNTER_SELECT struct + */ + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f + +#define CP_PERFCOUNTER_SELECT_MASK \ + (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) + +#define CP_PERFCOUNTER_SELECT(perfcount_sel) \ + ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)) + +#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \ + ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \ + cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + unsigned int : 26; + } cp_perfcounter_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int : 26; + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + } cp_perfcounter_select_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_select_t f; +} cp_perfcounter_select_u; + + +/* + * CP_PERFCOUNTER_LO struct + */ + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff + +#define CP_PERFCOUNTER_LO_MASK \ + (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) + +#define CP_PERFCOUNTER_LO(perfcount_lo) \ + ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)) + +#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \ + ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \ + cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_lo_t f; +} cp_perfcounter_lo_u; + + +/* + * CP_PERFCOUNTER_HI struct + */ + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff + +#define CP_PERFCOUNTER_HI_MASK \ + (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) + +#define CP_PERFCOUNTER_HI(perfcount_hi) \ + ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)) + +#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \ + ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \ + cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + unsigned int : 16; + } cp_perfcounter_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int : 16; + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + } cp_perfcounter_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_hi_t f; +} cp_perfcounter_hi_u; + + +/* + * CP_BIN_MASK_LO struct + */ + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff + +#define CP_BIN_MASK_LO_MASK \ + (CP_BIN_MASK_LO_BIN_MASK_LO_MASK) + +#define CP_BIN_MASK_LO(bin_mask_lo) \ + ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)) + +#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \ + ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \ + cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_lo_t f; +} cp_bin_mask_lo_u; + + +/* + * CP_BIN_MASK_HI struct + */ + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff + +#define CP_BIN_MASK_HI_MASK \ + (CP_BIN_MASK_HI_BIN_MASK_HI_MASK) + +#define CP_BIN_MASK_HI(bin_mask_hi) \ + ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)) + +#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \ + ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \ + cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_hi_t f; +} cp_bin_mask_hi_u; + + +/* + * CP_BIN_SELECT_LO struct + */ + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff + +#define CP_BIN_SELECT_LO_MASK \ + (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) + +#define CP_BIN_SELECT_LO(bin_select_lo) \ + ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)) + +#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \ + ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \ + cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_lo_t f; +} cp_bin_select_lo_u; + + +/* + * CP_BIN_SELECT_HI struct + */ + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff + +#define CP_BIN_SELECT_HI_MASK \ + (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) + +#define CP_BIN_SELECT_HI(bin_select_hi) \ + ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)) + +#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \ + ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \ + cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_hi_t f; +} cp_bin_select_hi_u; + + +/* + * CP_NV_FLAGS_0 struct + */ + +#define CP_NV_FLAGS_0_DISCARD_0_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_0_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_1_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_1_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_2_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_2_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_3_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_3_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_4_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_4_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_5_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_5_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_6_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_6_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_7_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_7_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_8_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_8_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_9_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_9_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_10_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_11_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_12_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_13_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_14_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_15_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1 + +#define CP_NV_FLAGS_0_DISCARD_0_SHIFT 0 +#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1 +#define CP_NV_FLAGS_0_DISCARD_1_SHIFT 2 +#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3 +#define CP_NV_FLAGS_0_DISCARD_2_SHIFT 4 +#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5 +#define CP_NV_FLAGS_0_DISCARD_3_SHIFT 6 +#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7 +#define CP_NV_FLAGS_0_DISCARD_4_SHIFT 8 +#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9 +#define CP_NV_FLAGS_0_DISCARD_5_SHIFT 10 +#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11 +#define CP_NV_FLAGS_0_DISCARD_6_SHIFT 12 +#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13 +#define CP_NV_FLAGS_0_DISCARD_7_SHIFT 14 +#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15 +#define CP_NV_FLAGS_0_DISCARD_8_SHIFT 16 +#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17 +#define CP_NV_FLAGS_0_DISCARD_9_SHIFT 18 +#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19 +#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20 +#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21 +#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22 +#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23 +#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24 +#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25 +#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26 +#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27 +#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28 +#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29 +#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30 +#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31 + +#define CP_NV_FLAGS_0_DISCARD_0_MASK 0x00000001 +#define CP_NV_FLAGS_0_END_RCVD_0_MASK 0x00000002 +#define CP_NV_FLAGS_0_DISCARD_1_MASK 0x00000004 +#define CP_NV_FLAGS_0_END_RCVD_1_MASK 0x00000008 +#define CP_NV_FLAGS_0_DISCARD_2_MASK 0x00000010 +#define CP_NV_FLAGS_0_END_RCVD_2_MASK 0x00000020 +#define CP_NV_FLAGS_0_DISCARD_3_MASK 0x00000040 +#define CP_NV_FLAGS_0_END_RCVD_3_MASK 0x00000080 +#define CP_NV_FLAGS_0_DISCARD_4_MASK 0x00000100 +#define CP_NV_FLAGS_0_END_RCVD_4_MASK 0x00000200 +#define CP_NV_FLAGS_0_DISCARD_5_MASK 0x00000400 +#define CP_NV_FLAGS_0_END_RCVD_5_MASK 0x00000800 +#define CP_NV_FLAGS_0_DISCARD_6_MASK 0x00001000 +#define CP_NV_FLAGS_0_END_RCVD_6_MASK 0x00002000 +#define CP_NV_FLAGS_0_DISCARD_7_MASK 0x00004000 +#define CP_NV_FLAGS_0_END_RCVD_7_MASK 0x00008000 +#define CP_NV_FLAGS_0_DISCARD_8_MASK 0x00010000 +#define CP_NV_FLAGS_0_END_RCVD_8_MASK 0x00020000 +#define CP_NV_FLAGS_0_DISCARD_9_MASK 0x00040000 +#define CP_NV_FLAGS_0_END_RCVD_9_MASK 0x00080000 +#define CP_NV_FLAGS_0_DISCARD_10_MASK 0x00100000 +#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000 +#define CP_NV_FLAGS_0_DISCARD_11_MASK 0x00400000 +#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000 +#define CP_NV_FLAGS_0_DISCARD_12_MASK 0x01000000 +#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000 +#define CP_NV_FLAGS_0_DISCARD_13_MASK 0x04000000 +#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000 +#define CP_NV_FLAGS_0_DISCARD_14_MASK 0x10000000 +#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000 +#define CP_NV_FLAGS_0_DISCARD_15_MASK 0x40000000 +#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000 + +#define CP_NV_FLAGS_0_MASK \ + (CP_NV_FLAGS_0_DISCARD_0_MASK | \ + CP_NV_FLAGS_0_END_RCVD_0_MASK | \ + CP_NV_FLAGS_0_DISCARD_1_MASK | \ + CP_NV_FLAGS_0_END_RCVD_1_MASK | \ + CP_NV_FLAGS_0_DISCARD_2_MASK | \ + CP_NV_FLAGS_0_END_RCVD_2_MASK | \ + CP_NV_FLAGS_0_DISCARD_3_MASK | \ + CP_NV_FLAGS_0_END_RCVD_3_MASK | \ + CP_NV_FLAGS_0_DISCARD_4_MASK | \ + CP_NV_FLAGS_0_END_RCVD_4_MASK | \ + CP_NV_FLAGS_0_DISCARD_5_MASK | \ + CP_NV_FLAGS_0_END_RCVD_5_MASK | \ + CP_NV_FLAGS_0_DISCARD_6_MASK | \ + CP_NV_FLAGS_0_END_RCVD_6_MASK | \ + CP_NV_FLAGS_0_DISCARD_7_MASK | \ + CP_NV_FLAGS_0_END_RCVD_7_MASK | \ + CP_NV_FLAGS_0_DISCARD_8_MASK | \ + CP_NV_FLAGS_0_END_RCVD_8_MASK | \ + CP_NV_FLAGS_0_DISCARD_9_MASK | \ + CP_NV_FLAGS_0_END_RCVD_9_MASK | \ + CP_NV_FLAGS_0_DISCARD_10_MASK | \ + CP_NV_FLAGS_0_END_RCVD_10_MASK | \ + CP_NV_FLAGS_0_DISCARD_11_MASK | \ + CP_NV_FLAGS_0_END_RCVD_11_MASK | \ + CP_NV_FLAGS_0_DISCARD_12_MASK | \ + CP_NV_FLAGS_0_END_RCVD_12_MASK | \ + CP_NV_FLAGS_0_DISCARD_13_MASK | \ + CP_NV_FLAGS_0_END_RCVD_13_MASK | \ + CP_NV_FLAGS_0_DISCARD_14_MASK | \ + CP_NV_FLAGS_0_END_RCVD_14_MASK | \ + CP_NV_FLAGS_0_DISCARD_15_MASK | \ + CP_NV_FLAGS_0_END_RCVD_15_MASK) + +#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \ + ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \ + (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \ + (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \ + (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \ + (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \ + (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \ + (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \ + (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \ + (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \ + (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \ + (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \ + (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \ + (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \ + (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \ + (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \ + (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \ + (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \ + (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \ + (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \ + (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \ + (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \ + (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \ + (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \ + (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \ + (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \ + (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \ + (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \ + (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \ + (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \ + (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \ + (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \ + (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)) + +#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + } cp_nv_flags_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + } cp_nv_flags_0_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_0_t f; +} cp_nv_flags_0_u; + + +/* + * CP_NV_FLAGS_1 struct + */ + +#define CP_NV_FLAGS_1_DISCARD_16_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_17_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_18_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_19_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_20_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_21_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_22_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_23_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_24_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_25_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_26_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_27_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_28_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_29_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_30_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_31_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1 + +#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0 +#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1 +#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2 +#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3 +#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4 +#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5 +#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6 +#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7 +#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8 +#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9 +#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10 +#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11 +#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12 +#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13 +#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14 +#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15 +#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16 +#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17 +#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18 +#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19 +#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20 +#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21 +#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22 +#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23 +#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24 +#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25 +#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26 +#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27 +#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28 +#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29 +#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30 +#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31 + +#define CP_NV_FLAGS_1_DISCARD_16_MASK 0x00000001 +#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002 +#define CP_NV_FLAGS_1_DISCARD_17_MASK 0x00000004 +#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008 +#define CP_NV_FLAGS_1_DISCARD_18_MASK 0x00000010 +#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020 +#define CP_NV_FLAGS_1_DISCARD_19_MASK 0x00000040 +#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080 +#define CP_NV_FLAGS_1_DISCARD_20_MASK 0x00000100 +#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200 +#define CP_NV_FLAGS_1_DISCARD_21_MASK 0x00000400 +#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800 +#define CP_NV_FLAGS_1_DISCARD_22_MASK 0x00001000 +#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000 +#define CP_NV_FLAGS_1_DISCARD_23_MASK 0x00004000 +#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000 +#define CP_NV_FLAGS_1_DISCARD_24_MASK 0x00010000 +#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000 +#define CP_NV_FLAGS_1_DISCARD_25_MASK 0x00040000 +#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000 +#define CP_NV_FLAGS_1_DISCARD_26_MASK 0x00100000 +#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000 +#define CP_NV_FLAGS_1_DISCARD_27_MASK 0x00400000 +#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000 +#define CP_NV_FLAGS_1_DISCARD_28_MASK 0x01000000 +#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000 +#define CP_NV_FLAGS_1_DISCARD_29_MASK 0x04000000 +#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000 +#define CP_NV_FLAGS_1_DISCARD_30_MASK 0x10000000 +#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000 +#define CP_NV_FLAGS_1_DISCARD_31_MASK 0x40000000 +#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000 + +#define CP_NV_FLAGS_1_MASK \ + (CP_NV_FLAGS_1_DISCARD_16_MASK | \ + CP_NV_FLAGS_1_END_RCVD_16_MASK | \ + CP_NV_FLAGS_1_DISCARD_17_MASK | \ + CP_NV_FLAGS_1_END_RCVD_17_MASK | \ + CP_NV_FLAGS_1_DISCARD_18_MASK | \ + CP_NV_FLAGS_1_END_RCVD_18_MASK | \ + CP_NV_FLAGS_1_DISCARD_19_MASK | \ + CP_NV_FLAGS_1_END_RCVD_19_MASK | \ + CP_NV_FLAGS_1_DISCARD_20_MASK | \ + CP_NV_FLAGS_1_END_RCVD_20_MASK | \ + CP_NV_FLAGS_1_DISCARD_21_MASK | \ + CP_NV_FLAGS_1_END_RCVD_21_MASK | \ + CP_NV_FLAGS_1_DISCARD_22_MASK | \ + CP_NV_FLAGS_1_END_RCVD_22_MASK | \ + CP_NV_FLAGS_1_DISCARD_23_MASK | \ + CP_NV_FLAGS_1_END_RCVD_23_MASK | \ + CP_NV_FLAGS_1_DISCARD_24_MASK | \ + CP_NV_FLAGS_1_END_RCVD_24_MASK | \ + CP_NV_FLAGS_1_DISCARD_25_MASK | \ + CP_NV_FLAGS_1_END_RCVD_25_MASK | \ + CP_NV_FLAGS_1_DISCARD_26_MASK | \ + CP_NV_FLAGS_1_END_RCVD_26_MASK | \ + CP_NV_FLAGS_1_DISCARD_27_MASK | \ + CP_NV_FLAGS_1_END_RCVD_27_MASK | \ + CP_NV_FLAGS_1_DISCARD_28_MASK | \ + CP_NV_FLAGS_1_END_RCVD_28_MASK | \ + CP_NV_FLAGS_1_DISCARD_29_MASK | \ + CP_NV_FLAGS_1_END_RCVD_29_MASK | \ + CP_NV_FLAGS_1_DISCARD_30_MASK | \ + CP_NV_FLAGS_1_END_RCVD_30_MASK | \ + CP_NV_FLAGS_1_DISCARD_31_MASK | \ + CP_NV_FLAGS_1_END_RCVD_31_MASK) + +#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \ + ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \ + (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \ + (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \ + (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \ + (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \ + (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \ + (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \ + (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \ + (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \ + (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \ + (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \ + (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \ + (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \ + (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \ + (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \ + (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \ + (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \ + (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \ + (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \ + (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \ + (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \ + (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \ + (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \ + (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \ + (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \ + (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \ + (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \ + (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \ + (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \ + (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \ + (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \ + (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)) + +#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + } cp_nv_flags_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + } cp_nv_flags_1_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_1_t f; +} cp_nv_flags_1_u; + + +/* + * CP_NV_FLAGS_2 struct + */ + +#define CP_NV_FLAGS_2_DISCARD_32_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_33_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_34_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_35_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_36_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_37_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_38_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_39_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_40_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_41_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_42_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_43_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_44_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_45_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_46_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_47_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1 + +#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0 +#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1 +#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2 +#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3 +#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4 +#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5 +#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6 +#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7 +#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8 +#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9 +#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10 +#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11 +#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12 +#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13 +#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14 +#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15 +#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16 +#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17 +#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18 +#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19 +#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20 +#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21 +#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22 +#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23 +#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24 +#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25 +#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26 +#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27 +#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28 +#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29 +#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30 +#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31 + +#define CP_NV_FLAGS_2_DISCARD_32_MASK 0x00000001 +#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002 +#define CP_NV_FLAGS_2_DISCARD_33_MASK 0x00000004 +#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008 +#define CP_NV_FLAGS_2_DISCARD_34_MASK 0x00000010 +#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020 +#define CP_NV_FLAGS_2_DISCARD_35_MASK 0x00000040 +#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080 +#define CP_NV_FLAGS_2_DISCARD_36_MASK 0x00000100 +#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200 +#define CP_NV_FLAGS_2_DISCARD_37_MASK 0x00000400 +#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800 +#define CP_NV_FLAGS_2_DISCARD_38_MASK 0x00001000 +#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000 +#define CP_NV_FLAGS_2_DISCARD_39_MASK 0x00004000 +#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000 +#define CP_NV_FLAGS_2_DISCARD_40_MASK 0x00010000 +#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000 +#define CP_NV_FLAGS_2_DISCARD_41_MASK 0x00040000 +#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000 +#define CP_NV_FLAGS_2_DISCARD_42_MASK 0x00100000 +#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000 +#define CP_NV_FLAGS_2_DISCARD_43_MASK 0x00400000 +#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000 +#define CP_NV_FLAGS_2_DISCARD_44_MASK 0x01000000 +#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000 +#define CP_NV_FLAGS_2_DISCARD_45_MASK 0x04000000 +#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000 +#define CP_NV_FLAGS_2_DISCARD_46_MASK 0x10000000 +#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000 +#define CP_NV_FLAGS_2_DISCARD_47_MASK 0x40000000 +#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000 + +#define CP_NV_FLAGS_2_MASK \ + (CP_NV_FLAGS_2_DISCARD_32_MASK | \ + CP_NV_FLAGS_2_END_RCVD_32_MASK | \ + CP_NV_FLAGS_2_DISCARD_33_MASK | \ + CP_NV_FLAGS_2_END_RCVD_33_MASK | \ + CP_NV_FLAGS_2_DISCARD_34_MASK | \ + CP_NV_FLAGS_2_END_RCVD_34_MASK | \ + CP_NV_FLAGS_2_DISCARD_35_MASK | \ + CP_NV_FLAGS_2_END_RCVD_35_MASK | \ + CP_NV_FLAGS_2_DISCARD_36_MASK | \ + CP_NV_FLAGS_2_END_RCVD_36_MASK | \ + CP_NV_FLAGS_2_DISCARD_37_MASK | \ + CP_NV_FLAGS_2_END_RCVD_37_MASK | \ + CP_NV_FLAGS_2_DISCARD_38_MASK | \ + CP_NV_FLAGS_2_END_RCVD_38_MASK | \ + CP_NV_FLAGS_2_DISCARD_39_MASK | \ + CP_NV_FLAGS_2_END_RCVD_39_MASK | \ + CP_NV_FLAGS_2_DISCARD_40_MASK | \ + CP_NV_FLAGS_2_END_RCVD_40_MASK | \ + CP_NV_FLAGS_2_DISCARD_41_MASK | \ + CP_NV_FLAGS_2_END_RCVD_41_MASK | \ + CP_NV_FLAGS_2_DISCARD_42_MASK | \ + CP_NV_FLAGS_2_END_RCVD_42_MASK | \ + CP_NV_FLAGS_2_DISCARD_43_MASK | \ + CP_NV_FLAGS_2_END_RCVD_43_MASK | \ + CP_NV_FLAGS_2_DISCARD_44_MASK | \ + CP_NV_FLAGS_2_END_RCVD_44_MASK | \ + CP_NV_FLAGS_2_DISCARD_45_MASK | \ + CP_NV_FLAGS_2_END_RCVD_45_MASK | \ + CP_NV_FLAGS_2_DISCARD_46_MASK | \ + CP_NV_FLAGS_2_END_RCVD_46_MASK | \ + CP_NV_FLAGS_2_DISCARD_47_MASK | \ + CP_NV_FLAGS_2_END_RCVD_47_MASK) + +#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \ + ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \ + (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \ + (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \ + (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \ + (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \ + (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \ + (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \ + (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \ + (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \ + (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \ + (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \ + (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \ + (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \ + (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \ + (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \ + (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \ + (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \ + (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \ + (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \ + (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \ + (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \ + (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \ + (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \ + (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \ + (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \ + (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \ + (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \ + (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \ + (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \ + (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \ + (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \ + (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)) + +#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + } cp_nv_flags_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + } cp_nv_flags_2_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_2_t f; +} cp_nv_flags_2_u; + + +/* + * CP_NV_FLAGS_3 struct + */ + +#define CP_NV_FLAGS_3_DISCARD_48_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_49_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_50_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_51_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_52_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_53_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_54_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_55_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_56_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_57_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_58_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_59_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_60_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_61_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_62_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_63_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1 + +#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0 +#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1 +#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2 +#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3 +#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4 +#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5 +#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6 +#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7 +#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8 +#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9 +#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10 +#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11 +#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12 +#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13 +#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14 +#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15 +#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16 +#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17 +#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18 +#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19 +#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20 +#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21 +#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22 +#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23 +#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24 +#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25 +#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26 +#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27 +#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28 +#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29 +#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30 +#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31 + +#define CP_NV_FLAGS_3_DISCARD_48_MASK 0x00000001 +#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002 +#define CP_NV_FLAGS_3_DISCARD_49_MASK 0x00000004 +#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008 +#define CP_NV_FLAGS_3_DISCARD_50_MASK 0x00000010 +#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020 +#define CP_NV_FLAGS_3_DISCARD_51_MASK 0x00000040 +#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080 +#define CP_NV_FLAGS_3_DISCARD_52_MASK 0x00000100 +#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200 +#define CP_NV_FLAGS_3_DISCARD_53_MASK 0x00000400 +#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800 +#define CP_NV_FLAGS_3_DISCARD_54_MASK 0x00001000 +#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000 +#define CP_NV_FLAGS_3_DISCARD_55_MASK 0x00004000 +#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000 +#define CP_NV_FLAGS_3_DISCARD_56_MASK 0x00010000 +#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000 +#define CP_NV_FLAGS_3_DISCARD_57_MASK 0x00040000 +#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000 +#define CP_NV_FLAGS_3_DISCARD_58_MASK 0x00100000 +#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000 +#define CP_NV_FLAGS_3_DISCARD_59_MASK 0x00400000 +#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000 +#define CP_NV_FLAGS_3_DISCARD_60_MASK 0x01000000 +#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000 +#define CP_NV_FLAGS_3_DISCARD_61_MASK 0x04000000 +#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000 +#define CP_NV_FLAGS_3_DISCARD_62_MASK 0x10000000 +#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000 +#define CP_NV_FLAGS_3_DISCARD_63_MASK 0x40000000 +#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000 + +#define CP_NV_FLAGS_3_MASK \ + (CP_NV_FLAGS_3_DISCARD_48_MASK | \ + CP_NV_FLAGS_3_END_RCVD_48_MASK | \ + CP_NV_FLAGS_3_DISCARD_49_MASK | \ + CP_NV_FLAGS_3_END_RCVD_49_MASK | \ + CP_NV_FLAGS_3_DISCARD_50_MASK | \ + CP_NV_FLAGS_3_END_RCVD_50_MASK | \ + CP_NV_FLAGS_3_DISCARD_51_MASK | \ + CP_NV_FLAGS_3_END_RCVD_51_MASK | \ + CP_NV_FLAGS_3_DISCARD_52_MASK | \ + CP_NV_FLAGS_3_END_RCVD_52_MASK | \ + CP_NV_FLAGS_3_DISCARD_53_MASK | \ + CP_NV_FLAGS_3_END_RCVD_53_MASK | \ + CP_NV_FLAGS_3_DISCARD_54_MASK | \ + CP_NV_FLAGS_3_END_RCVD_54_MASK | \ + CP_NV_FLAGS_3_DISCARD_55_MASK | \ + CP_NV_FLAGS_3_END_RCVD_55_MASK | \ + CP_NV_FLAGS_3_DISCARD_56_MASK | \ + CP_NV_FLAGS_3_END_RCVD_56_MASK | \ + CP_NV_FLAGS_3_DISCARD_57_MASK | \ + CP_NV_FLAGS_3_END_RCVD_57_MASK | \ + CP_NV_FLAGS_3_DISCARD_58_MASK | \ + CP_NV_FLAGS_3_END_RCVD_58_MASK | \ + CP_NV_FLAGS_3_DISCARD_59_MASK | \ + CP_NV_FLAGS_3_END_RCVD_59_MASK | \ + CP_NV_FLAGS_3_DISCARD_60_MASK | \ + CP_NV_FLAGS_3_END_RCVD_60_MASK | \ + CP_NV_FLAGS_3_DISCARD_61_MASK | \ + CP_NV_FLAGS_3_END_RCVD_61_MASK | \ + CP_NV_FLAGS_3_DISCARD_62_MASK | \ + CP_NV_FLAGS_3_END_RCVD_62_MASK | \ + CP_NV_FLAGS_3_DISCARD_63_MASK | \ + CP_NV_FLAGS_3_END_RCVD_63_MASK) + +#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \ + ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \ + (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \ + (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \ + (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \ + (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \ + (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \ + (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \ + (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \ + (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \ + (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \ + (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \ + (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \ + (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \ + (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \ + (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \ + (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \ + (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \ + (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \ + (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \ + (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \ + (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \ + (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \ + (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \ + (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \ + (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \ + (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \ + (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \ + (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \ + (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \ + (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \ + (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \ + (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)) + +#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + } cp_nv_flags_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + } cp_nv_flags_3_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_3_t f; +} cp_nv_flags_3_u; + + +/* + * CP_STATE_DEBUG_INDEX struct + */ + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f + +#define CP_STATE_DEBUG_INDEX_MASK \ + (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) + +#define CP_STATE_DEBUG_INDEX(state_debug_index) \ + ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)) + +#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \ + ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \ + cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + unsigned int : 27; + } cp_state_debug_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int : 27; + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + } cp_state_debug_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_index_t f; +} cp_state_debug_index_u; + + +/* + * CP_STATE_DEBUG_DATA struct + */ + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff + +#define CP_STATE_DEBUG_DATA_MASK \ + (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) + +#define CP_STATE_DEBUG_DATA(state_debug_data) \ + ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)) + +#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \ + ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \ + cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_data_t f; +} cp_state_debug_data_u; + + +/* + * CP_PROG_COUNTER struct + */ + +#define CP_PROG_COUNTER_COUNTER_SIZE 32 + +#define CP_PROG_COUNTER_COUNTER_SHIFT 0 + +#define CP_PROG_COUNTER_COUNTER_MASK 0xffffffff + +#define CP_PROG_COUNTER_MASK \ + (CP_PROG_COUNTER_COUNTER_MASK) + +#define CP_PROG_COUNTER(counter) \ + ((counter << CP_PROG_COUNTER_COUNTER_SHIFT)) + +#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \ + ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT) + +#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \ + cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_prog_counter_t f; +} cp_prog_counter_u; + + +/* + * CP_STAT struct + */ + +#define CP_STAT_MIU_WR_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_REQ_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1 +#define CP_STAT_RBIU_BUSY_SIZE 1 +#define CP_STAT_RCIU_BUSY_SIZE 1 +#define CP_STAT_CSF_RING_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_CSF_ST_BUSY_SIZE 1 +#define CP_STAT_CSF_BUSY_SIZE 1 +#define CP_STAT_RING_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1 +#define CP_STAT_ST_QUEUE_BUSY_SIZE 1 +#define CP_STAT_PFP_BUSY_SIZE 1 +#define CP_STAT_MEQ_RING_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_STALL_SIZE 1 +#define CP_STAT_CP_NRT_BUSY_SIZE 1 +#define CP_STAT__3D_BUSY_SIZE 1 +#define CP_STAT_ME_BUSY_SIZE 1 +#define CP_STAT_ME_WC_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1 +#define CP_STAT_CP_BUSY_SIZE 1 + +#define CP_STAT_MIU_WR_BUSY_SHIFT 0 +#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2 +#define CP_STAT_RBIU_BUSY_SHIFT 3 +#define CP_STAT_RCIU_BUSY_SHIFT 4 +#define CP_STAT_CSF_RING_BUSY_SHIFT 5 +#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6 +#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7 +#define CP_STAT_CSF_ST_BUSY_SHIFT 9 +#define CP_STAT_CSF_BUSY_SHIFT 10 +#define CP_STAT_RING_QUEUE_BUSY_SHIFT 11 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13 +#define CP_STAT_ST_QUEUE_BUSY_SHIFT 16 +#define CP_STAT_PFP_BUSY_SHIFT 17 +#define CP_STAT_MEQ_RING_BUSY_SHIFT 18 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20 +#define CP_STAT_MIU_WC_STALL_SHIFT 21 +#define CP_STAT_CP_NRT_BUSY_SHIFT 22 +#define CP_STAT__3D_BUSY_SHIFT 23 +#define CP_STAT_ME_BUSY_SHIFT 26 +#define CP_STAT_ME_WC_BUSY_SHIFT 29 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30 +#define CP_STAT_CP_BUSY_SHIFT 31 + +#define CP_STAT_MIU_WR_BUSY_MASK 0x00000001 +#define CP_STAT_MIU_RD_REQ_BUSY_MASK 0x00000002 +#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004 +#define CP_STAT_RBIU_BUSY_MASK 0x00000008 +#define CP_STAT_RCIU_BUSY_MASK 0x00000010 +#define CP_STAT_CSF_RING_BUSY_MASK 0x00000020 +#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040 +#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080 +#define CP_STAT_CSF_ST_BUSY_MASK 0x00000200 +#define CP_STAT_CSF_BUSY_MASK 0x00000400 +#define CP_STAT_RING_QUEUE_BUSY_MASK 0x00000800 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000 +#define CP_STAT_ST_QUEUE_BUSY_MASK 0x00010000 +#define CP_STAT_PFP_BUSY_MASK 0x00020000 +#define CP_STAT_MEQ_RING_BUSY_MASK 0x00040000 +#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000 +#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000 +#define CP_STAT_MIU_WC_STALL_MASK 0x00200000 +#define CP_STAT_CP_NRT_BUSY_MASK 0x00400000 +#define CP_STAT__3D_BUSY_MASK 0x00800000 +#define CP_STAT_ME_BUSY_MASK 0x04000000 +#define CP_STAT_ME_WC_BUSY_MASK 0x20000000 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000 +#define CP_STAT_CP_BUSY_MASK 0x80000000 + +#define CP_STAT_MASK \ + (CP_STAT_MIU_WR_BUSY_MASK | \ + CP_STAT_MIU_RD_REQ_BUSY_MASK | \ + CP_STAT_MIU_RD_RETURN_BUSY_MASK | \ + CP_STAT_RBIU_BUSY_MASK | \ + CP_STAT_RCIU_BUSY_MASK | \ + CP_STAT_CSF_RING_BUSY_MASK | \ + CP_STAT_CSF_INDIRECTS_BUSY_MASK | \ + CP_STAT_CSF_INDIRECT2_BUSY_MASK | \ + CP_STAT_CSF_ST_BUSY_MASK | \ + CP_STAT_CSF_BUSY_MASK | \ + CP_STAT_RING_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \ + CP_STAT_ST_QUEUE_BUSY_MASK | \ + CP_STAT_PFP_BUSY_MASK | \ + CP_STAT_MEQ_RING_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \ + CP_STAT_MIU_WC_STALL_MASK | \ + CP_STAT_CP_NRT_BUSY_MASK | \ + CP_STAT__3D_BUSY_MASK | \ + CP_STAT_ME_BUSY_MASK | \ + CP_STAT_ME_WC_BUSY_MASK | \ + CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \ + CP_STAT_CP_BUSY_MASK) + +#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \ + ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \ + (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \ + (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \ + (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \ + (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \ + (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \ + (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \ + (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \ + (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \ + (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \ + (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \ + (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \ + (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \ + (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \ + (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \ + (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \ + (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \ + (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \ + (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \ + (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \ + (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \ + (me_busy << CP_STAT_ME_BUSY_SHIFT) | \ + (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \ + (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \ + (cp_busy << CP_STAT_CP_BUSY_SHIFT)) + +#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_GET_RBIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_GET_RCIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_GET_CSF_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_PFP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_GET__3D_BUSY(cp_stat) \ + ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_GET_ME_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_GET_CP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT) + +#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + } cp_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + } cp_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stat_t f; +} cp_stat_u; + + +/* + * BIOS_0_SCRATCH struct + */ + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_0_SCRATCH_MASK \ + (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_0_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \ + ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \ + bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_0_scratch_t f; +} bios_0_scratch_u; + + +/* + * BIOS_1_SCRATCH struct + */ + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_1_SCRATCH_MASK \ + (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_1_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \ + ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \ + bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_1_scratch_t f; +} bios_1_scratch_u; + + +/* + * BIOS_2_SCRATCH struct + */ + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_2_SCRATCH_MASK \ + (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_2_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \ + ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \ + bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_2_scratch_t f; +} bios_2_scratch_u; + + +/* + * BIOS_3_SCRATCH struct + */ + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_3_SCRATCH_MASK \ + (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_3_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \ + ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \ + bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_3_scratch_t f; +} bios_3_scratch_u; + + +/* + * BIOS_4_SCRATCH struct + */ + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_4_SCRATCH_MASK \ + (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_4_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \ + ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \ + bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_4_scratch_t f; +} bios_4_scratch_u; + + +/* + * BIOS_5_SCRATCH struct + */ + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_5_SCRATCH_MASK \ + (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_5_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \ + ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \ + bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_5_scratch_t f; +} bios_5_scratch_u; + + +/* + * BIOS_6_SCRATCH struct + */ + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_6_SCRATCH_MASK \ + (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_6_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \ + ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \ + bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_6_scratch_t f; +} bios_6_scratch_u; + + +/* + * BIOS_7_SCRATCH struct + */ + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_7_SCRATCH_MASK \ + (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_7_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \ + ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \ + bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_7_scratch_t f; +} bios_7_scratch_u; + + +/* + * BIOS_8_SCRATCH struct + */ + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_8_SCRATCH_MASK \ + (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_8_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \ + ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \ + bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_8_scratch_t f; +} bios_8_scratch_u; + + +/* + * BIOS_9_SCRATCH struct + */ + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_9_SCRATCH_MASK \ + (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_9_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \ + ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \ + bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_9_scratch_t f; +} bios_9_scratch_u; + + +/* + * BIOS_10_SCRATCH struct + */ + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_10_SCRATCH_MASK \ + (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_10_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \ + ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \ + bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_10_scratch_t f; +} bios_10_scratch_u; + + +/* + * BIOS_11_SCRATCH struct + */ + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_11_SCRATCH_MASK \ + (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_11_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \ + ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \ + bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_11_scratch_t f; +} bios_11_scratch_u; + + +/* + * BIOS_12_SCRATCH struct + */ + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_12_SCRATCH_MASK \ + (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_12_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \ + ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \ + bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_12_scratch_t f; +} bios_12_scratch_u; + + +/* + * BIOS_13_SCRATCH struct + */ + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_13_SCRATCH_MASK \ + (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_13_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \ + ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \ + bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_13_scratch_t f; +} bios_13_scratch_u; + + +/* + * BIOS_14_SCRATCH struct + */ + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_14_SCRATCH_MASK \ + (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_14_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \ + ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \ + bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_14_scratch_t f; +} bios_14_scratch_u; + + +/* + * BIOS_15_SCRATCH struct + */ + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_15_SCRATCH_MASK \ + (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_15_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \ + ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \ + bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_15_scratch_t f; +} bios_15_scratch_u; + + +/* + * COHER_SIZE_PM4 struct + */ + +#define COHER_SIZE_PM4_SIZE_SIZE 32 + +#define COHER_SIZE_PM4_SIZE_SHIFT 0 + +#define COHER_SIZE_PM4_SIZE_MASK 0xffffffff + +#define COHER_SIZE_PM4_MASK \ + (COHER_SIZE_PM4_SIZE_MASK) + +#define COHER_SIZE_PM4(size) \ + ((size << COHER_SIZE_PM4_SIZE_SHIFT)) + +#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \ + ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT) + +#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \ + coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_pm4_t f; +} coher_size_pm4_u; + + +/* + * COHER_BASE_PM4 struct + */ + +#define COHER_BASE_PM4_BASE_SIZE 32 + +#define COHER_BASE_PM4_BASE_SHIFT 0 + +#define COHER_BASE_PM4_BASE_MASK 0xffffffff + +#define COHER_BASE_PM4_MASK \ + (COHER_BASE_PM4_BASE_MASK) + +#define COHER_BASE_PM4(base) \ + ((base << COHER_BASE_PM4_BASE_SHIFT)) + +#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \ + ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT) + +#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \ + coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_pm4_t f; +} coher_base_pm4_u; + + +/* + * COHER_STATUS_PM4 struct + */ + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_PM4_STATUS_SIZE 1 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_PM4_STATUS_SHIFT 31 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_PM4_STATUS_MASK 0x80000000 + +#define COHER_STATUS_PM4_MASK \ + (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \ + COHER_STATUS_PM4_STATUS_MASK) + +#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_PM4_STATUS_SHIFT)) + +#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT) + +#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int : 8; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + } coher_status_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 8; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + } coher_status_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_pm4_t f; +} coher_status_pm4_u; + + +/* + * COHER_SIZE_HOST struct + */ + +#define COHER_SIZE_HOST_SIZE_SIZE 32 + +#define COHER_SIZE_HOST_SIZE_SHIFT 0 + +#define COHER_SIZE_HOST_SIZE_MASK 0xffffffff + +#define COHER_SIZE_HOST_MASK \ + (COHER_SIZE_HOST_SIZE_MASK) + +#define COHER_SIZE_HOST(size) \ + ((size << COHER_SIZE_HOST_SIZE_SHIFT)) + +#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \ + ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT) + +#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \ + coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_host_t f; +} coher_size_host_u; + + +/* + * COHER_BASE_HOST struct + */ + +#define COHER_BASE_HOST_BASE_SIZE 32 + +#define COHER_BASE_HOST_BASE_SHIFT 0 + +#define COHER_BASE_HOST_BASE_MASK 0xffffffff + +#define COHER_BASE_HOST_MASK \ + (COHER_BASE_HOST_BASE_MASK) + +#define COHER_BASE_HOST(base) \ + ((base << COHER_BASE_HOST_BASE_SHIFT)) + +#define COHER_BASE_HOST_GET_BASE(coher_base_host) \ + ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT) + +#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \ + coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_host_t f; +} coher_base_host_u; + + +/* + * COHER_STATUS_HOST struct + */ + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_HOST_STATUS_SIZE 1 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_HOST_STATUS_SHIFT 31 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_HOST_STATUS_MASK 0x80000000 + +#define COHER_STATUS_HOST_MASK \ + (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \ + COHER_STATUS_HOST_STATUS_MASK) + +#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_HOST_STATUS_SHIFT)) + +#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT) + +#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int : 8; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + } coher_status_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 8; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + } coher_status_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_host_t f; +} coher_status_host_u; + + +/* + * COHER_DEST_BASE_0 struct + */ + +#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20 + +#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12 + +#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000 + +#define COHER_DEST_BASE_0_MASK \ + (COHER_DEST_BASE_0_DEST_BASE_0_MASK) + +#define COHER_DEST_BASE_0(dest_base_0) \ + ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)) + +#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \ + ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \ + coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int : 12; + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + } coher_dest_base_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + unsigned int : 12; + } coher_dest_base_0_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_0_t f; +} coher_dest_base_0_u; + + +/* + * COHER_DEST_BASE_1 struct + */ + +#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20 + +#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12 + +#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000 + +#define COHER_DEST_BASE_1_MASK \ + (COHER_DEST_BASE_1_DEST_BASE_1_MASK) + +#define COHER_DEST_BASE_1(dest_base_1) \ + ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)) + +#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \ + ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \ + coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int : 12; + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + } coher_dest_base_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + unsigned int : 12; + } coher_dest_base_1_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_1_t f; +} coher_dest_base_1_u; + + +/* + * COHER_DEST_BASE_2 struct + */ + +#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20 + +#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12 + +#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000 + +#define COHER_DEST_BASE_2_MASK \ + (COHER_DEST_BASE_2_DEST_BASE_2_MASK) + +#define COHER_DEST_BASE_2(dest_base_2) \ + ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)) + +#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \ + ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \ + coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int : 12; + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + } coher_dest_base_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + unsigned int : 12; + } coher_dest_base_2_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_2_t f; +} coher_dest_base_2_u; + + +/* + * COHER_DEST_BASE_3 struct + */ + +#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20 + +#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12 + +#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000 + +#define COHER_DEST_BASE_3_MASK \ + (COHER_DEST_BASE_3_DEST_BASE_3_MASK) + +#define COHER_DEST_BASE_3(dest_base_3) \ + ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)) + +#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \ + ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \ + coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int : 12; + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + } coher_dest_base_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + unsigned int : 12; + } coher_dest_base_3_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_3_t f; +} coher_dest_base_3_u; + + +/* + * COHER_DEST_BASE_4 struct + */ + +#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20 + +#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12 + +#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000 + +#define COHER_DEST_BASE_4_MASK \ + (COHER_DEST_BASE_4_DEST_BASE_4_MASK) + +#define COHER_DEST_BASE_4(dest_base_4) \ + ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)) + +#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \ + ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \ + coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int : 12; + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + } coher_dest_base_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + unsigned int : 12; + } coher_dest_base_4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_4_t f; +} coher_dest_base_4_u; + + +/* + * COHER_DEST_BASE_5 struct + */ + +#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20 + +#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12 + +#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000 + +#define COHER_DEST_BASE_5_MASK \ + (COHER_DEST_BASE_5_DEST_BASE_5_MASK) + +#define COHER_DEST_BASE_5(dest_base_5) \ + ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)) + +#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \ + ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \ + coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int : 12; + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + } coher_dest_base_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + unsigned int : 12; + } coher_dest_base_5_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_5_t f; +} coher_dest_base_5_u; + + +/* + * COHER_DEST_BASE_6 struct + */ + +#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20 + +#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12 + +#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000 + +#define COHER_DEST_BASE_6_MASK \ + (COHER_DEST_BASE_6_DEST_BASE_6_MASK) + +#define COHER_DEST_BASE_6(dest_base_6) \ + ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)) + +#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \ + ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \ + coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int : 12; + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + } coher_dest_base_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + unsigned int : 12; + } coher_dest_base_6_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_6_t f; +} coher_dest_base_6_u; + + +/* + * COHER_DEST_BASE_7 struct + */ + +#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20 + +#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12 + +#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000 + +#define COHER_DEST_BASE_7_MASK \ + (COHER_DEST_BASE_7_DEST_BASE_7_MASK) + +#define COHER_DEST_BASE_7(dest_base_7) \ + ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)) + +#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \ + ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \ + coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int : 12; + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + } coher_dest_base_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + unsigned int : 12; + } coher_dest_base_7_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_7_t f; +} coher_dest_base_7_u; + + +#endif + + +#if !defined (_RBBM_FIDDLE_H) +#define _RBBM_FIDDLE_H + +/***************************************************************************************************************** + * + * rbbm_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * WAIT_UNTIL struct + */ + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1 +#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2 +#define WAIT_UNTIL_WAIT_VSYNC_SHIFT 3 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6 +#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT 10 +#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT 14 +#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT 15 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK 0x00000002 +#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK 0x00000004 +#define WAIT_UNTIL_WAIT_VSYNC_MASK 0x00000008 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040 +#define WAIT_UNTIL_WAIT_CMDFIFO_MASK 0x00000400 +#define WAIT_UNTIL_WAIT_2D_IDLE_MASK 0x00004000 +#define WAIT_UNTIL_WAIT_3D_IDLE_MASK 0x00008000 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000 + +#define WAIT_UNTIL_MASK \ + (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \ + WAIT_UNTIL_WAIT_CMDFIFO_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \ + WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) + +#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \ + ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \ + (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \ + (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \ + (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \ + (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \ + (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \ + (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \ + (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \ + (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \ + (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \ + (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \ + (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)) + +#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \ + ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 1; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int : 2; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 8; + } wait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 8; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 2; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int : 1; + } wait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + wait_until_t f; +} wait_until_u; + + +/* + * RBBM_ISYNC_CNTL struct + */ + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020 + +#define RBBM_ISYNC_CNTL_MASK \ + (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \ + RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) + +#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \ + ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \ + (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)) + +#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 4; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int : 26; + } rbbm_isync_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 26; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int : 4; + } rbbm_isync_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_isync_cntl_t f; +} rbbm_isync_cntl_u; + + +/* + * RBBM_STATUS struct + */ + +#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5 +#define RBBM_STATUS_TC_BUSY_SIZE 1 +#define RBBM_STATUS_HIRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CPRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_PFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1 +#define RBBM_STATUS_RBBM_WU_BUSY_SIZE 1 +#define RBBM_STATUS_CP_NRT_BUSY_SIZE 1 +#define RBBM_STATUS_MH_BUSY_SIZE 1 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1 +#define RBBM_STATUS_SX_BUSY_SIZE 1 +#define RBBM_STATUS_TPC_BUSY_SIZE 1 +#define RBBM_STATUS_SC_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_PA_BUSY_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1 +#define RBBM_STATUS_RB_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_GUI_ACTIVE_SIZE 1 + +#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0 +#define RBBM_STATUS_TC_BUSY_SHIFT 5 +#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8 +#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9 +#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10 +#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12 +#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14 +#define RBBM_STATUS_CP_NRT_BUSY_SHIFT 16 +#define RBBM_STATUS_MH_BUSY_SHIFT 18 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19 +#define RBBM_STATUS_SX_BUSY_SHIFT 21 +#define RBBM_STATUS_TPC_BUSY_SHIFT 22 +#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24 +#define RBBM_STATUS_PA_BUSY_SHIFT 25 +#define RBBM_STATUS_VGT_BUSY_SHIFT 26 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28 +#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30 +#define RBBM_STATUS_GUI_ACTIVE_SHIFT 31 + +#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f +#define RBBM_STATUS_TC_BUSY_MASK 0x00000020 +#define RBBM_STATUS_HIRQ_PENDING_MASK 0x00000100 +#define RBBM_STATUS_CPRQ_PENDING_MASK 0x00000200 +#define RBBM_STATUS_CFRQ_PENDING_MASK 0x00000400 +#define RBBM_STATUS_PFRQ_PENDING_MASK 0x00000800 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000 +#define RBBM_STATUS_RBBM_WU_BUSY_MASK 0x00004000 +#define RBBM_STATUS_CP_NRT_BUSY_MASK 0x00010000 +#define RBBM_STATUS_MH_BUSY_MASK 0x00040000 +#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000 +#define RBBM_STATUS_SX_BUSY_MASK 0x00200000 +#define RBBM_STATUS_TPC_BUSY_MASK 0x00400000 +#define RBBM_STATUS_SC_CNTX_BUSY_MASK 0x01000000 +#define RBBM_STATUS_PA_BUSY_MASK 0x02000000 +#define RBBM_STATUS_VGT_BUSY_MASK 0x04000000 +#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000 +#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000 +#define RBBM_STATUS_RB_CNTX_BUSY_MASK 0x40000000 +#define RBBM_STATUS_GUI_ACTIVE_MASK 0x80000000 + +#define RBBM_STATUS_MASK \ + (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \ + RBBM_STATUS_TC_BUSY_MASK | \ + RBBM_STATUS_HIRQ_PENDING_MASK | \ + RBBM_STATUS_CPRQ_PENDING_MASK | \ + RBBM_STATUS_CFRQ_PENDING_MASK | \ + RBBM_STATUS_PFRQ_PENDING_MASK | \ + RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \ + RBBM_STATUS_RBBM_WU_BUSY_MASK | \ + RBBM_STATUS_CP_NRT_BUSY_MASK | \ + RBBM_STATUS_MH_BUSY_MASK | \ + RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \ + RBBM_STATUS_SX_BUSY_MASK | \ + RBBM_STATUS_TPC_BUSY_MASK | \ + RBBM_STATUS_SC_CNTX_BUSY_MASK | \ + RBBM_STATUS_PA_BUSY_MASK | \ + RBBM_STATUS_VGT_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \ + RBBM_STATUS_RB_CNTX_BUSY_MASK | \ + RBBM_STATUS_GUI_ACTIVE_MASK) + +#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \ + ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \ + (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \ + (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \ + (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \ + (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \ + (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \ + (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \ + (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \ + (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \ + (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \ + (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \ + (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \ + (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \ + (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \ + (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \ + (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \ + (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \ + (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \ + (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \ + (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)) + +#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int : 2; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int : 1; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int : 1; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int : 1; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + } rbbm_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int : 2; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + } rbbm_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_status_t f; +} rbbm_status_u; + + +/* + * RBBM_DSPLY struct + */ + +#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE 1 +#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE 1 +#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE 1 +#define RBBM_DSPLY_VSYNC_ACTIVE_SIZE 1 +#define RBBM_DSPLY_USE_DISPLAY_ID0_SIZE 1 +#define RBBM_DSPLY_USE_DISPLAY_ID1_SIZE 1 +#define RBBM_DSPLY_USE_DISPLAY_ID2_SIZE 1 +#define RBBM_DSPLY_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_NUM_BUFS_SIZE 2 + +#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT 0 +#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT 1 +#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT 2 +#define RBBM_DSPLY_VSYNC_ACTIVE_SHIFT 3 +#define RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT 4 +#define RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT 5 +#define RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT 6 +#define RBBM_DSPLY_SW_CNTL_SHIFT 7 +#define RBBM_DSPLY_NUM_BUFS_SHIFT 8 + +#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK 0x00000001 +#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK 0x00000002 +#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK 0x00000004 +#define RBBM_DSPLY_VSYNC_ACTIVE_MASK 0x00000008 +#define RBBM_DSPLY_USE_DISPLAY_ID0_MASK 0x00000010 +#define RBBM_DSPLY_USE_DISPLAY_ID1_MASK 0x00000020 +#define RBBM_DSPLY_USE_DISPLAY_ID2_MASK 0x00000040 +#define RBBM_DSPLY_SW_CNTL_MASK 0x00000080 +#define RBBM_DSPLY_NUM_BUFS_MASK 0x00000300 + +#define RBBM_DSPLY_MASK \ + (RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK | \ + RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK | \ + RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK | \ + RBBM_DSPLY_VSYNC_ACTIVE_MASK | \ + RBBM_DSPLY_USE_DISPLAY_ID0_MASK | \ + RBBM_DSPLY_USE_DISPLAY_ID1_MASK | \ + RBBM_DSPLY_USE_DISPLAY_ID2_MASK | \ + RBBM_DSPLY_SW_CNTL_MASK | \ + RBBM_DSPLY_NUM_BUFS_MASK) + +#define RBBM_DSPLY(display_id0_active, display_id1_active, display_id2_active, vsync_active, use_display_id0, use_display_id1, use_display_id2, sw_cntl, num_bufs) \ + ((display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) | \ + (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) | \ + (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) | \ + (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) | \ + (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) | \ + (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) | \ + (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) | \ + (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT) | \ + (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT)) + +#define RBBM_DSPLY_GET_DISPLAY_ID0_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_DISPLAY_ID1_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_DISPLAY_ID2_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_VSYNC_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_VSYNC_ACTIVE_MASK) >> RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_USE_DISPLAY_ID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID0_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) +#define RBBM_DSPLY_GET_USE_DISPLAY_ID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID1_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) +#define RBBM_DSPLY_GET_USE_DISPLAY_ID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID2_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) +#define RBBM_DSPLY_GET_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SW_CNTL_MASK) >> RBBM_DSPLY_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_NUM_BUFS_MASK) >> RBBM_DSPLY_NUM_BUFS_SHIFT) + +#define RBBM_DSPLY_SET_DISPLAY_ID0_ACTIVE(rbbm_dsply_reg, display_id0_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) | (display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_DISPLAY_ID1_ACTIVE(rbbm_dsply_reg, display_id1_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) | (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_DISPLAY_ID2_ACTIVE(rbbm_dsply_reg, display_id2_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) | (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_VSYNC_ACTIVE(rbbm_dsply_reg, vsync_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_VSYNC_ACTIVE_MASK) | (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_USE_DISPLAY_ID0(rbbm_dsply_reg, use_display_id0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID0_MASK) | (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) +#define RBBM_DSPLY_SET_USE_DISPLAY_ID1(rbbm_dsply_reg, use_display_id1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID1_MASK) | (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) +#define RBBM_DSPLY_SET_USE_DISPLAY_ID2(rbbm_dsply_reg, use_display_id2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID2_MASK) | (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) +#define RBBM_DSPLY_SET_SW_CNTL(rbbm_dsply_reg, sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SW_CNTL_MASK) | (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_NUM_BUFS(rbbm_dsply_reg, num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_NUM_BUFS_MASK) | (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int display_id0_active : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE; + unsigned int display_id1_active : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE; + unsigned int display_id2_active : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE; + unsigned int vsync_active : RBBM_DSPLY_VSYNC_ACTIVE_SIZE; + unsigned int use_display_id0 : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE; + unsigned int use_display_id1 : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE; + unsigned int use_display_id2 : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE; + unsigned int sw_cntl : RBBM_DSPLY_SW_CNTL_SIZE; + unsigned int num_bufs : RBBM_DSPLY_NUM_BUFS_SIZE; + unsigned int : 22; + } rbbm_dsply_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int : 22; + unsigned int num_bufs : RBBM_DSPLY_NUM_BUFS_SIZE; + unsigned int sw_cntl : RBBM_DSPLY_SW_CNTL_SIZE; + unsigned int use_display_id2 : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE; + unsigned int use_display_id1 : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE; + unsigned int use_display_id0 : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE; + unsigned int vsync_active : RBBM_DSPLY_VSYNC_ACTIVE_SIZE; + unsigned int display_id2_active : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE; + unsigned int display_id1_active : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE; + unsigned int display_id0_active : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE; + } rbbm_dsply_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_dsply_t f; +} rbbm_dsply_u; + + +/* + * RBBM_RENDER_LATEST struct + */ + +#define RBBM_RENDER_LATEST_BUFFER_ID_SIZE 2 + +#define RBBM_RENDER_LATEST_BUFFER_ID_SHIFT 0 + +#define RBBM_RENDER_LATEST_BUFFER_ID_MASK 0x00000003 + +#define RBBM_RENDER_LATEST_MASK \ + (RBBM_RENDER_LATEST_BUFFER_ID_MASK) + +#define RBBM_RENDER_LATEST(buffer_id) \ + ((buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT)) + +#define RBBM_RENDER_LATEST_GET_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_BUFFER_ID_SHIFT) + +#define RBBM_RENDER_LATEST_SET_BUFFER_ID(rbbm_render_latest_reg, buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_BUFFER_ID_MASK) | (buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int buffer_id : RBBM_RENDER_LATEST_BUFFER_ID_SIZE; + unsigned int : 30; + } rbbm_render_latest_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int : 30; + unsigned int buffer_id : RBBM_RENDER_LATEST_BUFFER_ID_SIZE; + } rbbm_render_latest_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_render_latest_t f; +} rbbm_render_latest_u; + + +/* + * RBBM_RTL_RELEASE struct + */ + +#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32 + +#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0 + +#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff + +#define RBBM_RTL_RELEASE_MASK \ + (RBBM_RTL_RELEASE_CHANGELIST_MASK) + +#define RBBM_RTL_RELEASE(changelist) \ + ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)) + +#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \ + ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \ + rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_rtl_release_t f; +} rbbm_rtl_release_u; + + +/* + * RBBM_PATCH_RELEASE struct + */ + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000 + +#define RBBM_PATCH_RELEASE_MASK \ + (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \ + RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \ + RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) + +#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \ + ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \ + (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \ + (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)) + +#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + } rbbm_patch_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + } rbbm_patch_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_patch_release_t f; +} rbbm_patch_release_u; + + +/* + * RBBM_AUXILIARY_CONFIG struct + */ + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff + +#define RBBM_AUXILIARY_CONFIG_MASK \ + (RBBM_AUXILIARY_CONFIG_RESERVED_MASK) + +#define RBBM_AUXILIARY_CONFIG(reserved) \ + ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)) + +#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \ + ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \ + rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_auxiliary_config_t f; +} rbbm_auxiliary_config_u; + + +/* + * RBBM_PERIPHID0 struct + */ + +#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8 + +#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0 + +#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff + +#define RBBM_PERIPHID0_MASK \ + (RBBM_PERIPHID0_PARTNUMBER0_MASK) + +#define RBBM_PERIPHID0(partnumber0) \ + ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)) + +#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \ + ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \ + rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + unsigned int : 24; + } rbbm_periphid0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int : 24; + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + } rbbm_periphid0_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid0_t f; +} rbbm_periphid0_u; + + +/* + * RBBM_PERIPHID1 struct + */ + +#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4 +#define RBBM_PERIPHID1_DESIGNER0_SIZE 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0 +#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f +#define RBBM_PERIPHID1_DESIGNER0_MASK 0x000000f0 + +#define RBBM_PERIPHID1_MASK \ + (RBBM_PERIPHID1_PARTNUMBER1_MASK | \ + RBBM_PERIPHID1_DESIGNER0_MASK) + +#define RBBM_PERIPHID1(partnumber1, designer0) \ + ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \ + (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)) + +#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int : 24; + } rbbm_periphid1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int : 24; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + } rbbm_periphid1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid1_t f; +} rbbm_periphid1_u; + + +/* + * RBBM_PERIPHID2 struct + */ + +#define RBBM_PERIPHID2_DESIGNER1_SIZE 4 +#define RBBM_PERIPHID2_REVISION_SIZE 4 + +#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0 +#define RBBM_PERIPHID2_REVISION_SHIFT 4 + +#define RBBM_PERIPHID2_DESIGNER1_MASK 0x0000000f +#define RBBM_PERIPHID2_REVISION_MASK 0x000000f0 + +#define RBBM_PERIPHID2_MASK \ + (RBBM_PERIPHID2_DESIGNER1_MASK | \ + RBBM_PERIPHID2_REVISION_MASK) + +#define RBBM_PERIPHID2(designer1, revision) \ + ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \ + (revision << RBBM_PERIPHID2_REVISION_SHIFT)) + +#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT) + +#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int : 24; + } rbbm_periphid2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int : 24; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + } rbbm_periphid2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid2_t f; +} rbbm_periphid2_u; + + +/* + * RBBM_PERIPHID3 struct + */ + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_CONTINUATION_SIZE 1 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4 +#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c +#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030 +#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080 + +#define RBBM_PERIPHID3_MASK \ + (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \ + RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \ + RBBM_PERIPHID3_MH_INTERFACE_MASK | \ + RBBM_PERIPHID3_CONTINUATION_MASK) + +#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \ + ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \ + (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \ + (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \ + (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)) + +#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int : 1; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 24; + } rbbm_periphid3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int : 24; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 1; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + } rbbm_periphid3_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid3_t f; +} rbbm_periphid3_u; + + +/* + * RBBM_CNTL struct + */ + +#define RBBM_CNTL_READ_TIMEOUT_SIZE 8 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9 + +#define RBBM_CNTL_READ_TIMEOUT_SHIFT 0 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8 + +#define RBBM_CNTL_READ_TIMEOUT_MASK 0x000000ff +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00 + +#define RBBM_CNTL_MASK \ + (RBBM_CNTL_READ_TIMEOUT_MASK | \ + RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) + +#define RBBM_CNTL(read_timeout, regclk_deassert_time) \ + ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \ + (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)) + +#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int : 15; + } rbbm_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int : 15; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + } rbbm_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_cntl_t f; +} rbbm_cntl_u; + + +/* + * RBBM_SKEW_CNTL struct + */ + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f +#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0 + +#define RBBM_SKEW_CNTL_MASK \ + (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \ + RBBM_SKEW_CNTL_SKEW_COUNT_MASK) + +#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \ + ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \ + (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)) + +#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int : 22; + } rbbm_skew_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int : 22; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + } rbbm_skew_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_skew_cntl_t f; +} rbbm_skew_cntl_u; + + +/* + * RBBM_SOFT_RESET struct + */ + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000 + +#define RBBM_SOFT_RESET_MASK \ + (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) + +#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \ + ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \ + (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \ + (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \ + (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \ + (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \ + (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \ + (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \ + (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \ + (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)) + +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + unsigned int : 1; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int : 5; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 2; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int : 15; + } rbbm_soft_reset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int : 15; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int : 2; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 5; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int : 1; + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + } rbbm_soft_reset_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_soft_reset_t f; +} rbbm_soft_reset_u; + + +/* + * RBBM_PM_OVERRIDE1 struct + */ + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000 + +#define RBBM_PM_OVERRIDE1_MASK \ + (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \ + ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \ + (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override1_t f; +} rbbm_pm_override1_u; + + +/* + * RBBM_PM_OVERRIDE2 struct + */ + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800 + +#define RBBM_PM_OVERRIDE2_MASK \ + (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \ + ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \ + (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \ + (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int : 20; + } rbbm_pm_override2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int : 20; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override2_t f; +} rbbm_pm_override2_u; + + +/* + * GC_SYS_IDLE struct + */ + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000 + +#define GC_SYS_IDLE_MASK \ + (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \ + GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) + +#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_idle_override) \ + ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \ + (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)) + +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + unsigned int : 15; + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + } gc_sys_idle_t; + +#else // !BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + unsigned int : 15; + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + } gc_sys_idle_t; + +#endif + +typedef union { + unsigned int val : 32; + gc_sys_idle_t f; +} gc_sys_idle_u; + + +/* + * NQWAIT_UNTIL struct + */ + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001 + +#define NQWAIT_UNTIL_MASK \ + (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) + +#define NQWAIT_UNTIL(wait_gui_idle) \ + ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)) + +#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \ + ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \ + nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + unsigned int : 31; + } nqwait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int : 31; + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + } nqwait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + nqwait_until_t f; +} nqwait_until_u; + + +/* + * RBBM_DEBUG struct + */ + +#define RBBM_DEBUG_IGNORE_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1 + +#define RBBM_DEBUG_IGNORE_RTR_SHIFT 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31 + +#define RBBM_DEBUG_IGNORE_RTR_MASK 0x00000002 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000 + +#define RBBM_DEBUG_MASK \ + (RBBM_DEBUG_IGNORE_RTR_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \ + RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \ + RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \ + RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) + +#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \ + ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \ + (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \ + (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \ + (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \ + (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \ + (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \ + (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \ + (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \ + (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \ + (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \ + (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \ + (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)) + +#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int : 1; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int : 3; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 4; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int : 6; + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + } rbbm_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + unsigned int : 6; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int : 4; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 3; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int : 1; + } rbbm_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_t f; +} rbbm_debug_u; + + +/* + * RBBM_READ_ERROR struct + */ + +#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15 +#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1 +#define RBBM_READ_ERROR_READ_ERROR_SIZE 1 + +#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2 +#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30 +#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31 + +#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc +#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000 +#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000 + +#define RBBM_READ_ERROR_MASK \ + (RBBM_READ_ERROR_READ_ADDRESS_MASK | \ + RBBM_READ_ERROR_READ_REQUESTER_MASK | \ + RBBM_READ_ERROR_READ_ERROR_MASK) + +#define RBBM_READ_ERROR(read_address, read_requester, read_error) \ + ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \ + (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \ + (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)) + +#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int : 2; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 13; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + } rbbm_read_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int : 13; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 2; + } rbbm_read_error_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_read_error_t f; +} rbbm_read_error_u; + + +/* + * RBBM_WAIT_IDLE_CLOCKS struct + */ + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff + +#define RBBM_WAIT_IDLE_CLOCKS_MASK \ + (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) + +#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \ + ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)) + +#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \ + ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \ + rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + unsigned int : 24; + } rbbm_wait_idle_clocks_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int : 24; + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + } rbbm_wait_idle_clocks_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_wait_idle_clocks_t f; +} rbbm_wait_idle_clocks_u; + + +/* + * RBBM_INT_CNTL struct + */ + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000 + +#define RBBM_INT_CNTL_MASK \ + (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \ + RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \ + RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) + +#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \ + ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \ + (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \ + (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)) + +#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 12; + } rbbm_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int : 12; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + } rbbm_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_cntl_t f; +} rbbm_int_cntl_u; + + +/* + * RBBM_INT_STATUS struct + */ + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000 + +#define RBBM_INT_STATUS_MASK \ + (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \ + RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \ + RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) + +#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \ + ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \ + (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \ + (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)) + +#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 12; + } rbbm_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int : 12; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + } rbbm_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_status_t f; +} rbbm_int_status_u; + + +/* + * RBBM_INT_ACK struct + */ + +#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1 + +#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19 + +#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000 + +#define RBBM_INT_ACK_MASK \ + (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \ + RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \ + RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) + +#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \ + ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \ + (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \ + (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)) + +#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 12; + } rbbm_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int : 12; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + } rbbm_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_ack_t f; +} rbbm_int_ack_u; + + +/* + * MASTER_INT_SIGNAL struct + */ + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020 +#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000 + +#define MASTER_INT_SIGNAL_MASK \ + (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) + +#define MASTER_INT_SIGNAL(mh_int_stat, cp_int_stat, rbbm_int_stat) \ + ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \ + (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \ + (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)) + +#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int : 5; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 24; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + } master_int_signal_t; + +#else // !BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int : 24; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 5; + } master_int_signal_t; + +#endif + +typedef union { + unsigned int val : 32; + master_int_signal_t f; +} master_int_signal_u; + + +/* + * RBBM_PERFCOUNTER1_SELECT struct + */ + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f + +#define RBBM_PERFCOUNTER1_SELECT_MASK \ + (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) + +#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \ + ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)) + +#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \ + ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \ + rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + unsigned int : 26; + } rbbm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int : 26; + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + } rbbm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_select_t f; +} rbbm_perfcounter1_select_u; + + +/* + * RBBM_PERFCOUNTER1_LO struct + */ + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff + +#define RBBM_PERFCOUNTER1_LO_MASK \ + (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) + +#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \ + ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)) + +#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \ + ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \ + rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_lo_t f; +} rbbm_perfcounter1_lo_u; + + +/* + * RBBM_PERFCOUNTER1_HI struct + */ + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff + +#define RBBM_PERFCOUNTER1_HI_MASK \ + (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) + +#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \ + ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)) + +#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \ + ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \ + rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + unsigned int : 16; + } rbbm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + } rbbm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_hi_t f; +} rbbm_perfcounter1_hi_u; + + +#endif + + +#if !defined (_MH_FIDDLE_H) +#define _MH_FIDDLE_H + +/***************************************************************************************************************** + * + * mh_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * MH_ARBITER_CONFIG struct + */ + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200 +#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000 + +#define MH_ARBITER_CONFIG_MASK \ + (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \ + MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \ + MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \ + MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \ + MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) + +#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable) \ + ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \ + (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \ + (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \ + (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \ + (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \ + (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \ + (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \ + (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \ + (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \ + (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \ + (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \ + (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \ + (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)) + +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) + +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int : 6; + } mh_arbiter_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int : 6; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + } mh_arbiter_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_arbiter_config_t f; +} mh_arbiter_config_u; + + +/* + * MH_CLNT_AXI_ID_REUSE struct + */ + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700 + +#define MH_CLNT_AXI_ID_REUSE_MASK \ + (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \ + MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \ + MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id) \ + ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \ + (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \ + (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \ + (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \ + (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 21; + } mh_clnt_axi_id_reuse_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int : 21; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + } mh_clnt_axi_id_reuse_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_clnt_axi_id_reuse_t f; +} mh_clnt_axi_id_reuse_u; + + +/* + * MH_INTERRUPT_MASK struct + */ + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_MASK_MASK \ + (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + } mh_interrupt_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_mask_t f; +} mh_interrupt_mask_u; + + +/* + * MH_INTERRUPT_STATUS struct + */ + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_STATUS_MASK \ + (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + } mh_interrupt_status_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_status_t f; +} mh_interrupt_status_u; + + +/* + * MH_INTERRUPT_CLEAR struct + */ + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_CLEAR_MASK \ + (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + } mh_interrupt_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_clear_t f; +} mh_interrupt_clear_u; + + +/* + * MH_AXI_ERROR struct + */ + +#define MH_AXI_ERROR_AXI_READ_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1 +#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1 + +#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3 +#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7 + +#define MH_AXI_ERROR_AXI_READ_ID_MASK 0x00000007 +#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008 +#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080 + +#define MH_AXI_ERROR_MASK \ + (MH_AXI_ERROR_AXI_READ_ID_MASK | \ + MH_AXI_ERROR_AXI_READ_ERROR_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ID_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) + +#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \ + ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \ + (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \ + (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)) + +#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int : 24; + } mh_axi_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int : 24; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + } mh_axi_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_error_t f; +} mh_axi_error_u; + + +/* + * MH_PERFCOUNTER0_SELECT struct + */ + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER0_SELECT_MASK \ + (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \ + ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \ + mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } mh_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_select_t f; +} mh_perfcounter0_select_u; + + +/* + * MH_PERFCOUNTER1_SELECT struct + */ + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER1_SELECT_MASK \ + (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \ + ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \ + mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } mh_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_select_t f; +} mh_perfcounter1_select_u; + + +/* + * MH_PERFCOUNTER0_CONFIG struct + */ + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER0_CONFIG_MASK \ + (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER0_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \ + ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \ + mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter0_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + } mh_perfcounter0_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_config_t f; +} mh_perfcounter0_config_u; + + +/* + * MH_PERFCOUNTER1_CONFIG struct + */ + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER1_CONFIG_MASK \ + (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER1_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \ + ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \ + mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter1_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + } mh_perfcounter1_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_config_t f; +} mh_perfcounter1_config_u; + + +/* + * MH_PERFCOUNTER0_LOW struct + */ + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER0_LOW_MASK \ + (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER0_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \ + ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \ + mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_low_t f; +} mh_perfcounter0_low_u; + + +/* + * MH_PERFCOUNTER1_LOW struct + */ + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER1_LOW_MASK \ + (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER1_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \ + ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \ + mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_low_t f; +} mh_perfcounter1_low_u; + + +/* + * MH_PERFCOUNTER0_HI struct + */ + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER0_HI_MASK \ + (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER0_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \ + ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \ + mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_hi_t f; +} mh_perfcounter0_hi_u; + + +/* + * MH_PERFCOUNTER1_HI struct + */ + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER1_HI_MASK \ + (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER1_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \ + ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \ + mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_hi_t f; +} mh_perfcounter1_hi_u; + + +/* + * MH_DEBUG_CTRL struct + */ + +#define MH_DEBUG_CTRL_INDEX_SIZE 6 + +#define MH_DEBUG_CTRL_INDEX_SHIFT 0 + +#define MH_DEBUG_CTRL_INDEX_MASK 0x0000003f + +#define MH_DEBUG_CTRL_MASK \ + (MH_DEBUG_CTRL_INDEX_MASK) + +#define MH_DEBUG_CTRL(index) \ + ((index << MH_DEBUG_CTRL_INDEX_SHIFT)) + +#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \ + ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT) + +#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \ + mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + unsigned int : 26; + } mh_debug_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int : 26; + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + } mh_debug_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_ctrl_t f; +} mh_debug_ctrl_u; + + +/* + * MH_DEBUG_DATA struct + */ + +#define MH_DEBUG_DATA_DATA_SIZE 32 + +#define MH_DEBUG_DATA_DATA_SHIFT 0 + +#define MH_DEBUG_DATA_DATA_MASK 0xffffffff + +#define MH_DEBUG_DATA_MASK \ + (MH_DEBUG_DATA_DATA_MASK) + +#define MH_DEBUG_DATA(data) \ + ((data << MH_DEBUG_DATA_DATA_SHIFT)) + +#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \ + ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT) + +#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \ + mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_data_t f; +} mh_debug_data_u; + + +/* + * MH_DEBUG_REG00 struct + */ + +#define MH_DEBUG_REG00_MH_BUSY_SIZE 1 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1 +#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1 +#define MH_DEBUG_REG00_TCD_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TCD_FULL_SIZE 1 +#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1 +#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_ARQ_FULL_SIZE 1 +#define MH_DEBUG_REG00_WDB_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_WDB_FULL_SIZE 1 +#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1 + +#define MH_DEBUG_REG00_MH_BUSY_SHIFT 0 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1 +#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2 +#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3 +#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5 +#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6 +#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7 +#define MH_DEBUG_REG00_TCD_FULL_SHIFT 8 +#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 10 +#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 11 +#define MH_DEBUG_REG00_ARQ_FULL_SHIFT 12 +#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 13 +#define MH_DEBUG_REG00_WDB_FULL_SHIFT 14 +#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 15 +#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 16 +#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 17 +#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 18 +#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 19 +#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 20 +#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 21 +#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 22 +#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 23 +#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 24 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 25 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 26 + +#define MH_DEBUG_REG00_MH_BUSY_MASK 0x00000001 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002 +#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004 +#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008 +#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020 +#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040 +#define MH_DEBUG_REG00_TCD_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG00_TCD_FULL_MASK 0x00000100 +#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000400 +#define MH_DEBUG_REG00_ARQ_EMPTY_MASK 0x00000800 +#define MH_DEBUG_REG00_ARQ_FULL_MASK 0x00001000 +#define MH_DEBUG_REG00_WDB_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG00_WDB_FULL_MASK 0x00004000 +#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00008000 +#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00010000 +#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00020000 +#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00040000 +#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00080000 +#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00100000 +#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00200000 +#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00400000 +#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x00800000 +#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x01000000 +#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x02000000 +#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x04000000 + +#define MH_DEBUG_REG00_MASK \ + (MH_DEBUG_REG00_MH_BUSY_MASK | \ + MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \ + MH_DEBUG_REG00_CP_REQUEST_MASK | \ + MH_DEBUG_REG00_VGT_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \ + MH_DEBUG_REG00_TC_CAM_FULL_MASK | \ + MH_DEBUG_REG00_TCD_EMPTY_MASK | \ + MH_DEBUG_REG00_TCD_FULL_MASK | \ + MH_DEBUG_REG00_RB_REQUEST_MASK | \ + MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \ + MH_DEBUG_REG00_ARQ_EMPTY_MASK | \ + MH_DEBUG_REG00_ARQ_FULL_MASK | \ + MH_DEBUG_REG00_WDB_EMPTY_MASK | \ + MH_DEBUG_REG00_WDB_FULL_MASK | \ + MH_DEBUG_REG00_AXI_AVALID_MASK | \ + MH_DEBUG_REG00_AXI_AREADY_MASK | \ + MH_DEBUG_REG00_AXI_ARVALID_MASK | \ + MH_DEBUG_REG00_AXI_ARREADY_MASK | \ + MH_DEBUG_REG00_AXI_WVALID_MASK | \ + MH_DEBUG_REG00_AXI_WREADY_MASK | \ + MH_DEBUG_REG00_AXI_RVALID_MASK | \ + MH_DEBUG_REG00_AXI_RREADY_MASK | \ + MH_DEBUG_REG00_AXI_BVALID_MASK | \ + MH_DEBUG_REG00_AXI_BREADY_MASK | \ + MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \ + MH_DEBUG_REG00_AXI_HALT_ACK_MASK) + +#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack) \ + ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \ + (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \ + (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \ + (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \ + (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \ + (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \ + (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \ + (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \ + (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \ + (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \ + (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \ + (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \ + (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \ + (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \ + (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \ + (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \ + (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \ + (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \ + (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \ + (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \ + (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \ + (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \ + (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \ + (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \ + (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \ + (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \ + (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)) + +#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) + +#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int : 5; + } mh_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int : 5; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + } mh_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg00_t f; +} mh_debug_reg00_u; + + +/* + * MH_DEBUG_REG01 struct + */ + +#define MH_DEBUG_REG01_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1 +#define MH_DEBUG_REG01_CP_TAG_q_SIZE 3 +#define MH_DEBUG_REG01_CP_BE_q_SIZE 8 +#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_TAG_q_SIZE 1 +#define MH_DEBUG_REG01_TC_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG01_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_RB_BE_q_SIZE 8 + +#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0 +#define MH_DEBUG_REG01_CP_RTR_q_SHIFT 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2 +#define MH_DEBUG_REG01_CP_TAG_q_SHIFT 3 +#define MH_DEBUG_REG01_CP_BE_q_SHIFT 6 +#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 14 +#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 15 +#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 16 +#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 17 +#define MH_DEBUG_REG01_TC_RTR_q_SHIFT 18 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 19 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 20 +#define MH_DEBUG_REG01_TC_MH_written_SHIFT 21 +#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 22 +#define MH_DEBUG_REG01_RB_RTR_q_SHIFT 23 +#define MH_DEBUG_REG01_RB_BE_q_SHIFT 24 + +#define MH_DEBUG_REG01_CP_SEND_q_MASK 0x00000001 +#define MH_DEBUG_REG01_CP_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004 +#define MH_DEBUG_REG01_CP_TAG_q_MASK 0x00000038 +#define MH_DEBUG_REG01_CP_BE_q_MASK 0x00003fc0 +#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00004000 +#define MH_DEBUG_REG01_VGT_RTR_q_MASK 0x00008000 +#define MH_DEBUG_REG01_VGT_TAG_q_MASK 0x00010000 +#define MH_DEBUG_REG01_TC_SEND_q_MASK 0x00020000 +#define MH_DEBUG_REG01_TC_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00080000 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00100000 +#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00200000 +#define MH_DEBUG_REG01_RB_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG01_RB_RTR_q_MASK 0x00800000 +#define MH_DEBUG_REG01_RB_BE_q_MASK 0xff000000 + +#define MH_DEBUG_REG01_MASK \ + (MH_DEBUG_REG01_CP_SEND_q_MASK | \ + MH_DEBUG_REG01_CP_RTR_q_MASK | \ + MH_DEBUG_REG01_CP_WRITE_q_MASK | \ + MH_DEBUG_REG01_CP_TAG_q_MASK | \ + MH_DEBUG_REG01_CP_BE_q_MASK | \ + MH_DEBUG_REG01_VGT_SEND_q_MASK | \ + MH_DEBUG_REG01_VGT_RTR_q_MASK | \ + MH_DEBUG_REG01_VGT_TAG_q_MASK | \ + MH_DEBUG_REG01_TC_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_MH_written_MASK | \ + MH_DEBUG_REG01_RB_SEND_q_MASK | \ + MH_DEBUG_REG01_RB_RTR_q_MASK | \ + MH_DEBUG_REG01_RB_BE_q_MASK) + +#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_be_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, rb_be_q) \ + ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \ + (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \ + (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \ + (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \ + (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \ + (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \ + (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \ + (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT)) + +#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_BE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BE_q_MASK) >> MH_DEBUG_REG01_CP_BE_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_BE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_BE_q_MASK) >> MH_DEBUG_REG01_RB_BE_q_SHIFT) + +#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_BE_q(mh_debug_reg01_reg, cp_be_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BE_q_MASK) | (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_BE_q(mh_debug_reg01_reg, rb_be_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_BE_q_MASK) | (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_be_q : MH_DEBUG_REG01_CP_BE_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_be_q : MH_DEBUG_REG01_RB_BE_q_SIZE; + } mh_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int rb_be_q : MH_DEBUG_REG01_RB_BE_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int cp_be_q : MH_DEBUG_REG01_CP_BE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + } mh_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg01_t f; +} mh_debug_reg01_u; + + +/* + * MH_DEBUG_REG02 struct + */ + +#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3 +#define MH_DEBUG_REG02_RDC_RID_SIZE 3 +#define MH_DEBUG_REG02_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1 +#define MH_DEBUG_REG02_BRC_BID_SIZE 3 +#define MH_DEBUG_REG02_BRC_BRESP_SIZE 2 + +#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3 +#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4 +#define MH_DEBUG_REG02_RDC_RID_SHIFT 7 +#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12 +#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13 +#define MH_DEBUG_REG02_BRC_BID_SHIFT 14 +#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 17 + +#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008 +#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070 +#define MH_DEBUG_REG02_RDC_RID_MASK 0x00000380 +#define MH_DEBUG_REG02_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000 +#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000 +#define MH_DEBUG_REG02_BRC_BID_MASK 0x0001c000 +#define MH_DEBUG_REG02_BRC_BRESP_MASK 0x00060000 + +#define MH_DEBUG_REG02_MASK \ + (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG02_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \ + MH_DEBUG_REG02_MH_CLNT_tag_MASK | \ + MH_DEBUG_REG02_RDC_RID_MASK | \ + MH_DEBUG_REG02_RDC_RRESP_MASK | \ + MH_DEBUG_REG02_MH_CP_writeclean_MASK | \ + MH_DEBUG_REG02_MH_RB_writeclean_MASK | \ + MH_DEBUG_REG02_BRC_BID_MASK | \ + MH_DEBUG_REG02_BRC_BRESP_MASK) + +#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, brc_bid, brc_bresp) \ + ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \ + (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \ + (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \ + (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \ + (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \ + (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \ + (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)) + +#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int : 13; + } mh_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int : 13; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + } mh_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg02_t f; +} mh_debug_reg02_u; + + +/* + * MH_DEBUG_REG03 struct + */ + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG03_MASK \ + (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) + +#define MH_DEBUG_REG03(mh_clnt_data_31_0) \ + ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)) + +#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \ + ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \ + mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg03_t f; +} mh_debug_reg03_u; + + +/* + * MH_DEBUG_REG04 struct + */ + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG04_MASK \ + (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) + +#define MH_DEBUG_REG04(mh_clnt_data_63_32) \ + ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)) + +#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \ + ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \ + mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg04_t f; +} mh_debug_reg04_u; + + +/* + * MH_DEBUG_REG05 struct + */ + +#define MH_DEBUG_REG05_CP_MH_send_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_tag_SIZE 3 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0 +#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1 +#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002 +#define MH_DEBUG_REG05_CP_MH_tag_MASK 0x0000001c +#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG05_MASK \ + (MH_DEBUG_REG05_CP_MH_send_MASK | \ + MH_DEBUG_REG05_CP_MH_write_MASK | \ + MH_DEBUG_REG05_CP_MH_tag_MASK | \ + MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \ + ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \ + (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \ + (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + } mh_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + } mh_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg05_t f; +} mh_debug_reg05_u; + + +/* + * MH_DEBUG_REG06 struct + */ + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG06_MASK \ + (MH_DEBUG_REG06_CP_MH_data_31_0_MASK) + +#define MH_DEBUG_REG06(cp_mh_data_31_0) \ + ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \ + ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \ + mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg06_t f; +} mh_debug_reg06_u; + + +/* + * MH_DEBUG_REG07 struct + */ + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG07_MASK \ + (MH_DEBUG_REG07_CP_MH_data_63_32_MASK) + +#define MH_DEBUG_REG07(cp_mh_data_63_32) \ + ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \ + ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \ + mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg07_t f; +} mh_debug_reg07_u; + + +/* + * MH_DEBUG_REG08 struct + */ + +#define MH_DEBUG_REG08_ALWAYS_ZERO_SIZE 3 +#define MH_DEBUG_REG08_VGT_MH_send_SIZE 1 +#define MH_DEBUG_REG08_VGT_MH_tagbe_SIZE 1 +#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG08_VGT_MH_send_SHIFT 3 +#define MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT 4 +#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG08_ALWAYS_ZERO_MASK 0x00000007 +#define MH_DEBUG_REG08_VGT_MH_send_MASK 0x00000008 +#define MH_DEBUG_REG08_VGT_MH_tagbe_MASK 0x00000010 +#define MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG08_MASK \ + (MH_DEBUG_REG08_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG08_VGT_MH_send_MASK | \ + MH_DEBUG_REG08_VGT_MH_tagbe_MASK | \ + MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG08(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \ + ((always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) | \ + (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT) | \ + (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) | \ + (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG08_GET_ALWAYS_ZERO(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG08_GET_VGT_MH_send(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_send_MASK) >> MH_DEBUG_REG08_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG08_GET_VGT_MH_tagbe(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG08_GET_VGT_MH_ad_31_5(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG08_SET_ALWAYS_ZERO(mh_debug_reg08_reg, always_zero) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG08_SET_VGT_MH_send(mh_debug_reg08_reg, vgt_mh_send) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG08_SET_VGT_MH_tagbe(mh_debug_reg08_reg, vgt_mh_tagbe) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG08_SET_VGT_MH_ad_31_5(mh_debug_reg08_reg, vgt_mh_ad_31_5) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int always_zero : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG08_VGT_MH_send_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE; + } mh_debug_reg08_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG08_VGT_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE; + } mh_debug_reg08_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg08_t f; +} mh_debug_reg08_u; + + +/* + * MH_DEBUG_REG09 struct + */ + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG09_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG09_TC_MH_mask_SIZE 2 +#define MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG09_TC_MH_send_SHIFT 2 +#define MH_DEBUG_REG09_TC_MH_mask_SHIFT 3 +#define MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG09_TC_MH_send_MASK 0x00000004 +#define MH_DEBUG_REG09_TC_MH_mask_MASK 0x00000018 +#define MH_DEBUG_REG09_TC_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG09_MASK \ + (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG09_TC_MH_send_MASK | \ + MH_DEBUG_REG09_TC_MH_mask_MASK | \ + MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG09(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT) | \ + (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT) | \ + (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_GET_TC_MH_send(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_send_MASK) >> MH_DEBUG_REG09_TC_MH_send_SHIFT) +#define MH_DEBUG_REG09_GET_TC_MH_mask(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_mask_MASK) >> MH_DEBUG_REG09_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG09_GET_TC_MH_addr_31_5(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_SET_TC_MH_send(mh_debug_reg09_reg, tc_mh_send) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT) +#define MH_DEBUG_REG09_SET_TC_MH_mask(mh_debug_reg09_reg, tc_mh_mask) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG09_SET_TC_MH_addr_31_5(mh_debug_reg09_reg, tc_mh_addr_31_5) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG09_TC_MH_send_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG09_TC_MH_mask_SIZE; + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE; + } mh_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG09_TC_MH_mask_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG09_TC_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + } mh_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg09_t f; +} mh_debug_reg09_u; + + +/* + * MH_DEBUG_REG10 struct + */ + +#define MH_DEBUG_REG10_TC_MH_info_SIZE 25 +#define MH_DEBUG_REG10_TC_MH_send_SIZE 1 + +#define MH_DEBUG_REG10_TC_MH_info_SHIFT 0 +#define MH_DEBUG_REG10_TC_MH_send_SHIFT 25 + +#define MH_DEBUG_REG10_TC_MH_info_MASK 0x01ffffff +#define MH_DEBUG_REG10_TC_MH_send_MASK 0x02000000 + +#define MH_DEBUG_REG10_MASK \ + (MH_DEBUG_REG10_TC_MH_info_MASK | \ + MH_DEBUG_REG10_TC_MH_send_MASK) + +#define MH_DEBUG_REG10(tc_mh_info, tc_mh_send) \ + ((tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)) + +#define MH_DEBUG_REG10_GET_TC_MH_info(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_info_MASK) >> MH_DEBUG_REG10_TC_MH_info_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT) + +#define MH_DEBUG_REG10_SET_TC_MH_info(mh_debug_reg10_reg, tc_mh_info) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int tc_mh_info : MH_DEBUG_REG10_TC_MH_info_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int : 6; + } mh_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int : 6; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int tc_mh_info : MH_DEBUG_REG10_TC_MH_info_SIZE; + } mh_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg10_t f; +} mh_debug_reg10_u; + + +/* + * MH_DEBUG_REG11 struct + */ + +#define MH_DEBUG_REG11_MH_TC_mcinfo_SIZE 25 +#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE 1 +#define MH_DEBUG_REG11_TC_MH_written_SIZE 1 + +#define MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT 0 +#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT 25 +#define MH_DEBUG_REG11_TC_MH_written_SHIFT 26 + +#define MH_DEBUG_REG11_MH_TC_mcinfo_MASK 0x01ffffff +#define MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK 0x02000000 +#define MH_DEBUG_REG11_TC_MH_written_MASK 0x04000000 + +#define MH_DEBUG_REG11_MASK \ + (MH_DEBUG_REG11_MH_TC_mcinfo_MASK | \ + MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK | \ + MH_DEBUG_REG11_TC_MH_written_MASK) + +#define MH_DEBUG_REG11(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \ + ((mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) | \ + (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT)) + +#define MH_DEBUG_REG11_GET_MH_TC_mcinfo(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG11_GET_MH_TC_mcinfo_send(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG11_GET_TC_MH_written(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_written_MASK) >> MH_DEBUG_REG11_TC_MH_written_SHIFT) + +#define MH_DEBUG_REG11_SET_MH_TC_mcinfo(mh_debug_reg11_reg, mh_tc_mcinfo) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG11_SET_MH_TC_mcinfo_send(mh_debug_reg11_reg, mh_tc_mcinfo_send) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG11_SET_TC_MH_written(mh_debug_reg11_reg, tc_mh_written) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int mh_tc_mcinfo : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG11_TC_MH_written_SIZE; + unsigned int : 5; + } mh_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int : 5; + unsigned int tc_mh_written : MH_DEBUG_REG11_TC_MH_written_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE; + unsigned int mh_tc_mcinfo : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE; + } mh_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg11_t f; +} mh_debug_reg11_u; + + +/* + * MH_DEBUG_REG12 struct + */ + +#define MH_DEBUG_REG12_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG12_TC_ROQ_SEND_SIZE 1 +#define MH_DEBUG_REG12_TC_ROQ_MASK_SIZE 2 +#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE 27 + +#define MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT 2 +#define MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT 3 +#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT 5 + +#define MH_DEBUG_REG12_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG12_TC_ROQ_SEND_MASK 0x00000004 +#define MH_DEBUG_REG12_TC_ROQ_MASK_MASK 0x00000018 +#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG12_MASK \ + (MH_DEBUG_REG12_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG12_TC_ROQ_SEND_MASK | \ + MH_DEBUG_REG12_TC_ROQ_MASK_MASK | \ + MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) + +#define MH_DEBUG_REG12(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \ + ((always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) | \ + (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) | \ + (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT)) + +#define MH_DEBUG_REG12_GET_ALWAYS_ZERO(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG12_GET_TC_ROQ_SEND(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG12_GET_TC_ROQ_MASK(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG12_GET_TC_ROQ_ADDR_31_5(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT) + +#define MH_DEBUG_REG12_SET_ALWAYS_ZERO(mh_debug_reg12_reg, always_zero) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG12_SET_TC_ROQ_SEND(mh_debug_reg12_reg, tc_roq_send) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG12_SET_TC_ROQ_MASK(mh_debug_reg12_reg, tc_roq_mask) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG12_SET_TC_ROQ_ADDR_31_5(mh_debug_reg12_reg, tc_roq_addr_31_5) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int always_zero : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE; + } mh_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE; + unsigned int always_zero : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE; + } mh_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg12_t f; +} mh_debug_reg12_u; + + +/* + * MH_DEBUG_REG13 struct + */ + +#define MH_DEBUG_REG13_TC_ROQ_INFO_SIZE 25 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1 + +#define MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT 0 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 25 + +#define MH_DEBUG_REG13_TC_ROQ_INFO_MASK 0x01ffffff +#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x02000000 + +#define MH_DEBUG_REG13_MASK \ + (MH_DEBUG_REG13_TC_ROQ_INFO_MASK | \ + MH_DEBUG_REG13_TC_ROQ_SEND_MASK) + +#define MH_DEBUG_REG13(tc_roq_info, tc_roq_send) \ + ((tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)) + +#define MH_DEBUG_REG13_GET_TC_ROQ_INFO(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) + +#define MH_DEBUG_REG13_SET_TC_ROQ_INFO(mh_debug_reg13_reg, tc_roq_info) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int tc_roq_info : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int : 6; + } mh_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int : 6; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_info : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE; + } mh_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg13_t f; +} mh_debug_reg13_u; + + +/* + * MH_DEBUG_REG14 struct + */ + +#define MH_DEBUG_REG14_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG14_RB_MH_send_SIZE 1 +#define MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG14_RB_MH_send_SHIFT 4 +#define MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG14_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG14_RB_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG14_RB_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG14_MASK \ + (MH_DEBUG_REG14_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG14_RB_MH_send_MASK | \ + MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG14(always_zero, rb_mh_send, rb_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) | \ + (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT) | \ + (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG14_GET_ALWAYS_ZERO(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG14_GET_RB_MH_send(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_send_MASK) >> MH_DEBUG_REG14_RB_MH_send_SHIFT) +#define MH_DEBUG_REG14_GET_RB_MH_addr_31_5(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG14_SET_ALWAYS_ZERO(mh_debug_reg14_reg, always_zero) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG14_SET_RB_MH_send(mh_debug_reg14_reg, rb_mh_send) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT) +#define MH_DEBUG_REG14_SET_RB_MH_addr_31_5(mh_debug_reg14_reg, rb_mh_addr_31_5) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int always_zero : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG14_RB_MH_send_SIZE; + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE; + } mh_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG14_RB_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE; + } mh_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg14_t f; +} mh_debug_reg14_u; + + +/* + * MH_DEBUG_REG15 struct + */ + +#define MH_DEBUG_REG15_RB_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG15_RB_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG15_MASK \ + (MH_DEBUG_REG15_RB_MH_data_31_0_MASK) + +#define MH_DEBUG_REG15(rb_mh_data_31_0) \ + ((rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG15_GET_RB_MH_data_31_0(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG15_SET_RB_MH_data_31_0(mh_debug_reg15_reg, rb_mh_data_31_0) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE; + } mh_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE; + } mh_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg15_t f; +} mh_debug_reg15_u; + + +/* + * MH_DEBUG_REG16 struct + */ + +#define MH_DEBUG_REG16_RB_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG16_RB_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG16_MASK \ + (MH_DEBUG_REG16_RB_MH_data_63_32_MASK) + +#define MH_DEBUG_REG16(rb_mh_data_63_32) \ + ((rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG16_GET_RB_MH_data_63_32(mh_debug_reg16) \ + ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG16_SET_RB_MH_data_63_32(mh_debug_reg16_reg, rb_mh_data_63_32) \ + mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE; + } mh_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE; + } mh_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg16_t f; +} mh_debug_reg16_u; + + +/* + * MH_DEBUG_REG17 struct + */ + +#define MH_DEBUG_REG17_AVALID_q_SIZE 1 +#define MH_DEBUG_REG17_AREADY_q_SIZE 1 +#define MH_DEBUG_REG17_AID_q_SIZE 3 +#define MH_DEBUG_REG17_ALEN_q_2_0_SIZE 3 +#define MH_DEBUG_REG17_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG17_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG17_ARID_q_SIZE 3 +#define MH_DEBUG_REG17_ARLEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG17_RVALID_q_SIZE 1 +#define MH_DEBUG_REG17_RREADY_q_SIZE 1 +#define MH_DEBUG_REG17_RLAST_q_SIZE 1 +#define MH_DEBUG_REG17_RID_q_SIZE 3 +#define MH_DEBUG_REG17_WVALID_q_SIZE 1 +#define MH_DEBUG_REG17_WREADY_q_SIZE 1 +#define MH_DEBUG_REG17_WLAST_q_SIZE 1 +#define MH_DEBUG_REG17_WID_q_SIZE 3 +#define MH_DEBUG_REG17_BVALID_q_SIZE 1 +#define MH_DEBUG_REG17_BREADY_q_SIZE 1 +#define MH_DEBUG_REG17_BID_q_SIZE 3 + +#define MH_DEBUG_REG17_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG17_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG17_AID_q_SHIFT 2 +#define MH_DEBUG_REG17_ALEN_q_2_0_SHIFT 5 +#define MH_DEBUG_REG17_ARVALID_q_SHIFT 8 +#define MH_DEBUG_REG17_ARREADY_q_SHIFT 9 +#define MH_DEBUG_REG17_ARID_q_SHIFT 10 +#define MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT 13 +#define MH_DEBUG_REG17_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG17_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG17_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG17_RID_q_SHIFT 18 +#define MH_DEBUG_REG17_WVALID_q_SHIFT 21 +#define MH_DEBUG_REG17_WREADY_q_SHIFT 22 +#define MH_DEBUG_REG17_WLAST_q_SHIFT 23 +#define MH_DEBUG_REG17_WID_q_SHIFT 24 +#define MH_DEBUG_REG17_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG17_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG17_BID_q_SHIFT 29 + +#define MH_DEBUG_REG17_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG17_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG17_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG17_ALEN_q_2_0_MASK 0x000000e0 +#define MH_DEBUG_REG17_ARVALID_q_MASK 0x00000100 +#define MH_DEBUG_REG17_ARREADY_q_MASK 0x00000200 +#define MH_DEBUG_REG17_ARID_q_MASK 0x00001c00 +#define MH_DEBUG_REG17_ARLEN_q_1_0_MASK 0x00006000 +#define MH_DEBUG_REG17_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG17_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG17_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG17_RID_q_MASK 0x001c0000 +#define MH_DEBUG_REG17_WVALID_q_MASK 0x00200000 +#define MH_DEBUG_REG17_WREADY_q_MASK 0x00400000 +#define MH_DEBUG_REG17_WLAST_q_MASK 0x00800000 +#define MH_DEBUG_REG17_WID_q_MASK 0x07000000 +#define MH_DEBUG_REG17_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG17_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG17_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG17_MASK \ + (MH_DEBUG_REG17_AVALID_q_MASK | \ + MH_DEBUG_REG17_AREADY_q_MASK | \ + MH_DEBUG_REG17_AID_q_MASK | \ + MH_DEBUG_REG17_ALEN_q_2_0_MASK | \ + MH_DEBUG_REG17_ARVALID_q_MASK | \ + MH_DEBUG_REG17_ARREADY_q_MASK | \ + MH_DEBUG_REG17_ARID_q_MASK | \ + MH_DEBUG_REG17_ARLEN_q_1_0_MASK | \ + MH_DEBUG_REG17_RVALID_q_MASK | \ + MH_DEBUG_REG17_RREADY_q_MASK | \ + MH_DEBUG_REG17_RLAST_q_MASK | \ + MH_DEBUG_REG17_RID_q_MASK | \ + MH_DEBUG_REG17_WVALID_q_MASK | \ + MH_DEBUG_REG17_WREADY_q_MASK | \ + MH_DEBUG_REG17_WLAST_q_MASK | \ + MH_DEBUG_REG17_WID_q_MASK | \ + MH_DEBUG_REG17_BVALID_q_MASK | \ + MH_DEBUG_REG17_BREADY_q_MASK | \ + MH_DEBUG_REG17_BID_q_MASK) + +#define MH_DEBUG_REG17(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG17_AID_q_SHIFT) | \ + (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT) | \ + (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT) | \ + (rid_q << MH_DEBUG_REG17_RID_q_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG17_WID_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG17_BID_q_SHIFT)) + +#define MH_DEBUG_REG17_GET_AVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_AVALID_q_MASK) >> MH_DEBUG_REG17_AVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_AREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_AREADY_q_MASK) >> MH_DEBUG_REG17_AREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_AID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_AID_q_MASK) >> MH_DEBUG_REG17_AID_q_SHIFT) +#define MH_DEBUG_REG17_GET_ALEN_q_2_0(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ALEN_q_2_0_MASK) >> MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG17_GET_ARVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARVALID_q_MASK) >> MH_DEBUG_REG17_ARVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_ARREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARREADY_q_MASK) >> MH_DEBUG_REG17_ARREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_ARID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARID_q_MASK) >> MH_DEBUG_REG17_ARID_q_SHIFT) +#define MH_DEBUG_REG17_GET_ARLEN_q_1_0(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG17_GET_RVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RVALID_q_MASK) >> MH_DEBUG_REG17_RVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_RREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RREADY_q_MASK) >> MH_DEBUG_REG17_RREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_RLAST_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RLAST_q_MASK) >> MH_DEBUG_REG17_RLAST_q_SHIFT) +#define MH_DEBUG_REG17_GET_RID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RID_q_MASK) >> MH_DEBUG_REG17_RID_q_SHIFT) +#define MH_DEBUG_REG17_GET_WVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WVALID_q_MASK) >> MH_DEBUG_REG17_WVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_WREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WREADY_q_MASK) >> MH_DEBUG_REG17_WREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_WLAST_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WLAST_q_MASK) >> MH_DEBUG_REG17_WLAST_q_SHIFT) +#define MH_DEBUG_REG17_GET_WID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WID_q_MASK) >> MH_DEBUG_REG17_WID_q_SHIFT) +#define MH_DEBUG_REG17_GET_BVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_BVALID_q_MASK) >> MH_DEBUG_REG17_BVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_BREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_BREADY_q_MASK) >> MH_DEBUG_REG17_BREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_BID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_BID_q_MASK) >> MH_DEBUG_REG17_BID_q_SHIFT) + +#define MH_DEBUG_REG17_SET_AVALID_q(mh_debug_reg17_reg, avalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_AREADY_q(mh_debug_reg17_reg, aready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_AID_q(mh_debug_reg17_reg, aid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AID_q_MASK) | (aid_q << MH_DEBUG_REG17_AID_q_SHIFT) +#define MH_DEBUG_REG17_SET_ALEN_q_2_0(mh_debug_reg17_reg, alen_q_2_0) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG17_SET_ARVALID_q(mh_debug_reg17_reg, arvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_ARREADY_q(mh_debug_reg17_reg, arready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_ARID_q(mh_debug_reg17_reg, arid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARID_q_MASK) | (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT) +#define MH_DEBUG_REG17_SET_ARLEN_q_1_0(mh_debug_reg17_reg, arlen_q_1_0) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG17_SET_RVALID_q(mh_debug_reg17_reg, rvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_RREADY_q(mh_debug_reg17_reg, rready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_RLAST_q(mh_debug_reg17_reg, rlast_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT) +#define MH_DEBUG_REG17_SET_RID_q(mh_debug_reg17_reg, rid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RID_q_MASK) | (rid_q << MH_DEBUG_REG17_RID_q_SHIFT) +#define MH_DEBUG_REG17_SET_WVALID_q(mh_debug_reg17_reg, wvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_WREADY_q(mh_debug_reg17_reg, wready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_WLAST_q(mh_debug_reg17_reg, wlast_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT) +#define MH_DEBUG_REG17_SET_WID_q(mh_debug_reg17_reg, wid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WID_q_MASK) | (wid_q << MH_DEBUG_REG17_WID_q_SHIFT) +#define MH_DEBUG_REG17_SET_BVALID_q(mh_debug_reg17_reg, bvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_BREADY_q(mh_debug_reg17_reg, bready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_BID_q(mh_debug_reg17_reg, bid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BID_q_MASK) | (bid_q << MH_DEBUG_REG17_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int avalid_q : MH_DEBUG_REG17_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG17_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG17_AID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG17_ALEN_q_2_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG17_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG17_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG17_ARID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG17_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG17_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG17_RLAST_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG17_RID_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG17_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG17_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG17_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG17_WID_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG17_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG17_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG17_BID_q_SIZE; + } mh_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int bid_q : MH_DEBUG_REG17_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG17_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG17_BVALID_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG17_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG17_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG17_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG17_WVALID_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG17_RID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG17_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG17_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG17_RVALID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE; + unsigned int arid_q : MH_DEBUG_REG17_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG17_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG17_ARVALID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG17_ALEN_q_2_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG17_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG17_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG17_AVALID_q_SIZE; + } mh_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg17_t f; +} mh_debug_reg17_u; + + +/* + * MH_DEBUG_REG18 struct + */ + +#define MH_DEBUG_REG18_AVALID_q_SIZE 1 +#define MH_DEBUG_REG18_AREADY_q_SIZE 1 +#define MH_DEBUG_REG18_AID_q_SIZE 3 +#define MH_DEBUG_REG18_ALEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG18_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG18_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG18_ARID_q_SIZE 3 +#define MH_DEBUG_REG18_ARLEN_q_1_1_SIZE 1 +#define MH_DEBUG_REG18_WVALID_q_SIZE 1 +#define MH_DEBUG_REG18_WREADY_q_SIZE 1 +#define MH_DEBUG_REG18_WLAST_q_SIZE 1 +#define MH_DEBUG_REG18_WID_q_SIZE 3 +#define MH_DEBUG_REG18_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG18_BVALID_q_SIZE 1 +#define MH_DEBUG_REG18_BREADY_q_SIZE 1 +#define MH_DEBUG_REG18_BID_q_SIZE 3 + +#define MH_DEBUG_REG18_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG18_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG18_AID_q_SHIFT 2 +#define MH_DEBUG_REG18_ALEN_q_1_0_SHIFT 5 +#define MH_DEBUG_REG18_ARVALID_q_SHIFT 7 +#define MH_DEBUG_REG18_ARREADY_q_SHIFT 8 +#define MH_DEBUG_REG18_ARID_q_SHIFT 9 +#define MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT 12 +#define MH_DEBUG_REG18_WVALID_q_SHIFT 13 +#define MH_DEBUG_REG18_WREADY_q_SHIFT 14 +#define MH_DEBUG_REG18_WLAST_q_SHIFT 15 +#define MH_DEBUG_REG18_WID_q_SHIFT 16 +#define MH_DEBUG_REG18_WSTRB_q_SHIFT 19 +#define MH_DEBUG_REG18_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG18_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG18_BID_q_SHIFT 29 + +#define MH_DEBUG_REG18_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG18_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG18_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG18_ALEN_q_1_0_MASK 0x00000060 +#define MH_DEBUG_REG18_ARVALID_q_MASK 0x00000080 +#define MH_DEBUG_REG18_ARREADY_q_MASK 0x00000100 +#define MH_DEBUG_REG18_ARID_q_MASK 0x00000e00 +#define MH_DEBUG_REG18_ARLEN_q_1_1_MASK 0x00001000 +#define MH_DEBUG_REG18_WVALID_q_MASK 0x00002000 +#define MH_DEBUG_REG18_WREADY_q_MASK 0x00004000 +#define MH_DEBUG_REG18_WLAST_q_MASK 0x00008000 +#define MH_DEBUG_REG18_WID_q_MASK 0x00070000 +#define MH_DEBUG_REG18_WSTRB_q_MASK 0x07f80000 +#define MH_DEBUG_REG18_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG18_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG18_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG18_MASK \ + (MH_DEBUG_REG18_AVALID_q_MASK | \ + MH_DEBUG_REG18_AREADY_q_MASK | \ + MH_DEBUG_REG18_AID_q_MASK | \ + MH_DEBUG_REG18_ALEN_q_1_0_MASK | \ + MH_DEBUG_REG18_ARVALID_q_MASK | \ + MH_DEBUG_REG18_ARREADY_q_MASK | \ + MH_DEBUG_REG18_ARID_q_MASK | \ + MH_DEBUG_REG18_ARLEN_q_1_1_MASK | \ + MH_DEBUG_REG18_WVALID_q_MASK | \ + MH_DEBUG_REG18_WREADY_q_MASK | \ + MH_DEBUG_REG18_WLAST_q_MASK | \ + MH_DEBUG_REG18_WID_q_MASK | \ + MH_DEBUG_REG18_WSTRB_q_MASK | \ + MH_DEBUG_REG18_BVALID_q_MASK | \ + MH_DEBUG_REG18_BREADY_q_MASK | \ + MH_DEBUG_REG18_BID_q_MASK) + +#define MH_DEBUG_REG18(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG18_AID_q_SHIFT) | \ + (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT) | \ + (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG18_WID_q_SHIFT) | \ + (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG18_BID_q_SHIFT)) + +#define MH_DEBUG_REG18_GET_AVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_AVALID_q_MASK) >> MH_DEBUG_REG18_AVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_AREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_AREADY_q_MASK) >> MH_DEBUG_REG18_AREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_AID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_AID_q_MASK) >> MH_DEBUG_REG18_AID_q_SHIFT) +#define MH_DEBUG_REG18_GET_ALEN_q_1_0(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ALEN_q_1_0_MASK) >> MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG18_GET_ARVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARVALID_q_MASK) >> MH_DEBUG_REG18_ARVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_ARREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARREADY_q_MASK) >> MH_DEBUG_REG18_ARREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_ARID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARID_q_MASK) >> MH_DEBUG_REG18_ARID_q_SHIFT) +#define MH_DEBUG_REG18_GET_ARLEN_q_1_1(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG18_GET_WVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WVALID_q_MASK) >> MH_DEBUG_REG18_WVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_WREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WREADY_q_MASK) >> MH_DEBUG_REG18_WREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_WLAST_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WLAST_q_MASK) >> MH_DEBUG_REG18_WLAST_q_SHIFT) +#define MH_DEBUG_REG18_GET_WID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WID_q_MASK) >> MH_DEBUG_REG18_WID_q_SHIFT) +#define MH_DEBUG_REG18_GET_WSTRB_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WSTRB_q_MASK) >> MH_DEBUG_REG18_WSTRB_q_SHIFT) +#define MH_DEBUG_REG18_GET_BVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_BVALID_q_MASK) >> MH_DEBUG_REG18_BVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_BREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_BREADY_q_MASK) >> MH_DEBUG_REG18_BREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_BID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_BID_q_MASK) >> MH_DEBUG_REG18_BID_q_SHIFT) + +#define MH_DEBUG_REG18_SET_AVALID_q(mh_debug_reg18_reg, avalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_AREADY_q(mh_debug_reg18_reg, aready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_AID_q(mh_debug_reg18_reg, aid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AID_q_MASK) | (aid_q << MH_DEBUG_REG18_AID_q_SHIFT) +#define MH_DEBUG_REG18_SET_ALEN_q_1_0(mh_debug_reg18_reg, alen_q_1_0) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG18_SET_ARVALID_q(mh_debug_reg18_reg, arvalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_ARREADY_q(mh_debug_reg18_reg, arready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_ARID_q(mh_debug_reg18_reg, arid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARID_q_MASK) | (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT) +#define MH_DEBUG_REG18_SET_ARLEN_q_1_1(mh_debug_reg18_reg, arlen_q_1_1) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG18_SET_WVALID_q(mh_debug_reg18_reg, wvalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_WREADY_q(mh_debug_reg18_reg, wready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_WLAST_q(mh_debug_reg18_reg, wlast_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT) +#define MH_DEBUG_REG18_SET_WID_q(mh_debug_reg18_reg, wid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WID_q_MASK) | (wid_q << MH_DEBUG_REG18_WID_q_SHIFT) +#define MH_DEBUG_REG18_SET_WSTRB_q(mh_debug_reg18_reg, wstrb_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT) +#define MH_DEBUG_REG18_SET_BVALID_q(mh_debug_reg18_reg, bvalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_BREADY_q(mh_debug_reg18_reg, bready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_BID_q(mh_debug_reg18_reg, bid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BID_q_MASK) | (bid_q << MH_DEBUG_REG18_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int avalid_q : MH_DEBUG_REG18_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG18_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG18_AID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG18_ALEN_q_1_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG18_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG18_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG18_ARID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG18_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG18_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG18_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG18_WID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG18_WSTRB_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG18_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG18_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG18_BID_q_SIZE; + } mh_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int bid_q : MH_DEBUG_REG18_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG18_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG18_BVALID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG18_WSTRB_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG18_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG18_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG18_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG18_WVALID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE; + unsigned int arid_q : MH_DEBUG_REG18_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG18_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG18_ARVALID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG18_ALEN_q_1_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG18_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG18_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG18_AVALID_q_SIZE; + } mh_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg18_t f; +} mh_debug_reg18_u; + + +/* + * MH_DEBUG_REG19 struct + */ + +#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG19_CTRL_ARC_ID_SIZE 3 +#define MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE 28 + +#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT 0 +#define MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT 1 +#define MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT 4 + +#define MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK 0x00000001 +#define MH_DEBUG_REG19_CTRL_ARC_ID_MASK 0x0000000e +#define MH_DEBUG_REG19_CTRL_ARC_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG19_MASK \ + (MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG19_CTRL_ARC_ID_MASK | \ + MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) + +#define MH_DEBUG_REG19(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \ + ((arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) | \ + (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) | \ + (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT)) + +#define MH_DEBUG_REG19_GET_ARC_CTRL_RE_q(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG19_GET_CTRL_ARC_ID(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG19_GET_CTRL_ARC_PAD(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT) + +#define MH_DEBUG_REG19_SET_ARC_CTRL_RE_q(mh_debug_reg19_reg, arc_ctrl_re_q) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG19_SET_CTRL_ARC_ID(mh_debug_reg19_reg, ctrl_arc_id) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG19_SET_CTRL_ARC_PAD(mh_debug_reg19_reg, ctrl_arc_pad) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int arc_ctrl_re_q : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE; + unsigned int ctrl_arc_pad : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE; + } mh_debug_reg19_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int ctrl_arc_pad : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE; + } mh_debug_reg19_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg19_t f; +} mh_debug_reg19_u; + + +/* + * MH_DEBUG_REG20 struct + */ + +#define MH_DEBUG_REG20_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG20_REG_A_SIZE 14 +#define MH_DEBUG_REG20_REG_RE_SIZE 1 +#define MH_DEBUG_REG20_REG_WE_SIZE 1 +#define MH_DEBUG_REG20_BLOCK_RS_SIZE 1 + +#define MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG20_REG_A_SHIFT 2 +#define MH_DEBUG_REG20_REG_RE_SHIFT 16 +#define MH_DEBUG_REG20_REG_WE_SHIFT 17 +#define MH_DEBUG_REG20_BLOCK_RS_SHIFT 18 + +#define MH_DEBUG_REG20_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG20_REG_A_MASK 0x0000fffc +#define MH_DEBUG_REG20_REG_RE_MASK 0x00010000 +#define MH_DEBUG_REG20_REG_WE_MASK 0x00020000 +#define MH_DEBUG_REG20_BLOCK_RS_MASK 0x00040000 + +#define MH_DEBUG_REG20_MASK \ + (MH_DEBUG_REG20_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG20_REG_A_MASK | \ + MH_DEBUG_REG20_REG_RE_MASK | \ + MH_DEBUG_REG20_REG_WE_MASK | \ + MH_DEBUG_REG20_BLOCK_RS_MASK) + +#define MH_DEBUG_REG20(always_zero, reg_a, reg_re, reg_we, block_rs) \ + ((always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) | \ + (reg_a << MH_DEBUG_REG20_REG_A_SHIFT) | \ + (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT) | \ + (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT) | \ + (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT)) + +#define MH_DEBUG_REG20_GET_ALWAYS_ZERO(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG20_GET_REG_A(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_REG_A_MASK) >> MH_DEBUG_REG20_REG_A_SHIFT) +#define MH_DEBUG_REG20_GET_REG_RE(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_REG_RE_MASK) >> MH_DEBUG_REG20_REG_RE_SHIFT) +#define MH_DEBUG_REG20_GET_REG_WE(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_REG_WE_MASK) >> MH_DEBUG_REG20_REG_WE_SHIFT) +#define MH_DEBUG_REG20_GET_BLOCK_RS(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_BLOCK_RS_MASK) >> MH_DEBUG_REG20_BLOCK_RS_SHIFT) + +#define MH_DEBUG_REG20_SET_ALWAYS_ZERO(mh_debug_reg20_reg, always_zero) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG20_SET_REG_A(mh_debug_reg20_reg, reg_a) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_A_MASK) | (reg_a << MH_DEBUG_REG20_REG_A_SHIFT) +#define MH_DEBUG_REG20_SET_REG_RE(mh_debug_reg20_reg, reg_re) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_RE_MASK) | (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT) +#define MH_DEBUG_REG20_SET_REG_WE(mh_debug_reg20_reg, reg_we) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_WE_MASK) | (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT) +#define MH_DEBUG_REG20_SET_BLOCK_RS(mh_debug_reg20_reg, block_rs) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int always_zero : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE; + unsigned int reg_a : MH_DEBUG_REG20_REG_A_SIZE; + unsigned int reg_re : MH_DEBUG_REG20_REG_RE_SIZE; + unsigned int reg_we : MH_DEBUG_REG20_REG_WE_SIZE; + unsigned int block_rs : MH_DEBUG_REG20_BLOCK_RS_SIZE; + unsigned int : 13; + } mh_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int : 13; + unsigned int block_rs : MH_DEBUG_REG20_BLOCK_RS_SIZE; + unsigned int reg_we : MH_DEBUG_REG20_REG_WE_SIZE; + unsigned int reg_re : MH_DEBUG_REG20_REG_RE_SIZE; + unsigned int reg_a : MH_DEBUG_REG20_REG_A_SIZE; + unsigned int always_zero : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE; + } mh_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg20_t f; +} mh_debug_reg20_u; + + +/* + * MH_DEBUG_REG21 struct + */ + +#define MH_DEBUG_REG21_REG_WD_SIZE 32 + +#define MH_DEBUG_REG21_REG_WD_SHIFT 0 + +#define MH_DEBUG_REG21_REG_WD_MASK 0xffffffff + +#define MH_DEBUG_REG21_MASK \ + (MH_DEBUG_REG21_REG_WD_MASK) + +#define MH_DEBUG_REG21(reg_wd) \ + ((reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT)) + +#define MH_DEBUG_REG21_GET_REG_WD(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_REG_WD_MASK) >> MH_DEBUG_REG21_REG_WD_SHIFT) + +#define MH_DEBUG_REG21_SET_REG_WD(mh_debug_reg21_reg, reg_wd) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int reg_wd : MH_DEBUG_REG21_REG_WD_SIZE; + } mh_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int reg_wd : MH_DEBUG_REG21_REG_WD_SIZE; + } mh_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg21_t f; +} mh_debug_reg21_u; + + +/* + * MH_DEBUG_REG22 struct + */ + +#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE 1 +#define MH_DEBUG_REG22_MH_RBBM_busy_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE 1 +#define MH_DEBUG_REG22_GAT_CLK_ENA_SIZE 1 +#define MH_DEBUG_REG22_AXI_RDY_ENA_SIZE 1 +#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE 1 +#define MH_DEBUG_REG22_CNT_q_SIZE 6 +#define MH_DEBUG_REG22_TCD_EMPTY_q_SIZE 1 +#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG22_MH_BUSY_d_SIZE 1 +#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE 1 +#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_DEBUG_REG22_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG22_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG22_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG22_BRC_VALID_SIZE 1 + +#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT 0 +#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT 1 +#define MH_DEBUG_REG22_MH_RBBM_busy_SHIFT 2 +#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT 3 +#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT 4 +#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT 5 +#define MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT 6 +#define MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT 7 +#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT 8 +#define MH_DEBUG_REG22_CNT_q_SHIFT 9 +#define MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT 15 +#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT 16 +#define MH_DEBUG_REG22_MH_BUSY_d_SHIFT 17 +#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT 18 +#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 19 +#define MH_DEBUG_REG22_CP_SEND_q_SHIFT 20 +#define MH_DEBUG_REG22_CP_RTR_q_SHIFT 21 +#define MH_DEBUG_REG22_VGT_SEND_q_SHIFT 22 +#define MH_DEBUG_REG22_VGT_RTR_q_SHIFT 23 +#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT 24 +#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG22_RB_SEND_q_SHIFT 26 +#define MH_DEBUG_REG22_RB_RTR_q_SHIFT 27 +#define MH_DEBUG_REG22_RDC_VALID_SHIFT 28 +#define MH_DEBUG_REG22_RDC_RLAST_SHIFT 29 +#define MH_DEBUG_REG22_TLBMISS_VALID_SHIFT 30 +#define MH_DEBUG_REG22_BRC_VALID_SHIFT 31 + +#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK 0x00000001 +#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK 0x00000002 +#define MH_DEBUG_REG22_MH_RBBM_busy_MASK 0x00000004 +#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK 0x00000008 +#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK 0x00000010 +#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK 0x00000020 +#define MH_DEBUG_REG22_GAT_CLK_ENA_MASK 0x00000040 +#define MH_DEBUG_REG22_AXI_RDY_ENA_MASK 0x00000080 +#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK 0x00000100 +#define MH_DEBUG_REG22_CNT_q_MASK 0x00007e00 +#define MH_DEBUG_REG22_TCD_EMPTY_q_MASK 0x00008000 +#define MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK 0x00010000 +#define MH_DEBUG_REG22_MH_BUSY_d_MASK 0x00020000 +#define MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK 0x00040000 +#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000 +#define MH_DEBUG_REG22_CP_SEND_q_MASK 0x00100000 +#define MH_DEBUG_REG22_CP_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG22_VGT_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG22_VGT_RTR_q_MASK 0x00800000 +#define MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK 0x01000000 +#define MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG22_RB_SEND_q_MASK 0x04000000 +#define MH_DEBUG_REG22_RB_RTR_q_MASK 0x08000000 +#define MH_DEBUG_REG22_RDC_VALID_MASK 0x10000000 +#define MH_DEBUG_REG22_RDC_RLAST_MASK 0x20000000 +#define MH_DEBUG_REG22_TLBMISS_VALID_MASK 0x40000000 +#define MH_DEBUG_REG22_BRC_VALID_MASK 0x80000000 + +#define MH_DEBUG_REG22_MASK \ + (MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK | \ + MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK | \ + MH_DEBUG_REG22_MH_RBBM_busy_MASK | \ + MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK | \ + MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK | \ + MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK | \ + MH_DEBUG_REG22_GAT_CLK_ENA_MASK | \ + MH_DEBUG_REG22_AXI_RDY_ENA_MASK | \ + MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK | \ + MH_DEBUG_REG22_CNT_q_MASK | \ + MH_DEBUG_REG22_TCD_EMPTY_q_MASK | \ + MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG22_MH_BUSY_d_MASK | \ + MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK | \ + MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_DEBUG_REG22_CP_SEND_q_MASK | \ + MH_DEBUG_REG22_CP_RTR_q_MASK | \ + MH_DEBUG_REG22_VGT_SEND_q_MASK | \ + MH_DEBUG_REG22_VGT_RTR_q_MASK | \ + MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG22_RB_SEND_q_MASK | \ + MH_DEBUG_REG22_RB_RTR_q_MASK | \ + MH_DEBUG_REG22_RDC_VALID_MASK | \ + MH_DEBUG_REG22_RDC_RLAST_MASK | \ + MH_DEBUG_REG22_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG22_BRC_VALID_MASK) + +#define MH_DEBUG_REG22(cib_mh_axi_halt_req, mh_cib_axi_halt_ack, mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, axi_rdy_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_q, rb_send_q, rb_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \ + ((cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) | \ + (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) | \ + (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) | \ + (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) | \ + (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) | \ + (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) | \ + (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) | \ + (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) | \ + (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) | \ + (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT) | \ + (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) | \ + (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT) | \ + (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) | \ + (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) | \ + (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT)) + +#define MH_DEBUG_REG22_GET_CIB_MH_axi_halt_req(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) >> MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_axi_halt_ack(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) >> MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) +#define MH_DEBUG_REG22_GET_MH_RBBM_busy(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_RBBM_busy_MASK) >> MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_mh_clk_en_int(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_GET_GAT_CLK_ENA(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG22_GET_AXI_RDY_ENA(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) +#define MH_DEBUG_REG22_GET_RBBM_MH_clk_en_override(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG22_GET_CNT_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CNT_q_MASK) >> MH_DEBUG_REG22_CNT_q_SHIFT) +#define MH_DEBUG_REG22_GET_TCD_EMPTY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG22_GET_TC_ROQ_EMPTY(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG22_GET_MH_BUSY_d(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_BUSY_d_MASK) >> MH_DEBUG_REG22_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG22_GET_ANY_CLNT_BUSY(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG22_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG22_GET_CP_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CP_SEND_q_MASK) >> MH_DEBUG_REG22_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_CP_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CP_RTR_q_MASK) >> MH_DEBUG_REG22_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_VGT_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_SEND_q_MASK) >> MH_DEBUG_REG22_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_VGT_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_RTR_q_MASK) >> MH_DEBUG_REG22_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_TC_ROQ_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_TC_ROQ_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_RB_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RB_SEND_q_MASK) >> MH_DEBUG_REG22_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_RB_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RB_RTR_q_MASK) >> MH_DEBUG_REG22_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_RDC_VALID(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_VALID_MASK) >> MH_DEBUG_REG22_RDC_VALID_SHIFT) +#define MH_DEBUG_REG22_GET_RDC_RLAST(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_RLAST_MASK) >> MH_DEBUG_REG22_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG22_GET_TLBMISS_VALID(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TLBMISS_VALID_MASK) >> MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG22_GET_BRC_VALID(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BRC_VALID_MASK) >> MH_DEBUG_REG22_BRC_VALID_SHIFT) + +#define MH_DEBUG_REG22_SET_CIB_MH_axi_halt_req(mh_debug_reg22_reg, cib_mh_axi_halt_req) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) | (cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_axi_halt_ack(mh_debug_reg22_reg, mh_cib_axi_halt_ack) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) | (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) +#define MH_DEBUG_REG22_SET_MH_RBBM_busy(mh_debug_reg22_reg, mh_rbbm_busy) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_mh_clk_en_int(mh_debug_reg22_reg, mh_cib_mh_clk_en_int) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg22_reg, mh_cib_mmu_clk_en_int) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22_reg, mh_cib_tcroq_clk_en_int) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_SET_GAT_CLK_ENA(mh_debug_reg22_reg, gat_clk_ena) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG22_SET_AXI_RDY_ENA(mh_debug_reg22_reg, axi_rdy_ena) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) +#define MH_DEBUG_REG22_SET_RBBM_MH_clk_en_override(mh_debug_reg22_reg, rbbm_mh_clk_en_override) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG22_SET_CNT_q(mh_debug_reg22_reg, cnt_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT) +#define MH_DEBUG_REG22_SET_TCD_EMPTY_q(mh_debug_reg22_reg, tcd_empty_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG22_SET_TC_ROQ_EMPTY(mh_debug_reg22_reg, tc_roq_empty) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG22_SET_MH_BUSY_d(mh_debug_reg22_reg, mh_busy_d) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG22_SET_ANY_CLNT_BUSY(mh_debug_reg22_reg, any_clnt_busy) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG22_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22_reg, mh_mmu_invalidate_invalidate_all) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG22_SET_CP_SEND_q(mh_debug_reg22_reg, cp_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_CP_RTR_q(mh_debug_reg22_reg, cp_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_VGT_SEND_q(mh_debug_reg22_reg, vgt_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_VGT_RTR_q(mh_debug_reg22_reg, vgt_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_TC_ROQ_SEND_q(mh_debug_reg22_reg, tc_roq_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_TC_ROQ_RTR_q(mh_debug_reg22_reg, tc_roq_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_RB_SEND_q(mh_debug_reg22_reg, rb_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_RB_RTR_q(mh_debug_reg22_reg, rb_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_RDC_VALID(mh_debug_reg22_reg, rdc_valid) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT) +#define MH_DEBUG_REG22_SET_RDC_RLAST(mh_debug_reg22_reg, rdc_rlast) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG22_SET_TLBMISS_VALID(mh_debug_reg22_reg, tlbmiss_valid) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG22_SET_BRC_VALID(mh_debug_reg22_reg, brc_valid) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int cib_mh_axi_halt_req : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE; + unsigned int mh_cib_axi_halt_ack : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG22_MH_RBBM_busy_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE; + unsigned int cnt_q : MH_DEBUG_REG22_CNT_q_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG22_MH_BUSY_d_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG22_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG22_CP_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG22_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG22_VGT_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG22_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG22_RB_RTR_q_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG22_RDC_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG22_RDC_RLAST_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG22_TLBMISS_VALID_SIZE; + unsigned int brc_valid : MH_DEBUG_REG22_BRC_VALID_SIZE; + } mh_debug_reg22_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int brc_valid : MH_DEBUG_REG22_BRC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG22_TLBMISS_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG22_RDC_RLAST_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG22_RDC_VALID_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG22_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG22_RB_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG22_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG22_VGT_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG22_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG22_CP_SEND_q_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG22_MH_BUSY_d_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE; + unsigned int cnt_q : MH_DEBUG_REG22_CNT_q_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG22_MH_RBBM_busy_SIZE; + unsigned int mh_cib_axi_halt_ack : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE; + unsigned int cib_mh_axi_halt_req : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE; + } mh_debug_reg22_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg22_t f; +} mh_debug_reg22_u; + + +/* + * MH_DEBUG_REG23 struct + */ + +#define MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE 3 +#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG23_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG23_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG23_ARB_WINNER_q_SIZE 3 +#define MH_DEBUG_REG23_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG23_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG23_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG23_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG23_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG23_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG23_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG23_TCHOLD_IP_q_SIZE 1 + +#define MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT 0 +#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT 3 +#define MH_DEBUG_REG23_EFF1_WINNER_SHIFT 6 +#define MH_DEBUG_REG23_ARB_WINNER_SHIFT 9 +#define MH_DEBUG_REG23_ARB_WINNER_q_SHIFT 12 +#define MH_DEBUG_REG23_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG23_KILL_EFF1_SHIFT 16 +#define MH_DEBUG_REG23_ARB_HOLD_SHIFT 17 +#define MH_DEBUG_REG23_ARB_RTR_q_SHIFT 18 +#define MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT 19 +#define MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT 20 +#define MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT 21 +#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT 22 +#define MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT 23 +#define MH_DEBUG_REG23_ARB_QUAL_SHIFT 24 +#define MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT 25 +#define MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT 26 +#define MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT 27 +#define MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT 28 +#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT 29 +#define MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT 30 +#define MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT 31 + +#define MH_DEBUG_REG23_EFF2_FP_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK 0x00000038 +#define MH_DEBUG_REG23_EFF1_WINNER_MASK 0x000001c0 +#define MH_DEBUG_REG23_ARB_WINNER_MASK 0x00000e00 +#define MH_DEBUG_REG23_ARB_WINNER_q_MASK 0x00007000 +#define MH_DEBUG_REG23_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG23_KILL_EFF1_MASK 0x00010000 +#define MH_DEBUG_REG23_ARB_HOLD_MASK 0x00020000 +#define MH_DEBUG_REG23_ARB_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG23_CP_SEND_QUAL_MASK 0x00080000 +#define MH_DEBUG_REG23_VGT_SEND_QUAL_MASK 0x00100000 +#define MH_DEBUG_REG23_TC_SEND_QUAL_MASK 0x00200000 +#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK 0x00400000 +#define MH_DEBUG_REG23_RB_SEND_QUAL_MASK 0x00800000 +#define MH_DEBUG_REG23_ARB_QUAL_MASK 0x01000000 +#define MH_DEBUG_REG23_CP_EFF1_REQ_MASK 0x02000000 +#define MH_DEBUG_REG23_VGT_EFF1_REQ_MASK 0x04000000 +#define MH_DEBUG_REG23_TC_EFF1_REQ_MASK 0x08000000 +#define MH_DEBUG_REG23_RB_EFF1_REQ_MASK 0x10000000 +#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK 0x20000000 +#define MH_DEBUG_REG23_TCD_NEARFULL_q_MASK 0x40000000 +#define MH_DEBUG_REG23_TCHOLD_IP_q_MASK 0x80000000 + +#define MH_DEBUG_REG23_MASK \ + (MH_DEBUG_REG23_EFF2_FP_WINNER_MASK | \ + MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG23_EFF1_WINNER_MASK | \ + MH_DEBUG_REG23_ARB_WINNER_MASK | \ + MH_DEBUG_REG23_ARB_WINNER_q_MASK | \ + MH_DEBUG_REG23_EFF1_WIN_MASK | \ + MH_DEBUG_REG23_KILL_EFF1_MASK | \ + MH_DEBUG_REG23_ARB_HOLD_MASK | \ + MH_DEBUG_REG23_ARB_RTR_q_MASK | \ + MH_DEBUG_REG23_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG23_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_ARB_QUAL_MASK | \ + MH_DEBUG_REG23_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG23_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG23_TCHOLD_IP_q_MASK) + +#define MH_DEBUG_REG23(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, any_same_row_bank, tcd_nearfull_q, tchold_ip_q) \ + ((eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) | \ + (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) | \ + (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT) | \ + (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT) | \ + (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT)) + +#define MH_DEBUG_REG23_GET_EFF2_FP_WINNER(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG23_GET_EFF2_LRU_WINNER_out(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG23_GET_EFF1_WINNER(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WINNER_MASK) >> MH_DEBUG_REG23_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_WINNER(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_MASK) >> MH_DEBUG_REG23_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_WINNER_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_q_MASK) >> MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG23_GET_EFF1_WIN(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WIN_MASK) >> MH_DEBUG_REG23_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG23_GET_KILL_EFF1(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_KILL_EFF1_MASK) >> MH_DEBUG_REG23_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_HOLD(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_HOLD_MASK) >> MH_DEBUG_REG23_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_RTR_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_RTR_q_MASK) >> MH_DEBUG_REG23_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG23_GET_CP_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_VGT_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_TC_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_TC_SEND_EFF1_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_RB_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_QUAL_MASK) >> MH_DEBUG_REG23_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_CP_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_VGT_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_TC_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_RB_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_ANY_SAME_ROW_BANK(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG23_GET_TCD_NEARFULL_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG23_GET_TCHOLD_IP_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT) + +#define MH_DEBUG_REG23_SET_EFF2_FP_WINNER(mh_debug_reg23_reg, eff2_fp_winner) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG23_SET_EFF2_LRU_WINNER_out(mh_debug_reg23_reg, eff2_lru_winner_out) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG23_SET_EFF1_WINNER(mh_debug_reg23_reg, eff1_winner) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_WINNER(mh_debug_reg23_reg, arb_winner) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_WINNER_q(mh_debug_reg23_reg, arb_winner_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG23_SET_EFF1_WIN(mh_debug_reg23_reg, eff1_win) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG23_SET_KILL_EFF1(mh_debug_reg23_reg, kill_eff1) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_HOLD(mh_debug_reg23_reg, arb_hold) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_RTR_q(mh_debug_reg23_reg, arb_rtr_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG23_SET_CP_SEND_QUAL(mh_debug_reg23_reg, cp_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_VGT_SEND_QUAL(mh_debug_reg23_reg, vgt_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_TC_SEND_QUAL(mh_debug_reg23_reg, tc_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_TC_SEND_EFF1_QUAL(mh_debug_reg23_reg, tc_send_eff1_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_RB_SEND_QUAL(mh_debug_reg23_reg, rb_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_QUAL(mh_debug_reg23_reg, arb_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_CP_EFF1_REQ(mh_debug_reg23_reg, cp_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_VGT_EFF1_REQ(mh_debug_reg23_reg, vgt_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_TC_EFF1_REQ(mh_debug_reg23_reg, tc_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_RB_EFF1_REQ(mh_debug_reg23_reg, rb_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_ANY_SAME_ROW_BANK(mh_debug_reg23_reg, any_same_row_bank) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG23_SET_TCD_NEARFULL_q(mh_debug_reg23_reg, tcd_nearfull_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG23_SET_TCHOLD_IP_q(mh_debug_reg23_reg, tchold_ip_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int eff2_fp_winner : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG23_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG23_ARB_WINNER_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG23_ARB_WINNER_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG23_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG23_KILL_EFF1_SIZE; + unsigned int arb_hold : MH_DEBUG_REG23_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG23_ARB_RTR_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG23_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE; + } mh_debug_reg23_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int tchold_ip_q : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG23_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG23_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG23_ARB_HOLD_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG23_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG23_EFF1_WIN_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG23_ARB_WINNER_q_SIZE; + unsigned int arb_winner : MH_DEBUG_REG23_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG23_EFF1_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff2_fp_winner : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE; + } mh_debug_reg23_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg23_t f; +} mh_debug_reg23_u; + + +/* + * MH_DEBUG_REG24 struct + */ + +#define MH_DEBUG_REG24_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG24_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG24_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG24_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG24_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG24_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG24_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG24_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG24_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE 10 + +#define MH_DEBUG_REG24_EFF1_WINNER_SHIFT 0 +#define MH_DEBUG_REG24_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT 6 +#define MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT 7 +#define MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT 8 +#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT 9 +#define MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT 10 +#define MH_DEBUG_REG24_ARB_QUAL_SHIFT 11 +#define MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT 12 +#define MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT 13 +#define MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT 14 +#define MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT 15 +#define MH_DEBUG_REG24_EFF1_WIN_SHIFT 16 +#define MH_DEBUG_REG24_KILL_EFF1_SHIFT 17 +#define MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT 18 +#define MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT 19 +#define MH_DEBUG_REG24_ARB_HOLD_SHIFT 20 +#define MH_DEBUG_REG24_ARB_RTR_q_SHIFT 21 +#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22 + +#define MH_DEBUG_REG24_EFF1_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG24_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG24_CP_SEND_QUAL_MASK 0x00000040 +#define MH_DEBUG_REG24_VGT_SEND_QUAL_MASK 0x00000080 +#define MH_DEBUG_REG24_TC_SEND_QUAL_MASK 0x00000100 +#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK 0x00000200 +#define MH_DEBUG_REG24_RB_SEND_QUAL_MASK 0x00000400 +#define MH_DEBUG_REG24_ARB_QUAL_MASK 0x00000800 +#define MH_DEBUG_REG24_CP_EFF1_REQ_MASK 0x00001000 +#define MH_DEBUG_REG24_VGT_EFF1_REQ_MASK 0x00002000 +#define MH_DEBUG_REG24_TC_EFF1_REQ_MASK 0x00004000 +#define MH_DEBUG_REG24_RB_EFF1_REQ_MASK 0x00008000 +#define MH_DEBUG_REG24_EFF1_WIN_MASK 0x00010000 +#define MH_DEBUG_REG24_KILL_EFF1_MASK 0x00020000 +#define MH_DEBUG_REG24_TCD_NEARFULL_q_MASK 0x00040000 +#define MH_DEBUG_REG24_TC_ARB_HOLD_MASK 0x00080000 +#define MH_DEBUG_REG24_ARB_HOLD_MASK 0x00100000 +#define MH_DEBUG_REG24_ARB_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000 + +#define MH_DEBUG_REG24_MASK \ + (MH_DEBUG_REG24_EFF1_WINNER_MASK | \ + MH_DEBUG_REG24_ARB_WINNER_MASK | \ + MH_DEBUG_REG24_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG24_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_ARB_QUAL_MASK | \ + MH_DEBUG_REG24_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_EFF1_WIN_MASK | \ + MH_DEBUG_REG24_KILL_EFF1_MASK | \ + MH_DEBUG_REG24_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG24_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG24_ARB_HOLD_MASK | \ + MH_DEBUG_REG24_ARB_RTR_q_MASK | \ + MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) + +#define MH_DEBUG_REG24(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \ + ((eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) | \ + (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) | \ + (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) | \ + (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT) | \ + (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT)) + +#define MH_DEBUG_REG24_GET_EFF1_WINNER(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WINNER_MASK) >> MH_DEBUG_REG24_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_WINNER(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_WINNER_MASK) >> MH_DEBUG_REG24_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG24_GET_CP_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_VGT_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_TC_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_TC_SEND_EFF1_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_RB_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_QUAL_MASK) >> MH_DEBUG_REG24_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_CP_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_VGT_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_TC_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_RB_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_EFF1_WIN(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WIN_MASK) >> MH_DEBUG_REG24_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG24_GET_KILL_EFF1(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_KILL_EFF1_MASK) >> MH_DEBUG_REG24_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG24_GET_TCD_NEARFULL_q(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG24_GET_TC_ARB_HOLD(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_HOLD(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_HOLD_MASK) >> MH_DEBUG_REG24_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_RTR_q(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_RTR_q_MASK) >> MH_DEBUG_REG24_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG24_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#define MH_DEBUG_REG24_SET_EFF1_WINNER(mh_debug_reg24_reg, eff1_winner) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_WINNER(mh_debug_reg24_reg, arb_winner) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG24_SET_CP_SEND_QUAL(mh_debug_reg24_reg, cp_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_VGT_SEND_QUAL(mh_debug_reg24_reg, vgt_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_TC_SEND_QUAL(mh_debug_reg24_reg, tc_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_TC_SEND_EFF1_QUAL(mh_debug_reg24_reg, tc_send_eff1_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_RB_SEND_QUAL(mh_debug_reg24_reg, rb_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_QUAL(mh_debug_reg24_reg, arb_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_CP_EFF1_REQ(mh_debug_reg24_reg, cp_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_VGT_EFF1_REQ(mh_debug_reg24_reg, vgt_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_TC_EFF1_REQ(mh_debug_reg24_reg, tc_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_RB_EFF1_REQ(mh_debug_reg24_reg, rb_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_EFF1_WIN(mh_debug_reg24_reg, eff1_win) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG24_SET_KILL_EFF1(mh_debug_reg24_reg, kill_eff1) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG24_SET_TCD_NEARFULL_q(mh_debug_reg24_reg, tcd_nearfull_q) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG24_SET_TC_ARB_HOLD(mh_debug_reg24_reg, tc_arb_hold) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_HOLD(mh_debug_reg24_reg, arb_hold) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_RTR_q(mh_debug_reg24_reg, arb_rtr_q) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG24_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24_reg, same_page_limit_count_q) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int eff1_winner : MH_DEBUG_REG24_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG24_ARB_WINNER_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG24_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG24_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG24_KILL_EFF1_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE; + unsigned int arb_hold : MH_DEBUG_REG24_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG24_ARB_RTR_q_SIZE; + unsigned int same_page_limit_count_q : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE; + } mh_debug_reg24_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int same_page_limit_count_q : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG24_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG24_ARB_HOLD_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG24_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG24_EFF1_WIN_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG24_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG24_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG24_EFF1_WINNER_SIZE; + } mh_debug_reg24_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg24_t f; +} mh_debug_reg24_u; + + +/* + * MH_DEBUG_REG25 struct + */ + +#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG25_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE 3 +#define MH_DEBUG_REG25_LEAST_RECENT_d_SIZE 3 +#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE 1 +#define MH_DEBUG_REG25_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG25_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG25_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG25_CLNT_REQ_SIZE 4 +#define MH_DEBUG_REG25_RECENT_d_0_SIZE 3 +#define MH_DEBUG_REG25_RECENT_d_1_SIZE 3 +#define MH_DEBUG_REG25_RECENT_d_2_SIZE 3 +#define MH_DEBUG_REG25_RECENT_d_3_SIZE 3 + +#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT 0 +#define MH_DEBUG_REG25_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT 6 +#define MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT 9 +#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT 12 +#define MH_DEBUG_REG25_ARB_HOLD_SHIFT 13 +#define MH_DEBUG_REG25_ARB_RTR_q_SHIFT 14 +#define MH_DEBUG_REG25_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG25_CLNT_REQ_SHIFT 16 +#define MH_DEBUG_REG25_RECENT_d_0_SHIFT 20 +#define MH_DEBUG_REG25_RECENT_d_1_SHIFT 23 +#define MH_DEBUG_REG25_RECENT_d_2_SHIFT 26 +#define MH_DEBUG_REG25_RECENT_d_3_SHIFT 29 + +#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK 0x00000007 +#define MH_DEBUG_REG25_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK 0x000001c0 +#define MH_DEBUG_REG25_LEAST_RECENT_d_MASK 0x00000e00 +#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK 0x00001000 +#define MH_DEBUG_REG25_ARB_HOLD_MASK 0x00002000 +#define MH_DEBUG_REG25_ARB_RTR_q_MASK 0x00004000 +#define MH_DEBUG_REG25_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG25_CLNT_REQ_MASK 0x000f0000 +#define MH_DEBUG_REG25_RECENT_d_0_MASK 0x00700000 +#define MH_DEBUG_REG25_RECENT_d_1_MASK 0x03800000 +#define MH_DEBUG_REG25_RECENT_d_2_MASK 0x1c000000 +#define MH_DEBUG_REG25_RECENT_d_3_MASK 0xe0000000 + +#define MH_DEBUG_REG25_MASK \ + (MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG25_ARB_WINNER_MASK | \ + MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK | \ + MH_DEBUG_REG25_LEAST_RECENT_d_MASK | \ + MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK | \ + MH_DEBUG_REG25_ARB_HOLD_MASK | \ + MH_DEBUG_REG25_ARB_RTR_q_MASK | \ + MH_DEBUG_REG25_EFF1_WIN_MASK | \ + MH_DEBUG_REG25_CLNT_REQ_MASK | \ + MH_DEBUG_REG25_RECENT_d_0_MASK | \ + MH_DEBUG_REG25_RECENT_d_1_MASK | \ + MH_DEBUG_REG25_RECENT_d_2_MASK | \ + MH_DEBUG_REG25_RECENT_d_3_MASK) + +#define MH_DEBUG_REG25(eff2_lru_winner_out, arb_winner, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, eff1_win, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3) \ + ((eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) | \ + (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT) | \ + (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) | \ + (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) | \ + (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) | \ + (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT) | \ + (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT) | \ + (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT) | \ + (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT) | \ + (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT) | \ + (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT)) + +#define MH_DEBUG_REG25_GET_EFF2_LRU_WINNER_out(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG25_GET_ARB_WINNER(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_WINNER_MASK) >> MH_DEBUG_REG25_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG25_GET_LEAST_RECENT_INDEX_d(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG25_GET_LEAST_RECENT_d(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG25_GET_UPDATE_RECENT_STACK_d(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG25_GET_ARB_HOLD(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_HOLD_MASK) >> MH_DEBUG_REG25_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG25_GET_ARB_RTR_q(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_RTR_q_MASK) >> MH_DEBUG_REG25_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG25_GET_EFF1_WIN(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_EFF1_WIN_MASK) >> MH_DEBUG_REG25_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG25_GET_CLNT_REQ(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_CLNT_REQ_MASK) >> MH_DEBUG_REG25_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_0(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_0_MASK) >> MH_DEBUG_REG25_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_1(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_1_MASK) >> MH_DEBUG_REG25_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_2(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_2_MASK) >> MH_DEBUG_REG25_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_3(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_3_MASK) >> MH_DEBUG_REG25_RECENT_d_3_SHIFT) + +#define MH_DEBUG_REG25_SET_EFF2_LRU_WINNER_out(mh_debug_reg25_reg, eff2_lru_winner_out) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG25_SET_ARB_WINNER(mh_debug_reg25_reg, arb_winner) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG25_SET_LEAST_RECENT_INDEX_d(mh_debug_reg25_reg, least_recent_index_d) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG25_SET_LEAST_RECENT_d(mh_debug_reg25_reg, least_recent_d) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG25_SET_UPDATE_RECENT_STACK_d(mh_debug_reg25_reg, update_recent_stack_d) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG25_SET_ARB_HOLD(mh_debug_reg25_reg, arb_hold) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG25_SET_ARB_RTR_q(mh_debug_reg25_reg, arb_rtr_q) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG25_SET_EFF1_WIN(mh_debug_reg25_reg, eff1_win) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG25_SET_CLNT_REQ(mh_debug_reg25_reg, clnt_req) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_0(mh_debug_reg25_reg, recent_d_0) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_1(mh_debug_reg25_reg, recent_d_1) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_2(mh_debug_reg25_reg, recent_d_2) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_3(mh_debug_reg25_reg, recent_d_3) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int eff2_lru_winner_out : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE; + unsigned int arb_winner : MH_DEBUG_REG25_ARB_WINNER_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE; + unsigned int arb_hold : MH_DEBUG_REG25_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG25_ARB_RTR_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG25_EFF1_WIN_SIZE; + unsigned int clnt_req : MH_DEBUG_REG25_CLNT_REQ_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG25_RECENT_d_0_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG25_RECENT_d_1_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG25_RECENT_d_2_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG25_RECENT_d_3_SIZE; + } mh_debug_reg25_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int recent_d_3 : MH_DEBUG_REG25_RECENT_d_3_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG25_RECENT_d_2_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG25_RECENT_d_1_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG25_RECENT_d_0_SIZE; + unsigned int clnt_req : MH_DEBUG_REG25_CLNT_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG25_EFF1_WIN_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG25_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG25_ARB_HOLD_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE; + unsigned int arb_winner : MH_DEBUG_REG25_ARB_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE; + } mh_debug_reg25_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg25_t f; +} mh_debug_reg25_u; + + +/* + * MH_DEBUG_REG26 struct + */ + +#define MH_DEBUG_REG26_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG26_TCHOLD_IP_q_SIZE 1 +#define MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE 3 +#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE 7 +#define MH_DEBUG_REG26_WBURST_ACTIVE_SIZE 1 +#define MH_DEBUG_REG26_WLAST_q_SIZE 1 +#define MH_DEBUG_REG26_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG26_WBURST_CNT_q_SIZE 3 +#define MH_DEBUG_REG26_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG26_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG26_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG26_ARB_WINNER_SIZE 3 + +#define MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT 0 +#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT 1 +#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT 2 +#define MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT 3 +#define MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT 4 +#define MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT 5 +#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 9 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 10 +#define MH_DEBUG_REG26_TC_MH_written_SHIFT 11 +#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT 12 +#define MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT 19 +#define MH_DEBUG_REG26_WLAST_q_SHIFT 20 +#define MH_DEBUG_REG26_WBURST_IP_q_SHIFT 21 +#define MH_DEBUG_REG26_WBURST_CNT_q_SHIFT 22 +#define MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT 25 +#define MH_DEBUG_REG26_CP_MH_write_SHIFT 26 +#define MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT 27 +#define MH_DEBUG_REG26_ARB_WINNER_SHIFT 28 + +#define MH_DEBUG_REG26_TC_ARB_HOLD_MASK 0x00000001 +#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002 +#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004 +#define MH_DEBUG_REG26_TCD_NEARFULL_q_MASK 0x00000008 +#define MH_DEBUG_REG26_TCHOLD_IP_q_MASK 0x00000010 +#define MH_DEBUG_REG26_TCHOLD_CNT_q_MASK 0x000000e0 +#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00000200 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG26_TC_MH_written_MASK 0x00000800 +#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK 0x0007f000 +#define MH_DEBUG_REG26_WBURST_ACTIVE_MASK 0x00080000 +#define MH_DEBUG_REG26_WLAST_q_MASK 0x00100000 +#define MH_DEBUG_REG26_WBURST_IP_q_MASK 0x00200000 +#define MH_DEBUG_REG26_WBURST_CNT_q_MASK 0x01c00000 +#define MH_DEBUG_REG26_CP_SEND_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG26_CP_MH_write_MASK 0x04000000 +#define MH_DEBUG_REG26_RB_SEND_QUAL_MASK 0x08000000 +#define MH_DEBUG_REG26_ARB_WINNER_MASK 0x70000000 + +#define MH_DEBUG_REG26_MASK \ + (MH_DEBUG_REG26_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG26_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG26_TCHOLD_IP_q_MASK | \ + MH_DEBUG_REG26_TCHOLD_CNT_q_MASK | \ + MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG26_TC_MH_written_MASK | \ + MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK | \ + MH_DEBUG_REG26_WBURST_ACTIVE_MASK | \ + MH_DEBUG_REG26_WLAST_q_MASK | \ + MH_DEBUG_REG26_WBURST_IP_q_MASK | \ + MH_DEBUG_REG26_WBURST_CNT_q_MASK | \ + MH_DEBUG_REG26_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG26_CP_MH_write_MASK | \ + MH_DEBUG_REG26_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG26_ARB_WINNER_MASK) + +#define MH_DEBUG_REG26(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, arb_winner) \ + ((tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) | \ + (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \ + (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) | \ + (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) | \ + (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT) | \ + (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) | \ + (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) | \ + (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT) | \ + (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) | \ + (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT)) + +#define MH_DEBUG_REG26_GET_TC_ARB_HOLD(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG26_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_NEARFULL_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCHOLD_IP_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCHOLD_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_MH_written(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_MH_written_MASK) >> MH_DEBUG_REG26_TC_MH_written_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_FULLNESS_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_WBURST_ACTIVE(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG26_GET_WLAST_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WLAST_q_MASK) >> MH_DEBUG_REG26_WLAST_q_SHIFT) +#define MH_DEBUG_REG26_GET_WBURST_IP_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_IP_q_MASK) >> MH_DEBUG_REG26_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG26_GET_WBURST_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_CNT_q_MASK) >> MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_CP_SEND_QUAL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_GET_CP_MH_write(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_MH_write_MASK) >> MH_DEBUG_REG26_CP_MH_write_SHIFT) +#define MH_DEBUG_REG26_GET_RB_SEND_QUAL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_GET_ARB_WINNER(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_ARB_WINNER_MASK) >> MH_DEBUG_REG26_ARB_WINNER_SHIFT) + +#define MH_DEBUG_REG26_SET_TC_ARB_HOLD(mh_debug_reg26_reg, tc_arb_hold) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG26_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_noroq_same_row_bank) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_roq_same_row_bank) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_NEARFULL_q(mh_debug_reg26_reg, tcd_nearfull_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCHOLD_IP_q(mh_debug_reg26_reg, tchold_ip_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCHOLD_CNT_q(mh_debug_reg26_reg, tchold_cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26_reg, mh_arbiter_config_tc_reorder_enable) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_MH_written(mh_debug_reg26_reg, tc_mh_written) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_FULLNESS_CNT_q(mh_debug_reg26_reg, tcd_fullness_cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_WBURST_ACTIVE(mh_debug_reg26_reg, wburst_active) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG26_SET_WLAST_q(mh_debug_reg26_reg, wlast_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT) +#define MH_DEBUG_REG26_SET_WBURST_IP_q(mh_debug_reg26_reg, wburst_ip_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG26_SET_WBURST_CNT_q(mh_debug_reg26_reg, wburst_cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_CP_SEND_QUAL(mh_debug_reg26_reg, cp_send_qual) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_SET_CP_MH_write(mh_debug_reg26_reg, cp_mh_write) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT) +#define MH_DEBUG_REG26_SET_RB_SEND_QUAL(mh_debug_reg26_reg, rb_send_qual) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_SET_ARB_WINNER(mh_debug_reg26_reg, arb_winner) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int tc_arb_hold : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG26_TC_MH_written_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE; + unsigned int wlast_q : MH_DEBUG_REG26_WLAST_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG26_WBURST_IP_q_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG26_WBURST_CNT_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG26_CP_MH_write_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG26_ARB_WINNER_SIZE; + unsigned int : 1; + } mh_debug_reg26_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int : 1; + unsigned int arb_winner : MH_DEBUG_REG26_ARB_WINNER_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG26_CP_MH_write_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG26_WBURST_CNT_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG26_WBURST_IP_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG26_WLAST_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG26_TC_MH_written_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE; + } mh_debug_reg26_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg26_t f; +} mh_debug_reg26_u; + + +/* + * MH_DEBUG_REG27 struct + */ + +#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE 26 +#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26 + +#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK 0x03ffffff +#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000 + +#define MH_DEBUG_REG27_MASK \ + (MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK | \ + MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG27(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \ + ((rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG27_GET_RF_ARBITER_CONFIG_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG27_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG27_SET_RF_ARBITER_CONFIG_q(mh_debug_reg27_reg, rf_arbiter_config_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG27_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int rf_arbiter_config_q : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 3; + } mh_debug_reg27_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int : 3; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int rf_arbiter_config_q : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE; + } mh_debug_reg27_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg27_t f; +} mh_debug_reg27_u; + + +/* + * MH_DEBUG_REG28 struct + */ + +#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG28_ROQ_MARK_q_SIZE 8 +#define MH_DEBUG_REG28_ROQ_VALID_q_SIZE 8 +#define MH_DEBUG_REG28_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG28_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG28_ROQ_MARK_q_SHIFT 8 +#define MH_DEBUG_REG28_ROQ_VALID_q_SHIFT 16 +#define MH_DEBUG_REG28_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG28_ROQ_MARK_q_MASK 0x0000ff00 +#define MH_DEBUG_REG28_ROQ_VALID_q_MASK 0x00ff0000 +#define MH_DEBUG_REG28_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG28_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG28_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG28_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG28_MASK \ + (MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG28_ROQ_MARK_q_MASK | \ + MH_DEBUG_REG28_ROQ_VALID_q_MASK | \ + MH_DEBUG_REG28_TC_MH_send_MASK | \ + MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG28_KILL_EFF1_MASK | \ + MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG28_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG28_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG28(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) | \ + (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG28_GET_SAME_ROW_BANK_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG28_GET_ROQ_MARK_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_MARK_q_MASK) >> MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG28_GET_ROQ_VALID_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_VALID_q_MASK) >> MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG28_GET_TC_MH_send(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_MH_send_MASK) >> MH_DEBUG_REG28_TC_MH_send_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_RTR_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG28_GET_ANY_SAME_ROW_BANK(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG28_GET_TC_EFF1_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_EMPTY(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_FULL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG28_SET_SAME_ROW_BANK_q(mh_debug_reg28_reg, same_row_bank_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG28_SET_ROQ_MARK_q(mh_debug_reg28_reg, roq_mark_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG28_SET_ROQ_VALID_q(mh_debug_reg28_reg, roq_valid_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG28_SET_TC_MH_send(mh_debug_reg28_reg, tc_mh_send) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_RTR_q(mh_debug_reg28_reg, tc_roq_rtr_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG28_SET_ANY_SAME_ROW_BANK(mh_debug_reg28_reg, any_same_row_bank) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG28_SET_TC_EFF1_QUAL(mh_debug_reg28_reg, tc_eff1_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_EMPTY(mh_debug_reg28_reg, tc_roq_empty) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_FULL(mh_debug_reg28_reg, tc_roq_full) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int same_row_bank_q : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG28_ROQ_MARK_q_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG28_ROQ_VALID_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG28_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE; + } mh_debug_reg28_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int tc_roq_full : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG28_TC_MH_send_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG28_ROQ_VALID_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG28_ROQ_MARK_q_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg28_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg28_t f; +} mh_debug_reg28_u; + + +/* + * MH_DEBUG_REG29 struct + */ + +#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG29_ROQ_MARK_d_SIZE 8 +#define MH_DEBUG_REG29_ROQ_VALID_d_SIZE 8 +#define MH_DEBUG_REG29_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG29_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG29_ROQ_MARK_d_SHIFT 8 +#define MH_DEBUG_REG29_ROQ_VALID_d_SHIFT 16 +#define MH_DEBUG_REG29_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG29_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG29_ROQ_MARK_d_MASK 0x0000ff00 +#define MH_DEBUG_REG29_ROQ_VALID_d_MASK 0x00ff0000 +#define MH_DEBUG_REG29_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG29_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG29_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG29_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG29_MASK \ + (MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG29_ROQ_MARK_d_MASK | \ + MH_DEBUG_REG29_ROQ_VALID_d_MASK | \ + MH_DEBUG_REG29_TC_MH_send_MASK | \ + MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG29_KILL_EFF1_MASK | \ + MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG29_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG29_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG29(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) | \ + (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG29_GET_SAME_ROW_BANK_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG29_GET_ROQ_MARK_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_MARK_d_MASK) >> MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG29_GET_ROQ_VALID_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_VALID_d_MASK) >> MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG29_GET_TC_MH_send(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_MH_send_MASK) >> MH_DEBUG_REG29_TC_MH_send_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_RTR_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG29_GET_KILL_EFF1(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_KILL_EFF1_MASK) >> MH_DEBUG_REG29_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG29_GET_ANY_SAME_ROW_BANK(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG29_GET_TC_EFF1_QUAL(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_EMPTY(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_FULL(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG29_SET_SAME_ROW_BANK_q(mh_debug_reg29_reg, same_row_bank_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG29_SET_ROQ_MARK_d(mh_debug_reg29_reg, roq_mark_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG29_SET_ROQ_VALID_d(mh_debug_reg29_reg, roq_valid_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG29_SET_TC_MH_send(mh_debug_reg29_reg, tc_mh_send) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_RTR_q(mh_debug_reg29_reg, tc_roq_rtr_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG29_SET_KILL_EFF1(mh_debug_reg29_reg, kill_eff1) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG29_SET_ANY_SAME_ROW_BANK(mh_debug_reg29_reg, any_same_row_bank) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG29_SET_TC_EFF1_QUAL(mh_debug_reg29_reg, tc_eff1_qual) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_EMPTY(mh_debug_reg29_reg, tc_roq_empty) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_FULL(mh_debug_reg29_reg, tc_roq_full) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int same_row_bank_q : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG29_ROQ_MARK_d_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG29_ROQ_VALID_d_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG29_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG29_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE; + } mh_debug_reg29_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int tc_roq_full : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG29_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG29_TC_MH_send_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG29_ROQ_VALID_d_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG29_ROQ_MARK_d_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg29_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg29_t f; +} mh_debug_reg29_u; + + +/* + * MH_DEBUG_REG30 struct + */ + +#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE 8 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE 8 + +#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT 0 +#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT 8 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT 16 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT 24 + +#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK 0x000000ff +#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK 0x0000ff00 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK 0xff000000 + +#define MH_DEBUG_REG30_MASK \ + (MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK | \ + MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) + +#define MH_DEBUG_REG30(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \ + ((same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) | \ + (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) | \ + (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) | \ + (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT)) + +#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_WIN(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_REQ(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT) + +#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, same_row_bank_win) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, same_row_bank_req) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, non_same_row_bank_win) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, non_same_row_bank_req) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int same_row_bank_win : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int non_same_row_bank_req : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE; + } mh_debug_reg30_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int non_same_row_bank_req : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE; + unsigned int same_row_bank_win : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE; + } mh_debug_reg30_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg30_t f; +} mh_debug_reg30_u; + + +/* + * MH_DEBUG_REG31 struct + */ + +#define MH_DEBUG_REG31_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE 1 +#define MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE 1 +#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE 1 +#define MH_DEBUG_REG31_ROQ_ADDR_0_SIZE 27 + +#define MH_DEBUG_REG31_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT 2 +#define MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT 3 +#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT 4 +#define MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT 5 + +#define MH_DEBUG_REG31_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG31_ROQ_MARK_q_0_MASK 0x00000004 +#define MH_DEBUG_REG31_ROQ_VALID_q_0_MASK 0x00000008 +#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK 0x00000010 +#define MH_DEBUG_REG31_ROQ_ADDR_0_MASK 0xffffffe0 + +#define MH_DEBUG_REG31_MASK \ + (MH_DEBUG_REG31_TC_MH_send_MASK | \ + MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG31_ROQ_MARK_q_0_MASK | \ + MH_DEBUG_REG31_ROQ_VALID_q_0_MASK | \ + MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK | \ + MH_DEBUG_REG31_ROQ_ADDR_0_MASK) + +#define MH_DEBUG_REG31(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \ + ((tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) | \ + (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) | \ + (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) | \ + (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT)) + +#define MH_DEBUG_REG31_GET_TC_MH_send(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_TC_MH_send_MASK) >> MH_DEBUG_REG31_TC_MH_send_SHIFT) +#define MH_DEBUG_REG31_GET_TC_ROQ_RTR_q(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG31_GET_ROQ_MARK_q_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG31_GET_ROQ_VALID_q_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG31_GET_SAME_ROW_BANK_q_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG31_GET_ROQ_ADDR_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT) + +#define MH_DEBUG_REG31_SET_TC_MH_send(mh_debug_reg31_reg, tc_mh_send) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT) +#define MH_DEBUG_REG31_SET_TC_ROQ_RTR_q(mh_debug_reg31_reg, tc_roq_rtr_q) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG31_SET_ROQ_MARK_q_0(mh_debug_reg31_reg, roq_mark_q_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG31_SET_ROQ_VALID_q_0(mh_debug_reg31_reg, roq_valid_q_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG31_SET_SAME_ROW_BANK_q_0(mh_debug_reg31_reg, same_row_bank_q_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG31_SET_ROQ_ADDR_0(mh_debug_reg31_reg, roq_addr_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int tc_mh_send : MH_DEBUG_REG31_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_addr_0 : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE; + } mh_debug_reg31_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int roq_addr_0 : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG31_TC_MH_send_SIZE; + } mh_debug_reg31_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg31_t f; +} mh_debug_reg31_u; + + +/* + * MH_DEBUG_REG32 struct + */ + +#define MH_DEBUG_REG32_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE 1 +#define MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE 1 +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE 1 +#define MH_DEBUG_REG32_ROQ_ADDR_1_SIZE 27 + +#define MH_DEBUG_REG32_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT 2 +#define MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT 3 +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT 4 +#define MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT 5 + +#define MH_DEBUG_REG32_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG32_ROQ_MARK_q_1_MASK 0x00000004 +#define MH_DEBUG_REG32_ROQ_VALID_q_1_MASK 0x00000008 +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK 0x00000010 +#define MH_DEBUG_REG32_ROQ_ADDR_1_MASK 0xffffffe0 + +#define MH_DEBUG_REG32_MASK \ + (MH_DEBUG_REG32_TC_MH_send_MASK | \ + MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG32_ROQ_MARK_q_1_MASK | \ + MH_DEBUG_REG32_ROQ_VALID_q_1_MASK | \ + MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK | \ + MH_DEBUG_REG32_ROQ_ADDR_1_MASK) + +#define MH_DEBUG_REG32(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \ + ((tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) | \ + (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) | \ + (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) | \ + (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT)) + +#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_MARK_q_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_VALID_q_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_ADDR_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT) + +#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_MARK_q_1(mh_debug_reg32_reg, roq_mark_q_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_VALID_q_1(mh_debug_reg32_reg, roq_valid_q_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q_1(mh_debug_reg32_reg, same_row_bank_q_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_ADDR_1(mh_debug_reg32_reg, roq_addr_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_addr_1 : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE; + } mh_debug_reg32_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int roq_addr_1 : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + } mh_debug_reg32_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg32_t f; +} mh_debug_reg32_u; + + +/* + * MH_DEBUG_REG33 struct + */ + +#define MH_DEBUG_REG33_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE 1 +#define MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE 1 +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE 1 +#define MH_DEBUG_REG33_ROQ_ADDR_2_SIZE 27 + +#define MH_DEBUG_REG33_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT 2 +#define MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT 3 +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT 4 +#define MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT 5 + +#define MH_DEBUG_REG33_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG33_ROQ_MARK_q_2_MASK 0x00000004 +#define MH_DEBUG_REG33_ROQ_VALID_q_2_MASK 0x00000008 +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK 0x00000010 +#define MH_DEBUG_REG33_ROQ_ADDR_2_MASK 0xffffffe0 + +#define MH_DEBUG_REG33_MASK \ + (MH_DEBUG_REG33_TC_MH_send_MASK | \ + MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG33_ROQ_MARK_q_2_MASK | \ + MH_DEBUG_REG33_ROQ_VALID_q_2_MASK | \ + MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK | \ + MH_DEBUG_REG33_ROQ_ADDR_2_MASK) + +#define MH_DEBUG_REG33(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \ + ((tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) | \ + (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) | \ + (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) | \ + (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT)) + +#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_MARK_q_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_VALID_q_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_ADDR_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT) + +#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_MARK_q_2(mh_debug_reg33_reg, roq_mark_q_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_VALID_q_2(mh_debug_reg33_reg, roq_valid_q_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q_2(mh_debug_reg33_reg, same_row_bank_q_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_ADDR_2(mh_debug_reg33_reg, roq_addr_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_addr_2 : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE; + } mh_debug_reg33_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int roq_addr_2 : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + } mh_debug_reg33_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg33_t f; +} mh_debug_reg33_u; + + +/* + * MH_DEBUG_REG34 struct + */ + +#define MH_DEBUG_REG34_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE 1 +#define MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE 1 +#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE 1 +#define MH_DEBUG_REG34_ROQ_ADDR_3_SIZE 27 + +#define MH_DEBUG_REG34_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT 2 +#define MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT 3 +#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT 4 +#define MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT 5 + +#define MH_DEBUG_REG34_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG34_ROQ_MARK_q_3_MASK 0x00000004 +#define MH_DEBUG_REG34_ROQ_VALID_q_3_MASK 0x00000008 +#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK 0x00000010 +#define MH_DEBUG_REG34_ROQ_ADDR_3_MASK 0xffffffe0 + +#define MH_DEBUG_REG34_MASK \ + (MH_DEBUG_REG34_TC_MH_send_MASK | \ + MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG34_ROQ_MARK_q_3_MASK | \ + MH_DEBUG_REG34_ROQ_VALID_q_3_MASK | \ + MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK | \ + MH_DEBUG_REG34_ROQ_ADDR_3_MASK) + +#define MH_DEBUG_REG34(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \ + ((tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) | \ + (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) | \ + (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) | \ + (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT)) + +#define MH_DEBUG_REG34_GET_TC_MH_send(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_TC_MH_send_MASK) >> MH_DEBUG_REG34_TC_MH_send_SHIFT) +#define MH_DEBUG_REG34_GET_TC_ROQ_RTR_q(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG34_GET_ROQ_MARK_q_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG34_GET_ROQ_VALID_q_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_q_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG34_GET_ROQ_ADDR_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT) + +#define MH_DEBUG_REG34_SET_TC_MH_send(mh_debug_reg34_reg, tc_mh_send) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT) +#define MH_DEBUG_REG34_SET_TC_ROQ_RTR_q(mh_debug_reg34_reg, tc_roq_rtr_q) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG34_SET_ROQ_MARK_q_3(mh_debug_reg34_reg, roq_mark_q_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG34_SET_ROQ_VALID_q_3(mh_debug_reg34_reg, roq_valid_q_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_q_3(mh_debug_reg34_reg, same_row_bank_q_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG34_SET_ROQ_ADDR_3(mh_debug_reg34_reg, roq_addr_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int tc_mh_send : MH_DEBUG_REG34_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_addr_3 : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE; + } mh_debug_reg34_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int roq_addr_3 : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG34_TC_MH_send_SIZE; + } mh_debug_reg34_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg34_t f; +} mh_debug_reg34_u; + + +/* + * MH_DEBUG_REG35 struct + */ + +#define MH_DEBUG_REG35_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE 1 +#define MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE 1 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE 1 +#define MH_DEBUG_REG35_ROQ_ADDR_4_SIZE 27 + +#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT 2 +#define MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT 3 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT 4 +#define MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT 5 + +#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG35_ROQ_MARK_q_4_MASK 0x00000004 +#define MH_DEBUG_REG35_ROQ_VALID_q_4_MASK 0x00000008 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK 0x00000010 +#define MH_DEBUG_REG35_ROQ_ADDR_4_MASK 0xffffffe0 + +#define MH_DEBUG_REG35_MASK \ + (MH_DEBUG_REG35_TC_MH_send_MASK | \ + MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG35_ROQ_MARK_q_4_MASK | \ + MH_DEBUG_REG35_ROQ_VALID_q_4_MASK | \ + MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK | \ + MH_DEBUG_REG35_ROQ_ADDR_4_MASK) + +#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \ + ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) | \ + (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) | \ + (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) | \ + (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT)) + +#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_MARK_q_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_VALID_q_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_ADDR_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT) + +#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_MARK_q_4(mh_debug_reg35_reg, roq_mark_q_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_VALID_q_4(mh_debug_reg35_reg, roq_valid_q_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_4(mh_debug_reg35_reg, same_row_bank_q_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_ADDR_4(mh_debug_reg35_reg, roq_addr_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_addr_4 : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE; + } mh_debug_reg35_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int roq_addr_4 : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + } mh_debug_reg35_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg35_t f; +} mh_debug_reg35_u; + + +/* + * MH_DEBUG_REG36 struct + */ + +#define MH_DEBUG_REG36_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE 1 +#define MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE 1 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE 1 +#define MH_DEBUG_REG36_ROQ_ADDR_5_SIZE 27 + +#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT 2 +#define MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT 3 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT 4 +#define MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT 5 + +#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG36_ROQ_MARK_q_5_MASK 0x00000004 +#define MH_DEBUG_REG36_ROQ_VALID_q_5_MASK 0x00000008 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK 0x00000010 +#define MH_DEBUG_REG36_ROQ_ADDR_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG36_MASK \ + (MH_DEBUG_REG36_TC_MH_send_MASK | \ + MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG36_ROQ_MARK_q_5_MASK | \ + MH_DEBUG_REG36_ROQ_VALID_q_5_MASK | \ + MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK | \ + MH_DEBUG_REG36_ROQ_ADDR_5_MASK) + +#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \ + ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) | \ + (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) | \ + (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) | \ + (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT)) + +#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_MARK_q_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_VALID_q_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_ADDR_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT) + +#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_MARK_q_5(mh_debug_reg36_reg, roq_mark_q_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_VALID_q_5(mh_debug_reg36_reg, roq_valid_q_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_5(mh_debug_reg36_reg, same_row_bank_q_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_ADDR_5(mh_debug_reg36_reg, roq_addr_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_addr_5 : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE; + } mh_debug_reg36_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int roq_addr_5 : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + } mh_debug_reg36_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg36_t f; +} mh_debug_reg36_u; + + +/* + * MH_DEBUG_REG37 struct + */ + +#define MH_DEBUG_REG37_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE 1 +#define MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE 1 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE 1 +#define MH_DEBUG_REG37_ROQ_ADDR_6_SIZE 27 + +#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT 2 +#define MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT 3 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT 4 +#define MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT 5 + +#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG37_ROQ_MARK_q_6_MASK 0x00000004 +#define MH_DEBUG_REG37_ROQ_VALID_q_6_MASK 0x00000008 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK 0x00000010 +#define MH_DEBUG_REG37_ROQ_ADDR_6_MASK 0xffffffe0 + +#define MH_DEBUG_REG37_MASK \ + (MH_DEBUG_REG37_TC_MH_send_MASK | \ + MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG37_ROQ_MARK_q_6_MASK | \ + MH_DEBUG_REG37_ROQ_VALID_q_6_MASK | \ + MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK | \ + MH_DEBUG_REG37_ROQ_ADDR_6_MASK) + +#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \ + ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) | \ + (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) | \ + (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) | \ + (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT)) + +#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_MARK_q_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_VALID_q_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_ADDR_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT) + +#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_MARK_q_6(mh_debug_reg37_reg, roq_mark_q_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_VALID_q_6(mh_debug_reg37_reg, roq_valid_q_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_6(mh_debug_reg37_reg, same_row_bank_q_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_ADDR_6(mh_debug_reg37_reg, roq_addr_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_addr_6 : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE; + } mh_debug_reg37_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int roq_addr_6 : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + } mh_debug_reg37_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg37_t f; +} mh_debug_reg37_u; + + +/* + * MH_DEBUG_REG38 struct + */ + +#define MH_DEBUG_REG38_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE 1 +#define MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE 1 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE 1 +#define MH_DEBUG_REG38_ROQ_ADDR_7_SIZE 27 + +#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT 2 +#define MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT 3 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT 4 +#define MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT 5 + +#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG38_ROQ_MARK_q_7_MASK 0x00000004 +#define MH_DEBUG_REG38_ROQ_VALID_q_7_MASK 0x00000008 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK 0x00000010 +#define MH_DEBUG_REG38_ROQ_ADDR_7_MASK 0xffffffe0 + +#define MH_DEBUG_REG38_MASK \ + (MH_DEBUG_REG38_TC_MH_send_MASK | \ + MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG38_ROQ_MARK_q_7_MASK | \ + MH_DEBUG_REG38_ROQ_VALID_q_7_MASK | \ + MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK | \ + MH_DEBUG_REG38_ROQ_ADDR_7_MASK) + +#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \ + ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) | \ + (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) | \ + (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) | \ + (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT)) + +#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_MARK_q_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_VALID_q_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_ADDR_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT) + +#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_MARK_q_7(mh_debug_reg38_reg, roq_mark_q_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_VALID_q_7(mh_debug_reg38_reg, roq_valid_q_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_7(mh_debug_reg38_reg, same_row_bank_q_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_ADDR_7(mh_debug_reg38_reg, roq_addr_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_addr_7 : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE; + } mh_debug_reg38_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int roq_addr_7 : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + } mh_debug_reg38_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg38_t f; +} mh_debug_reg38_u; + + +/* + * MH_DEBUG_REG39 struct + */ + +#define MH_DEBUG_REG39_ARB_WE_SIZE 1 +#define MH_DEBUG_REG39_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG39_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG39_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG39_ARB_BLEN_q_SIZE 1 +#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE 3 +#define MH_DEBUG_REG39_MMU_WE_SIZE 1 +#define MH_DEBUG_REG39_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG39_MMU_ID_SIZE 3 +#define MH_DEBUG_REG39_MMU_WRITE_SIZE 1 +#define MH_DEBUG_REG39_MMU_BLEN_SIZE 1 + +#define MH_DEBUG_REG39_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG39_MMU_RTR_SHIFT 1 +#define MH_DEBUG_REG39_ARB_ID_q_SHIFT 2 +#define MH_DEBUG_REG39_ARB_WRITE_q_SHIFT 5 +#define MH_DEBUG_REG39_ARB_BLEN_q_SHIFT 6 +#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT 7 +#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT 8 +#define MH_DEBUG_REG39_MMU_WE_SHIFT 11 +#define MH_DEBUG_REG39_ARQ_RTR_SHIFT 12 +#define MH_DEBUG_REG39_MMU_ID_SHIFT 13 +#define MH_DEBUG_REG39_MMU_WRITE_SHIFT 16 +#define MH_DEBUG_REG39_MMU_BLEN_SHIFT 17 + +#define MH_DEBUG_REG39_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG39_MMU_RTR_MASK 0x00000002 +#define MH_DEBUG_REG39_ARB_ID_q_MASK 0x0000001c +#define MH_DEBUG_REG39_ARB_WRITE_q_MASK 0x00000020 +#define MH_DEBUG_REG39_ARB_BLEN_q_MASK 0x00000040 +#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK 0x00000700 +#define MH_DEBUG_REG39_MMU_WE_MASK 0x00000800 +#define MH_DEBUG_REG39_ARQ_RTR_MASK 0x00001000 +#define MH_DEBUG_REG39_MMU_ID_MASK 0x0000e000 +#define MH_DEBUG_REG39_MMU_WRITE_MASK 0x00010000 +#define MH_DEBUG_REG39_MMU_BLEN_MASK 0x00020000 + +#define MH_DEBUG_REG39_MASK \ + (MH_DEBUG_REG39_ARB_WE_MASK | \ + MH_DEBUG_REG39_MMU_RTR_MASK | \ + MH_DEBUG_REG39_ARB_ID_q_MASK | \ + MH_DEBUG_REG39_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG39_ARB_BLEN_q_MASK | \ + MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG39_MMU_WE_MASK | \ + MH_DEBUG_REG39_ARQ_RTR_MASK | \ + MH_DEBUG_REG39_MMU_ID_MASK | \ + MH_DEBUG_REG39_MMU_WRITE_MASK | \ + MH_DEBUG_REG39_MMU_BLEN_MASK) + +#define MH_DEBUG_REG39(arb_we, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen) \ + ((arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) | \ + (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) | \ + (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT) | \ + (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT) | \ + (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT) | \ + (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT) | \ + (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT)) + +#define MH_DEBUG_REG39_GET_ARB_WE(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WE_MASK) >> MH_DEBUG_REG39_ARB_WE_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_RTR(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_RTR_MASK) >> MH_DEBUG_REG39_MMU_RTR_SHIFT) +#define MH_DEBUG_REG39_GET_ARB_ID_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_ID_q_MASK) >> MH_DEBUG_REG39_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG39_GET_ARB_WRITE_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WRITE_q_MASK) >> MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG39_GET_ARB_BLEN_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_BLEN_q_MASK) >> MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG39_GET_ARQ_CTRL_EMPTY(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG39_GET_ARQ_FIFO_CNT_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_WE(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WE_MASK) >> MH_DEBUG_REG39_MMU_WE_SHIFT) +#define MH_DEBUG_REG39_GET_ARQ_RTR(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_RTR_MASK) >> MH_DEBUG_REG39_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_ID(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_ID_MASK) >> MH_DEBUG_REG39_MMU_ID_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_WRITE(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WRITE_MASK) >> MH_DEBUG_REG39_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_BLEN(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_BLEN_MASK) >> MH_DEBUG_REG39_MMU_BLEN_SHIFT) + +#define MH_DEBUG_REG39_SET_ARB_WE(mh_debug_reg39_reg, arb_we) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_RTR(mh_debug_reg39_reg, mmu_rtr) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT) +#define MH_DEBUG_REG39_SET_ARB_ID_q(mh_debug_reg39_reg, arb_id_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG39_SET_ARB_WRITE_q(mh_debug_reg39_reg, arb_write_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG39_SET_ARB_BLEN_q(mh_debug_reg39_reg, arb_blen_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG39_SET_ARQ_CTRL_EMPTY(mh_debug_reg39_reg, arq_ctrl_empty) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG39_SET_ARQ_FIFO_CNT_q(mh_debug_reg39_reg, arq_fifo_cnt_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_WE(mh_debug_reg39_reg, mmu_we) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT) +#define MH_DEBUG_REG39_SET_ARQ_RTR(mh_debug_reg39_reg, arq_rtr) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_ID(mh_debug_reg39_reg, mmu_id) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_WRITE(mh_debug_reg39_reg, mmu_write) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_BLEN(mh_debug_reg39_reg, mmu_blen) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int arb_we : MH_DEBUG_REG39_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG39_MMU_RTR_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG39_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG39_ARB_WRITE_q_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG39_ARB_BLEN_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG39_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG39_ARQ_RTR_SIZE; + unsigned int mmu_id : MH_DEBUG_REG39_MMU_ID_SIZE; + unsigned int mmu_write : MH_DEBUG_REG39_MMU_WRITE_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG39_MMU_BLEN_SIZE; + unsigned int : 14; + } mh_debug_reg39_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int : 14; + unsigned int mmu_blen : MH_DEBUG_REG39_MMU_BLEN_SIZE; + unsigned int mmu_write : MH_DEBUG_REG39_MMU_WRITE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG39_MMU_ID_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG39_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG39_MMU_WE_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG39_ARB_BLEN_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG39_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG39_ARB_ID_q_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG39_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG39_ARB_WE_SIZE; + } mh_debug_reg39_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg39_t f; +} mh_debug_reg39_u; + + +/* + * MH_DEBUG_REG40 struct + */ + +#define MH_DEBUG_REG40_ARB_WE_SIZE 1 +#define MH_DEBUG_REG40_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG40_ARB_VAD_q_SIZE 28 + +#define MH_DEBUG_REG40_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG40_ARB_ID_q_SHIFT 1 +#define MH_DEBUG_REG40_ARB_VAD_q_SHIFT 4 + +#define MH_DEBUG_REG40_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG40_ARB_ID_q_MASK 0x0000000e +#define MH_DEBUG_REG40_ARB_VAD_q_MASK 0xfffffff0 + +#define MH_DEBUG_REG40_MASK \ + (MH_DEBUG_REG40_ARB_WE_MASK | \ + MH_DEBUG_REG40_ARB_ID_q_MASK | \ + MH_DEBUG_REG40_ARB_VAD_q_MASK) + +#define MH_DEBUG_REG40(arb_we, arb_id_q, arb_vad_q) \ + ((arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT) | \ + (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT)) + +#define MH_DEBUG_REG40_GET_ARB_WE(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_WE_MASK) >> MH_DEBUG_REG40_ARB_WE_SHIFT) +#define MH_DEBUG_REG40_GET_ARB_ID_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_ID_q_MASK) >> MH_DEBUG_REG40_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG40_GET_ARB_VAD_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_VAD_q_MASK) >> MH_DEBUG_REG40_ARB_VAD_q_SHIFT) + +#define MH_DEBUG_REG40_SET_ARB_WE(mh_debug_reg40_reg, arb_we) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT) +#define MH_DEBUG_REG40_SET_ARB_ID_q(mh_debug_reg40_reg, arb_id_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG40_SET_ARB_VAD_q(mh_debug_reg40_reg, arb_vad_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int arb_we : MH_DEBUG_REG40_ARB_WE_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG40_ARB_ID_q_SIZE; + unsigned int arb_vad_q : MH_DEBUG_REG40_ARB_VAD_q_SIZE; + } mh_debug_reg40_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int arb_vad_q : MH_DEBUG_REG40_ARB_VAD_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG40_ARB_ID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG40_ARB_WE_SIZE; + } mh_debug_reg40_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg40_t f; +} mh_debug_reg40_u; + + +/* + * MH_DEBUG_REG41 struct + */ + +#define MH_DEBUG_REG41_MMU_WE_SIZE 1 +#define MH_DEBUG_REG41_MMU_ID_SIZE 3 +#define MH_DEBUG_REG41_MMU_PAD_SIZE 28 + +#define MH_DEBUG_REG41_MMU_WE_SHIFT 0 +#define MH_DEBUG_REG41_MMU_ID_SHIFT 1 +#define MH_DEBUG_REG41_MMU_PAD_SHIFT 4 + +#define MH_DEBUG_REG41_MMU_WE_MASK 0x00000001 +#define MH_DEBUG_REG41_MMU_ID_MASK 0x0000000e +#define MH_DEBUG_REG41_MMU_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG41_MASK \ + (MH_DEBUG_REG41_MMU_WE_MASK | \ + MH_DEBUG_REG41_MMU_ID_MASK | \ + MH_DEBUG_REG41_MMU_PAD_MASK) + +#define MH_DEBUG_REG41(mmu_we, mmu_id, mmu_pad) \ + ((mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT) | \ + (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT) | \ + (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT)) + +#define MH_DEBUG_REG41_GET_MMU_WE(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_WE_MASK) >> MH_DEBUG_REG41_MMU_WE_SHIFT) +#define MH_DEBUG_REG41_GET_MMU_ID(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_ID_MASK) >> MH_DEBUG_REG41_MMU_ID_SHIFT) +#define MH_DEBUG_REG41_GET_MMU_PAD(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_PAD_MASK) >> MH_DEBUG_REG41_MMU_PAD_SHIFT) + +#define MH_DEBUG_REG41_SET_MMU_WE(mh_debug_reg41_reg, mmu_we) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT) +#define MH_DEBUG_REG41_SET_MMU_ID(mh_debug_reg41_reg, mmu_id) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT) +#define MH_DEBUG_REG41_SET_MMU_PAD(mh_debug_reg41_reg, mmu_pad) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int mmu_we : MH_DEBUG_REG41_MMU_WE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG41_MMU_ID_SIZE; + unsigned int mmu_pad : MH_DEBUG_REG41_MMU_PAD_SIZE; + } mh_debug_reg41_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int mmu_pad : MH_DEBUG_REG41_MMU_PAD_SIZE; + unsigned int mmu_id : MH_DEBUG_REG41_MMU_ID_SIZE; + unsigned int mmu_we : MH_DEBUG_REG41_MMU_WE_SIZE; + } mh_debug_reg41_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg41_t f; +} mh_debug_reg41_u; + + +/* + * MH_DEBUG_REG42 struct + */ + +#define MH_DEBUG_REG42_WDB_WE_SIZE 1 +#define MH_DEBUG_REG42_WDB_RTR_SKID_SIZE 1 +#define MH_DEBUG_REG42_ARB_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG42_ARB_WLAST_SIZE 1 +#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE 5 +#define MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE 1 +#define MH_DEBUG_REG42_WDB_WDC_WID_SIZE 3 +#define MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE 1 +#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE 8 + +#define MH_DEBUG_REG42_WDB_WE_SHIFT 0 +#define MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT 1 +#define MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT 2 +#define MH_DEBUG_REG42_ARB_WLAST_SHIFT 10 +#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT 11 +#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT 12 +#define MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT 17 +#define MH_DEBUG_REG42_WDB_WDC_WID_SHIFT 18 +#define MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT 21 +#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT 22 + +#define MH_DEBUG_REG42_WDB_WE_MASK 0x00000001 +#define MH_DEBUG_REG42_WDB_RTR_SKID_MASK 0x00000002 +#define MH_DEBUG_REG42_ARB_WSTRB_q_MASK 0x000003fc +#define MH_DEBUG_REG42_ARB_WLAST_MASK 0x00000400 +#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK 0x00000800 +#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK 0x0001f000 +#define MH_DEBUG_REG42_WDC_WDB_RE_q_MASK 0x00020000 +#define MH_DEBUG_REG42_WDB_WDC_WID_MASK 0x001c0000 +#define MH_DEBUG_REG42_WDB_WDC_WLAST_MASK 0x00200000 +#define MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK 0x3fc00000 + +#define MH_DEBUG_REG42_MASK \ + (MH_DEBUG_REG42_WDB_WE_MASK | \ + MH_DEBUG_REG42_WDB_RTR_SKID_MASK | \ + MH_DEBUG_REG42_ARB_WSTRB_q_MASK | \ + MH_DEBUG_REG42_ARB_WLAST_MASK | \ + MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG42_WDC_WDB_RE_q_MASK | \ + MH_DEBUG_REG42_WDB_WDC_WID_MASK | \ + MH_DEBUG_REG42_WDB_WDC_WLAST_MASK | \ + MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) + +#define MH_DEBUG_REG42(wdb_we, wdb_rtr_skid, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \ + ((wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT) | \ + (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) | \ + (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) | \ + (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT) | \ + (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) | \ + (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) | \ + (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) | \ + (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) | \ + (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) | \ + (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT)) + +#define MH_DEBUG_REG42_GET_WDB_WE(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WE_MASK) >> MH_DEBUG_REG42_WDB_WE_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_RTR_SKID(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_RTR_SKID_MASK) >> MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) +#define MH_DEBUG_REG42_GET_ARB_WSTRB_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG42_GET_ARB_WLAST(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WLAST_MASK) >> MH_DEBUG_REG42_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_CTRL_EMPTY(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_FIFO_CNT_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG42_GET_WDC_WDB_RE_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_WDC_WID(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WID_MASK) >> MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_WDC_WLAST(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_WDC_WSTRB(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT) + +#define MH_DEBUG_REG42_SET_WDB_WE(mh_debug_reg42_reg, wdb_we) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_RTR_SKID(mh_debug_reg42_reg, wdb_rtr_skid) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_RTR_SKID_MASK) | (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) +#define MH_DEBUG_REG42_SET_ARB_WSTRB_q(mh_debug_reg42_reg, arb_wstrb_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG42_SET_ARB_WLAST(mh_debug_reg42_reg, arb_wlast) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_CTRL_EMPTY(mh_debug_reg42_reg, wdb_ctrl_empty) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_FIFO_CNT_q(mh_debug_reg42_reg, wdb_fifo_cnt_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG42_SET_WDC_WDB_RE_q(mh_debug_reg42_reg, wdc_wdb_re_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_WDC_WID(mh_debug_reg42_reg, wdb_wdc_wid) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_WDC_WLAST(mh_debug_reg42_reg, wdb_wdc_wlast) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_WDC_WSTRB(mh_debug_reg42_reg, wdb_wdc_wstrb) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int wdb_we : MH_DEBUG_REG42_WDB_WE_SIZE; + unsigned int wdb_rtr_skid : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG42_ARB_WLAST_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG42_WDB_WDC_WID_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE; + unsigned int : 2; + } mh_debug_reg42_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int : 2; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG42_WDB_WDC_WID_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG42_ARB_WLAST_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE; + unsigned int wdb_rtr_skid : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE; + unsigned int wdb_we : MH_DEBUG_REG42_WDB_WE_SIZE; + } mh_debug_reg42_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg42_t f; +} mh_debug_reg42_u; + + +/* + * MH_DEBUG_REG43 struct + */ + +#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE 32 + +#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT 0 + +#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG43_MASK \ + (MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) + +#define MH_DEBUG_REG43(arb_wdata_q_31_0) \ + ((arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT)) + +#define MH_DEBUG_REG43_GET_ARB_WDATA_q_31_0(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) >> MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT) + +#define MH_DEBUG_REG43_SET_ARB_WDATA_q_31_0(mh_debug_reg43_reg, arb_wdata_q_31_0) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) | (arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_wdata_q_31_0 : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE; + } mh_debug_reg43_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_wdata_q_31_0 : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE; + } mh_debug_reg43_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg43_t f; +} mh_debug_reg43_u; + + +/* + * MH_DEBUG_REG44 struct + */ + +#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE 32 + +#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT 0 + +#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG44_MASK \ + (MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) + +#define MH_DEBUG_REG44(arb_wdata_q_63_32) \ + ((arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT)) + +#define MH_DEBUG_REG44_GET_ARB_WDATA_q_63_32(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) >> MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT) + +#define MH_DEBUG_REG44_SET_ARB_WDATA_q_63_32(mh_debug_reg44_reg, arb_wdata_q_63_32) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) | (arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_wdata_q_63_32 : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE; + } mh_debug_reg44_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_wdata_q_63_32 : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE; + } mh_debug_reg44_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg44_t f; +} mh_debug_reg44_u; + + +/* + * MH_DEBUG_REG45 struct + */ + +#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE 32 + +#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT 0 + +#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG45_MASK \ + (MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) + +#define MH_DEBUG_REG45(wdb_wdc_wdata_31_0) \ + ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT)) + +#define MH_DEBUG_REG45_GET_WDB_WDC_WDATA_31_0(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT) + +#define MH_DEBUG_REG45_SET_WDB_WDC_WDATA_31_0(mh_debug_reg45_reg, wdb_wdc_wdata_31_0) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg45_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg45_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg45_t f; +} mh_debug_reg45_u; + + +/* + * MH_DEBUG_REG46 struct + */ + +#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE 32 + +#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT 0 + +#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG46_MASK \ + (MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) + +#define MH_DEBUG_REG46(wdb_wdc_wdata_63_32) \ + ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT)) + +#define MH_DEBUG_REG46_GET_WDB_WDC_WDATA_63_32(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT) + +#define MH_DEBUG_REG46_SET_WDB_WDC_WDATA_63_32(mh_debug_reg46_reg, wdb_wdc_wdata_63_32) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg46_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg46_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg46_t f; +} mh_debug_reg46_u; + + +/* + * MH_DEBUG_REG47 struct + */ + +#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE 1 +#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE 1 +#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE 6 +#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG47_RVALID_q_SIZE 1 +#define MH_DEBUG_REG47_RREADY_q_SIZE 1 +#define MH_DEBUG_REG47_RLAST_q_SIZE 1 +#define MH_DEBUG_REG47_BVALID_q_SIZE 1 +#define MH_DEBUG_REG47_BREADY_q_SIZE 1 + +#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT 0 +#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT 1 +#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT 2 +#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT 3 +#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT 4 +#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT 5 +#define MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT 6 +#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT 7 +#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT 13 +#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT 14 +#define MH_DEBUG_REG47_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG47_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG47_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG47_BVALID_q_SHIFT 18 +#define MH_DEBUG_REG47_BREADY_q_SHIFT 19 + +#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK 0x00000001 +#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK 0x00000002 +#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK 0x00000004 +#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK 0x00000008 +#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK 0x00000010 +#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK 0x00000020 +#define MH_DEBUG_REG47_INFLT_LIMIT_q_MASK 0x00000040 +#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK 0x00001f80 +#define MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK 0x00004000 +#define MH_DEBUG_REG47_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG47_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG47_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG47_BVALID_q_MASK 0x00040000 +#define MH_DEBUG_REG47_BREADY_q_MASK 0x00080000 + +#define MH_DEBUG_REG47_MASK \ + (MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK | \ + MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK | \ + MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK | \ + MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG47_INFLT_LIMIT_q_MASK | \ + MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK | \ + MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG47_RVALID_q_MASK | \ + MH_DEBUG_REG47_RREADY_q_MASK | \ + MH_DEBUG_REG47_RLAST_q_MASK | \ + MH_DEBUG_REG47_BVALID_q_MASK | \ + MH_DEBUG_REG47_BREADY_q_MASK) + +#define MH_DEBUG_REG47(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \ + ((ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) | \ + (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) | \ + (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) | \ + (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) | \ + (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) | \ + (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT)) + +#define MH_DEBUG_REG47_GET_CTRL_ARC_EMPTY(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_GET_CTRL_RARC_EMPTY(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_GET_ARQ_CTRL_EMPTY(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG47_GET_ARQ_CTRL_WRITE(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG47_GET_TLBMISS_CTRL_RTS(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG47_GET_CTRL_TLBMISS_RE_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG47_GET_INFLT_LIMIT_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG47_GET_INFLT_LIMIT_CNT_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG47_GET_ARC_CTRL_RE_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_GET_RARC_CTRL_RE_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_GET_RVALID_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RVALID_q_MASK) >> MH_DEBUG_REG47_RVALID_q_SHIFT) +#define MH_DEBUG_REG47_GET_RREADY_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RREADY_q_MASK) >> MH_DEBUG_REG47_RREADY_q_SHIFT) +#define MH_DEBUG_REG47_GET_RLAST_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RLAST_q_MASK) >> MH_DEBUG_REG47_RLAST_q_SHIFT) +#define MH_DEBUG_REG47_GET_BVALID_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_BVALID_q_MASK) >> MH_DEBUG_REG47_BVALID_q_SHIFT) +#define MH_DEBUG_REG47_GET_BREADY_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_BREADY_q_MASK) >> MH_DEBUG_REG47_BREADY_q_SHIFT) + +#define MH_DEBUG_REG47_SET_CTRL_ARC_EMPTY(mh_debug_reg47_reg, ctrl_arc_empty) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_SET_CTRL_RARC_EMPTY(mh_debug_reg47_reg, ctrl_rarc_empty) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_SET_ARQ_CTRL_EMPTY(mh_debug_reg47_reg, arq_ctrl_empty) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG47_SET_ARQ_CTRL_WRITE(mh_debug_reg47_reg, arq_ctrl_write) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG47_SET_TLBMISS_CTRL_RTS(mh_debug_reg47_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG47_SET_CTRL_TLBMISS_RE_q(mh_debug_reg47_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG47_SET_INFLT_LIMIT_q(mh_debug_reg47_reg, inflt_limit_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG47_SET_INFLT_LIMIT_CNT_q(mh_debug_reg47_reg, inflt_limit_cnt_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG47_SET_ARC_CTRL_RE_q(mh_debug_reg47_reg, arc_ctrl_re_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_SET_RARC_CTRL_RE_q(mh_debug_reg47_reg, rarc_ctrl_re_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_SET_RVALID_q(mh_debug_reg47_reg, rvalid_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT) +#define MH_DEBUG_REG47_SET_RREADY_q(mh_debug_reg47_reg, rready_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT) +#define MH_DEBUG_REG47_SET_RLAST_q(mh_debug_reg47_reg, rlast_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT) +#define MH_DEBUG_REG47_SET_BVALID_q(mh_debug_reg47_reg, bvalid_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT) +#define MH_DEBUG_REG47_SET_BREADY_q(mh_debug_reg47_reg, bready_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int ctrl_arc_empty : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG47_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG47_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG47_RLAST_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG47_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG47_BREADY_q_SIZE; + unsigned int : 12; + } mh_debug_reg47_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int : 12; + unsigned int bready_q : MH_DEBUG_REG47_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG47_BVALID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG47_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG47_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG47_RVALID_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE; + unsigned int ctrl_arc_empty : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE; + } mh_debug_reg47_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg47_t f; +} mh_debug_reg47_u; + + +/* + * MH_DEBUG_REG48 struct + */ + +#define MH_DEBUG_REG48_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG48_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG48_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG48_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG48_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG48_RDC_RID_SIZE 3 +#define MH_DEBUG_REG48_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG48_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE 1 +#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE 6 +#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE 1 +#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE 6 +#define MH_DEBUG_REG48_CNT_HOLD_q1_SIZE 1 +#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG48_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG48_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT 3 +#define MH_DEBUG_REG48_TLBMISS_VALID_SHIFT 4 +#define MH_DEBUG_REG48_RDC_VALID_SHIFT 5 +#define MH_DEBUG_REG48_RDC_RID_SHIFT 6 +#define MH_DEBUG_REG48_RDC_RLAST_SHIFT 9 +#define MH_DEBUG_REG48_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT 12 +#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT 13 +#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT 14 +#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT 15 +#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT 21 +#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT 22 +#define MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT 28 +#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29 + +#define MH_DEBUG_REG48_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG48_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG48_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK 0x00000008 +#define MH_DEBUG_REG48_TLBMISS_VALID_MASK 0x00000010 +#define MH_DEBUG_REG48_RDC_VALID_MASK 0x00000020 +#define MH_DEBUG_REG48_RDC_RID_MASK 0x000001c0 +#define MH_DEBUG_REG48_RDC_RLAST_MASK 0x00000200 +#define MH_DEBUG_REG48_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK 0x00001000 +#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK 0x00004000 +#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000 +#define MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK 0x00200000 +#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000 +#define MH_DEBUG_REG48_CNT_HOLD_q1_MASK 0x10000000 +#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000 + +#define MH_DEBUG_REG48_MASK \ + (MH_DEBUG_REG48_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG48_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG48_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG48_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG48_RDC_VALID_MASK | \ + MH_DEBUG_REG48_RDC_RID_MASK | \ + MH_DEBUG_REG48_RDC_RLAST_MASK | \ + MH_DEBUG_REG48_RDC_RRESP_MASK | \ + MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK | \ + MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK | \ + MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK | \ + MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK | \ + MH_DEBUG_REG48_CNT_HOLD_q1_MASK | \ + MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG48(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \ + ((mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) | \ + (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) | \ + (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) | \ + (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) | \ + (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) | \ + (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG48_GET_MH_CP_grb_send(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CP_grb_send_MASK) >> MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG48_GET_MH_VGT_grb_send(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG48_GET_MH_TC_mcsend(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TC_mcsend_MASK) >> MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG48_GET_MH_TLBMISS_SEND(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG48_GET_TLBMISS_VALID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_VALID_MASK) >> MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_VALID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_VALID_MASK) >> MH_DEBUG_REG48_RDC_VALID_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_RID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RID_MASK) >> MH_DEBUG_REG48_RDC_RID_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_RLAST(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RLAST_MASK) >> MH_DEBUG_REG48_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_RRESP(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RRESP_MASK) >> MH_DEBUG_REG48_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG48_GET_TLBMISS_CTRL_RTS(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG48_GET_CTRL_TLBMISS_RE_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG48_GET_MMU_ID_REQUEST_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG48_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG48_GET_MMU_ID_RESPONSE(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG48_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG48_GET_CNT_HOLD_q1(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG48_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG48_SET_MH_CP_grb_send(mh_debug_reg48_reg, mh_cp_grb_send) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG48_SET_MH_VGT_grb_send(mh_debug_reg48_reg, mh_vgt_grb_send) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG48_SET_MH_TC_mcsend(mh_debug_reg48_reg, mh_tc_mcsend) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG48_SET_MH_TLBMISS_SEND(mh_debug_reg48_reg, mh_tlbmiss_send) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG48_SET_TLBMISS_VALID(mh_debug_reg48_reg, tlbmiss_valid) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_VALID(mh_debug_reg48_reg, rdc_valid) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_RID(mh_debug_reg48_reg, rdc_rid) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_RLAST(mh_debug_reg48_reg, rdc_rlast) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_RRESP(mh_debug_reg48_reg, rdc_rresp) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG48_SET_TLBMISS_CTRL_RTS(mh_debug_reg48_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG48_SET_CTRL_TLBMISS_RE_q(mh_debug_reg48_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG48_SET_MMU_ID_REQUEST_q(mh_debug_reg48_reg, mmu_id_request_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG48_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48_reg, outstanding_mmuid_cnt_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG48_SET_MMU_ID_RESPONSE(mh_debug_reg48_reg, mmu_id_response) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG48_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg48_reg, tlbmiss_return_cnt_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG48_SET_CNT_HOLD_q1(mh_debug_reg48_reg, cnt_hold_q1) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG48_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG48_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG48_MH_TC_mcsend_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG48_TLBMISS_VALID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG48_RDC_VALID_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG48_RDC_RID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG48_RDC_RLAST_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG48_RDC_RRESP_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + } mh_debug_reg48_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG48_RDC_RRESP_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG48_RDC_RLAST_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG48_RDC_RID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG48_RDC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG48_TLBMISS_VALID_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG48_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG48_MH_CP_grb_send_SIZE; + } mh_debug_reg48_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg48_t f; +} mh_debug_reg48_u; + + +/* + * MH_DEBUG_REG49 struct + */ + +#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE 32 + +#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT 0 + +#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK 0xffffffff + +#define MH_DEBUG_REG49_MASK \ + (MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) + +#define MH_DEBUG_REG49(rf_mmu_page_fault) \ + ((rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT)) + +#define MH_DEBUG_REG49_GET_RF_MMU_PAGE_FAULT(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT) + +#define MH_DEBUG_REG49_SET_RF_MMU_PAGE_FAULT(mh_debug_reg49_reg, rf_mmu_page_fault) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg49_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg49_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg49_t f; +} mh_debug_reg49_u; + + +/* + * MH_DEBUG_REG50 struct + */ + +#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE 24 +#define MH_DEBUG_REG50_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG50_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG50_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG50_ARB_WE_SIZE 1 +#define MH_DEBUG_REG50_MMU_RTR_SIZE 1 + +#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG50_ARB_ID_q_SHIFT 24 +#define MH_DEBUG_REG50_ARB_WRITE_q_SHIFT 27 +#define MH_DEBUG_REG50_client_behavior_q_SHIFT 28 +#define MH_DEBUG_REG50_ARB_WE_SHIFT 30 +#define MH_DEBUG_REG50_MMU_RTR_SHIFT 31 + +#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK 0x00ffffff +#define MH_DEBUG_REG50_ARB_ID_q_MASK 0x07000000 +#define MH_DEBUG_REG50_ARB_WRITE_q_MASK 0x08000000 +#define MH_DEBUG_REG50_client_behavior_q_MASK 0x30000000 +#define MH_DEBUG_REG50_ARB_WE_MASK 0x40000000 +#define MH_DEBUG_REG50_MMU_RTR_MASK 0x80000000 + +#define MH_DEBUG_REG50_MASK \ + (MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK | \ + MH_DEBUG_REG50_ARB_ID_q_MASK | \ + MH_DEBUG_REG50_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG50_client_behavior_q_MASK | \ + MH_DEBUG_REG50_ARB_WE_MASK | \ + MH_DEBUG_REG50_MMU_RTR_MASK) + +#define MH_DEBUG_REG50(rf_mmu_config_q, arb_id_q, arb_write_q, client_behavior_q, arb_we, mmu_rtr) \ + ((rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT) | \ + (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT)) + +#define MH_DEBUG_REG50_GET_RF_MMU_CONFIG_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) >> MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) +#define MH_DEBUG_REG50_GET_ARB_ID_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_ID_q_MASK) >> MH_DEBUG_REG50_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG50_GET_ARB_WRITE_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WRITE_q_MASK) >> MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG50_GET_client_behavior_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_client_behavior_q_MASK) >> MH_DEBUG_REG50_client_behavior_q_SHIFT) +#define MH_DEBUG_REG50_GET_ARB_WE(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WE_MASK) >> MH_DEBUG_REG50_ARB_WE_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_RTR(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_RTR_MASK) >> MH_DEBUG_REG50_MMU_RTR_SHIFT) + +#define MH_DEBUG_REG50_SET_RF_MMU_CONFIG_q(mh_debug_reg50_reg, rf_mmu_config_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) | (rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) +#define MH_DEBUG_REG50_SET_ARB_ID_q(mh_debug_reg50_reg, arb_id_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG50_SET_ARB_WRITE_q(mh_debug_reg50_reg, arb_write_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG50_SET_client_behavior_q(mh_debug_reg50_reg, client_behavior_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT) +#define MH_DEBUG_REG50_SET_ARB_WE(mh_debug_reg50_reg, arb_we) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_RTR(mh_debug_reg50_reg, mmu_rtr) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int rf_mmu_config_q : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG50_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG50_ARB_WRITE_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG50_client_behavior_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG50_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG50_MMU_RTR_SIZE; + } mh_debug_reg50_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mmu_rtr : MH_DEBUG_REG50_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG50_ARB_WE_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG50_client_behavior_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG50_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG50_ARB_ID_q_SIZE; + unsigned int rf_mmu_config_q : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE; + } mh_debug_reg50_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg50_t f; +} mh_debug_reg50_u; + + +/* + * MH_DEBUG_REG51 struct + */ + +#define MH_DEBUG_REG51_stage1_valid_SIZE 1 +#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG51_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG51_tag_match_q_SIZE 1 +#define MH_DEBUG_REG51_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG51_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG51_MMU_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_READ_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_READ_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1 +#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE 16 + +#define MH_DEBUG_REG51_stage1_valid_SHIFT 0 +#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT 1 +#define MH_DEBUG_REG51_pa_in_mpu_range_SHIFT 2 +#define MH_DEBUG_REG51_tag_match_q_SHIFT 3 +#define MH_DEBUG_REG51_tag_miss_q_SHIFT 4 +#define MH_DEBUG_REG51_va_in_range_q_SHIFT 5 +#define MH_DEBUG_REG51_MMU_MISS_SHIFT 6 +#define MH_DEBUG_REG51_MMU_READ_MISS_SHIFT 7 +#define MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT 8 +#define MH_DEBUG_REG51_MMU_HIT_SHIFT 9 +#define MH_DEBUG_REG51_MMU_READ_HIT_SHIFT 10 +#define MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT 11 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT 12 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT 13 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15 +#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT 16 + +#define MH_DEBUG_REG51_stage1_valid_MASK 0x00000001 +#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK 0x00000002 +#define MH_DEBUG_REG51_pa_in_mpu_range_MASK 0x00000004 +#define MH_DEBUG_REG51_tag_match_q_MASK 0x00000008 +#define MH_DEBUG_REG51_tag_miss_q_MASK 0x00000010 +#define MH_DEBUG_REG51_va_in_range_q_MASK 0x00000020 +#define MH_DEBUG_REG51_MMU_MISS_MASK 0x00000040 +#define MH_DEBUG_REG51_MMU_READ_MISS_MASK 0x00000080 +#define MH_DEBUG_REG51_MMU_WRITE_MISS_MASK 0x00000100 +#define MH_DEBUG_REG51_MMU_HIT_MASK 0x00000200 +#define MH_DEBUG_REG51_MMU_READ_HIT_MASK 0x00000400 +#define MH_DEBUG_REG51_MMU_WRITE_HIT_MASK 0x00000800 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000 +#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK 0xffff0000 + +#define MH_DEBUG_REG51_MASK \ + (MH_DEBUG_REG51_stage1_valid_MASK | \ + MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG51_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG51_tag_match_q_MASK | \ + MH_DEBUG_REG51_tag_miss_q_MASK | \ + MH_DEBUG_REG51_va_in_range_q_MASK | \ + MH_DEBUG_REG51_MMU_MISS_MASK | \ + MH_DEBUG_REG51_MMU_READ_MISS_MASK | \ + MH_DEBUG_REG51_MMU_WRITE_MISS_MASK | \ + MH_DEBUG_REG51_MMU_HIT_MASK | \ + MH_DEBUG_REG51_MMU_READ_HIT_MASK | \ + MH_DEBUG_REG51_MMU_WRITE_HIT_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK | \ + MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) + +#define MH_DEBUG_REG51(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \ + ((stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT) | \ + (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT) | \ + (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) | \ + (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) | \ + (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT) | \ + (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) | \ + (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) | \ + (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \ + (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \ + (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \ + (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \ + (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT)) + +#define MH_DEBUG_REG51_GET_stage1_valid(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_stage1_valid_MASK) >> MH_DEBUG_REG51_stage1_valid_SHIFT) +#define MH_DEBUG_REG51_GET_IGNORE_TAG_MISS_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG51_GET_pa_in_mpu_range(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_pa_in_mpu_range_MASK) >> MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG51_GET_tag_match_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_tag_match_q_MASK) >> MH_DEBUG_REG51_tag_match_q_SHIFT) +#define MH_DEBUG_REG51_GET_tag_miss_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_tag_miss_q_MASK) >> MH_DEBUG_REG51_tag_miss_q_SHIFT) +#define MH_DEBUG_REG51_GET_va_in_range_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_va_in_range_q_MASK) >> MH_DEBUG_REG51_va_in_range_q_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_MISS_MASK) >> MH_DEBUG_REG51_MMU_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_READ_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_MISS_MASK) >> MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_WRITE_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_HIT_MASK) >> MH_DEBUG_REG51_MMU_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_READ_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_HIT_MASK) >> MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_WRITE_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_REQ_VA_OFFSET_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT) + +#define MH_DEBUG_REG51_SET_stage1_valid(mh_debug_reg51_reg, stage1_valid) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT) +#define MH_DEBUG_REG51_SET_IGNORE_TAG_MISS_q(mh_debug_reg51_reg, ignore_tag_miss_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG51_SET_pa_in_mpu_range(mh_debug_reg51_reg, pa_in_mpu_range) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG51_SET_tag_match_q(mh_debug_reg51_reg, tag_match_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT) +#define MH_DEBUG_REG51_SET_tag_miss_q(mh_debug_reg51_reg, tag_miss_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT) +#define MH_DEBUG_REG51_SET_va_in_range_q(mh_debug_reg51_reg, va_in_range_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_MISS(mh_debug_reg51_reg, mmu_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_READ_MISS(mh_debug_reg51_reg, mmu_read_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_WRITE_MISS(mh_debug_reg51_reg, mmu_write_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_HIT(mh_debug_reg51_reg, mmu_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_READ_HIT(mh_debug_reg51_reg, mmu_read_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_WRITE_HIT(mh_debug_reg51_reg, mmu_write_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51_reg, mmu_split_mode_tc_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51_reg, mmu_split_mode_tc_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51_reg, mmu_split_mode_nontc_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51_reg, mmu_split_mode_nontc_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_REQ_VA_OFFSET_q(mh_debug_reg51_reg, req_va_offset_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int stage1_valid : MH_DEBUG_REG51_stage1_valid_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG51_pa_in_mpu_range_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG51_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG51_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG51_va_in_range_q_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG51_MMU_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG51_MMU_READ_MISS_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG51_MMU_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG51_MMU_READ_HIT_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int req_va_offset_q : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE; + } mh_debug_reg51_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int req_va_offset_q : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG51_MMU_READ_HIT_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG51_MMU_HIT_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG51_MMU_READ_MISS_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG51_MMU_MISS_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG51_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG51_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG51_tag_match_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG51_pa_in_mpu_range_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG51_stage1_valid_SIZE; + } mh_debug_reg51_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg51_t f; +} mh_debug_reg51_u; + + +/* + * MH_DEBUG_REG52 struct + */ + +#define MH_DEBUG_REG52_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG52_MMU_WE_SIZE 1 +#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1 +#define MH_DEBUG_REG52_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG52_stage1_valid_SIZE 1 +#define MH_DEBUG_REG52_stage2_valid_SIZE 1 +#define MH_DEBUG_REG52_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG52_tag_match_q_SIZE 1 +#define MH_DEBUG_REG52_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG52_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE 1 +#define MH_DEBUG_REG52_TAG_valid_q_SIZE 16 + +#define MH_DEBUG_REG52_ARQ_RTR_SHIFT 0 +#define MH_DEBUG_REG52_MMU_WE_SHIFT 1 +#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT 2 +#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT 3 +#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT 4 +#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5 +#define MH_DEBUG_REG52_pa_in_mpu_range_SHIFT 6 +#define MH_DEBUG_REG52_stage1_valid_SHIFT 7 +#define MH_DEBUG_REG52_stage2_valid_SHIFT 8 +#define MH_DEBUG_REG52_client_behavior_q_SHIFT 9 +#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT 11 +#define MH_DEBUG_REG52_tag_match_q_SHIFT 12 +#define MH_DEBUG_REG52_tag_miss_q_SHIFT 13 +#define MH_DEBUG_REG52_va_in_range_q_SHIFT 14 +#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT 15 +#define MH_DEBUG_REG52_TAG_valid_q_SHIFT 16 + +#define MH_DEBUG_REG52_ARQ_RTR_MASK 0x00000001 +#define MH_DEBUG_REG52_MMU_WE_MASK 0x00000002 +#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK 0x00000004 +#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK 0x00000008 +#define MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK 0x00000010 +#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020 +#define MH_DEBUG_REG52_pa_in_mpu_range_MASK 0x00000040 +#define MH_DEBUG_REG52_stage1_valid_MASK 0x00000080 +#define MH_DEBUG_REG52_stage2_valid_MASK 0x00000100 +#define MH_DEBUG_REG52_client_behavior_q_MASK 0x00000600 +#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK 0x00000800 +#define MH_DEBUG_REG52_tag_match_q_MASK 0x00001000 +#define MH_DEBUG_REG52_tag_miss_q_MASK 0x00002000 +#define MH_DEBUG_REG52_va_in_range_q_MASK 0x00004000 +#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK 0x00008000 +#define MH_DEBUG_REG52_TAG_valid_q_MASK 0xffff0000 + +#define MH_DEBUG_REG52_MASK \ + (MH_DEBUG_REG52_ARQ_RTR_MASK | \ + MH_DEBUG_REG52_MMU_WE_MASK | \ + MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \ + MH_DEBUG_REG52_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG52_stage1_valid_MASK | \ + MH_DEBUG_REG52_stage2_valid_MASK | \ + MH_DEBUG_REG52_client_behavior_q_MASK | \ + MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG52_tag_match_q_MASK | \ + MH_DEBUG_REG52_tag_miss_q_MASK | \ + MH_DEBUG_REG52_va_in_range_q_MASK | \ + MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK | \ + MH_DEBUG_REG52_TAG_valid_q_MASK) + +#define MH_DEBUG_REG52(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \ + ((arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT) | \ + (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) | \ + (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) | \ + (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT) | \ + (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT) | \ + (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) | \ + (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT)) + +#define MH_DEBUG_REG52_GET_ARQ_RTR(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARQ_RTR_MASK) >> MH_DEBUG_REG52_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_WE(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_WE_MASK) >> MH_DEBUG_REG52_MMU_WE_SHIFT) +#define MH_DEBUG_REG52_GET_CTRL_TLBMISS_RE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG52_GET_TLBMISS_CTRL_RTS(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG52_GET_MH_TLBMISS_SEND(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG52_GET_pa_in_mpu_range(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_pa_in_mpu_range_MASK) >> MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG52_GET_stage1_valid(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_stage1_valid_MASK) >> MH_DEBUG_REG52_stage1_valid_SHIFT) +#define MH_DEBUG_REG52_GET_stage2_valid(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_stage2_valid_MASK) >> MH_DEBUG_REG52_stage2_valid_SHIFT) +#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT) +#define MH_DEBUG_REG52_GET_IGNORE_TAG_MISS_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG52_GET_tag_match_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_tag_match_q_MASK) >> MH_DEBUG_REG52_tag_match_q_SHIFT) +#define MH_DEBUG_REG52_GET_tag_miss_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_tag_miss_q_MASK) >> MH_DEBUG_REG52_tag_miss_q_SHIFT) +#define MH_DEBUG_REG52_GET_va_in_range_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_va_in_range_q_MASK) >> MH_DEBUG_REG52_va_in_range_q_SHIFT) +#define MH_DEBUG_REG52_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG52_GET_TAG_valid_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_TAG_valid_q_MASK) >> MH_DEBUG_REG52_TAG_valid_q_SHIFT) + +#define MH_DEBUG_REG52_SET_ARQ_RTR(mh_debug_reg52_reg, arq_rtr) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_WE(mh_debug_reg52_reg, mmu_we) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT) +#define MH_DEBUG_REG52_SET_CTRL_TLBMISS_RE_q(mh_debug_reg52_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG52_SET_TLBMISS_CTRL_RTS(mh_debug_reg52_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG52_SET_MH_TLBMISS_SEND(mh_debug_reg52_reg, mh_tlbmiss_send) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52_reg, mmu_stall_awaiting_tlb_miss_fetch) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG52_SET_pa_in_mpu_range(mh_debug_reg52_reg, pa_in_mpu_range) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG52_SET_stage1_valid(mh_debug_reg52_reg, stage1_valid) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT) +#define MH_DEBUG_REG52_SET_stage2_valid(mh_debug_reg52_reg, stage2_valid) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT) +#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) +#define MH_DEBUG_REG52_SET_IGNORE_TAG_MISS_q(mh_debug_reg52_reg, ignore_tag_miss_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG52_SET_tag_match_q(mh_debug_reg52_reg, tag_match_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT) +#define MH_DEBUG_REG52_SET_tag_miss_q(mh_debug_reg52_reg, tag_miss_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT) +#define MH_DEBUG_REG52_SET_va_in_range_q(mh_debug_reg52_reg, va_in_range_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT) +#define MH_DEBUG_REG52_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg52_reg, pte_fetch_complete_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG52_SET_TAG_valid_q(mh_debug_reg52_reg, tag_valid_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int arq_rtr : MH_DEBUG_REG52_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG52_MMU_WE_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG52_pa_in_mpu_range_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG52_stage1_valid_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG52_stage2_valid_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG52_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG52_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG52_va_in_range_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int tag_valid_q : MH_DEBUG_REG52_TAG_valid_q_SIZE; + } mh_debug_reg52_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int tag_valid_q : MH_DEBUG_REG52_TAG_valid_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG52_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG52_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG52_tag_match_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG52_stage2_valid_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG52_stage1_valid_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG52_pa_in_mpu_range_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG52_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG52_ARQ_RTR_SIZE; + } mh_debug_reg52_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg52_t f; +} mh_debug_reg52_u; + + +/* + * MH_DEBUG_REG53 struct + */ + +#define MH_DEBUG_REG53_TAG0_VA_SIZE 13 +#define MH_DEBUG_REG53_TAG_valid_q_0_SIZE 1 +#define MH_DEBUG_REG53_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG53_TAG1_VA_SIZE 13 +#define MH_DEBUG_REG53_TAG_valid_q_1_SIZE 1 + +#define MH_DEBUG_REG53_TAG0_VA_SHIFT 0 +#define MH_DEBUG_REG53_TAG_valid_q_0_SHIFT 13 +#define MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG53_TAG1_VA_SHIFT 16 +#define MH_DEBUG_REG53_TAG_valid_q_1_SHIFT 29 + +#define MH_DEBUG_REG53_TAG0_VA_MASK 0x00001fff +#define MH_DEBUG_REG53_TAG_valid_q_0_MASK 0x00002000 +#define MH_DEBUG_REG53_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG53_TAG1_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG53_TAG_valid_q_1_MASK 0x20000000 + +#define MH_DEBUG_REG53_MASK \ + (MH_DEBUG_REG53_TAG0_VA_MASK | \ + MH_DEBUG_REG53_TAG_valid_q_0_MASK | \ + MH_DEBUG_REG53_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG53_TAG1_VA_MASK | \ + MH_DEBUG_REG53_TAG_valid_q_1_MASK) + +#define MH_DEBUG_REG53(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \ + ((tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT) | \ + (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) | \ + (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) | \ + (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT) | \ + (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT)) + +#define MH_DEBUG_REG53_GET_TAG0_VA(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG0_VA_MASK) >> MH_DEBUG_REG53_TAG0_VA_SHIFT) +#define MH_DEBUG_REG53_GET_TAG_valid_q_0(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_0_MASK) >> MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG53_GET_ALWAYS_ZERO(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG53_GET_TAG1_VA(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG1_VA_MASK) >> MH_DEBUG_REG53_TAG1_VA_SHIFT) +#define MH_DEBUG_REG53_GET_TAG_valid_q_1(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_1_MASK) >> MH_DEBUG_REG53_TAG_valid_q_1_SHIFT) + +#define MH_DEBUG_REG53_SET_TAG0_VA(mh_debug_reg53_reg, tag0_va) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT) +#define MH_DEBUG_REG53_SET_TAG_valid_q_0(mh_debug_reg53_reg, tag_valid_q_0) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG53_SET_ALWAYS_ZERO(mh_debug_reg53_reg, always_zero) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG53_SET_TAG1_VA(mh_debug_reg53_reg, tag1_va) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT) +#define MH_DEBUG_REG53_SET_TAG_valid_q_1(mh_debug_reg53_reg, tag_valid_q_1) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int tag0_va : MH_DEBUG_REG53_TAG0_VA_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG53_TAG_valid_q_0_SIZE; + unsigned int always_zero : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE; + unsigned int tag1_va : MH_DEBUG_REG53_TAG1_VA_SIZE; + unsigned int tag_valid_q_1 : MH_DEBUG_REG53_TAG_valid_q_1_SIZE; + unsigned int : 2; + } mh_debug_reg53_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int : 2; + unsigned int tag_valid_q_1 : MH_DEBUG_REG53_TAG_valid_q_1_SIZE; + unsigned int tag1_va : MH_DEBUG_REG53_TAG1_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG53_TAG_valid_q_0_SIZE; + unsigned int tag0_va : MH_DEBUG_REG53_TAG0_VA_SIZE; + } mh_debug_reg53_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg53_t f; +} mh_debug_reg53_u; + + +/* + * MH_DEBUG_REG54 struct + */ + +#define MH_DEBUG_REG54_TAG2_VA_SIZE 13 +#define MH_DEBUG_REG54_TAG_valid_q_2_SIZE 1 +#define MH_DEBUG_REG54_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG54_TAG3_VA_SIZE 13 +#define MH_DEBUG_REG54_TAG_valid_q_3_SIZE 1 + +#define MH_DEBUG_REG54_TAG2_VA_SHIFT 0 +#define MH_DEBUG_REG54_TAG_valid_q_2_SHIFT 13 +#define MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG54_TAG3_VA_SHIFT 16 +#define MH_DEBUG_REG54_TAG_valid_q_3_SHIFT 29 + +#define MH_DEBUG_REG54_TAG2_VA_MASK 0x00001fff +#define MH_DEBUG_REG54_TAG_valid_q_2_MASK 0x00002000 +#define MH_DEBUG_REG54_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG54_TAG3_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG54_TAG_valid_q_3_MASK 0x20000000 + +#define MH_DEBUG_REG54_MASK \ + (MH_DEBUG_REG54_TAG2_VA_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_2_MASK | \ + MH_DEBUG_REG54_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG54_TAG3_VA_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_3_MASK) + +#define MH_DEBUG_REG54(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \ + ((tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT) | \ + (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) | \ + (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) | \ + (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT) | \ + (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT)) + +#define MH_DEBUG_REG54_GET_TAG2_VA(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG2_VA_MASK) >> MH_DEBUG_REG54_TAG2_VA_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q_2(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_2_MASK) >> MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG54_GET_ALWAYS_ZERO(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG54_GET_TAG3_VA(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG3_VA_MASK) >> MH_DEBUG_REG54_TAG3_VA_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q_3(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_3_MASK) >> MH_DEBUG_REG54_TAG_valid_q_3_SHIFT) + +#define MH_DEBUG_REG54_SET_TAG2_VA(mh_debug_reg54_reg, tag2_va) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q_2(mh_debug_reg54_reg, tag_valid_q_2) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG54_SET_ALWAYS_ZERO(mh_debug_reg54_reg, always_zero) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG54_SET_TAG3_VA(mh_debug_reg54_reg, tag3_va) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q_3(mh_debug_reg54_reg, tag_valid_q_3) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int tag2_va : MH_DEBUG_REG54_TAG2_VA_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG54_TAG_valid_q_2_SIZE; + unsigned int always_zero : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE; + unsigned int tag3_va : MH_DEBUG_REG54_TAG3_VA_SIZE; + unsigned int tag_valid_q_3 : MH_DEBUG_REG54_TAG_valid_q_3_SIZE; + unsigned int : 2; + } mh_debug_reg54_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int : 2; + unsigned int tag_valid_q_3 : MH_DEBUG_REG54_TAG_valid_q_3_SIZE; + unsigned int tag3_va : MH_DEBUG_REG54_TAG3_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG54_TAG_valid_q_2_SIZE; + unsigned int tag2_va : MH_DEBUG_REG54_TAG2_VA_SIZE; + } mh_debug_reg54_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg54_t f; +} mh_debug_reg54_u; + + +/* + * MH_DEBUG_REG55 struct + */ + +#define MH_DEBUG_REG55_TAG4_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_4_SIZE 1 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG55_TAG5_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_5_SIZE 1 + +#define MH_DEBUG_REG55_TAG4_VA_SHIFT 0 +#define MH_DEBUG_REG55_TAG_valid_q_4_SHIFT 13 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG55_TAG5_VA_SHIFT 16 +#define MH_DEBUG_REG55_TAG_valid_q_5_SHIFT 29 + +#define MH_DEBUG_REG55_TAG4_VA_MASK 0x00001fff +#define MH_DEBUG_REG55_TAG_valid_q_4_MASK 0x00002000 +#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG55_TAG5_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG55_TAG_valid_q_5_MASK 0x20000000 + +#define MH_DEBUG_REG55_MASK \ + (MH_DEBUG_REG55_TAG4_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_4_MASK | \ + MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG55_TAG5_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_5_MASK) + +#define MH_DEBUG_REG55(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \ + ((tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT) | \ + (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) | \ + (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \ + (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT) | \ + (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT)) + +#define MH_DEBUG_REG55_GET_TAG4_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG4_VA_MASK) >> MH_DEBUG_REG55_TAG4_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_4(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_4_MASK) >> MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_GET_TAG5_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG5_VA_MASK) >> MH_DEBUG_REG55_TAG5_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_5(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_5_MASK) >> MH_DEBUG_REG55_TAG_valid_q_5_SHIFT) + +#define MH_DEBUG_REG55_SET_TAG4_VA(mh_debug_reg55_reg, tag4_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_4(mh_debug_reg55_reg, tag_valid_q_4) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_SET_TAG5_VA(mh_debug_reg55_reg, tag5_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_5(mh_debug_reg55_reg, tag_valid_q_5) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int tag4_va : MH_DEBUG_REG55_TAG4_VA_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG55_TAG_valid_q_4_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag5_va : MH_DEBUG_REG55_TAG5_VA_SIZE; + unsigned int tag_valid_q_5 : MH_DEBUG_REG55_TAG_valid_q_5_SIZE; + unsigned int : 2; + } mh_debug_reg55_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int : 2; + unsigned int tag_valid_q_5 : MH_DEBUG_REG55_TAG_valid_q_5_SIZE; + unsigned int tag5_va : MH_DEBUG_REG55_TAG5_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG55_TAG_valid_q_4_SIZE; + unsigned int tag4_va : MH_DEBUG_REG55_TAG4_VA_SIZE; + } mh_debug_reg55_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg55_t f; +} mh_debug_reg55_u; + + +/* + * MH_DEBUG_REG56 struct + */ + +#define MH_DEBUG_REG56_TAG6_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_6_SIZE 1 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG56_TAG7_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_7_SIZE 1 + +#define MH_DEBUG_REG56_TAG6_VA_SHIFT 0 +#define MH_DEBUG_REG56_TAG_valid_q_6_SHIFT 13 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG56_TAG7_VA_SHIFT 16 +#define MH_DEBUG_REG56_TAG_valid_q_7_SHIFT 29 + +#define MH_DEBUG_REG56_TAG6_VA_MASK 0x00001fff +#define MH_DEBUG_REG56_TAG_valid_q_6_MASK 0x00002000 +#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG56_TAG7_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG56_TAG_valid_q_7_MASK 0x20000000 + +#define MH_DEBUG_REG56_MASK \ + (MH_DEBUG_REG56_TAG6_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_6_MASK | \ + MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG56_TAG7_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_7_MASK) + +#define MH_DEBUG_REG56(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \ + ((tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT) | \ + (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) | \ + (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \ + (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT) | \ + (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT)) + +#define MH_DEBUG_REG56_GET_TAG6_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG6_VA_MASK) >> MH_DEBUG_REG56_TAG6_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_6(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_6_MASK) >> MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_GET_TAG7_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG7_VA_MASK) >> MH_DEBUG_REG56_TAG7_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_7(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_7_MASK) >> MH_DEBUG_REG56_TAG_valid_q_7_SHIFT) + +#define MH_DEBUG_REG56_SET_TAG6_VA(mh_debug_reg56_reg, tag6_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_6(mh_debug_reg56_reg, tag_valid_q_6) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_SET_TAG7_VA(mh_debug_reg56_reg, tag7_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_7(mh_debug_reg56_reg, tag_valid_q_7) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int tag6_va : MH_DEBUG_REG56_TAG6_VA_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG56_TAG_valid_q_6_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag7_va : MH_DEBUG_REG56_TAG7_VA_SIZE; + unsigned int tag_valid_q_7 : MH_DEBUG_REG56_TAG_valid_q_7_SIZE; + unsigned int : 2; + } mh_debug_reg56_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int : 2; + unsigned int tag_valid_q_7 : MH_DEBUG_REG56_TAG_valid_q_7_SIZE; + unsigned int tag7_va : MH_DEBUG_REG56_TAG7_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG56_TAG_valid_q_6_SIZE; + unsigned int tag6_va : MH_DEBUG_REG56_TAG6_VA_SIZE; + } mh_debug_reg56_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg56_t f; +} mh_debug_reg56_u; + + +/* + * MH_DEBUG_REG57 struct + */ + +#define MH_DEBUG_REG57_TAG8_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_8_SIZE 1 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG57_TAG9_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_9_SIZE 1 + +#define MH_DEBUG_REG57_TAG8_VA_SHIFT 0 +#define MH_DEBUG_REG57_TAG_valid_q_8_SHIFT 13 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG57_TAG9_VA_SHIFT 16 +#define MH_DEBUG_REG57_TAG_valid_q_9_SHIFT 29 + +#define MH_DEBUG_REG57_TAG8_VA_MASK 0x00001fff +#define MH_DEBUG_REG57_TAG_valid_q_8_MASK 0x00002000 +#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG57_TAG9_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG57_TAG_valid_q_9_MASK 0x20000000 + +#define MH_DEBUG_REG57_MASK \ + (MH_DEBUG_REG57_TAG8_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_8_MASK | \ + MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG57_TAG9_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_9_MASK) + +#define MH_DEBUG_REG57(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \ + ((tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT) | \ + (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) | \ + (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \ + (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT) | \ + (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT)) + +#define MH_DEBUG_REG57_GET_TAG8_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG8_VA_MASK) >> MH_DEBUG_REG57_TAG8_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_8(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_8_MASK) >> MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_GET_TAG9_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG9_VA_MASK) >> MH_DEBUG_REG57_TAG9_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_9(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_9_MASK) >> MH_DEBUG_REG57_TAG_valid_q_9_SHIFT) + +#define MH_DEBUG_REG57_SET_TAG8_VA(mh_debug_reg57_reg, tag8_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_8(mh_debug_reg57_reg, tag_valid_q_8) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_SET_TAG9_VA(mh_debug_reg57_reg, tag9_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_9(mh_debug_reg57_reg, tag_valid_q_9) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int tag8_va : MH_DEBUG_REG57_TAG8_VA_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG57_TAG_valid_q_8_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag9_va : MH_DEBUG_REG57_TAG9_VA_SIZE; + unsigned int tag_valid_q_9 : MH_DEBUG_REG57_TAG_valid_q_9_SIZE; + unsigned int : 2; + } mh_debug_reg57_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int : 2; + unsigned int tag_valid_q_9 : MH_DEBUG_REG57_TAG_valid_q_9_SIZE; + unsigned int tag9_va : MH_DEBUG_REG57_TAG9_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG57_TAG_valid_q_8_SIZE; + unsigned int tag8_va : MH_DEBUG_REG57_TAG8_VA_SIZE; + } mh_debug_reg57_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg57_t f; +} mh_debug_reg57_u; + + +/* + * MH_DEBUG_REG58 struct + */ + +#define MH_DEBUG_REG58_TAG10_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_10_SIZE 1 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG58_TAG11_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_11_SIZE 1 + +#define MH_DEBUG_REG58_TAG10_VA_SHIFT 0 +#define MH_DEBUG_REG58_TAG_valid_q_10_SHIFT 13 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG58_TAG11_VA_SHIFT 16 +#define MH_DEBUG_REG58_TAG_valid_q_11_SHIFT 29 + +#define MH_DEBUG_REG58_TAG10_VA_MASK 0x00001fff +#define MH_DEBUG_REG58_TAG_valid_q_10_MASK 0x00002000 +#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG58_TAG11_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG58_TAG_valid_q_11_MASK 0x20000000 + +#define MH_DEBUG_REG58_MASK \ + (MH_DEBUG_REG58_TAG10_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_10_MASK | \ + MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG58_TAG11_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_11_MASK) + +#define MH_DEBUG_REG58(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \ + ((tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT) | \ + (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) | \ + (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \ + (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT) | \ + (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT)) + +#define MH_DEBUG_REG58_GET_TAG10_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG10_VA_MASK) >> MH_DEBUG_REG58_TAG10_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_10(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_10_MASK) >> MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_GET_TAG11_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG11_VA_MASK) >> MH_DEBUG_REG58_TAG11_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_11(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_11_MASK) >> MH_DEBUG_REG58_TAG_valid_q_11_SHIFT) + +#define MH_DEBUG_REG58_SET_TAG10_VA(mh_debug_reg58_reg, tag10_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_10(mh_debug_reg58_reg, tag_valid_q_10) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_SET_TAG11_VA(mh_debug_reg58_reg, tag11_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_11(mh_debug_reg58_reg, tag_valid_q_11) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int tag10_va : MH_DEBUG_REG58_TAG10_VA_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag11_va : MH_DEBUG_REG58_TAG11_VA_SIZE; + unsigned int tag_valid_q_11 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE; + unsigned int : 2; + } mh_debug_reg58_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int : 2; + unsigned int tag_valid_q_11 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE; + unsigned int tag11_va : MH_DEBUG_REG58_TAG11_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE; + unsigned int tag10_va : MH_DEBUG_REG58_TAG10_VA_SIZE; + } mh_debug_reg58_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg58_t f; +} mh_debug_reg58_u; + + +/* + * MH_DEBUG_REG59 struct + */ + +#define MH_DEBUG_REG59_TAG12_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_12_SIZE 1 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG59_TAG13_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_13_SIZE 1 + +#define MH_DEBUG_REG59_TAG12_VA_SHIFT 0 +#define MH_DEBUG_REG59_TAG_valid_q_12_SHIFT 13 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG59_TAG13_VA_SHIFT 16 +#define MH_DEBUG_REG59_TAG_valid_q_13_SHIFT 29 + +#define MH_DEBUG_REG59_TAG12_VA_MASK 0x00001fff +#define MH_DEBUG_REG59_TAG_valid_q_12_MASK 0x00002000 +#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG59_TAG13_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG59_TAG_valid_q_13_MASK 0x20000000 + +#define MH_DEBUG_REG59_MASK \ + (MH_DEBUG_REG59_TAG12_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_12_MASK | \ + MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG59_TAG13_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_13_MASK) + +#define MH_DEBUG_REG59(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \ + ((tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT) | \ + (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) | \ + (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \ + (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT) | \ + (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT)) + +#define MH_DEBUG_REG59_GET_TAG12_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG12_VA_MASK) >> MH_DEBUG_REG59_TAG12_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_12(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_12_MASK) >> MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_GET_TAG13_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG13_VA_MASK) >> MH_DEBUG_REG59_TAG13_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_13(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_13_MASK) >> MH_DEBUG_REG59_TAG_valid_q_13_SHIFT) + +#define MH_DEBUG_REG59_SET_TAG12_VA(mh_debug_reg59_reg, tag12_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_12(mh_debug_reg59_reg, tag_valid_q_12) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_SET_TAG13_VA(mh_debug_reg59_reg, tag13_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_13(mh_debug_reg59_reg, tag_valid_q_13) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int tag12_va : MH_DEBUG_REG59_TAG12_VA_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag13_va : MH_DEBUG_REG59_TAG13_VA_SIZE; + unsigned int tag_valid_q_13 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE; + unsigned int : 2; + } mh_debug_reg59_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int : 2; + unsigned int tag_valid_q_13 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE; + unsigned int tag13_va : MH_DEBUG_REG59_TAG13_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE; + unsigned int tag12_va : MH_DEBUG_REG59_TAG12_VA_SIZE; + } mh_debug_reg59_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg59_t f; +} mh_debug_reg59_u; + + +/* + * MH_DEBUG_REG60 struct + */ + +#define MH_DEBUG_REG60_TAG14_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_14_SIZE 1 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG60_TAG15_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_15_SIZE 1 + +#define MH_DEBUG_REG60_TAG14_VA_SHIFT 0 +#define MH_DEBUG_REG60_TAG_valid_q_14_SHIFT 13 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG60_TAG15_VA_SHIFT 16 +#define MH_DEBUG_REG60_TAG_valid_q_15_SHIFT 29 + +#define MH_DEBUG_REG60_TAG14_VA_MASK 0x00001fff +#define MH_DEBUG_REG60_TAG_valid_q_14_MASK 0x00002000 +#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG60_TAG15_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG60_TAG_valid_q_15_MASK 0x20000000 + +#define MH_DEBUG_REG60_MASK \ + (MH_DEBUG_REG60_TAG14_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_14_MASK | \ + MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG60_TAG15_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_15_MASK) + +#define MH_DEBUG_REG60(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \ + ((tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT) | \ + (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) | \ + (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \ + (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT) | \ + (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT)) + +#define MH_DEBUG_REG60_GET_TAG14_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG14_VA_MASK) >> MH_DEBUG_REG60_TAG14_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_14(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_14_MASK) >> MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_GET_TAG15_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG15_VA_MASK) >> MH_DEBUG_REG60_TAG15_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_15(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_15_MASK) >> MH_DEBUG_REG60_TAG_valid_q_15_SHIFT) + +#define MH_DEBUG_REG60_SET_TAG14_VA(mh_debug_reg60_reg, tag14_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_14(mh_debug_reg60_reg, tag_valid_q_14) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_SET_TAG15_VA(mh_debug_reg60_reg, tag15_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_15(mh_debug_reg60_reg, tag_valid_q_15) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int tag14_va : MH_DEBUG_REG60_TAG14_VA_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag15_va : MH_DEBUG_REG60_TAG15_VA_SIZE; + unsigned int tag_valid_q_15 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE; + unsigned int : 2; + } mh_debug_reg60_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int : 2; + unsigned int tag_valid_q_15 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE; + unsigned int tag15_va : MH_DEBUG_REG60_TAG15_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE; + unsigned int tag14_va : MH_DEBUG_REG60_TAG14_VA_SIZE; + } mh_debug_reg60_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg60_t f; +} mh_debug_reg60_u; + + +/* + * MH_DEBUG_REG61 struct + */ + +#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG61_MASK \ + (MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG61(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG61_GET_MH_DBG_DEFAULT(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG61_SET_MH_DBG_DEFAULT(mh_debug_reg61_reg, mh_dbg_default) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int mh_dbg_default : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg61_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int mh_dbg_default : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg61_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg61_t f; +} mh_debug_reg61_u; + + +/* + * MH_DEBUG_REG62 struct + */ + +#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG62_MASK \ + (MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG62(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG62_GET_MH_DBG_DEFAULT(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG62_SET_MH_DBG_DEFAULT(mh_debug_reg62_reg, mh_dbg_default) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int mh_dbg_default : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg62_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int mh_dbg_default : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg62_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg62_t f; +} mh_debug_reg62_u; + + +/* + * MH_DEBUG_REG63 struct + */ + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG63_MASK \ + (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG63(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \ + ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \ + mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg63_t f; +} mh_debug_reg63_u; + + +/* + * MH_MMU_CONFIG struct + */ + +#define MH_MMU_CONFIG_MMU_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_RESERVED1_SIZE 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2 + +#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1 +#define MH_MMU_CONFIG_RESERVED1_SHIFT 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22 + +#define MH_MMU_CONFIG_MMU_ENABLE_MASK 0x00000001 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002 +#define MH_MMU_CONFIG_RESERVED1_MASK 0x0000000c +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000 + +#define MH_MMU_CONFIG_MASK \ + (MH_MMU_CONFIG_MMU_ENABLE_MASK | \ + MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \ + MH_MMU_CONFIG_RESERVED1_MASK | \ + MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) + +#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior) \ + ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \ + (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \ + (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \ + (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \ + (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)) + +#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) + +#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int : 8; + } mh_mmu_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int : 8; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + } mh_mmu_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_config_t f; +} mh_mmu_config_u; + + +/* + * MH_MMU_VA_RANGE struct + */ + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12 +#define MH_MMU_VA_RANGE_VA_BASE_SIZE 20 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0 +#define MH_MMU_VA_RANGE_VA_BASE_SHIFT 12 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff +#define MH_MMU_VA_RANGE_VA_BASE_MASK 0xfffff000 + +#define MH_MMU_VA_RANGE_MASK \ + (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \ + MH_MMU_VA_RANGE_VA_BASE_MASK) + +#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \ + ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \ + (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)) + +#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + } mh_mmu_va_range_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + } mh_mmu_va_range_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_va_range_t f; +} mh_mmu_va_range_u; + + +/* + * MH_MMU_PT_BASE struct + */ + +#define MH_MMU_PT_BASE_PT_BASE_SIZE 20 + +#define MH_MMU_PT_BASE_PT_BASE_SHIFT 12 + +#define MH_MMU_PT_BASE_PT_BASE_MASK 0xfffff000 + +#define MH_MMU_PT_BASE_MASK \ + (MH_MMU_PT_BASE_PT_BASE_MASK) + +#define MH_MMU_PT_BASE(pt_base) \ + ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)) + +#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \ + ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \ + mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int : 12; + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + } mh_mmu_pt_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + unsigned int : 12; + } mh_mmu_pt_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_pt_base_t f; +} mh_mmu_pt_base_u; + + +/* + * MH_MMU_PAGE_FAULT struct + */ + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE 3 +#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE 20 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4 +#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11 +#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001 +#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c +#define MH_MMU_PAGE_FAULT_AXI_ID_MASK 0x00000070 +#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800 +#define MH_MMU_PAGE_FAULT_REQ_VA_MASK 0xfffff000 + +#define MH_MMU_PAGE_FAULT_MASK \ + (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \ + MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \ + MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \ + MH_MMU_PAGE_FAULT_AXI_ID_MASK | \ + MH_MMU_PAGE_FAULT_RESERVED1_MASK | \ + MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_REQ_VA_MASK) + +#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \ + ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \ + (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \ + (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \ + (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \ + (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \ + (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \ + (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \ + (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)) + +#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + } mh_mmu_page_fault_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + } mh_mmu_page_fault_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_page_fault_t f; +} mh_mmu_page_fault_u; + + +/* + * MH_MMU_TRAN_ERROR struct + */ + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0 + +#define MH_MMU_TRAN_ERROR_MASK \ + (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) + +#define MH_MMU_TRAN_ERROR(tran_error) \ + ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)) + +#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \ + ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \ + mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int : 5; + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + } mh_mmu_tran_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + unsigned int : 5; + } mh_mmu_tran_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_tran_error_t f; +} mh_mmu_tran_error_u; + + +/* + * MH_MMU_INVALIDATE struct + */ + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002 + +#define MH_MMU_INVALIDATE_MASK \ + (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) + +#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \ + ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)) + +#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int : 30; + } mh_mmu_invalidate_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int : 30; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + } mh_mmu_invalidate_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_invalidate_t f; +} mh_mmu_invalidate_u; + + +/* + * MH_MMU_MPU_BASE struct + */ + +#define MH_MMU_MPU_BASE_MPU_BASE_SIZE 20 + +#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12 + +#define MH_MMU_MPU_BASE_MPU_BASE_MASK 0xfffff000 + +#define MH_MMU_MPU_BASE_MASK \ + (MH_MMU_MPU_BASE_MPU_BASE_MASK) + +#define MH_MMU_MPU_BASE(mpu_base) \ + ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)) + +#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \ + ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \ + mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int : 12; + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + } mh_mmu_mpu_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + unsigned int : 12; + } mh_mmu_mpu_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_base_t f; +} mh_mmu_mpu_base_u; + + +/* + * MH_MMU_MPU_END struct + */ + +#define MH_MMU_MPU_END_MPU_END_SIZE 20 + +#define MH_MMU_MPU_END_MPU_END_SHIFT 12 + +#define MH_MMU_MPU_END_MPU_END_MASK 0xfffff000 + +#define MH_MMU_MPU_END_MASK \ + (MH_MMU_MPU_END_MPU_END_MASK) + +#define MH_MMU_MPU_END(mpu_end) \ + ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)) + +#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \ + ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT) + +#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \ + mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int : 12; + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + } mh_mmu_mpu_end_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + unsigned int : 12; + } mh_mmu_mpu_end_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_end_t f; +} mh_mmu_mpu_end_u; + + +#endif + + +#if !defined (_PA_FIDDLE_H) +#define _PA_FIDDLE_H + +/***************************************************************************************************************** + * + * pa_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * PA_CL_VPORT_XSCALE struct + */ + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_XSCALE_MASK \ + (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) + +#define PA_CL_VPORT_XSCALE(vport_xscale) \ + ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)) + +#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \ + ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \ + pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xscale_t f; +} pa_cl_vport_xscale_u; + + +/* + * PA_CL_VPORT_XOFFSET struct + */ + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_XOFFSET_MASK \ + (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) + +#define PA_CL_VPORT_XOFFSET(vport_xoffset) \ + ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)) + +#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \ + ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \ + pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xoffset_t f; +} pa_cl_vport_xoffset_u; + + +/* + * PA_CL_VPORT_YSCALE struct + */ + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_YSCALE_MASK \ + (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) + +#define PA_CL_VPORT_YSCALE(vport_yscale) \ + ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)) + +#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \ + ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \ + pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yscale_t f; +} pa_cl_vport_yscale_u; + + +/* + * PA_CL_VPORT_YOFFSET struct + */ + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_YOFFSET_MASK \ + (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) + +#define PA_CL_VPORT_YOFFSET(vport_yoffset) \ + ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)) + +#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \ + ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \ + pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yoffset_t f; +} pa_cl_vport_yoffset_u; + + +/* + * PA_CL_VPORT_ZSCALE struct + */ + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_ZSCALE_MASK \ + (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) + +#define PA_CL_VPORT_ZSCALE(vport_zscale) \ + ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)) + +#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \ + ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \ + pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zscale_t f; +} pa_cl_vport_zscale_u; + + +/* + * PA_CL_VPORT_ZOFFSET struct + */ + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_ZOFFSET_MASK \ + (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) + +#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \ + ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)) + +#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \ + ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \ + pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zoffset_t f; +} pa_cl_vport_zoffset_u; + + +/* + * PA_CL_VTE_CNTL struct + */ + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK 0x00000200 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800 + +#define PA_CL_VTE_CNTL_MASK \ + (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \ + PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) + +#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \ + ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \ + (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \ + (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \ + (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \ + (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \ + (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \ + (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \ + (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \ + (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \ + (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)) + +#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int : 2; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int : 20; + } pa_cl_vte_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int : 20; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int : 2; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + } pa_cl_vte_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vte_cntl_t f; +} pa_cl_vte_cntl_u; + + +/* + * PA_CL_CLIP_CNTL struct + */ + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000 + +#define PA_CL_CLIP_CNTL_MASK \ + (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \ + PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \ + PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \ + PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \ + PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \ + PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) + +#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \ + ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \ + (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \ + (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \ + (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \ + (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \ + (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \ + (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \ + (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)) + +#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 16; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 1; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int : 7; + } pa_cl_clip_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 7; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int : 1; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 16; + } pa_cl_clip_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_clip_cntl_t f; +} pa_cl_clip_cntl_u; + + +/* + * PA_CL_GB_VERT_CLIP_ADJ struct + */ + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_CLIP_ADJ_MASK \ + (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \ + ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \ + pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_clip_adj_t f; +} pa_cl_gb_vert_clip_adj_u; + + +/* + * PA_CL_GB_VERT_DISC_ADJ struct + */ + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_DISC_ADJ_MASK \ + (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \ + ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \ + pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_disc_adj_t f; +} pa_cl_gb_vert_disc_adj_u; + + +/* + * PA_CL_GB_HORZ_CLIP_ADJ struct + */ + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \ + (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \ + ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \ + pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_clip_adj_t f; +} pa_cl_gb_horz_clip_adj_u; + + +/* + * PA_CL_GB_HORZ_DISC_ADJ struct + */ + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_DISC_ADJ_MASK \ + (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \ + ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \ + pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_disc_adj_t f; +} pa_cl_gb_horz_disc_adj_u; + + +/* + * PA_CL_ENHANCE struct + */ + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0 +#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001 +#define PA_CL_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_CL_ENHANCE_MASK \ + (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \ + PA_CL_ENHANCE_ECO_SPARE3_MASK | \ + PA_CL_ENHANCE_ECO_SPARE2_MASK | \ + PA_CL_ENHANCE_ECO_SPARE1_MASK | \ + PA_CL_ENHANCE_ECO_SPARE0_MASK) + +#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \ + (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + unsigned int : 27; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + } pa_cl_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 27; + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + } pa_cl_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_enhance_t f; +} pa_cl_enhance_u; + + +/* + * PA_SC_ENHANCE struct + */ + +#define PA_SC_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_SC_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_SC_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_SC_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_SC_ENHANCE_MASK \ + (PA_SC_ENHANCE_ECO_SPARE3_MASK | \ + PA_SC_ENHANCE_ECO_SPARE2_MASK | \ + PA_SC_ENHANCE_ECO_SPARE1_MASK | \ + PA_SC_ENHANCE_ECO_SPARE0_MASK) + +#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int : 28; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + } pa_sc_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 28; + } pa_sc_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_enhance_t f; +} pa_sc_enhance_u; + + +/* + * PA_SU_VTX_CNTL struct + */ + +#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1 +#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2 +#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0 +#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1 +#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001 +#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006 +#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038 + +#define PA_SU_VTX_CNTL_MASK \ + (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \ + PA_SU_VTX_CNTL_ROUND_MODE_MASK | \ + PA_SU_VTX_CNTL_QUANT_MODE_MASK) + +#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \ + ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \ + (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \ + (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)) + +#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int : 26; + } pa_su_vtx_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int : 26; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + } pa_su_vtx_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_vtx_cntl_t f; +} pa_su_vtx_cntl_u; + + +/* + * PA_SU_POINT_SIZE struct + */ + +#define PA_SU_POINT_SIZE_HEIGHT_SIZE 16 +#define PA_SU_POINT_SIZE_WIDTH_SIZE 16 + +#define PA_SU_POINT_SIZE_HEIGHT_SHIFT 0 +#define PA_SU_POINT_SIZE_WIDTH_SHIFT 16 + +#define PA_SU_POINT_SIZE_HEIGHT_MASK 0x0000ffff +#define PA_SU_POINT_SIZE_WIDTH_MASK 0xffff0000 + +#define PA_SU_POINT_SIZE_MASK \ + (PA_SU_POINT_SIZE_HEIGHT_MASK | \ + PA_SU_POINT_SIZE_WIDTH_MASK) + +#define PA_SU_POINT_SIZE(height, width) \ + ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \ + (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)) + +#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + } pa_su_point_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + } pa_su_point_size_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_size_t f; +} pa_su_point_size_u; + + +/* + * PA_SU_POINT_MINMAX struct + */ + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff +#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000 + +#define PA_SU_POINT_MINMAX_MASK \ + (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \ + PA_SU_POINT_MINMAX_MAX_SIZE_MASK) + +#define PA_SU_POINT_MINMAX(min_size, max_size) \ + ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \ + (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)) + +#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + } pa_su_point_minmax_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + } pa_su_point_minmax_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_minmax_t f; +} pa_su_point_minmax_u; + + +/* + * PA_SU_LINE_CNTL struct + */ + +#define PA_SU_LINE_CNTL_WIDTH_SIZE 16 + +#define PA_SU_LINE_CNTL_WIDTH_SHIFT 0 + +#define PA_SU_LINE_CNTL_WIDTH_MASK 0x0000ffff + +#define PA_SU_LINE_CNTL_MASK \ + (PA_SU_LINE_CNTL_WIDTH_MASK) + +#define PA_SU_LINE_CNTL(width) \ + ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT)) + +#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \ + ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \ + pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + unsigned int : 16; + } pa_su_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int : 16; + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + } pa_su_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_line_cntl_t f; +} pa_su_line_cntl_u; + + +/* + * PA_SU_SC_MODE_CNTL struct + */ + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1 +#define PA_SU_SC_MODE_CNTL_FACE_SHIFT 2 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002 +#define PA_SU_SC_MODE_CNTL_FACE_MASK 0x00000004 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000 + +#define PA_SU_SC_MODE_CNTL_MASK \ + (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \ + PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \ + PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \ + PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \ + PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) + +#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state) \ + ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \ + (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \ + (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \ + (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \ + (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \ + (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \ + (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \ + (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \ + (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \ + (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \ + (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \ + (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \ + (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \ + (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \ + (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \ + (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \ + (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \ + (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)) + +#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) + +#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int : 1; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int : 1; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int : 5; + } pa_su_sc_mode_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int : 5; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int : 1; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int : 1; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + } pa_su_sc_mode_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_sc_mode_cntl_t f; +} pa_su_sc_mode_cntl_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \ + (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \ + ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \ + pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_scale_t f; +} pa_su_poly_offset_front_scale_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \ + ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \ + pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_offset_t f; +} pa_su_poly_offset_front_offset_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \ + (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \ + ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \ + pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_scale_t f; +} pa_su_poly_offset_back_scale_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \ + ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \ + pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_offset_t f; +} pa_su_poly_offset_back_offset_u; + + +/* + * PA_SU_PERFCOUNTER0_SELECT struct + */ + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER0_SELECT_MASK \ + (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \ + ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \ + pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_select_t f; +} pa_su_perfcounter0_select_u; + + +/* + * PA_SU_PERFCOUNTER1_SELECT struct + */ + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER1_SELECT_MASK \ + (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \ + ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \ + pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_select_t f; +} pa_su_perfcounter1_select_u; + + +/* + * PA_SU_PERFCOUNTER2_SELECT struct + */ + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER2_SELECT_MASK \ + (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \ + ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \ + pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_select_t f; +} pa_su_perfcounter2_select_u; + + +/* + * PA_SU_PERFCOUNTER3_SELECT struct + */ + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER3_SELECT_MASK \ + (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \ + ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \ + pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_select_t f; +} pa_su_perfcounter3_select_u; + + +/* + * PA_SU_PERFCOUNTER0_LOW struct + */ + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER0_LOW_MASK \ + (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \ + ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \ + pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_low_t f; +} pa_su_perfcounter0_low_u; + + +/* + * PA_SU_PERFCOUNTER0_HI struct + */ + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER0_HI_MASK \ + (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \ + ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \ + pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_hi_t f; +} pa_su_perfcounter0_hi_u; + + +/* + * PA_SU_PERFCOUNTER1_LOW struct + */ + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER1_LOW_MASK \ + (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \ + ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \ + pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_low_t f; +} pa_su_perfcounter1_low_u; + + +/* + * PA_SU_PERFCOUNTER1_HI struct + */ + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER1_HI_MASK \ + (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \ + ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \ + pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_hi_t f; +} pa_su_perfcounter1_hi_u; + + +/* + * PA_SU_PERFCOUNTER2_LOW struct + */ + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER2_LOW_MASK \ + (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \ + ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \ + pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_low_t f; +} pa_su_perfcounter2_low_u; + + +/* + * PA_SU_PERFCOUNTER2_HI struct + */ + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER2_HI_MASK \ + (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \ + ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \ + pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_hi_t f; +} pa_su_perfcounter2_hi_u; + + +/* + * PA_SU_PERFCOUNTER3_LOW struct + */ + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER3_LOW_MASK \ + (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \ + ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \ + pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_low_t f; +} pa_su_perfcounter3_low_u; + + +/* + * PA_SU_PERFCOUNTER3_HI struct + */ + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER3_HI_MASK \ + (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \ + ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \ + pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_hi_t f; +} pa_su_perfcounter3_hi_u; + + +/* + * PA_SC_WINDOW_OFFSET struct + */ + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000 + +#define PA_SC_WINDOW_OFFSET_MASK \ + (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \ + PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) + +#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \ + ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \ + (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)) + +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + } pa_sc_window_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + } pa_sc_window_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_offset_t f; +} pa_sc_window_offset_u; + + +/* + * PA_SC_AA_CONFIG struct + */ + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000 + +#define PA_SC_AA_CONFIG_MASK \ + (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \ + PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) + +#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \ + ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \ + (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)) + +#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + unsigned int : 10; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 15; + } pa_sc_aa_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int : 15; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 10; + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + } pa_sc_aa_config_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_config_t f; +} pa_sc_aa_config_u; + + +/* + * PA_SC_AA_MASK struct + */ + +#define PA_SC_AA_MASK_AA_MASK_SIZE 16 + +#define PA_SC_AA_MASK_AA_MASK_SHIFT 0 + +#define PA_SC_AA_MASK_AA_MASK_MASK 0x0000ffff + +#define PA_SC_AA_MASK_MASK \ + (PA_SC_AA_MASK_AA_MASK_MASK) + +#define PA_SC_AA_MASK(aa_mask) \ + ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)) + +#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \ + ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT) + +#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \ + pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + unsigned int : 16; + } pa_sc_aa_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int : 16; + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + } pa_sc_aa_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_mask_t f; +} pa_sc_aa_mask_u; + + +/* + * PA_SC_LINE_STIPPLE struct + */ + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000 + +#define PA_SC_LINE_STIPPLE_MASK \ + (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \ + PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \ + PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \ + PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) + +#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \ + ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \ + (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \ + (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \ + (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)) + +#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int : 4; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int : 1; + } pa_sc_line_stipple_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int : 1; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int : 4; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + } pa_sc_line_stipple_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_t f; +} pa_sc_line_stipple_u; + + +/* + * PA_SC_LINE_CNTL struct + */ + +#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1 + +#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10 + +#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200 +#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400 + +#define PA_SC_LINE_CNTL_MASK \ + (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \ + PA_SC_LINE_CNTL_LAST_PIXEL_MASK) + +#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \ + ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \ + (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \ + (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \ + (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)) + +#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int : 21; + } pa_sc_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int : 21; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + } pa_sc_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_cntl_t f; +} pa_sc_line_cntl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_TL struct + */ + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000 + +#define PA_SC_WINDOW_SCISSOR_TL_MASK \ + (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) + +#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \ + ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \ + (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + unsigned int : 2; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + } pa_sc_window_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 2; + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + } pa_sc_window_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_tl_t f; +} pa_sc_window_scissor_tl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_BR struct + */ + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000 + +#define PA_SC_WINDOW_SCISSOR_BR_MASK \ + (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \ + PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + } pa_sc_window_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + } pa_sc_window_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_br_t f; +} pa_sc_window_scissor_br_u; + + +/* + * PA_SC_SCREEN_SCISSOR_TL struct + */ + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_TL_MASK \ + (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \ + PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \ + ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + } pa_sc_screen_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_tl_t f; +} pa_sc_screen_scissor_tl_u; + + +/* + * PA_SC_SCREEN_SCISSOR_BR struct + */ + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_BR_MASK \ + (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \ + PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + } pa_sc_screen_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_br_t f; +} pa_sc_screen_scissor_br_u; + + +/* + * PA_SC_VIZ_QUERY struct + */ + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080 + +#define PA_SC_VIZ_QUERY_MASK \ + (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \ + PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \ + PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) + +#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \ + ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \ + (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \ + (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)) + +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int : 1; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 24; + } pa_sc_viz_query_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int : 24; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 1; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + } pa_sc_viz_query_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_t f; +} pa_sc_viz_query_u; + + +/* + * PA_SC_VIZ_QUERY_STATUS struct + */ + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff + +#define PA_SC_VIZ_QUERY_STATUS_MASK \ + (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) + +#define PA_SC_VIZ_QUERY_STATUS(status_bits) \ + ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)) + +#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \ + ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \ + pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_status_t f; +} pa_sc_viz_query_status_u; + + +/* + * PA_SC_LINE_STIPPLE_STATE struct + */ + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00 + +#define PA_SC_LINE_STIPPLE_STATE_MASK \ + (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \ + PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) + +#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \ + ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \ + (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)) + +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + unsigned int : 4; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 16; + } pa_sc_line_stipple_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int : 16; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 4; + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + } pa_sc_line_stipple_state_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_state_t f; +} pa_sc_line_stipple_state_u; + + +/* + * PA_SC_PERFCOUNTER0_SELECT struct + */ + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SC_PERFCOUNTER0_SELECT_MASK \ + (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \ + ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \ + pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_sc_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_sc_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_select_t f; +} pa_sc_perfcounter0_select_u; + + +/* + * PA_SC_PERFCOUNTER0_LOW struct + */ + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SC_PERFCOUNTER0_LOW_MASK \ + (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \ + ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \ + pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_low_t f; +} pa_sc_perfcounter0_low_u; + + +/* + * PA_SC_PERFCOUNTER0_HI struct + */ + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SC_PERFCOUNTER0_HI_MASK \ + (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \ + ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \ + pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_sc_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_hi_t f; +} pa_sc_perfcounter0_hi_u; + + +/* + * PA_CL_CNTL_STATUS struct + */ + +#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1 + +#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31 + +#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000 + +#define PA_CL_CNTL_STATUS_MASK \ + (PA_CL_CNTL_STATUS_CL_BUSY_MASK) + +#define PA_CL_CNTL_STATUS(cl_busy) \ + ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)) + +#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \ + ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \ + pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int : 31; + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + } pa_cl_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + unsigned int : 31; + } pa_cl_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_cntl_status_t f; +} pa_cl_cntl_status_u; + + +/* + * PA_SU_CNTL_STATUS struct + */ + +#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1 + +#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31 + +#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000 + +#define PA_SU_CNTL_STATUS_MASK \ + (PA_SU_CNTL_STATUS_SU_BUSY_MASK) + +#define PA_SU_CNTL_STATUS(su_busy) \ + ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)) + +#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \ + ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \ + pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int : 31; + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + } pa_su_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + unsigned int : 31; + } pa_su_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_cntl_status_t f; +} pa_su_cntl_status_u; + + +/* + * PA_SC_CNTL_STATUS struct + */ + +#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1 + +#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31 + +#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000 + +#define PA_SC_CNTL_STATUS_MASK \ + (PA_SC_CNTL_STATUS_SC_BUSY_MASK) + +#define PA_SC_CNTL_STATUS(sc_busy) \ + ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)) + +#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \ + ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \ + pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int : 31; + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + } pa_sc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + unsigned int : 31; + } pa_sc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_cntl_status_t f; +} pa_sc_cntl_status_u; + + +/* + * PA_SU_DEBUG_CNTL struct + */ + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f + +#define PA_SU_DEBUG_CNTL_MASK \ + (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) + +#define PA_SU_DEBUG_CNTL(su_debug_indx) \ + ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)) + +#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \ + ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \ + pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_su_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int : 27; + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + } pa_su_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_cntl_t f; +} pa_su_debug_cntl_u; + + +/* + * PA_SU_DEBUG_DATA struct + */ + +#define PA_SU_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SU_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SU_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SU_DEBUG_DATA_MASK \ + (PA_SU_DEBUG_DATA_DATA_MASK) + +#define PA_SU_DEBUG_DATA(data) \ + ((data << PA_SU_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \ + ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT) + +#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \ + pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_data_t f; +} pa_su_debug_data_u; + + +/* + * CLIPPER_DEBUG_REG00 struct + */ + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000 + +#define CLIPPER_DEBUG_REG00_MASK \ + (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \ + ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \ + (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \ + (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \ + (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \ + (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \ + (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \ + (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \ + (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \ + (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \ + (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \ + (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \ + (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \ + (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \ + (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \ + (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \ + (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \ + (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \ + (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \ + (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \ + (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + } clipper_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + } clipper_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg00_t f; +} clipper_debug_reg00_u; + + +/* + * CLIPPER_DEBUG_REG01 struct + */ + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000 + +#define CLIPPER_DEBUG_REG01_MASK \ + (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \ + CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \ + ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \ + (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \ + (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \ + (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \ + (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \ + (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \ + (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + } clipper_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + } clipper_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg01_t f; +} clipper_debug_reg01_u; + + +/* + * CLIPPER_DEBUG_REG02 struct + */ + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 + +#define CLIPPER_DEBUG_REG02_MASK \ + (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \ + CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) + +#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \ + ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \ + (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)) + +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + } clipper_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + } clipper_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg02_t f; +} clipper_debug_reg02_u; + + +/* + * CLIPPER_DEBUG_REG03 struct + */ + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG03_MASK \ + (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \ + ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + } clipper_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg03_t f; +} clipper_debug_reg03_u; + + +/* + * CLIPPER_DEBUG_REG04 struct + */ + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00 + +#define CLIPPER_DEBUG_REG04_MASK \ + (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \ + ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + } clipper_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg04_t f; +} clipper_debug_reg04_u; + + +/* + * CLIPPER_DEBUG_REG05 struct + */ + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000 + +#define CLIPPER_DEBUG_REG05_MASK \ + (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \ + ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \ + (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + } clipper_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg05_t f; +} clipper_debug_reg05_u; + + +/* + * CLIPPER_DEBUG_REG09 struct + */ + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000 +#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000 + +#define CLIPPER_DEBUG_REG09_MASK \ + (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \ + CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) + +#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \ + ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \ + (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \ + (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \ + (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \ + (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \ + (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \ + (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \ + (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \ + (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \ + (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \ + (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)) + +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + } clipper_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + } clipper_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg09_t f; +} clipper_debug_reg09_u; + + +/* + * CLIPPER_DEBUG_REG10 struct + */ + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG10_MASK \ + (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) + +#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \ + ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \ + (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \ + (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \ + (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \ + (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)) + +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + } clipper_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + } clipper_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg10_t f; +} clipper_debug_reg10_u; + + +/* + * CLIPPER_DEBUG_REG11 struct + */ + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0 + +#define CLIPPER_DEBUG_REG11_MASK \ + (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \ + CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \ + ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + } clipper_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + } clipper_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg11_t f; +} clipper_debug_reg11_u; + + +/* + * CLIPPER_DEBUG_REG12 struct + */ + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000 + +#define CLIPPER_DEBUG_REG12_MASK \ + (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \ + CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \ + ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \ + (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \ + (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \ + (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \ + (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \ + (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + } clipper_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg12_t f; +} clipper_debug_reg12_u; + + +/* + * CLIPPER_DEBUG_REG13 struct + */ + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000 +#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000 + +#define CLIPPER_DEBUG_REG13_MASK \ + (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \ + CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \ + ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \ + (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \ + (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \ + (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \ + (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \ + (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + } clipper_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg13_t f; +} clipper_debug_reg13_u; + + +/* + * SXIFCCG_DEBUG_REG0 struct + */ + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4 +#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3 +#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0 +#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380 +#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000 + +#define SXIFCCG_DEBUG_REG0_MASK \ + (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \ + SXIFCCG_DEBUG_REG0_position_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG0_point_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) + +#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \ + ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \ + (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \ + (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \ + (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \ + (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \ + (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \ + (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \ + (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)) + +#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + } sxifccg_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + } sxifccg_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg0_t f; +} sxifccg_debug_reg0_u; + + +/* + * SXIFCCG_DEBUG_REG1 struct + */ + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4 +#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c +#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000 +#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000 +#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000 + +#define SXIFCCG_DEBUG_REG1_MASK \ + (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \ + SXIFCCG_DEBUG_REG1_available_positions_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \ + SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \ + SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG1_aux_sel_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \ + SXIFCCG_DEBUG_REG1_param_cache_base_MASK) + +#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \ + ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \ + (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \ + (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \ + (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \ + (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \ + (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \ + (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \ + (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)) + +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + } sxifccg_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + } sxifccg_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg1_t f; +} sxifccg_debug_reg1_u; + + +/* + * SXIFCCG_DEBUG_REG2 struct + */ + +#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3 + +#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29 + +#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002 +#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8 +#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000 + +#define SXIFCCG_DEBUG_REG2_MASK \ + (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG2_sx_aux_MASK | \ + SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) + +#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \ + ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \ + (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \ + (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \ + (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \ + (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \ + (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \ + (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \ + (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \ + (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \ + (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)) + +#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + } sxifccg_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + } sxifccg_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg2_t f; +} sxifccg_debug_reg2_u; + + +/* + * SXIFCCG_DEBUG_REG3 struct + */ + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4 +#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8 +#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010 +#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00 +#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000 + +#define SXIFCCG_DEBUG_REG3_MASK \ + (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG3_available_positions_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG3_current_state_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) + +#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \ + ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \ + (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \ + (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \ + (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \ + (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \ + (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \ + (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \ + (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)) + +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + } sxifccg_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + } sxifccg_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg3_t f; +} sxifccg_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG0 struct + */ + +#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5 +#define SETUP_DEBUG_REG0_pmode_state_SIZE 6 +#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1 +#define SETUP_DEBUG_REG0_geom_enable_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1 +#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1 +#define SETUP_DEBUG_REG0_geom_busy_SIZE 1 + +#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0 +#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5 +#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11 +#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13 +#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14 +#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15 +#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16 +#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17 + +#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f +#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0 +#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800 +#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000 +#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000 +#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000 +#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000 +#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000 + +#define SETUP_DEBUG_REG0_MASK \ + (SETUP_DEBUG_REG0_su_cntl_state_MASK | \ + SETUP_DEBUG_REG0_pmode_state_MASK | \ + SETUP_DEBUG_REG0_ge_stallb_MASK | \ + SETUP_DEBUG_REG0_geom_enable_MASK | \ + SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \ + SETUP_DEBUG_REG0_su_clip_rtr_MASK | \ + SETUP_DEBUG_REG0_pfifo_busy_MASK | \ + SETUP_DEBUG_REG0_su_cntl_busy_MASK | \ + SETUP_DEBUG_REG0_geom_busy_MASK) + +#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \ + ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \ + (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \ + (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \ + (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \ + (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \ + (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \ + (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \ + (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \ + (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)) + +#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int : 14; + } setup_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int : 14; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + } setup_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg0_t f; +} setup_debug_reg0_u; + + +/* + * SETUP_DEBUG_REG1 struct + */ + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG1_MASK \ + (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \ + SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) + +#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \ + ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \ + (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + } setup_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg1_t f; +} setup_debug_reg1_u; + + +/* + * SETUP_DEBUG_REG2 struct + */ + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG2_MASK \ + (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \ + SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) + +#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \ + ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \ + (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + } setup_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg2_t f; +} setup_debug_reg2_u; + + +/* + * SETUP_DEBUG_REG3 struct + */ + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG3_MASK \ + (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \ + SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) + +#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \ + ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \ + (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + } setup_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg3_t f; +} setup_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG4 struct + */ + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11 +#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1 +#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3 +#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3 +#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2 +#define SETUP_DEBUG_REG4_type_gated_SIZE 3 +#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_event_gated_SIZE 1 +#define SETUP_DEBUG_REG4_eop_gated_SIZE 1 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0 +#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11 +#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12 +#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13 +#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17 +#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21 +#define SETUP_DEBUG_REG4_type_gated_SHIFT 23 +#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27 +#define SETUP_DEBUG_REG4_event_gated_SHIFT 28 +#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800 +#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000 +#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000 +#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000 +#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000 +#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000 +#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000 +#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000 +#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000 +#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000 + +#define SETUP_DEBUG_REG4_MASK \ + (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \ + SETUP_DEBUG_REG4_null_prim_gated_MASK | \ + SETUP_DEBUG_REG4_backfacing_gated_MASK | \ + SETUP_DEBUG_REG4_st_indx_gated_MASK | \ + SETUP_DEBUG_REG4_clipped_gated_MASK | \ + SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \ + SETUP_DEBUG_REG4_xmajor_gated_MASK | \ + SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \ + SETUP_DEBUG_REG4_type_gated_MASK | \ + SETUP_DEBUG_REG4_fpov_gated_MASK | \ + SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \ + SETUP_DEBUG_REG4_event_gated_MASK | \ + SETUP_DEBUG_REG4_eop_gated_MASK) + +#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \ + ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \ + (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \ + (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \ + (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \ + (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \ + (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \ + (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \ + (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \ + (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \ + (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \ + (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \ + (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \ + (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)) + +#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int : 2; + } setup_debug_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int : 2; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + } setup_debug_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg4_t f; +} setup_debug_reg4_u; + + +/* + * SETUP_DEBUG_REG5 struct + */ + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2 +#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22 +#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000 +#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000 + +#define SETUP_DEBUG_REG5_MASK \ + (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \ + SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \ + SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \ + SETUP_DEBUG_REG5_event_id_gated_MASK) + +#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \ + ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \ + (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \ + (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \ + (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)) + +#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int : 3; + } setup_debug_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int : 3; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + } setup_debug_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg5_t f; +} setup_debug_reg5_u; + + +/* + * PA_SC_DEBUG_CNTL struct + */ + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f + +#define PA_SC_DEBUG_CNTL_MASK \ + (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) + +#define PA_SC_DEBUG_CNTL(sc_debug_indx) \ + ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)) + +#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \ + ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \ + pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_sc_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int : 27; + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + } pa_sc_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_cntl_t f; +} pa_sc_debug_cntl_u; + + +/* + * PA_SC_DEBUG_DATA struct + */ + +#define PA_SC_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SC_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SC_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SC_DEBUG_DATA_MASK \ + (PA_SC_DEBUG_DATA_DATA_MASK) + +#define PA_SC_DEBUG_DATA(data) \ + ((data << PA_SC_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \ + ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT) + +#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \ + pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_data_t f; +} pa_sc_debug_data_u; + + +/* + * SC_DEBUG_0 struct + */ + +#define SC_DEBUG_0_pa_freeze_b1_SIZE 1 +#define SC_DEBUG_0_pa_sc_valid_SIZE 1 +#define SC_DEBUG_0_pa_sc_phase_SIZE 3 +#define SC_DEBUG_0_cntx_cnt_SIZE 7 +#define SC_DEBUG_0_decr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_incr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_trigger_SIZE 1 + +#define SC_DEBUG_0_pa_freeze_b1_SHIFT 0 +#define SC_DEBUG_0_pa_sc_valid_SHIFT 1 +#define SC_DEBUG_0_pa_sc_phase_SHIFT 2 +#define SC_DEBUG_0_cntx_cnt_SHIFT 5 +#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12 +#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13 +#define SC_DEBUG_0_trigger_SHIFT 31 + +#define SC_DEBUG_0_pa_freeze_b1_MASK 0x00000001 +#define SC_DEBUG_0_pa_sc_valid_MASK 0x00000002 +#define SC_DEBUG_0_pa_sc_phase_MASK 0x0000001c +#define SC_DEBUG_0_cntx_cnt_MASK 0x00000fe0 +#define SC_DEBUG_0_decr_cntx_cnt_MASK 0x00001000 +#define SC_DEBUG_0_incr_cntx_cnt_MASK 0x00002000 +#define SC_DEBUG_0_trigger_MASK 0x80000000 + +#define SC_DEBUG_0_MASK \ + (SC_DEBUG_0_pa_freeze_b1_MASK | \ + SC_DEBUG_0_pa_sc_valid_MASK | \ + SC_DEBUG_0_pa_sc_phase_MASK | \ + SC_DEBUG_0_cntx_cnt_MASK | \ + SC_DEBUG_0_decr_cntx_cnt_MASK | \ + SC_DEBUG_0_incr_cntx_cnt_MASK | \ + SC_DEBUG_0_trigger_MASK) + +#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \ + ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \ + (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \ + (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \ + (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \ + (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \ + (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \ + (trigger << SC_DEBUG_0_trigger_SHIFT)) + +#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_trigger(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT) + +#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int : 17; + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + } sc_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + unsigned int : 17; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + } sc_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_0_t f; +} sc_debug_0_u; + + +/* + * SC_DEBUG_1 struct + */ + +#define SC_DEBUG_1_em_state_SIZE 3 +#define SC_DEBUG_1_em1_data_ready_SIZE 1 +#define SC_DEBUG_1_em2_data_ready_SIZE 1 +#define SC_DEBUG_1_move_em1_to_em2_SIZE 1 +#define SC_DEBUG_1_ef_data_ready_SIZE 1 +#define SC_DEBUG_1_ef_state_SIZE 2 +#define SC_DEBUG_1_pipe_valid_SIZE 1 +#define SC_DEBUG_1_trigger_SIZE 1 + +#define SC_DEBUG_1_em_state_SHIFT 0 +#define SC_DEBUG_1_em1_data_ready_SHIFT 3 +#define SC_DEBUG_1_em2_data_ready_SHIFT 4 +#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5 +#define SC_DEBUG_1_ef_data_ready_SHIFT 6 +#define SC_DEBUG_1_ef_state_SHIFT 7 +#define SC_DEBUG_1_pipe_valid_SHIFT 9 +#define SC_DEBUG_1_trigger_SHIFT 31 + +#define SC_DEBUG_1_em_state_MASK 0x00000007 +#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008 +#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010 +#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020 +#define SC_DEBUG_1_ef_data_ready_MASK 0x00000040 +#define SC_DEBUG_1_ef_state_MASK 0x00000180 +#define SC_DEBUG_1_pipe_valid_MASK 0x00000200 +#define SC_DEBUG_1_trigger_MASK 0x80000000 + +#define SC_DEBUG_1_MASK \ + (SC_DEBUG_1_em_state_MASK | \ + SC_DEBUG_1_em1_data_ready_MASK | \ + SC_DEBUG_1_em2_data_ready_MASK | \ + SC_DEBUG_1_move_em1_to_em2_MASK | \ + SC_DEBUG_1_ef_data_ready_MASK | \ + SC_DEBUG_1_ef_state_MASK | \ + SC_DEBUG_1_pipe_valid_MASK | \ + SC_DEBUG_1_trigger_MASK) + +#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \ + ((em_state << SC_DEBUG_1_em_state_SHIFT) | \ + (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \ + (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \ + (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \ + (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \ + (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \ + (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \ + (trigger << SC_DEBUG_1_trigger_SHIFT)) + +#define SC_DEBUG_1_GET_em_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_GET_trigger(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT) + +#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int : 21; + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + } sc_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + unsigned int : 21; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + } sc_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_1_t f; +} sc_debug_1_u; + + +/* + * SC_DEBUG_2 struct + */ + +#define SC_DEBUG_2_rc_rtr_dly_SIZE 1 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1 +#define SC_DEBUG_2_pipe_freeze_b_SIZE 1 +#define SC_DEBUG_2_prim_rts_SIZE 1 +#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1 +#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1 +#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1 +#define SC_DEBUG_2_stage0_rts_SIZE 1 +#define SC_DEBUG_2_phase_rts_dly_SIZE 1 +#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1 +#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1 +#define SC_DEBUG_2_event_id_s1_SIZE 5 +#define SC_DEBUG_2_event_s1_SIZE 1 +#define SC_DEBUG_2_trigger_SIZE 1 + +#define SC_DEBUG_2_rc_rtr_dly_SHIFT 0 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1 +#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3 +#define SC_DEBUG_2_prim_rts_SHIFT 4 +#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5 +#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6 +#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7 +#define SC_DEBUG_2_stage0_rts_SHIFT 8 +#define SC_DEBUG_2_phase_rts_dly_SHIFT 9 +#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15 +#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16 +#define SC_DEBUG_2_event_id_s1_SHIFT 17 +#define SC_DEBUG_2_event_s1_SHIFT 22 +#define SC_DEBUG_2_trigger_SHIFT 31 + +#define SC_DEBUG_2_rc_rtr_dly_MASK 0x00000001 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002 +#define SC_DEBUG_2_pipe_freeze_b_MASK 0x00000008 +#define SC_DEBUG_2_prim_rts_MASK 0x00000010 +#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020 +#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040 +#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080 +#define SC_DEBUG_2_stage0_rts_MASK 0x00000100 +#define SC_DEBUG_2_phase_rts_dly_MASK 0x00000200 +#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000 +#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000 +#define SC_DEBUG_2_event_id_s1_MASK 0x003e0000 +#define SC_DEBUG_2_event_s1_MASK 0x00400000 +#define SC_DEBUG_2_trigger_MASK 0x80000000 + +#define SC_DEBUG_2_MASK \ + (SC_DEBUG_2_rc_rtr_dly_MASK | \ + SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \ + SC_DEBUG_2_pipe_freeze_b_MASK | \ + SC_DEBUG_2_prim_rts_MASK | \ + SC_DEBUG_2_next_prim_rts_dly_MASK | \ + SC_DEBUG_2_next_prim_rtr_dly_MASK | \ + SC_DEBUG_2_pre_stage1_rts_d1_MASK | \ + SC_DEBUG_2_stage0_rts_MASK | \ + SC_DEBUG_2_phase_rts_dly_MASK | \ + SC_DEBUG_2_end_of_prim_s1_dly_MASK | \ + SC_DEBUG_2_pass_empty_prim_s1_MASK | \ + SC_DEBUG_2_event_id_s1_MASK | \ + SC_DEBUG_2_event_s1_MASK | \ + SC_DEBUG_2_trigger_MASK) + +#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \ + ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \ + (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \ + (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \ + (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \ + (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \ + (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \ + (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \ + (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \ + (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \ + (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \ + (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \ + (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \ + (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \ + (trigger << SC_DEBUG_2_trigger_SHIFT)) + +#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_GET_trigger(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT) + +#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int : 1; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int : 8; + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + } sc_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + unsigned int : 8; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int : 5; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + } sc_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_2_t f; +} sc_debug_2_u; + + +/* + * SC_DEBUG_3 struct + */ + +#define SC_DEBUG_3_x_curr_s1_SIZE 11 +#define SC_DEBUG_3_y_curr_s1_SIZE 11 +#define SC_DEBUG_3_trigger_SIZE 1 + +#define SC_DEBUG_3_x_curr_s1_SHIFT 0 +#define SC_DEBUG_3_y_curr_s1_SHIFT 11 +#define SC_DEBUG_3_trigger_SHIFT 31 + +#define SC_DEBUG_3_x_curr_s1_MASK 0x000007ff +#define SC_DEBUG_3_y_curr_s1_MASK 0x003ff800 +#define SC_DEBUG_3_trigger_MASK 0x80000000 + +#define SC_DEBUG_3_MASK \ + (SC_DEBUG_3_x_curr_s1_MASK | \ + SC_DEBUG_3_y_curr_s1_MASK | \ + SC_DEBUG_3_trigger_MASK) + +#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \ + ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \ + (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \ + (trigger << SC_DEBUG_3_trigger_SHIFT)) + +#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_trigger(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT) + +#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int : 9; + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + } sc_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + unsigned int : 9; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + } sc_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_3_t f; +} sc_debug_3_u; + + +/* + * SC_DEBUG_4 struct + */ + +#define SC_DEBUG_4_y_end_s1_SIZE 14 +#define SC_DEBUG_4_y_start_s1_SIZE 14 +#define SC_DEBUG_4_y_dir_s1_SIZE 1 +#define SC_DEBUG_4_trigger_SIZE 1 + +#define SC_DEBUG_4_y_end_s1_SHIFT 0 +#define SC_DEBUG_4_y_start_s1_SHIFT 14 +#define SC_DEBUG_4_y_dir_s1_SHIFT 28 +#define SC_DEBUG_4_trigger_SHIFT 31 + +#define SC_DEBUG_4_y_end_s1_MASK 0x00003fff +#define SC_DEBUG_4_y_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_4_y_dir_s1_MASK 0x10000000 +#define SC_DEBUG_4_trigger_MASK 0x80000000 + +#define SC_DEBUG_4_MASK \ + (SC_DEBUG_4_y_end_s1_MASK | \ + SC_DEBUG_4_y_start_s1_MASK | \ + SC_DEBUG_4_y_dir_s1_MASK | \ + SC_DEBUG_4_trigger_MASK) + +#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \ + ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \ + (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \ + (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_4_trigger_SHIFT)) + +#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_GET_trigger(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT) + +#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + } sc_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + unsigned int : 2; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + } sc_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_4_t f; +} sc_debug_4_u; + + +/* + * SC_DEBUG_5 struct + */ + +#define SC_DEBUG_5_x_end_s1_SIZE 14 +#define SC_DEBUG_5_x_start_s1_SIZE 14 +#define SC_DEBUG_5_x_dir_s1_SIZE 1 +#define SC_DEBUG_5_trigger_SIZE 1 + +#define SC_DEBUG_5_x_end_s1_SHIFT 0 +#define SC_DEBUG_5_x_start_s1_SHIFT 14 +#define SC_DEBUG_5_x_dir_s1_SHIFT 28 +#define SC_DEBUG_5_trigger_SHIFT 31 + +#define SC_DEBUG_5_x_end_s1_MASK 0x00003fff +#define SC_DEBUG_5_x_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_5_x_dir_s1_MASK 0x10000000 +#define SC_DEBUG_5_trigger_MASK 0x80000000 + +#define SC_DEBUG_5_MASK \ + (SC_DEBUG_5_x_end_s1_MASK | \ + SC_DEBUG_5_x_start_s1_MASK | \ + SC_DEBUG_5_x_dir_s1_MASK | \ + SC_DEBUG_5_trigger_MASK) + +#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \ + ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \ + (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \ + (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_5_trigger_SHIFT)) + +#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_GET_trigger(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT) + +#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + } sc_debug_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + unsigned int : 2; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + } sc_debug_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_5_t f; +} sc_debug_5_u; + + +/* + * SC_DEBUG_6 struct + */ + +#define SC_DEBUG_6_z_ff_empty_SIZE 1 +#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1 +#define SC_DEBUG_6_xy_ff_empty_SIZE 1 +#define SC_DEBUG_6_event_flag_SIZE 1 +#define SC_DEBUG_6_z_mask_needed_SIZE 1 +#define SC_DEBUG_6_state_SIZE 3 +#define SC_DEBUG_6_state_delayed_SIZE 3 +#define SC_DEBUG_6_data_valid_SIZE 1 +#define SC_DEBUG_6_data_valid_d_SIZE 1 +#define SC_DEBUG_6_tilex_delayed_SIZE 9 +#define SC_DEBUG_6_tiley_delayed_SIZE 9 +#define SC_DEBUG_6_trigger_SIZE 1 + +#define SC_DEBUG_6_z_ff_empty_SHIFT 0 +#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1 +#define SC_DEBUG_6_xy_ff_empty_SHIFT 2 +#define SC_DEBUG_6_event_flag_SHIFT 3 +#define SC_DEBUG_6_z_mask_needed_SHIFT 4 +#define SC_DEBUG_6_state_SHIFT 5 +#define SC_DEBUG_6_state_delayed_SHIFT 8 +#define SC_DEBUG_6_data_valid_SHIFT 11 +#define SC_DEBUG_6_data_valid_d_SHIFT 12 +#define SC_DEBUG_6_tilex_delayed_SHIFT 13 +#define SC_DEBUG_6_tiley_delayed_SHIFT 22 +#define SC_DEBUG_6_trigger_SHIFT 31 + +#define SC_DEBUG_6_z_ff_empty_MASK 0x00000001 +#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002 +#define SC_DEBUG_6_xy_ff_empty_MASK 0x00000004 +#define SC_DEBUG_6_event_flag_MASK 0x00000008 +#define SC_DEBUG_6_z_mask_needed_MASK 0x00000010 +#define SC_DEBUG_6_state_MASK 0x000000e0 +#define SC_DEBUG_6_state_delayed_MASK 0x00000700 +#define SC_DEBUG_6_data_valid_MASK 0x00000800 +#define SC_DEBUG_6_data_valid_d_MASK 0x00001000 +#define SC_DEBUG_6_tilex_delayed_MASK 0x003fe000 +#define SC_DEBUG_6_tiley_delayed_MASK 0x7fc00000 +#define SC_DEBUG_6_trigger_MASK 0x80000000 + +#define SC_DEBUG_6_MASK \ + (SC_DEBUG_6_z_ff_empty_MASK | \ + SC_DEBUG_6_qmcntl_ff_empty_MASK | \ + SC_DEBUG_6_xy_ff_empty_MASK | \ + SC_DEBUG_6_event_flag_MASK | \ + SC_DEBUG_6_z_mask_needed_MASK | \ + SC_DEBUG_6_state_MASK | \ + SC_DEBUG_6_state_delayed_MASK | \ + SC_DEBUG_6_data_valid_MASK | \ + SC_DEBUG_6_data_valid_d_MASK | \ + SC_DEBUG_6_tilex_delayed_MASK | \ + SC_DEBUG_6_tiley_delayed_MASK | \ + SC_DEBUG_6_trigger_MASK) + +#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \ + ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \ + (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \ + (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \ + (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \ + (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \ + (state << SC_DEBUG_6_state_SHIFT) | \ + (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \ + (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \ + (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \ + (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \ + (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \ + (trigger << SC_DEBUG_6_trigger_SHIFT)) + +#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_GET_state(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_GET_trigger(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT) + +#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + } sc_debug_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + } sc_debug_6_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_6_t f; +} sc_debug_6_u; + + +/* + * SC_DEBUG_7 struct + */ + +#define SC_DEBUG_7_event_flag_SIZE 1 +#define SC_DEBUG_7_deallocate_SIZE 3 +#define SC_DEBUG_7_fpos_SIZE 1 +#define SC_DEBUG_7_sr_prim_we_SIZE 1 +#define SC_DEBUG_7_last_tile_SIZE 1 +#define SC_DEBUG_7_tile_ff_we_SIZE 1 +#define SC_DEBUG_7_qs_data_valid_SIZE 1 +#define SC_DEBUG_7_qs_q0_y_SIZE 2 +#define SC_DEBUG_7_qs_q0_x_SIZE 2 +#define SC_DEBUG_7_qs_q0_valid_SIZE 1 +#define SC_DEBUG_7_prim_ff_we_SIZE 1 +#define SC_DEBUG_7_tile_ff_re_SIZE 1 +#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_7_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_7_new_prim_SIZE 1 +#define SC_DEBUG_7_load_new_tile_data_SIZE 1 +#define SC_DEBUG_7_state_SIZE 2 +#define SC_DEBUG_7_fifos_ready_SIZE 1 +#define SC_DEBUG_7_trigger_SIZE 1 + +#define SC_DEBUG_7_event_flag_SHIFT 0 +#define SC_DEBUG_7_deallocate_SHIFT 1 +#define SC_DEBUG_7_fpos_SHIFT 4 +#define SC_DEBUG_7_sr_prim_we_SHIFT 5 +#define SC_DEBUG_7_last_tile_SHIFT 6 +#define SC_DEBUG_7_tile_ff_we_SHIFT 7 +#define SC_DEBUG_7_qs_data_valid_SHIFT 8 +#define SC_DEBUG_7_qs_q0_y_SHIFT 9 +#define SC_DEBUG_7_qs_q0_x_SHIFT 11 +#define SC_DEBUG_7_qs_q0_valid_SHIFT 13 +#define SC_DEBUG_7_prim_ff_we_SHIFT 14 +#define SC_DEBUG_7_tile_ff_re_SHIFT 15 +#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16 +#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17 +#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18 +#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19 +#define SC_DEBUG_7_new_prim_SHIFT 20 +#define SC_DEBUG_7_load_new_tile_data_SHIFT 21 +#define SC_DEBUG_7_state_SHIFT 22 +#define SC_DEBUG_7_fifos_ready_SHIFT 24 +#define SC_DEBUG_7_trigger_SHIFT 31 + +#define SC_DEBUG_7_event_flag_MASK 0x00000001 +#define SC_DEBUG_7_deallocate_MASK 0x0000000e +#define SC_DEBUG_7_fpos_MASK 0x00000010 +#define SC_DEBUG_7_sr_prim_we_MASK 0x00000020 +#define SC_DEBUG_7_last_tile_MASK 0x00000040 +#define SC_DEBUG_7_tile_ff_we_MASK 0x00000080 +#define SC_DEBUG_7_qs_data_valid_MASK 0x00000100 +#define SC_DEBUG_7_qs_q0_y_MASK 0x00000600 +#define SC_DEBUG_7_qs_q0_x_MASK 0x00001800 +#define SC_DEBUG_7_qs_q0_valid_MASK 0x00002000 +#define SC_DEBUG_7_prim_ff_we_MASK 0x00004000 +#define SC_DEBUG_7_tile_ff_re_MASK 0x00008000 +#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000 +#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000 +#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000 +#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000 +#define SC_DEBUG_7_new_prim_MASK 0x00100000 +#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000 +#define SC_DEBUG_7_state_MASK 0x00c00000 +#define SC_DEBUG_7_fifos_ready_MASK 0x01000000 +#define SC_DEBUG_7_trigger_MASK 0x80000000 + +#define SC_DEBUG_7_MASK \ + (SC_DEBUG_7_event_flag_MASK | \ + SC_DEBUG_7_deallocate_MASK | \ + SC_DEBUG_7_fpos_MASK | \ + SC_DEBUG_7_sr_prim_we_MASK | \ + SC_DEBUG_7_last_tile_MASK | \ + SC_DEBUG_7_tile_ff_we_MASK | \ + SC_DEBUG_7_qs_data_valid_MASK | \ + SC_DEBUG_7_qs_q0_y_MASK | \ + SC_DEBUG_7_qs_q0_x_MASK | \ + SC_DEBUG_7_qs_q0_valid_MASK | \ + SC_DEBUG_7_prim_ff_we_MASK | \ + SC_DEBUG_7_tile_ff_re_MASK | \ + SC_DEBUG_7_fw_prim_data_valid_MASK | \ + SC_DEBUG_7_last_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_prim_MASK | \ + SC_DEBUG_7_new_prim_MASK | \ + SC_DEBUG_7_load_new_tile_data_MASK | \ + SC_DEBUG_7_state_MASK | \ + SC_DEBUG_7_fifos_ready_MASK | \ + SC_DEBUG_7_trigger_MASK) + +#define SC_DEBUG_7(event_flag, deallocate, fpos, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \ + ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \ + (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \ + (fpos << SC_DEBUG_7_fpos_SHIFT) | \ + (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \ + (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \ + (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \ + (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \ + (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \ + (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \ + (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \ + (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \ + (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \ + (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \ + (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \ + (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \ + (state << SC_DEBUG_7_state_SHIFT) | \ + (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \ + (trigger << SC_DEBUG_7_trigger_SHIFT)) + +#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_GET_fpos(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fpos_MASK) >> SC_DEBUG_7_fpos_SHIFT) +#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_GET_state(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_GET_trigger(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT) + +#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_SET_fpos(sc_debug_7_reg, fpos) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fpos_MASK) | (fpos << SC_DEBUG_7_fpos_SHIFT) +#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int fpos : SC_DEBUG_7_fpos_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int : 6; + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + } sc_debug_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + unsigned int : 6; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int fpos : SC_DEBUG_7_fpos_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + } sc_debug_7_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_7_t f; +} sc_debug_7_u; + + +/* + * SC_DEBUG_8 struct + */ + +#define SC_DEBUG_8_sample_last_SIZE 1 +#define SC_DEBUG_8_sample_mask_SIZE 4 +#define SC_DEBUG_8_sample_y_SIZE 2 +#define SC_DEBUG_8_sample_x_SIZE 2 +#define SC_DEBUG_8_sample_send_SIZE 1 +#define SC_DEBUG_8_next_cycle_SIZE 2 +#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1 +#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1 +#define SC_DEBUG_8_num_samples_SIZE 2 +#define SC_DEBUG_8_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_8_last_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_sample_we_SIZE 1 +#define SC_DEBUG_8_fpos_SIZE 1 +#define SC_DEBUG_8_event_id_SIZE 5 +#define SC_DEBUG_8_event_flag_SIZE 1 +#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_8_trigger_SIZE 1 + +#define SC_DEBUG_8_sample_last_SHIFT 0 +#define SC_DEBUG_8_sample_mask_SHIFT 1 +#define SC_DEBUG_8_sample_y_SHIFT 5 +#define SC_DEBUG_8_sample_x_SHIFT 7 +#define SC_DEBUG_8_sample_send_SHIFT 9 +#define SC_DEBUG_8_next_cycle_SHIFT 10 +#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12 +#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13 +#define SC_DEBUG_8_num_samples_SHIFT 14 +#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16 +#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17 +#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18 +#define SC_DEBUG_8_sample_we_SHIFT 19 +#define SC_DEBUG_8_fpos_SHIFT 20 +#define SC_DEBUG_8_event_id_SHIFT 21 +#define SC_DEBUG_8_event_flag_SHIFT 26 +#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27 +#define SC_DEBUG_8_trigger_SHIFT 31 + +#define SC_DEBUG_8_sample_last_MASK 0x00000001 +#define SC_DEBUG_8_sample_mask_MASK 0x0000001e +#define SC_DEBUG_8_sample_y_MASK 0x00000060 +#define SC_DEBUG_8_sample_x_MASK 0x00000180 +#define SC_DEBUG_8_sample_send_MASK 0x00000200 +#define SC_DEBUG_8_next_cycle_MASK 0x00000c00 +#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000 +#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000 +#define SC_DEBUG_8_num_samples_MASK 0x0000c000 +#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000 +#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000 +#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000 +#define SC_DEBUG_8_sample_we_MASK 0x00080000 +#define SC_DEBUG_8_fpos_MASK 0x00100000 +#define SC_DEBUG_8_event_id_MASK 0x03e00000 +#define SC_DEBUG_8_event_flag_MASK 0x04000000 +#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000 +#define SC_DEBUG_8_trigger_MASK 0x80000000 + +#define SC_DEBUG_8_MASK \ + (SC_DEBUG_8_sample_last_MASK | \ + SC_DEBUG_8_sample_mask_MASK | \ + SC_DEBUG_8_sample_y_MASK | \ + SC_DEBUG_8_sample_x_MASK | \ + SC_DEBUG_8_sample_send_MASK | \ + SC_DEBUG_8_next_cycle_MASK | \ + SC_DEBUG_8_ez_sample_ff_full_MASK | \ + SC_DEBUG_8_rb_sc_samp_rtr_MASK | \ + SC_DEBUG_8_num_samples_MASK | \ + SC_DEBUG_8_last_quad_of_tile_MASK | \ + SC_DEBUG_8_last_quad_of_prim_MASK | \ + SC_DEBUG_8_first_quad_of_prim_MASK | \ + SC_DEBUG_8_sample_we_MASK | \ + SC_DEBUG_8_fpos_MASK | \ + SC_DEBUG_8_event_id_MASK | \ + SC_DEBUG_8_event_flag_MASK | \ + SC_DEBUG_8_fw_prim_data_valid_MASK | \ + SC_DEBUG_8_trigger_MASK) + +#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fpos, event_id, event_flag, fw_prim_data_valid, trigger) \ + ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \ + (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \ + (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \ + (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \ + (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \ + (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \ + (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \ + (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \ + (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \ + (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \ + (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \ + (fpos << SC_DEBUG_8_fpos_SHIFT) | \ + (event_id << SC_DEBUG_8_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \ + (trigger << SC_DEBUG_8_trigger_SHIFT)) + +#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_GET_fpos(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fpos_MASK) >> SC_DEBUG_8_fpos_SHIFT) +#define SC_DEBUG_8_GET_event_id(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_GET_trigger(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT) + +#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_SET_fpos(sc_debug_8_reg, fpos) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fpos_MASK) | (fpos << SC_DEBUG_8_fpos_SHIFT) +#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int fpos : SC_DEBUG_8_fpos_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int : 3; + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + } sc_debug_8_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + unsigned int : 3; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int fpos : SC_DEBUG_8_fpos_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + } sc_debug_8_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_8_t f; +} sc_debug_8_u; + + +/* + * SC_DEBUG_9 struct + */ + +#define SC_DEBUG_9_rb_sc_send_SIZE 1 +#define SC_DEBUG_9_rb_sc_ez_mask_SIZE 4 +#define SC_DEBUG_9_fifo_data_ready_SIZE 1 +#define SC_DEBUG_9_early_z_enable_SIZE 1 +#define SC_DEBUG_9_mask_state_SIZE 2 +#define SC_DEBUG_9_next_ez_mask_SIZE 16 +#define SC_DEBUG_9_mask_ready_SIZE 1 +#define SC_DEBUG_9_drop_sample_SIZE 1 +#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_9_trigger_SIZE 1 + +#define SC_DEBUG_9_rb_sc_send_SHIFT 0 +#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1 +#define SC_DEBUG_9_fifo_data_ready_SHIFT 5 +#define SC_DEBUG_9_early_z_enable_SHIFT 6 +#define SC_DEBUG_9_mask_state_SHIFT 7 +#define SC_DEBUG_9_next_ez_mask_SHIFT 9 +#define SC_DEBUG_9_mask_ready_SHIFT 25 +#define SC_DEBUG_9_drop_sample_SHIFT 26 +#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30 +#define SC_DEBUG_9_trigger_SHIFT 31 + +#define SC_DEBUG_9_rb_sc_send_MASK 0x00000001 +#define SC_DEBUG_9_rb_sc_ez_mask_MASK 0x0000001e +#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020 +#define SC_DEBUG_9_early_z_enable_MASK 0x00000040 +#define SC_DEBUG_9_mask_state_MASK 0x00000180 +#define SC_DEBUG_9_next_ez_mask_MASK 0x01fffe00 +#define SC_DEBUG_9_mask_ready_MASK 0x02000000 +#define SC_DEBUG_9_drop_sample_MASK 0x04000000 +#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000 +#define SC_DEBUG_9_trigger_MASK 0x80000000 + +#define SC_DEBUG_9_MASK \ + (SC_DEBUG_9_rb_sc_send_MASK | \ + SC_DEBUG_9_rb_sc_ez_mask_MASK | \ + SC_DEBUG_9_fifo_data_ready_MASK | \ + SC_DEBUG_9_early_z_enable_MASK | \ + SC_DEBUG_9_mask_state_MASK | \ + SC_DEBUG_9_next_ez_mask_MASK | \ + SC_DEBUG_9_mask_ready_MASK | \ + SC_DEBUG_9_drop_sample_MASK | \ + SC_DEBUG_9_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \ + SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_9_trigger_MASK) + +#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \ + ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \ + (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \ + (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \ + (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \ + (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \ + (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \ + (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \ + (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \ + (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \ + (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \ + (trigger << SC_DEBUG_9_trigger_SHIFT)) + +#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_GET_trigger(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT) + +#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + } sc_debug_9_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + } sc_debug_9_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_9_t f; +} sc_debug_9_u; + + +/* + * SC_DEBUG_10 struct + */ + +#define SC_DEBUG_10_combined_sample_mask_SIZE 16 +#define SC_DEBUG_10_trigger_SIZE 1 + +#define SC_DEBUG_10_combined_sample_mask_SHIFT 0 +#define SC_DEBUG_10_trigger_SHIFT 31 + +#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff +#define SC_DEBUG_10_trigger_MASK 0x80000000 + +#define SC_DEBUG_10_MASK \ + (SC_DEBUG_10_combined_sample_mask_MASK | \ + SC_DEBUG_10_trigger_MASK) + +#define SC_DEBUG_10(combined_sample_mask, trigger) \ + ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \ + (trigger << SC_DEBUG_10_trigger_SHIFT)) + +#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_GET_trigger(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT) + +#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + unsigned int : 15; + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + } sc_debug_10_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + unsigned int : 15; + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + } sc_debug_10_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_10_t f; +} sc_debug_10_u; + + +/* + * SC_DEBUG_11 struct + */ + +#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_11_iterator_input_fz_SIZE 1 +#define SC_DEBUG_11_packer_send_quads_SIZE 1 +#define SC_DEBUG_11_packer_send_cmd_SIZE 1 +#define SC_DEBUG_11_packer_send_event_SIZE 1 +#define SC_DEBUG_11_next_state_SIZE 3 +#define SC_DEBUG_11_state_SIZE 3 +#define SC_DEBUG_11_stall_SIZE 1 +#define SC_DEBUG_11_trigger_SIZE 1 + +#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1 +#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3 +#define SC_DEBUG_11_iterator_input_fz_SHIFT 4 +#define SC_DEBUG_11_packer_send_quads_SHIFT 5 +#define SC_DEBUG_11_packer_send_cmd_SHIFT 6 +#define SC_DEBUG_11_packer_send_event_SHIFT 7 +#define SC_DEBUG_11_next_state_SHIFT 8 +#define SC_DEBUG_11_state_SHIFT 11 +#define SC_DEBUG_11_stall_SHIFT 14 +#define SC_DEBUG_11_trigger_SHIFT 31 + +#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002 +#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008 +#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010 +#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020 +#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040 +#define SC_DEBUG_11_packer_send_event_MASK 0x00000080 +#define SC_DEBUG_11_next_state_MASK 0x00000700 +#define SC_DEBUG_11_state_MASK 0x00003800 +#define SC_DEBUG_11_stall_MASK 0x00004000 +#define SC_DEBUG_11_trigger_MASK 0x80000000 + +#define SC_DEBUG_11_MASK \ + (SC_DEBUG_11_ez_sample_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_11_ez_prim_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_11_iterator_input_fz_MASK | \ + SC_DEBUG_11_packer_send_quads_MASK | \ + SC_DEBUG_11_packer_send_cmd_MASK | \ + SC_DEBUG_11_packer_send_event_MASK | \ + SC_DEBUG_11_next_state_MASK | \ + SC_DEBUG_11_state_MASK | \ + SC_DEBUG_11_stall_MASK | \ + SC_DEBUG_11_trigger_MASK) + +#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \ + ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \ + (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \ + (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \ + (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \ + (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \ + (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \ + (next_state << SC_DEBUG_11_next_state_SHIFT) | \ + (state << SC_DEBUG_11_state_SHIFT) | \ + (stall << SC_DEBUG_11_stall_SHIFT) | \ + (trigger << SC_DEBUG_11_trigger_SHIFT)) + +#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_GET_next_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_GET_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_GET_stall(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_GET_trigger(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT) + +#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int : 16; + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + } sc_debug_11_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + unsigned int : 16; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + } sc_debug_11_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_11_t f; +} sc_debug_11_u; + + +/* + * SC_DEBUG_12 struct + */ + +#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1 +#define SC_DEBUG_12_event_id_SIZE 5 +#define SC_DEBUG_12_event_flag_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_full_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1 +#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1 +#define SC_DEBUG_12_iter_qdhit0_SIZE 1 +#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1 +#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1 +#define SC_DEBUG_12_iter_phase_out_SIZE 2 +#define SC_DEBUG_12_iter_phase_reg_SIZE 2 +#define SC_DEBUG_12_iterator_SP_valid_SIZE 1 +#define SC_DEBUG_12_eopv_reg_SIZE 1 +#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1 +#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1 +#define SC_DEBUG_12_trigger_SIZE 1 + +#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0 +#define SC_DEBUG_12_event_id_SHIFT 1 +#define SC_DEBUG_12_event_flag_SHIFT 6 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7 +#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8 +#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9 +#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11 +#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12 +#define SC_DEBUG_12_iter_qdhit0_SHIFT 13 +#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14 +#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15 +#define SC_DEBUG_12_iter_phase_out_SHIFT 16 +#define SC_DEBUG_12_iter_phase_reg_SHIFT 18 +#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20 +#define SC_DEBUG_12_eopv_reg_SHIFT 21 +#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22 +#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23 +#define SC_DEBUG_12_trigger_SHIFT 31 + +#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001 +#define SC_DEBUG_12_event_id_MASK 0x0000003e +#define SC_DEBUG_12_event_flag_MASK 0x00000040 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080 +#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100 +#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200 +#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400 +#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800 +#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000 +#define SC_DEBUG_12_iter_qdhit0_MASK 0x00002000 +#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000 +#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000 +#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000 +#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000 +#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000 +#define SC_DEBUG_12_eopv_reg_MASK 0x00200000 +#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000 +#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000 +#define SC_DEBUG_12_trigger_MASK 0x80000000 + +#define SC_DEBUG_12_MASK \ + (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \ + SC_DEBUG_12_event_id_MASK | \ + SC_DEBUG_12_event_flag_MASK | \ + SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \ + SC_DEBUG_12_itercmdfifo_full_MASK | \ + SC_DEBUG_12_itercmdfifo_empty_MASK | \ + SC_DEBUG_12_iter_ds_one_clk_command_MASK | \ + SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \ + SC_DEBUG_12_iter_ds_end_of_vector_MASK | \ + SC_DEBUG_12_iter_qdhit0_MASK | \ + SC_DEBUG_12_bc_use_centers_reg_MASK | \ + SC_DEBUG_12_bc_output_xy_reg_MASK | \ + SC_DEBUG_12_iter_phase_out_MASK | \ + SC_DEBUG_12_iter_phase_reg_MASK | \ + SC_DEBUG_12_iterator_SP_valid_MASK | \ + SC_DEBUG_12_eopv_reg_MASK | \ + SC_DEBUG_12_one_clk_cmd_reg_MASK | \ + SC_DEBUG_12_iter_dx_end_of_prim_MASK | \ + SC_DEBUG_12_trigger_MASK) + +#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \ + ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \ + (event_id << SC_DEBUG_12_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \ + (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \ + (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \ + (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \ + (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \ + (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \ + (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \ + (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \ + (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \ + (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \ + (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \ + (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \ + (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \ + (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \ + (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \ + (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \ + (trigger << SC_DEBUG_12_trigger_SHIFT)) + +#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_GET_event_id(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_GET_trigger(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT) + +#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int : 7; + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + } sc_debug_12_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + } sc_debug_12_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_12_t f; +} sc_debug_12_u; + + +#endif + + +#if !defined (_VGT_FIDDLE_H) +#define _VGT_FIDDLE_H + +/***************************************************************************************************************** + * + * vgt_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + +/* + * VGT_OUT_PRIM_TYPE enum + */ + +#define VGT_OUT_POINT 0x00000000 +#define VGT_OUT_LINE 0x00000001 +#define VGT_OUT_TRI 0x00000002 +#define VGT_OUT_RECT_V0 0x00000003 +#define VGT_OUT_RECT_V1 0x00000004 +#define VGT_OUT_RECT_V2 0x00000005 +#define VGT_OUT_RECT_V3 0x00000006 +#define VGT_OUT_RESERVED 0x00000007 +#define VGT_TE_QUAD 0x00000008 +#define VGT_TE_PRIM_INDEX_LINE 0x00000009 +#define VGT_TE_PRIM_INDEX_TRI 0x0000000a +#define VGT_TE_PRIM_INDEX_QUAD 0x0000000b + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * GFX_COPY_STATE struct + */ + +#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1 + +#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0 + +#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 + +#define GFX_COPY_STATE_MASK \ + (GFX_COPY_STATE_SRC_STATE_ID_MASK) + +#define GFX_COPY_STATE(src_state_id) \ + ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)) + +#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \ + ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \ + gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 31; + } gfx_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int : 31; + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + } gfx_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + gfx_copy_state_t f; +} gfx_copy_state_u; + + +/* + * VGT_DRAW_INITIATOR struct + */ + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1 +#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11 +#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800 +#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000 +#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000 + +#define VGT_DRAW_INITIATOR_MASK \ + (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \ + VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \ + VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \ + VGT_DRAW_INITIATOR_NOT_EOP_MASK | \ + VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \ + VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_NUM_INDICES_MASK) + +#define VGT_DRAW_INITIATOR(prim_type, source_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \ + ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \ + (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \ + (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \ + (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \ + (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \ + (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \ + (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \ + (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)) + +#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int : 3; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + } vgt_draw_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int : 3; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + } vgt_draw_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_draw_initiator_t f; +} vgt_draw_initiator_u; + + +/* + * VGT_EVENT_INITIATOR struct + */ + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f + +#define VGT_EVENT_INITIATOR_MASK \ + (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) + +#define VGT_EVENT_INITIATOR(event_type) \ + ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)) + +#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \ + ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \ + vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + unsigned int : 26; + } vgt_event_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int : 26; + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + } vgt_event_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_event_initiator_t f; +} vgt_event_initiator_u; + + +/* + * VGT_DMA_BASE struct + */ + +#define VGT_DMA_BASE_BASE_ADDR_SIZE 32 + +#define VGT_DMA_BASE_BASE_ADDR_SHIFT 0 + +#define VGT_DMA_BASE_BASE_ADDR_MASK 0xffffffff + +#define VGT_DMA_BASE_MASK \ + (VGT_DMA_BASE_BASE_ADDR_MASK) + +#define VGT_DMA_BASE(base_addr) \ + ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)) + +#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \ + ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \ + vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_base_t f; +} vgt_dma_base_u; + + +/* + * VGT_DMA_SIZE struct + */ + +#define VGT_DMA_SIZE_NUM_WORDS_SIZE 24 +#define VGT_DMA_SIZE_SWAP_MODE_SIZE 2 + +#define VGT_DMA_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_DMA_SIZE_SWAP_MODE_SHIFT 30 + +#define VGT_DMA_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_DMA_SIZE_SWAP_MODE_MASK 0xc0000000 + +#define VGT_DMA_SIZE_MASK \ + (VGT_DMA_SIZE_NUM_WORDS_MASK | \ + VGT_DMA_SIZE_SWAP_MODE_MASK) + +#define VGT_DMA_SIZE(num_words, swap_mode) \ + ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \ + (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)) + +#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + } vgt_dma_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + } vgt_dma_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_size_t f; +} vgt_dma_size_u; + + +/* + * VGT_BIN_BASE struct + */ + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff + +#define VGT_BIN_BASE_MASK \ + (VGT_BIN_BASE_BIN_BASE_ADDR_MASK) + +#define VGT_BIN_BASE(bin_base_addr) \ + ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)) + +#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \ + ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \ + vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_base_t f; +} vgt_bin_base_u; + + +/* + * VGT_BIN_SIZE struct + */ + +#define VGT_BIN_SIZE_NUM_WORDS_SIZE 24 + +#define VGT_BIN_SIZE_NUM_WORDS_SHIFT 0 + +#define VGT_BIN_SIZE_NUM_WORDS_MASK 0x00ffffff + +#define VGT_BIN_SIZE_MASK \ + (VGT_BIN_SIZE_NUM_WORDS_MASK) + +#define VGT_BIN_SIZE(num_words) \ + ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)) + +#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT) + +#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + unsigned int : 8; + } vgt_bin_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int : 8; + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + } vgt_bin_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_size_t f; +} vgt_bin_size_u; + + +/* + * VGT_CURRENT_BIN_ID_MIN struct + */ + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MIN_MASK \ + (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_min_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + } vgt_current_bin_id_min_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_min_t f; +} vgt_current_bin_id_min_u; + + +/* + * VGT_CURRENT_BIN_ID_MAX struct + */ + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MAX_MASK \ + (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_max_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + } vgt_current_bin_id_max_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_max_t f; +} vgt_current_bin_id_max_u; + + +/* + * VGT_IMMED_DATA struct + */ + +#define VGT_IMMED_DATA_DATA_SIZE 32 + +#define VGT_IMMED_DATA_DATA_SHIFT 0 + +#define VGT_IMMED_DATA_DATA_MASK 0xffffffff + +#define VGT_IMMED_DATA_MASK \ + (VGT_IMMED_DATA_DATA_MASK) + +#define VGT_IMMED_DATA(data) \ + ((data << VGT_IMMED_DATA_DATA_SHIFT)) + +#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \ + ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT) + +#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \ + vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_immed_data_t f; +} vgt_immed_data_u; + + +/* + * VGT_MAX_VTX_INDX struct + */ + +#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24 + +#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0 + +#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff + +#define VGT_MAX_VTX_INDX_MASK \ + (VGT_MAX_VTX_INDX_MAX_INDX_MASK) + +#define VGT_MAX_VTX_INDX(max_indx) \ + ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)) + +#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \ + ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \ + vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + unsigned int : 8; + } vgt_max_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int : 8; + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + } vgt_max_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_max_vtx_indx_t f; +} vgt_max_vtx_indx_u; + + +/* + * VGT_MIN_VTX_INDX struct + */ + +#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24 + +#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0 + +#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff + +#define VGT_MIN_VTX_INDX_MASK \ + (VGT_MIN_VTX_INDX_MIN_INDX_MASK) + +#define VGT_MIN_VTX_INDX(min_indx) \ + ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)) + +#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \ + ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \ + vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + unsigned int : 8; + } vgt_min_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int : 8; + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + } vgt_min_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_min_vtx_indx_t f; +} vgt_min_vtx_indx_u; + + +/* + * VGT_INDX_OFFSET struct + */ + +#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24 + +#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0 + +#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff + +#define VGT_INDX_OFFSET_MASK \ + (VGT_INDX_OFFSET_INDX_OFFSET_MASK) + +#define VGT_INDX_OFFSET(indx_offset) \ + ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)) + +#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \ + ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \ + vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + unsigned int : 8; + } vgt_indx_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int : 8; + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + } vgt_indx_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_indx_offset_t f; +} vgt_indx_offset_u; + + +/* + * VGT_VERTEX_REUSE_BLOCK_CNTL struct + */ + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \ + (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \ + ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \ + ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \ + vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + unsigned int : 29; + } vgt_vertex_reuse_block_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int : 29; + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + } vgt_vertex_reuse_block_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vertex_reuse_block_cntl_t f; +} vgt_vertex_reuse_block_cntl_u; + + +/* + * VGT_OUT_DEALLOC_CNTL struct + */ + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003 + +#define VGT_OUT_DEALLOC_CNTL_MASK \ + (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) + +#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \ + ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)) + +#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \ + ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \ + vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + unsigned int : 30; + } vgt_out_dealloc_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int : 30; + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + } vgt_out_dealloc_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_out_dealloc_cntl_t f; +} vgt_out_dealloc_cntl_u; + + +/* + * VGT_MULTI_PRIM_IB_RESET_INDX struct + */ + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff + +#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \ + (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) + +#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \ + ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \ + ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \ + vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + unsigned int : 8; + } vgt_multi_prim_ib_reset_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int : 8; + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + } vgt_multi_prim_ib_reset_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_multi_prim_ib_reset_indx_t f; +} vgt_multi_prim_ib_reset_indx_u; + + +/* + * VGT_ENHANCE struct + */ + +#define VGT_ENHANCE_MISC_SIZE 16 + +#define VGT_ENHANCE_MISC_SHIFT 0 + +#define VGT_ENHANCE_MISC_MASK 0x0000ffff + +#define VGT_ENHANCE_MASK \ + (VGT_ENHANCE_MISC_MASK) + +#define VGT_ENHANCE(misc) \ + ((misc << VGT_ENHANCE_MISC_SHIFT)) + +#define VGT_ENHANCE_GET_MISC(vgt_enhance) \ + ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT) + +#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \ + vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + unsigned int : 16; + } vgt_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int : 16; + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + } vgt_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_enhance_t f; +} vgt_enhance_u; + + +/* + * VGT_VTX_VECT_EJECT_REG struct + */ + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f + +#define VGT_VTX_VECT_EJECT_REG_MASK \ + (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) + +#define VGT_VTX_VECT_EJECT_REG(prim_count) \ + ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)) + +#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \ + ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \ + vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + unsigned int : 27; + } vgt_vtx_vect_eject_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int : 27; + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + } vgt_vtx_vect_eject_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vtx_vect_eject_reg_t f; +} vgt_vtx_vect_eject_reg_u; + + +/* + * VGT_LAST_COPY_STATE struct + */ + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000 + +#define VGT_LAST_COPY_STATE_MASK \ + (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \ + VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) + +#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \ + ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \ + (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)) + +#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + } vgt_last_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + } vgt_last_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_last_copy_state_t f; +} vgt_last_copy_state_u; + + +/* + * VGT_DEBUG_CNTL struct + */ + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f + +#define VGT_DEBUG_CNTL_MASK \ + (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) + +#define VGT_DEBUG_CNTL(vgt_debug_indx) \ + ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)) + +#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \ + ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \ + vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + unsigned int : 27; + } vgt_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int : 27; + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + } vgt_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_cntl_t f; +} vgt_debug_cntl_u; + + +/* + * VGT_DEBUG_DATA struct + */ + +#define VGT_DEBUG_DATA_DATA_SIZE 32 + +#define VGT_DEBUG_DATA_DATA_SHIFT 0 + +#define VGT_DEBUG_DATA_DATA_MASK 0xffffffff + +#define VGT_DEBUG_DATA_MASK \ + (VGT_DEBUG_DATA_DATA_MASK) + +#define VGT_DEBUG_DATA(data) \ + ((data << VGT_DEBUG_DATA_DATA_SHIFT)) + +#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \ + ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT) + +#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \ + vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_data_t f; +} vgt_debug_data_u; + + +/* + * VGT_CNTL_STATUS struct + */ + +#define VGT_CNTL_STATUS_VGT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1 + +#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8 + +#define VGT_CNTL_STATUS_VGT_BUSY_MASK 0x00000001 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100 + +#define VGT_CNTL_STATUS_MASK \ + (VGT_CNTL_STATUS_VGT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) + +#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \ + ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \ + (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \ + (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \ + (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \ + (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \ + (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \ + (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \ + (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \ + (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)) + +#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int : 23; + } vgt_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int : 23; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + } vgt_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_cntl_status_t f; +} vgt_cntl_status_u; + + +/* + * VGT_DEBUG_REG0 struct + */ + +#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_out_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1 + +#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0 +#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2 +#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3 +#define VGT_DEBUG_REG0_out_busy_SHIFT 4 +#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5 +#define VGT_DEBUG_REG0_grp_busy_SHIFT 6 +#define VGT_DEBUG_REG0_dma_busy_SHIFT 7 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8 +#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11 +#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12 +#define VGT_DEBUG_REG0_vgt_busy_SHIFT 13 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16 + +#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001 +#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002 +#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004 +#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008 +#define VGT_DEBUG_REG0_out_busy_MASK 0x00000010 +#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020 +#define VGT_DEBUG_REG0_grp_busy_MASK 0x00000040 +#define VGT_DEBUG_REG0_dma_busy_MASK 0x00000080 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100 +#define VGT_DEBUG_REG0_rbiu_busy_MASK 0x00000200 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800 +#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000 +#define VGT_DEBUG_REG0_vgt_busy_MASK 0x00002000 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000 + +#define VGT_DEBUG_REG0_MASK \ + (VGT_DEBUG_REG0_te_grp_busy_MASK | \ + VGT_DEBUG_REG0_pt_grp_busy_MASK | \ + VGT_DEBUG_REG0_vr_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_out_busy_MASK | \ + VGT_DEBUG_REG0_grp_backend_busy_MASK | \ + VGT_DEBUG_REG0_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_busy_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_vgt_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_busy_MASK | \ + VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) + +#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \ + ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \ + (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \ + (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \ + (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \ + (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \ + (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \ + (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \ + (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \ + (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \ + (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \ + (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \ + (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \ + (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \ + (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \ + (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \ + (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \ + (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)) + +#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int : 15; + } vgt_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int : 15; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + } vgt_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg0_t f; +} vgt_debug_reg0_u; + + +/* + * VGT_DEBUG_REG1 struct + */ + +#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1 +#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_te_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1 +#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1 +#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1 +#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1 + +#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0 +#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3 +#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5 +#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7 +#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9 +#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10 +#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11 +#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12 +#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13 +#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14 +#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15 +#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16 +#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20 +#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28 +#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30 + +#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001 +#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002 +#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004 +#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008 +#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010 +#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020 +#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040 +#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080 +#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100 +#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200 +#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400 +#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800 +#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000 +#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000 +#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000 +#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000 +#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000 +#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000 +#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000 +#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000 + +#define VGT_DEBUG_REG1_MASK \ + (VGT_DEBUG_REG1_out_te_data_read_MASK | \ + VGT_DEBUG_REG1_te_out_data_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_prim_read_MASK | \ + VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_data_read_MASK | \ + VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_prim_read_MASK | \ + VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_indx_read_MASK | \ + VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_te_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_te_valid_MASK | \ + VGT_DEBUG_REG1_pt_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_pt_valid_MASK | \ + VGT_DEBUG_REG1_vr_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_vr_valid_MASK | \ + VGT_DEBUG_REG1_grp_dma_read_MASK | \ + VGT_DEBUG_REG1_dma_grp_valid_MASK | \ + VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \ + VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \ + VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_MH_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \ + VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_SQ_send_MASK | \ + VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) + +#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \ + ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \ + (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \ + (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \ + (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \ + (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \ + (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \ + (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \ + (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \ + (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \ + (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \ + (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \ + (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \ + (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \ + (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \ + (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \ + (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \ + (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \ + (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \ + (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \ + (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \ + (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \ + (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \ + (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \ + (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \ + (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \ + (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \ + (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \ + (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \ + (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \ + (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \ + (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)) + +#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int : 1; + } vgt_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + } vgt_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg1_t f; +} vgt_debug_reg1_u; + + +/* + * VGT_DEBUG_REG3 struct + */ + +#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002 + +#define VGT_DEBUG_REG3_MASK \ + (VGT_DEBUG_REG3_vgt_clk_en_MASK | \ + VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) + +#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \ + ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \ + (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)) + +#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int : 30; + } vgt_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int : 30; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + } vgt_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg3_t f; +} vgt_debug_reg3_u; + + +/* + * VGT_DEBUG_REG6 struct + */ + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG6_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_extract_vector_SIZE 1 +#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG6_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG6_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG6_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG6_MASK \ + (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG6_right_word_indx_q_MASK | \ + VGT_DEBUG_REG6_input_data_valid_MASK | \ + VGT_DEBUG_REG6_input_data_xfer_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG6_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG6_shifter_first_load_MASK | \ + VGT_DEBUG_REG6_di_state_sel_q_MASK | \ + VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG6_di_event_flag_q_MASK | \ + VGT_DEBUG_REG6_read_draw_initiator_MASK | \ + VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG6_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG6_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG6_extract_vector_MASK | \ + VGT_DEBUG_REG6_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG6_destination_rtr_MASK | \ + VGT_DEBUG_REG6_grp_trigger_MASK) + +#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int : 3; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + } vgt_debug_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg6_t f; +} vgt_debug_reg6_u; + + +/* + * VGT_DEBUG_REG7 struct + */ + +#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG7_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG7_MASK \ + (VGT_DEBUG_REG7_di_index_counter_q_MASK | \ + VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG7_shift_amount_extract_MASK | \ + VGT_DEBUG_REG7_di_prim_type_q_MASK | \ + VGT_DEBUG_REG7_current_source_sel_MASK) + +#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + } vgt_debug_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + } vgt_debug_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg7_t f; +} vgt_debug_reg7_u; + + +/* + * VGT_DEBUG_REG8 struct + */ + +#define VGT_DEBUG_REG8_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG8_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG8_MASK \ + (VGT_DEBUG_REG8_current_source_sel_MASK | \ + VGT_DEBUG_REG8_left_word_indx_q_MASK | \ + VGT_DEBUG_REG8_input_data_cnt_MASK | \ + VGT_DEBUG_REG8_input_data_lsw_MASK | \ + VGT_DEBUG_REG8_input_data_msw_MASK | \ + VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg8_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + } vgt_debug_reg8_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg8_t f; +} vgt_debug_reg8_u; + + +/* + * VGT_DEBUG_REG9 struct + */ + +#define VGT_DEBUG_REG9_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG9_MASK \ + (VGT_DEBUG_REG9_next_stride_q_MASK | \ + VGT_DEBUG_REG9_next_stride_d_MASK | \ + VGT_DEBUG_REG9_current_shift_q_MASK | \ + VGT_DEBUG_REG9_current_shift_d_MASK | \ + VGT_DEBUG_REG9_current_stride_q_MASK | \ + VGT_DEBUG_REG9_current_stride_d_MASK | \ + VGT_DEBUG_REG9_grp_trigger_MASK) + +#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg9_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int : 1; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + } vgt_debug_reg9_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg9_t f; +} vgt_debug_reg9_u; + + +/* + * VGT_DEBUG_REG10 struct + */ + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG10_bin_valid_SIZE 1 +#define VGT_DEBUG_REG10_read_block_SIZE 1 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1 +#define VGT_DEBUG_REG10_selected_data_SIZE 8 +#define VGT_DEBUG_REG10_mask_input_data_SIZE 8 +#define VGT_DEBUG_REG10_gap_q_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1 +#define VGT_DEBUG_REG10_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3 +#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4 +#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5 +#define VGT_DEBUG_REG10_bin_valid_SHIFT 6 +#define VGT_DEBUG_REG10_read_block_SHIFT 7 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8 +#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10 +#define VGT_DEBUG_REG10_selected_data_SHIFT 11 +#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19 +#define VGT_DEBUG_REG10_gap_q_SHIFT 27 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30 +#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008 +#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010 +#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020 +#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040 +#define VGT_DEBUG_REG10_read_block_MASK 0x00000080 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100 +#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200 +#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400 +#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800 +#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000 +#define VGT_DEBUG_REG10_gap_q_MASK 0x08000000 +#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000 +#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000 +#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000 +#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG10_MASK \ + (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_di_state_sel_q_MASK | \ + VGT_DEBUG_REG10_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG10_bin_valid_MASK | \ + VGT_DEBUG_REG10_read_block_MASK | \ + VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \ + VGT_DEBUG_REG10_last_bit_enable_q_MASK | \ + VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \ + VGT_DEBUG_REG10_selected_data_MASK | \ + VGT_DEBUG_REG10_mask_input_data_MASK | \ + VGT_DEBUG_REG10_gap_q_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \ + VGT_DEBUG_REG10_grp_trigger_MASK) + +#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \ + ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \ + (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \ + (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \ + (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \ + (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \ + (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \ + (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \ + (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \ + (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \ + (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \ + (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \ + (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \ + (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \ + (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \ + (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + } vgt_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + } vgt_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg10_t f; +} vgt_debug_reg10_u; + + +/* + * VGT_DEBUG_REG12 struct + */ + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG12_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_extract_vector_SIZE 1 +#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG12_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG12_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG12_MASK \ + (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG12_right_word_indx_q_MASK | \ + VGT_DEBUG_REG12_input_data_valid_MASK | \ + VGT_DEBUG_REG12_input_data_xfer_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG12_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG12_shifter_first_load_MASK | \ + VGT_DEBUG_REG12_di_state_sel_q_MASK | \ + VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG12_di_event_flag_q_MASK | \ + VGT_DEBUG_REG12_read_draw_initiator_MASK | \ + VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG12_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG12_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG12_extract_vector_MASK | \ + VGT_DEBUG_REG12_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG12_destination_rtr_MASK | \ + VGT_DEBUG_REG12_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int : 3; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + } vgt_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg12_t f; +} vgt_debug_reg12_u; + + +/* + * VGT_DEBUG_REG13 struct + */ + +#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG13_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG13_MASK \ + (VGT_DEBUG_REG13_di_index_counter_q_MASK | \ + VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG13_shift_amount_extract_MASK | \ + VGT_DEBUG_REG13_di_prim_type_q_MASK | \ + VGT_DEBUG_REG13_current_source_sel_MASK) + +#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + } vgt_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + } vgt_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg13_t f; +} vgt_debug_reg13_u; + + +/* + * VGT_DEBUG_REG14 struct + */ + +#define VGT_DEBUG_REG14_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG14_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG14_MASK \ + (VGT_DEBUG_REG14_current_source_sel_MASK | \ + VGT_DEBUG_REG14_left_word_indx_q_MASK | \ + VGT_DEBUG_REG14_input_data_cnt_MASK | \ + VGT_DEBUG_REG14_input_data_lsw_MASK | \ + VGT_DEBUG_REG14_input_data_msw_MASK | \ + VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + } vgt_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg14_t f; +} vgt_debug_reg14_u; + + +/* + * VGT_DEBUG_REG15 struct + */ + +#define VGT_DEBUG_REG15_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG15_MASK \ + (VGT_DEBUG_REG15_next_stride_q_MASK | \ + VGT_DEBUG_REG15_next_stride_d_MASK | \ + VGT_DEBUG_REG15_current_shift_q_MASK | \ + VGT_DEBUG_REG15_current_shift_d_MASK | \ + VGT_DEBUG_REG15_current_stride_q_MASK | \ + VGT_DEBUG_REG15_current_stride_d_MASK | \ + VGT_DEBUG_REG15_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int : 1; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + } vgt_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg15_t f; +} vgt_debug_reg15_u; + + +/* + * VGT_DEBUG_REG16 struct + */ + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1 +#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1 +#define VGT_DEBUG_REG16_current_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_en_SIZE 1 +#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1 +#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9 +#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10 +#define VGT_DEBUG_REG16_current_state_q_SHIFT 11 +#define VGT_DEBUG_REG16_old_state_q_SHIFT 12 +#define VGT_DEBUG_REG16_old_state_en_SHIFT 13 +#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15 +#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17 +#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30 +#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200 +#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400 +#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800 +#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000 +#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000 +#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000 +#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000 +#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000 +#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000 +#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000 +#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG16_MASK \ + (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \ + VGT_DEBUG_REG16_rst_last_bit_MASK | \ + VGT_DEBUG_REG16_current_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_en_MASK | \ + VGT_DEBUG_REG16_prev_last_bit_q_MASK | \ + VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \ + VGT_DEBUG_REG16_last_bit_block_q_MASK | \ + VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \ + VGT_DEBUG_REG16_load_empty_reg_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \ + VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \ + VGT_DEBUG_REG16_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \ + ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \ + (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \ + (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \ + (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \ + (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \ + (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \ + (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \ + (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \ + (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \ + (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \ + (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \ + (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \ + (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \ + (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \ + (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \ + (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \ + (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \ + (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \ + (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \ + (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \ + (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + } vgt_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + } vgt_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg16_t f; +} vgt_debug_reg16_u; + + +/* + * VGT_DEBUG_REG17 struct + */ + +#define VGT_DEBUG_REG17_save_read_q_SIZE 1 +#define VGT_DEBUG_REG17_extend_read_q_SIZE 1 +#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2 +#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1 +#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1 +#define VGT_DEBUG_REG17_check_second_reg_SIZE 1 +#define VGT_DEBUG_REG17_check_first_reg_SIZE 1 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1 +#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG17_save_read_q_SHIFT 0 +#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1 +#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2 +#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4 +#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5 +#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6 +#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7 +#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8 +#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14 +#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15 +#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24 +#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001 +#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002 +#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c +#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010 +#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020 +#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040 +#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080 +#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100 +#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000 +#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000 +#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000 +#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000 +#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000 +#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG17_MASK \ + (VGT_DEBUG_REG17_save_read_q_MASK | \ + VGT_DEBUG_REG17_extend_read_q_MASK | \ + VGT_DEBUG_REG17_grp_indx_size_MASK | \ + VGT_DEBUG_REG17_cull_prim_true_MASK | \ + VGT_DEBUG_REG17_reset_bit2_q_MASK | \ + VGT_DEBUG_REG17_reset_bit1_q_MASK | \ + VGT_DEBUG_REG17_first_reg_first_q_MASK | \ + VGT_DEBUG_REG17_check_second_reg_MASK | \ + VGT_DEBUG_REG17_check_first_reg_MASK | \ + VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \ + VGT_DEBUG_REG17_to_second_reg_q_MASK | \ + VGT_DEBUG_REG17_roll_over_msk_q_MASK | \ + VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \ + ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \ + (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \ + (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \ + (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \ + (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \ + (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \ + (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \ + (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \ + (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \ + (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \ + (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \ + (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \ + (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \ + (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \ + (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \ + (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \ + (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \ + (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + } vgt_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + } vgt_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg17_t f; +} vgt_debug_reg17_u; + + +/* + * VGT_DEBUG_REG18 struct + */ + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_start_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1 +#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13 +#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15 +#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16 +#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17 +#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20 +#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21 +#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22 +#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23 +#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24 +#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26 +#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27 +#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28 +#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000 +#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000 +#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000 +#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000 +#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000 +#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000 +#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000 +#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000 +#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000 +#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000 +#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000 +#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000 +#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000 +#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000 + +#define VGT_DEBUG_REG18_MASK \ + (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG18_dma_mem_full_MASK | \ + VGT_DEBUG_REG18_dma_ram_re_MASK | \ + VGT_DEBUG_REG18_dma_ram_we_MASK | \ + VGT_DEBUG_REG18_dma_mem_empty_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \ + VGT_DEBUG_REG18_bin_mem_full_MASK | \ + VGT_DEBUG_REG18_bin_ram_we_MASK | \ + VGT_DEBUG_REG18_bin_ram_re_MASK | \ + VGT_DEBUG_REG18_bin_mem_empty_MASK | \ + VGT_DEBUG_REG18_start_bin_req_MASK | \ + VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \ + VGT_DEBUG_REG18_dma_req_xfer_MASK | \ + VGT_DEBUG_REG18_have_valid_bin_req_MASK | \ + VGT_DEBUG_REG18_have_valid_dma_req_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) + +#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \ + ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \ + (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \ + (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \ + (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \ + (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \ + (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \ + (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \ + (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \ + (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \ + (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \ + (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \ + (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \ + (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \ + (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \ + (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \ + (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \ + (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \ + (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \ + (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)) + +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + } vgt_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + } vgt_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg18_t f; +} vgt_debug_reg18_u; + + +/* + * VGT_DEBUG_REG20 struct + */ + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_sent_cnt_SIZE 4 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5 +#define VGT_DEBUG_REG20_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5 +#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6 +#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7 +#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8 +#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9 +#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10 +#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11 +#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12 +#define VGT_DEBUG_REG20_hold_prim_SHIFT 13 +#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21 +#define VGT_DEBUG_REG20_out_trigger_SHIFT 26 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004 +#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020 +#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040 +#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080 +#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100 +#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200 +#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400 +#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800 +#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000 +#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000 +#define VGT_DEBUG_REG20_sent_cnt_MASK 0x0003c000 +#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000 +#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000 +#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000 + +#define VGT_DEBUG_REG20_MASK \ + (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \ + VGT_DEBUG_REG20_prim_buffer_empty_MASK | \ + VGT_DEBUG_REG20_prim_buffer_re_MASK | \ + VGT_DEBUG_REG20_prim_buffer_we_MASK | \ + VGT_DEBUG_REG20_prim_buffer_full_MASK | \ + VGT_DEBUG_REG20_indx_buffer_empty_MASK | \ + VGT_DEBUG_REG20_indx_buffer_re_MASK | \ + VGT_DEBUG_REG20_indx_buffer_we_MASK | \ + VGT_DEBUG_REG20_indx_buffer_full_MASK | \ + VGT_DEBUG_REG20_hold_prim_MASK | \ + VGT_DEBUG_REG20_sent_cnt_MASK | \ + VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \ + VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \ + VGT_DEBUG_REG20_out_trigger_MASK) + +#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \ + ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \ + (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \ + (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \ + (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \ + (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \ + (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \ + (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \ + (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \ + (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \ + (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \ + (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \ + (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \ + (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \ + (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \ + (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \ + (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \ + (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \ + (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \ + (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT) + +#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int : 5; + } vgt_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int : 5; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + } vgt_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg20_t f; +} vgt_debug_reg20_u; + + +/* + * VGT_DEBUG_REG21 struct + */ + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3 +#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4 +#define VGT_DEBUG_REG21_new_packet_q_SIZE 1 +#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1 +#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1 +#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1 +#define VGT_DEBUG_REG21_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1 +#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14 +#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18 +#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22 +#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25 +#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26 +#define VGT_DEBUG_REG21_out_trigger_SHIFT 31 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e +#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380 +#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000 +#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000 +#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000 +#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000 +#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000 +#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000 +#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG21_MASK \ + (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \ + VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \ + VGT_DEBUG_REG21_alloc_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \ + VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \ + VGT_DEBUG_REG21_new_packet_q_MASK | \ + VGT_DEBUG_REG21_new_allocate_q_MASK | \ + VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \ + VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \ + VGT_DEBUG_REG21_insert_null_prim_MASK | \ + VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \ + VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \ + VGT_DEBUG_REG21_buffered_thread_size_MASK | \ + VGT_DEBUG_REG21_out_trigger_MASK) + +#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \ + ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \ + (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \ + (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \ + (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \ + (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \ + (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \ + (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \ + (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \ + (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \ + (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \ + (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \ + (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \ + (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \ + (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT) + +#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int : 4; + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + } vgt_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + unsigned int : 4; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + } vgt_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg21_t f; +} vgt_debug_reg21_u; + + +/* + * VGT_CRC_SQ_DATA struct + */ + +#define VGT_CRC_SQ_DATA_CRC_SIZE 32 + +#define VGT_CRC_SQ_DATA_CRC_SHIFT 0 + +#define VGT_CRC_SQ_DATA_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_DATA_MASK \ + (VGT_CRC_SQ_DATA_CRC_MASK) + +#define VGT_CRC_SQ_DATA(crc) \ + ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT)) + +#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \ + ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT) + +#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \ + vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_data_t f; +} vgt_crc_sq_data_u; + + +/* + * VGT_CRC_SQ_CTRL struct + */ + +#define VGT_CRC_SQ_CTRL_CRC_SIZE 32 + +#define VGT_CRC_SQ_CTRL_CRC_SHIFT 0 + +#define VGT_CRC_SQ_CTRL_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_CTRL_MASK \ + (VGT_CRC_SQ_CTRL_CRC_MASK) + +#define VGT_CRC_SQ_CTRL(crc) \ + ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)) + +#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \ + ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \ + vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_ctrl_t f; +} vgt_crc_sq_ctrl_u; + + +/* + * VGT_PERFCOUNTER0_SELECT struct + */ + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER0_SELECT_MASK \ + (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \ + ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \ + vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_select_t f; +} vgt_perfcounter0_select_u; + + +/* + * VGT_PERFCOUNTER1_SELECT struct + */ + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER1_SELECT_MASK \ + (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \ + ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \ + vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_select_t f; +} vgt_perfcounter1_select_u; + + +/* + * VGT_PERFCOUNTER2_SELECT struct + */ + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER2_SELECT_MASK \ + (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \ + ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \ + vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_select_t f; +} vgt_perfcounter2_select_u; + + +/* + * VGT_PERFCOUNTER3_SELECT struct + */ + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER3_SELECT_MASK \ + (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \ + ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \ + vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_select_t f; +} vgt_perfcounter3_select_u; + + +/* + * VGT_PERFCOUNTER0_LOW struct + */ + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER0_LOW_MASK \ + (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \ + ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \ + vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_low_t f; +} vgt_perfcounter0_low_u; + + +/* + * VGT_PERFCOUNTER1_LOW struct + */ + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER1_LOW_MASK \ + (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \ + ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \ + vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_low_t f; +} vgt_perfcounter1_low_u; + + +/* + * VGT_PERFCOUNTER2_LOW struct + */ + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER2_LOW_MASK \ + (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \ + ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \ + vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_low_t f; +} vgt_perfcounter2_low_u; + + +/* + * VGT_PERFCOUNTER3_LOW struct + */ + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER3_LOW_MASK \ + (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \ + ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \ + vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_low_t f; +} vgt_perfcounter3_low_u; + + +/* + * VGT_PERFCOUNTER0_HI struct + */ + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER0_HI_MASK \ + (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \ + ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \ + vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } vgt_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_hi_t f; +} vgt_perfcounter0_hi_u; + + +/* + * VGT_PERFCOUNTER1_HI struct + */ + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER1_HI_MASK \ + (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \ + ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \ + vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } vgt_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_hi_t f; +} vgt_perfcounter1_hi_u; + + +/* + * VGT_PERFCOUNTER2_HI struct + */ + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER2_HI_MASK \ + (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \ + ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \ + vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } vgt_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_hi_t f; +} vgt_perfcounter2_hi_u; + + +/* + * VGT_PERFCOUNTER3_HI struct + */ + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER3_HI_MASK \ + (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \ + ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \ + vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } vgt_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_hi_t f; +} vgt_perfcounter3_hi_u; + + +#endif + + +#if !defined (_SQ_FIDDLE_H) +#define _SQ_FIDDLE_H + +/***************************************************************************************************************** + * + * sq_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * SQ_GPR_MANAGEMENT struct + */ + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000 + +#define SQ_GPR_MANAGEMENT_MASK \ + (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) + +#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \ + ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \ + (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \ + (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)) + +#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + unsigned int : 3; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 1; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 13; + } sq_gpr_management_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int : 13; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 1; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 3; + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + } sq_gpr_management_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_gpr_management_t f; +} sq_gpr_management_u; + + +/* + * SQ_FLOW_CONTROL struct + */ + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1 +#define SQ_FLOW_CONTROL_ONE_ALU_SIZE 1 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4 +#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE 1 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0 +#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4 +#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT 8 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12 +#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003 +#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010 +#define SQ_FLOW_CONTROL_ONE_ALU_MASK 0x00000100 +#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000 +#define SQ_FLOW_CONTROL_NO_PV_PS_MASK 0x00010000 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000 + +#define SQ_FLOW_CONTROL_MASK \ + (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ONE_THREAD_MASK | \ + SQ_FLOW_CONTROL_ONE_ALU_MASK | \ + SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \ + SQ_FLOW_CONTROL_NO_PV_PS_MASK | \ + SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \ + SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \ + SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \ + SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \ + SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \ + SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \ + SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) + +#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \ + ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \ + (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \ + (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \ + (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \ + (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \ + (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \ + (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \ + (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \ + (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \ + (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \ + (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \ + (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \ + (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \ + (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \ + (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)) + +#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + unsigned int : 2; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int : 4; + } sq_flow_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int : 4; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 2; + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + } sq_flow_control_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_flow_control_t f; +} sq_flow_control_u; + + +/* + * SQ_INST_STORE_MANAGMENT struct + */ + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000 + +#define SQ_INST_STORE_MANAGMENT_MASK \ + (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \ + SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) + +#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \ + ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \ + (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)) + +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + } sq_inst_store_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + } sq_inst_store_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_inst_store_managment_t f; +} sq_inst_store_managment_u; + + +/* + * SQ_RESOURCE_MANAGMENT struct + */ + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000 + +#define SQ_RESOURCE_MANAGMENT_MASK \ + (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) + +#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \ + ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \ + (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \ + (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)) + +#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int : 7; + } sq_resource_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int : 7; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + } sq_resource_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_resource_managment_t f; +} sq_resource_managment_u; + + +/* + * SQ_EO_RT struct + */ + +#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE 8 +#define SQ_EO_RT_EO_TSTATE_RT_SIZE 8 + +#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0 +#define SQ_EO_RT_EO_TSTATE_RT_SHIFT 16 + +#define SQ_EO_RT_EO_CONSTANTS_RT_MASK 0x000000ff +#define SQ_EO_RT_EO_TSTATE_RT_MASK 0x00ff0000 + +#define SQ_EO_RT_MASK \ + (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \ + SQ_EO_RT_EO_TSTATE_RT_MASK) + +#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \ + ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \ + (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)) + +#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + } sq_eo_rt_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + } sq_eo_rt_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_eo_rt_t f; +} sq_eo_rt_u; + + +/* + * SQ_DEBUG_MISC struct + */ + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8 +#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1 +#define SQ_DEBUG_MISC_RESERVED_SIZE 2 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12 +#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20 +#define SQ_DEBUG_MISC_RESERVED_SHIFT 21 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000 +#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000 +#define SQ_DEBUG_MISC_RESERVED_MASK 0x00600000 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000 + +#define SQ_DEBUG_MISC_MASK \ + (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_READ_CTX_MASK | \ + SQ_DEBUG_MISC_RESERVED_MASK | \ + SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) + +#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \ + ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \ + (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \ + (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \ + (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \ + (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \ + (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \ + (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \ + (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \ + (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)) + +#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + unsigned int : 1; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int : 3; + } sq_debug_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int : 3; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int : 1; + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + } sq_debug_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_t f; +} sq_debug_misc_u; + + +/* + * SQ_ACTIVITY_METER_CNTL struct + */ + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000 +#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000 + +#define SQ_ACTIVITY_METER_CNTL_MASK \ + (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \ + SQ_ACTIVITY_METER_CNTL_SPARE_MASK) + +#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \ + ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \ + (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \ + (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \ + (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)) + +#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + } sq_activity_meter_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + } sq_activity_meter_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_cntl_t f; +} sq_activity_meter_cntl_u; + + +/* + * SQ_ACTIVITY_METER_STATUS struct + */ + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff + +#define SQ_ACTIVITY_METER_STATUS_MASK \ + (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) + +#define SQ_ACTIVITY_METER_STATUS(percent_busy) \ + ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)) + +#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \ + ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \ + sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + unsigned int : 24; + } sq_activity_meter_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int : 24; + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + } sq_activity_meter_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_status_t f; +} sq_activity_meter_status_u; + + +/* + * SQ_INPUT_ARB_PRIORITY struct + */ + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 + +#define SQ_INPUT_ARB_PRIORITY_MASK \ + (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) + +#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \ + ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)) + +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int : 14; + } sq_input_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int : 14; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_input_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_input_arb_priority_t f; +} sq_input_arb_priority_u; + + +/* + * SQ_THREAD_ARB_PRIORITY struct + */ + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000 + +#define SQ_THREAD_ARB_PRIORITY_MASK \ + (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \ + SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \ + SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) + +#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \ + ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \ + (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \ + (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \ + (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \ + (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)) + +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int : 9; + } sq_thread_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int : 9; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_thread_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_thread_arb_priority_t f; +} sq_thread_arb_priority_u; + + +/* + * SQ_DEBUG_INPUT_FSM struct + */ + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007 +#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK 0x00007000 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000 + +#define SQ_DEBUG_INPUT_FSM_MASK \ + (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \ + SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) + +#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \ + ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \ + (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \ + (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \ + (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \ + (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \ + (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \ + (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \ + (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)) + +#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int : 4; + } sq_debug_input_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int : 4; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + } sq_debug_input_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_input_fsm_t f; +} sq_debug_input_fsm_u; + + +/* + * SQ_DEBUG_CONST_MGR_FSM struct + */ + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000 + +#define SQ_DEBUG_CONST_MGR_FSM_MASK \ + (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) + +#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \ + ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \ + (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \ + (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \ + (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \ + (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \ + (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \ + (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \ + (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \ + (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \ + (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)) + +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int : 8; + } sq_debug_const_mgr_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int : 8; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + } sq_debug_const_mgr_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_const_mgr_fsm_t f; +} sq_debug_const_mgr_fsm_u; + + +/* + * SQ_DEBUG_TP_FSM struct + */ + +#define SQ_DEBUG_TP_FSM_EX_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1 +#define SQ_DEBUG_TP_FSM_CF_TP_SIZE 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2 +#define SQ_DEBUG_TP_FSM_GS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3 + +#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT 0 +#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3 +#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT 8 +#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT 12 +#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14 +#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT 16 +#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18 +#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT 20 +#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22 +#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT 24 +#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28 + +#define SQ_DEBUG_TP_FSM_EX_TP_MASK 0x00000007 +#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_TP_FSM_CF_TP_MASK 0x000000f0 +#define SQ_DEBUG_TP_FSM_IF_TP_MASK 0x00000700 +#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_TP_FSM_TIS_TP_MASK 0x00003000 +#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000 +#define SQ_DEBUG_TP_FSM_GS_TP_MASK 0x00030000 +#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000 +#define SQ_DEBUG_TP_FSM_FCR_TP_MASK 0x00300000 +#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000 +#define SQ_DEBUG_TP_FSM_FCS_TP_MASK 0x03000000 +#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000 + +#define SQ_DEBUG_TP_FSM_MASK \ + (SQ_DEBUG_TP_FSM_EX_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED0_MASK | \ + SQ_DEBUG_TP_FSM_CF_TP_MASK | \ + SQ_DEBUG_TP_FSM_IF_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED1_MASK | \ + SQ_DEBUG_TP_FSM_TIS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED2_MASK | \ + SQ_DEBUG_TP_FSM_GS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED3_MASK | \ + SQ_DEBUG_TP_FSM_FCR_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED4_MASK | \ + SQ_DEBUG_TP_FSM_FCS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED5_MASK | \ + SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) + +#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \ + ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \ + (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \ + (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \ + (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \ + (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \ + (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \ + (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \ + (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \ + (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \ + (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \ + (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \ + (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \ + (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \ + (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)) + +#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int : 1; + } sq_debug_tp_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int : 1; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + } sq_debug_tp_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tp_fsm_t f; +} sq_debug_tp_fsm_u; + + +/* + * SQ_DEBUG_FSM_ALU_0 struct + */ + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_0_MASK \ + (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_0_t f; +} sq_debug_fsm_alu_0_u; + + +/* + * SQ_DEBUG_FSM_ALU_1 struct + */ + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_1_MASK \ + (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_1_t f; +} sq_debug_fsm_alu_1_u; + + +/* + * SQ_DEBUG_EXP_ALLOC struct + */ + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000 + +#define SQ_DEBUG_EXP_ALLOC_MASK \ + (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \ + SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) + +#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \ + ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \ + (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \ + (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \ + (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \ + (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)) + +#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int : 10; + } sq_debug_exp_alloc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int : 10; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + } sq_debug_exp_alloc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_exp_alloc_t f; +} sq_debug_exp_alloc_u; + + +/* + * SQ_DEBUG_PTR_BUFF struct + */ + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000 + +#define SQ_DEBUG_PTR_BUFF_MASK \ + (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \ + SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \ + SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \ + SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \ + SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \ + SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) + +#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \ + ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \ + (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \ + (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \ + (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \ + (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \ + (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \ + (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \ + (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \ + (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)) + +#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int : 4; + } sq_debug_ptr_buff_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int : 4; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + } sq_debug_ptr_buff_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_ptr_buff_t f; +} sq_debug_ptr_buff_u; + + +/* + * SQ_DEBUG_GPR_VTX struct + */ + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_VTX_MASK \ + (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) + +#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \ + ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \ + (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \ + (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \ + (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_vtx_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int : 1; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + } sq_debug_gpr_vtx_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_vtx_t f; +} sq_debug_gpr_vtx_u; + + +/* + * SQ_DEBUG_GPR_PIX struct + */ + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_PIX_MASK \ + (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) + +#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \ + ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \ + (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \ + (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \ + (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_pix_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int : 1; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + } sq_debug_gpr_pix_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_pix_t f; +} sq_debug_gpr_pix_u; + + +/* + * SQ_DEBUG_TB_STATUS_SEL struct + */ + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000 + +#define SQ_DEBUG_TB_STATUS_SEL_MASK \ + (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) + +#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \ + ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \ + (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \ + (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \ + (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \ + (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)) + +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int : 1; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + } sq_debug_tb_status_sel_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int : 1; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + } sq_debug_tb_status_sel_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tb_status_sel_t f; +} sq_debug_tb_status_sel_u; + + +/* + * SQ_DEBUG_VTX_TB_0 struct + */ + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE 1 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK 0x00200000 + +#define SQ_DEBUG_VTX_TB_0_MASK \ + (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \ + SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) + +#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \ + ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \ + (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \ + (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \ + (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \ + (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \ + (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \ + (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)) + +#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int : 10; + } sq_debug_vtx_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int : 10; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + } sq_debug_vtx_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_0_t f; +} sq_debug_vtx_tb_0_u; + + +/* + * SQ_DEBUG_VTX_TB_1 struct + */ + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff + +#define SQ_DEBUG_VTX_TB_1_MASK \ + (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) + +#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \ + ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)) + +#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \ + ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \ + sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + unsigned int : 16; + } sq_debug_vtx_tb_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int : 16; + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + } sq_debug_vtx_tb_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_1_t f; +} sq_debug_vtx_tb_1_u; + + +/* + * SQ_DEBUG_VTX_TB_STATUS_REG struct + */ + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \ + (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) + +#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \ + ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \ + ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \ + sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_status_reg_t f; +} sq_debug_vtx_tb_status_reg_u; + + +/* + * SQ_DEBUG_VTX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) + +#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \ + ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \ + ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \ + sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_state_mem_t f; +} sq_debug_vtx_tb_state_mem_u; + + +/* + * SQ_DEBUG_PIX_TB_0 struct + */ + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE 1 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25 +#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT 31 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000 +#define SQ_DEBUG_PIX_TB_0_BUSY_MASK 0x80000000 + +#define SQ_DEBUG_PIX_TB_0_MASK \ + (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_BUSY_MASK) + +#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \ + ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \ + (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \ + (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \ + (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \ + (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \ + (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)) + +#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + } sq_debug_pix_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + } sq_debug_pix_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_0_t f; +} sq_debug_pix_tb_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \ + ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \ + ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \ + sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_0_t f; +} sq_debug_pix_tb_status_reg_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \ + ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \ + ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \ + sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_1_t f; +} sq_debug_pix_tb_status_reg_1_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \ + ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \ + ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \ + sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_2_t f; +} sq_debug_pix_tb_status_reg_2_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \ + ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \ + ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \ + sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_3_t f; +} sq_debug_pix_tb_status_reg_3_u; + + +/* + * SQ_DEBUG_PIX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) + +#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \ + ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \ + ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \ + sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_state_mem_t f; +} sq_debug_pix_tb_state_mem_u; + + +/* + * SQ_PERFCOUNTER0_SELECT struct + */ + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER0_SELECT_MASK \ + (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \ + ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \ + sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sq_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_select_t f; +} sq_perfcounter0_select_u; + + +/* + * SQ_PERFCOUNTER1_SELECT struct + */ + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER1_SELECT_MASK \ + (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \ + ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \ + sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } sq_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_select_t f; +} sq_perfcounter1_select_u; + + +/* + * SQ_PERFCOUNTER2_SELECT struct + */ + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER2_SELECT_MASK \ + (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \ + ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \ + sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } sq_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_select_t f; +} sq_perfcounter2_select_u; + + +/* + * SQ_PERFCOUNTER3_SELECT struct + */ + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER3_SELECT_MASK \ + (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \ + ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \ + sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } sq_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_select_t f; +} sq_perfcounter3_select_u; + + +/* + * SQ_PERFCOUNTER0_LOW struct + */ + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER0_LOW_MASK \ + (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \ + ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \ + sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_low_t f; +} sq_perfcounter0_low_u; + + +/* + * SQ_PERFCOUNTER0_HI struct + */ + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER0_HI_MASK \ + (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \ + ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \ + sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sq_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_hi_t f; +} sq_perfcounter0_hi_u; + + +/* + * SQ_PERFCOUNTER1_LOW struct + */ + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER1_LOW_MASK \ + (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \ + ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \ + sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_low_t f; +} sq_perfcounter1_low_u; + + +/* + * SQ_PERFCOUNTER1_HI struct + */ + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER1_HI_MASK \ + (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \ + ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \ + sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } sq_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_hi_t f; +} sq_perfcounter1_hi_u; + + +/* + * SQ_PERFCOUNTER2_LOW struct + */ + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER2_LOW_MASK \ + (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \ + ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \ + sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_low_t f; +} sq_perfcounter2_low_u; + + +/* + * SQ_PERFCOUNTER2_HI struct + */ + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER2_HI_MASK \ + (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \ + ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \ + sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } sq_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_hi_t f; +} sq_perfcounter2_hi_u; + + +/* + * SQ_PERFCOUNTER3_LOW struct + */ + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER3_LOW_MASK \ + (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \ + ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \ + sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_low_t f; +} sq_perfcounter3_low_u; + + +/* + * SQ_PERFCOUNTER3_HI struct + */ + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER3_HI_MASK \ + (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \ + ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \ + sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } sq_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_hi_t f; +} sq_perfcounter3_hi_u; + + +/* + * SX_PERFCOUNTER0_SELECT struct + */ + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SX_PERFCOUNTER0_SELECT_MASK \ + (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SX_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \ + ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \ + sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sx_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sx_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_select_t f; +} sx_perfcounter0_select_u; + + +/* + * SX_PERFCOUNTER0_LOW struct + */ + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SX_PERFCOUNTER0_LOW_MASK \ + (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \ + ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \ + sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_low_t f; +} sx_perfcounter0_low_u; + + +/* + * SX_PERFCOUNTER0_HI struct + */ + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SX_PERFCOUNTER0_HI_MASK \ + (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \ + ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \ + sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sx_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sx_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_hi_t f; +} sx_perfcounter0_hi_u; + + +/* + * SQ_INSTRUCTION_ALU_0 struct + */ + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0 +#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT 6 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8 +#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT 14 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000 + +#define SQ_INSTRUCTION_ALU_0_MASK \ + (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK | \ + SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK | \ + SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) + +#define SQ_INSTRUCTION_ALU_0(vector_result, cst_0_abs_mod, low_precision_16b_fp, scalar_result, sst_0_abs_mod, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \ + ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \ + (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) | \ + (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \ + (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \ + (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) | \ + (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \ + (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \ + (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \ + (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \ + (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \ + (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_CST_0_ABS_MOD(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SST_0_ABS_MOD(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_CST_0_ABS_MOD(sq_instruction_alu_0_reg, cst_0_abs_mod) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) | (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SST_0_ABS_MOD(sq_instruction_alu_0_reg, sst_0_abs_mod) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) | (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + unsigned int cst_0_abs_mod : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int sst_0_abs_mod : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + } sq_instruction_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int sst_0_abs_mod : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int cst_0_abs_mod : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE; + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + } sq_instruction_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_0_t f; +} sq_instruction_alu_0_u; + + +/* + * SQ_INSTRUCTION_ALU_1 struct + */ + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_1_MASK \ + (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \ + SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) + +#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \ + ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \ + (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \ + (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \ + (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \ + (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \ + (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \ + (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \ + (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \ + (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \ + (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \ + (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \ + (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \ + (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \ + (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \ + (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \ + (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \ + (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \ + (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)) + +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + } sq_instruction_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + } sq_instruction_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_1_t f; +} sq_instruction_alu_1_u; + + +/* + * SQ_INSTRUCTION_ALU_2 struct + */ + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_2_MASK \ + (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \ + SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) + +#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \ + ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \ + (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \ + (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \ + (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \ + (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \ + (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \ + (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \ + (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \ + (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \ + (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \ + (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \ + (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \ + (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)) + +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + } sq_instruction_alu_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + } sq_instruction_alu_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_2_t f; +} sq_instruction_alu_2_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_0 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_0_MASK \ + (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \ + ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \ + (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + } sq_instruction_cf_exec_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + } sq_instruction_cf_exec_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_0_t f; +} sq_instruction_cf_exec_0_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_1 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_1_MASK \ + (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \ + ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + } sq_instruction_cf_exec_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + } sq_instruction_cf_exec_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_1_t f; +} sq_instruction_cf_exec_1_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_2 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_EXEC_2_MASK \ + (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \ + ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \ + (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + } sq_instruction_cf_exec_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + } sq_instruction_cf_exec_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_2_t f; +} sq_instruction_cf_exec_2_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_0 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000 + +#define SQ_INSTRUCTION_CF_LOOP_0_MASK \ + (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \ + (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + } sq_instruction_cf_loop_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + } sq_instruction_cf_loop_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_0_t f; +} sq_instruction_cf_loop_0_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_1 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000 + +#define SQ_INSTRUCTION_CF_LOOP_1_MASK \ + (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + } sq_instruction_cf_loop_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + } sq_instruction_cf_loop_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_1_t f; +} sq_instruction_cf_loop_1_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_2 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_LOOP_2_MASK \ + (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \ + ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + } sq_instruction_cf_loop_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + } sq_instruction_cf_loop_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_2_t f; +} sq_instruction_cf_loop_2_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_0 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \ + (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_0_t f; +} sq_instruction_cf_jmp_call_0_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_1 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \ + ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \ + (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_1_t f; +} sq_instruction_cf_jmp_call_1_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_2 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_2_t f; +} sq_instruction_cf_jmp_call_2_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_0 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0 + +#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \ + ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + } sq_instruction_cf_alloc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + } sq_instruction_cf_alloc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_0_t f; +} sq_instruction_cf_alloc_0_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_1 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000 + +#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \ + (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + } sq_instruction_cf_alloc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + } sq_instruction_cf_alloc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_1_t f; +} sq_instruction_cf_alloc_1_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_2 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + } sq_instruction_cf_alloc_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + } sq_instruction_cf_alloc_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_2_t f; +} sq_instruction_cf_alloc_2_u; + + +/* + * SQ_INSTRUCTION_TFETCH_0 struct + */ + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000 + +#define SQ_INSTRUCTION_TFETCH_0_MASK \ + (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \ + SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) + +#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \ + ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \ + (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \ + (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \ + (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \ + (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \ + (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \ + (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + } sq_instruction_tfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + } sq_instruction_tfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_0_t f; +} sq_instruction_tfetch_0_u; + + +/* + * SQ_INSTRUCTION_TFETCH_1 struct + */ + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_1_MASK \ + (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \ + (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \ + (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \ + (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \ + (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \ + (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \ + (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \ + (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \ + (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \ + (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_tfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_tfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_1_t f; +} sq_instruction_tfetch_1_u; + + +/* + * SQ_INSTRUCTION_TFETCH_2 struct + */ + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_2_MASK \ + (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \ + SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \ + ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \ + (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \ + (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \ + (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \ + (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \ + (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \ + (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_tfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + } sq_instruction_tfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_2_t f; +} sq_instruction_tfetch_2_u; + + +/* + * SQ_INSTRUCTION_VFETCH_0 struct + */ + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000 + +#define SQ_INSTRUCTION_VFETCH_0_MASK \ + (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) + +#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \ + ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \ + (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \ + (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \ + (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \ + (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int : 3; + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + } sq_instruction_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + unsigned int : 3; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + } sq_instruction_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_0_t f; +} sq_instruction_vfetch_0_u; + + +/* + * SQ_INSTRUCTION_VFETCH_1 struct + */ + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_1_MASK \ + (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \ + SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \ + (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \ + (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \ + (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \ + (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \ + (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_1_t f; +} sq_instruction_vfetch_1_u; + + +/* + * SQ_INSTRUCTION_VFETCH_2 struct + */ + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_2_MASK \ + (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \ + SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \ + SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \ + ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \ + (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + unsigned int : 8; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 7; + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_vfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + unsigned int : 7; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 8; + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + } sq_instruction_vfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_2_t f; +} sq_instruction_vfetch_2_u; + + +/* + * SQ_CONSTANT_0 struct + */ + +#define SQ_CONSTANT_0_RED_SIZE 32 + +#define SQ_CONSTANT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_0_MASK \ + (SQ_CONSTANT_0_RED_MASK) + +#define SQ_CONSTANT_0(red) \ + ((red << SQ_CONSTANT_0_RED_SHIFT)) + +#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \ + ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT) + +#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \ + sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_0_t f; +} sq_constant_0_u; + + +/* + * SQ_CONSTANT_1 struct + */ + +#define SQ_CONSTANT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_1_MASK \ + (SQ_CONSTANT_1_GREEN_MASK) + +#define SQ_CONSTANT_1(green) \ + ((green << SQ_CONSTANT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \ + ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \ + sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_1_t f; +} sq_constant_1_u; + + +/* + * SQ_CONSTANT_2 struct + */ + +#define SQ_CONSTANT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_2_MASK \ + (SQ_CONSTANT_2_BLUE_MASK) + +#define SQ_CONSTANT_2(blue) \ + ((blue << SQ_CONSTANT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \ + ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \ + sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_2_t f; +} sq_constant_2_u; + + +/* + * SQ_CONSTANT_3 struct + */ + +#define SQ_CONSTANT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_3_MASK \ + (SQ_CONSTANT_3_ALPHA_MASK) + +#define SQ_CONSTANT_3(alpha) \ + ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \ + ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \ + sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_3_t f; +} sq_constant_3_u; + + +/* + * SQ_FETCH_0 struct + */ + +#define SQ_FETCH_0_VALUE_SIZE 32 + +#define SQ_FETCH_0_VALUE_SHIFT 0 + +#define SQ_FETCH_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_0_MASK \ + (SQ_FETCH_0_VALUE_MASK) + +#define SQ_FETCH_0(value) \ + ((value << SQ_FETCH_0_VALUE_SHIFT)) + +#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \ + ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT) + +#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \ + sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_0_t f; +} sq_fetch_0_u; + + +/* + * SQ_FETCH_1 struct + */ + +#define SQ_FETCH_1_VALUE_SIZE 32 + +#define SQ_FETCH_1_VALUE_SHIFT 0 + +#define SQ_FETCH_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_1_MASK \ + (SQ_FETCH_1_VALUE_MASK) + +#define SQ_FETCH_1(value) \ + ((value << SQ_FETCH_1_VALUE_SHIFT)) + +#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \ + ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT) + +#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \ + sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_1_t f; +} sq_fetch_1_u; + + +/* + * SQ_FETCH_2 struct + */ + +#define SQ_FETCH_2_VALUE_SIZE 32 + +#define SQ_FETCH_2_VALUE_SHIFT 0 + +#define SQ_FETCH_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_2_MASK \ + (SQ_FETCH_2_VALUE_MASK) + +#define SQ_FETCH_2(value) \ + ((value << SQ_FETCH_2_VALUE_SHIFT)) + +#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \ + ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT) + +#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \ + sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_2_t f; +} sq_fetch_2_u; + + +/* + * SQ_FETCH_3 struct + */ + +#define SQ_FETCH_3_VALUE_SIZE 32 + +#define SQ_FETCH_3_VALUE_SHIFT 0 + +#define SQ_FETCH_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_3_MASK \ + (SQ_FETCH_3_VALUE_MASK) + +#define SQ_FETCH_3(value) \ + ((value << SQ_FETCH_3_VALUE_SHIFT)) + +#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \ + ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT) + +#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \ + sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_3_t f; +} sq_fetch_3_u; + + +/* + * SQ_FETCH_4 struct + */ + +#define SQ_FETCH_4_VALUE_SIZE 32 + +#define SQ_FETCH_4_VALUE_SHIFT 0 + +#define SQ_FETCH_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_4_MASK \ + (SQ_FETCH_4_VALUE_MASK) + +#define SQ_FETCH_4(value) \ + ((value << SQ_FETCH_4_VALUE_SHIFT)) + +#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \ + ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT) + +#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \ + sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_4_t f; +} sq_fetch_4_u; + + +/* + * SQ_FETCH_5 struct + */ + +#define SQ_FETCH_5_VALUE_SIZE 32 + +#define SQ_FETCH_5_VALUE_SHIFT 0 + +#define SQ_FETCH_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_5_MASK \ + (SQ_FETCH_5_VALUE_MASK) + +#define SQ_FETCH_5(value) \ + ((value << SQ_FETCH_5_VALUE_SHIFT)) + +#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \ + ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT) + +#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \ + sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_5_t f; +} sq_fetch_5_u; + + +/* + * SQ_CONSTANT_VFETCH_0 struct + */ + +#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0 +#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001 +#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_0_MASK \ + (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \ + SQ_CONSTANT_VFETCH_0_STATE_MASK | \ + SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \ + ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \ + (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \ + (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + } sq_constant_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + } sq_constant_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_0_t f; +} sq_constant_vfetch_0_u; + + +/* + * SQ_CONSTANT_VFETCH_1 struct + */ + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_1_MASK \ + (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \ + SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \ + ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \ + (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + } sq_constant_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + } sq_constant_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_1_t f; +} sq_constant_vfetch_1_u; + + +/* + * SQ_CONSTANT_T2 struct + */ + +#define SQ_CONSTANT_T2_VALUE_SIZE 32 + +#define SQ_CONSTANT_T2_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T2_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T2_MASK \ + (SQ_CONSTANT_T2_VALUE_MASK) + +#define SQ_CONSTANT_T2(value) \ + ((value << SQ_CONSTANT_T2_VALUE_SHIFT)) + +#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \ + ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT) + +#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \ + sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t2_t f; +} sq_constant_t2_u; + + +/* + * SQ_CONSTANT_T3 struct + */ + +#define SQ_CONSTANT_T3_VALUE_SIZE 32 + +#define SQ_CONSTANT_T3_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T3_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T3_MASK \ + (SQ_CONSTANT_T3_VALUE_MASK) + +#define SQ_CONSTANT_T3(value) \ + ((value << SQ_CONSTANT_T3_VALUE_SHIFT)) + +#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \ + ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT) + +#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \ + sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t3_t f; +} sq_constant_t3_u; + + +/* + * SQ_CF_BOOLEANS struct + */ + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_BOOLEANS_MASK \ + (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_booleans_t f; +} sq_cf_booleans_u; + + +/* + * SQ_CF_LOOP struct + */ + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_LOOP_MASK \ + (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_loop_t f; +} sq_cf_loop_u; + + +/* + * SQ_CONSTANT_RT_0 struct + */ + +#define SQ_CONSTANT_RT_0_RED_SIZE 32 + +#define SQ_CONSTANT_RT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_RT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_RT_0_MASK \ + (SQ_CONSTANT_RT_0_RED_MASK) + +#define SQ_CONSTANT_RT_0(red) \ + ((red << SQ_CONSTANT_RT_0_RED_SHIFT)) + +#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \ + ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT) + +#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \ + sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_0_t f; +} sq_constant_rt_0_u; + + +/* + * SQ_CONSTANT_RT_1 struct + */ + +#define SQ_CONSTANT_RT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_RT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_RT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_RT_1_MASK \ + (SQ_CONSTANT_RT_1_GREEN_MASK) + +#define SQ_CONSTANT_RT_1(green) \ + ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \ + ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \ + sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_1_t f; +} sq_constant_rt_1_u; + + +/* + * SQ_CONSTANT_RT_2 struct + */ + +#define SQ_CONSTANT_RT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_RT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_RT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_RT_2_MASK \ + (SQ_CONSTANT_RT_2_BLUE_MASK) + +#define SQ_CONSTANT_RT_2(blue) \ + ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \ + ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \ + sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_2_t f; +} sq_constant_rt_2_u; + + +/* + * SQ_CONSTANT_RT_3 struct + */ + +#define SQ_CONSTANT_RT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_RT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_RT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_RT_3_MASK \ + (SQ_CONSTANT_RT_3_ALPHA_MASK) + +#define SQ_CONSTANT_RT_3(alpha) \ + ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \ + ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \ + sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_3_t f; +} sq_constant_rt_3_u; + + +/* + * SQ_FETCH_RT_0 struct + */ + +#define SQ_FETCH_RT_0_VALUE_SIZE 32 + +#define SQ_FETCH_RT_0_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_0_MASK \ + (SQ_FETCH_RT_0_VALUE_MASK) + +#define SQ_FETCH_RT_0(value) \ + ((value << SQ_FETCH_RT_0_VALUE_SHIFT)) + +#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \ + ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT) + +#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \ + sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_0_t f; +} sq_fetch_rt_0_u; + + +/* + * SQ_FETCH_RT_1 struct + */ + +#define SQ_FETCH_RT_1_VALUE_SIZE 32 + +#define SQ_FETCH_RT_1_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_1_MASK \ + (SQ_FETCH_RT_1_VALUE_MASK) + +#define SQ_FETCH_RT_1(value) \ + ((value << SQ_FETCH_RT_1_VALUE_SHIFT)) + +#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \ + ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT) + +#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \ + sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_1_t f; +} sq_fetch_rt_1_u; + + +/* + * SQ_FETCH_RT_2 struct + */ + +#define SQ_FETCH_RT_2_VALUE_SIZE 32 + +#define SQ_FETCH_RT_2_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_2_MASK \ + (SQ_FETCH_RT_2_VALUE_MASK) + +#define SQ_FETCH_RT_2(value) \ + ((value << SQ_FETCH_RT_2_VALUE_SHIFT)) + +#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \ + ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT) + +#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \ + sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_2_t f; +} sq_fetch_rt_2_u; + + +/* + * SQ_FETCH_RT_3 struct + */ + +#define SQ_FETCH_RT_3_VALUE_SIZE 32 + +#define SQ_FETCH_RT_3_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_3_MASK \ + (SQ_FETCH_RT_3_VALUE_MASK) + +#define SQ_FETCH_RT_3(value) \ + ((value << SQ_FETCH_RT_3_VALUE_SHIFT)) + +#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \ + ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT) + +#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \ + sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_3_t f; +} sq_fetch_rt_3_u; + + +/* + * SQ_FETCH_RT_4 struct + */ + +#define SQ_FETCH_RT_4_VALUE_SIZE 32 + +#define SQ_FETCH_RT_4_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_4_MASK \ + (SQ_FETCH_RT_4_VALUE_MASK) + +#define SQ_FETCH_RT_4(value) \ + ((value << SQ_FETCH_RT_4_VALUE_SHIFT)) + +#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \ + ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT) + +#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \ + sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_4_t f; +} sq_fetch_rt_4_u; + + +/* + * SQ_FETCH_RT_5 struct + */ + +#define SQ_FETCH_RT_5_VALUE_SIZE 32 + +#define SQ_FETCH_RT_5_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_5_MASK \ + (SQ_FETCH_RT_5_VALUE_MASK) + +#define SQ_FETCH_RT_5(value) \ + ((value << SQ_FETCH_RT_5_VALUE_SHIFT)) + +#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \ + ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT) + +#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \ + sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_5_t f; +} sq_fetch_rt_5_u; + + +/* + * SQ_CF_RT_BOOLEANS struct + */ + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_RT_BOOLEANS_MASK \ + (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_rt_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_rt_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_booleans_t f; +} sq_cf_rt_booleans_u; + + +/* + * SQ_CF_RT_LOOP struct + */ + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_RT_LOOP_MASK \ + (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_rt_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_rt_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_loop_t f; +} sq_cf_rt_loop_u; + + +/* + * SQ_VS_PROGRAM struct + */ + +#define SQ_VS_PROGRAM_BASE_SIZE 12 +#define SQ_VS_PROGRAM_SIZE_SIZE 12 + +#define SQ_VS_PROGRAM_BASE_SHIFT 0 +#define SQ_VS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_VS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_VS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_VS_PROGRAM_MASK \ + (SQ_VS_PROGRAM_BASE_MASK | \ + SQ_VS_PROGRAM_SIZE_MASK) + +#define SQ_VS_PROGRAM(base, size) \ + ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_VS_PROGRAM_SIZE_SHIFT)) + +#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT) + +#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_vs_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int : 8; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + } sq_vs_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_program_t f; +} sq_vs_program_u; + + +/* + * SQ_PS_PROGRAM struct + */ + +#define SQ_PS_PROGRAM_BASE_SIZE 12 +#define SQ_PS_PROGRAM_SIZE_SIZE 12 + +#define SQ_PS_PROGRAM_BASE_SHIFT 0 +#define SQ_PS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_PS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_PS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_PS_PROGRAM_MASK \ + (SQ_PS_PROGRAM_BASE_MASK | \ + SQ_PS_PROGRAM_SIZE_MASK) + +#define SQ_PS_PROGRAM(base, size) \ + ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_PS_PROGRAM_SIZE_SHIFT)) + +#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT) + +#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_ps_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int : 8; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + } sq_ps_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_program_t f; +} sq_ps_program_u; + + +/* + * SQ_CF_PROGRAM_SIZE struct + */ + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000 + +#define SQ_CF_PROGRAM_SIZE_MASK \ + (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \ + SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) + +#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \ + ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \ + (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)) + +#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 9; + } sq_cf_program_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int : 9; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + } sq_cf_program_size_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_program_size_t f; +} sq_cf_program_size_u; + + +/* + * SQ_INTERPOLATOR_CNTL struct + */ + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000 + +#define SQ_INTERPOLATOR_CNTL_MASK \ + (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \ + SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) + +#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \ + ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \ + (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)) + +#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + } sq_interpolator_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + } sq_interpolator_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_interpolator_cntl_t f; +} sq_interpolator_cntl_u; + + +/* + * SQ_PROGRAM_CNTL struct + */ + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f +#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000 +#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000 + +#define SQ_PROGRAM_CNTL_MASK \ + (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) + +#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \ + ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \ + (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \ + (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \ + (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \ + (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \ + (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \ + (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \ + (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \ + (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \ + (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)) + +#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + } sq_program_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + } sq_program_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_program_cntl_t f; +} sq_program_cntl_u; + + +/* + * SQ_WRAPPING_0 struct + */ + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f +#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0 +#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00 +#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000 +#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000 +#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000 +#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000 +#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000 + +#define SQ_WRAPPING_0_MASK \ + (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_7_MASK) + +#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \ + ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \ + (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \ + (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \ + (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \ + (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \ + (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \ + (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \ + (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)) + +#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + } sq_wrapping_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + } sq_wrapping_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_0_t f; +} sq_wrapping_0_u; + + +/* + * SQ_WRAPPING_1 struct + */ + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f +#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0 +#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00 +#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000 +#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000 +#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000 +#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000 +#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000 + +#define SQ_WRAPPING_1_MASK \ + (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_15_MASK) + +#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \ + ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \ + (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \ + (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \ + (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \ + (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \ + (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \ + (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \ + (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)) + +#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + } sq_wrapping_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + } sq_wrapping_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_1_t f; +} sq_wrapping_1_u; + + +/* + * SQ_VS_CONST struct + */ + +#define SQ_VS_CONST_BASE_SIZE 9 +#define SQ_VS_CONST_SIZE_SIZE 9 + +#define SQ_VS_CONST_BASE_SHIFT 0 +#define SQ_VS_CONST_SIZE_SHIFT 12 + +#define SQ_VS_CONST_BASE_MASK 0x000001ff +#define SQ_VS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_VS_CONST_MASK \ + (SQ_VS_CONST_BASE_MASK | \ + SQ_VS_CONST_SIZE_MASK) + +#define SQ_VS_CONST(base, size) \ + ((base << SQ_VS_CONST_BASE_SHIFT) | \ + (size << SQ_VS_CONST_SIZE_SHIFT)) + +#define SQ_VS_CONST_GET_BASE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT) + +#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int base : SQ_VS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_vs_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int : 11; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_VS_CONST_BASE_SIZE; + } sq_vs_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_const_t f; +} sq_vs_const_u; + + +/* + * SQ_PS_CONST struct + */ + +#define SQ_PS_CONST_BASE_SIZE 9 +#define SQ_PS_CONST_SIZE_SIZE 9 + +#define SQ_PS_CONST_BASE_SHIFT 0 +#define SQ_PS_CONST_SIZE_SHIFT 12 + +#define SQ_PS_CONST_BASE_MASK 0x000001ff +#define SQ_PS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_PS_CONST_MASK \ + (SQ_PS_CONST_BASE_MASK | \ + SQ_PS_CONST_SIZE_MASK) + +#define SQ_PS_CONST(base, size) \ + ((base << SQ_PS_CONST_BASE_SHIFT) | \ + (size << SQ_PS_CONST_SIZE_SHIFT)) + +#define SQ_PS_CONST_GET_BASE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT) + +#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int base : SQ_PS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_ps_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int : 11; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_PS_CONST_BASE_SIZE; + } sq_ps_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_const_t f; +} sq_ps_const_u; + + +/* + * SQ_CONTEXT_MISC struct + */ + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000 + +#define SQ_CONTEXT_MISC_MASK \ + (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \ + SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \ + SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \ + SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \ + SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) + +#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \ + ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \ + (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \ + (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \ + (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \ + (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \ + (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \ + (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)) + +#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int : 4; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int : 13; + } sq_context_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int : 13; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int : 4; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + } sq_context_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_context_misc_t f; +} sq_context_misc_u; + + +/* + * SQ_CF_RD_BASE struct + */ + +#define SQ_CF_RD_BASE_RD_BASE_SIZE 3 + +#define SQ_CF_RD_BASE_RD_BASE_SHIFT 0 + +#define SQ_CF_RD_BASE_RD_BASE_MASK 0x00000007 + +#define SQ_CF_RD_BASE_MASK \ + (SQ_CF_RD_BASE_RD_BASE_MASK) + +#define SQ_CF_RD_BASE(rd_base) \ + ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)) + +#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \ + ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \ + sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + unsigned int : 29; + } sq_cf_rd_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int : 29; + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + } sq_cf_rd_base_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rd_base_t f; +} sq_cf_rd_base_u; + + +/* + * SQ_DEBUG_MISC_0 struct + */ + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000 + +#define SQ_DEBUG_MISC_0_MASK \ + (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) + +#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \ + ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \ + (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \ + (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \ + (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)) + +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 5; + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + } sq_debug_misc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + unsigned int : 5; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + } sq_debug_misc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_0_t f; +} sq_debug_misc_0_u; + + +/* + * SQ_DEBUG_MISC_1 struct + */ + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000 + +#define SQ_DEBUG_MISC_1_MASK \ + (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \ + SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \ + SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \ + SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) + +#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \ + ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \ + (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \ + (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \ + (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)) + +#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int : 6; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int : 5; + } sq_debug_misc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int : 5; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int : 6; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + } sq_debug_misc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_1_t f; +} sq_debug_misc_1_u; + + +#endif + + +#if !defined (_SX_FIDDLE_H) +#define _SX_FIDDLE_H + +/***************************************************************************************************************** + * + * sx_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_TP_FIDDLE_H) +#define _TP_FIDDLE_H + +/***************************************************************************************************************** + * + * tp_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * TC_CNTL_STATUS struct + */ + +#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2 +#define TC_CNTL_STATUS_TC_BUSY_SIZE 1 + +#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18 +#define TC_CNTL_STATUS_TC_BUSY_SHIFT 31 + +#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000 +#define TC_CNTL_STATUS_TC_BUSY_MASK 0x80000000 + +#define TC_CNTL_STATUS_MASK \ + (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \ + TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \ + TC_CNTL_STATUS_TC_BUSY_MASK) + +#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \ + ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \ + (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \ + (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)) + +#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + unsigned int : 17; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 11; + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + } tc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + unsigned int : 11; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 17; + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + } tc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tc_cntl_status_t f; +} tc_cntl_status_u; + + +/* + * TCR_CHICKEN struct + */ + +#define TCR_CHICKEN_SPARE_SIZE 32 + +#define TCR_CHICKEN_SPARE_SHIFT 0 + +#define TCR_CHICKEN_SPARE_MASK 0xffffffff + +#define TCR_CHICKEN_MASK \ + (TCR_CHICKEN_SPARE_MASK) + +#define TCR_CHICKEN(spare) \ + ((spare << TCR_CHICKEN_SPARE_SHIFT)) + +#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \ + ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT) + +#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \ + tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_chicken_t f; +} tcr_chicken_u; + + +/* + * TCF_CHICKEN struct + */ + +#define TCF_CHICKEN_SPARE_SIZE 32 + +#define TCF_CHICKEN_SPARE_SHIFT 0 + +#define TCF_CHICKEN_SPARE_MASK 0xffffffff + +#define TCF_CHICKEN_MASK \ + (TCF_CHICKEN_SPARE_MASK) + +#define TCF_CHICKEN(spare) \ + ((spare << TCF_CHICKEN_SPARE_SHIFT)) + +#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \ + ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT) + +#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \ + tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_chicken_t f; +} tcf_chicken_u; + + +/* + * TCM_CHICKEN struct + */ + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1 +#define TCM_CHICKEN_SPARE_SIZE 23 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8 +#define TCM_CHICKEN_SPARE_SHIFT 9 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100 +#define TCM_CHICKEN_SPARE_MASK 0xfffffe00 + +#define TCM_CHICKEN_MASK \ + (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \ + TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \ + TCM_CHICKEN_SPARE_MASK) + +#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \ + ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \ + (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \ + (spare << TCM_CHICKEN_SPARE_SHIFT)) + +#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT) + +#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + } tcm_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + } tcm_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_chicken_t f; +} tcm_chicken_u; + + +/* + * TCR_PERFCOUNTER0_SELECT struct + */ + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER0_SELECT_MASK \ + (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \ + ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \ + tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_select_t f; +} tcr_perfcounter0_select_u; + + +/* + * TCR_PERFCOUNTER1_SELECT struct + */ + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER1_SELECT_MASK \ + (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \ + ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \ + tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_select_t f; +} tcr_perfcounter1_select_u; + + +/* + * TCR_PERFCOUNTER0_HI struct + */ + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER0_HI_MASK \ + (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \ + ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \ + tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_hi_t f; +} tcr_perfcounter0_hi_u; + + +/* + * TCR_PERFCOUNTER1_HI struct + */ + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER1_HI_MASK \ + (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \ + ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \ + tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_hi_t f; +} tcr_perfcounter1_hi_u; + + +/* + * TCR_PERFCOUNTER0_LOW struct + */ + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER0_LOW_MASK \ + (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \ + ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \ + tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_low_t f; +} tcr_perfcounter0_low_u; + + +/* + * TCR_PERFCOUNTER1_LOW struct + */ + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER1_LOW_MASK \ + (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \ + ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \ + tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_low_t f; +} tcr_perfcounter1_low_u; + + +/* + * TP_TC_CLKGATE_CNTL struct + */ + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038 + +#define TP_TC_CLKGATE_CNTL_MASK \ + (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \ + TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) + +#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \ + ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \ + (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)) + +#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int : 26; + } tp_tc_clkgate_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int : 26; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + } tp_tc_clkgate_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + tp_tc_clkgate_cntl_t f; +} tp_tc_clkgate_cntl_u; + + +/* + * TPC_CNTL_STATUS struct + */ + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BUSY_SIZE 1 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15 +#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17 +#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19 +#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22 +#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23 +#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25 +#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27 +#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30 +#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000 +#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000 +#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000 +#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000 +#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000 +#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000 +#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000 +#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000 +#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000 +#define TPC_CNTL_STATUS_TPC_BUSY_MASK 0x80000000 + +#define TPC_CNTL_STATUS_MASK \ + (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTR_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TF_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \ + TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \ + TPC_CNTL_STATUS_TPC_BUSY_MASK) + +#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \ + ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \ + (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \ + (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \ + (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \ + (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \ + (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \ + (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \ + (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \ + (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \ + (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \ + (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \ + (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \ + (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \ + (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \ + (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \ + (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \ + (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \ + (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \ + (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \ + (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \ + (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \ + (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \ + (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \ + (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \ + (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \ + (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \ + (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \ + (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)) + +#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int : 1; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int : 1; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + } tpc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int : 1; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int : 1; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + } tpc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_cntl_status_t f; +} tpc_cntl_status_u; + + +/* + * TPC_DEBUG0 struct + */ + +#define TPC_DEBUG0_LOD_CNTL_SIZE 2 +#define TPC_DEBUG0_IC_CTR_SIZE 2 +#define TPC_DEBUG0_WALKER_CNTL_SIZE 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SIZE 3 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1 +#define TPC_DEBUG0_WALKER_STATE_SIZE 10 +#define TPC_DEBUG0_ALIGNER_STATE_SIZE 2 +#define TPC_DEBUG0_REG_CLK_EN_SIZE 1 +#define TPC_DEBUG0_TPC_CLK_EN_SIZE 1 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE 1 + +#define TPC_DEBUG0_LOD_CNTL_SHIFT 0 +#define TPC_DEBUG0_IC_CTR_SHIFT 2 +#define TPC_DEBUG0_WALKER_CNTL_SHIFT 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT 8 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12 +#define TPC_DEBUG0_WALKER_STATE_SHIFT 16 +#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26 +#define TPC_DEBUG0_REG_CLK_EN_SHIFT 29 +#define TPC_DEBUG0_TPC_CLK_EN_SHIFT 30 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT 31 + +#define TPC_DEBUG0_LOD_CNTL_MASK 0x00000003 +#define TPC_DEBUG0_IC_CTR_MASK 0x0000000c +#define TPC_DEBUG0_WALKER_CNTL_MASK 0x000000f0 +#define TPC_DEBUG0_ALIGNER_CNTL_MASK 0x00000700 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000 +#define TPC_DEBUG0_WALKER_STATE_MASK 0x03ff0000 +#define TPC_DEBUG0_ALIGNER_STATE_MASK 0x0c000000 +#define TPC_DEBUG0_REG_CLK_EN_MASK 0x20000000 +#define TPC_DEBUG0_TPC_CLK_EN_MASK 0x40000000 +#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK 0x80000000 + +#define TPC_DEBUG0_MASK \ + (TPC_DEBUG0_LOD_CNTL_MASK | \ + TPC_DEBUG0_IC_CTR_MASK | \ + TPC_DEBUG0_WALKER_CNTL_MASK | \ + TPC_DEBUG0_ALIGNER_CNTL_MASK | \ + TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \ + TPC_DEBUG0_WALKER_STATE_MASK | \ + TPC_DEBUG0_ALIGNER_STATE_MASK | \ + TPC_DEBUG0_REG_CLK_EN_MASK | \ + TPC_DEBUG0_TPC_CLK_EN_MASK | \ + TPC_DEBUG0_SQ_TP_WAKEUP_MASK) + +#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \ + ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \ + (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \ + (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \ + (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \ + (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \ + (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \ + (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \ + (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \ + (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \ + (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)) + +#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int : 1; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 3; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int : 1; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + } tpc_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int : 1; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int : 3; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 1; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + } tpc_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug0_t f; +} tpc_debug0_u; + + +/* + * TPC_DEBUG1 struct + */ + +#define TPC_DEBUG1_UNUSED_SIZE 1 + +#define TPC_DEBUG1_UNUSED_SHIFT 0 + +#define TPC_DEBUG1_UNUSED_MASK 0x00000001 + +#define TPC_DEBUG1_MASK \ + (TPC_DEBUG1_UNUSED_MASK) + +#define TPC_DEBUG1(unused) \ + ((unused << TPC_DEBUG1_UNUSED_SHIFT)) + +#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \ + ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT) + +#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \ + tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + unsigned int : 31; + } tpc_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int : 31; + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + } tpc_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug1_t f; +} tpc_debug1_u; + + +/* + * TPC_CHICKEN struct + */ + +#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1 +#define TPC_CHICKEN_SPARE_SIZE 31 + +#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0 +#define TPC_CHICKEN_SPARE_SHIFT 1 + +#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001 +#define TPC_CHICKEN_SPARE_MASK 0xfffffffe + +#define TPC_CHICKEN_MASK \ + (TPC_CHICKEN_BLEND_PRECISION_MASK | \ + TPC_CHICKEN_SPARE_MASK) + +#define TPC_CHICKEN(blend_precision, spare) \ + ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \ + (spare << TPC_CHICKEN_SPARE_SHIFT)) + +#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT) + +#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + } tpc_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + } tpc_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_chicken_t f; +} tpc_chicken_u; + + +/* + * TP0_CNTL_STATUS struct + */ + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1 +#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TP_BUSY_SIZE 1 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14 +#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16 +#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17 +#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18 +#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19 +#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21 +#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23 +#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25 +#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27 +#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29 +#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30 +#define TP0_CNTL_STATUS_TP_BUSY_SHIFT 31 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200 +#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000 +#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000 +#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000 +#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000 +#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000 +#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000 +#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000 +#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000 +#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000 +#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000 +#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000 +#define TP0_CNTL_STATUS_TP_BUSY_MASK 0x80000000 + +#define TP0_CNTL_STATUS_MASK \ + (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_IN_LC_RTS_MASK | \ + TP0_CNTL_STATUS_LC_LA_RTS_MASK | \ + TP0_CNTL_STATUS_LA_FL_RTS_MASK | \ + TP0_CNTL_STATUS_FL_TA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \ + TP0_CNTL_STATUS_TB_TO_RTS_MASK | \ + TP0_CNTL_STATUS_TP_BUSY_MASK) + +#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \ + ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \ + (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \ + (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \ + (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \ + (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \ + (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \ + (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \ + (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \ + (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \ + (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \ + (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \ + (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \ + (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \ + (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \ + (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \ + (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \ + (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \ + (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \ + (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \ + (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \ + (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \ + (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \ + (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \ + (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \ + (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \ + (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \ + (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \ + (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \ + (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \ + (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \ + (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)) + +#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int : 1; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + } tp0_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int : 1; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + } tp0_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_cntl_status_t f; +} tp0_cntl_status_u; + + +/* + * TP0_DEBUG struct + */ + +#define TP0_DEBUG_Q_LOD_CNTL_SIZE 2 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE 1 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17 +#define TP0_DEBUG_REG_CLK_EN_SIZE 1 +#define TP0_DEBUG_PERF_CLK_EN_SIZE 1 +#define TP0_DEBUG_TP_CLK_EN_SIZE 1 +#define TP0_DEBUG_Q_WALKER_CNTL_SIZE 4 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE 3 + +#define TP0_DEBUG_Q_LOD_CNTL_SHIFT 0 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4 +#define TP0_DEBUG_REG_CLK_EN_SHIFT 21 +#define TP0_DEBUG_PERF_CLK_EN_SHIFT 22 +#define TP0_DEBUG_TP_CLK_EN_SHIFT 23 +#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT 24 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28 + +#define TP0_DEBUG_Q_LOD_CNTL_MASK 0x00000003 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK 0x00000008 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0 +#define TP0_DEBUG_REG_CLK_EN_MASK 0x00200000 +#define TP0_DEBUG_PERF_CLK_EN_MASK 0x00400000 +#define TP0_DEBUG_TP_CLK_EN_MASK 0x00800000 +#define TP0_DEBUG_Q_WALKER_CNTL_MASK 0x0f000000 +#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK 0x70000000 + +#define TP0_DEBUG_MASK \ + (TP0_DEBUG_Q_LOD_CNTL_MASK | \ + TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \ + TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \ + TP0_DEBUG_REG_CLK_EN_MASK | \ + TP0_DEBUG_PERF_CLK_EN_MASK | \ + TP0_DEBUG_TP_CLK_EN_MASK | \ + TP0_DEBUG_Q_WALKER_CNTL_MASK | \ + TP0_DEBUG_Q_ALIGNER_CNTL_MASK) + +#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \ + ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \ + (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \ + (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \ + (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \ + (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \ + (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \ + (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \ + (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)) + +#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + unsigned int : 1; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int : 1; + } tp0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int : 1; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int : 1; + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + } tp0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_debug_t f; +} tp0_debug_u; + + +/* + * TP0_CHICKEN struct + */ + +#define TP0_CHICKEN_TT_MODE_SIZE 1 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1 +#define TP0_CHICKEN_SPARE_SIZE 30 + +#define TP0_CHICKEN_TT_MODE_SHIFT 0 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1 +#define TP0_CHICKEN_SPARE_SHIFT 2 + +#define TP0_CHICKEN_TT_MODE_MASK 0x00000001 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002 +#define TP0_CHICKEN_SPARE_MASK 0xfffffffc + +#define TP0_CHICKEN_MASK \ + (TP0_CHICKEN_TT_MODE_MASK | \ + TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \ + TP0_CHICKEN_SPARE_MASK) + +#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \ + ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \ + (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \ + (spare << TP0_CHICKEN_SPARE_SHIFT)) + +#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT) + +#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + } tp0_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + } tp0_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_chicken_t f; +} tp0_chicken_u; + + +/* + * TP0_PERFCOUNTER0_SELECT struct + */ + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER0_SELECT_MASK \ + (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \ + ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \ + tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_select_t f; +} tp0_perfcounter0_select_u; + + +/* + * TP0_PERFCOUNTER0_HI struct + */ + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER0_HI_MASK \ + (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \ + ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \ + tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_hi_t f; +} tp0_perfcounter0_hi_u; + + +/* + * TP0_PERFCOUNTER0_LOW struct + */ + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER0_LOW_MASK \ + (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \ + ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \ + tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_low_t f; +} tp0_perfcounter0_low_u; + + +/* + * TP0_PERFCOUNTER1_SELECT struct + */ + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER1_SELECT_MASK \ + (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \ + ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \ + tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_select_t f; +} tp0_perfcounter1_select_u; + + +/* + * TP0_PERFCOUNTER1_HI struct + */ + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER1_HI_MASK \ + (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \ + ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \ + tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_hi_t f; +} tp0_perfcounter1_hi_u; + + +/* + * TP0_PERFCOUNTER1_LOW struct + */ + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER1_LOW_MASK \ + (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \ + ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \ + tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_low_t f; +} tp0_perfcounter1_low_u; + + +/* + * TCM_PERFCOUNTER0_SELECT struct + */ + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER0_SELECT_MASK \ + (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \ + ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \ + tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_select_t f; +} tcm_perfcounter0_select_u; + + +/* + * TCM_PERFCOUNTER1_SELECT struct + */ + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER1_SELECT_MASK \ + (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \ + ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \ + tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_select_t f; +} tcm_perfcounter1_select_u; + + +/* + * TCM_PERFCOUNTER0_HI struct + */ + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER0_HI_MASK \ + (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \ + ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \ + tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_hi_t f; +} tcm_perfcounter0_hi_u; + + +/* + * TCM_PERFCOUNTER1_HI struct + */ + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER1_HI_MASK \ + (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \ + ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \ + tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_hi_t f; +} tcm_perfcounter1_hi_u; + + +/* + * TCM_PERFCOUNTER0_LOW struct + */ + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER0_LOW_MASK \ + (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \ + ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \ + tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_low_t f; +} tcm_perfcounter0_low_u; + + +/* + * TCM_PERFCOUNTER1_LOW struct + */ + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER1_LOW_MASK \ + (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \ + ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \ + tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_low_t f; +} tcm_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER0_SELECT struct + */ + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER0_SELECT_MASK \ + (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \ + ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \ + tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_select_t f; +} tcf_perfcounter0_select_u; + + +/* + * TCF_PERFCOUNTER1_SELECT struct + */ + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER1_SELECT_MASK \ + (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \ + ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \ + tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_select_t f; +} tcf_perfcounter1_select_u; + + +/* + * TCF_PERFCOUNTER2_SELECT struct + */ + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER2_SELECT_MASK \ + (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \ + ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \ + tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_select_t f; +} tcf_perfcounter2_select_u; + + +/* + * TCF_PERFCOUNTER3_SELECT struct + */ + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER3_SELECT_MASK \ + (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \ + ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \ + tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_select_t f; +} tcf_perfcounter3_select_u; + + +/* + * TCF_PERFCOUNTER4_SELECT struct + */ + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER4_SELECT_MASK \ + (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \ + ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \ + tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter4_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter4_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_select_t f; +} tcf_perfcounter4_select_u; + + +/* + * TCF_PERFCOUNTER5_SELECT struct + */ + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER5_SELECT_MASK \ + (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \ + ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \ + tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter5_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter5_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_select_t f; +} tcf_perfcounter5_select_u; + + +/* + * TCF_PERFCOUNTER6_SELECT struct + */ + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER6_SELECT_MASK \ + (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \ + ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \ + tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter6_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter6_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_select_t f; +} tcf_perfcounter6_select_u; + + +/* + * TCF_PERFCOUNTER7_SELECT struct + */ + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER7_SELECT_MASK \ + (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \ + ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \ + tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter7_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter7_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_select_t f; +} tcf_perfcounter7_select_u; + + +/* + * TCF_PERFCOUNTER8_SELECT struct + */ + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER8_SELECT_MASK \ + (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \ + ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \ + tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter8_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter8_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_select_t f; +} tcf_perfcounter8_select_u; + + +/* + * TCF_PERFCOUNTER9_SELECT struct + */ + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER9_SELECT_MASK \ + (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \ + ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \ + tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter9_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter9_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_select_t f; +} tcf_perfcounter9_select_u; + + +/* + * TCF_PERFCOUNTER10_SELECT struct + */ + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER10_SELECT_MASK \ + (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \ + ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \ + tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter10_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter10_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_select_t f; +} tcf_perfcounter10_select_u; + + +/* + * TCF_PERFCOUNTER11_SELECT struct + */ + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER11_SELECT_MASK \ + (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \ + ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \ + tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter11_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter11_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_select_t f; +} tcf_perfcounter11_select_u; + + +/* + * TCF_PERFCOUNTER0_HI struct + */ + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER0_HI_MASK \ + (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \ + ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \ + tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_hi_t f; +} tcf_perfcounter0_hi_u; + + +/* + * TCF_PERFCOUNTER1_HI struct + */ + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER1_HI_MASK \ + (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \ + ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \ + tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_hi_t f; +} tcf_perfcounter1_hi_u; + + +/* + * TCF_PERFCOUNTER2_HI struct + */ + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER2_HI_MASK \ + (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \ + ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \ + tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_hi_t f; +} tcf_perfcounter2_hi_u; + + +/* + * TCF_PERFCOUNTER3_HI struct + */ + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER3_HI_MASK \ + (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \ + ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \ + tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_hi_t f; +} tcf_perfcounter3_hi_u; + + +/* + * TCF_PERFCOUNTER4_HI struct + */ + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER4_HI_MASK \ + (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \ + ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \ + tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter4_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter4_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_hi_t f; +} tcf_perfcounter4_hi_u; + + +/* + * TCF_PERFCOUNTER5_HI struct + */ + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER5_HI_MASK \ + (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \ + ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \ + tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter5_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter5_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_hi_t f; +} tcf_perfcounter5_hi_u; + + +/* + * TCF_PERFCOUNTER6_HI struct + */ + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER6_HI_MASK \ + (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \ + ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \ + tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter6_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter6_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_hi_t f; +} tcf_perfcounter6_hi_u; + + +/* + * TCF_PERFCOUNTER7_HI struct + */ + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER7_HI_MASK \ + (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \ + ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \ + tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter7_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter7_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_hi_t f; +} tcf_perfcounter7_hi_u; + + +/* + * TCF_PERFCOUNTER8_HI struct + */ + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER8_HI_MASK \ + (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \ + ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \ + tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter8_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter8_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_hi_t f; +} tcf_perfcounter8_hi_u; + + +/* + * TCF_PERFCOUNTER9_HI struct + */ + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER9_HI_MASK \ + (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \ + ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \ + tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter9_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter9_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_hi_t f; +} tcf_perfcounter9_hi_u; + + +/* + * TCF_PERFCOUNTER10_HI struct + */ + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER10_HI_MASK \ + (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \ + ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \ + tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter10_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter10_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_hi_t f; +} tcf_perfcounter10_hi_u; + + +/* + * TCF_PERFCOUNTER11_HI struct + */ + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER11_HI_MASK \ + (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \ + ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \ + tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter11_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter11_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_hi_t f; +} tcf_perfcounter11_hi_u; + + +/* + * TCF_PERFCOUNTER0_LOW struct + */ + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER0_LOW_MASK \ + (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \ + ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \ + tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_low_t f; +} tcf_perfcounter0_low_u; + + +/* + * TCF_PERFCOUNTER1_LOW struct + */ + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER1_LOW_MASK \ + (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \ + ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \ + tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_low_t f; +} tcf_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER2_LOW struct + */ + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER2_LOW_MASK \ + (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \ + ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \ + tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_low_t f; +} tcf_perfcounter2_low_u; + + +/* + * TCF_PERFCOUNTER3_LOW struct + */ + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER3_LOW_MASK \ + (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \ + ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \ + tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_low_t f; +} tcf_perfcounter3_low_u; + + +/* + * TCF_PERFCOUNTER4_LOW struct + */ + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER4_LOW_MASK \ + (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \ + ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \ + tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_low_t f; +} tcf_perfcounter4_low_u; + + +/* + * TCF_PERFCOUNTER5_LOW struct + */ + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER5_LOW_MASK \ + (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \ + ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \ + tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_low_t f; +} tcf_perfcounter5_low_u; + + +/* + * TCF_PERFCOUNTER6_LOW struct + */ + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER6_LOW_MASK \ + (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \ + ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \ + tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_low_t f; +} tcf_perfcounter6_low_u; + + +/* + * TCF_PERFCOUNTER7_LOW struct + */ + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER7_LOW_MASK \ + (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \ + ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \ + tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_low_t f; +} tcf_perfcounter7_low_u; + + +/* + * TCF_PERFCOUNTER8_LOW struct + */ + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER8_LOW_MASK \ + (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \ + ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \ + tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_low_t f; +} tcf_perfcounter8_low_u; + + +/* + * TCF_PERFCOUNTER9_LOW struct + */ + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER9_LOW_MASK \ + (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \ + ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \ + tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_low_t f; +} tcf_perfcounter9_low_u; + + +/* + * TCF_PERFCOUNTER10_LOW struct + */ + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER10_LOW_MASK \ + (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \ + ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \ + tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_low_t f; +} tcf_perfcounter10_low_u; + + +/* + * TCF_PERFCOUNTER11_LOW struct + */ + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER11_LOW_MASK \ + (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \ + ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \ + tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_low_t f; +} tcf_perfcounter11_low_u; + + +/* + * TCF_DEBUG struct + */ + +#define TCF_DEBUG_not_MH_TC_rtr_SIZE 1 +#define TCF_DEBUG_TC_MH_send_SIZE 1 +#define TCF_DEBUG_not_FG0_rtr_SIZE 1 +#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1 +#define TCF_DEBUG_TCB_ff_stall_SIZE 1 +#define TCF_DEBUG_TCB_miss_stall_SIZE 1 +#define TCF_DEBUG_TCA_TCB_stall_SIZE 1 +#define TCF_DEBUG_PF0_stall_SIZE 1 +#define TCF_DEBUG_TP0_full_SIZE 1 +#define TCF_DEBUG_TPC_full_SIZE 1 +#define TCF_DEBUG_not_TPC_rtr_SIZE 1 +#define TCF_DEBUG_tca_state_rts_SIZE 1 +#define TCF_DEBUG_tca_rts_SIZE 1 + +#define TCF_DEBUG_not_MH_TC_rtr_SHIFT 6 +#define TCF_DEBUG_TC_MH_send_SHIFT 7 +#define TCF_DEBUG_not_FG0_rtr_SHIFT 8 +#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12 +#define TCF_DEBUG_TCB_ff_stall_SHIFT 13 +#define TCF_DEBUG_TCB_miss_stall_SHIFT 14 +#define TCF_DEBUG_TCA_TCB_stall_SHIFT 15 +#define TCF_DEBUG_PF0_stall_SHIFT 16 +#define TCF_DEBUG_TP0_full_SHIFT 20 +#define TCF_DEBUG_TPC_full_SHIFT 24 +#define TCF_DEBUG_not_TPC_rtr_SHIFT 25 +#define TCF_DEBUG_tca_state_rts_SHIFT 26 +#define TCF_DEBUG_tca_rts_SHIFT 27 + +#define TCF_DEBUG_not_MH_TC_rtr_MASK 0x00000040 +#define TCF_DEBUG_TC_MH_send_MASK 0x00000080 +#define TCF_DEBUG_not_FG0_rtr_MASK 0x00000100 +#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000 +#define TCF_DEBUG_TCB_ff_stall_MASK 0x00002000 +#define TCF_DEBUG_TCB_miss_stall_MASK 0x00004000 +#define TCF_DEBUG_TCA_TCB_stall_MASK 0x00008000 +#define TCF_DEBUG_PF0_stall_MASK 0x00010000 +#define TCF_DEBUG_TP0_full_MASK 0x00100000 +#define TCF_DEBUG_TPC_full_MASK 0x01000000 +#define TCF_DEBUG_not_TPC_rtr_MASK 0x02000000 +#define TCF_DEBUG_tca_state_rts_MASK 0x04000000 +#define TCF_DEBUG_tca_rts_MASK 0x08000000 + +#define TCF_DEBUG_MASK \ + (TCF_DEBUG_not_MH_TC_rtr_MASK | \ + TCF_DEBUG_TC_MH_send_MASK | \ + TCF_DEBUG_not_FG0_rtr_MASK | \ + TCF_DEBUG_not_TCB_TCO_rtr_MASK | \ + TCF_DEBUG_TCB_ff_stall_MASK | \ + TCF_DEBUG_TCB_miss_stall_MASK | \ + TCF_DEBUG_TCA_TCB_stall_MASK | \ + TCF_DEBUG_PF0_stall_MASK | \ + TCF_DEBUG_TP0_full_MASK | \ + TCF_DEBUG_TPC_full_MASK | \ + TCF_DEBUG_not_TPC_rtr_MASK | \ + TCF_DEBUG_tca_state_rts_MASK | \ + TCF_DEBUG_tca_rts_MASK) + +#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \ + ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \ + (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \ + (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \ + (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \ + (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \ + (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \ + (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \ + (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \ + (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \ + (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \ + (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \ + (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \ + (tca_rts << TCF_DEBUG_tca_rts_SHIFT)) + +#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_GET_TP0_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_GET_TPC_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_GET_tca_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT) + +#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 6; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int : 3; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int : 4; + } tcf_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 4; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int : 3; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int : 6; + } tcf_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_debug_t f; +} tcf_debug_u; + + +/* + * TCA_FIFO_DEBUG struct + */ + +#define TCA_FIFO_DEBUG_tp0_full_SIZE 1 +#define TCA_FIFO_DEBUG_tpc_full_SIZE 1 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1 +#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1 +#define TCA_FIFO_DEBUG_FW_full_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1 +#define TCA_FIFO_DEBUG_FW_rts0_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1 + +#define TCA_FIFO_DEBUG_tp0_full_SHIFT 0 +#define TCA_FIFO_DEBUG_tpc_full_SHIFT 4 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5 +#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6 +#define TCA_FIFO_DEBUG_FW_full_SHIFT 7 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8 +#define TCA_FIFO_DEBUG_FW_rts0_SHIFT 12 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17 + +#define TCA_FIFO_DEBUG_tp0_full_MASK 0x00000001 +#define TCA_FIFO_DEBUG_tpc_full_MASK 0x00000010 +#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020 +#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040 +#define TCA_FIFO_DEBUG_FW_full_MASK 0x00000080 +#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100 +#define TCA_FIFO_DEBUG_FW_rts0_MASK 0x00001000 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000 +#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000 + +#define TCA_FIFO_DEBUG_MASK \ + (TCA_FIFO_DEBUG_tp0_full_MASK | \ + TCA_FIFO_DEBUG_tpc_full_MASK | \ + TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \ + TCA_FIFO_DEBUG_load_tp_fifos_MASK | \ + TCA_FIFO_DEBUG_FW_full_MASK | \ + TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \ + TCA_FIFO_DEBUG_FW_rts0_MASK | \ + TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \ + TCA_FIFO_DEBUG_FW_tpc_rts_MASK) + +#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \ + ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \ + (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \ + (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \ + (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \ + (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \ + (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \ + (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \ + (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \ + (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)) + +#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int : 14; + } tca_fifo_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int : 14; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + } tca_fifo_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_fifo_debug_t f; +} tca_fifo_debug_u; + + +/* + * TCA_PROBE_DEBUG struct + */ + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001 + +#define TCA_PROBE_DEBUG_MASK \ + (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) + +#define TCA_PROBE_DEBUG(probefilter_stall) \ + ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)) + +#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \ + ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \ + tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + unsigned int : 31; + } tca_probe_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int : 31; + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + } tca_probe_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_probe_debug_t f; +} tca_probe_debug_u; + + +/* + * TCA_TPC_DEBUG struct + */ + +#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1 +#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1 + +#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12 +#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13 + +#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000 +#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000 + +#define TCA_TPC_DEBUG_MASK \ + (TCA_TPC_DEBUG_captue_state_rts_MASK | \ + TCA_TPC_DEBUG_capture_tca_rts_MASK) + +#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \ + ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \ + (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)) + +#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 12; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int : 18; + } tca_tpc_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 18; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int : 12; + } tca_tpc_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_tpc_debug_t f; +} tca_tpc_debug_u; + + +/* + * TCB_CORE_DEBUG struct + */ + +#define TCB_CORE_DEBUG_access512_SIZE 1 +#define TCB_CORE_DEBUG_tiled_SIZE 1 +#define TCB_CORE_DEBUG_opcode_SIZE 3 +#define TCB_CORE_DEBUG_format_SIZE 6 +#define TCB_CORE_DEBUG_sector_format_SIZE 5 +#define TCB_CORE_DEBUG_sector_format512_SIZE 3 + +#define TCB_CORE_DEBUG_access512_SHIFT 0 +#define TCB_CORE_DEBUG_tiled_SHIFT 1 +#define TCB_CORE_DEBUG_opcode_SHIFT 4 +#define TCB_CORE_DEBUG_format_SHIFT 8 +#define TCB_CORE_DEBUG_sector_format_SHIFT 16 +#define TCB_CORE_DEBUG_sector_format512_SHIFT 24 + +#define TCB_CORE_DEBUG_access512_MASK 0x00000001 +#define TCB_CORE_DEBUG_tiled_MASK 0x00000002 +#define TCB_CORE_DEBUG_opcode_MASK 0x00000070 +#define TCB_CORE_DEBUG_format_MASK 0x00003f00 +#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000 +#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000 + +#define TCB_CORE_DEBUG_MASK \ + (TCB_CORE_DEBUG_access512_MASK | \ + TCB_CORE_DEBUG_tiled_MASK | \ + TCB_CORE_DEBUG_opcode_MASK | \ + TCB_CORE_DEBUG_format_MASK | \ + TCB_CORE_DEBUG_sector_format_MASK | \ + TCB_CORE_DEBUG_sector_format512_MASK) + +#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \ + ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \ + (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \ + (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \ + (format << TCB_CORE_DEBUG_format_SHIFT) | \ + (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \ + (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)) + +#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT) + +#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int : 2; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 1; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 2; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 3; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 5; + } tcb_core_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int : 5; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 3; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 2; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 1; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 2; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + } tcb_core_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_core_debug_t f; +} tcb_core_debug_u; + + +/* + * TCB_TAG0_DEBUG struct + */ + +#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG0_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG0_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG0_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG0_DEBUG_MASK \ + (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG0_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG0_DEBUG_miss_stall_MASK | \ + TCB_TAG0_DEBUG_num_feee_lines_MASK | \ + TCB_TAG0_DEBUG_max_misses_MASK) + +#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT) + +#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + } tcb_tag0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + } tcb_tag0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag0_debug_t f; +} tcb_tag0_debug_u; + + +/* + * TCB_TAG1_DEBUG struct + */ + +#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG1_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG1_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG1_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG1_DEBUG_MASK \ + (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG1_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG1_DEBUG_miss_stall_MASK | \ + TCB_TAG1_DEBUG_num_feee_lines_MASK | \ + TCB_TAG1_DEBUG_max_misses_MASK) + +#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT) + +#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + } tcb_tag1_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + } tcb_tag1_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag1_debug_t f; +} tcb_tag1_debug_u; + + +/* + * TCB_TAG2_DEBUG struct + */ + +#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG2_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG2_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG2_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG2_DEBUG_MASK \ + (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG2_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG2_DEBUG_miss_stall_MASK | \ + TCB_TAG2_DEBUG_num_feee_lines_MASK | \ + TCB_TAG2_DEBUG_max_misses_MASK) + +#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT) + +#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + } tcb_tag2_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + } tcb_tag2_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag2_debug_t f; +} tcb_tag2_debug_u; + + +/* + * TCB_TAG3_DEBUG struct + */ + +#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG3_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG3_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG3_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG3_DEBUG_MASK \ + (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG3_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG3_DEBUG_miss_stall_MASK | \ + TCB_TAG3_DEBUG_num_feee_lines_MASK | \ + TCB_TAG3_DEBUG_max_misses_MASK) + +#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT) + +#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + } tcb_tag3_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + } tcb_tag3_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag3_debug_t f; +} tcb_tag3_debug_u; + + +/* + * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct + */ + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \ + (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \ + ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \ + (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \ + (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \ + (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \ + (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \ + (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \ + (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \ + (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int : 3; + } tcb_fetch_gen_sector_walker0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int : 3; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + } tcb_fetch_gen_sector_walker0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_sector_walker0_debug_t f; +} tcb_fetch_gen_sector_walker0_debug_u; + + +/* + * TCB_FETCH_GEN_WALKER_DEBUG struct + */ + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000 + +#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \ + (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) + +#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \ + ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \ + (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \ + (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \ + (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \ + (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \ + (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)) + +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 4; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int : 3; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int : 12; + } tcb_fetch_gen_walker_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 12; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int : 3; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int : 4; + } tcb_fetch_gen_walker_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_walker_debug_t f; +} tcb_fetch_gen_walker_debug_u; + + +/* + * TCB_FETCH_GEN_PIPE0_DEBUG struct + */ + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \ + (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) + +#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \ + ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \ + (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \ + (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \ + (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \ + (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \ + (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \ + (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \ + (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \ + (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \ + (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \ + (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + } tcb_fetch_gen_pipe0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + } tcb_fetch_gen_pipe0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_pipe0_debug_t f; +} tcb_fetch_gen_pipe0_debug_u; + + +/* + * TCD_INPUT0_DEBUG struct + */ + +#define TCD_INPUT0_DEBUG_empty_SIZE 1 +#define TCD_INPUT0_DEBUG_full_SIZE 1 +#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_cnt_q1_SIZE 2 +#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_ip_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1 + +#define TCD_INPUT0_DEBUG_empty_SHIFT 16 +#define TCD_INPUT0_DEBUG_full_SHIFT 17 +#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20 +#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT 21 +#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23 +#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26 + +#define TCD_INPUT0_DEBUG_empty_MASK 0x00010000 +#define TCD_INPUT0_DEBUG_full_MASK 0x00020000 +#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000 +#define TCD_INPUT0_DEBUG_cnt_q1_MASK 0x00600000 +#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000 +#define TCD_INPUT0_DEBUG_ip_send_MASK 0x01000000 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000 +#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000 + +#define TCD_INPUT0_DEBUG_MASK \ + (TCD_INPUT0_DEBUG_empty_MASK | \ + TCD_INPUT0_DEBUG_full_MASK | \ + TCD_INPUT0_DEBUG_valid_q1_MASK | \ + TCD_INPUT0_DEBUG_cnt_q1_MASK | \ + TCD_INPUT0_DEBUG_last_send_q1_MASK | \ + TCD_INPUT0_DEBUG_ip_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_busy_MASK) + +#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \ + ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \ + (full << TCD_INPUT0_DEBUG_full_SHIFT) | \ + (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \ + (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \ + (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \ + (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \ + (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \ + (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)) + +#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 16; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int : 2; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int : 5; + } tcd_input0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 5; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int : 2; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int : 16; + } tcd_input0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_input0_debug_t f; +} tcd_input0_debug_u; + + +/* + * TCD_DEGAMMA_DEBUG struct + */ + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040 + +#define TCD_DEGAMMA_DEBUG_MASK \ + (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) + +#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \ + ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \ + (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \ + (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \ + (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \ + (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \ + (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)) + +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int : 25; + } tcd_degamma_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int : 25; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + } tcd_degamma_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_degamma_debug_t f; +} tcd_degamma_debug_u; + + +/* + * TCD_DXTMUX_SCTARB_DEBUG struct + */ + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000 + +#define TCD_DXTMUX_SCTARB_DEBUG_MASK \ + (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) + +#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \ + ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \ + (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \ + (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \ + (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \ + (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \ + (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \ + (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \ + (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \ + (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)) + +#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 9; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int : 2; + } tcd_dxtmux_sctarb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 2; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int : 3; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int : 9; + } tcd_dxtmux_sctarb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtmux_sctarb_debug_t f; +} tcd_dxtmux_sctarb_debug_u; + + +/* + * TCD_DXTC_ARB_DEBUG struct + */ + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4 +#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010 +#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000 + +#define TCD_DXTC_ARB_DEBUG_MASK \ + (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \ + TCD_DXTC_ARB_DEBUG_pstate_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \ + TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) + +#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \ + ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \ + (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \ + (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \ + (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \ + (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \ + (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \ + (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \ + (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \ + (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)) + +#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int : 4; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + } tcd_dxtc_arb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int : 4; + } tcd_dxtc_arb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtc_arb_debug_t f; +} tcd_dxtc_arb_debug_u; + + +/* + * TCD_STALLS_DEBUG struct + */ + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000 +#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000 + +#define TCD_STALLS_DEBUG_MASK \ + (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \ + TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \ + TCD_STALLS_DEBUG_not_incoming_rtr_MASK) + +#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \ + ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \ + (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \ + (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \ + (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \ + (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \ + (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)) + +#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int : 11; + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + } tcd_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int : 10; + } tcd_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_stalls_debug_t f; +} tcd_stalls_debug_u; + + +/* + * TCO_STALLS_DEBUG struct + */ + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080 + +#define TCO_STALLS_DEBUG_MASK \ + (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) + +#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \ + ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \ + (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \ + (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)) + +#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 5; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int : 24; + } tco_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 24; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int : 5; + } tco_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_stalls_debug_t f; +} tco_stalls_debug_u; + + +/* + * TCO_QUAD0_DEBUG0 struct + */ + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1 +#define TCO_QUAD0_DEBUG0_busy_SIZE 1 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16 +#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29 +#define TCO_QUAD0_DEBUG0_busy_SHIFT 30 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000 +#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000 +#define TCO_QUAD0_DEBUG0_busy_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG0_MASK \ + (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \ + TCO_QUAD0_DEBUG0_read_cache_q_MASK | \ + TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \ + TCO_QUAD0_DEBUG0_busy_MASK) + +#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \ + ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \ + (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \ + (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \ + (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \ + (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \ + (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \ + (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \ + (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \ + (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \ + (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \ + (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)) + +#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT) + +#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int : 2; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 7; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int : 1; + } tco_quad0_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int : 1; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int : 7; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 2; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + } tco_quad0_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug0_t f; +} tco_quad0_debug0_u; + + +/* + * TCO_QUAD0_DEBUG1 struct + */ + +#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_empty_SIZE 1 +#define TCO_QUAD0_DEBUG1_full_SIZE 1 +#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1 + +#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0 +#define TCO_QUAD0_DEBUG1_empty_SHIFT 1 +#define TCO_QUAD0_DEBUG1_full_SHIFT 2 +#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30 + +#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001 +#define TCO_QUAD0_DEBUG1_empty_MASK 0x00000002 +#define TCO_QUAD0_DEBUG1_full_MASK 0x00000004 +#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800 +#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000 +#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG1_MASK \ + (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_empty_MASK | \ + TCO_QUAD0_DEBUG1_full_MASK | \ + TCO_QUAD0_DEBUG1_write_enable_MASK | \ + TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \ + TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \ + TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \ + TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \ + TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) + +#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \ + ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \ + (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \ + (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \ + (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \ + (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \ + (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \ + (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \ + (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \ + (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \ + (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \ + (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \ + (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \ + (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)) + +#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int : 2; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int : 1; + } tco_quad0_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int : 1; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int : 2; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + } tco_quad0_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug1_t f; +} tco_quad0_debug1_u; + + +#endif + + +#if !defined (_TC_FIDDLE_H) +#define _TC_FIDDLE_H + +/***************************************************************************************************************** + * + * tc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_SC_FIDDLE_H) +#define _SC_FIDDLE_H + +/***************************************************************************************************************** + * + * sc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_BC_FIDDLE_H) +#define _BC_FIDDLE_H + +/***************************************************************************************************************** + * + * bc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * RB_SURFACE_INFO struct + */ + +#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2 + +#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14 + +#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff +#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000 + +#define RB_SURFACE_INFO_MASK \ + (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \ + RB_SURFACE_INFO_MSAA_SAMPLES_MASK) + +#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \ + ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \ + (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)) + +#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int : 16; + } rb_surface_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int : 16; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + } rb_surface_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_surface_info_t f; +} rb_surface_info_u; + + +/* + * RB_COLOR_INFO struct + */ + +#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2 +#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1 +#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2 +#define RB_COLOR_INFO_COLOR_SWAP_SIZE 2 +#define RB_COLOR_INFO_COLOR_BASE_SIZE 20 + +#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4 +#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6 +#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7 +#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9 +#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12 + +#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f +#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030 +#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040 +#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180 +#define RB_COLOR_INFO_COLOR_SWAP_MASK 0x00000600 +#define RB_COLOR_INFO_COLOR_BASE_MASK 0xfffff000 + +#define RB_COLOR_INFO_MASK \ + (RB_COLOR_INFO_COLOR_FORMAT_MASK | \ + RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \ + RB_COLOR_INFO_COLOR_LINEAR_MASK | \ + RB_COLOR_INFO_COLOR_ENDIAN_MASK | \ + RB_COLOR_INFO_COLOR_SWAP_MASK | \ + RB_COLOR_INFO_COLOR_BASE_MASK) + +#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \ + ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \ + (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \ + (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \ + (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \ + (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \ + (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)) + +#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int : 1; + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + } rb_color_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + unsigned int : 1; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + } rb_color_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_info_t f; +} rb_color_info_u; + + +/* + * RB_DEPTH_INFO struct + */ + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1 +#define RB_DEPTH_INFO_DEPTH_BASE_SIZE 20 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0 +#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001 +#define RB_DEPTH_INFO_DEPTH_BASE_MASK 0xfffff000 + +#define RB_DEPTH_INFO_MASK \ + (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \ + RB_DEPTH_INFO_DEPTH_BASE_MASK) + +#define RB_DEPTH_INFO(depth_format, depth_base) \ + ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \ + (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)) + +#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + unsigned int : 11; + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + } rb_depth_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + unsigned int : 11; + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + } rb_depth_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_info_t f; +} rb_depth_info_u; + + +/* + * RB_STENCILREFMASK struct + */ + +#define RB_STENCILREFMASK_STENCILREF_SIZE 8 +#define RB_STENCILREFMASK_STENCILMASK_SIZE 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8 + +#define RB_STENCILREFMASK_STENCILREF_SHIFT 0 +#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16 + +#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff +#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00 +#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000 + +#define RB_STENCILREFMASK_MASK \ + (RB_STENCILREFMASK_STENCILREF_MASK | \ + RB_STENCILREFMASK_STENCILMASK_MASK | \ + RB_STENCILREFMASK_STENCILWRITEMASK_MASK) + +#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask) \ + ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \ + (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \ + (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)) + +#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) + +#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int : 8; + } rb_stencilrefmask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int : 8; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + } rb_stencilrefmask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_t f; +} rb_stencilrefmask_u; + + +/* + * RB_ALPHA_REF struct + */ + +#define RB_ALPHA_REF_ALPHA_REF_SIZE 32 + +#define RB_ALPHA_REF_ALPHA_REF_SHIFT 0 + +#define RB_ALPHA_REF_ALPHA_REF_MASK 0xffffffff + +#define RB_ALPHA_REF_MASK \ + (RB_ALPHA_REF_ALPHA_REF_MASK) + +#define RB_ALPHA_REF(alpha_ref) \ + ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)) + +#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \ + ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \ + rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_alpha_ref_t f; +} rb_alpha_ref_u; + + +/* + * RB_COLOR_MASK struct + */ + +#define RB_COLOR_MASK_WRITE_RED_SIZE 1 +#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1 +#define RB_COLOR_MASK_WRITE_BLUE_SIZE 1 +#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COLOR_MASK_WRITE_RED_SHIFT 0 +#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1 +#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2 +#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3 + +#define RB_COLOR_MASK_WRITE_RED_MASK 0x00000001 +#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002 +#define RB_COLOR_MASK_WRITE_BLUE_MASK 0x00000004 +#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008 + +#define RB_COLOR_MASK_MASK \ + (RB_COLOR_MASK_WRITE_RED_MASK | \ + RB_COLOR_MASK_WRITE_GREEN_MASK | \ + RB_COLOR_MASK_WRITE_BLUE_MASK | \ + RB_COLOR_MASK_WRITE_ALPHA_MASK) + +#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha) \ + ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \ + (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \ + (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \ + (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int : 28; + } rb_color_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int : 28; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + } rb_color_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_mask_t f; +} rb_color_mask_u; + + +/* + * RB_BLEND_RED struct + */ + +#define RB_BLEND_RED_BLEND_RED_SIZE 8 + +#define RB_BLEND_RED_BLEND_RED_SHIFT 0 + +#define RB_BLEND_RED_BLEND_RED_MASK 0x000000ff + +#define RB_BLEND_RED_MASK \ + (RB_BLEND_RED_BLEND_RED_MASK) + +#define RB_BLEND_RED(blend_red) \ + ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)) + +#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \ + ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT) + +#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \ + rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + unsigned int : 24; + } rb_blend_red_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int : 24; + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + } rb_blend_red_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_red_t f; +} rb_blend_red_u; + + +/* + * RB_BLEND_GREEN struct + */ + +#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8 + +#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0 + +#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff + +#define RB_BLEND_GREEN_MASK \ + (RB_BLEND_GREEN_BLEND_GREEN_MASK) + +#define RB_BLEND_GREEN(blend_green) \ + ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)) + +#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \ + ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \ + rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + unsigned int : 24; + } rb_blend_green_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int : 24; + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + } rb_blend_green_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_green_t f; +} rb_blend_green_u; + + +/* + * RB_BLEND_BLUE struct + */ + +#define RB_BLEND_BLUE_BLEND_BLUE_SIZE 8 + +#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0 + +#define RB_BLEND_BLUE_BLEND_BLUE_MASK 0x000000ff + +#define RB_BLEND_BLUE_MASK \ + (RB_BLEND_BLUE_BLEND_BLUE_MASK) + +#define RB_BLEND_BLUE(blend_blue) \ + ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)) + +#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \ + ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \ + rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + unsigned int : 24; + } rb_blend_blue_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int : 24; + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + } rb_blend_blue_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_blue_t f; +} rb_blend_blue_u; + + +/* + * RB_BLEND_ALPHA struct + */ + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff + +#define RB_BLEND_ALPHA_MASK \ + (RB_BLEND_ALPHA_BLEND_ALPHA_MASK) + +#define RB_BLEND_ALPHA(blend_alpha) \ + ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)) + +#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \ + ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \ + rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + unsigned int : 24; + } rb_blend_alpha_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int : 24; + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + } rb_blend_alpha_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_alpha_t f; +} rb_blend_alpha_u; + + +/* + * RB_FOG_COLOR struct + */ + +#define RB_FOG_COLOR_FOG_RED_SIZE 8 +#define RB_FOG_COLOR_FOG_GREEN_SIZE 8 +#define RB_FOG_COLOR_FOG_BLUE_SIZE 8 + +#define RB_FOG_COLOR_FOG_RED_SHIFT 0 +#define RB_FOG_COLOR_FOG_GREEN_SHIFT 8 +#define RB_FOG_COLOR_FOG_BLUE_SHIFT 16 + +#define RB_FOG_COLOR_FOG_RED_MASK 0x000000ff +#define RB_FOG_COLOR_FOG_GREEN_MASK 0x0000ff00 +#define RB_FOG_COLOR_FOG_BLUE_MASK 0x00ff0000 + +#define RB_FOG_COLOR_MASK \ + (RB_FOG_COLOR_FOG_RED_MASK | \ + RB_FOG_COLOR_FOG_GREEN_MASK | \ + RB_FOG_COLOR_FOG_BLUE_MASK) + +#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \ + ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \ + (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \ + (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)) + +#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int : 8; + } rb_fog_color_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int : 8; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + } rb_fog_color_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_fog_color_t f; +} rb_fog_color_u; + + +/* + * RB_STENCILREFMASK_BF struct + */ + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000 + +#define RB_STENCILREFMASK_BF_MASK \ + (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) + +#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf) \ + ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \ + (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \ + (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)) + +#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) + +#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int : 8; + } rb_stencilrefmask_bf_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int : 8; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + } rb_stencilrefmask_bf_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_bf_t f; +} rb_stencilrefmask_bf_u; + + +/* + * RB_DEPTHCONTROL struct + */ + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_ZFUNC_SIZE 3 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0 +#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3 +#define RB_DEPTHCONTROL_ZFUNC_SHIFT 4 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7 +#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8 +#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11 +#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14 +#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001 +#define RB_DEPTHCONTROL_Z_ENABLE_MASK 0x00000002 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008 +#define RB_DEPTHCONTROL_ZFUNC_MASK 0x00000070 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080 +#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700 +#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800 +#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000 +#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000 + +#define RB_DEPTHCONTROL_MASK \ + (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \ + RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_ZFUNC_MASK | \ + RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) + +#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \ + ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \ + (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \ + (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \ + (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \ + (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \ + (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \ + (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \ + (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \ + (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \ + (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \ + (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \ + (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \ + (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \ + (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)) + +#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + } rb_depthcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + } rb_depthcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depthcontrol_t f; +} rb_depthcontrol_u; + + +/* + * RB_BLENDCONTROL struct + */ + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1 +#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29 +#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f +#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000 +#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000 + +#define RB_BLENDCONTROL_MASK \ + (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \ + RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \ + RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \ + RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_MASK) + +#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \ + ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \ + (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \ + (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \ + (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \ + (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \ + (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \ + (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \ + (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)) + +#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int : 3; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int : 1; + } rb_blendcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int : 1; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int : 3; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + } rb_blendcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blendcontrol_t f; +} rb_blendcontrol_u; + + +/* + * RB_COLORCONTROL struct + */ + +#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1 +#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1 +#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1 +#define RB_COLORCONTROL_ROP_CODE_SIZE 4 +#define RB_COLORCONTROL_DITHER_MODE_SIZE 2 +#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2 +#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2 + +#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4 +#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5 +#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7 +#define RB_COLORCONTROL_ROP_CODE_SHIFT 8 +#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12 +#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14 +#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30 + +#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010 +#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020 +#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080 +#define RB_COLORCONTROL_ROP_CODE_MASK 0x00000f00 +#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000 +#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000 +#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000 + +#define RB_COLORCONTROL_MASK \ + (RB_COLORCONTROL_ALPHA_FUNC_MASK | \ + RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \ + RB_COLORCONTROL_BLEND_DISABLE_MASK | \ + RB_COLORCONTROL_FOG_ENABLE_MASK | \ + RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \ + RB_COLORCONTROL_ROP_CODE_MASK | \ + RB_COLORCONTROL_DITHER_MODE_MASK | \ + RB_COLORCONTROL_DITHER_TYPE_MASK | \ + RB_COLORCONTROL_PIXEL_FOG_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) + +#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \ + ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \ + (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \ + (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \ + (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \ + (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \ + (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \ + (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \ + (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \ + (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \ + (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \ + (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \ + (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \ + (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \ + (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)) + +#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int : 7; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + } rb_colorcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int : 7; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + } rb_colorcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_colorcontrol_t f; +} rb_colorcontrol_u; + + +/* + * RB_MODECONTROL struct + */ + +#define RB_MODECONTROL_EDRAM_MODE_SIZE 3 + +#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0 + +#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007 + +#define RB_MODECONTROL_MASK \ + (RB_MODECONTROL_EDRAM_MODE_MASK) + +#define RB_MODECONTROL(edram_mode) \ + ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)) + +#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \ + ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \ + rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + unsigned int : 29; + } rb_modecontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int : 29; + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + } rb_modecontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_modecontrol_t f; +} rb_modecontrol_u; + + +/* + * RB_COLOR_DEST_MASK struct + */ + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff + +#define RB_COLOR_DEST_MASK_MASK \ + (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) + +#define RB_COLOR_DEST_MASK(color_dest_mask) \ + ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)) + +#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \ + ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \ + rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_dest_mask_t f; +} rb_color_dest_mask_u; + + +/* + * RB_COPY_CONTROL struct + */ + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1 +#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3 +#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008 +#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0 + +#define RB_COPY_CONTROL_MASK \ + (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \ + RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \ + RB_COPY_CONTROL_CLEAR_MASK_MASK) + +#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \ + ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \ + (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \ + (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)) + +#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int : 24; + } rb_copy_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int : 24; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + } rb_copy_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_control_t f; +} rb_copy_control_u; + + +/* + * RB_COPY_DEST_BASE struct + */ + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000 + +#define RB_COPY_DEST_BASE_MASK \ + (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) + +#define RB_COPY_DEST_BASE(copy_dest_base) \ + ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)) + +#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \ + ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \ + rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int : 12; + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + } rb_copy_dest_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + unsigned int : 12; + } rb_copy_dest_base_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_base_t f; +} rb_copy_dest_base_u; + + +/* + * RB_COPY_DEST_PITCH struct + */ + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff + +#define RB_COPY_DEST_PITCH_MASK \ + (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) + +#define RB_COPY_DEST_PITCH(copy_dest_pitch) \ + ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)) + +#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \ + ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \ + rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + unsigned int : 23; + } rb_copy_dest_pitch_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int : 23; + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + } rb_copy_dest_pitch_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pitch_t f; +} rb_copy_dest_pitch_u; + + +/* + * RB_COPY_DEST_INFO struct + */ + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000 + +#define RB_COPY_DEST_INFO_MASK \ + (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) + +#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \ + ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \ + (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \ + (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \ + (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \ + (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \ + (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \ + (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \ + (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \ + (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \ + (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int : 14; + } rb_copy_dest_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int : 14; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + } rb_copy_dest_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_info_t f; +} rb_copy_dest_info_u; + + +/* + * RB_COPY_DEST_PIXEL_OFFSET struct + */ + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000 + +#define RB_COPY_DEST_PIXEL_OFFSET_MASK \ + (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \ + RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) + +#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \ + ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \ + (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)) + +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int : 6; + } rb_copy_dest_pixel_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int : 6; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + } rb_copy_dest_pixel_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pixel_offset_t f; +} rb_copy_dest_pixel_offset_u; + + +/* + * RB_DEPTH_CLEAR struct + */ + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff + +#define RB_DEPTH_CLEAR_MASK \ + (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) + +#define RB_DEPTH_CLEAR(depth_clear) \ + ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)) + +#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \ + ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \ + rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_clear_t f; +} rb_depth_clear_u; + + +/* + * RB_SAMPLE_COUNT_CTL struct + */ + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002 + +#define RB_SAMPLE_COUNT_CTL_MASK \ + (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \ + RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) + +#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \ + ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \ + (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)) + +#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int : 30; + } rb_sample_count_ctl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int : 30; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + } rb_sample_count_ctl_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_ctl_t f; +} rb_sample_count_ctl_u; + + +/* + * RB_SAMPLE_COUNT_ADDR struct + */ + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff + +#define RB_SAMPLE_COUNT_ADDR_MASK \ + (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) + +#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \ + ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)) + +#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \ + ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \ + rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_addr_t f; +} rb_sample_count_addr_u; + + +/* + * RB_BC_CONTROL struct + */ + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1 +#define RB_BC_CONTROL_CRC_MODE_SIZE 1 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1 +#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_RESERVED9_SIZE 1 +#define RB_BC_CONTROL_RESERVED10_SIZE 1 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14 +#define RB_BC_CONTROL_CRC_MODE_SHIFT 15 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16 +#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29 +#define RB_BC_CONTROL_RESERVED9_SHIFT 30 +#define RB_BC_CONTROL_RESERVED10_SHIFT 31 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000 +#define RB_BC_CONTROL_CRC_MODE_MASK 0x00008000 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000 +#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000 +#define RB_BC_CONTROL_RESERVED9_MASK 0x40000000 +#define RB_BC_CONTROL_RESERVED10_MASK 0x80000000 + +#define RB_BC_CONTROL_MASK \ + (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \ + RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \ + RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \ + RB_BC_CONTROL_CRC_MODE_MASK | \ + RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \ + RB_BC_CONTROL_DISABLE_ACCUM_MASK | \ + RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \ + RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_RESERVED9_MASK | \ + RB_BC_CONTROL_RESERVED10_MASK) + +#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, reserved9, reserved10) \ + ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \ + (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \ + (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \ + (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \ + (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \ + (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \ + (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \ + (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \ + (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \ + (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \ + (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \ + (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \ + (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \ + (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \ + (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \ + (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \ + (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \ + (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT) | \ + (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT)) + +#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED9(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED9_MASK) >> RB_BC_CONTROL_RESERVED9_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED10(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED10_MASK) >> RB_BC_CONTROL_RESERVED10_SHIFT) + +#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED9(rb_bc_control_reg, reserved9) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED9_MASK) | (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED10(rb_bc_control_reg, reserved10) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED10_MASK) | (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int : 1; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int reserved9 : RB_BC_CONTROL_RESERVED9_SIZE; + unsigned int reserved10 : RB_BC_CONTROL_RESERVED10_SIZE; + } rb_bc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int reserved10 : RB_BC_CONTROL_RESERVED10_SIZE; + unsigned int reserved9 : RB_BC_CONTROL_RESERVED9_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int : 1; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + } rb_bc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_control_t f; +} rb_bc_control_u; + + +/* + * RB_EDRAM_INFO struct + */ + +#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2 +#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18 + +#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4 +#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14 + +#define RB_EDRAM_INFO_EDRAM_SIZE_MASK 0x0000000f +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030 +#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000 + +#define RB_EDRAM_INFO_MASK \ + (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \ + RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \ + RB_EDRAM_INFO_EDRAM_RANGE_MASK) + +#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \ + ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \ + (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \ + (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)) + +#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int : 8; + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + } rb_edram_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + unsigned int : 8; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + } rb_edram_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_edram_info_t f; +} rb_edram_info_u; + + +/* + * RB_CRC_RD_PORT struct + */ + +#define RB_CRC_RD_PORT_CRC_DATA_SIZE 32 + +#define RB_CRC_RD_PORT_CRC_DATA_SHIFT 0 + +#define RB_CRC_RD_PORT_CRC_DATA_MASK 0xffffffff + +#define RB_CRC_RD_PORT_MASK \ + (RB_CRC_RD_PORT_CRC_DATA_MASK) + +#define RB_CRC_RD_PORT(crc_data) \ + ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)) + +#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \ + ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \ + rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_rd_port_t f; +} rb_crc_rd_port_u; + + +/* + * RB_CRC_CONTROL struct + */ + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001 + +#define RB_CRC_CONTROL_MASK \ + (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) + +#define RB_CRC_CONTROL(crc_rd_advance) \ + ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)) + +#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \ + ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \ + rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + unsigned int : 31; + } rb_crc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int : 31; + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + } rb_crc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_control_t f; +} rb_crc_control_u; + + +/* + * RB_CRC_MASK struct + */ + +#define RB_CRC_MASK_CRC_MASK_SIZE 32 + +#define RB_CRC_MASK_CRC_MASK_SHIFT 0 + +#define RB_CRC_MASK_CRC_MASK_MASK 0xffffffff + +#define RB_CRC_MASK_MASK \ + (RB_CRC_MASK_CRC_MASK_MASK) + +#define RB_CRC_MASK(crc_mask) \ + ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)) + +#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \ + ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT) + +#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \ + rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_mask_t f; +} rb_crc_mask_u; + + +/* + * RB_PERFCOUNTER0_SELECT struct + */ + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define RB_PERFCOUNTER0_SELECT_MASK \ + (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define RB_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \ + ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \ + rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } rb_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } rb_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_select_t f; +} rb_perfcounter0_select_u; + + +/* + * RB_PERFCOUNTER0_LOW struct + */ + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define RB_PERFCOUNTER0_LOW_MASK \ + (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \ + ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \ + rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_low_t f; +} rb_perfcounter0_low_u; + + +/* + * RB_PERFCOUNTER0_HI struct + */ + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define RB_PERFCOUNTER0_HI_MASK \ + (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \ + ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \ + rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } rb_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } rb_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_hi_t f; +} rb_perfcounter0_hi_u; + + +/* + * RB_TOTAL_SAMPLES struct + */ + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff + +#define RB_TOTAL_SAMPLES_MASK \ + (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) + +#define RB_TOTAL_SAMPLES(total_samples) \ + ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)) + +#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \ + ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \ + rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_total_samples_t f; +} rb_total_samples_u; + + +/* + * RB_ZPASS_SAMPLES struct + */ + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff + +#define RB_ZPASS_SAMPLES_MASK \ + (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) + +#define RB_ZPASS_SAMPLES(zpass_samples) \ + ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)) + +#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \ + ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \ + rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zpass_samples_t f; +} rb_zpass_samples_u; + + +/* + * RB_ZFAIL_SAMPLES struct + */ + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff + +#define RB_ZFAIL_SAMPLES_MASK \ + (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) + +#define RB_ZFAIL_SAMPLES(zfail_samples) \ + ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)) + +#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \ + ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \ + rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zfail_samples_t f; +} rb_zfail_samples_u; + + +/* + * RB_SFAIL_SAMPLES struct + */ + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff + +#define RB_SFAIL_SAMPLES_MASK \ + (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) + +#define RB_SFAIL_SAMPLES(sfail_samples) \ + ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)) + +#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \ + ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \ + rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sfail_samples_t f; +} rb_sfail_samples_u; + + +/* + * RB_DEBUG_0 struct + */ + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE 1 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1 +#define RB_DEBUG_0_C_REQ_FULL_SIZE 1 +#define RB_DEBUG_0_C_MASK_FULL_SIZE 1 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7 +#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8 +#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17 +#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18 +#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25 +#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26 +#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28 +#define RB_DEBUG_0_C_REQ_FULL_SHIFT 29 +#define RB_DEBUG_0_C_MASK_FULL_SHIFT 30 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020 +#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK 0x00000040 +#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK 0x00000080 +#define RB_DEBUG_0_RDREQ_C1_FULL_MASK 0x00000100 +#define RB_DEBUG_0_RDREQ_C0_FULL_MASK 0x00000200 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000 +#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK 0x00010000 +#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK 0x00020000 +#define RB_DEBUG_0_WRREQ_C1_FULL_MASK 0x00040000 +#define RB_DEBUG_0_WRREQ_C0_FULL_MASK 0x00080000 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000 +#define RB_DEBUG_0_C_SX_LAT_FULL_MASK 0x04000000 +#define RB_DEBUG_0_C_SX_CMD_FULL_MASK 0x08000000 +#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000 +#define RB_DEBUG_0_C_REQ_FULL_MASK 0x20000000 +#define RB_DEBUG_0_C_MASK_FULL_MASK 0x40000000 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000 + +#define RB_DEBUG_0_MASK \ + (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C0_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \ + RB_DEBUG_0_C_SX_LAT_FULL_MASK | \ + RB_DEBUG_0_C_SX_CMD_FULL_MASK | \ + RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \ + RB_DEBUG_0_C_REQ_FULL_MASK | \ + RB_DEBUG_0_C_MASK_FULL_MASK | \ + RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) + +#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \ + ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \ + (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \ + (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \ + (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \ + (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \ + (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \ + (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \ + (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \ + (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \ + (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \ + (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \ + (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \ + (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \ + (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \ + (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \ + (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \ + (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \ + (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \ + (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \ + (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \ + (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \ + (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \ + (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \ + (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \ + (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \ + (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \ + (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)) + +#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + } rb_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + } rb_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_0_t f; +} rb_debug_0_u; + + +/* + * RB_DEBUG_1 struct + */ + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28 +#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT 30 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000 +#define RB_DEBUG_1_C_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_1_C_MASK_EMPTY_MASK 0x40000000 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_1_MASK \ + (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \ + RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \ + RB_DEBUG_1_C_REQ_EMPTY_MASK | \ + RB_DEBUG_1_C_MASK_EMPTY_MASK | \ + RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) + +#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \ + ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \ + (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \ + (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \ + (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \ + (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \ + (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \ + (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \ + (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \ + (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \ + (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \ + (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \ + (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \ + (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \ + (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \ + (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \ + (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \ + (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \ + (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \ + (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \ + (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \ + (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \ + (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \ + (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \ + (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)) + +#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + } rb_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + } rb_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_1_t f; +} rb_debug_1_u; + + +/* + * RB_DEBUG_2 struct + */ + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_FULL_SIZE 1 +#define RB_DEBUG_2_Z_TILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE 1 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16 +#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT 17 +#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT 18 +#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT 19 +#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT 20 +#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT 21 +#define RB_DEBUG_2_Z_TILE_FULL_SHIFT 22 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT 28 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT 30 +#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT 31 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000 +#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000 +#define RB_DEBUG_2_Z0_MASK_FULL_MASK 0x00020000 +#define RB_DEBUG_2_Z1_MASK_FULL_MASK 0x00040000 +#define RB_DEBUG_2_Z0_REQ_FULL_MASK 0x00080000 +#define RB_DEBUG_2_Z1_REQ_FULL_MASK 0x00100000 +#define RB_DEBUG_2_Z_SAMP_FULL_MASK 0x00200000 +#define RB_DEBUG_2_Z_TILE_FULL_MASK 0x00400000 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK 0x04000000 +#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK 0x08000000 +#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK 0x10000000 +#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK 0x40000000 +#define RB_DEBUG_2_Z_TILE_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_2_MASK \ + (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \ + RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \ + RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \ + RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \ + RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \ + RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \ + RB_DEBUG_2_Z0_MASK_FULL_MASK | \ + RB_DEBUG_2_Z1_MASK_FULL_MASK | \ + RB_DEBUG_2_Z0_REQ_FULL_MASK | \ + RB_DEBUG_2_Z1_REQ_FULL_MASK | \ + RB_DEBUG_2_Z_SAMP_FULL_MASK | \ + RB_DEBUG_2_Z_TILE_FULL_MASK | \ + RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \ + RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \ + RB_DEBUG_2_Z_TILE_EMPTY_MASK) + +#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \ + ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \ + (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \ + (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \ + (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \ + (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \ + (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \ + (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \ + (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \ + (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \ + (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \ + (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \ + (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \ + (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \ + (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \ + (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \ + (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \ + (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \ + (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \ + (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \ + (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \ + (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \ + (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \ + (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)) + +#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + } rb_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + } rb_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_2_t f; +} rb_debug_2_u; + + +/* + * RB_DEBUG_3 struct + */ + +#define RB_DEBUG_3_ACCUM_VALID_SIZE 4 +#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4 +#define RB_DEBUG_3_SHD_FULL_SIZE 1 +#define RB_DEBUG_3_SHD_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1 + +#define RB_DEBUG_3_ACCUM_VALID_SHIFT 0 +#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15 +#define RB_DEBUG_3_SHD_FULL_SHIFT 19 +#define RB_DEBUG_3_SHD_EMPTY_SHIFT 20 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28 + +#define RB_DEBUG_3_ACCUM_VALID_MASK 0x0000000f +#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000 +#define RB_DEBUG_3_SHD_FULL_MASK 0x00080000 +#define RB_DEBUG_3_SHD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000 + +#define RB_DEBUG_3_MASK \ + (RB_DEBUG_3_ACCUM_VALID_MASK | \ + RB_DEBUG_3_ACCUM_FLUSHING_MASK | \ + RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \ + RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \ + RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \ + RB_DEBUG_3_SHD_FULL_MASK | \ + RB_DEBUG_3_SHD_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) + +#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \ + ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \ + (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \ + (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \ + (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \ + (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \ + (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \ + (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \ + (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \ + (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \ + (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \ + (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \ + (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \ + (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \ + (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \ + (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)) + +#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int : 3; + } rb_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int : 3; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + } rb_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_3_t f; +} rb_debug_3_u; + + +/* + * RB_DEBUG_4 struct + */ + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00 + +#define RB_DEBUG_4_MASK \ + (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \ + RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \ + RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) + +#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \ + ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \ + (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \ + (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \ + (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \ + (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \ + (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \ + (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \ + (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \ + (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \ + (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)) + +#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int : 19; + } rb_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int : 19; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + } rb_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_4_t f; +} rb_debug_4_u; + + +/* + * RB_FLAG_CONTROL struct + */ + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001 + +#define RB_FLAG_CONTROL_MASK \ + (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) + +#define RB_FLAG_CONTROL(debug_flag_clear) \ + ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)) + +#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \ + ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \ + rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + unsigned int : 31; + } rb_flag_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int : 31; + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + } rb_flag_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_flag_control_t f; +} rb_flag_control_u; + + +/* + * BC_DUMMY_CRAYRB_ENUMS struct + */ + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000 + +#define BC_DUMMY_CRAYRB_ENUMS_MASK \ + (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) + +#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \ + ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \ + (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \ + (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \ + (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \ + (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \ + (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \ + (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)) + +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + } bc_dummy_crayrb_enums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + } bc_dummy_crayrb_enums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_enums_t f; +} bc_dummy_crayrb_enums_u; + + +/* + * BC_DUMMY_CRAYRB_MOREENUMS struct + */ + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003 + +#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \ + (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) + +#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \ + ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)) + +#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \ + ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \ + bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + unsigned int : 30; + } bc_dummy_crayrb_moreenums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int : 30; + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + } bc_dummy_crayrb_moreenums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_moreenums_t f; +} bc_dummy_crayrb_moreenums_u; + + +#endif + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h new file mode 100644 index 000000000000..1feebebda054 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h @@ -0,0 +1,540 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_TYPEDEF_HEADER) +#define _yamato_TYPEDEF_HEADER + +#include "yamato_registers.h" + +typedef union PA_CL_VPORT_XSCALE regPA_CL_VPORT_XSCALE; +typedef union PA_CL_VPORT_XOFFSET regPA_CL_VPORT_XOFFSET; +typedef union PA_CL_VPORT_YSCALE regPA_CL_VPORT_YSCALE; +typedef union PA_CL_VPORT_YOFFSET regPA_CL_VPORT_YOFFSET; +typedef union PA_CL_VPORT_ZSCALE regPA_CL_VPORT_ZSCALE; +typedef union PA_CL_VPORT_ZOFFSET regPA_CL_VPORT_ZOFFSET; +typedef union PA_CL_VTE_CNTL regPA_CL_VTE_CNTL; +typedef union PA_CL_CLIP_CNTL regPA_CL_CLIP_CNTL; +typedef union PA_CL_GB_VERT_CLIP_ADJ regPA_CL_GB_VERT_CLIP_ADJ; +typedef union PA_CL_GB_VERT_DISC_ADJ regPA_CL_GB_VERT_DISC_ADJ; +typedef union PA_CL_GB_HORZ_CLIP_ADJ regPA_CL_GB_HORZ_CLIP_ADJ; +typedef union PA_CL_GB_HORZ_DISC_ADJ regPA_CL_GB_HORZ_DISC_ADJ; +typedef union PA_CL_ENHANCE regPA_CL_ENHANCE; +typedef union PA_SC_ENHANCE regPA_SC_ENHANCE; +typedef union PA_SU_VTX_CNTL regPA_SU_VTX_CNTL; +typedef union PA_SU_POINT_SIZE regPA_SU_POINT_SIZE; +typedef union PA_SU_POINT_MINMAX regPA_SU_POINT_MINMAX; +typedef union PA_SU_LINE_CNTL regPA_SU_LINE_CNTL; +typedef union PA_SU_SC_MODE_CNTL regPA_SU_SC_MODE_CNTL; +typedef union PA_SU_POLY_OFFSET_FRONT_SCALE regPA_SU_POLY_OFFSET_FRONT_SCALE; +typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET regPA_SU_POLY_OFFSET_FRONT_OFFSET; +typedef union PA_SU_POLY_OFFSET_BACK_SCALE regPA_SU_POLY_OFFSET_BACK_SCALE; +typedef union PA_SU_POLY_OFFSET_BACK_OFFSET regPA_SU_POLY_OFFSET_BACK_OFFSET; +typedef union PA_SU_PERFCOUNTER0_SELECT regPA_SU_PERFCOUNTER0_SELECT; +typedef union PA_SU_PERFCOUNTER1_SELECT regPA_SU_PERFCOUNTER1_SELECT; +typedef union PA_SU_PERFCOUNTER2_SELECT regPA_SU_PERFCOUNTER2_SELECT; +typedef union PA_SU_PERFCOUNTER3_SELECT regPA_SU_PERFCOUNTER3_SELECT; +typedef union PA_SU_PERFCOUNTER0_LOW regPA_SU_PERFCOUNTER0_LOW; +typedef union PA_SU_PERFCOUNTER0_HI regPA_SU_PERFCOUNTER0_HI; +typedef union PA_SU_PERFCOUNTER1_LOW regPA_SU_PERFCOUNTER1_LOW; +typedef union PA_SU_PERFCOUNTER1_HI regPA_SU_PERFCOUNTER1_HI; +typedef union PA_SU_PERFCOUNTER2_LOW regPA_SU_PERFCOUNTER2_LOW; +typedef union PA_SU_PERFCOUNTER2_HI regPA_SU_PERFCOUNTER2_HI; +typedef union PA_SU_PERFCOUNTER3_LOW regPA_SU_PERFCOUNTER3_LOW; +typedef union PA_SU_PERFCOUNTER3_HI regPA_SU_PERFCOUNTER3_HI; +typedef union PA_SC_WINDOW_OFFSET regPA_SC_WINDOW_OFFSET; +typedef union PA_SC_AA_CONFIG regPA_SC_AA_CONFIG; +typedef union PA_SC_AA_MASK regPA_SC_AA_MASK; +typedef union PA_SC_LINE_STIPPLE regPA_SC_LINE_STIPPLE; +typedef union PA_SC_LINE_CNTL regPA_SC_LINE_CNTL; +typedef union PA_SC_WINDOW_SCISSOR_TL regPA_SC_WINDOW_SCISSOR_TL; +typedef union PA_SC_WINDOW_SCISSOR_BR regPA_SC_WINDOW_SCISSOR_BR; +typedef union PA_SC_SCREEN_SCISSOR_TL regPA_SC_SCREEN_SCISSOR_TL; +typedef union PA_SC_SCREEN_SCISSOR_BR regPA_SC_SCREEN_SCISSOR_BR; +typedef union PA_SC_VIZ_QUERY regPA_SC_VIZ_QUERY; +typedef union PA_SC_VIZ_QUERY_STATUS regPA_SC_VIZ_QUERY_STATUS; +typedef union PA_SC_LINE_STIPPLE_STATE regPA_SC_LINE_STIPPLE_STATE; +typedef union PA_SC_PERFCOUNTER0_SELECT regPA_SC_PERFCOUNTER0_SELECT; +typedef union PA_SC_PERFCOUNTER0_LOW regPA_SC_PERFCOUNTER0_LOW; +typedef union PA_SC_PERFCOUNTER0_HI regPA_SC_PERFCOUNTER0_HI; +typedef union PA_CL_CNTL_STATUS regPA_CL_CNTL_STATUS; +typedef union PA_SU_CNTL_STATUS regPA_SU_CNTL_STATUS; +typedef union PA_SC_CNTL_STATUS regPA_SC_CNTL_STATUS; +typedef union PA_SU_DEBUG_CNTL regPA_SU_DEBUG_CNTL; +typedef union PA_SU_DEBUG_DATA regPA_SU_DEBUG_DATA; +typedef union PA_SC_DEBUG_CNTL regPA_SC_DEBUG_CNTL; +typedef union PA_SC_DEBUG_DATA regPA_SC_DEBUG_DATA; +typedef union GFX_COPY_STATE regGFX_COPY_STATE; +typedef union VGT_DRAW_INITIATOR regVGT_DRAW_INITIATOR; +typedef union VGT_EVENT_INITIATOR regVGT_EVENT_INITIATOR; +typedef union VGT_DMA_BASE regVGT_DMA_BASE; +typedef union VGT_DMA_SIZE regVGT_DMA_SIZE; +typedef union VGT_BIN_BASE regVGT_BIN_BASE; +typedef union VGT_BIN_SIZE regVGT_BIN_SIZE; +typedef union VGT_CURRENT_BIN_ID_MIN regVGT_CURRENT_BIN_ID_MIN; +typedef union VGT_CURRENT_BIN_ID_MAX regVGT_CURRENT_BIN_ID_MAX; +typedef union VGT_IMMED_DATA regVGT_IMMED_DATA; +typedef union VGT_MAX_VTX_INDX regVGT_MAX_VTX_INDX; +typedef union VGT_MIN_VTX_INDX regVGT_MIN_VTX_INDX; +typedef union VGT_INDX_OFFSET regVGT_INDX_OFFSET; +typedef union VGT_VERTEX_REUSE_BLOCK_CNTL regVGT_VERTEX_REUSE_BLOCK_CNTL; +typedef union VGT_OUT_DEALLOC_CNTL regVGT_OUT_DEALLOC_CNTL; +typedef union VGT_MULTI_PRIM_IB_RESET_INDX regVGT_MULTI_PRIM_IB_RESET_INDX; +typedef union VGT_ENHANCE regVGT_ENHANCE; +typedef union VGT_VTX_VECT_EJECT_REG regVGT_VTX_VECT_EJECT_REG; +typedef union VGT_LAST_COPY_STATE regVGT_LAST_COPY_STATE; +typedef union VGT_DEBUG_CNTL regVGT_DEBUG_CNTL; +typedef union VGT_DEBUG_DATA regVGT_DEBUG_DATA; +typedef union VGT_CNTL_STATUS regVGT_CNTL_STATUS; +typedef union VGT_CRC_SQ_DATA regVGT_CRC_SQ_DATA; +typedef union VGT_CRC_SQ_CTRL regVGT_CRC_SQ_CTRL; +typedef union VGT_PERFCOUNTER0_SELECT regVGT_PERFCOUNTER0_SELECT; +typedef union VGT_PERFCOUNTER1_SELECT regVGT_PERFCOUNTER1_SELECT; +typedef union VGT_PERFCOUNTER2_SELECT regVGT_PERFCOUNTER2_SELECT; +typedef union VGT_PERFCOUNTER3_SELECT regVGT_PERFCOUNTER3_SELECT; +typedef union VGT_PERFCOUNTER0_LOW regVGT_PERFCOUNTER0_LOW; +typedef union VGT_PERFCOUNTER1_LOW regVGT_PERFCOUNTER1_LOW; +typedef union VGT_PERFCOUNTER2_LOW regVGT_PERFCOUNTER2_LOW; +typedef union VGT_PERFCOUNTER3_LOW regVGT_PERFCOUNTER3_LOW; +typedef union VGT_PERFCOUNTER0_HI regVGT_PERFCOUNTER0_HI; +typedef union VGT_PERFCOUNTER1_HI regVGT_PERFCOUNTER1_HI; +typedef union VGT_PERFCOUNTER2_HI regVGT_PERFCOUNTER2_HI; +typedef union VGT_PERFCOUNTER3_HI regVGT_PERFCOUNTER3_HI; +typedef union TC_CNTL_STATUS regTC_CNTL_STATUS; +typedef union TCR_CHICKEN regTCR_CHICKEN; +typedef union TCF_CHICKEN regTCF_CHICKEN; +typedef union TCM_CHICKEN regTCM_CHICKEN; +typedef union TCR_PERFCOUNTER0_SELECT regTCR_PERFCOUNTER0_SELECT; +typedef union TCR_PERFCOUNTER1_SELECT regTCR_PERFCOUNTER1_SELECT; +typedef union TCR_PERFCOUNTER0_HI regTCR_PERFCOUNTER0_HI; +typedef union TCR_PERFCOUNTER1_HI regTCR_PERFCOUNTER1_HI; +typedef union TCR_PERFCOUNTER0_LOW regTCR_PERFCOUNTER0_LOW; +typedef union TCR_PERFCOUNTER1_LOW regTCR_PERFCOUNTER1_LOW; +typedef union TP_TC_CLKGATE_CNTL regTP_TC_CLKGATE_CNTL; +typedef union TPC_CNTL_STATUS regTPC_CNTL_STATUS; +typedef union TPC_DEBUG0 regTPC_DEBUG0; +typedef union TPC_DEBUG1 regTPC_DEBUG1; +typedef union TPC_CHICKEN regTPC_CHICKEN; +typedef union TP0_CNTL_STATUS regTP0_CNTL_STATUS; +typedef union TP0_DEBUG regTP0_DEBUG; +typedef union TP0_CHICKEN regTP0_CHICKEN; +typedef union TP0_PERFCOUNTER0_SELECT regTP0_PERFCOUNTER0_SELECT; +typedef union TP0_PERFCOUNTER0_HI regTP0_PERFCOUNTER0_HI; +typedef union TP0_PERFCOUNTER0_LOW regTP0_PERFCOUNTER0_LOW; +typedef union TP0_PERFCOUNTER1_SELECT regTP0_PERFCOUNTER1_SELECT; +typedef union TP0_PERFCOUNTER1_HI regTP0_PERFCOUNTER1_HI; +typedef union TP0_PERFCOUNTER1_LOW regTP0_PERFCOUNTER1_LOW; +typedef union TCM_PERFCOUNTER0_SELECT regTCM_PERFCOUNTER0_SELECT; +typedef union TCM_PERFCOUNTER1_SELECT regTCM_PERFCOUNTER1_SELECT; +typedef union TCM_PERFCOUNTER0_HI regTCM_PERFCOUNTER0_HI; +typedef union TCM_PERFCOUNTER1_HI regTCM_PERFCOUNTER1_HI; +typedef union TCM_PERFCOUNTER0_LOW regTCM_PERFCOUNTER0_LOW; +typedef union TCM_PERFCOUNTER1_LOW regTCM_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER0_SELECT regTCF_PERFCOUNTER0_SELECT; +typedef union TCF_PERFCOUNTER1_SELECT regTCF_PERFCOUNTER1_SELECT; +typedef union TCF_PERFCOUNTER2_SELECT regTCF_PERFCOUNTER2_SELECT; +typedef union TCF_PERFCOUNTER3_SELECT regTCF_PERFCOUNTER3_SELECT; +typedef union TCF_PERFCOUNTER4_SELECT regTCF_PERFCOUNTER4_SELECT; +typedef union TCF_PERFCOUNTER5_SELECT regTCF_PERFCOUNTER5_SELECT; +typedef union TCF_PERFCOUNTER6_SELECT regTCF_PERFCOUNTER6_SELECT; +typedef union TCF_PERFCOUNTER7_SELECT regTCF_PERFCOUNTER7_SELECT; +typedef union TCF_PERFCOUNTER8_SELECT regTCF_PERFCOUNTER8_SELECT; +typedef union TCF_PERFCOUNTER9_SELECT regTCF_PERFCOUNTER9_SELECT; +typedef union TCF_PERFCOUNTER10_SELECT regTCF_PERFCOUNTER10_SELECT; +typedef union TCF_PERFCOUNTER11_SELECT regTCF_PERFCOUNTER11_SELECT; +typedef union TCF_PERFCOUNTER0_HI regTCF_PERFCOUNTER0_HI; +typedef union TCF_PERFCOUNTER1_HI regTCF_PERFCOUNTER1_HI; +typedef union TCF_PERFCOUNTER2_HI regTCF_PERFCOUNTER2_HI; +typedef union TCF_PERFCOUNTER3_HI regTCF_PERFCOUNTER3_HI; +typedef union TCF_PERFCOUNTER4_HI regTCF_PERFCOUNTER4_HI; +typedef union TCF_PERFCOUNTER5_HI regTCF_PERFCOUNTER5_HI; +typedef union TCF_PERFCOUNTER6_HI regTCF_PERFCOUNTER6_HI; +typedef union TCF_PERFCOUNTER7_HI regTCF_PERFCOUNTER7_HI; +typedef union TCF_PERFCOUNTER8_HI regTCF_PERFCOUNTER8_HI; +typedef union TCF_PERFCOUNTER9_HI regTCF_PERFCOUNTER9_HI; +typedef union TCF_PERFCOUNTER10_HI regTCF_PERFCOUNTER10_HI; +typedef union TCF_PERFCOUNTER11_HI regTCF_PERFCOUNTER11_HI; +typedef union TCF_PERFCOUNTER0_LOW regTCF_PERFCOUNTER0_LOW; +typedef union TCF_PERFCOUNTER1_LOW regTCF_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER2_LOW regTCF_PERFCOUNTER2_LOW; +typedef union TCF_PERFCOUNTER3_LOW regTCF_PERFCOUNTER3_LOW; +typedef union TCF_PERFCOUNTER4_LOW regTCF_PERFCOUNTER4_LOW; +typedef union TCF_PERFCOUNTER5_LOW regTCF_PERFCOUNTER5_LOW; +typedef union TCF_PERFCOUNTER6_LOW regTCF_PERFCOUNTER6_LOW; +typedef union TCF_PERFCOUNTER7_LOW regTCF_PERFCOUNTER7_LOW; +typedef union TCF_PERFCOUNTER8_LOW regTCF_PERFCOUNTER8_LOW; +typedef union TCF_PERFCOUNTER9_LOW regTCF_PERFCOUNTER9_LOW; +typedef union TCF_PERFCOUNTER10_LOW regTCF_PERFCOUNTER10_LOW; +typedef union TCF_PERFCOUNTER11_LOW regTCF_PERFCOUNTER11_LOW; +typedef union TCF_DEBUG regTCF_DEBUG; +typedef union TCA_FIFO_DEBUG regTCA_FIFO_DEBUG; +typedef union TCA_PROBE_DEBUG regTCA_PROBE_DEBUG; +typedef union TCA_TPC_DEBUG regTCA_TPC_DEBUG; +typedef union TCB_CORE_DEBUG regTCB_CORE_DEBUG; +typedef union TCB_TAG0_DEBUG regTCB_TAG0_DEBUG; +typedef union TCB_TAG1_DEBUG regTCB_TAG1_DEBUG; +typedef union TCB_TAG2_DEBUG regTCB_TAG2_DEBUG; +typedef union TCB_TAG3_DEBUG regTCB_TAG3_DEBUG; +typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG; +typedef union TCB_FETCH_GEN_WALKER_DEBUG regTCB_FETCH_GEN_WALKER_DEBUG; +typedef union TCB_FETCH_GEN_PIPE0_DEBUG regTCB_FETCH_GEN_PIPE0_DEBUG; +typedef union TCD_INPUT0_DEBUG regTCD_INPUT0_DEBUG; +typedef union TCD_DEGAMMA_DEBUG regTCD_DEGAMMA_DEBUG; +typedef union TCD_DXTMUX_SCTARB_DEBUG regTCD_DXTMUX_SCTARB_DEBUG; +typedef union TCD_DXTC_ARB_DEBUG regTCD_DXTC_ARB_DEBUG; +typedef union TCD_STALLS_DEBUG regTCD_STALLS_DEBUG; +typedef union TCO_STALLS_DEBUG regTCO_STALLS_DEBUG; +typedef union TCO_QUAD0_DEBUG0 regTCO_QUAD0_DEBUG0; +typedef union TCO_QUAD0_DEBUG1 regTCO_QUAD0_DEBUG1; +typedef union SQ_GPR_MANAGEMENT regSQ_GPR_MANAGEMENT; +typedef union SQ_FLOW_CONTROL regSQ_FLOW_CONTROL; +typedef union SQ_INST_STORE_MANAGMENT regSQ_INST_STORE_MANAGMENT; +typedef union SQ_RESOURCE_MANAGMENT regSQ_RESOURCE_MANAGMENT; +typedef union SQ_EO_RT regSQ_EO_RT; +typedef union SQ_DEBUG_MISC regSQ_DEBUG_MISC; +typedef union SQ_ACTIVITY_METER_CNTL regSQ_ACTIVITY_METER_CNTL; +typedef union SQ_ACTIVITY_METER_STATUS regSQ_ACTIVITY_METER_STATUS; +typedef union SQ_INPUT_ARB_PRIORITY regSQ_INPUT_ARB_PRIORITY; +typedef union SQ_THREAD_ARB_PRIORITY regSQ_THREAD_ARB_PRIORITY; +typedef union SQ_DEBUG_INPUT_FSM regSQ_DEBUG_INPUT_FSM; +typedef union SQ_DEBUG_CONST_MGR_FSM regSQ_DEBUG_CONST_MGR_FSM; +typedef union SQ_DEBUG_TP_FSM regSQ_DEBUG_TP_FSM; +typedef union SQ_DEBUG_FSM_ALU_0 regSQ_DEBUG_FSM_ALU_0; +typedef union SQ_DEBUG_FSM_ALU_1 regSQ_DEBUG_FSM_ALU_1; +typedef union SQ_DEBUG_EXP_ALLOC regSQ_DEBUG_EXP_ALLOC; +typedef union SQ_DEBUG_PTR_BUFF regSQ_DEBUG_PTR_BUFF; +typedef union SQ_DEBUG_GPR_VTX regSQ_DEBUG_GPR_VTX; +typedef union SQ_DEBUG_GPR_PIX regSQ_DEBUG_GPR_PIX; +typedef union SQ_DEBUG_TB_STATUS_SEL regSQ_DEBUG_TB_STATUS_SEL; +typedef union SQ_DEBUG_VTX_TB_0 regSQ_DEBUG_VTX_TB_0; +typedef union SQ_DEBUG_VTX_TB_1 regSQ_DEBUG_VTX_TB_1; +typedef union SQ_DEBUG_VTX_TB_STATUS_REG regSQ_DEBUG_VTX_TB_STATUS_REG; +typedef union SQ_DEBUG_VTX_TB_STATE_MEM regSQ_DEBUG_VTX_TB_STATE_MEM; +typedef union SQ_DEBUG_PIX_TB_0 regSQ_DEBUG_PIX_TB_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0 regSQ_DEBUG_PIX_TB_STATUS_REG_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1 regSQ_DEBUG_PIX_TB_STATUS_REG_1; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2 regSQ_DEBUG_PIX_TB_STATUS_REG_2; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3 regSQ_DEBUG_PIX_TB_STATUS_REG_3; +typedef union SQ_DEBUG_PIX_TB_STATE_MEM regSQ_DEBUG_PIX_TB_STATE_MEM; +typedef union SQ_PERFCOUNTER0_SELECT regSQ_PERFCOUNTER0_SELECT; +typedef union SQ_PERFCOUNTER1_SELECT regSQ_PERFCOUNTER1_SELECT; +typedef union SQ_PERFCOUNTER2_SELECT regSQ_PERFCOUNTER2_SELECT; +typedef union SQ_PERFCOUNTER3_SELECT regSQ_PERFCOUNTER3_SELECT; +typedef union SQ_PERFCOUNTER0_LOW regSQ_PERFCOUNTER0_LOW; +typedef union SQ_PERFCOUNTER0_HI regSQ_PERFCOUNTER0_HI; +typedef union SQ_PERFCOUNTER1_LOW regSQ_PERFCOUNTER1_LOW; +typedef union SQ_PERFCOUNTER1_HI regSQ_PERFCOUNTER1_HI; +typedef union SQ_PERFCOUNTER2_LOW regSQ_PERFCOUNTER2_LOW; +typedef union SQ_PERFCOUNTER2_HI regSQ_PERFCOUNTER2_HI; +typedef union SQ_PERFCOUNTER3_LOW regSQ_PERFCOUNTER3_LOW; +typedef union SQ_PERFCOUNTER3_HI regSQ_PERFCOUNTER3_HI; +typedef union SX_PERFCOUNTER0_SELECT regSX_PERFCOUNTER0_SELECT; +typedef union SX_PERFCOUNTER0_LOW regSX_PERFCOUNTER0_LOW; +typedef union SX_PERFCOUNTER0_HI regSX_PERFCOUNTER0_HI; +typedef union SQ_INSTRUCTION_ALU_0 regSQ_INSTRUCTION_ALU_0; +typedef union SQ_INSTRUCTION_ALU_1 regSQ_INSTRUCTION_ALU_1; +typedef union SQ_INSTRUCTION_ALU_2 regSQ_INSTRUCTION_ALU_2; +typedef union SQ_INSTRUCTION_CF_EXEC_0 regSQ_INSTRUCTION_CF_EXEC_0; +typedef union SQ_INSTRUCTION_CF_EXEC_1 regSQ_INSTRUCTION_CF_EXEC_1; +typedef union SQ_INSTRUCTION_CF_EXEC_2 regSQ_INSTRUCTION_CF_EXEC_2; +typedef union SQ_INSTRUCTION_CF_LOOP_0 regSQ_INSTRUCTION_CF_LOOP_0; +typedef union SQ_INSTRUCTION_CF_LOOP_1 regSQ_INSTRUCTION_CF_LOOP_1; +typedef union SQ_INSTRUCTION_CF_LOOP_2 regSQ_INSTRUCTION_CF_LOOP_2; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_0 regSQ_INSTRUCTION_CF_JMP_CALL_0; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_1 regSQ_INSTRUCTION_CF_JMP_CALL_1; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_2 regSQ_INSTRUCTION_CF_JMP_CALL_2; +typedef union SQ_INSTRUCTION_CF_ALLOC_0 regSQ_INSTRUCTION_CF_ALLOC_0; +typedef union SQ_INSTRUCTION_CF_ALLOC_1 regSQ_INSTRUCTION_CF_ALLOC_1; +typedef union SQ_INSTRUCTION_CF_ALLOC_2 regSQ_INSTRUCTION_CF_ALLOC_2; +typedef union SQ_INSTRUCTION_TFETCH_0 regSQ_INSTRUCTION_TFETCH_0; +typedef union SQ_INSTRUCTION_TFETCH_1 regSQ_INSTRUCTION_TFETCH_1; +typedef union SQ_INSTRUCTION_TFETCH_2 regSQ_INSTRUCTION_TFETCH_2; +typedef union SQ_INSTRUCTION_VFETCH_0 regSQ_INSTRUCTION_VFETCH_0; +typedef union SQ_INSTRUCTION_VFETCH_1 regSQ_INSTRUCTION_VFETCH_1; +typedef union SQ_INSTRUCTION_VFETCH_2 regSQ_INSTRUCTION_VFETCH_2; +typedef union SQ_CONSTANT_0 regSQ_CONSTANT_0; +typedef union SQ_CONSTANT_1 regSQ_CONSTANT_1; +typedef union SQ_CONSTANT_2 regSQ_CONSTANT_2; +typedef union SQ_CONSTANT_3 regSQ_CONSTANT_3; +typedef union SQ_FETCH_0 regSQ_FETCH_0; +typedef union SQ_FETCH_1 regSQ_FETCH_1; +typedef union SQ_FETCH_2 regSQ_FETCH_2; +typedef union SQ_FETCH_3 regSQ_FETCH_3; +typedef union SQ_FETCH_4 regSQ_FETCH_4; +typedef union SQ_FETCH_5 regSQ_FETCH_5; +typedef union SQ_CONSTANT_VFETCH_0 regSQ_CONSTANT_VFETCH_0; +typedef union SQ_CONSTANT_VFETCH_1 regSQ_CONSTANT_VFETCH_1; +typedef union SQ_CONSTANT_T2 regSQ_CONSTANT_T2; +typedef union SQ_CONSTANT_T3 regSQ_CONSTANT_T3; +typedef union SQ_CF_BOOLEANS regSQ_CF_BOOLEANS; +typedef union SQ_CF_LOOP regSQ_CF_LOOP; +typedef union SQ_CONSTANT_RT_0 regSQ_CONSTANT_RT_0; +typedef union SQ_CONSTANT_RT_1 regSQ_CONSTANT_RT_1; +typedef union SQ_CONSTANT_RT_2 regSQ_CONSTANT_RT_2; +typedef union SQ_CONSTANT_RT_3 regSQ_CONSTANT_RT_3; +typedef union SQ_FETCH_RT_0 regSQ_FETCH_RT_0; +typedef union SQ_FETCH_RT_1 regSQ_FETCH_RT_1; +typedef union SQ_FETCH_RT_2 regSQ_FETCH_RT_2; +typedef union SQ_FETCH_RT_3 regSQ_FETCH_RT_3; +typedef union SQ_FETCH_RT_4 regSQ_FETCH_RT_4; +typedef union SQ_FETCH_RT_5 regSQ_FETCH_RT_5; +typedef union SQ_CF_RT_BOOLEANS regSQ_CF_RT_BOOLEANS; +typedef union SQ_CF_RT_LOOP regSQ_CF_RT_LOOP; +typedef union SQ_VS_PROGRAM regSQ_VS_PROGRAM; +typedef union SQ_PS_PROGRAM regSQ_PS_PROGRAM; +typedef union SQ_CF_PROGRAM_SIZE regSQ_CF_PROGRAM_SIZE; +typedef union SQ_INTERPOLATOR_CNTL regSQ_INTERPOLATOR_CNTL; +typedef union SQ_PROGRAM_CNTL regSQ_PROGRAM_CNTL; +typedef union SQ_WRAPPING_0 regSQ_WRAPPING_0; +typedef union SQ_WRAPPING_1 regSQ_WRAPPING_1; +typedef union SQ_VS_CONST regSQ_VS_CONST; +typedef union SQ_PS_CONST regSQ_PS_CONST; +typedef union SQ_CONTEXT_MISC regSQ_CONTEXT_MISC; +typedef union SQ_CF_RD_BASE regSQ_CF_RD_BASE; +typedef union SQ_DEBUG_MISC_0 regSQ_DEBUG_MISC_0; +typedef union SQ_DEBUG_MISC_1 regSQ_DEBUG_MISC_1; +typedef union MH_ARBITER_CONFIG regMH_ARBITER_CONFIG; +typedef union MH_CLNT_AXI_ID_REUSE regMH_CLNT_AXI_ID_REUSE; +typedef union MH_INTERRUPT_MASK regMH_INTERRUPT_MASK; +typedef union MH_INTERRUPT_STATUS regMH_INTERRUPT_STATUS; +typedef union MH_INTERRUPT_CLEAR regMH_INTERRUPT_CLEAR; +typedef union MH_AXI_ERROR regMH_AXI_ERROR; +typedef union MH_PERFCOUNTER0_SELECT regMH_PERFCOUNTER0_SELECT; +typedef union MH_PERFCOUNTER1_SELECT regMH_PERFCOUNTER1_SELECT; +typedef union MH_PERFCOUNTER0_CONFIG regMH_PERFCOUNTER0_CONFIG; +typedef union MH_PERFCOUNTER1_CONFIG regMH_PERFCOUNTER1_CONFIG; +typedef union MH_PERFCOUNTER0_LOW regMH_PERFCOUNTER0_LOW; +typedef union MH_PERFCOUNTER1_LOW regMH_PERFCOUNTER1_LOW; +typedef union MH_PERFCOUNTER0_HI regMH_PERFCOUNTER0_HI; +typedef union MH_PERFCOUNTER1_HI regMH_PERFCOUNTER1_HI; +typedef union MH_DEBUG_CTRL regMH_DEBUG_CTRL; +typedef union MH_DEBUG_DATA regMH_DEBUG_DATA; +typedef union MH_MMU_CONFIG regMH_MMU_CONFIG; +typedef union MH_MMU_VA_RANGE regMH_MMU_VA_RANGE; +typedef union MH_MMU_PT_BASE regMH_MMU_PT_BASE; +typedef union MH_MMU_PAGE_FAULT regMH_MMU_PAGE_FAULT; +typedef union MH_MMU_TRAN_ERROR regMH_MMU_TRAN_ERROR; +typedef union MH_MMU_INVALIDATE regMH_MMU_INVALIDATE; +typedef union MH_MMU_MPU_BASE regMH_MMU_MPU_BASE; +typedef union MH_MMU_MPU_END regMH_MMU_MPU_END; +typedef union WAIT_UNTIL regWAIT_UNTIL; +typedef union RBBM_ISYNC_CNTL regRBBM_ISYNC_CNTL; +typedef union RBBM_STATUS regRBBM_STATUS; +typedef union RBBM_DSPLY regRBBM_DSPLY; +typedef union RBBM_RENDER_LATEST regRBBM_RENDER_LATEST; +typedef union RBBM_RTL_RELEASE regRBBM_RTL_RELEASE; +typedef union RBBM_PATCH_RELEASE regRBBM_PATCH_RELEASE; +typedef union RBBM_AUXILIARY_CONFIG regRBBM_AUXILIARY_CONFIG; +typedef union RBBM_PERIPHID0 regRBBM_PERIPHID0; +typedef union RBBM_PERIPHID1 regRBBM_PERIPHID1; +typedef union RBBM_PERIPHID2 regRBBM_PERIPHID2; +typedef union RBBM_PERIPHID3 regRBBM_PERIPHID3; +typedef union RBBM_CNTL regRBBM_CNTL; +typedef union RBBM_SKEW_CNTL regRBBM_SKEW_CNTL; +typedef union RBBM_SOFT_RESET regRBBM_SOFT_RESET; +typedef union RBBM_PM_OVERRIDE1 regRBBM_PM_OVERRIDE1; +typedef union RBBM_PM_OVERRIDE2 regRBBM_PM_OVERRIDE2; +typedef union GC_SYS_IDLE regGC_SYS_IDLE; +typedef union NQWAIT_UNTIL regNQWAIT_UNTIL; +typedef union RBBM_DEBUG regRBBM_DEBUG; +typedef union RBBM_READ_ERROR regRBBM_READ_ERROR; +typedef union RBBM_WAIT_IDLE_CLOCKS regRBBM_WAIT_IDLE_CLOCKS; +typedef union RBBM_INT_CNTL regRBBM_INT_CNTL; +typedef union RBBM_INT_STATUS regRBBM_INT_STATUS; +typedef union RBBM_INT_ACK regRBBM_INT_ACK; +typedef union MASTER_INT_SIGNAL regMASTER_INT_SIGNAL; +typedef union RBBM_PERFCOUNTER1_SELECT regRBBM_PERFCOUNTER1_SELECT; +typedef union RBBM_PERFCOUNTER1_LO regRBBM_PERFCOUNTER1_LO; +typedef union RBBM_PERFCOUNTER1_HI regRBBM_PERFCOUNTER1_HI; +typedef union CP_RB_BASE regCP_RB_BASE; +typedef union CP_RB_CNTL regCP_RB_CNTL; +typedef union CP_RB_RPTR_ADDR regCP_RB_RPTR_ADDR; +typedef union CP_RB_RPTR regCP_RB_RPTR; +typedef union CP_RB_RPTR_WR regCP_RB_RPTR_WR; +typedef union CP_RB_WPTR regCP_RB_WPTR; +typedef union CP_RB_WPTR_DELAY regCP_RB_WPTR_DELAY; +typedef union CP_RB_WPTR_BASE regCP_RB_WPTR_BASE; +typedef union CP_IB1_BASE regCP_IB1_BASE; +typedef union CP_IB1_BUFSZ regCP_IB1_BUFSZ; +typedef union CP_IB2_BASE regCP_IB2_BASE; +typedef union CP_IB2_BUFSZ regCP_IB2_BUFSZ; +typedef union CP_ST_BASE regCP_ST_BASE; +typedef union CP_ST_BUFSZ regCP_ST_BUFSZ; +typedef union CP_QUEUE_THRESHOLDS regCP_QUEUE_THRESHOLDS; +typedef union CP_MEQ_THRESHOLDS regCP_MEQ_THRESHOLDS; +typedef union CP_CSQ_AVAIL regCP_CSQ_AVAIL; +typedef union CP_STQ_AVAIL regCP_STQ_AVAIL; +typedef union CP_MEQ_AVAIL regCP_MEQ_AVAIL; +typedef union CP_CSQ_RB_STAT regCP_CSQ_RB_STAT; +typedef union CP_CSQ_IB1_STAT regCP_CSQ_IB1_STAT; +typedef union CP_CSQ_IB2_STAT regCP_CSQ_IB2_STAT; +typedef union CP_NON_PREFETCH_CNTRS regCP_NON_PREFETCH_CNTRS; +typedef union CP_STQ_ST_STAT regCP_STQ_ST_STAT; +typedef union CP_MEQ_STAT regCP_MEQ_STAT; +typedef union CP_MIU_TAG_STAT regCP_MIU_TAG_STAT; +typedef union CP_CMD_INDEX regCP_CMD_INDEX; +typedef union CP_CMD_DATA regCP_CMD_DATA; +typedef union CP_ME_CNTL regCP_ME_CNTL; +typedef union CP_ME_STATUS regCP_ME_STATUS; +typedef union CP_ME_RAM_WADDR regCP_ME_RAM_WADDR; +typedef union CP_ME_RAM_RADDR regCP_ME_RAM_RADDR; +typedef union CP_ME_RAM_DATA regCP_ME_RAM_DATA; +typedef union CP_ME_RDADDR regCP_ME_RDADDR; +typedef union CP_DEBUG regCP_DEBUG; +typedef union SCRATCH_REG0 regSCRATCH_REG0; +typedef union GUI_SCRATCH_REG0 regGUI_SCRATCH_REG0; +typedef union SCRATCH_REG1 regSCRATCH_REG1; +typedef union GUI_SCRATCH_REG1 regGUI_SCRATCH_REG1; +typedef union SCRATCH_REG2 regSCRATCH_REG2; +typedef union GUI_SCRATCH_REG2 regGUI_SCRATCH_REG2; +typedef union SCRATCH_REG3 regSCRATCH_REG3; +typedef union GUI_SCRATCH_REG3 regGUI_SCRATCH_REG3; +typedef union SCRATCH_REG4 regSCRATCH_REG4; +typedef union GUI_SCRATCH_REG4 regGUI_SCRATCH_REG4; +typedef union SCRATCH_REG5 regSCRATCH_REG5; +typedef union GUI_SCRATCH_REG5 regGUI_SCRATCH_REG5; +typedef union SCRATCH_REG6 regSCRATCH_REG6; +typedef union GUI_SCRATCH_REG6 regGUI_SCRATCH_REG6; +typedef union SCRATCH_REG7 regSCRATCH_REG7; +typedef union GUI_SCRATCH_REG7 regGUI_SCRATCH_REG7; +typedef union SCRATCH_UMSK regSCRATCH_UMSK; +typedef union SCRATCH_ADDR regSCRATCH_ADDR; +typedef union CP_ME_VS_EVENT_SRC regCP_ME_VS_EVENT_SRC; +typedef union CP_ME_VS_EVENT_ADDR regCP_ME_VS_EVENT_ADDR; +typedef union CP_ME_VS_EVENT_DATA regCP_ME_VS_EVENT_DATA; +typedef union CP_ME_VS_EVENT_ADDR_SWM regCP_ME_VS_EVENT_ADDR_SWM; +typedef union CP_ME_VS_EVENT_DATA_SWM regCP_ME_VS_EVENT_DATA_SWM; +typedef union CP_ME_PS_EVENT_SRC regCP_ME_PS_EVENT_SRC; +typedef union CP_ME_PS_EVENT_ADDR regCP_ME_PS_EVENT_ADDR; +typedef union CP_ME_PS_EVENT_DATA regCP_ME_PS_EVENT_DATA; +typedef union CP_ME_PS_EVENT_ADDR_SWM regCP_ME_PS_EVENT_ADDR_SWM; +typedef union CP_ME_PS_EVENT_DATA_SWM regCP_ME_PS_EVENT_DATA_SWM; +typedef union CP_ME_CF_EVENT_SRC regCP_ME_CF_EVENT_SRC; +typedef union CP_ME_CF_EVENT_ADDR regCP_ME_CF_EVENT_ADDR; +typedef union CP_ME_CF_EVENT_DATA regCP_ME_CF_EVENT_DATA; +typedef union CP_ME_NRT_ADDR regCP_ME_NRT_ADDR; +typedef union CP_ME_NRT_DATA regCP_ME_NRT_DATA; +typedef union CP_ME_VS_FETCH_DONE_SRC regCP_ME_VS_FETCH_DONE_SRC; +typedef union CP_ME_VS_FETCH_DONE_ADDR regCP_ME_VS_FETCH_DONE_ADDR; +typedef union CP_ME_VS_FETCH_DONE_DATA regCP_ME_VS_FETCH_DONE_DATA; +typedef union CP_INT_CNTL regCP_INT_CNTL; +typedef union CP_INT_STATUS regCP_INT_STATUS; +typedef union CP_INT_ACK regCP_INT_ACK; +typedef union CP_PFP_UCODE_ADDR regCP_PFP_UCODE_ADDR; +typedef union CP_PFP_UCODE_DATA regCP_PFP_UCODE_DATA; +typedef union CP_PERFMON_CNTL regCP_PERFMON_CNTL; +typedef union CP_PERFCOUNTER_SELECT regCP_PERFCOUNTER_SELECT; +typedef union CP_PERFCOUNTER_LO regCP_PERFCOUNTER_LO; +typedef union CP_PERFCOUNTER_HI regCP_PERFCOUNTER_HI; +typedef union CP_BIN_MASK_LO regCP_BIN_MASK_LO; +typedef union CP_BIN_MASK_HI regCP_BIN_MASK_HI; +typedef union CP_BIN_SELECT_LO regCP_BIN_SELECT_LO; +typedef union CP_BIN_SELECT_HI regCP_BIN_SELECT_HI; +typedef union CP_NV_FLAGS_0 regCP_NV_FLAGS_0; +typedef union CP_NV_FLAGS_1 regCP_NV_FLAGS_1; +typedef union CP_NV_FLAGS_2 regCP_NV_FLAGS_2; +typedef union CP_NV_FLAGS_3 regCP_NV_FLAGS_3; +typedef union CP_STATE_DEBUG_INDEX regCP_STATE_DEBUG_INDEX; +typedef union CP_STATE_DEBUG_DATA regCP_STATE_DEBUG_DATA; +typedef union CP_PROG_COUNTER regCP_PROG_COUNTER; +typedef union CP_STAT regCP_STAT; +typedef union BIOS_0_SCRATCH regBIOS_0_SCRATCH; +typedef union BIOS_1_SCRATCH regBIOS_1_SCRATCH; +typedef union BIOS_2_SCRATCH regBIOS_2_SCRATCH; +typedef union BIOS_3_SCRATCH regBIOS_3_SCRATCH; +typedef union BIOS_4_SCRATCH regBIOS_4_SCRATCH; +typedef union BIOS_5_SCRATCH regBIOS_5_SCRATCH; +typedef union BIOS_6_SCRATCH regBIOS_6_SCRATCH; +typedef union BIOS_7_SCRATCH regBIOS_7_SCRATCH; +typedef union BIOS_8_SCRATCH regBIOS_8_SCRATCH; +typedef union BIOS_9_SCRATCH regBIOS_9_SCRATCH; +typedef union BIOS_10_SCRATCH regBIOS_10_SCRATCH; +typedef union BIOS_11_SCRATCH regBIOS_11_SCRATCH; +typedef union BIOS_12_SCRATCH regBIOS_12_SCRATCH; +typedef union BIOS_13_SCRATCH regBIOS_13_SCRATCH; +typedef union BIOS_14_SCRATCH regBIOS_14_SCRATCH; +typedef union BIOS_15_SCRATCH regBIOS_15_SCRATCH; +typedef union COHER_SIZE_PM4 regCOHER_SIZE_PM4; +typedef union COHER_BASE_PM4 regCOHER_BASE_PM4; +typedef union COHER_STATUS_PM4 regCOHER_STATUS_PM4; +typedef union COHER_SIZE_HOST regCOHER_SIZE_HOST; +typedef union COHER_BASE_HOST regCOHER_BASE_HOST; +typedef union COHER_STATUS_HOST regCOHER_STATUS_HOST; +typedef union COHER_DEST_BASE_0 regCOHER_DEST_BASE_0; +typedef union COHER_DEST_BASE_1 regCOHER_DEST_BASE_1; +typedef union COHER_DEST_BASE_2 regCOHER_DEST_BASE_2; +typedef union COHER_DEST_BASE_3 regCOHER_DEST_BASE_3; +typedef union COHER_DEST_BASE_4 regCOHER_DEST_BASE_4; +typedef union COHER_DEST_BASE_5 regCOHER_DEST_BASE_5; +typedef union COHER_DEST_BASE_6 regCOHER_DEST_BASE_6; +typedef union COHER_DEST_BASE_7 regCOHER_DEST_BASE_7; +typedef union RB_SURFACE_INFO regRB_SURFACE_INFO; +typedef union RB_COLOR_INFO regRB_COLOR_INFO; +typedef union RB_DEPTH_INFO regRB_DEPTH_INFO; +typedef union RB_STENCILREFMASK regRB_STENCILREFMASK; +typedef union RB_ALPHA_REF regRB_ALPHA_REF; +typedef union RB_COLOR_MASK regRB_COLOR_MASK; +typedef union RB_BLEND_RED regRB_BLEND_RED; +typedef union RB_BLEND_GREEN regRB_BLEND_GREEN; +typedef union RB_BLEND_BLUE regRB_BLEND_BLUE; +typedef union RB_BLEND_ALPHA regRB_BLEND_ALPHA; +typedef union RB_FOG_COLOR regRB_FOG_COLOR; +typedef union RB_STENCILREFMASK_BF regRB_STENCILREFMASK_BF; +typedef union RB_DEPTHCONTROL regRB_DEPTHCONTROL; +typedef union RB_BLENDCONTROL regRB_BLENDCONTROL; +typedef union RB_COLORCONTROL regRB_COLORCONTROL; +typedef union RB_MODECONTROL regRB_MODECONTROL; +typedef union RB_COLOR_DEST_MASK regRB_COLOR_DEST_MASK; +typedef union RB_COPY_CONTROL regRB_COPY_CONTROL; +typedef union RB_COPY_DEST_BASE regRB_COPY_DEST_BASE; +typedef union RB_COPY_DEST_PITCH regRB_COPY_DEST_PITCH; +typedef union RB_COPY_DEST_INFO regRB_COPY_DEST_INFO; +typedef union RB_COPY_DEST_PIXEL_OFFSET regRB_COPY_DEST_PIXEL_OFFSET; +typedef union RB_DEPTH_CLEAR regRB_DEPTH_CLEAR; +typedef union RB_SAMPLE_COUNT_CTL regRB_SAMPLE_COUNT_CTL; +typedef union RB_SAMPLE_COUNT_ADDR regRB_SAMPLE_COUNT_ADDR; +typedef union RB_BC_CONTROL regRB_BC_CONTROL; +typedef union RB_EDRAM_INFO regRB_EDRAM_INFO; +typedef union RB_CRC_RD_PORT regRB_CRC_RD_PORT; +typedef union RB_CRC_CONTROL regRB_CRC_CONTROL; +typedef union RB_CRC_MASK regRB_CRC_MASK; +typedef union RB_PERFCOUNTER0_SELECT regRB_PERFCOUNTER0_SELECT; +typedef union RB_PERFCOUNTER0_LOW regRB_PERFCOUNTER0_LOW; +typedef union RB_PERFCOUNTER0_HI regRB_PERFCOUNTER0_HI; +typedef union RB_TOTAL_SAMPLES regRB_TOTAL_SAMPLES; +typedef union RB_ZPASS_SAMPLES regRB_ZPASS_SAMPLES; +typedef union RB_ZFAIL_SAMPLES regRB_ZFAIL_SAMPLES; +typedef union RB_SFAIL_SAMPLES regRB_SFAIL_SAMPLES; +typedef union RB_DEBUG_0 regRB_DEBUG_0; +typedef union RB_DEBUG_1 regRB_DEBUG_1; +typedef union RB_DEBUG_2 regRB_DEBUG_2; +typedef union RB_DEBUG_3 regRB_DEBUG_3; +typedef union RB_DEBUG_4 regRB_DEBUG_4; +typedef union RB_FLAG_CONTROL regRB_FLAG_CONTROL; +typedef union BC_DUMMY_CRAYRB_ENUMS regBC_DUMMY_CRAYRB_ENUMS; +typedef union BC_DUMMY_CRAYRB_MOREENUMS regBC_DUMMY_CRAYRB_MOREENUMS; +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h new file mode 100644 index 000000000000..15cfbebf2907 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h @@ -0,0 +1,1897 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_ENUM_HEADER) +#define _yamato_ENUM_HEADER + + + +#ifndef _DRIVER_BUILD +#ifndef GL_ZERO +#define GL__ZERO BLEND_ZERO +#define GL__ONE BLEND_ONE +#define GL__SRC_COLOR BLEND_SRC_COLOR +#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR +#define GL__DST_COLOR BLEND_DST_COLOR +#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR +#define GL__SRC_ALPHA BLEND_SRC_ALPHA +#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA +#define GL__DST_ALPHA BLEND_DST_ALPHA +#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA +#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE +#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR +#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR +#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA +#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA +#endif +#endif + +/******************************************************* + * PA Enums + *******************************************************/ +#ifndef ENUMS_SU_PERFCNT_SELECT_H +#define ENUMS_SU_PERFCNT_SELECT_H +typedef enum SU_PERFCNT_SELECT { + PERF_PAPC_PASX_REQ = 0, + UNUSED1 = 1, + PERF_PAPC_PASX_FIRST_VECTOR = 2, + PERF_PAPC_PASX_SECOND_VECTOR = 3, + PERF_PAPC_PASX_FIRST_DEAD = 4, + PERF_PAPC_PASX_SECOND_DEAD = 5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, + PERF_PAPC_PA_INPUT_PRIM = 8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, + PERF_PAPC_CLPR_CULL_PRIM = 13, + UNUSED2 = 14, + PERF_PAPC_CLPR_VV_CULL_PRIM = 15, + UNUSED3 = 16, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, + UNUSED4 = 20, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, + UNUSED5 = 22, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, + PERF_PAPC_CLSM_NULL_PRIM = 36, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, + PERF_PAPC_CLSM_CLIP_PRIM = 38, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, + PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, + PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, + PERF_PAPC_SU_INPUT_PRIM = 47, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, + PERF_PAPC_SU_INPUT_NULL_PRIM = 49, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, + PERF_PAPC_SU_OUTPUT_PRIM = 57, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, + PERF_PAPC_PASX_REQ_IDLE = 69, + PERF_PAPC_PASX_REQ_BUSY = 70, + PERF_PAPC_PASX_REQ_STALLED = 71, + PERF_PAPC_PASX_REC_IDLE = 72, + PERF_PAPC_PASX_REC_BUSY = 73, + PERF_PAPC_PASX_REC_STARVED_SX = 74, + PERF_PAPC_PASX_REC_STALLED = 75, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, + PERF_PAPC_CCGSM_IDLE = 78, + PERF_PAPC_CCGSM_BUSY = 79, + PERF_PAPC_CCGSM_STALLED = 80, + PERF_PAPC_CLPRIM_IDLE = 81, + PERF_PAPC_CLPRIM_BUSY = 82, + PERF_PAPC_CLPRIM_STALLED = 83, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, + PERF_PAPC_CLIPSM_IDLE = 85, + PERF_PAPC_CLIPSM_BUSY = 86, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, + PERF_PAPC_CLIPGA_IDLE = 92, + PERF_PAPC_CLIPGA_BUSY = 93, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, + PERF_PAPC_CLIPGA_STALLED = 95, + PERF_PAPC_CLIP_IDLE = 96, + PERF_PAPC_CLIP_BUSY = 97, + PERF_PAPC_SU_IDLE = 98, + PERF_PAPC_SU_BUSY = 99, + PERF_PAPC_SU_STARVED_CLIP = 100, + PERF_PAPC_SU_STALLED_SC = 101, + PERF_PAPC_SU_FACENESS_CULL = 102, +} SU_PERFCNT_SELECT; +#endif /*ENUMS_SU_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SC_PERFCNT_SELECT_H +#define ENUMS_SC_PERFCNT_SELECT_H +typedef enum SC_PERFCNT_SELECT { + SC_SR_WINDOW_VALID = 0, + SC_CW_WINDOW_VALID = 1, + SC_QM_WINDOW_VALID = 2, + SC_FW_WINDOW_VALID = 3, + SC_EZ_WINDOW_VALID = 4, + SC_IT_WINDOW_VALID = 5, + SC_STARVED_BY_PA = 6, + SC_STALLED_BY_RB_TILE = 7, + SC_STALLED_BY_RB_SAMP = 8, + SC_STARVED_BY_RB_EZ = 9, + SC_STALLED_BY_SAMPLE_FF = 10, + SC_STALLED_BY_SQ = 11, + SC_STALLED_BY_SP = 12, + SC_TOTAL_NO_PRIMS = 13, + SC_NON_EMPTY_PRIMS = 14, + SC_NO_TILES_PASSING_QM = 15, + SC_NO_PIXELS_PRE_EZ = 16, + SC_NO_PIXELS_POST_EZ = 17, +} SC_PERFCNT_SELECT; +#endif /*ENUMS_SC_PERFCNT_SELECT_H*/ + +/******************************************************* + * VGT Enums + *******************************************************/ +#ifndef ENUMS_VGT_DI_PRIM_TYPE_H +#define ENUMS_VGT_DI_PRIM_TYPE_H +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0, + DI_PT_POINTLIST = 1, + DI_PT_LINELIST = 2, + DI_PT_LINESTRIP = 3, + DI_PT_TRILIST = 4, + DI_PT_TRIFAN = 5, + DI_PT_TRISTRIP = 6, + DI_PT_UNUSED_1 = 7, + DI_PT_RECTLIST = 8, + DI_PT_UNUSED_2 = 9, + DI_PT_UNUSED_3 = 10, + DI_PT_UNUSED_4 = 11, + DI_PT_UNUSED_5 = 12, + DI_PT_QUADLIST = 13, + DI_PT_QUADSTRIP = 14, + DI_PT_POLYGON = 15, + DI_PT_2D_COPY_RECT_LIST_V0 = 16, + DI_PT_2D_COPY_RECT_LIST_V1 = 17, + DI_PT_2D_COPY_RECT_LIST_V2 = 18, + DI_PT_2D_COPY_RECT_LIST_V3 = 19, + DI_PT_2D_FILL_RECT_LIST = 20, + DI_PT_2D_LINE_STRIP = 21, + DI_PT_2D_TRI_STRIP = 22, +} VGT_DI_PRIM_TYPE; +#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/ + +#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H +#define ENUMS_VGT_DI_SOURCE_SELECT_H +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0, + DI_SRC_SEL_IMMEDIATE = 1, + DI_SRC_SEL_AUTO_INDEX = 2, + DI_SRC_SEL_RESERVED = 3 +} VGT_DI_SOURCE_SELECT; +#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +typedef enum VGT_DI_FACENESS_CULL_SELECT { + DI_FACE_CULL_NONE = 0, + DI_FACE_CULL_FETCH = 1, + DI_FACE_BACKFACE_CULL = 2, + DI_FACE_FRONTFACE_CULL = 3 +} VGT_DI_FACENESS_CULL_SELECT; +#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_INDEX_SIZE_H +#define ENUMS_VGT_DI_INDEX_SIZE_H +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0, + DI_INDEX_SIZE_32_BIT = 1 +} VGT_DI_INDEX_SIZE; +#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/ + +#ifndef ENUMS_VGT_DI_SMALL_INDEX_H +#define ENUMS_VGT_DI_SMALL_INDEX_H +typedef enum VGT_DI_SMALL_INDEX { + DI_USE_INDEX_SIZE = 0, + DI_INDEX_SIZE_8_BIT = 1 +} VGT_DI_SMALL_INDEX; +#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/ + +#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE { + DISABLE_PRE_FETCH_CULL_ENABLE = 0, + PRE_FETCH_CULL_ENABLE = 1 +} VGT_DI_PRE_FETCH_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H +#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H +typedef enum VGT_DI_GRP_CULL_ENABLE { + DISABLE_GRP_CULL_ENABLE = 0, + GRP_CULL_ENABLE = 1 +} VGT_DI_GRP_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_EVENT_TYPE_H +#define ENUMS_VGT_EVENT_TYPE_H +typedef enum VGT_EVENT_TYPE { + VS_DEALLOC = 0, + PS_DEALLOC = 1, + VS_DONE_TS = 2, + PS_DONE_TS = 3, + CACHE_FLUSH_TS = 4, + CONTEXT_DONE = 5, + CACHE_FLUSH = 6, + VIZQUERY_START = 7, + VIZQUERY_END = 8, + SC_WAIT_WC = 9, + RST_PIX_CNT = 13, + RST_VTX_CNT = 14, + TILE_FLUSH = 15, + CACHE_FLUSH_AND_INV_TS_EVENT = 20, + ZPASS_DONE = 21, + CACHE_FLUSH_AND_INV_EVENT = 22, + PERFCOUNTER_START = 23, + PERFCOUNTER_STOP = 24, + VS_FETCH_DONE = 27, + FACENESS_FLUSH = 28, +} VGT_EVENT_TYPE; +#endif /*ENUMS_VGT_EVENT_TYPE_H*/ + +#ifndef ENUMS_VGT_DMA_SWAP_MODE_H +#define ENUMS_VGT_DMA_SWAP_MODE_H +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0, + VGT_DMA_SWAP_16_BIT = 1, + VGT_DMA_SWAP_32_BIT = 2, + VGT_DMA_SWAP_WORD = 3 +} VGT_DMA_SWAP_MODE; +#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/ + +#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H +#define ENUMS_VGT_PERFCOUNT_SELECT_H +typedef enum VGT_PERFCOUNT_SELECT { + VGT_SQ_EVENT_WINDOW_ACTIVE = 0, + VGT_SQ_SEND = 1, + VGT_SQ_STALLED = 2, + VGT_SQ_STARVED_BUSY = 3, + VGT_SQ_STARVED_IDLE = 4, + VGT_SQ_STATIC = 5, + VGT_PA_EVENT_WINDOW_ACTIVE = 6, + VGT_PA_CLIP_V_SEND = 7, + VGT_PA_CLIP_V_STALLED = 8, + VGT_PA_CLIP_V_STARVED_BUSY = 9, + VGT_PA_CLIP_V_STARVED_IDLE = 10, + VGT_PA_CLIP_V_STATIC = 11, + VGT_PA_CLIP_P_SEND = 12, + VGT_PA_CLIP_P_STALLED = 13, + VGT_PA_CLIP_P_STARVED_BUSY = 14, + VGT_PA_CLIP_P_STARVED_IDLE = 15, + VGT_PA_CLIP_P_STATIC = 16, + VGT_PA_CLIP_S_SEND = 17, + VGT_PA_CLIP_S_STALLED = 18, + VGT_PA_CLIP_S_STARVED_BUSY = 19, + VGT_PA_CLIP_S_STARVED_IDLE = 20, + VGT_PA_CLIP_S_STATIC = 21, + RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, + RBIU_IMMED_DATA_FIFO_STARVED = 23, + RBIU_IMMED_DATA_FIFO_STALLED = 24, + RBIU_DMA_REQUEST_FIFO_STARVED = 25, + RBIU_DMA_REQUEST_FIFO_STALLED = 26, + RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, + RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, + BIN_PRIM_NEAR_CULL = 29, + BIN_PRIM_ZERO_CULL = 30, + BIN_PRIM_FAR_CULL = 31, + BIN_PRIM_BIN_CULL = 32, + BIN_PRIM_FACE_CULL = 33, + SPARE34 = 34, + SPARE35 = 35, + SPARE36 = 36, + SPARE37 = 37, + SPARE38 = 38, + SPARE39 = 39, + TE_SU_IN_VALID = 40, + TE_SU_IN_READ = 41, + TE_SU_IN_PRIM = 42, + TE_SU_IN_EOP = 43, + TE_SU_IN_NULL_PRIM = 44, + TE_WK_IN_VALID = 45, + TE_WK_IN_READ = 46, + TE_OUT_PRIM_VALID = 47, + TE_OUT_PRIM_READ = 48, +} VGT_PERFCOUNT_SELECT; +#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TP Enums + *******************************************************/ +#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H +#define ENUMS_TCR_PERFCOUNT_SELECT_H +typedef enum TCR_PERFCOUNT_SELECT { + DGMMPD_IPMUX0_STALL = 0, + reserved_46 = 1, + reserved_47 = 2, + reserved_48 = 3, + DGMMPD_IPMUX_ALL_STALL = 4, + OPMUX0_L2_WRITES = 5, + reserved_49 = 6, + reserved_50 = 7, + reserved_51 = 8, +} TCR_PERFCOUNT_SELECT; +#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TP_PERFCOUNT_SELECT_H +#define ENUMS_TP_PERFCOUNT_SELECT_H +typedef enum TP_PERFCOUNT_SELECT { + POINT_QUADS = 0, + BILIN_QUADS = 1, + ANISO_QUADS = 2, + MIP_QUADS = 3, + VOL_QUADS = 4, + MIP_VOL_QUADS = 5, + MIP_ANISO_QUADS = 6, + VOL_ANISO_QUADS = 7, + ANISO_2_1_QUADS = 8, + ANISO_4_1_QUADS = 9, + ANISO_6_1_QUADS = 10, + ANISO_8_1_QUADS = 11, + ANISO_10_1_QUADS = 12, + ANISO_12_1_QUADS = 13, + ANISO_14_1_QUADS = 14, + ANISO_16_1_QUADS = 15, + MIP_VOL_ANISO_QUADS = 16, + ALIGN_2_QUADS = 17, + ALIGN_4_QUADS = 18, + PIX_0_QUAD = 19, + PIX_1_QUAD = 20, + PIX_2_QUAD = 21, + PIX_3_QUAD = 22, + PIX_4_QUAD = 23, + TP_MIPMAP_LOD0 = 24, + TP_MIPMAP_LOD1 = 25, + TP_MIPMAP_LOD2 = 26, + TP_MIPMAP_LOD3 = 27, + TP_MIPMAP_LOD4 = 28, + TP_MIPMAP_LOD5 = 29, + TP_MIPMAP_LOD6 = 30, + TP_MIPMAP_LOD7 = 31, + TP_MIPMAP_LOD8 = 32, + TP_MIPMAP_LOD9 = 33, + TP_MIPMAP_LOD10 = 34, + TP_MIPMAP_LOD11 = 35, + TP_MIPMAP_LOD12 = 36, + TP_MIPMAP_LOD13 = 37, + TP_MIPMAP_LOD14 = 38, +} TP_PERFCOUNT_SELECT; +#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H +#define ENUMS_TCM_PERFCOUNT_SELECT_H +typedef enum TCM_PERFCOUNT_SELECT { + QUAD0_RD_LAT_FIFO_EMPTY = 0, + reserved_01 = 1, + reserved_02 = 2, + QUAD0_RD_LAT_FIFO_4TH_FULL = 3, + QUAD0_RD_LAT_FIFO_HALF_FULL = 4, + QUAD0_RD_LAT_FIFO_FULL = 5, + QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, + reserved_07 = 7, + reserved_08 = 8, + reserved_09 = 9, + reserved_10 = 10, + reserved_11 = 11, + reserved_12 = 12, + reserved_13 = 13, + reserved_14 = 14, + reserved_15 = 15, + reserved_16 = 16, + reserved_17 = 17, + reserved_18 = 18, + reserved_19 = 19, + reserved_20 = 20, + reserved_21 = 21, + reserved_22 = 22, + reserved_23 = 23, + reserved_24 = 24, + reserved_25 = 25, + reserved_26 = 26, + reserved_27 = 27, + READ_STARVED_QUAD0 = 28, + reserved_29 = 29, + reserved_30 = 30, + reserved_31 = 31, + READ_STARVED = 32, + READ_STALLED_QUAD0 = 33, + reserved_34 = 34, + reserved_35 = 35, + reserved_36 = 36, + READ_STALLED = 37, + VALID_READ_QUAD0 = 38, + reserved_39 = 39, + reserved_40 = 40, + reserved_41 = 41, + TC_TP_STARVED_QUAD0 = 42, + reserved_43 = 43, + reserved_44 = 44, + reserved_45 = 45, + TC_TP_STARVED = 46, +} TCM_PERFCOUNT_SELECT; +#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H +#define ENUMS_TCF_PERFCOUNT_SELECT_H +typedef enum TCF_PERFCOUNT_SELECT { + VALID_CYCLES = 0, + SINGLE_PHASES = 1, + ANISO_PHASES = 2, + MIP_PHASES = 3, + VOL_PHASES = 4, + MIP_VOL_PHASES = 5, + MIP_ANISO_PHASES = 6, + VOL_ANISO_PHASES = 7, + ANISO_2_1_PHASES = 8, + ANISO_4_1_PHASES = 9, + ANISO_6_1_PHASES = 10, + ANISO_8_1_PHASES = 11, + ANISO_10_1_PHASES = 12, + ANISO_12_1_PHASES = 13, + ANISO_14_1_PHASES = 14, + ANISO_16_1_PHASES = 15, + MIP_VOL_ANISO_PHASES = 16, + ALIGN_2_PHASES = 17, + ALIGN_4_PHASES = 18, + TPC_BUSY = 19, + TPC_STALLED = 20, + TPC_STARVED = 21, + TPC_WORKING = 22, + TPC_WALKER_BUSY = 23, + TPC_WALKER_STALLED = 24, + TPC_WALKER_WORKING = 25, + TPC_ALIGNER_BUSY = 26, + TPC_ALIGNER_STALLED = 27, + TPC_ALIGNER_STALLED_BY_BLEND = 28, + TPC_ALIGNER_STALLED_BY_CACHE = 29, + TPC_ALIGNER_WORKING = 30, + TPC_BLEND_BUSY = 31, + TPC_BLEND_SYNC = 32, + TPC_BLEND_STARVED = 33, + TPC_BLEND_WORKING = 34, + OPCODE_0x00 = 35, + OPCODE_0x01 = 36, + OPCODE_0x04 = 37, + OPCODE_0x10 = 38, + OPCODE_0x11 = 39, + OPCODE_0x12 = 40, + OPCODE_0x13 = 41, + OPCODE_0x18 = 42, + OPCODE_0x19 = 43, + OPCODE_0x1A = 44, + OPCODE_OTHER = 45, + IN_FIFO_0_EMPTY = 56, + IN_FIFO_0_LT_HALF_FULL = 57, + IN_FIFO_0_HALF_FULL = 58, + IN_FIFO_0_FULL = 59, + IN_FIFO_TPC_EMPTY = 72, + IN_FIFO_TPC_LT_HALF_FULL = 73, + IN_FIFO_TPC_HALF_FULL = 74, + IN_FIFO_TPC_FULL = 75, + TPC_TC_XFC = 76, + TPC_TC_STATE = 77, + TC_STALL = 78, + QUAD0_TAPS = 79, + QUADS = 83, + TCA_SYNC_STALL = 84, + TAG_STALL = 85, + TCB_SYNC_STALL = 88, + TCA_VALID = 89, + PROBES_VALID = 90, + MISS_STALL = 91, + FETCH_FIFO_STALL = 92, + TCO_STALL = 93, + ANY_STALL = 94, + TAG_MISSES = 95, + TAG_HITS = 96, + SUB_TAG_MISSES = 97, + SET0_INVALIDATES = 98, + SET1_INVALIDATES = 99, + SET2_INVALIDATES = 100, + SET3_INVALIDATES = 101, + SET0_TAG_MISSES = 102, + SET1_TAG_MISSES = 103, + SET2_TAG_MISSES = 104, + SET3_TAG_MISSES = 105, + SET0_TAG_HITS = 106, + SET1_TAG_HITS = 107, + SET2_TAG_HITS = 108, + SET3_TAG_HITS = 109, + SET0_SUB_TAG_MISSES = 110, + SET1_SUB_TAG_MISSES = 111, + SET2_SUB_TAG_MISSES = 112, + SET3_SUB_TAG_MISSES = 113, + SET0_EVICT1 = 114, + SET0_EVICT2 = 115, + SET0_EVICT3 = 116, + SET0_EVICT4 = 117, + SET0_EVICT5 = 118, + SET0_EVICT6 = 119, + SET0_EVICT7 = 120, + SET0_EVICT8 = 121, + SET1_EVICT1 = 130, + SET1_EVICT2 = 131, + SET1_EVICT3 = 132, + SET1_EVICT4 = 133, + SET1_EVICT5 = 134, + SET1_EVICT6 = 135, + SET1_EVICT7 = 136, + SET1_EVICT8 = 137, + SET2_EVICT1 = 146, + SET2_EVICT2 = 147, + SET2_EVICT3 = 148, + SET2_EVICT4 = 149, + SET2_EVICT5 = 150, + SET2_EVICT6 = 151, + SET2_EVICT7 = 152, + SET2_EVICT8 = 153, + SET3_EVICT1 = 162, + SET3_EVICT2 = 163, + SET3_EVICT3 = 164, + SET3_EVICT4 = 165, + SET3_EVICT5 = 166, + SET3_EVICT6 = 167, + SET3_EVICT7 = 168, + SET3_EVICT8 = 169, + FF_EMPTY = 178, + FF_LT_HALF_FULL = 179, + FF_HALF_FULL = 180, + FF_FULL = 181, + FF_XFC = 182, + FF_STALLED = 183, + FG_MASKS = 184, + FG_LEFT_MASKS = 185, + FG_LEFT_MASK_STALLED = 186, + FG_LEFT_NOT_DONE_STALL = 187, + FG_LEFT_FG_STALL = 188, + FG_LEFT_SECTORS = 189, + FG0_REQUESTS = 195, + FG0_STALLED = 196, + MEM_REQ512 = 199, + MEM_REQ_SENT = 200, + MEM_LOCAL_READ_REQ = 202, + TC0_MH_STALLED = 203, +} TCF_PERFCOUNT_SELECT; +#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +#ifndef ENUMS_SQ_PERFCNT_SELECT_H +#define ENUMS_SQ_PERFCNT_SELECT_H +typedef enum SQ_PERFCNT_SELECT { + SQ_PIXEL_VECTORS_SUB = 0, + SQ_VERTEX_VECTORS_SUB = 1, + SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, + SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, + SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, + SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, + SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, + SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, + SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, + SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, + SQ_EXPORT_CYCLES = 10, + SQ_ALU_CST_WRITTEN = 11, + SQ_TEX_CST_WRITTEN = 12, + SQ_ALU_CST_STALL = 13, + SQ_ALU_TEX_STALL = 14, + SQ_INST_WRITTEN = 15, + SQ_BOOLEAN_WRITTEN = 16, + SQ_LOOPS_WRITTEN = 17, + SQ_PIXEL_SWAP_IN = 18, + SQ_PIXEL_SWAP_OUT = 19, + SQ_VERTEX_SWAP_IN = 20, + SQ_VERTEX_SWAP_OUT = 21, + SQ_ALU_VTX_INST_ISSUED = 22, + SQ_TEX_VTX_INST_ISSUED = 23, + SQ_VC_VTX_INST_ISSUED = 24, + SQ_CF_VTX_INST_ISSUED = 25, + SQ_ALU_PIX_INST_ISSUED = 26, + SQ_TEX_PIX_INST_ISSUED = 27, + SQ_VC_PIX_INST_ISSUED = 28, + SQ_CF_PIX_INST_ISSUED = 29, + SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, + SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, + SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, + SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, + SQ_ALU_NOPS = 34, + SQ_PRED_SKIP = 35, + SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, + SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, + SQ_SYNC_TEX_STALL_VTX = 38, + SQ_SYNC_VC_STALL_VTX = 39, + SQ_CONSTANTS_USED_SIMD0 = 40, + SQ_CONSTANTS_SENT_SP_SIMD0 = 41, + SQ_GPR_STALL_VTX = 42, + SQ_GPR_STALL_PIX = 43, + SQ_VTX_RS_STALL = 44, + SQ_PIX_RS_STALL = 45, + SQ_SX_PC_FULL = 46, + SQ_SX_EXP_BUFF_FULL = 47, + SQ_SX_POS_BUFF_FULL = 48, + SQ_INTERP_QUADS = 49, + SQ_INTERP_ACTIVE = 50, + SQ_IN_PIXEL_STALL = 51, + SQ_IN_VTX_STALL = 52, + SQ_VTX_CNT = 53, + SQ_VTX_VECTOR2 = 54, + SQ_VTX_VECTOR3 = 55, + SQ_VTX_VECTOR4 = 56, + SQ_PIXEL_VECTOR1 = 57, + SQ_PIXEL_VECTOR23 = 58, + SQ_PIXEL_VECTOR4 = 59, + SQ_CONSTANTS_USED_SIMD1 = 60, + SQ_CONSTANTS_SENT_SP_SIMD1 = 61, + SQ_SX_MEM_EXP_FULL = 62, + SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, + SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, + SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, + SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, + SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, + SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, + SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, + SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, + SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, + SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, + SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, + SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, + SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, + SQ_PERFCOUNT_VTX_POP_THREAD = 76, + SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, + SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, + SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, + SQ_PERFCOUNT_PIX_POP_THREAD = 80, + SQ_SYNC_TEX_STALL_PIX = 81, + SQ_SYNC_VC_STALL_PIX = 82, + SQ_CONSTANTS_USED_SIMD2 = 83, + SQ_CONSTANTS_SENT_SP_SIMD2 = 84, + SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, + SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, + SQ_ALU0_FIFO_FULL_SIMD0 = 87, + SQ_ALU1_FIFO_FULL_SIMD0 = 88, + SQ_ALU0_FIFO_FULL_SIMD1 = 89, + SQ_ALU1_FIFO_FULL_SIMD1 = 90, + SQ_ALU0_FIFO_FULL_SIMD2 = 91, + SQ_ALU1_FIFO_FULL_SIMD2 = 92, + SQ_ALU0_FIFO_FULL_SIMD3 = 93, + SQ_ALU1_FIFO_FULL_SIMD3 = 94, + VC_PERF_STATIC = 95, + VC_PERF_STALLED = 96, + VC_PERF_STARVED = 97, + VC_PERF_SEND = 98, + VC_PERF_ACTUAL_STARVED = 99, + PIXEL_THREAD_0_ACTIVE = 100, + VERTEX_THREAD_0_ACTIVE = 101, + PIXEL_THREAD_0_NUMBER = 102, + VERTEX_THREAD_0_NUMBER = 103, + VERTEX_EVENT_NUMBER = 104, + PIXEL_EVENT_NUMBER = 105, + PTRBUFF_EF_PUSH = 106, + PTRBUFF_EF_POP_EVENT = 107, + PTRBUFF_EF_POP_NEW_VTX = 108, + PTRBUFF_EF_POP_DEALLOC = 109, + PTRBUFF_EF_POP_PVECTOR = 110, + PTRBUFF_EF_POP_PVECTOR_X = 111, + PTRBUFF_EF_POP_PVECTOR_VNZ = 112, + PTRBUFF_PB_DEALLOC = 113, + PTRBUFF_PI_STATE_PPB_POP = 114, + PTRBUFF_PI_RTR = 115, + PTRBUFF_PI_READ_EN = 116, + PTRBUFF_PI_BUFF_SWAP = 117, + PTRBUFF_SQ_FREE_BUFF = 118, + PTRBUFF_SQ_DEC = 119, + PTRBUFF_SC_VALID_CNTL_EVENT = 120, + PTRBUFF_SC_VALID_IJ_XFER = 121, + PTRBUFF_SC_NEW_VECTOR_1_Q = 122, + PTRBUFF_QUAL_NEW_VECTOR = 123, + PTRBUFF_QUAL_EVENT = 124, + PTRBUFF_END_BUFFER = 125, + PTRBUFF_FILL_QUAD = 126, + VERTS_WRITTEN_SPI = 127, + TP_FETCH_INSTR_EXEC = 128, + TP_FETCH_INSTR_REQ = 129, + TP_DATA_RETURN = 130, + SPI_WRITE_CYCLES_SP = 131, + SPI_WRITES_SP = 132, + SP_ALU_INSTR_EXEC = 133, + SP_CONST_ADDR_TO_SQ = 134, + SP_PRED_KILLS_TO_SQ = 135, + SP_EXPORT_CYCLES_TO_SX = 136, + SP_EXPORTS_TO_SX = 137, + SQ_CYCLES_ELAPSED = 138, + SQ_TCFS_OPT_ALLOC_EXEC = 139, + SQ_TCFS_NO_OPT_ALLOC = 140, + SQ_ALU0_NO_OPT_ALLOC = 141, + SQ_ALU1_NO_OPT_ALLOC = 142, + SQ_TCFS_ARB_XFC_CNT = 143, + SQ_ALU0_ARB_XFC_CNT = 144, + SQ_ALU1_ARB_XFC_CNT = 145, + SQ_TCFS_CFS_UPDATE_CNT = 146, + SQ_ALU0_CFS_UPDATE_CNT = 147, + SQ_ALU1_CFS_UPDATE_CNT = 148, + SQ_VTX_PUSH_THREAD_CNT = 149, + SQ_VTX_POP_THREAD_CNT = 150, + SQ_PIX_PUSH_THREAD_CNT = 151, + SQ_PIX_POP_THREAD_CNT = 152, + SQ_PIX_TOTAL = 153, + SQ_PIX_KILLED = 154, +} SQ_PERFCNT_SELECT; +#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SX_PERFCNT_SELECT_H +#define ENUMS_SX_PERFCNT_SELECT_H +typedef enum SX_PERFCNT_SELECT { + SX_EXPORT_VECTORS = 0, + SX_DUMMY_QUADS = 1, + SX_ALPHA_FAIL = 2, + SX_RB_QUAD_BUSY = 3, + SX_RB_COLOR_BUSY = 4, + SX_RB_QUAD_STALL = 5, + SX_RB_COLOR_STALL = 6, +} SX_PERFCNT_SELECT; +#endif /*ENUMS_SX_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_Abs_modifier_H +#define ENUMS_Abs_modifier_H +typedef enum Abs_modifier { + NO_ABS_MOD = 0, + ABS_MOD = 1 +} Abs_modifier; +#endif /*ENUMS_Abs_modifier_H*/ + +#ifndef ENUMS_Exporting_H +#define ENUMS_Exporting_H +typedef enum Exporting { + NOT_EXPORTING = 0, + EXPORTING = 1 +} Exporting; +#endif /*ENUMS_Exporting_H*/ + +#ifndef ENUMS_ScalarOpcode_H +#define ENUMS_ScalarOpcode_H +typedef enum ScalarOpcode { + ADDs = 0, + ADD_PREVs = 1, + MULs = 2, + MUL_PREVs = 3, + MUL_PREV2s = 4, + MAXs = 5, + MINs = 6, + SETEs = 7, + SETGTs = 8, + SETGTEs = 9, + SETNEs = 10, + FRACs = 11, + TRUNCs = 12, + FLOORs = 13, + EXP_IEEE = 14, + LOG_CLAMP = 15, + LOG_IEEE = 16, + RECIP_CLAMP = 17, + RECIP_FF = 18, + RECIP_IEEE = 19, + RECIPSQ_CLAMP = 20, + RECIPSQ_FF = 21, + RECIPSQ_IEEE = 22, + MOVAs = 23, + MOVA_FLOORs = 24, + SUBs = 25, + SUB_PREVs = 26, + PRED_SETEs = 27, + PRED_SETNEs = 28, + PRED_SETGTs = 29, + PRED_SETGTEs = 30, + PRED_SET_INVs = 31, + PRED_SET_POPs = 32, + PRED_SET_CLRs = 33, + PRED_SET_RESTOREs = 34, + KILLEs = 35, + KILLGTs = 36, + KILLGTEs = 37, + KILLNEs = 38, + KILLONEs = 39, + SQRT_IEEE = 40, + MUL_CONST_0 = 42, + MUL_CONST_1 = 43, + ADD_CONST_0 = 44, + ADD_CONST_1 = 45, + SUB_CONST_0 = 46, + SUB_CONST_1 = 47, + SIN = 48, + COS = 49, + RETAIN_PREV = 50, +} ScalarOpcode; +#endif /*ENUMS_ScalarOpcode_H*/ + +#ifndef ENUMS_SwizzleType_H +#define ENUMS_SwizzleType_H +typedef enum SwizzleType { + NO_SWIZZLE = 0, + SHIFT_RIGHT_1 = 1, + SHIFT_RIGHT_2 = 2, + SHIFT_RIGHT_3 = 3 +} SwizzleType; +#endif /*ENUMS_SwizzleType_H*/ + +#ifndef ENUMS_InputModifier_H +#define ENUMS_InputModifier_H +typedef enum InputModifier { + NIL = 0, + NEGATE = 1 +} InputModifier; +#endif /*ENUMS_InputModifier_H*/ + +#ifndef ENUMS_PredicateSelect_H +#define ENUMS_PredicateSelect_H +typedef enum PredicateSelect { + NO_PREDICATION = 0, + PREDICATE_QUAD = 1, + PREDICATED_2 = 2, + PREDICATED_3 = 3 +} PredicateSelect; +#endif /*ENUMS_PredicateSelect_H*/ + +#ifndef ENUMS_OperandSelect1_H +#define ENUMS_OperandSelect1_H +typedef enum OperandSelect1 { + ABSOLUTE_REG = 0, + RELATIVE_REG = 1 +} OperandSelect1; +#endif /*ENUMS_OperandSelect1_H*/ + +#ifndef ENUMS_VectorOpcode_H +#define ENUMS_VectorOpcode_H +typedef enum VectorOpcode { + ADDv = 0, + MULv = 1, + MAXv = 2, + MINv = 3, + SETEv = 4, + SETGTv = 5, + SETGTEv = 6, + SETNEv = 7, + FRACv = 8, + TRUNCv = 9, + FLOORv = 10, + MULADDv = 11, + CNDEv = 12, + CNDGTEv = 13, + CNDGTv = 14, + DOT4v = 15, + DOT3v = 16, + DOT2ADDv = 17, + CUBEv = 18, + MAX4v = 19, + PRED_SETE_PUSHv = 20, + PRED_SETNE_PUSHv = 21, + PRED_SETGT_PUSHv = 22, + PRED_SETGTE_PUSHv = 23, + KILLEv = 24, + KILLGTv = 25, + KILLGTEv = 26, + KILLNEv = 27, + DSTv = 28, + MOVAv = 29, +} VectorOpcode; +#endif /*ENUMS_VectorOpcode_H*/ + +#ifndef ENUMS_OperandSelect0_H +#define ENUMS_OperandSelect0_H +typedef enum OperandSelect0 { + CONSTANT = 0, + NON_CONSTANT = 1 +} OperandSelect0; +#endif /*ENUMS_OperandSelect0_H*/ + +#ifndef ENUMS_Ressource_type_H +#define ENUMS_Ressource_type_H +typedef enum Ressource_type { + ALU = 0, + TEXTURE = 1 +} Ressource_type; +#endif /*ENUMS_Ressource_type_H*/ + +#ifndef ENUMS_Instruction_serial_H +#define ENUMS_Instruction_serial_H +typedef enum Instruction_serial { + NOT_SERIAL = 0, + SERIAL = 1 +} Instruction_serial; +#endif /*ENUMS_Instruction_serial_H*/ + +#ifndef ENUMS_VC_type_H +#define ENUMS_VC_type_H +typedef enum VC_type { + ALU_TP_REQUEST = 0, + VC_REQUEST = 1 +} VC_type; +#endif /*ENUMS_VC_type_H*/ + +#ifndef ENUMS_Addressing_H +#define ENUMS_Addressing_H +typedef enum Addressing { + RELATIVE_ADDR = 0, + ABSOLUTE_ADDR = 1 +} Addressing; +#endif /*ENUMS_Addressing_H*/ + +#ifndef ENUMS_CFOpcode_H +#define ENUMS_CFOpcode_H +typedef enum CFOpcode { + NOP = 0, + EXECUTE = 1, + EXECUTE_END = 2, + COND_EXECUTE = 3, + COND_EXECUTE_END = 4, + COND_PRED_EXECUTE = 5, + COND_PRED_EXECUTE_END = 6, + LOOP_START = 7, + LOOP_END = 8, + COND_CALL = 9, + RETURN = 10, + COND_JMP = 11, + ALLOCATE = 12, + COND_EXECUTE_PRED_CLEAN = 13, + COND_EXECUTE_PRED_CLEAN_END = 14, + MARK_VS_FETCH_DONE = 15 +} CFOpcode; +#endif /*ENUMS_CFOpcode_H*/ + +#ifndef ENUMS_Allocation_type_H +#define ENUMS_Allocation_type_H +typedef enum Allocation_type { + SQ_NO_ALLOC = 0, + SQ_POSITION = 1, + SQ_PARAMETER_PIXEL = 2, + SQ_MEMORY = 3 +} Allocation_type; +#endif /*ENUMS_Allocation_type_H*/ + +#ifndef ENUMS_TexInstOpcode_H +#define ENUMS_TexInstOpcode_H +typedef enum TexInstOpcode { + TEX_INST_FETCH = 1, + TEX_INST_RESERVED_1 = 2, + TEX_INST_RESERVED_2 = 3, + TEX_INST_RESERVED_3 = 4, + TEX_INST_GET_BORDER_COLOR_FRAC = 16, + TEX_INST_GET_COMP_TEX_LOD = 17, + TEX_INST_GET_GRADIENTS = 18, + TEX_INST_GET_WEIGHTS = 19, + TEX_INST_SET_TEX_LOD = 24, + TEX_INST_SET_GRADIENTS_H = 25, + TEX_INST_SET_GRADIENTS_V = 26, + TEX_INST_RESERVED_4 = 27, +} TexInstOpcode; +#endif /*ENUMS_TexInstOpcode_H*/ + +#ifndef ENUMS_Addressmode_H +#define ENUMS_Addressmode_H +typedef enum Addressmode { + LOGICAL = 0, + LOOP_RELATIVE = 1 +} Addressmode; +#endif /*ENUMS_Addressmode_H*/ + +#ifndef ENUMS_TexCoordDenorm_H +#define ENUMS_TexCoordDenorm_H +typedef enum TexCoordDenorm { + TEX_COORD_NORMALIZED = 0, + TEX_COORD_UNNORMALIZED = 1 +} TexCoordDenorm; +#endif /*ENUMS_TexCoordDenorm_H*/ + +#ifndef ENUMS_SrcSel_H +#define ENUMS_SrcSel_H +typedef enum SrcSel { + SRC_SEL_X = 0, + SRC_SEL_Y = 1, + SRC_SEL_Z = 2, + SRC_SEL_W = 3 +} SrcSel; +#endif /*ENUMS_SrcSel_H*/ + +#ifndef ENUMS_DstSel_H +#define ENUMS_DstSel_H +typedef enum DstSel { + DST_SEL_X = 0, + DST_SEL_Y = 1, + DST_SEL_Z = 2, + DST_SEL_W = 3, + DST_SEL_0 = 4, + DST_SEL_1 = 5, + DST_SEL_RSVD = 6, + DST_SEL_MASK = 7 +} DstSel; +#endif /*ENUMS_DstSel_H*/ + +#ifndef ENUMS_MagFilter_H +#define ENUMS_MagFilter_H +typedef enum MagFilter { + MAG_FILTER_POINT = 0, + MAG_FILTER_LINEAR = 1, + MAG_FILTER_RESERVED_0 = 2, + MAG_FILTER_USE_FETCH_CONST = 3 +} MagFilter; +#endif /*ENUMS_MagFilter_H*/ + +#ifndef ENUMS_MinFilter_H +#define ENUMS_MinFilter_H +typedef enum MinFilter { + MIN_FILTER_POINT = 0, + MIN_FILTER_LINEAR = 1, + MIN_FILTER_RESERVED_0 = 2, + MIN_FILTER_USE_FETCH_CONST = 3 +} MinFilter; +#endif /*ENUMS_MinFilter_H*/ + +#ifndef ENUMS_MipFilter_H +#define ENUMS_MipFilter_H +typedef enum MipFilter { + MIP_FILTER_POINT = 0, + MIP_FILTER_LINEAR = 1, + MIP_FILTER_BASEMAP = 2, + MIP_FILTER_USE_FETCH_CONST = 3 +} MipFilter; +#endif /*ENUMS_MipFilter_H*/ + +#ifndef ENUMS_AnisoFilter_H +#define ENUMS_AnisoFilter_H +typedef enum AnisoFilter { + ANISO_FILTER_DISABLED = 0, + ANISO_FILTER_MAX_1_1 = 1, + ANISO_FILTER_MAX_2_1 = 2, + ANISO_FILTER_MAX_4_1 = 3, + ANISO_FILTER_MAX_8_1 = 4, + ANISO_FILTER_MAX_16_1 = 5, + ANISO_FILTER_USE_FETCH_CONST = 7 +} AnisoFilter; +#endif /*ENUMS_AnisoFilter_H*/ + +#ifndef ENUMS_ArbitraryFilter_H +#define ENUMS_ArbitraryFilter_H +typedef enum ArbitraryFilter { + ARBITRARY_FILTER_2X4_SYM = 0, + ARBITRARY_FILTER_2X4_ASYM = 1, + ARBITRARY_FILTER_4X2_SYM = 2, + ARBITRARY_FILTER_4X2_ASYM = 3, + ARBITRARY_FILTER_4X4_SYM = 4, + ARBITRARY_FILTER_4X4_ASYM = 5, + ARBITRARY_FILTER_USE_FETCH_CONST = 7 +} ArbitraryFilter; +#endif /*ENUMS_ArbitraryFilter_H*/ + +#ifndef ENUMS_VolMagFilter_H +#define ENUMS_VolMagFilter_H +typedef enum VolMagFilter { + VOL_MAG_FILTER_POINT = 0, + VOL_MAG_FILTER_LINEAR = 1, + VOL_MAG_FILTER_USE_FETCH_CONST = 3 +} VolMagFilter; +#endif /*ENUMS_VolMagFilter_H*/ + +#ifndef ENUMS_VolMinFilter_H +#define ENUMS_VolMinFilter_H +typedef enum VolMinFilter { + VOL_MIN_FILTER_POINT = 0, + VOL_MIN_FILTER_LINEAR = 1, + VOL_MIN_FILTER_USE_FETCH_CONST = 3 +} VolMinFilter; +#endif /*ENUMS_VolMinFilter_H*/ + +#ifndef ENUMS_PredSelect_H +#define ENUMS_PredSelect_H +typedef enum PredSelect { + NOT_PREDICATED = 0, + PREDICATED = 1 +} PredSelect; +#endif /*ENUMS_PredSelect_H*/ + +#ifndef ENUMS_SampleLocation_H +#define ENUMS_SampleLocation_H +typedef enum SampleLocation { + SAMPLE_CENTROID = 0, + SAMPLE_CENTER = 1 +} SampleLocation; +#endif /*ENUMS_SampleLocation_H*/ + +#ifndef ENUMS_VertexMode_H +#define ENUMS_VertexMode_H +typedef enum VertexMode { + POSITION_1_VECTOR = 0, + POSITION_2_VECTORS_UNUSED = 1, + POSITION_2_VECTORS_SPRITE = 2, + POSITION_2_VECTORS_EDGE = 3, + POSITION_2_VECTORS_KILL = 4, + POSITION_2_VECTORS_SPRITE_KILL = 5, + POSITION_2_VECTORS_EDGE_KILL = 6, + MULTIPASS = 7 +} VertexMode; +#endif /*ENUMS_VertexMode_H*/ + +#ifndef ENUMS_Sample_Cntl_H +#define ENUMS_Sample_Cntl_H +typedef enum Sample_Cntl { + CENTROIDS_ONLY = 0, + CENTERS_ONLY = 1, + CENTROIDS_AND_CENTERS = 2, + UNDEF = 3 +} Sample_Cntl; +#endif /*ENUMS_Sample_Cntl_H*/ + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +#ifndef ENUMS_MhPerfEncode_H +#define ENUMS_MhPerfEncode_H +typedef enum MhPerfEncode { + CP_R0_REQUESTS = 0, + CP_R1_REQUESTS = 1, + CP_R2_REQUESTS = 2, + CP_R3_REQUESTS = 3, + CP_R4_REQUESTS = 4, + CP_TOTAL_READ_REQUESTS = 5, + CP_TOTAL_WRITE_REQUESTS = 6, + CP_TOTAL_REQUESTS = 7, + CP_DATA_BYTES_WRITTEN = 8, + CP_WRITE_CLEAN_RESPONSES = 9, + CP_R0_READ_BURSTS_RECEIVED = 10, + CP_R1_READ_BURSTS_RECEIVED = 11, + CP_R2_READ_BURSTS_RECEIVED = 12, + CP_R3_READ_BURSTS_RECEIVED = 13, + CP_R4_READ_BURSTS_RECEIVED = 14, + CP_TOTAL_READ_BURSTS_RECEIVED = 15, + CP_R0_DATA_BEATS_READ = 16, + CP_R1_DATA_BEATS_READ = 17, + CP_R2_DATA_BEATS_READ = 18, + CP_R3_DATA_BEATS_READ = 19, + CP_R4_DATA_BEATS_READ = 20, + CP_TOTAL_DATA_BEATS_READ = 21, + VGT_R0_REQUESTS = 22, + VGT_R1_REQUESTS = 23, + VGT_TOTAL_REQUESTS = 24, + VGT_R0_READ_BURSTS_RECEIVED = 25, + VGT_R1_READ_BURSTS_RECEIVED = 26, + VGT_TOTAL_READ_BURSTS_RECEIVED = 27, + VGT_R0_DATA_BEATS_READ = 28, + VGT_R1_DATA_BEATS_READ = 29, + VGT_TOTAL_DATA_BEATS_READ = 30, + TC_TOTAL_REQUESTS = 31, + TC_ROQ_REQUESTS = 32, + TC_INFO_SENT = 33, + TC_READ_BURSTS_RECEIVED = 34, + TC_DATA_BEATS_READ = 35, + TCD_BURSTS_READ = 36, + RB_REQUESTS = 37, + RB_DATA_BYTES_WRITTEN = 38, + RB_WRITE_CLEAN_RESPONSES = 39, + AXI_READ_REQUESTS_ID_0 = 40, + AXI_READ_REQUESTS_ID_1 = 41, + AXI_READ_REQUESTS_ID_2 = 42, + AXI_READ_REQUESTS_ID_3 = 43, + AXI_READ_REQUESTS_ID_4 = 44, + AXI_READ_REQUESTS_ID_5 = 45, + AXI_READ_REQUESTS_ID_6 = 46, + AXI_READ_REQUESTS_ID_7 = 47, + AXI_TOTAL_READ_REQUESTS = 48, + AXI_WRITE_REQUESTS_ID_0 = 49, + AXI_WRITE_REQUESTS_ID_1 = 50, + AXI_WRITE_REQUESTS_ID_2 = 51, + AXI_WRITE_REQUESTS_ID_3 = 52, + AXI_WRITE_REQUESTS_ID_4 = 53, + AXI_WRITE_REQUESTS_ID_5 = 54, + AXI_WRITE_REQUESTS_ID_6 = 55, + AXI_WRITE_REQUESTS_ID_7 = 56, + AXI_TOTAL_WRITE_REQUESTS = 57, + AXI_TOTAL_REQUESTS_ID_0 = 58, + AXI_TOTAL_REQUESTS_ID_1 = 59, + AXI_TOTAL_REQUESTS_ID_2 = 60, + AXI_TOTAL_REQUESTS_ID_3 = 61, + AXI_TOTAL_REQUESTS_ID_4 = 62, + AXI_TOTAL_REQUESTS_ID_5 = 63, + AXI_TOTAL_REQUESTS_ID_6 = 64, + AXI_TOTAL_REQUESTS_ID_7 = 65, + AXI_TOTAL_REQUESTS = 66, + AXI_READ_CHANNEL_BURSTS_ID_0 = 67, + AXI_READ_CHANNEL_BURSTS_ID_1 = 68, + AXI_READ_CHANNEL_BURSTS_ID_2 = 69, + AXI_READ_CHANNEL_BURSTS_ID_3 = 70, + AXI_READ_CHANNEL_BURSTS_ID_4 = 71, + AXI_READ_CHANNEL_BURSTS_ID_5 = 72, + AXI_READ_CHANNEL_BURSTS_ID_6 = 73, + AXI_READ_CHANNEL_BURSTS_ID_7 = 74, + AXI_READ_CHANNEL_TOTAL_BURSTS = 75, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, + AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, + AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, + AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, + AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, + AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, + AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, + AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, + AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, + AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, + AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, + AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, + AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, + TOTAL_MMU_MISSES = 112, + MMU_READ_MISSES = 113, + MMU_WRITE_MISSES = 114, + TOTAL_MMU_HITS = 115, + MMU_READ_HITS = 116, + MMU_WRITE_HITS = 117, + SPLIT_MODE_TC_HITS = 118, + SPLIT_MODE_TC_MISSES = 119, + SPLIT_MODE_NON_TC_HITS = 120, + SPLIT_MODE_NON_TC_MISSES = 121, + STALL_AWAITING_TLB_MISS_FETCH = 122, + MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, + MMU_TLB_MISS_DATA_BEATS_READ = 124, + CP_CYCLES_HELD_OFF = 125, + VGT_CYCLES_HELD_OFF = 126, + TC_CYCLES_HELD_OFF = 127, + TC_ROQ_CYCLES_HELD_OFF = 128, + TC_CYCLES_HELD_OFF_TCD_FULL = 129, + RB_CYCLES_HELD_OFF = 130, + TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, + TLB_MISS_CYCLES_HELD_OFF = 132, + AXI_READ_REQUEST_HELD_OFF = 133, + AXI_WRITE_REQUEST_HELD_OFF = 134, + AXI_REQUEST_HELD_OFF = 135, + AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, + AXI_WRITE_DATA_HELD_OFF = 137, + CP_SAME_PAGE_BANK_REQUESTS = 138, + VGT_SAME_PAGE_BANK_REQUESTS = 139, + TC_SAME_PAGE_BANK_REQUESTS = 140, + TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, + RB_SAME_PAGE_BANK_REQUESTS = 142, + TOTAL_SAME_PAGE_BANK_REQUESTS = 143, + CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, + VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, + TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, + RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, + TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, + TOTAL_MH_READ_REQUESTS = 149, + TOTAL_MH_WRITE_REQUESTS = 150, + TOTAL_MH_REQUESTS = 151, + MH_BUSY = 152, + CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, + VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, + TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, + RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, + TC_ROQ_N_VALID_ENTRIES = 157, + ARQ_N_ENTRIES = 158, + WDB_N_ENTRIES = 159, + MH_READ_LATENCY_OUTST_REQ_SUM = 160, + MC_READ_LATENCY_OUTST_REQ_SUM = 161, + MC_TOTAL_READ_REQUESTS = 162, + ELAPSED_CYCLES_MH_GATED_CLK = 163, + ELAPSED_CLK_CYCLES = 164, + CP_W_16B_REQUESTS = 165, + CP_W_32B_REQUESTS = 166, + TC_16B_REQUESTS = 167, + TC_32B_REQUESTS = 168, + PA_REQUESTS = 169, + PA_DATA_BYTES_WRITTEN = 170, + PA_WRITE_CLEAN_RESPONSES = 171, + PA_CYCLES_HELD_OFF = 172, + AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173, + AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174, + AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175, + AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176, + AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177, + AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178, + AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179, + AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180, + AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, +} MhPerfEncode; +#endif /*ENUMS_MhPerfEncode_H*/ + +#ifndef ENUMS_MmuClntBeh_H +#define ENUMS_MmuClntBeh_H +typedef enum MmuClntBeh { + BEH_NEVR = 0, + BEH_TRAN_RNG = 1, + BEH_TRAN_FLT = 2, +} MmuClntBeh; +#endif /*ENUMS_MmuClntBeh_H*/ + +/******************************************************* + * RBBM Enums + *******************************************************/ +#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H +#define ENUMS_RBBM_PERFCOUNT1_SEL_H +typedef enum RBBM_PERFCOUNT1_SEL { + RBBM1_COUNT = 0, + RBBM1_NRT_BUSY = 1, + RBBM1_RB_BUSY = 2, + RBBM1_SQ_CNTX0_BUSY = 3, + RBBM1_SQ_CNTX17_BUSY = 4, + RBBM1_VGT_BUSY = 5, + RBBM1_VGT_NODMA_BUSY = 6, + RBBM1_PA_BUSY = 7, + RBBM1_SC_CNTX_BUSY = 8, + RBBM1_TPC_BUSY = 9, + RBBM1_TC_BUSY = 10, + RBBM1_SX_BUSY = 11, + RBBM1_CP_COHER_BUSY = 12, + RBBM1_CP_NRT_BUSY = 13, + RBBM1_GFX_IDLE_STALL = 14, + RBBM1_INTERRUPT = 15, +} RBBM_PERFCOUNT1_SEL; +#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/ + +/******************************************************* + * CP Enums + *******************************************************/ +#ifndef ENUMS_CP_PERFCOUNT_SEL_H +#define ENUMS_CP_PERFCOUNT_SEL_H +typedef enum CP_PERFCOUNT_SEL { + ALWAYS_COUNT = 0, + TRANS_FIFO_FULL = 1, + TRANS_FIFO_AF = 2, + RCIU_PFPTRANS_WAIT = 3, + Reserved_04 = 4, + Reserved_05 = 5, + RCIU_NRTTRANS_WAIT = 6, + Reserved_07 = 7, + CSF_NRT_READ_WAIT = 8, + CSF_I1_FIFO_FULL = 9, + CSF_I2_FIFO_FULL = 10, + CSF_ST_FIFO_FULL = 11, + Reserved_12 = 12, + CSF_RING_ROQ_FULL = 13, + CSF_I1_ROQ_FULL = 14, + CSF_I2_ROQ_FULL = 15, + CSF_ST_ROQ_FULL = 16, + Reserved_17 = 17, + MIU_TAG_MEM_FULL = 18, + MIU_WRITECLEAN = 19, + Reserved_20 = 20, + Reserved_21 = 21, + MIU_NRT_WRITE_STALLED = 22, + MIU_NRT_READ_STALLED = 23, + ME_WRITE_CONFIRM_FIFO_FULL = 24, + ME_VS_DEALLOC_FIFO_FULL = 25, + ME_PS_DEALLOC_FIFO_FULL = 26, + ME_REGS_VS_EVENT_FIFO_FULL = 27, + ME_REGS_PS_EVENT_FIFO_FULL = 28, + ME_REGS_CF_EVENT_FIFO_FULL = 29, + ME_MICRO_RB_STARVED = 30, + ME_MICRO_I1_STARVED = 31, + ME_MICRO_I2_STARVED = 32, + ME_MICRO_ST_STARVED = 33, + Reserved_34 = 34, + Reserved_35 = 35, + Reserved_36 = 36, + Reserved_37 = 37, + Reserved_38 = 38, + Reserved_39 = 39, + RCIU_RBBM_DWORD_SENT = 40, + ME_BUSY_CLOCKS = 41, + ME_WAIT_CONTEXT_AVAIL = 42, + PFP_TYPE0_PACKET = 43, + PFP_TYPE3_PACKET = 44, + CSF_RB_WPTR_NEQ_RPTR = 45, + CSF_I1_SIZE_NEQ_ZERO = 46, + CSF_I2_SIZE_NEQ_ZERO = 47, + CSF_RBI1I2_FETCHING = 48, + Reserved_49 = 49, + Reserved_50 = 50, + Reserved_51 = 51, + Reserved_52 = 52, + Reserved_53 = 53, + Reserved_54 = 54, + Reserved_55 = 55, + Reserved_56 = 56, + Reserved_57 = 57, + Reserved_58 = 58, + Reserved_59 = 59, + Reserved_60 = 60, + Reserved_61 = 61, + Reserved_62 = 62, + Reserved_63 = 63 +} CP_PERFCOUNT_SEL; +#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/ + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +#ifndef ENUMS_ColorformatX_H +#define ENUMS_ColorformatX_H +typedef enum ColorformatX { + COLORX_4_4_4_4 = 0, + COLORX_1_5_5_5 = 1, + COLORX_5_6_5 = 2, + COLORX_8 = 3, + COLORX_8_8 = 4, + COLORX_8_8_8_8 = 5, + COLORX_S8_8_8_8 = 6, + COLORX_16_FLOAT = 7, + COLORX_16_16_FLOAT = 8, + COLORX_16_16_16_16_FLOAT = 9, + COLORX_32_FLOAT = 10, + COLORX_32_32_FLOAT = 11, + COLORX_32_32_32_32_FLOAT = 12, + COLORX_2_3_3 = 13, + COLORX_8_8_8 = 14, +} ColorformatX; +#endif /*ENUMS_ColorformatX_H*/ + +#ifndef ENUMS_DepthformatX_H +#define ENUMS_DepthformatX_H +typedef enum DepthformatX { + DEPTHX_16 = 0, + DEPTHX_24_8 = 1 +} DepthformatX; +#endif /*ENUMS_DepthformatX_H*/ + +#ifndef ENUMS_CompareFrag_H +#define ENUMS_CompareFrag_H +typedef enum CompareFrag { + FRAG_NEVER = 0, + FRAG_LESS = 1, + FRAG_EQUAL = 2, + FRAG_LEQUAL = 3, + FRAG_GREATER = 4, + FRAG_NOTEQUAL = 5, + FRAG_GEQUAL = 6, + FRAG_ALWAYS = 7 +} CompareFrag; +#endif /*ENUMS_CompareFrag_H*/ + +#ifndef ENUMS_CompareRef_H +#define ENUMS_CompareRef_H +typedef enum CompareRef { + REF_NEVER = 0, + REF_LESS = 1, + REF_EQUAL = 2, + REF_LEQUAL = 3, + REF_GREATER = 4, + REF_NOTEQUAL = 5, + REF_GEQUAL = 6, + REF_ALWAYS = 7 +} CompareRef; +#endif /*ENUMS_CompareRef_H*/ + +#ifndef ENUMS_StencilOp_H +#define ENUMS_StencilOp_H +typedef enum StencilOp { + STENCIL_KEEP = 0, + STENCIL_ZERO = 1, + STENCIL_REPLACE = 2, + STENCIL_INCR_CLAMP = 3, + STENCIL_DECR_CLAMP = 4, + STENCIL_INVERT = 5, + STENCIL_INCR_WRAP = 6, + STENCIL_DECR_WRAP = 7 +} StencilOp; +#endif /*ENUMS_StencilOp_H*/ + +#ifndef ENUMS_BlendOpX_H +#define ENUMS_BlendOpX_H +typedef enum BlendOpX { + BLENDX_ZERO = 0, + BLENDX_ONE = 1, + BLENDX_SRC_COLOR = 4, + BLENDX_ONE_MINUS_SRC_COLOR = 5, + BLENDX_SRC_ALPHA = 6, + BLENDX_ONE_MINUS_SRC_ALPHA = 7, + BLENDX_DST_COLOR = 8, + BLENDX_ONE_MINUS_DST_COLOR = 9, + BLENDX_DST_ALPHA = 10, + BLENDX_ONE_MINUS_DST_ALPHA = 11, + BLENDX_CONSTANT_COLOR = 12, + BLENDX_ONE_MINUS_CONSTANT_COLOR = 13, + BLENDX_CONSTANT_ALPHA = 14, + BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15, + BLENDX_SRC_ALPHA_SATURATE = 16, +} BlendOpX; +#endif /*ENUMS_BlendOpX_H*/ + +#ifndef ENUMS_CombFuncX_H +#define ENUMS_CombFuncX_H +typedef enum CombFuncX { + COMB_DST_PLUS_SRC = 0, + COMB_SRC_MINUS_DST = 1, + COMB_MIN_DST_SRC = 2, + COMB_MAX_DST_SRC = 3, + COMB_DST_MINUS_SRC = 4, + COMB_DST_PLUS_SRC_BIAS = 5, +} CombFuncX; +#endif /*ENUMS_CombFuncX_H*/ + +#ifndef ENUMS_DitherModeX_H +#define ENUMS_DitherModeX_H +typedef enum DitherModeX { + DITHER_DISABLE = 0, + DITHER_ALWAYS = 1, + DITHER_IF_ALPHA_OFF = 2, +} DitherModeX; +#endif /*ENUMS_DitherModeX_H*/ + +#ifndef ENUMS_DitherTypeX_H +#define ENUMS_DitherTypeX_H +typedef enum DitherTypeX { + DITHER_PIXEL = 0, + DITHER_SUBPIXEL = 1, +} DitherTypeX; +#endif /*ENUMS_DitherTypeX_H*/ + +#ifndef ENUMS_EdramMode_H +#define ENUMS_EdramMode_H +typedef enum EdramMode { + EDRAM_NOP = 0, + COLOR_DEPTH = 4, + DEPTH_ONLY = 5, + EDRAM_COPY = 6, +} EdramMode; +#endif /*ENUMS_EdramMode_H*/ + +#ifndef ENUMS_SurfaceEndian_H +#define ENUMS_SurfaceEndian_H +typedef enum SurfaceEndian { + ENDIAN_NONE = 0, + ENDIAN_8IN16 = 1, + ENDIAN_8IN32 = 2, + ENDIAN_16IN32 = 3, + ENDIAN_8IN64 = 4, + ENDIAN_8IN128 = 5, +} SurfaceEndian; +#endif /*ENUMS_SurfaceEndian_H*/ + +#ifndef ENUMS_EdramSizeX_H +#define ENUMS_EdramSizeX_H +typedef enum EdramSizeX { + EDRAMSIZE_16KB = 0, + EDRAMSIZE_32KB = 1, + EDRAMSIZE_64KB = 2, + EDRAMSIZE_128KB = 3, + EDRAMSIZE_256KB = 4, + EDRAMSIZE_512KB = 5, + EDRAMSIZE_1MB = 6, + EDRAMSIZE_2MB = 7, + EDRAMSIZE_4MB = 8, + EDRAMSIZE_8MB = 9, + EDRAMSIZE_16MB = 10, +} EdramSizeX; +#endif /*ENUMS_EdramSizeX_H*/ + +#ifndef ENUMS_RB_PERFCNT_SELECT_H +#define ENUMS_RB_PERFCNT_SELECT_H +typedef enum RB_PERFCNT_SELECT { + RBPERF_CNTX_BUSY = 0, + RBPERF_CNTX_BUSY_MAX = 1, + RBPERF_SX_QUAD_STARVED = 2, + RBPERF_SX_QUAD_STARVED_MAX = 3, + RBPERF_GA_GC_CH0_SYS_REQ = 4, + RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, + RBPERF_GA_GC_CH1_SYS_REQ = 6, + RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, + RBPERF_MH_STARVED = 8, + RBPERF_MH_STARVED_MAX = 9, + RBPERF_AZ_BC_COLOR_BUSY = 10, + RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, + RBPERF_AZ_BC_Z_BUSY = 12, + RBPERF_AZ_BC_Z_BUSY_MAX = 13, + RBPERF_RB_SC_TILE_RTR_N = 14, + RBPERF_RB_SC_TILE_RTR_N_MAX = 15, + RBPERF_RB_SC_SAMP_RTR_N = 16, + RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, + RBPERF_RB_SX_QUAD_RTR_N = 18, + RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, + RBPERF_RB_SX_COLOR_RTR_N = 20, + RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, + RBPERF_RB_SC_SAMP_LZ_BUSY = 22, + RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, + RBPERF_ZXP_STALL = 24, + RBPERF_ZXP_STALL_MAX = 25, + RBPERF_EVENT_PENDING = 26, + RBPERF_EVENT_PENDING_MAX = 27, + RBPERF_RB_MH_VALID = 28, + RBPERF_RB_MH_VALID_MAX = 29, + RBPERF_SX_RB_QUAD_SEND = 30, + RBPERF_SX_RB_COLOR_SEND = 31, + RBPERF_SC_RB_TILE_SEND = 32, + RBPERF_SC_RB_SAMPLE_SEND = 33, + RBPERF_SX_RB_MEM_EXPORT = 34, + RBPERF_SX_RB_QUAD_EVENT = 35, + RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, + RBPERF_SC_RB_TILE_EVENT_ALL = 37, + RBPERF_RB_SC_EZ_SEND = 38, + RBPERF_RB_SX_INDEX_SEND = 39, + RBPERF_GMEM_INTFO_RD = 40, + RBPERF_GMEM_INTF1_RD = 41, + RBPERF_GMEM_INTFO_WR = 42, + RBPERF_GMEM_INTF1_WR = 43, + RBPERF_RB_CP_CONTEXT_DONE = 44, + RBPERF_RB_CP_CACHE_FLUSH = 45, + RBPERF_ZPASS_DONE = 46, + RBPERF_ZCMD_VALID = 47, + RBPERF_CCMD_VALID = 48, + RBPERF_ACCUM_GRANT = 49, + RBPERF_ACCUM_C0_GRANT = 50, + RBPERF_ACCUM_C1_GRANT = 51, + RBPERF_ACCUM_FULL_BE_WR = 52, + RBPERF_ACCUM_REQUEST_NO_GRANT = 53, + RBPERF_ACCUM_TIMEOUT_PULSE = 54, + RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, + RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, +} RB_PERFCNT_SELECT; +#endif /*ENUMS_RB_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_DepthFormat_H +#define ENUMS_DepthFormat_H +typedef enum DepthFormat { + DEPTH_24_8 = 22, + DEPTH_24_8_FLOAT = 23, + DEPTH_16 = 24, +} DepthFormat; +#endif /*ENUMS_DepthFormat_H*/ + +#ifndef ENUMS_SurfaceSwap_H +#define ENUMS_SurfaceSwap_H +typedef enum SurfaceSwap { + SWAP_LOWRED = 0, + SWAP_LOWBLUE = 1 +} SurfaceSwap; +#endif /*ENUMS_SurfaceSwap_H*/ + +#ifndef ENUMS_DepthArray_H +#define ENUMS_DepthArray_H +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0, + ARRAY_2D_DEPTH = 1, +} DepthArray; +#endif /*ENUMS_DepthArray_H*/ + +#ifndef ENUMS_ColorArray_H +#define ENUMS_ColorArray_H +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0, + ARRAY_2D_COLOR = 1, + ARRAY_3D_SLICE_COLOR = 3 +} ColorArray; +#endif /*ENUMS_ColorArray_H*/ + +#ifndef ENUMS_ColorFormat_H +#define ENUMS_ColorFormat_H +typedef enum ColorFormat { + COLOR_8 = 2, + COLOR_1_5_5_5 = 3, + COLOR_5_6_5 = 4, + COLOR_6_5_5 = 5, + COLOR_8_8_8_8 = 6, + COLOR_2_10_10_10 = 7, + COLOR_8_A = 8, + COLOR_8_B = 9, + COLOR_8_8 = 10, + COLOR_8_8_8 = 11, + COLOR_8_8_8_8_A = 14, + COLOR_4_4_4_4 = 15, + COLOR_10_11_11 = 16, + COLOR_11_11_10 = 17, + COLOR_16 = 24, + COLOR_16_16 = 25, + COLOR_16_16_16_16 = 26, + COLOR_16_FLOAT = 30, + COLOR_16_16_FLOAT = 31, + COLOR_16_16_16_16_FLOAT = 32, + COLOR_32_FLOAT = 36, + COLOR_32_32_FLOAT = 37, + COLOR_32_32_32_32_FLOAT = 38, + COLOR_2_3_3 = 39, +} ColorFormat; +#endif /*ENUMS_ColorFormat_H*/ + +#ifndef ENUMS_SurfaceNumber_H +#define ENUMS_SurfaceNumber_H +typedef enum SurfaceNumber { + NUMBER_UREPEAT = 0, + NUMBER_SREPEAT = 1, + NUMBER_UINTEGER = 2, + NUMBER_SINTEGER = 3, + NUMBER_GAMMA = 4, + NUMBER_FIXED = 5, + NUMBER_FLOAT = 7 +} SurfaceNumber; +#endif /*ENUMS_SurfaceNumber_H*/ + +#ifndef ENUMS_SurfaceFormat_H +#define ENUMS_SurfaceFormat_H +typedef enum SurfaceFormat { + FMT_1_REVERSE = 0, + FMT_1 = 1, + FMT_8 = 2, + FMT_1_5_5_5 = 3, + FMT_5_6_5 = 4, + FMT_6_5_5 = 5, + FMT_8_8_8_8 = 6, + FMT_2_10_10_10 = 7, + FMT_8_A = 8, + FMT_8_B = 9, + FMT_8_8 = 10, + FMT_Cr_Y1_Cb_Y0 = 11, + FMT_Y1_Cr_Y0_Cb = 12, + FMT_5_5_5_1 = 13, + FMT_8_8_8_8_A = 14, + FMT_4_4_4_4 = 15, + FMT_8_8_8 = 16, + FMT_DXT1 = 18, + FMT_DXT2_3 = 19, + FMT_DXT4_5 = 20, + FMT_10_10_10_2 = 21, + FMT_24_8 = 22, + FMT_16 = 24, + FMT_16_16 = 25, + FMT_16_16_16_16 = 26, + FMT_16_EXPAND = 27, + FMT_16_16_EXPAND = 28, + FMT_16_16_16_16_EXPAND = 29, + FMT_16_FLOAT = 30, + FMT_16_16_FLOAT = 31, + FMT_16_16_16_16_FLOAT = 32, + FMT_32 = 33, + FMT_32_32 = 34, + FMT_32_32_32_32 = 35, + FMT_32_FLOAT = 36, + FMT_32_32_FLOAT = 37, + FMT_32_32_32_32_FLOAT = 38, + FMT_ATI_TC_RGB = 39, + FMT_ATI_TC_RGBA = 40, + FMT_ATI_TC_555_565_RGB = 41, + FMT_ATI_TC_555_565_RGBA = 42, + FMT_ATI_TC_RGBA_INTERP = 43, + FMT_ATI_TC_555_565_RGBA_INTERP = 44, + FMT_ETC1_RGBA_INTERP = 46, + FMT_ETC1_RGB = 47, + FMT_ETC1_RGBA = 48, + FMT_DXN = 49, + FMT_2_3_3 = 51, + FMT_2_10_10_10_AS_16_16_16_16 = 54, + FMT_10_10_10_2_AS_16_16_16_16 = 55, + FMT_32_32_32_FLOAT = 57, + FMT_DXT3A = 58, + FMT_DXT5A = 59, + FMT_CTX1 = 60, +} SurfaceFormat; +#endif /*ENUMS_SurfaceFormat_H*/ + +#ifndef ENUMS_SurfaceTiling_H +#define ENUMS_SurfaceTiling_H +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0, + ARRAY_TILED = 1 +} SurfaceTiling; +#endif /*ENUMS_SurfaceTiling_H*/ + +#ifndef ENUMS_SurfaceArray_H +#define ENUMS_SurfaceArray_H +typedef enum SurfaceArray { + ARRAY_1D = 0, + ARRAY_2D = 1, + ARRAY_3D = 2, + ARRAY_3D_SLICE = 3 +} SurfaceArray; +#endif /*ENUMS_SurfaceArray_H*/ + +#ifndef ENUMS_SurfaceNumberX_H +#define ENUMS_SurfaceNumberX_H +typedef enum SurfaceNumberX { + NUMBERX_UREPEAT = 0, + NUMBERX_SREPEAT = 1, + NUMBERX_UINTEGER = 2, + NUMBERX_SINTEGER = 3, + NUMBERX_FLOAT = 7 +} SurfaceNumberX; +#endif /*ENUMS_SurfaceNumberX_H*/ + +#ifndef ENUMS_ColorArrayX_H +#define ENUMS_ColorArrayX_H +typedef enum ColorArrayX { + ARRAYX_2D_COLOR = 0, + ARRAYX_3D_SLICE_COLOR = 1, +} ColorArrayX; +#endif /*ENUMS_ColorArrayX_H*/ + +#endif /*_yamato_ENUM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h new file mode 100644 index 000000000000..87a454a1e38a --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h @@ -0,0 +1,1703 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_ENUMTYPE(SU_PERFCNT_SELECT) + GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0) + GENERATE_ENUM(UNUSED1, 1) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13) + GENERATE_ENUM(UNUSED2, 14) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15) + GENERATE_ENUM(UNUSED3, 16) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19) + GENERATE_ENUM(UNUSED4, 20) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21) + GENERATE_ENUM(UNUSED5, 22) + GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35) + GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36) + GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37) + GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38) + GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45) + GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49) + GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50) + GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51) + GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71) + GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72) + GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77) + GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78) + GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79) + GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80) + GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81) + GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84) + GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85) + GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91) + GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92) + GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95) + GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96) + GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97) + GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98) + GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99) + GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100) + GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101) + GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102) +END_ENUMTYPE(SU_PERFCNT_SELECT) + +START_ENUMTYPE(SC_PERFCNT_SELECT) + GENERATE_ENUM(SC_SR_WINDOW_VALID, 0) + GENERATE_ENUM(SC_CW_WINDOW_VALID, 1) + GENERATE_ENUM(SC_QM_WINDOW_VALID, 2) + GENERATE_ENUM(SC_FW_WINDOW_VALID, 3) + GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4) + GENERATE_ENUM(SC_IT_WINDOW_VALID, 5) + GENERATE_ENUM(SC_STARVED_BY_PA, 6) + GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7) + GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8) + GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9) + GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10) + GENERATE_ENUM(SC_STALLED_BY_SQ, 11) + GENERATE_ENUM(SC_STALLED_BY_SP, 12) + GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13) + GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14) + GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15) + GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16) + GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17) +END_ENUMTYPE(SC_PERFCNT_SELECT) + +START_ENUMTYPE(VGT_DI_PRIM_TYPE) + GENERATE_ENUM(DI_PT_NONE, 0) + GENERATE_ENUM(DI_PT_POINTLIST, 1) + GENERATE_ENUM(DI_PT_LINELIST, 2) + GENERATE_ENUM(DI_PT_LINESTRIP, 3) + GENERATE_ENUM(DI_PT_TRILIST, 4) + GENERATE_ENUM(DI_PT_TRIFAN, 5) + GENERATE_ENUM(DI_PT_TRISTRIP, 6) + GENERATE_ENUM(DI_PT_UNUSED_1, 7) + GENERATE_ENUM(DI_PT_RECTLIST, 8) + GENERATE_ENUM(DI_PT_UNUSED_2, 9) + GENERATE_ENUM(DI_PT_UNUSED_3, 10) + GENERATE_ENUM(DI_PT_UNUSED_4, 11) + GENERATE_ENUM(DI_PT_UNUSED_5, 12) + GENERATE_ENUM(DI_PT_QUADLIST, 13) + GENERATE_ENUM(DI_PT_QUADSTRIP, 14) + GENERATE_ENUM(DI_PT_POLYGON, 15) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19) + GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20) + GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21) + GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22) +END_ENUMTYPE(VGT_DI_PRIM_TYPE) + +START_ENUMTYPE(VGT_DI_SOURCE_SELECT) + GENERATE_ENUM(DI_SRC_SEL_DMA, 0) + GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1) + GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2) + GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3) +END_ENUMTYPE(VGT_DI_SOURCE_SELECT) + +START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + GENERATE_ENUM(DI_FACE_CULL_NONE, 0) + GENERATE_ENUM(DI_FACE_CULL_FETCH, 1) + GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2) + GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3) +END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + +START_ENUMTYPE(VGT_DI_INDEX_SIZE) + GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0) + GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1) +END_ENUMTYPE(VGT_DI_INDEX_SIZE) + +START_ENUMTYPE(VGT_DI_SMALL_INDEX) + GENERATE_ENUM(DI_USE_INDEX_SIZE, 0) + GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1) +END_ENUMTYPE(VGT_DI_SMALL_INDEX) + +START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0) + GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + +START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0) + GENERATE_ENUM(GRP_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + +START_ENUMTYPE(VGT_EVENT_TYPE) + GENERATE_ENUM(VS_DEALLOC, 0) + GENERATE_ENUM(PS_DEALLOC, 1) + GENERATE_ENUM(VS_DONE_TS, 2) + GENERATE_ENUM(PS_DONE_TS, 3) + GENERATE_ENUM(CACHE_FLUSH_TS, 4) + GENERATE_ENUM(CONTEXT_DONE, 5) + GENERATE_ENUM(CACHE_FLUSH, 6) + GENERATE_ENUM(VIZQUERY_START, 7) + GENERATE_ENUM(VIZQUERY_END, 8) + GENERATE_ENUM(SC_WAIT_WC, 9) + GENERATE_ENUM(RST_PIX_CNT, 13) + GENERATE_ENUM(RST_VTX_CNT, 14) + GENERATE_ENUM(TILE_FLUSH, 15) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20) + GENERATE_ENUM(ZPASS_DONE, 21) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22) + GENERATE_ENUM(PERFCOUNTER_START, 23) + GENERATE_ENUM(PERFCOUNTER_STOP, 24) + GENERATE_ENUM(VS_FETCH_DONE, 27) + GENERATE_ENUM(FACENESS_FLUSH, 28) +END_ENUMTYPE(VGT_EVENT_TYPE) + +START_ENUMTYPE(VGT_DMA_SWAP_MODE) + GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0) + GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1) + GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2) + GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3) +END_ENUMTYPE(VGT_DMA_SWAP_MODE) + +START_ENUMTYPE(VGT_PERFCOUNT_SELECT) + GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0) + GENERATE_ENUM(VGT_SQ_SEND, 1) + GENERATE_ENUM(VGT_SQ_STALLED, 2) + GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3) + GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4) + GENERATE_ENUM(VGT_SQ_STATIC, 5) + GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6) + GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7) + GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10) + GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11) + GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12) + GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15) + GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16) + GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17) + GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20) + GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21) + GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28) + GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29) + GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30) + GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31) + GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32) + GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33) + GENERATE_ENUM(SPARE34, 34) + GENERATE_ENUM(SPARE35, 35) + GENERATE_ENUM(SPARE36, 36) + GENERATE_ENUM(SPARE37, 37) + GENERATE_ENUM(SPARE38, 38) + GENERATE_ENUM(SPARE39, 39) + GENERATE_ENUM(TE_SU_IN_VALID, 40) + GENERATE_ENUM(TE_SU_IN_READ, 41) + GENERATE_ENUM(TE_SU_IN_PRIM, 42) + GENERATE_ENUM(TE_SU_IN_EOP, 43) + GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44) + GENERATE_ENUM(TE_WK_IN_VALID, 45) + GENERATE_ENUM(TE_WK_IN_READ, 46) + GENERATE_ENUM(TE_OUT_PRIM_VALID, 47) + GENERATE_ENUM(TE_OUT_PRIM_READ, 48) +END_ENUMTYPE(VGT_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCR_PERFCOUNT_SELECT) + GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0) + GENERATE_ENUM(reserved_46, 1) + GENERATE_ENUM(reserved_47, 2) + GENERATE_ENUM(reserved_48, 3) + GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4) + GENERATE_ENUM(OPMUX0_L2_WRITES, 5) + GENERATE_ENUM(reserved_49, 6) + GENERATE_ENUM(reserved_50, 7) + GENERATE_ENUM(reserved_51, 8) +END_ENUMTYPE(TCR_PERFCOUNT_SELECT) + +START_ENUMTYPE(TP_PERFCOUNT_SELECT) + GENERATE_ENUM(POINT_QUADS, 0) + GENERATE_ENUM(BILIN_QUADS, 1) + GENERATE_ENUM(ANISO_QUADS, 2) + GENERATE_ENUM(MIP_QUADS, 3) + GENERATE_ENUM(VOL_QUADS, 4) + GENERATE_ENUM(MIP_VOL_QUADS, 5) + GENERATE_ENUM(MIP_ANISO_QUADS, 6) + GENERATE_ENUM(VOL_ANISO_QUADS, 7) + GENERATE_ENUM(ANISO_2_1_QUADS, 8) + GENERATE_ENUM(ANISO_4_1_QUADS, 9) + GENERATE_ENUM(ANISO_6_1_QUADS, 10) + GENERATE_ENUM(ANISO_8_1_QUADS, 11) + GENERATE_ENUM(ANISO_10_1_QUADS, 12) + GENERATE_ENUM(ANISO_12_1_QUADS, 13) + GENERATE_ENUM(ANISO_14_1_QUADS, 14) + GENERATE_ENUM(ANISO_16_1_QUADS, 15) + GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16) + GENERATE_ENUM(ALIGN_2_QUADS, 17) + GENERATE_ENUM(ALIGN_4_QUADS, 18) + GENERATE_ENUM(PIX_0_QUAD, 19) + GENERATE_ENUM(PIX_1_QUAD, 20) + GENERATE_ENUM(PIX_2_QUAD, 21) + GENERATE_ENUM(PIX_3_QUAD, 22) + GENERATE_ENUM(PIX_4_QUAD, 23) + GENERATE_ENUM(TP_MIPMAP_LOD0, 24) + GENERATE_ENUM(TP_MIPMAP_LOD1, 25) + GENERATE_ENUM(TP_MIPMAP_LOD2, 26) + GENERATE_ENUM(TP_MIPMAP_LOD3, 27) + GENERATE_ENUM(TP_MIPMAP_LOD4, 28) + GENERATE_ENUM(TP_MIPMAP_LOD5, 29) + GENERATE_ENUM(TP_MIPMAP_LOD6, 30) + GENERATE_ENUM(TP_MIPMAP_LOD7, 31) + GENERATE_ENUM(TP_MIPMAP_LOD8, 32) + GENERATE_ENUM(TP_MIPMAP_LOD9, 33) + GENERATE_ENUM(TP_MIPMAP_LOD10, 34) + GENERATE_ENUM(TP_MIPMAP_LOD11, 35) + GENERATE_ENUM(TP_MIPMAP_LOD12, 36) + GENERATE_ENUM(TP_MIPMAP_LOD13, 37) + GENERATE_ENUM(TP_MIPMAP_LOD14, 38) +END_ENUMTYPE(TP_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCM_PERFCOUNT_SELECT) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0) + GENERATE_ENUM(reserved_01, 1) + GENERATE_ENUM(reserved_02, 2) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6) + GENERATE_ENUM(reserved_07, 7) + GENERATE_ENUM(reserved_08, 8) + GENERATE_ENUM(reserved_09, 9) + GENERATE_ENUM(reserved_10, 10) + GENERATE_ENUM(reserved_11, 11) + GENERATE_ENUM(reserved_12, 12) + GENERATE_ENUM(reserved_13, 13) + GENERATE_ENUM(reserved_14, 14) + GENERATE_ENUM(reserved_15, 15) + GENERATE_ENUM(reserved_16, 16) + GENERATE_ENUM(reserved_17, 17) + GENERATE_ENUM(reserved_18, 18) + GENERATE_ENUM(reserved_19, 19) + GENERATE_ENUM(reserved_20, 20) + GENERATE_ENUM(reserved_21, 21) + GENERATE_ENUM(reserved_22, 22) + GENERATE_ENUM(reserved_23, 23) + GENERATE_ENUM(reserved_24, 24) + GENERATE_ENUM(reserved_25, 25) + GENERATE_ENUM(reserved_26, 26) + GENERATE_ENUM(reserved_27, 27) + GENERATE_ENUM(READ_STARVED_QUAD0, 28) + GENERATE_ENUM(reserved_29, 29) + GENERATE_ENUM(reserved_30, 30) + GENERATE_ENUM(reserved_31, 31) + GENERATE_ENUM(READ_STARVED, 32) + GENERATE_ENUM(READ_STALLED_QUAD0, 33) + GENERATE_ENUM(reserved_34, 34) + GENERATE_ENUM(reserved_35, 35) + GENERATE_ENUM(reserved_36, 36) + GENERATE_ENUM(READ_STALLED, 37) + GENERATE_ENUM(VALID_READ_QUAD0, 38) + GENERATE_ENUM(reserved_39, 39) + GENERATE_ENUM(reserved_40, 40) + GENERATE_ENUM(reserved_41, 41) + GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42) + GENERATE_ENUM(reserved_43, 43) + GENERATE_ENUM(reserved_44, 44) + GENERATE_ENUM(reserved_45, 45) + GENERATE_ENUM(TC_TP_STARVED, 46) +END_ENUMTYPE(TCM_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCF_PERFCOUNT_SELECT) + GENERATE_ENUM(VALID_CYCLES, 0) + GENERATE_ENUM(SINGLE_PHASES, 1) + GENERATE_ENUM(ANISO_PHASES, 2) + GENERATE_ENUM(MIP_PHASES, 3) + GENERATE_ENUM(VOL_PHASES, 4) + GENERATE_ENUM(MIP_VOL_PHASES, 5) + GENERATE_ENUM(MIP_ANISO_PHASES, 6) + GENERATE_ENUM(VOL_ANISO_PHASES, 7) + GENERATE_ENUM(ANISO_2_1_PHASES, 8) + GENERATE_ENUM(ANISO_4_1_PHASES, 9) + GENERATE_ENUM(ANISO_6_1_PHASES, 10) + GENERATE_ENUM(ANISO_8_1_PHASES, 11) + GENERATE_ENUM(ANISO_10_1_PHASES, 12) + GENERATE_ENUM(ANISO_12_1_PHASES, 13) + GENERATE_ENUM(ANISO_14_1_PHASES, 14) + GENERATE_ENUM(ANISO_16_1_PHASES, 15) + GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16) + GENERATE_ENUM(ALIGN_2_PHASES, 17) + GENERATE_ENUM(ALIGN_4_PHASES, 18) + GENERATE_ENUM(TPC_BUSY, 19) + GENERATE_ENUM(TPC_STALLED, 20) + GENERATE_ENUM(TPC_STARVED, 21) + GENERATE_ENUM(TPC_WORKING, 22) + GENERATE_ENUM(TPC_WALKER_BUSY, 23) + GENERATE_ENUM(TPC_WALKER_STALLED, 24) + GENERATE_ENUM(TPC_WALKER_WORKING, 25) + GENERATE_ENUM(TPC_ALIGNER_BUSY, 26) + GENERATE_ENUM(TPC_ALIGNER_STALLED, 27) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29) + GENERATE_ENUM(TPC_ALIGNER_WORKING, 30) + GENERATE_ENUM(TPC_BLEND_BUSY, 31) + GENERATE_ENUM(TPC_BLEND_SYNC, 32) + GENERATE_ENUM(TPC_BLEND_STARVED, 33) + GENERATE_ENUM(TPC_BLEND_WORKING, 34) + GENERATE_ENUM(OPCODE_0x00, 35) + GENERATE_ENUM(OPCODE_0x01, 36) + GENERATE_ENUM(OPCODE_0x04, 37) + GENERATE_ENUM(OPCODE_0x10, 38) + GENERATE_ENUM(OPCODE_0x11, 39) + GENERATE_ENUM(OPCODE_0x12, 40) + GENERATE_ENUM(OPCODE_0x13, 41) + GENERATE_ENUM(OPCODE_0x18, 42) + GENERATE_ENUM(OPCODE_0x19, 43) + GENERATE_ENUM(OPCODE_0x1A, 44) + GENERATE_ENUM(OPCODE_OTHER, 45) + GENERATE_ENUM(IN_FIFO_0_EMPTY, 56) + GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57) + GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58) + GENERATE_ENUM(IN_FIFO_0_FULL, 59) + GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72) + GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73) + GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74) + GENERATE_ENUM(IN_FIFO_TPC_FULL, 75) + GENERATE_ENUM(TPC_TC_XFC, 76) + GENERATE_ENUM(TPC_TC_STATE, 77) + GENERATE_ENUM(TC_STALL, 78) + GENERATE_ENUM(QUAD0_TAPS, 79) + GENERATE_ENUM(QUADS, 83) + GENERATE_ENUM(TCA_SYNC_STALL, 84) + GENERATE_ENUM(TAG_STALL, 85) + GENERATE_ENUM(TCB_SYNC_STALL, 88) + GENERATE_ENUM(TCA_VALID, 89) + GENERATE_ENUM(PROBES_VALID, 90) + GENERATE_ENUM(MISS_STALL, 91) + GENERATE_ENUM(FETCH_FIFO_STALL, 92) + GENERATE_ENUM(TCO_STALL, 93) + GENERATE_ENUM(ANY_STALL, 94) + GENERATE_ENUM(TAG_MISSES, 95) + GENERATE_ENUM(TAG_HITS, 96) + GENERATE_ENUM(SUB_TAG_MISSES, 97) + GENERATE_ENUM(SET0_INVALIDATES, 98) + GENERATE_ENUM(SET1_INVALIDATES, 99) + GENERATE_ENUM(SET2_INVALIDATES, 100) + GENERATE_ENUM(SET3_INVALIDATES, 101) + GENERATE_ENUM(SET0_TAG_MISSES, 102) + GENERATE_ENUM(SET1_TAG_MISSES, 103) + GENERATE_ENUM(SET2_TAG_MISSES, 104) + GENERATE_ENUM(SET3_TAG_MISSES, 105) + GENERATE_ENUM(SET0_TAG_HITS, 106) + GENERATE_ENUM(SET1_TAG_HITS, 107) + GENERATE_ENUM(SET2_TAG_HITS, 108) + GENERATE_ENUM(SET3_TAG_HITS, 109) + GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110) + GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111) + GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112) + GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113) + GENERATE_ENUM(SET0_EVICT1, 114) + GENERATE_ENUM(SET0_EVICT2, 115) + GENERATE_ENUM(SET0_EVICT3, 116) + GENERATE_ENUM(SET0_EVICT4, 117) + GENERATE_ENUM(SET0_EVICT5, 118) + GENERATE_ENUM(SET0_EVICT6, 119) + GENERATE_ENUM(SET0_EVICT7, 120) + GENERATE_ENUM(SET0_EVICT8, 121) + GENERATE_ENUM(SET1_EVICT1, 130) + GENERATE_ENUM(SET1_EVICT2, 131) + GENERATE_ENUM(SET1_EVICT3, 132) + GENERATE_ENUM(SET1_EVICT4, 133) + GENERATE_ENUM(SET1_EVICT5, 134) + GENERATE_ENUM(SET1_EVICT6, 135) + GENERATE_ENUM(SET1_EVICT7, 136) + GENERATE_ENUM(SET1_EVICT8, 137) + GENERATE_ENUM(SET2_EVICT1, 146) + GENERATE_ENUM(SET2_EVICT2, 147) + GENERATE_ENUM(SET2_EVICT3, 148) + GENERATE_ENUM(SET2_EVICT4, 149) + GENERATE_ENUM(SET2_EVICT5, 150) + GENERATE_ENUM(SET2_EVICT6, 151) + GENERATE_ENUM(SET2_EVICT7, 152) + GENERATE_ENUM(SET2_EVICT8, 153) + GENERATE_ENUM(SET3_EVICT1, 162) + GENERATE_ENUM(SET3_EVICT2, 163) + GENERATE_ENUM(SET3_EVICT3, 164) + GENERATE_ENUM(SET3_EVICT4, 165) + GENERATE_ENUM(SET3_EVICT5, 166) + GENERATE_ENUM(SET3_EVICT6, 167) + GENERATE_ENUM(SET3_EVICT7, 168) + GENERATE_ENUM(SET3_EVICT8, 169) + GENERATE_ENUM(FF_EMPTY, 178) + GENERATE_ENUM(FF_LT_HALF_FULL, 179) + GENERATE_ENUM(FF_HALF_FULL, 180) + GENERATE_ENUM(FF_FULL, 181) + GENERATE_ENUM(FF_XFC, 182) + GENERATE_ENUM(FF_STALLED, 183) + GENERATE_ENUM(FG_MASKS, 184) + GENERATE_ENUM(FG_LEFT_MASKS, 185) + GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186) + GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187) + GENERATE_ENUM(FG_LEFT_FG_STALL, 188) + GENERATE_ENUM(FG_LEFT_SECTORS, 189) + GENERATE_ENUM(FG0_REQUESTS, 195) + GENERATE_ENUM(FG0_STALLED, 196) + GENERATE_ENUM(MEM_REQ512, 199) + GENERATE_ENUM(MEM_REQ_SENT, 200) + GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202) + GENERATE_ENUM(TC0_MH_STALLED, 203) +END_ENUMTYPE(TCF_PERFCOUNT_SELECT) + +START_ENUMTYPE(SQ_PERFCNT_SELECT) + GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0) + GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9) + GENERATE_ENUM(SQ_EXPORT_CYCLES, 10) + GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11) + GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12) + GENERATE_ENUM(SQ_ALU_CST_STALL, 13) + GENERATE_ENUM(SQ_ALU_TEX_STALL, 14) + GENERATE_ENUM(SQ_INST_WRITTEN, 15) + GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16) + GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17) + GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18) + GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19) + GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20) + GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21) + GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22) + GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23) + GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24) + GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25) + GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26) + GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27) + GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28) + GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33) + GENERATE_ENUM(SQ_ALU_NOPS, 34) + GENERATE_ENUM(SQ_PRED_SKIP, 35) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38) + GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41) + GENERATE_ENUM(SQ_GPR_STALL_VTX, 42) + GENERATE_ENUM(SQ_GPR_STALL_PIX, 43) + GENERATE_ENUM(SQ_VTX_RS_STALL, 44) + GENERATE_ENUM(SQ_PIX_RS_STALL, 45) + GENERATE_ENUM(SQ_SX_PC_FULL, 46) + GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47) + GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48) + GENERATE_ENUM(SQ_INTERP_QUADS, 49) + GENERATE_ENUM(SQ_INTERP_ACTIVE, 50) + GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51) + GENERATE_ENUM(SQ_IN_VTX_STALL, 52) + GENERATE_ENUM(SQ_VTX_CNT, 53) + GENERATE_ENUM(SQ_VTX_VECTOR2, 54) + GENERATE_ENUM(SQ_VTX_VECTOR3, 55) + GENERATE_ENUM(SQ_VTX_VECTOR4, 56) + GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57) + GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58) + GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61) + GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81) + GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94) + GENERATE_ENUM(VC_PERF_STATIC, 95) + GENERATE_ENUM(VC_PERF_STALLED, 96) + GENERATE_ENUM(VC_PERF_STARVED, 97) + GENERATE_ENUM(VC_PERF_SEND, 98) + GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99) + GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100) + GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101) + GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102) + GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103) + GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104) + GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105) + GENERATE_ENUM(PTRBUFF_EF_PUSH, 106) + GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107) + GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108) + GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112) + GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113) + GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114) + GENERATE_ENUM(PTRBUFF_PI_RTR, 115) + GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116) + GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117) + GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118) + GENERATE_ENUM(PTRBUFF_SQ_DEC, 119) + GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120) + GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121) + GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122) + GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123) + GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124) + GENERATE_ENUM(PTRBUFF_END_BUFFER, 125) + GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126) + GENERATE_ENUM(VERTS_WRITTEN_SPI, 127) + GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128) + GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129) + GENERATE_ENUM(TP_DATA_RETURN, 130) + GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131) + GENERATE_ENUM(SPI_WRITES_SP, 132) + GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133) + GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134) + GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135) + GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136) + GENERATE_ENUM(SP_EXPORTS_TO_SX, 137) + GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138) + GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139) + GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140) + GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141) + GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142) + GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143) + GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144) + GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145) + GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146) + GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147) + GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148) + GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149) + GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150) + GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151) + GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152) + GENERATE_ENUM(SQ_PIX_TOTAL, 153) + GENERATE_ENUM(SQ_PIX_KILLED, 154) +END_ENUMTYPE(SQ_PERFCNT_SELECT) + +START_ENUMTYPE(SX_PERFCNT_SELECT) + GENERATE_ENUM(SX_EXPORT_VECTORS, 0) + GENERATE_ENUM(SX_DUMMY_QUADS, 1) + GENERATE_ENUM(SX_ALPHA_FAIL, 2) + GENERATE_ENUM(SX_RB_QUAD_BUSY, 3) + GENERATE_ENUM(SX_RB_COLOR_BUSY, 4) + GENERATE_ENUM(SX_RB_QUAD_STALL, 5) + GENERATE_ENUM(SX_RB_COLOR_STALL, 6) +END_ENUMTYPE(SX_PERFCNT_SELECT) + +START_ENUMTYPE(Abs_modifier) + GENERATE_ENUM(NO_ABS_MOD, 0) + GENERATE_ENUM(ABS_MOD, 1) +END_ENUMTYPE(Abs_modifier) + +START_ENUMTYPE(Exporting) + GENERATE_ENUM(NOT_EXPORTING, 0) + GENERATE_ENUM(EXPORTING, 1) +END_ENUMTYPE(Exporting) + +START_ENUMTYPE(ScalarOpcode) + GENERATE_ENUM(ADDs, 0) + GENERATE_ENUM(ADD_PREVs, 1) + GENERATE_ENUM(MULs, 2) + GENERATE_ENUM(MUL_PREVs, 3) + GENERATE_ENUM(MUL_PREV2s, 4) + GENERATE_ENUM(MAXs, 5) + GENERATE_ENUM(MINs, 6) + GENERATE_ENUM(SETEs, 7) + GENERATE_ENUM(SETGTs, 8) + GENERATE_ENUM(SETGTEs, 9) + GENERATE_ENUM(SETNEs, 10) + GENERATE_ENUM(FRACs, 11) + GENERATE_ENUM(TRUNCs, 12) + GENERATE_ENUM(FLOORs, 13) + GENERATE_ENUM(EXP_IEEE, 14) + GENERATE_ENUM(LOG_CLAMP, 15) + GENERATE_ENUM(LOG_IEEE, 16) + GENERATE_ENUM(RECIP_CLAMP, 17) + GENERATE_ENUM(RECIP_FF, 18) + GENERATE_ENUM(RECIP_IEEE, 19) + GENERATE_ENUM(RECIPSQ_CLAMP, 20) + GENERATE_ENUM(RECIPSQ_FF, 21) + GENERATE_ENUM(RECIPSQ_IEEE, 22) + GENERATE_ENUM(MOVAs, 23) + GENERATE_ENUM(MOVA_FLOORs, 24) + GENERATE_ENUM(SUBs, 25) + GENERATE_ENUM(SUB_PREVs, 26) + GENERATE_ENUM(PRED_SETEs, 27) + GENERATE_ENUM(PRED_SETNEs, 28) + GENERATE_ENUM(PRED_SETGTs, 29) + GENERATE_ENUM(PRED_SETGTEs, 30) + GENERATE_ENUM(PRED_SET_INVs, 31) + GENERATE_ENUM(PRED_SET_POPs, 32) + GENERATE_ENUM(PRED_SET_CLRs, 33) + GENERATE_ENUM(PRED_SET_RESTOREs, 34) + GENERATE_ENUM(KILLEs, 35) + GENERATE_ENUM(KILLGTs, 36) + GENERATE_ENUM(KILLGTEs, 37) + GENERATE_ENUM(KILLNEs, 38) + GENERATE_ENUM(KILLONEs, 39) + GENERATE_ENUM(SQRT_IEEE, 40) + GENERATE_ENUM(MUL_CONST_0, 42) + GENERATE_ENUM(MUL_CONST_1, 43) + GENERATE_ENUM(ADD_CONST_0, 44) + GENERATE_ENUM(ADD_CONST_1, 45) + GENERATE_ENUM(SUB_CONST_0, 46) + GENERATE_ENUM(SUB_CONST_1, 47) + GENERATE_ENUM(SIN, 48) + GENERATE_ENUM(COS, 49) + GENERATE_ENUM(RETAIN_PREV, 50) +END_ENUMTYPE(ScalarOpcode) + +START_ENUMTYPE(SwizzleType) + GENERATE_ENUM(NO_SWIZZLE, 0) + GENERATE_ENUM(SHIFT_RIGHT_1, 1) + GENERATE_ENUM(SHIFT_RIGHT_2, 2) + GENERATE_ENUM(SHIFT_RIGHT_3, 3) +END_ENUMTYPE(SwizzleType) + +START_ENUMTYPE(InputModifier) + GENERATE_ENUM(NIL, 0) + GENERATE_ENUM(NEGATE, 1) +END_ENUMTYPE(InputModifier) + +START_ENUMTYPE(PredicateSelect) + GENERATE_ENUM(NO_PREDICATION, 0) + GENERATE_ENUM(PREDICATE_QUAD, 1) + GENERATE_ENUM(PREDICATED_2, 2) + GENERATE_ENUM(PREDICATED_3, 3) +END_ENUMTYPE(PredicateSelect) + +START_ENUMTYPE(OperandSelect1) + GENERATE_ENUM(ABSOLUTE_REG, 0) + GENERATE_ENUM(RELATIVE_REG, 1) +END_ENUMTYPE(OperandSelect1) + +START_ENUMTYPE(VectorOpcode) + GENERATE_ENUM(ADDv, 0) + GENERATE_ENUM(MULv, 1) + GENERATE_ENUM(MAXv, 2) + GENERATE_ENUM(MINv, 3) + GENERATE_ENUM(SETEv, 4) + GENERATE_ENUM(SETGTv, 5) + GENERATE_ENUM(SETGTEv, 6) + GENERATE_ENUM(SETNEv, 7) + GENERATE_ENUM(FRACv, 8) + GENERATE_ENUM(TRUNCv, 9) + GENERATE_ENUM(FLOORv, 10) + GENERATE_ENUM(MULADDv, 11) + GENERATE_ENUM(CNDEv, 12) + GENERATE_ENUM(CNDGTEv, 13) + GENERATE_ENUM(CNDGTv, 14) + GENERATE_ENUM(DOT4v, 15) + GENERATE_ENUM(DOT3v, 16) + GENERATE_ENUM(DOT2ADDv, 17) + GENERATE_ENUM(CUBEv, 18) + GENERATE_ENUM(MAX4v, 19) + GENERATE_ENUM(PRED_SETE_PUSHv, 20) + GENERATE_ENUM(PRED_SETNE_PUSHv, 21) + GENERATE_ENUM(PRED_SETGT_PUSHv, 22) + GENERATE_ENUM(PRED_SETGTE_PUSHv, 23) + GENERATE_ENUM(KILLEv, 24) + GENERATE_ENUM(KILLGTv, 25) + GENERATE_ENUM(KILLGTEv, 26) + GENERATE_ENUM(KILLNEv, 27) + GENERATE_ENUM(DSTv, 28) + GENERATE_ENUM(MOVAv, 29) +END_ENUMTYPE(VectorOpcode) + +START_ENUMTYPE(OperandSelect0) + GENERATE_ENUM(CONSTANT, 0) + GENERATE_ENUM(NON_CONSTANT, 1) +END_ENUMTYPE(OperandSelect0) + +START_ENUMTYPE(Ressource_type) + GENERATE_ENUM(ALU, 0) + GENERATE_ENUM(TEXTURE, 1) +END_ENUMTYPE(Ressource_type) + +START_ENUMTYPE(Instruction_serial) + GENERATE_ENUM(NOT_SERIAL, 0) + GENERATE_ENUM(SERIAL, 1) +END_ENUMTYPE(Instruction_serial) + +START_ENUMTYPE(VC_type) + GENERATE_ENUM(ALU_TP_REQUEST, 0) + GENERATE_ENUM(VC_REQUEST, 1) +END_ENUMTYPE(VC_type) + +START_ENUMTYPE(Addressing) + GENERATE_ENUM(RELATIVE_ADDR, 0) + GENERATE_ENUM(ABSOLUTE_ADDR, 1) +END_ENUMTYPE(Addressing) + +START_ENUMTYPE(CFOpcode) + GENERATE_ENUM(NOP, 0) + GENERATE_ENUM(EXECUTE, 1) + GENERATE_ENUM(EXECUTE_END, 2) + GENERATE_ENUM(COND_EXECUTE, 3) + GENERATE_ENUM(COND_EXECUTE_END, 4) + GENERATE_ENUM(COND_PRED_EXECUTE, 5) + GENERATE_ENUM(COND_PRED_EXECUTE_END, 6) + GENERATE_ENUM(LOOP_START, 7) + GENERATE_ENUM(LOOP_END, 8) + GENERATE_ENUM(COND_CALL, 9) + GENERATE_ENUM(RETURN, 10) + GENERATE_ENUM(COND_JMP, 11) + GENERATE_ENUM(ALLOCATE, 12) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14) + GENERATE_ENUM(MARK_VS_FETCH_DONE, 15) +END_ENUMTYPE(CFOpcode) + +START_ENUMTYPE(Allocation_type) + GENERATE_ENUM(SQ_NO_ALLOC, 0) + GENERATE_ENUM(SQ_POSITION, 1) + GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2) + GENERATE_ENUM(SQ_MEMORY, 3) +END_ENUMTYPE(Allocation_type) + +START_ENUMTYPE(TexInstOpcode) + GENERATE_ENUM(TEX_INST_FETCH, 1) + GENERATE_ENUM(TEX_INST_RESERVED_1, 2) + GENERATE_ENUM(TEX_INST_RESERVED_2, 3) + GENERATE_ENUM(TEX_INST_RESERVED_3, 4) + GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16) + GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17) + GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18) + GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19) + GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26) + GENERATE_ENUM(TEX_INST_RESERVED_4, 27) +END_ENUMTYPE(TexInstOpcode) + +START_ENUMTYPE(Addressmode) + GENERATE_ENUM(LOGICAL, 0) + GENERATE_ENUM(LOOP_RELATIVE, 1) +END_ENUMTYPE(Addressmode) + +START_ENUMTYPE(TexCoordDenorm) + GENERATE_ENUM(TEX_COORD_NORMALIZED, 0) + GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1) +END_ENUMTYPE(TexCoordDenorm) + +START_ENUMTYPE(SrcSel) + GENERATE_ENUM(SRC_SEL_X, 0) + GENERATE_ENUM(SRC_SEL_Y, 1) + GENERATE_ENUM(SRC_SEL_Z, 2) + GENERATE_ENUM(SRC_SEL_W, 3) +END_ENUMTYPE(SrcSel) + +START_ENUMTYPE(DstSel) + GENERATE_ENUM(DST_SEL_X, 0) + GENERATE_ENUM(DST_SEL_Y, 1) + GENERATE_ENUM(DST_SEL_Z, 2) + GENERATE_ENUM(DST_SEL_W, 3) + GENERATE_ENUM(DST_SEL_0, 4) + GENERATE_ENUM(DST_SEL_1, 5) + GENERATE_ENUM(DST_SEL_RSVD, 6) + GENERATE_ENUM(DST_SEL_MASK, 7) +END_ENUMTYPE(DstSel) + +START_ENUMTYPE(MagFilter) + GENERATE_ENUM(MAG_FILTER_POINT, 0) + GENERATE_ENUM(MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MagFilter) + +START_ENUMTYPE(MinFilter) + GENERATE_ENUM(MIN_FILTER_POINT, 0) + GENERATE_ENUM(MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MinFilter) + +START_ENUMTYPE(MipFilter) + GENERATE_ENUM(MIP_FILTER_POINT, 0) + GENERATE_ENUM(MIP_FILTER_LINEAR, 1) + GENERATE_ENUM(MIP_FILTER_BASEMAP, 2) + GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MipFilter) + +START_ENUMTYPE(AnisoFilter) + GENERATE_ENUM(ANISO_FILTER_DISABLED, 0) + GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1) + GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2) + GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3) + GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4) + GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5) + GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(AnisoFilter) + +START_ENUMTYPE(ArbitraryFilter) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5) + GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(ArbitraryFilter) + +START_ENUMTYPE(VolMagFilter) + GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMagFilter) + +START_ENUMTYPE(VolMinFilter) + GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMinFilter) + +START_ENUMTYPE(PredSelect) + GENERATE_ENUM(NOT_PREDICATED, 0) + GENERATE_ENUM(PREDICATED, 1) +END_ENUMTYPE(PredSelect) + +START_ENUMTYPE(SampleLocation) + GENERATE_ENUM(SAMPLE_CENTROID, 0) + GENERATE_ENUM(SAMPLE_CENTER, 1) +END_ENUMTYPE(SampleLocation) + +START_ENUMTYPE(VertexMode) + GENERATE_ENUM(POSITION_1_VECTOR, 0) + GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3) + GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6) + GENERATE_ENUM(MULTIPASS, 7) +END_ENUMTYPE(VertexMode) + +START_ENUMTYPE(Sample_Cntl) + GENERATE_ENUM(CENTROIDS_ONLY, 0) + GENERATE_ENUM(CENTERS_ONLY, 1) + GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2) + GENERATE_ENUM(UNDEF, 3) +END_ENUMTYPE(Sample_Cntl) + +START_ENUMTYPE(MhPerfEncode) + GENERATE_ENUM(CP_R0_REQUESTS, 0) + GENERATE_ENUM(CP_R1_REQUESTS, 1) + GENERATE_ENUM(CP_R2_REQUESTS, 2) + GENERATE_ENUM(CP_R3_REQUESTS, 3) + GENERATE_ENUM(CP_R4_REQUESTS, 4) + GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5) + GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6) + GENERATE_ENUM(CP_TOTAL_REQUESTS, 7) + GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8) + GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9) + GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10) + GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11) + GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12) + GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13) + GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14) + GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15) + GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16) + GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17) + GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18) + GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19) + GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20) + GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21) + GENERATE_ENUM(VGT_R0_REQUESTS, 22) + GENERATE_ENUM(VGT_R1_REQUESTS, 23) + GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24) + GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25) + GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26) + GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27) + GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28) + GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29) + GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30) + GENERATE_ENUM(TC_TOTAL_REQUESTS, 31) + GENERATE_ENUM(TC_ROQ_REQUESTS, 32) + GENERATE_ENUM(TC_INFO_SENT, 33) + GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34) + GENERATE_ENUM(TC_DATA_BEATS_READ, 35) + GENERATE_ENUM(TCD_BURSTS_READ, 36) + GENERATE_ENUM(RB_REQUESTS, 37) + GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38) + GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47) + GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56) + GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65) + GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111) + GENERATE_ENUM(TOTAL_MMU_MISSES, 112) + GENERATE_ENUM(MMU_READ_MISSES, 113) + GENERATE_ENUM(MMU_WRITE_MISSES, 114) + GENERATE_ENUM(TOTAL_MMU_HITS, 115) + GENERATE_ENUM(MMU_READ_HITS, 116) + GENERATE_ENUM(MMU_WRITE_HITS, 117) + GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118) + GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119) + GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120) + GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121) + GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122) + GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123) + GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124) + GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125) + GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126) + GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127) + GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128) + GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129) + GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130) + GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131) + GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132) + GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133) + GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136) + GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140) + GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148) + GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149) + GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150) + GENERATE_ENUM(TOTAL_MH_REQUESTS, 151) + GENERATE_ENUM(MH_BUSY, 152) + GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153) + GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154) + GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155) + GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156) + GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157) + GENERATE_ENUM(ARQ_N_ENTRIES, 158) + GENERATE_ENUM(WDB_N_ENTRIES, 159) + GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160) + GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161) + GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162) + GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163) + GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164) + GENERATE_ENUM(CP_W_16B_REQUESTS, 165) + GENERATE_ENUM(CP_W_32B_REQUESTS, 166) + GENERATE_ENUM(TC_16B_REQUESTS, 167) + GENERATE_ENUM(TC_32B_REQUESTS, 168) + GENERATE_ENUM(PA_REQUESTS, 169) + GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170) + GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171) + GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180) + GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181) +END_ENUMTYPE(MhPerfEncode) + +START_ENUMTYPE(MmuClntBeh) + GENERATE_ENUM(BEH_NEVR, 0) + GENERATE_ENUM(BEH_TRAN_RNG, 1) + GENERATE_ENUM(BEH_TRAN_FLT, 2) +END_ENUMTYPE(MmuClntBeh) + +START_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + GENERATE_ENUM(RBBM1_COUNT, 0) + GENERATE_ENUM(RBBM1_NRT_BUSY, 1) + GENERATE_ENUM(RBBM1_RB_BUSY, 2) + GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3) + GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4) + GENERATE_ENUM(RBBM1_VGT_BUSY, 5) + GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6) + GENERATE_ENUM(RBBM1_PA_BUSY, 7) + GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8) + GENERATE_ENUM(RBBM1_TPC_BUSY, 9) + GENERATE_ENUM(RBBM1_TC_BUSY, 10) + GENERATE_ENUM(RBBM1_SX_BUSY, 11) + GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12) + GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13) + GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14) + GENERATE_ENUM(RBBM1_INTERRUPT, 15) +END_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + +START_ENUMTYPE(CP_PERFCOUNT_SEL) + GENERATE_ENUM(ALWAYS_COUNT, 0) + GENERATE_ENUM(TRANS_FIFO_FULL, 1) + GENERATE_ENUM(TRANS_FIFO_AF, 2) + GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3) + GENERATE_ENUM(Reserved_04, 4) + GENERATE_ENUM(Reserved_05, 5) + GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6) + GENERATE_ENUM(Reserved_07, 7) + GENERATE_ENUM(CSF_NRT_READ_WAIT, 8) + GENERATE_ENUM(CSF_I1_FIFO_FULL, 9) + GENERATE_ENUM(CSF_I2_FIFO_FULL, 10) + GENERATE_ENUM(CSF_ST_FIFO_FULL, 11) + GENERATE_ENUM(Reserved_12, 12) + GENERATE_ENUM(CSF_RING_ROQ_FULL, 13) + GENERATE_ENUM(CSF_I1_ROQ_FULL, 14) + GENERATE_ENUM(CSF_I2_ROQ_FULL, 15) + GENERATE_ENUM(CSF_ST_ROQ_FULL, 16) + GENERATE_ENUM(Reserved_17, 17) + GENERATE_ENUM(MIU_TAG_MEM_FULL, 18) + GENERATE_ENUM(MIU_WRITECLEAN, 19) + GENERATE_ENUM(Reserved_20, 20) + GENERATE_ENUM(Reserved_21, 21) + GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22) + GENERATE_ENUM(MIU_NRT_READ_STALLED, 23) + GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24) + GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25) + GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26) + GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27) + GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28) + GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29) + GENERATE_ENUM(ME_MICRO_RB_STARVED, 30) + GENERATE_ENUM(ME_MICRO_I1_STARVED, 31) + GENERATE_ENUM(ME_MICRO_I2_STARVED, 32) + GENERATE_ENUM(ME_MICRO_ST_STARVED, 33) + GENERATE_ENUM(Reserved_34, 34) + GENERATE_ENUM(Reserved_35, 35) + GENERATE_ENUM(Reserved_36, 36) + GENERATE_ENUM(Reserved_37, 37) + GENERATE_ENUM(Reserved_38, 38) + GENERATE_ENUM(Reserved_39, 39) + GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40) + GENERATE_ENUM(ME_BUSY_CLOCKS, 41) + GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42) + GENERATE_ENUM(PFP_TYPE0_PACKET, 43) + GENERATE_ENUM(PFP_TYPE3_PACKET, 44) + GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45) + GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46) + GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47) + GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48) + GENERATE_ENUM(Reserved_49, 49) + GENERATE_ENUM(Reserved_50, 50) + GENERATE_ENUM(Reserved_51, 51) + GENERATE_ENUM(Reserved_52, 52) + GENERATE_ENUM(Reserved_53, 53) + GENERATE_ENUM(Reserved_54, 54) + GENERATE_ENUM(Reserved_55, 55) + GENERATE_ENUM(Reserved_56, 56) + GENERATE_ENUM(Reserved_57, 57) + GENERATE_ENUM(Reserved_58, 58) + GENERATE_ENUM(Reserved_59, 59) + GENERATE_ENUM(Reserved_60, 60) + GENERATE_ENUM(Reserved_61, 61) + GENERATE_ENUM(Reserved_62, 62) + GENERATE_ENUM(Reserved_63, 63) +END_ENUMTYPE(CP_PERFCOUNT_SEL) + +START_ENUMTYPE(ColorformatX) + GENERATE_ENUM(COLORX_4_4_4_4, 0) + GENERATE_ENUM(COLORX_1_5_5_5, 1) + GENERATE_ENUM(COLORX_5_6_5, 2) + GENERATE_ENUM(COLORX_8, 3) + GENERATE_ENUM(COLORX_8_8, 4) + GENERATE_ENUM(COLORX_8_8_8_8, 5) + GENERATE_ENUM(COLORX_S8_8_8_8, 6) + GENERATE_ENUM(COLORX_16_FLOAT, 7) + GENERATE_ENUM(COLORX_16_16_FLOAT, 8) + GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9) + GENERATE_ENUM(COLORX_32_FLOAT, 10) + GENERATE_ENUM(COLORX_32_32_FLOAT, 11) + GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12) + GENERATE_ENUM(COLORX_2_3_3, 13) + GENERATE_ENUM(COLORX_8_8_8, 14) +END_ENUMTYPE(ColorformatX) + +START_ENUMTYPE(DepthformatX) + GENERATE_ENUM(DEPTHX_16, 0) + GENERATE_ENUM(DEPTHX_24_8, 1) +END_ENUMTYPE(DepthformatX) + +START_ENUMTYPE(CompareFrag) + GENERATE_ENUM(FRAG_NEVER, 0) + GENERATE_ENUM(FRAG_LESS, 1) + GENERATE_ENUM(FRAG_EQUAL, 2) + GENERATE_ENUM(FRAG_LEQUAL, 3) + GENERATE_ENUM(FRAG_GREATER, 4) + GENERATE_ENUM(FRAG_NOTEQUAL, 5) + GENERATE_ENUM(FRAG_GEQUAL, 6) + GENERATE_ENUM(FRAG_ALWAYS, 7) +END_ENUMTYPE(CompareFrag) + +START_ENUMTYPE(CompareRef) + GENERATE_ENUM(REF_NEVER, 0) + GENERATE_ENUM(REF_LESS, 1) + GENERATE_ENUM(REF_EQUAL, 2) + GENERATE_ENUM(REF_LEQUAL, 3) + GENERATE_ENUM(REF_GREATER, 4) + GENERATE_ENUM(REF_NOTEQUAL, 5) + GENERATE_ENUM(REF_GEQUAL, 6) + GENERATE_ENUM(REF_ALWAYS, 7) +END_ENUMTYPE(CompareRef) + +START_ENUMTYPE(StencilOp) + GENERATE_ENUM(STENCIL_KEEP, 0) + GENERATE_ENUM(STENCIL_ZERO, 1) + GENERATE_ENUM(STENCIL_REPLACE, 2) + GENERATE_ENUM(STENCIL_INCR_CLAMP, 3) + GENERATE_ENUM(STENCIL_DECR_CLAMP, 4) + GENERATE_ENUM(STENCIL_INVERT, 5) + GENERATE_ENUM(STENCIL_INCR_WRAP, 6) + GENERATE_ENUM(STENCIL_DECR_WRAP, 7) +END_ENUMTYPE(StencilOp) + +START_ENUMTYPE(BlendOpX) + GENERATE_ENUM(BLENDX_ZERO, 0) + GENERATE_ENUM(BLENDX_ONE, 1) + GENERATE_ENUM(BLENDX_SRC_COLOR, 4) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5) + GENERATE_ENUM(BLENDX_SRC_ALPHA, 6) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7) + GENERATE_ENUM(BLENDX_DST_COLOR, 8) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9) + GENERATE_ENUM(BLENDX_DST_ALPHA, 10) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11) + GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13) + GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15) + GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16) +END_ENUMTYPE(BlendOpX) + +START_ENUMTYPE(CombFuncX) + GENERATE_ENUM(COMB_DST_PLUS_SRC, 0) + GENERATE_ENUM(COMB_SRC_MINUS_DST, 1) + GENERATE_ENUM(COMB_MIN_DST_SRC, 2) + GENERATE_ENUM(COMB_MAX_DST_SRC, 3) + GENERATE_ENUM(COMB_DST_MINUS_SRC, 4) + GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5) +END_ENUMTYPE(CombFuncX) + +START_ENUMTYPE(DitherModeX) + GENERATE_ENUM(DITHER_DISABLE, 0) + GENERATE_ENUM(DITHER_ALWAYS, 1) + GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2) +END_ENUMTYPE(DitherModeX) + +START_ENUMTYPE(DitherTypeX) + GENERATE_ENUM(DITHER_PIXEL, 0) + GENERATE_ENUM(DITHER_SUBPIXEL, 1) +END_ENUMTYPE(DitherTypeX) + +START_ENUMTYPE(EdramMode) + GENERATE_ENUM(EDRAM_NOP, 0) + GENERATE_ENUM(COLOR_DEPTH, 4) + GENERATE_ENUM(DEPTH_ONLY, 5) + GENERATE_ENUM(EDRAM_COPY, 6) +END_ENUMTYPE(EdramMode) + +START_ENUMTYPE(SurfaceEndian) + GENERATE_ENUM(ENDIAN_NONE, 0) + GENERATE_ENUM(ENDIAN_8IN16, 1) + GENERATE_ENUM(ENDIAN_8IN32, 2) + GENERATE_ENUM(ENDIAN_16IN32, 3) + GENERATE_ENUM(ENDIAN_8IN64, 4) + GENERATE_ENUM(ENDIAN_8IN128, 5) +END_ENUMTYPE(SurfaceEndian) + +START_ENUMTYPE(EdramSizeX) + GENERATE_ENUM(EDRAMSIZE_16KB, 0) + GENERATE_ENUM(EDRAMSIZE_32KB, 1) + GENERATE_ENUM(EDRAMSIZE_64KB, 2) + GENERATE_ENUM(EDRAMSIZE_128KB, 3) + GENERATE_ENUM(EDRAMSIZE_256KB, 4) + GENERATE_ENUM(EDRAMSIZE_512KB, 5) + GENERATE_ENUM(EDRAMSIZE_1MB, 6) + GENERATE_ENUM(EDRAMSIZE_2MB, 7) + GENERATE_ENUM(EDRAMSIZE_4MB, 8) + GENERATE_ENUM(EDRAMSIZE_8MB, 9) + GENERATE_ENUM(EDRAMSIZE_16MB, 10) +END_ENUMTYPE(EdramSizeX) + +START_ENUMTYPE(RB_PERFCNT_SELECT) + GENERATE_ENUM(RBPERF_CNTX_BUSY, 0) + GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7) + GENERATE_ENUM(RBPERF_MH_STARVED, 8) + GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23) + GENERATE_ENUM(RBPERF_ZXP_STALL, 24) + GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25) + GENERATE_ENUM(RBPERF_EVENT_PENDING, 26) + GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27) + GENERATE_ENUM(RBPERF_RB_MH_VALID, 28) + GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30) + GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31) + GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32) + GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33) + GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37) + GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38) + GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39) + GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40) + GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41) + GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42) + GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43) + GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44) + GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45) + GENERATE_ENUM(RBPERF_ZPASS_DONE, 46) + GENERATE_ENUM(RBPERF_ZCMD_VALID, 47) + GENERATE_ENUM(RBPERF_CCMD_VALID, 48) + GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49) + GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50) + GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51) + GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52) + GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53) + GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54) + GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55) + GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56) +END_ENUMTYPE(RB_PERFCNT_SELECT) + +START_ENUMTYPE(DepthFormat) + GENERATE_ENUM(DEPTH_24_8, 22) + GENERATE_ENUM(DEPTH_24_8_FLOAT, 23) + GENERATE_ENUM(DEPTH_16, 24) +END_ENUMTYPE(DepthFormat) + +START_ENUMTYPE(SurfaceSwap) + GENERATE_ENUM(SWAP_LOWRED, 0) + GENERATE_ENUM(SWAP_LOWBLUE, 1) +END_ENUMTYPE(SurfaceSwap) + +START_ENUMTYPE(DepthArray) + GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0) + GENERATE_ENUM(ARRAY_2D_DEPTH, 1) +END_ENUMTYPE(DepthArray) + +START_ENUMTYPE(ColorArray) + GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0) + GENERATE_ENUM(ARRAY_2D_COLOR, 1) + GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3) +END_ENUMTYPE(ColorArray) + +START_ENUMTYPE(ColorFormat) + GENERATE_ENUM(COLOR_8, 2) + GENERATE_ENUM(COLOR_1_5_5_5, 3) + GENERATE_ENUM(COLOR_5_6_5, 4) + GENERATE_ENUM(COLOR_6_5_5, 5) + GENERATE_ENUM(COLOR_8_8_8_8, 6) + GENERATE_ENUM(COLOR_2_10_10_10, 7) + GENERATE_ENUM(COLOR_8_A, 8) + GENERATE_ENUM(COLOR_8_B, 9) + GENERATE_ENUM(COLOR_8_8, 10) + GENERATE_ENUM(COLOR_8_8_8, 11) + GENERATE_ENUM(COLOR_8_8_8_8_A, 14) + GENERATE_ENUM(COLOR_4_4_4_4, 15) + GENERATE_ENUM(COLOR_10_11_11, 16) + GENERATE_ENUM(COLOR_11_11_10, 17) + GENERATE_ENUM(COLOR_16, 24) + GENERATE_ENUM(COLOR_16_16, 25) + GENERATE_ENUM(COLOR_16_16_16_16, 26) + GENERATE_ENUM(COLOR_16_FLOAT, 30) + GENERATE_ENUM(COLOR_16_16_FLOAT, 31) + GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(COLOR_32_FLOAT, 36) + GENERATE_ENUM(COLOR_32_32_FLOAT, 37) + GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(COLOR_2_3_3, 39) +END_ENUMTYPE(ColorFormat) + +START_ENUMTYPE(SurfaceNumber) + GENERATE_ENUM(NUMBER_UREPEAT, 0) + GENERATE_ENUM(NUMBER_SREPEAT, 1) + GENERATE_ENUM(NUMBER_UINTEGER, 2) + GENERATE_ENUM(NUMBER_SINTEGER, 3) + GENERATE_ENUM(NUMBER_GAMMA, 4) + GENERATE_ENUM(NUMBER_FIXED, 5) + GENERATE_ENUM(NUMBER_FLOAT, 7) +END_ENUMTYPE(SurfaceNumber) + +START_ENUMTYPE(SurfaceFormat) + GENERATE_ENUM(FMT_1_REVERSE, 0) + GENERATE_ENUM(FMT_1, 1) + GENERATE_ENUM(FMT_8, 2) + GENERATE_ENUM(FMT_1_5_5_5, 3) + GENERATE_ENUM(FMT_5_6_5, 4) + GENERATE_ENUM(FMT_6_5_5, 5) + GENERATE_ENUM(FMT_8_8_8_8, 6) + GENERATE_ENUM(FMT_2_10_10_10, 7) + GENERATE_ENUM(FMT_8_A, 8) + GENERATE_ENUM(FMT_8_B, 9) + GENERATE_ENUM(FMT_8_8, 10) + GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11) + GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12) + GENERATE_ENUM(FMT_5_5_5_1, 13) + GENERATE_ENUM(FMT_8_8_8_8_A, 14) + GENERATE_ENUM(FMT_4_4_4_4, 15) + GENERATE_ENUM(FMT_8_8_8, 16) + GENERATE_ENUM(FMT_DXT1, 18) + GENERATE_ENUM(FMT_DXT2_3, 19) + GENERATE_ENUM(FMT_DXT4_5, 20) + GENERATE_ENUM(FMT_10_10_10_2, 21) + GENERATE_ENUM(FMT_24_8, 22) + GENERATE_ENUM(FMT_16, 24) + GENERATE_ENUM(FMT_16_16, 25) + GENERATE_ENUM(FMT_16_16_16_16, 26) + GENERATE_ENUM(FMT_16_EXPAND, 27) + GENERATE_ENUM(FMT_16_16_EXPAND, 28) + GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29) + GENERATE_ENUM(FMT_16_FLOAT, 30) + GENERATE_ENUM(FMT_16_16_FLOAT, 31) + GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(FMT_32, 33) + GENERATE_ENUM(FMT_32_32, 34) + GENERATE_ENUM(FMT_32_32_32_32, 35) + GENERATE_ENUM(FMT_32_FLOAT, 36) + GENERATE_ENUM(FMT_32_32_FLOAT, 37) + GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(FMT_ATI_TC_RGB, 39) + GENERATE_ENUM(FMT_ATI_TC_RGBA, 40) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42) + GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44) + GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46) + GENERATE_ENUM(FMT_ETC1_RGB, 47) + GENERATE_ENUM(FMT_ETC1_RGBA, 48) + GENERATE_ENUM(FMT_DXN, 49) + GENERATE_ENUM(FMT_2_3_3, 51) + GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54) + GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55) + GENERATE_ENUM(FMT_32_32_32_FLOAT, 57) + GENERATE_ENUM(FMT_DXT3A, 58) + GENERATE_ENUM(FMT_DXT5A, 59) + GENERATE_ENUM(FMT_CTX1, 60) +END_ENUMTYPE(SurfaceFormat) + +START_ENUMTYPE(SurfaceTiling) + GENERATE_ENUM(ARRAY_LINEAR, 0) + GENERATE_ENUM(ARRAY_TILED, 1) +END_ENUMTYPE(SurfaceTiling) + +START_ENUMTYPE(SurfaceArray) + GENERATE_ENUM(ARRAY_1D, 0) + GENERATE_ENUM(ARRAY_2D, 1) + GENERATE_ENUM(ARRAY_3D, 2) + GENERATE_ENUM(ARRAY_3D_SLICE, 3) +END_ENUMTYPE(SurfaceArray) + +START_ENUMTYPE(SurfaceNumberX) + GENERATE_ENUM(NUMBERX_UREPEAT, 0) + GENERATE_ENUM(NUMBERX_SREPEAT, 1) + GENERATE_ENUM(NUMBERX_UINTEGER, 2) + GENERATE_ENUM(NUMBERX_SINTEGER, 3) + GENERATE_ENUM(NUMBERX_FLOAT, 7) +END_ENUMTYPE(SurfaceNumberX) + +START_ENUMTYPE(ColorArrayX) + GENERATE_ENUM(ARRAYX_2D_COLOR, 0) + GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1) +END_ENUMTYPE(ColorArrayX) + + + + +// ************************************************************************** +// These are ones that had to be added in addition to what's generated +// by the autoreg (in CSIM) +// ************************************************************************** +START_ENUMTYPE(DXClipSpaceDef) + GENERATE_ENUM(DXCLIP_OPENGL, 0) + GENERATE_ENUM(DXCLIP_DIRECTX, 1) +END_ENUMTYPE(DXClipSpaceDef) + +START_ENUMTYPE(PixCenter) + GENERATE_ENUM(PIXCENTER_D3D, 0) + GENERATE_ENUM(PIXCENTER_OGL, 1) +END_ENUMTYPE(PixCenter) + +START_ENUMTYPE(RoundMode) + GENERATE_ENUM(TRUNCATE, 0) + GENERATE_ENUM(ROUND, 1) + GENERATE_ENUM(ROUNDTOEVEN, 2) + GENERATE_ENUM(ROUNDTOODD, 3) +END_ENUMTYPE(RoundMode) + +START_ENUMTYPE(QuantMode) + GENERATE_ENUM(ONE_SIXTEENTH, 0) + GENERATE_ENUM(ONE_EIGHTH, 1) + GENERATE_ENUM(ONE_QUARTER, 2) + GENERATE_ENUM(ONE_HALF, 3) + GENERATE_ENUM(ONE, 4) +END_ENUMTYPE(QuantMode) + +START_ENUMTYPE(FrontFace) + GENERATE_ENUM(FRONT_CCW, 0) + GENERATE_ENUM(FRONT_CW, 1) +END_ENUMTYPE(FrontFace) + +START_ENUMTYPE(PolyMode) + GENERATE_ENUM(DISABLED, 0) + GENERATE_ENUM(DUALMODE, 1) +END_ENUMTYPE(PolyMode) + +START_ENUMTYPE(PType) + GENERATE_ENUM(DRAW_POINTS, 0) + GENERATE_ENUM(DRAW_LINES, 1) + GENERATE_ENUM(DRAW_TRIANGLES, 2) +END_ENUMTYPE(PType) + +START_ENUMTYPE(MSAANumSamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 3) +END_ENUMTYPE(MSAANumSamples) + +START_ENUMTYPE(PatternBitOrder) + GENERATE_ENUM(LITTLE, 0) + GENERATE_ENUM(BIG, 1) +END_ENUMTYPE(PatternBitOrder) + +START_ENUMTYPE(AutoResetCntl) + GENERATE_ENUM(NEVER, 0) + GENERATE_ENUM(EACHPRIMITIVE, 1) + GENERATE_ENUM(EACHPACKET, 2) +END_ENUMTYPE(AutoResetCntl) + +START_ENUMTYPE(ParamShade) + GENERATE_ENUM(FLAT, 0) + GENERATE_ENUM(GOURAUD, 1) +END_ENUMTYPE(ParamShade) + +START_ENUMTYPE(SamplingPattern) + GENERATE_ENUM(CENTROID, 0) + GENERATE_ENUM(PIXCENTER, 1) +END_ENUMTYPE(SamplingPattern) + +START_ENUMTYPE(MSAASamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 2) +END_ENUMTYPE(MSAASamples) + +START_ENUMTYPE(CopySampleSelect) + GENERATE_ENUM(SAMPLE_0, 0) + GENERATE_ENUM(SAMPLE_1, 1) + GENERATE_ENUM(SAMPLE_2, 2) + GENERATE_ENUM(SAMPLE_3, 3) + GENERATE_ENUM(SAMPLE_01, 4) + GENERATE_ENUM(SAMPLE_23, 5) + GENERATE_ENUM(SAMPLE_0123, 6) +END_ENUMTYPE(CopySampleSelect) + + +#undef START_ENUMTYPE +#undef GENERATE_ENUM +#undef END_ENUMTYPE + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h new file mode 100644 index 000000000000..d04379887b78 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h @@ -0,0 +1,3405 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_REGISTER(PA_CL_VPORT_XSCALE) + GENERATE_FIELD(VPORT_XSCALE, float) +END_REGISTER(PA_CL_VPORT_XSCALE) + +START_REGISTER(PA_CL_VPORT_XOFFSET) + GENERATE_FIELD(VPORT_XOFFSET, float) +END_REGISTER(PA_CL_VPORT_XOFFSET) + +START_REGISTER(PA_CL_VPORT_YSCALE) + GENERATE_FIELD(VPORT_YSCALE, float) +END_REGISTER(PA_CL_VPORT_YSCALE) + +START_REGISTER(PA_CL_VPORT_YOFFSET) + GENERATE_FIELD(VPORT_YOFFSET, float) +END_REGISTER(PA_CL_VPORT_YOFFSET) + +START_REGISTER(PA_CL_VPORT_ZSCALE) + GENERATE_FIELD(VPORT_ZSCALE, float) +END_REGISTER(PA_CL_VPORT_ZSCALE) + +START_REGISTER(PA_CL_VPORT_ZOFFSET) + GENERATE_FIELD(VPORT_ZOFFSET, float) +END_REGISTER(PA_CL_VPORT_ZOFFSET) + +START_REGISTER(PA_CL_VTE_CNTL) + GENERATE_FIELD(VPORT_X_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool) + GENERATE_FIELD(VTX_XY_FMT, bool) + GENERATE_FIELD(VTX_Z_FMT, bool) + GENERATE_FIELD(VTX_W0_FMT, bool) + GENERATE_FIELD(PERFCOUNTER_REF, bool) +END_REGISTER(PA_CL_VTE_CNTL) + +START_REGISTER(PA_CL_CLIP_CNTL) + GENERATE_FIELD(CLIP_DISABLE, bool) + GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool) + GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef) + GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool) + GENERATE_FIELD(VTX_KILL_OR, bool) + GENERATE_FIELD(XY_NAN_RETAIN, bool) + GENERATE_FIELD(Z_NAN_RETAIN, bool) + GENERATE_FIELD(W_NAN_RETAIN, bool) +END_REGISTER(PA_CL_CLIP_CNTL) + +START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + +START_REGISTER(PA_CL_ENHANCE) + GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_CL_ENHANCE) + +START_REGISTER(PA_SC_ENHANCE) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_SC_ENHANCE) + +START_REGISTER(PA_SU_VTX_CNTL) + GENERATE_FIELD(PIX_CENTER, PixCenter) + GENERATE_FIELD(ROUND_MODE, RoundMode) + GENERATE_FIELD(QUANT_MODE, QuantMode) +END_REGISTER(PA_SU_VTX_CNTL) + +START_REGISTER(PA_SU_POINT_SIZE) + GENERATE_FIELD(HEIGHT, fixed12_4) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_POINT_SIZE) + +START_REGISTER(PA_SU_POINT_MINMAX) + GENERATE_FIELD(MIN_SIZE, fixed12_4) + GENERATE_FIELD(MAX_SIZE, fixed12_4) +END_REGISTER(PA_SU_POINT_MINMAX) + +START_REGISTER(PA_SU_LINE_CNTL) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_LINE_CNTL) + +START_REGISTER(PA_SU_FACE_DATA) + GENERATE_FIELD(BASE_ADDR, int) +END_REGISTER(PA_SU_FACE_DATA) + +START_REGISTER(PA_SU_SC_MODE_CNTL) + GENERATE_FIELD(CULL_FRONT, bool) + GENERATE_FIELD(CULL_BACK, bool) + GENERATE_FIELD(FACE, FrontFace) + GENERATE_FIELD(POLY_MODE, PolyMode) + GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType) + GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType) + GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool) + GENERATE_FIELD(MSAA_ENABLE, bool) + GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool) + GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool) + GENERATE_FIELD(PROVOKING_VTX_LAST, bool) + GENERATE_FIELD(PERSP_CORR_DIS, bool) + GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool) + GENERATE_FIELD(QUAD_ORDER_ENABLE, bool) + GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool) + GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool) + GENERATE_FIELD(CLAMPED_FACENESS, bool) + GENERATE_FIELD(ZERO_AREA_FACENESS, bool) + GENERATE_FIELD(FACE_KILL_ENABLE, bool) + GENERATE_FIELD(FACE_WRITE_ENABLE, bool) +END_REGISTER(PA_SU_SC_MODE_CNTL) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + +START_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT) +END_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_HI) + +START_REGISTER(PA_SU_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_HI) + +START_REGISTER(PA_SU_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_HI) + +START_REGISTER(PA_SU_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_HI) + +START_REGISTER(PA_SC_WINDOW_OFFSET) + GENERATE_FIELD(WINDOW_X_OFFSET, signedint15) + GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15) +END_REGISTER(PA_SC_WINDOW_OFFSET) + +START_REGISTER(PA_SC_AA_CONFIG) + GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples) + GENERATE_FIELD(MAX_SAMPLE_DIST, int) +END_REGISTER(PA_SC_AA_CONFIG) + +START_REGISTER(PA_SC_AA_MASK) + GENERATE_FIELD(AA_MASK, hex) +END_REGISTER(PA_SC_AA_MASK) + +START_REGISTER(PA_SC_LINE_STIPPLE) + GENERATE_FIELD(LINE_PATTERN, hex) + GENERATE_FIELD(REPEAT_COUNT, intMinusOne) + GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder) + GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl) +END_REGISTER(PA_SC_LINE_STIPPLE) + +START_REGISTER(PA_SC_LINE_CNTL) + GENERATE_FIELD(BRES_CNTL, int) + GENERATE_FIELD(USE_BRES_CNTL, bool) + GENERATE_FIELD(EXPAND_LINE_WIDTH, bool) + GENERATE_FIELD(LAST_PIXEL, bool) +END_REGISTER(PA_SC_LINE_CNTL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool) +END_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + +START_REGISTER(PA_SC_VIZ_QUERY) + GENERATE_FIELD(VIZ_QUERY_ENA, bool) + GENERATE_FIELD(VIZ_QUERY_ID, int) + GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool) +END_REGISTER(PA_SC_VIZ_QUERY) + +START_REGISTER(PA_SC_VIZ_QUERY_STATUS) + GENERATE_FIELD(STATUS_BITS, hex) +END_REGISTER(PA_SC_VIZ_QUERY_STATUS) + +START_REGISTER(PA_SC_LINE_STIPPLE_STATE) + GENERATE_FIELD(CURRENT_PTR, int) + GENERATE_FIELD(CURRENT_COUNT, int) +END_REGISTER(PA_SC_LINE_STIPPLE_STATE) + +START_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT) +END_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SC_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SC_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_HI) + +START_REGISTER(PA_CL_CNTL_STATUS) + GENERATE_FIELD(CL_BUSY, int) +END_REGISTER(PA_CL_CNTL_STATUS) + +START_REGISTER(PA_SU_CNTL_STATUS) + GENERATE_FIELD(SU_BUSY, int) +END_REGISTER(PA_SU_CNTL_STATUS) + +START_REGISTER(PA_SC_CNTL_STATUS) + GENERATE_FIELD(SC_BUSY, int) +END_REGISTER(PA_SC_CNTL_STATUS) + +START_REGISTER(PA_SU_DEBUG_CNTL) + GENERATE_FIELD(SU_DEBUG_INDX, int) +END_REGISTER(PA_SU_DEBUG_CNTL) + +START_REGISTER(PA_SU_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(PA_SU_DEBUG_DATA) + +START_REGISTER(PA_SC_DEBUG_CNTL) + GENERATE_FIELD(SC_DEBUG_INDX, int) +END_REGISTER(PA_SC_DEBUG_CNTL) + +START_REGISTER(PA_SC_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(PA_SC_DEBUG_DATA) + +START_REGISTER(GFX_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(GFX_COPY_STATE) + +START_REGISTER(VGT_DRAW_INITIATOR) + GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE) + GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT) + GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT) + GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE) + GENERATE_FIELD(NOT_EOP, bool) + GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX) + GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE) + GENERATE_FIELD(NUM_INDICES, uint) +END_REGISTER(VGT_DRAW_INITIATOR) + +START_REGISTER(VGT_EVENT_INITIATOR) + GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE) +END_REGISTER(VGT_EVENT_INITIATOR) + +START_REGISTER(VGT_DMA_BASE) + GENERATE_FIELD(BASE_ADDR, uint) +END_REGISTER(VGT_DMA_BASE) + +START_REGISTER(VGT_DMA_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) + GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE) +END_REGISTER(VGT_DMA_SIZE) + +START_REGISTER(VGT_BIN_BASE) + GENERATE_FIELD(BIN_BASE_ADDR, uint) +END_REGISTER(VGT_BIN_BASE) + +START_REGISTER(VGT_BIN_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) + GENERATE_FIELD(FACENESS_FETCH, int) + GENERATE_FIELD(FACENESS_RESET, int) +END_REGISTER(VGT_BIN_SIZE) + +START_REGISTER(VGT_CURRENT_BIN_ID_MIN) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MIN) + +START_REGISTER(VGT_CURRENT_BIN_ID_MAX) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MAX) + +START_REGISTER(VGT_IMMED_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_IMMED_DATA) + +START_REGISTER(VGT_MAX_VTX_INDX) + GENERATE_FIELD(MAX_INDX, int) +END_REGISTER(VGT_MAX_VTX_INDX) + +START_REGISTER(VGT_MIN_VTX_INDX) + GENERATE_FIELD(MIN_INDX, int) +END_REGISTER(VGT_MIN_VTX_INDX) + +START_REGISTER(VGT_INDX_OFFSET) + GENERATE_FIELD(INDX_OFFSET, int) +END_REGISTER(VGT_INDX_OFFSET) + +START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + GENERATE_FIELD(VTX_REUSE_DEPTH, int) +END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + +START_REGISTER(VGT_OUT_DEALLOC_CNTL) + GENERATE_FIELD(DEALLOC_DIST, int) +END_REGISTER(VGT_OUT_DEALLOC_CNTL) + +START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + GENERATE_FIELD(RESET_INDX, int) +END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + +START_REGISTER(VGT_ENHANCE) + GENERATE_FIELD(MISC, hex) +END_REGISTER(VGT_ENHANCE) + +START_REGISTER(VGT_VTX_VECT_EJECT_REG) + GENERATE_FIELD(PRIM_COUNT, int) +END_REGISTER(VGT_VTX_VECT_EJECT_REG) + +START_REGISTER(VGT_LAST_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) + GENERATE_FIELD(DST_STATE_ID, int) +END_REGISTER(VGT_LAST_COPY_STATE) + +START_REGISTER(VGT_DEBUG_CNTL) + GENERATE_FIELD(VGT_DEBUG_INDX, int) +END_REGISTER(VGT_DEBUG_CNTL) + +START_REGISTER(VGT_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_DEBUG_DATA) + +START_REGISTER(VGT_CNTL_STATUS) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(VGT_DMA_BUSY, int) + GENERATE_FIELD(VGT_DMA_REQ_BUSY, int) + GENERATE_FIELD(VGT_GRP_BUSY, int) + GENERATE_FIELD(VGT_VR_BUSY, int) + GENERATE_FIELD(VGT_BIN_BUSY, int) + GENERATE_FIELD(VGT_PT_BUSY, int) + GENERATE_FIELD(VGT_OUT_BUSY, int) + GENERATE_FIELD(VGT_OUT_INDX_BUSY, int) +END_REGISTER(VGT_CNTL_STATUS) + +START_REGISTER(VGT_CRC_SQ_DATA) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_DATA) + +START_REGISTER(VGT_CRC_SQ_CTRL) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_CTRL) + +START_REGISTER(VGT_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER0_SELECT) + +START_REGISTER(VGT_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER1_SELECT) + +START_REGISTER(VGT_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER2_SELECT) + +START_REGISTER(VGT_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER3_SELECT) + +START_REGISTER(VGT_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_LOW) + +START_REGISTER(VGT_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_LOW) + +START_REGISTER(VGT_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_LOW) + +START_REGISTER(VGT_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_LOW) + +START_REGISTER(VGT_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_HI) + +START_REGISTER(VGT_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_HI) + +START_REGISTER(VGT_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_HI) + +START_REGISTER(VGT_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_HI) + +START_REGISTER(TC_CNTL_STATUS) + GENERATE_FIELD(L2_INVALIDATE, int) + GENERATE_FIELD(TC_L2_HIT_MISS, int) + GENERATE_FIELD(TC_BUSY, int) +END_REGISTER(TC_CNTL_STATUS) + +START_REGISTER(TCR_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCR_CHICKEN) + +START_REGISTER(TCF_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCF_CHICKEN) + +START_REGISTER(TCM_CHICKEN) + GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int) + GENERATE_FIELD(ETC_COLOR_ENDIAN, int) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCM_CHICKEN) + +START_REGISTER(TCR_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER0_SELECT) + +START_REGISTER(TCR_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER1_SELECT) + +START_REGISTER(TCR_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER0_HI) + +START_REGISTER(TCR_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER1_HI) + +START_REGISTER(TCR_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER0_LOW) + +START_REGISTER(TCR_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER1_LOW) + +START_REGISTER(TP_TC_CLKGATE_CNTL) + GENERATE_FIELD(TP_BUSY_EXTEND, int) + GENERATE_FIELD(TC_BUSY_EXTEND, int) +END_REGISTER(TP_TC_CLKGATE_CNTL) + +START_REGISTER(TPC_CNTL_STATUS) + GENERATE_FIELD(TPC_INPUT_BUSY, int) + GENERATE_FIELD(TPC_TC_FIFO_BUSY, int) + GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int) + GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_BUSY, int) + GENERATE_FIELD(TPC_RR_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int) + GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_BUSY, int) + GENERATE_FIELD(TF_TW_RTS, int) + GENERATE_FIELD(TF_TW_STATE_RTS, int) + GENERATE_FIELD(TF_TW_RTR, int) + GENERATE_FIELD(TW_TA_RTS, int) + GENERATE_FIELD(TW_TA_TT_RTS, int) + GENERATE_FIELD(TW_TA_LAST_RTS, int) + GENERATE_FIELD(TW_TA_RTR, int) + GENERATE_FIELD(TA_TB_RTS, int) + GENERATE_FIELD(TA_TB_TT_RTS, int) + GENERATE_FIELD(TA_TB_RTR, int) + GENERATE_FIELD(TA_TF_RTS, int) + GENERATE_FIELD(TA_TF_TC_FIFO_REN, int) + GENERATE_FIELD(TP_SQ_DEC, int) + GENERATE_FIELD(TPC_BUSY, int) +END_REGISTER(TPC_CNTL_STATUS) + +START_REGISTER(TPC_DEBUG0) + GENERATE_FIELD(LOD_CNTL, int) + GENERATE_FIELD(IC_CTR, int) + GENERATE_FIELD(WALKER_CNTL, int) + GENERATE_FIELD(ALIGNER_CNTL, int) + GENERATE_FIELD(PREV_TC_STATE_VALID, int) + GENERATE_FIELD(WALKER_STATE, int) + GENERATE_FIELD(ALIGNER_STATE, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(TPC_CLK_EN, int) + GENERATE_FIELD(SQ_TP_WAKEUP, int) +END_REGISTER(TPC_DEBUG0) + +START_REGISTER(TPC_DEBUG1) + GENERATE_FIELD(UNUSED, int) +END_REGISTER(TPC_DEBUG1) + +START_REGISTER(TPC_CHICKEN) + GENERATE_FIELD(BLEND_PRECISION, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TPC_CHICKEN) + +START_REGISTER(TP0_CNTL_STATUS) + GENERATE_FIELD(TP_INPUT_BUSY, int) + GENERATE_FIELD(TP_LOD_BUSY, int) + GENERATE_FIELD(TP_LOD_FIFO_BUSY, int) + GENERATE_FIELD(TP_ADDR_BUSY, int) + GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TP_ALIGNER_BUSY, int) + GENERATE_FIELD(TP_TC_FIFO_BUSY, int) + GENERATE_FIELD(TP_RR_FIFO_BUSY, int) + GENERATE_FIELD(TP_FETCH_BUSY, int) + GENERATE_FIELD(TP_CH_BLEND_BUSY, int) + GENERATE_FIELD(TP_TT_BUSY, int) + GENERATE_FIELD(TP_HICOLOR_BUSY, int) + GENERATE_FIELD(TP_BLEND_BUSY, int) + GENERATE_FIELD(TP_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TP_OUTPUT_BUSY, int) + GENERATE_FIELD(IN_LC_RTS, int) + GENERATE_FIELD(LC_LA_RTS, int) + GENERATE_FIELD(LA_FL_RTS, int) + GENERATE_FIELD(FL_TA_RTS, int) + GENERATE_FIELD(TA_FA_RTS, int) + GENERATE_FIELD(TA_FA_TT_RTS, int) + GENERATE_FIELD(FA_AL_RTS, int) + GENERATE_FIELD(FA_AL_TT_RTS, int) + GENERATE_FIELD(AL_TF_RTS, int) + GENERATE_FIELD(AL_TF_TT_RTS, int) + GENERATE_FIELD(TF_TB_RTS, int) + GENERATE_FIELD(TF_TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_TT_RESET, int) + GENERATE_FIELD(TB_TO_RTS, int) + GENERATE_FIELD(TP_BUSY, int) +END_REGISTER(TP0_CNTL_STATUS) + +START_REGISTER(TP0_DEBUG) + GENERATE_FIELD(Q_LOD_CNTL, int) + GENERATE_FIELD(Q_SQ_TP_WAKEUP, int) + GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(PERF_CLK_EN, int) + GENERATE_FIELD(TP_CLK_EN, int) + GENERATE_FIELD(Q_WALKER_CNTL, int) + GENERATE_FIELD(Q_ALIGNER_CNTL, int) +END_REGISTER(TP0_DEBUG) + +START_REGISTER(TP0_CHICKEN) + GENERATE_FIELD(TT_MODE, int) + GENERATE_FIELD(VFETCH_ADDRESS_MODE, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TP0_CHICKEN) + +START_REGISTER(TP0_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT) +END_REGISTER(TP0_PERFCOUNTER0_SELECT) + +START_REGISTER(TP0_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER0_HI) + +START_REGISTER(TP0_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER0_LOW) + +START_REGISTER(TP0_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, int) +END_REGISTER(TP0_PERFCOUNTER1_SELECT) + +START_REGISTER(TP0_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER1_HI) + +START_REGISTER(TP0_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER1_LOW) + +START_REGISTER(TCM_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER0_SELECT) + +START_REGISTER(TCM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER1_SELECT) + +START_REGISTER(TCM_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER0_HI) + +START_REGISTER(TCM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER1_HI) + +START_REGISTER(TCM_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER0_LOW) + +START_REGISTER(TCM_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER0_SELECT) + +START_REGISTER(TCF_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER1_SELECT) + +START_REGISTER(TCF_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER2_SELECT) + +START_REGISTER(TCF_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER3_SELECT) + +START_REGISTER(TCF_PERFCOUNTER4_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER4_SELECT) + +START_REGISTER(TCF_PERFCOUNTER5_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER5_SELECT) + +START_REGISTER(TCF_PERFCOUNTER6_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER6_SELECT) + +START_REGISTER(TCF_PERFCOUNTER7_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER7_SELECT) + +START_REGISTER(TCF_PERFCOUNTER8_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER8_SELECT) + +START_REGISTER(TCF_PERFCOUNTER9_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER9_SELECT) + +START_REGISTER(TCF_PERFCOUNTER10_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER10_SELECT) + +START_REGISTER(TCF_PERFCOUNTER11_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER11_SELECT) + +START_REGISTER(TCF_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER0_HI) + +START_REGISTER(TCF_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER1_HI) + +START_REGISTER(TCF_PERFCOUNTER2_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER2_HI) + +START_REGISTER(TCF_PERFCOUNTER3_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER3_HI) + +START_REGISTER(TCF_PERFCOUNTER4_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER4_HI) + +START_REGISTER(TCF_PERFCOUNTER5_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER5_HI) + +START_REGISTER(TCF_PERFCOUNTER6_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER6_HI) + +START_REGISTER(TCF_PERFCOUNTER7_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER7_HI) + +START_REGISTER(TCF_PERFCOUNTER8_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER8_HI) + +START_REGISTER(TCF_PERFCOUNTER9_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER9_HI) + +START_REGISTER(TCF_PERFCOUNTER10_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER10_HI) + +START_REGISTER(TCF_PERFCOUNTER11_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER11_HI) + +START_REGISTER(TCF_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER0_LOW) + +START_REGISTER(TCF_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER2_LOW) + +START_REGISTER(TCF_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER3_LOW) + +START_REGISTER(TCF_PERFCOUNTER4_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER4_LOW) + +START_REGISTER(TCF_PERFCOUNTER5_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER5_LOW) + +START_REGISTER(TCF_PERFCOUNTER6_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER6_LOW) + +START_REGISTER(TCF_PERFCOUNTER7_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER7_LOW) + +START_REGISTER(TCF_PERFCOUNTER8_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER8_LOW) + +START_REGISTER(TCF_PERFCOUNTER9_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER9_LOW) + +START_REGISTER(TCF_PERFCOUNTER10_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER10_LOW) + +START_REGISTER(TCF_PERFCOUNTER11_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER11_LOW) + +START_REGISTER(TCF_DEBUG) + GENERATE_FIELD(not_MH_TC_rtr, int) + GENERATE_FIELD(TC_MH_send, int) + GENERATE_FIELD(not_FG0_rtr, int) + GENERATE_FIELD(not_TCB_TCO_rtr, int) + GENERATE_FIELD(TCB_ff_stall, int) + GENERATE_FIELD(TCB_miss_stall, int) + GENERATE_FIELD(TCA_TCB_stall, int) + GENERATE_FIELD(PF0_stall, int) + GENERATE_FIELD(TP0_full, int) + GENERATE_FIELD(TPC_full, int) + GENERATE_FIELD(not_TPC_rtr, int) + GENERATE_FIELD(tca_state_rts, int) + GENERATE_FIELD(tca_rts, int) +END_REGISTER(TCF_DEBUG) + +START_REGISTER(TCA_FIFO_DEBUG) + GENERATE_FIELD(tp0_full, int) + GENERATE_FIELD(tpc_full, int) + GENERATE_FIELD(load_tpc_fifo, int) + GENERATE_FIELD(load_tp_fifos, int) + GENERATE_FIELD(FW_full, int) + GENERATE_FIELD(not_FW_rtr0, int) + GENERATE_FIELD(FW_rts0, int) + GENERATE_FIELD(not_FW_tpc_rtr, int) + GENERATE_FIELD(FW_tpc_rts, int) +END_REGISTER(TCA_FIFO_DEBUG) + +START_REGISTER(TCA_PROBE_DEBUG) + GENERATE_FIELD(ProbeFilter_stall, int) +END_REGISTER(TCA_PROBE_DEBUG) + +START_REGISTER(TCA_TPC_DEBUG) + GENERATE_FIELD(captue_state_rts, int) + GENERATE_FIELD(capture_tca_rts, int) +END_REGISTER(TCA_TPC_DEBUG) + +START_REGISTER(TCB_CORE_DEBUG) + GENERATE_FIELD(access512, int) + GENERATE_FIELD(tiled, int) + GENERATE_FIELD(opcode, int) + GENERATE_FIELD(format, int) + GENERATE_FIELD(sector_format, int) + GENERATE_FIELD(sector_format512, int) +END_REGISTER(TCB_CORE_DEBUG) + +START_REGISTER(TCB_TAG0_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG0_DEBUG) + +START_REGISTER(TCB_TAG1_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG1_DEBUG) + +START_REGISTER(TCB_TAG2_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG2_DEBUG) + +START_REGISTER(TCB_TAG3_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG3_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + GENERATE_FIELD(left_done, int) + GENERATE_FIELD(fg0_sends_left, int) + GENERATE_FIELD(one_sector_to_go_left_q, int) + GENERATE_FIELD(no_sectors_to_go, int) + GENERATE_FIELD(update_left, int) + GENERATE_FIELD(sector_mask_left_count_q, int) + GENERATE_FIELD(sector_mask_left_q, int) + GENERATE_FIELD(valid_left_q, int) +END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + GENERATE_FIELD(quad_sel_left, int) + GENERATE_FIELD(set_sel_left, int) + GENERATE_FIELD(right_eq_left, int) + GENERATE_FIELD(ff_fg_type512, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(setquads_to_send, int) +END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + GENERATE_FIELD(tc0_arb_rts, int) + GENERATE_FIELD(ga_out_rts, int) + GENERATE_FIELD(tc_arb_format, int) + GENERATE_FIELD(tc_arb_fmsopcode, int) + GENERATE_FIELD(tc_arb_request_type, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(fgo_busy, int) + GENERATE_FIELD(ga_busy, int) + GENERATE_FIELD(mc_sel_q, int) + GENERATE_FIELD(valid_q, int) + GENERATE_FIELD(arb_RTR, int) +END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + +START_REGISTER(TCD_INPUT0_DEBUG) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(valid_q1, int) + GENERATE_FIELD(cnt_q1, int) + GENERATE_FIELD(last_send_q1, int) + GENERATE_FIELD(ip_send, int) + GENERATE_FIELD(ipbuf_dxt_send, int) + GENERATE_FIELD(ipbuf_busy, int) +END_REGISTER(TCD_INPUT0_DEBUG) + +START_REGISTER(TCD_DEGAMMA_DEBUG) + GENERATE_FIELD(dgmm_ftfconv_dgmmen, int) + GENERATE_FIELD(dgmm_ctrl_dgmm8, int) + GENERATE_FIELD(dgmm_ctrl_last_send, int) + GENERATE_FIELD(dgmm_ctrl_send, int) + GENERATE_FIELD(dgmm_stall, int) + GENERATE_FIELD(dgmm_pstate, int) +END_REGISTER(TCD_DEGAMMA_DEBUG) + +START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(sctrmx_rtr, int) + GENERATE_FIELD(dxtc_rtr, int) + GENERATE_FIELD(sctrarb_multcyl_send, int) + GENERATE_FIELD(sctrmx0_sctrarb_rts, int) + GENERATE_FIELD(dxtc_sctrarb_send, int) + GENERATE_FIELD(dxtc_dgmmpd_last_send, int) + GENERATE_FIELD(dxtc_dgmmpd_send, int) + GENERATE_FIELD(dcmp_mux_send, int) +END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + +START_REGISTER(TCD_DXTC_ARB_DEBUG) + GENERATE_FIELD(n0_stall, int) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(arb_dcmp01_last_send, int) + GENERATE_FIELD(arb_dcmp01_cnt, int) + GENERATE_FIELD(arb_dcmp01_sector, int) + GENERATE_FIELD(arb_dcmp01_cacheline, int) + GENERATE_FIELD(arb_dcmp01_format, int) + GENERATE_FIELD(arb_dcmp01_send, int) + GENERATE_FIELD(n0_dxt2_4_types, int) +END_REGISTER(TCD_DXTC_ARB_DEBUG) + +START_REGISTER(TCD_STALLS_DEBUG) + GENERATE_FIELD(not_multcyl_sctrarb_rtr, int) + GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int) + GENERATE_FIELD(not_dcmp0_arb_rtr, int) + GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int) + GENERATE_FIELD(not_mux_dcmp_rtr, int) + GENERATE_FIELD(not_incoming_rtr, int) +END_REGISTER(TCD_STALLS_DEBUG) + +START_REGISTER(TCO_STALLS_DEBUG) + GENERATE_FIELD(quad0_sg_crd_RTR, int) + GENERATE_FIELD(quad0_rl_sg_RTR, int) + GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int) +END_REGISTER(TCO_STALLS_DEBUG) + +START_REGISTER(TCO_QUAD0_DEBUG0) + GENERATE_FIELD(rl_sg_sector_format, int) + GENERATE_FIELD(rl_sg_end_of_sample, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_end_of_sample, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(stageN1_valid_q, int) + GENERATE_FIELD(read_cache_q, int) + GENERATE_FIELD(cache_read_RTR, int) + GENERATE_FIELD(all_sectors_written_set3, int) + GENERATE_FIELD(all_sectors_written_set2, int) + GENERATE_FIELD(all_sectors_written_set1, int) + GENERATE_FIELD(all_sectors_written_set0, int) + GENERATE_FIELD(busy, int) +END_REGISTER(TCO_QUAD0_DEBUG0) + +START_REGISTER(TCO_QUAD0_DEBUG1) + GENERATE_FIELD(fifo_busy, int) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(write_enable, int) + GENERATE_FIELD(fifo_write_ptr, int) + GENERATE_FIELD(fifo_read_ptr, int) + GENERATE_FIELD(cache_read_busy, int) + GENERATE_FIELD(latency_fifo_busy, int) + GENERATE_FIELD(input_quad_busy, int) + GENERATE_FIELD(tco_quad_pipe_busy, int) + GENERATE_FIELD(TCB_TCO_rtr_d, int) + GENERATE_FIELD(TCB_TCO_xfc_q, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(TCO_TCB_read_xfc, int) +END_REGISTER(TCO_QUAD0_DEBUG1) + +START_REGISTER(SQ_GPR_MANAGEMENT) + GENERATE_FIELD(REG_DYNAMIC, int) + GENERATE_FIELD(REG_SIZE_PIX, int) + GENERATE_FIELD(REG_SIZE_VTX, int) +END_REGISTER(SQ_GPR_MANAGEMENT) + +START_REGISTER(SQ_FLOW_CONTROL) + GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int) + GENERATE_FIELD(ONE_THREAD, int) + GENERATE_FIELD(ONE_ALU, int) + GENERATE_FIELD(CF_WR_BASE, hex) + GENERATE_FIELD(NO_PV_PS, int) + GENERATE_FIELD(NO_LOOP_EXIT, int) + GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int) + GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int) + GENERATE_FIELD(VC_ARBITRATION_POLICY, int) + GENERATE_FIELD(ALU_ARBITRATION_POLICY, int) + GENERATE_FIELD(NO_ARB_EJECT, int) + GENERATE_FIELD(NO_CFS_EJECT, int) + GENERATE_FIELD(POS_EXP_PRIORITY, int) + GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int) + GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int) +END_REGISTER(SQ_FLOW_CONTROL) + +START_REGISTER(SQ_INST_STORE_MANAGMENT) + GENERATE_FIELD(INST_BASE_PIX, int) + GENERATE_FIELD(INST_BASE_VTX, int) +END_REGISTER(SQ_INST_STORE_MANAGMENT) + +START_REGISTER(SQ_RESOURCE_MANAGMENT) + GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(EXPORT_BUF_ENTRIES, int) +END_REGISTER(SQ_RESOURCE_MANAGMENT) + +START_REGISTER(SQ_EO_RT) + GENERATE_FIELD(EO_CONSTANTS_RT, int) + GENERATE_FIELD(EO_TSTATE_RT, int) +END_REGISTER(SQ_EO_RT) + +START_REGISTER(SQ_DEBUG_MISC) + GENERATE_FIELD(DB_ALUCST_SIZE, int) + GENERATE_FIELD(DB_TSTATE_SIZE, int) + GENERATE_FIELD(DB_READ_CTX, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DB_READ_MEMORY, int) + GENERATE_FIELD(DB_WEN_MEMORY_0, int) + GENERATE_FIELD(DB_WEN_MEMORY_1, int) + GENERATE_FIELD(DB_WEN_MEMORY_2, int) + GENERATE_FIELD(DB_WEN_MEMORY_3, int) +END_REGISTER(SQ_DEBUG_MISC) + +START_REGISTER(SQ_ACTIVITY_METER_CNTL) + GENERATE_FIELD(TIMEBASE, int) + GENERATE_FIELD(THRESHOLD_LOW, int) + GENERATE_FIELD(THRESHOLD_HIGH, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(SQ_ACTIVITY_METER_CNTL) + +START_REGISTER(SQ_ACTIVITY_METER_STATUS) + GENERATE_FIELD(PERCENT_BUSY, int) +END_REGISTER(SQ_ACTIVITY_METER_STATUS) + +START_REGISTER(SQ_INPUT_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) +END_REGISTER(SQ_INPUT_ARB_PRIORITY) + +START_REGISTER(SQ_THREAD_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int) +END_REGISTER(SQ_THREAD_ARB_PRIORITY) + +START_REGISTER(SQ_VS_WATCHDOG_TIMER) + GENERATE_FIELD(ENABLE, int) + GENERATE_FIELD(TIMEOUT_COUNT, int) +END_REGISTER(SQ_VS_WATCHDOG_TIMER) + +START_REGISTER(SQ_PS_WATCHDOG_TIMER) + GENERATE_FIELD(ENABLE, int) + GENERATE_FIELD(TIMEOUT_COUNT, int) +END_REGISTER(SQ_PS_WATCHDOG_TIMER) + +START_REGISTER(SQ_INT_CNTL) + GENERATE_FIELD(PS_WATCHDOG_MASK, int) + GENERATE_FIELD(VS_WATCHDOG_MASK, int) +END_REGISTER(SQ_INT_CNTL) + +START_REGISTER(SQ_INT_STATUS) + GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int) + GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int) +END_REGISTER(SQ_INT_STATUS) + +START_REGISTER(SQ_INT_ACK) + GENERATE_FIELD(PS_WATCHDOG_ACK, int) + GENERATE_FIELD(VS_WATCHDOG_ACK, int) +END_REGISTER(SQ_INT_ACK) + +START_REGISTER(SQ_DEBUG_INPUT_FSM) + GENERATE_FIELD(VC_VSR_LD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VC_GPR_LD, int) + GENERATE_FIELD(PC_PISM, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PC_AS, int) + GENERATE_FIELD(PC_INTERP_CNT, int) + GENERATE_FIELD(PC_GPR_SIZE, int) +END_REGISTER(SQ_DEBUG_INPUT_FSM) + +START_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + GENERATE_FIELD(TEX_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(ALU_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(ALU_CONST_CNTX_VALID, int) + GENERATE_FIELD(TEX_CONST_CNTX_VALID, int) + GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int) +END_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + +START_REGISTER(SQ_DEBUG_TP_FSM) + GENERATE_FIELD(EX_TP, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_TP, int) + GENERATE_FIELD(IF_TP, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(TIS_TP, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(GS_TP, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(FCR_TP, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(FCS_TP, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_TP, int) +END_REGISTER(SQ_DEBUG_TP_FSM) + +START_REGISTER(SQ_DEBUG_FSM_ALU_0) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_0) + +START_REGISTER(SQ_DEBUG_FSM_ALU_1) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_1) + +START_REGISTER(SQ_DEBUG_EXP_ALLOC) + GENERATE_FIELD(POS_BUF_AVAIL, int) + GENERATE_FIELD(COLOR_BUF_AVAIL, int) + GENERATE_FIELD(EA_BUF_AVAIL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int) +END_REGISTER(SQ_DEBUG_EXP_ALLOC) + +START_REGISTER(SQ_DEBUG_PTR_BUFF) + GENERATE_FIELD(END_OF_BUFFER, int) + GENERATE_FIELD(DEALLOC_CNT, int) + GENERATE_FIELD(QUAL_NEW_VECTOR, int) + GENERATE_FIELD(EVENT_CONTEXT_ID, int) + GENERATE_FIELD(SC_EVENT_ID, int) + GENERATE_FIELD(QUAL_EVENT, int) + GENERATE_FIELD(PRIM_TYPE_POLYGON, int) + GENERATE_FIELD(EF_EMPTY, int) + GENERATE_FIELD(VTX_SYNC_CNT, int) +END_REGISTER(SQ_DEBUG_PTR_BUFF) + +START_REGISTER(SQ_DEBUG_GPR_VTX) + GENERATE_FIELD(VTX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VTX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(VTX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(VTX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_VTX) + +START_REGISTER(SQ_DEBUG_GPR_PIX) + GENERATE_FIELD(PIX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PIX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(PIX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_PIX) + +START_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int) + GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VC_THREAD_BUF_DLY, int) + GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int) +END_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + +START_REGISTER(SQ_DEBUG_VTX_TB_0) + GENERATE_FIELD(VTX_HEAD_PTR_Q, int) + GENERATE_FIELD(TAIL_PTR_Q, int) + GENERATE_FIELD(FULL_CNT_Q, int) + GENERATE_FIELD(NXT_POS_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PC_ALLOC_CNT, int) + GENERATE_FIELD(SX_EVENT_FULL, int) + GENERATE_FIELD(BUSY_Q, int) +END_REGISTER(SQ_DEBUG_VTX_TB_0) + +START_REGISTER(SQ_DEBUG_VTX_TB_1) + GENERATE_FIELD(VS_DONE_PTR, int) +END_REGISTER(SQ_DEBUG_VTX_TB_1) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + GENERATE_FIELD(VS_STATUS_REG, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + GENERATE_FIELD(VS_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + +START_REGISTER(SQ_DEBUG_PIX_TB_0) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(TAIL_PTR, int) + GENERATE_FIELD(FULL_CNT, int) + GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PIX_EXP_CNT, int) + GENERATE_FIELD(BUSY, int) +END_REGISTER(SQ_DEBUG_PIX_TB_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + GENERATE_FIELD(PIX_TB_STATUS_REG_0, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + GENERATE_FIELD(PIX_TB_STATUS_REG_1, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + GENERATE_FIELD(PIX_TB_STATUS_REG_2, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + GENERATE_FIELD(PIX_TB_STATUS_REG_3, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + GENERATE_FIELD(PIX_TB_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + +START_REGISTER(SQ_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT) +END_REGISTER(SQ_PERFCOUNTER0_SELECT) + +START_REGISTER(SQ_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER1_SELECT) + +START_REGISTER(SQ_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER2_SELECT) + +START_REGISTER(SQ_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER3_SELECT) + +START_REGISTER(SQ_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_LOW) + +START_REGISTER(SQ_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_HI) + +START_REGISTER(SQ_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_LOW) + +START_REGISTER(SQ_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_HI) + +START_REGISTER(SQ_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_LOW) + +START_REGISTER(SQ_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_HI) + +START_REGISTER(SQ_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_LOW) + +START_REGISTER(SQ_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_HI) + +START_REGISTER(SX_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT) +END_REGISTER(SX_PERFCOUNTER0_SELECT) + +START_REGISTER(SX_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_LOW) + +START_REGISTER(SX_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_HI) + +START_REGISTER(SQ_INSTRUCTION_ALU_0) + GENERATE_FIELD(VECTOR_RESULT, int) + GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier) + GENERATE_FIELD(LOW_PRECISION_16B_FP, int) + GENERATE_FIELD(SCALAR_RESULT, int) + GENERATE_FIELD(SCALAR_DST_REL, int) + GENERATE_FIELD(EXPORT_DATA, Exporting) + GENERATE_FIELD(VECTOR_WRT_MSK, int) + GENERATE_FIELD(SCALAR_WRT_MSK, int) + GENERATE_FIELD(VECTOR_CLAMP, int) + GENERATE_FIELD(SCALAR_CLAMP, int) + GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode) +END_REGISTER(SQ_INSTRUCTION_ALU_0) + +START_REGISTER(SQ_INSTRUCTION_ALU_1) + GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier) + GENERATE_FIELD(PRED_SELECT, PredicateSelect) + GENERATE_FIELD(RELATIVE_ADDR, int) + GENERATE_FIELD(CONST_1_REL_ABS, int) + GENERATE_FIELD(CONST_0_REL_ABS, int) +END_REGISTER(SQ_INSTRUCTION_ALU_1) + +START_REGISTER(SQ_INSTRUCTION_ALU_2) + GENERATE_FIELD(SRC_C_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_C, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier) + GENERATE_FIELD(SRC_B_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_B, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier) + GENERATE_FIELD(SRC_A_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_A, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier) + GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode) + GENERATE_FIELD(SRC_C_SEL, OperandSelect0) + GENERATE_FIELD(SRC_B_SEL, OperandSelect0) + GENERATE_FIELD(SRC_A_SEL, OperandSelect0) +END_REGISTER(SQ_INSTRUCTION_ALU_2) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(PREDICATED_JMP, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_2, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_0) + GENERATE_FIELD(OPCODE, TexInstOpcode) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, Addressmode) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, Addressmode) + GENERATE_FIELD(FETCH_VALID_ONLY, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm) + GENERATE_FIELD(SRC_SEL_X, SrcSel) + GENERATE_FIELD(SRC_SEL_Y, SrcSel) + GENERATE_FIELD(SRC_SEL_Z, SrcSel) +END_REGISTER(SQ_INSTRUCTION_TFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_1) + GENERATE_FIELD(DST_SEL_X, DstSel) + GENERATE_FIELD(DST_SEL_Y, DstSel) + GENERATE_FIELD(DST_SEL_Z, DstSel) + GENERATE_FIELD(DST_SEL_W, DstSel) + GENERATE_FIELD(MAG_FILTER, MagFilter) + GENERATE_FIELD(MIN_FILTER, MinFilter) + GENERATE_FIELD(MIP_FILTER, MipFilter) + GENERATE_FIELD(ANISO_FILTER, AnisoFilter) + GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter) + GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter) + GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter) + GENERATE_FIELD(USE_COMP_LOD, int) + GENERATE_FIELD(USE_REG_LOD, int) + GENERATE_FIELD(PRED_SELECT, PredSelect) +END_REGISTER(SQ_INSTRUCTION_TFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_2) + GENERATE_FIELD(USE_REG_GRADIENTS, int) + GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation) + GENERATE_FIELD(LOD_BIAS, int) + GENERATE_FIELD(UNUSED, int) + GENERATE_FIELD(OFFSET_X, int) + GENERATE_FIELD(OFFSET_Y, int) + GENERATE_FIELD(OFFSET_Z, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_TFETCH_2) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_0) + GENERATE_FIELD(OPCODE, int) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, int) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, int) + GENERATE_FIELD(MUST_BE_ONE, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(CONST_INDEX_SEL, int) + GENERATE_FIELD(SRC_SEL, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_1) + GENERATE_FIELD(DST_SEL_X, int) + GENERATE_FIELD(DST_SEL_Y, int) + GENERATE_FIELD(DST_SEL_Z, int) + GENERATE_FIELD(DST_SEL_W, int) + GENERATE_FIELD(FORMAT_COMP_ALL, int) + GENERATE_FIELD(NUM_FORMAT_ALL, int) + GENERATE_FIELD(SIGNED_RF_MODE_ALL, int) + GENERATE_FIELD(DATA_FORMAT, int) + GENERATE_FIELD(EXP_ADJUST_ALL, int) + GENERATE_FIELD(PRED_SELECT, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_2) + GENERATE_FIELD(STRIDE, int) + GENERATE_FIELD(OFFSET, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_2) + +START_REGISTER(SQ_CONSTANT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_0) + +START_REGISTER(SQ_CONSTANT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_1) + +START_REGISTER(SQ_CONSTANT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_2) + +START_REGISTER(SQ_CONSTANT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_3) + +START_REGISTER(SQ_FETCH_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_0) + +START_REGISTER(SQ_FETCH_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_1) + +START_REGISTER(SQ_FETCH_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_2) + +START_REGISTER(SQ_FETCH_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_3) + +START_REGISTER(SQ_FETCH_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_4) + +START_REGISTER(SQ_FETCH_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_5) + +START_REGISTER(SQ_CONSTANT_VFETCH_0) + GENERATE_FIELD(TYPE, int) + GENERATE_FIELD(STATE, int) + GENERATE_FIELD(BASE_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_0) + +START_REGISTER(SQ_CONSTANT_VFETCH_1) + GENERATE_FIELD(ENDIAN_SWAP, int) + GENERATE_FIELD(LIMIT_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_1) + +START_REGISTER(SQ_CONSTANT_T2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T2) + +START_REGISTER(SQ_CONSTANT_T3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T3) + +START_REGISTER(SQ_CF_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_BOOLEANS) + +START_REGISTER(SQ_CF_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_LOOP) + +START_REGISTER(SQ_CONSTANT_RT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_RT_0) + +START_REGISTER(SQ_CONSTANT_RT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_RT_1) + +START_REGISTER(SQ_CONSTANT_RT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_RT_2) + +START_REGISTER(SQ_CONSTANT_RT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_RT_3) + +START_REGISTER(SQ_FETCH_RT_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_0) + +START_REGISTER(SQ_FETCH_RT_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_1) + +START_REGISTER(SQ_FETCH_RT_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_2) + +START_REGISTER(SQ_FETCH_RT_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_3) + +START_REGISTER(SQ_FETCH_RT_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_4) + +START_REGISTER(SQ_FETCH_RT_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_5) + +START_REGISTER(SQ_CF_RT_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_RT_BOOLEANS) + +START_REGISTER(SQ_CF_RT_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_RT_LOOP) + +START_REGISTER(SQ_VS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_PROGRAM) + +START_REGISTER(SQ_PS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_PROGRAM) + +START_REGISTER(SQ_CF_PROGRAM_SIZE) + GENERATE_FIELD(VS_CF_SIZE, int) + GENERATE_FIELD(PS_CF_SIZE, int) +END_REGISTER(SQ_CF_PROGRAM_SIZE) + +START_REGISTER(SQ_INTERPOLATOR_CNTL) + GENERATE_FIELD(PARAM_SHADE, ParamShade) + GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern) +END_REGISTER(SQ_INTERPOLATOR_CNTL) + +START_REGISTER(SQ_PROGRAM_CNTL) + GENERATE_FIELD(VS_NUM_REG, intMinusOne) + GENERATE_FIELD(PS_NUM_REG, intMinusOne) + GENERATE_FIELD(VS_RESOURCE, int) + GENERATE_FIELD(PS_RESOURCE, int) + GENERATE_FIELD(PARAM_GEN, int) + GENERATE_FIELD(GEN_INDEX_PIX, int) + GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne) + GENERATE_FIELD(VS_EXPORT_MODE, VertexMode) + GENERATE_FIELD(PS_EXPORT_MODE, int) + GENERATE_FIELD(GEN_INDEX_VTX, int) +END_REGISTER(SQ_PROGRAM_CNTL) + +START_REGISTER(SQ_WRAPPING_0) + GENERATE_FIELD(PARAM_WRAP_0, hex) + GENERATE_FIELD(PARAM_WRAP_1, hex) + GENERATE_FIELD(PARAM_WRAP_2, hex) + GENERATE_FIELD(PARAM_WRAP_3, hex) + GENERATE_FIELD(PARAM_WRAP_4, hex) + GENERATE_FIELD(PARAM_WRAP_5, hex) + GENERATE_FIELD(PARAM_WRAP_6, hex) + GENERATE_FIELD(PARAM_WRAP_7, hex) +END_REGISTER(SQ_WRAPPING_0) + +START_REGISTER(SQ_WRAPPING_1) + GENERATE_FIELD(PARAM_WRAP_8, hex) + GENERATE_FIELD(PARAM_WRAP_9, hex) + GENERATE_FIELD(PARAM_WRAP_10, hex) + GENERATE_FIELD(PARAM_WRAP_11, hex) + GENERATE_FIELD(PARAM_WRAP_12, hex) + GENERATE_FIELD(PARAM_WRAP_13, hex) + GENERATE_FIELD(PARAM_WRAP_14, hex) + GENERATE_FIELD(PARAM_WRAP_15, hex) +END_REGISTER(SQ_WRAPPING_1) + +START_REGISTER(SQ_VS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_CONST) + +START_REGISTER(SQ_PS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_CONST) + +START_REGISTER(SQ_CONTEXT_MISC) + GENERATE_FIELD(INST_PRED_OPTIMIZE, int) + GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int) + GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl) + GENERATE_FIELD(PARAM_GEN_POS, int) + GENERATE_FIELD(PERFCOUNTER_REF, int) + GENERATE_FIELD(YEILD_OPTIMIZE, int) + GENERATE_FIELD(TX_CACHE_SEL, int) +END_REGISTER(SQ_CONTEXT_MISC) + +START_REGISTER(SQ_CF_RD_BASE) + GENERATE_FIELD(RD_BASE, hex) +END_REGISTER(SQ_CF_RD_BASE) + +START_REGISTER(SQ_DEBUG_MISC_0) + GENERATE_FIELD(DB_PROB_ON, int) + GENERATE_FIELD(DB_PROB_BREAK, int) + GENERATE_FIELD(DB_PROB_ADDR, int) + GENERATE_FIELD(DB_PROB_COUNT, int) +END_REGISTER(SQ_DEBUG_MISC_0) + +START_REGISTER(SQ_DEBUG_MISC_1) + GENERATE_FIELD(DB_ON_PIX, int) + GENERATE_FIELD(DB_ON_VTX, int) + GENERATE_FIELD(DB_INST_COUNT, int) + GENERATE_FIELD(DB_BREAK_ADDR, int) +END_REGISTER(SQ_DEBUG_MISC_1) + +START_REGISTER(MH_ARBITER_CONFIG) + GENERATE_FIELD(SAME_PAGE_LIMIT, int) + GENERATE_FIELD(SAME_PAGE_GRANULARITY, int) + GENERATE_FIELD(L1_ARB_ENABLE, bool) + GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int) + GENERATE_FIELD(L2_ARB_CONTROL, int) + GENERATE_FIELD(PAGE_SIZE, int) + GENERATE_FIELD(TC_REORDER_ENABLE, bool) + GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT, int) + GENERATE_FIELD(CP_CLNT_ENABLE, bool) + GENERATE_FIELD(VGT_CLNT_ENABLE, bool) + GENERATE_FIELD(TC_CLNT_ENABLE, bool) + GENERATE_FIELD(RB_CLNT_ENABLE, bool) + GENERATE_FIELD(PA_CLNT_ENABLE, bool) +END_REGISTER(MH_ARBITER_CONFIG) + +START_REGISTER(MH_CLNT_AXI_ID_REUSE) + GENERATE_FIELD(CPw_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RBw_ID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(MMUr_ID, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(PAw_ID, int) +END_REGISTER(MH_CLNT_AXI_ID_REUSE) + +START_REGISTER(MH_INTERRUPT_MASK) + GENERATE_FIELD(AXI_READ_ERROR, bool) + GENERATE_FIELD(AXI_WRITE_ERROR, bool) + GENERATE_FIELD(MMU_PAGE_FAULT, bool) +END_REGISTER(MH_INTERRUPT_MASK) + +START_REGISTER(MH_INTERRUPT_STATUS) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_STATUS) + +START_REGISTER(MH_INTERRUPT_CLEAR) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_CLEAR) + +START_REGISTER(MH_AXI_ERROR) + GENERATE_FIELD(AXI_READ_ID, int) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ID, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) +END_REGISTER(MH_AXI_ERROR) + +START_REGISTER(MH_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER0_SELECT) + +START_REGISTER(MH_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER1_SELECT) + +START_REGISTER(MH_PERFCOUNTER0_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER0_CONFIG) + +START_REGISTER(MH_PERFCOUNTER1_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER1_CONFIG) + +START_REGISTER(MH_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER0_LOW) + +START_REGISTER(MH_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER1_LOW) + +START_REGISTER(MH_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER0_HI) + +START_REGISTER(MH_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER1_HI) + +START_REGISTER(MH_DEBUG_CTRL) + GENERATE_FIELD(INDEX, int) +END_REGISTER(MH_DEBUG_CTRL) + +START_REGISTER(MH_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(MH_DEBUG_DATA) + +START_REGISTER(MH_AXI_HALT_CONTROL) + GENERATE_FIELD(AXI_HALT, bool) +END_REGISTER(MH_AXI_HALT_CONTROL) + +START_REGISTER(MH_MMU_CONFIG) + GENERATE_FIELD(MMU_ENABLE, bool) + GENERATE_FIELD(SPLIT_MODE_ENABLE, bool) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh) +END_REGISTER(MH_MMU_CONFIG) + +START_REGISTER(MH_MMU_VA_RANGE) + GENERATE_FIELD(NUM_64KB_REGIONS, int) + GENERATE_FIELD(VA_BASE, int) +END_REGISTER(MH_MMU_VA_RANGE) + +START_REGISTER(MH_MMU_PT_BASE) + GENERATE_FIELD(PT_BASE, int) +END_REGISTER(MH_MMU_PT_BASE) + +START_REGISTER(MH_MMU_PAGE_FAULT) + GENERATE_FIELD(PAGE_FAULT, int) + GENERATE_FIELD(OP_TYPE, int) + GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(AXI_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(READ_PROTECTION_ERROR, int) + GENERATE_FIELD(WRITE_PROTECTION_ERROR, int) + GENERATE_FIELD(REQ_VA, int) +END_REGISTER(MH_MMU_PAGE_FAULT) + +START_REGISTER(MH_MMU_TRAN_ERROR) + GENERATE_FIELD(TRAN_ERROR, int) +END_REGISTER(MH_MMU_TRAN_ERROR) + +START_REGISTER(MH_MMU_INVALIDATE) + GENERATE_FIELD(INVALIDATE_ALL, int) + GENERATE_FIELD(INVALIDATE_TC, int) +END_REGISTER(MH_MMU_INVALIDATE) + +START_REGISTER(MH_MMU_MPU_BASE) + GENERATE_FIELD(MPU_BASE, int) +END_REGISTER(MH_MMU_MPU_BASE) + +START_REGISTER(MH_MMU_MPU_END) + GENERATE_FIELD(MPU_END, int) +END_REGISTER(MH_MMU_MPU_END) + +START_REGISTER(WAIT_UNTIL) + GENERATE_FIELD(WAIT_RE_VSYNC, int) + GENERATE_FIELD(WAIT_FE_VSYNC, int) + GENERATE_FIELD(WAIT_VSYNC, int) + GENERATE_FIELD(WAIT_DSPLY_ID0, int) + GENERATE_FIELD(WAIT_DSPLY_ID1, int) + GENERATE_FIELD(WAIT_DSPLY_ID2, int) + GENERATE_FIELD(WAIT_CMDFIFO, int) + GENERATE_FIELD(WAIT_2D_IDLE, int) + GENERATE_FIELD(WAIT_3D_IDLE, int) + GENERATE_FIELD(WAIT_2D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_3D_IDLECLEAN, int) + GENERATE_FIELD(CMDFIFO_ENTRIES, int) +END_REGISTER(WAIT_UNTIL) + +START_REGISTER(RBBM_ISYNC_CNTL) + GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int) + GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int) +END_REGISTER(RBBM_ISYNC_CNTL) + +START_REGISTER(RBBM_STATUS) + GENERATE_FIELD(CMDFIFO_AVAIL, int) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(HIRQ_PENDING, int) + GENERATE_FIELD(CPRQ_PENDING, int) + GENERATE_FIELD(CFRQ_PENDING, int) + GENERATE_FIELD(PFRQ_PENDING, int) + GENERATE_FIELD(VGT_BUSY_NO_DMA, int) + GENERATE_FIELD(RBBM_WU_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(MH_BUSY, int) + GENERATE_FIELD(MH_COHERENCY_BUSY, int) + GENERATE_FIELD(SX_BUSY, int) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(SC_CNTX_BUSY, int) + GENERATE_FIELD(PA_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(SQ_CNTX17_BUSY, int) + GENERATE_FIELD(SQ_CNTX0_BUSY, int) + GENERATE_FIELD(RB_CNTX_BUSY, int) + GENERATE_FIELD(GUI_ACTIVE, int) +END_REGISTER(RBBM_STATUS) + +START_REGISTER(RBBM_DSPLY) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int) + GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH1_SW_CNTL, int) + GENERATE_FIELD(DMI_CH1_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH2_SW_CNTL, int) + GENERATE_FIELD(DMI_CH2_NUM_BUFS, int) + GENERATE_FIELD(DMI_CHANNEL_SELECT, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH3_SW_CNTL, int) + GENERATE_FIELD(DMI_CH3_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH4_SW_CNTL, int) + GENERATE_FIELD(DMI_CH4_NUM_BUFS, int) +END_REGISTER(RBBM_DSPLY) + +START_REGISTER(RBBM_RENDER_LATEST) + GENERATE_FIELD(DMI_CH1_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH2_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH3_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH4_BUFFER_ID, int) +END_REGISTER(RBBM_RENDER_LATEST) + +START_REGISTER(RBBM_RTL_RELEASE) + GENERATE_FIELD(CHANGELIST, int) +END_REGISTER(RBBM_RTL_RELEASE) + +START_REGISTER(RBBM_PATCH_RELEASE) + GENERATE_FIELD(PATCH_REVISION, int) + GENERATE_FIELD(PATCH_SELECTION, int) + GENERATE_FIELD(CUSTOMER_ID, int) +END_REGISTER(RBBM_PATCH_RELEASE) + +START_REGISTER(RBBM_AUXILIARY_CONFIG) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(RBBM_AUXILIARY_CONFIG) + +START_REGISTER(RBBM_PERIPHID0) + GENERATE_FIELD(PARTNUMBER0, int) +END_REGISTER(RBBM_PERIPHID0) + +START_REGISTER(RBBM_PERIPHID1) + GENERATE_FIELD(PARTNUMBER1, int) + GENERATE_FIELD(DESIGNER0, int) +END_REGISTER(RBBM_PERIPHID1) + +START_REGISTER(RBBM_PERIPHID2) + GENERATE_FIELD(DESIGNER1, int) + GENERATE_FIELD(REVISION, int) +END_REGISTER(RBBM_PERIPHID2) + +START_REGISTER(RBBM_PERIPHID3) + GENERATE_FIELD(RBBM_HOST_INTERFACE, int) + GENERATE_FIELD(GARB_SLAVE_INTERFACE, int) + GENERATE_FIELD(MH_INTERFACE, int) + GENERATE_FIELD(CONTINUATION, int) +END_REGISTER(RBBM_PERIPHID3) + +START_REGISTER(RBBM_CNTL) + GENERATE_FIELD(READ_TIMEOUT, int) + GENERATE_FIELD(REGCLK_DEASSERT_TIME, int) +END_REGISTER(RBBM_CNTL) + +START_REGISTER(RBBM_SKEW_CNTL) + GENERATE_FIELD(SKEW_TOP_THRESHOLD, int) + GENERATE_FIELD(SKEW_COUNT, int) +END_REGISTER(RBBM_SKEW_CNTL) + +START_REGISTER(RBBM_SOFT_RESET) + GENERATE_FIELD(SOFT_RESET_CP, int) + GENERATE_FIELD(SOFT_RESET_PA, int) + GENERATE_FIELD(SOFT_RESET_MH, int) + GENERATE_FIELD(SOFT_RESET_BC, int) + GENERATE_FIELD(SOFT_RESET_SQ, int) + GENERATE_FIELD(SOFT_RESET_SX, int) + GENERATE_FIELD(SOFT_RESET_CIB, int) + GENERATE_FIELD(SOFT_RESET_SC, int) + GENERATE_FIELD(SOFT_RESET_VGT, int) +END_REGISTER(RBBM_SOFT_RESET) + +START_REGISTER(RBBM_PM_OVERRIDE1) + GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE1) + +START_REGISTER(RBBM_PM_OVERRIDE2) + GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE2) + +START_REGISTER(GC_SYS_IDLE) + GENERATE_FIELD(GC_SYS_IDLE_DELAY, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int) +END_REGISTER(GC_SYS_IDLE) + +START_REGISTER(NQWAIT_UNTIL) + GENERATE_FIELD(WAIT_GUI_IDLE, int) +END_REGISTER(NQWAIT_UNTIL) + +START_REGISTER(RBBM_DEBUG_OUT) + GENERATE_FIELD(DEBUG_BUS_OUT, int) +END_REGISTER(RBBM_DEBUG_OUT) + +START_REGISTER(RBBM_DEBUG_CNTL) + GENERATE_FIELD(SUB_BLOCK_ADDR, int) + GENERATE_FIELD(SUB_BLOCK_SEL, int) + GENERATE_FIELD(SW_ENABLE, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int) + GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int) +END_REGISTER(RBBM_DEBUG_CNTL) + +START_REGISTER(RBBM_DEBUG) + GENERATE_FIELD(IGNORE_RTR, int) + GENERATE_FIELD(IGNORE_CP_SCHED_WU, int) + GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int) + GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int) + GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int) + GENERATE_FIELD(IGNORE_RTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(CP_RBBM_NRTRTR, int) + GENERATE_FIELD(VGT_RBBM_NRTRTR, int) + GENERATE_FIELD(SQ_RBBM_NRTRTR, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int) + GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int) +END_REGISTER(RBBM_DEBUG) + +START_REGISTER(RBBM_READ_ERROR) + GENERATE_FIELD(READ_ADDRESS, int) + GENERATE_FIELD(READ_REQUESTER, int) + GENERATE_FIELD(READ_ERROR, int) +END_REGISTER(RBBM_READ_ERROR) + +START_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int) +END_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + +START_REGISTER(RBBM_INT_CNTL) + GENERATE_FIELD(RDERR_INT_MASK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int) + GENERATE_FIELD(GUI_IDLE_INT_MASK, int) +END_REGISTER(RBBM_INT_CNTL) + +START_REGISTER(RBBM_INT_STATUS) + GENERATE_FIELD(RDERR_INT_STAT, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int) + GENERATE_FIELD(GUI_IDLE_INT_STAT, int) +END_REGISTER(RBBM_INT_STATUS) + +START_REGISTER(RBBM_INT_ACK) + GENERATE_FIELD(RDERR_INT_ACK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int) + GENERATE_FIELD(GUI_IDLE_INT_ACK, int) +END_REGISTER(RBBM_INT_ACK) + +START_REGISTER(MASTER_INT_SIGNAL) + GENERATE_FIELD(MH_INT_STAT, int) + GENERATE_FIELD(SQ_INT_STAT, int) + GENERATE_FIELD(CP_INT_STAT, int) + GENERATE_FIELD(RBBM_INT_STAT, int) +END_REGISTER(MASTER_INT_SIGNAL) + +START_REGISTER(RBBM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL) +END_REGISTER(RBBM_PERFCOUNTER1_SELECT) + +START_REGISTER(RBBM_PERFCOUNTER1_LO) + GENERATE_FIELD(PERF_COUNT1_LO, int) +END_REGISTER(RBBM_PERFCOUNTER1_LO) + +START_REGISTER(RBBM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT1_HI, int) +END_REGISTER(RBBM_PERFCOUNTER1_HI) + +START_REGISTER(CP_RB_BASE) + GENERATE_FIELD(RB_BASE, int) +END_REGISTER(CP_RB_BASE) + +START_REGISTER(CP_RB_CNTL) + GENERATE_FIELD(RB_BUFSZ, int) + GENERATE_FIELD(RB_BLKSZ, int) + GENERATE_FIELD(BUF_SWAP, int) + GENERATE_FIELD(RB_POLL_EN, int) + GENERATE_FIELD(RB_NO_UPDATE, int) + GENERATE_FIELD(RB_RPTR_WR_ENA, int) +END_REGISTER(CP_RB_CNTL) + +START_REGISTER(CP_RB_RPTR_ADDR) + GENERATE_FIELD(RB_RPTR_SWAP, int) + GENERATE_FIELD(RB_RPTR_ADDR, int) +END_REGISTER(CP_RB_RPTR_ADDR) + +START_REGISTER(CP_RB_RPTR) + GENERATE_FIELD(RB_RPTR, int) +END_REGISTER(CP_RB_RPTR) + +START_REGISTER(CP_RB_RPTR_WR) + GENERATE_FIELD(RB_RPTR_WR, int) +END_REGISTER(CP_RB_RPTR_WR) + +START_REGISTER(CP_RB_WPTR) + GENERATE_FIELD(RB_WPTR, int) +END_REGISTER(CP_RB_WPTR) + +START_REGISTER(CP_RB_WPTR_DELAY) + GENERATE_FIELD(PRE_WRITE_TIMER, int) + GENERATE_FIELD(PRE_WRITE_LIMIT, int) +END_REGISTER(CP_RB_WPTR_DELAY) + +START_REGISTER(CP_RB_WPTR_BASE) + GENERATE_FIELD(RB_WPTR_SWAP, int) + GENERATE_FIELD(RB_WPTR_BASE, int) +END_REGISTER(CP_RB_WPTR_BASE) + +START_REGISTER(CP_IB1_BASE) + GENERATE_FIELD(IB1_BASE, int) +END_REGISTER(CP_IB1_BASE) + +START_REGISTER(CP_IB1_BUFSZ) + GENERATE_FIELD(IB1_BUFSZ, int) +END_REGISTER(CP_IB1_BUFSZ) + +START_REGISTER(CP_IB2_BASE) + GENERATE_FIELD(IB2_BASE, int) +END_REGISTER(CP_IB2_BASE) + +START_REGISTER(CP_IB2_BUFSZ) + GENERATE_FIELD(IB2_BUFSZ, int) +END_REGISTER(CP_IB2_BUFSZ) + +START_REGISTER(CP_ST_BASE) + GENERATE_FIELD(ST_BASE, int) +END_REGISTER(CP_ST_BASE) + +START_REGISTER(CP_ST_BUFSZ) + GENERATE_FIELD(ST_BUFSZ, int) +END_REGISTER(CP_ST_BUFSZ) + +START_REGISTER(CP_QUEUE_THRESHOLDS) + GENERATE_FIELD(CSQ_IB1_START, int) + GENERATE_FIELD(CSQ_IB2_START, int) + GENERATE_FIELD(CSQ_ST_START, int) +END_REGISTER(CP_QUEUE_THRESHOLDS) + +START_REGISTER(CP_MEQ_THRESHOLDS) + GENERATE_FIELD(MEQ_END, int) + GENERATE_FIELD(ROQ_END, int) +END_REGISTER(CP_MEQ_THRESHOLDS) + +START_REGISTER(CP_CSQ_AVAIL) + GENERATE_FIELD(CSQ_CNT_RING, int) + GENERATE_FIELD(CSQ_CNT_IB1, int) + GENERATE_FIELD(CSQ_CNT_IB2, int) +END_REGISTER(CP_CSQ_AVAIL) + +START_REGISTER(CP_STQ_AVAIL) + GENERATE_FIELD(STQ_CNT_ST, int) +END_REGISTER(CP_STQ_AVAIL) + +START_REGISTER(CP_MEQ_AVAIL) + GENERATE_FIELD(MEQ_CNT, int) +END_REGISTER(CP_MEQ_AVAIL) + +START_REGISTER(CP_CSQ_RB_STAT) + GENERATE_FIELD(CSQ_RPTR_PRIMARY, int) + GENERATE_FIELD(CSQ_WPTR_PRIMARY, int) +END_REGISTER(CP_CSQ_RB_STAT) + +START_REGISTER(CP_CSQ_IB1_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int) +END_REGISTER(CP_CSQ_IB1_STAT) + +START_REGISTER(CP_CSQ_IB2_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int) +END_REGISTER(CP_CSQ_IB2_STAT) + +START_REGISTER(CP_NON_PREFETCH_CNTRS) + GENERATE_FIELD(IB1_COUNTER, int) + GENERATE_FIELD(IB2_COUNTER, int) +END_REGISTER(CP_NON_PREFETCH_CNTRS) + +START_REGISTER(CP_STQ_ST_STAT) + GENERATE_FIELD(STQ_RPTR_ST, int) + GENERATE_FIELD(STQ_WPTR_ST, int) +END_REGISTER(CP_STQ_ST_STAT) + +START_REGISTER(CP_MEQ_STAT) + GENERATE_FIELD(MEQ_RPTR, int) + GENERATE_FIELD(MEQ_WPTR, int) +END_REGISTER(CP_MEQ_STAT) + +START_REGISTER(CP_MIU_TAG_STAT) + GENERATE_FIELD(TAG_0_STAT, int) + GENERATE_FIELD(TAG_1_STAT, int) + GENERATE_FIELD(TAG_2_STAT, int) + GENERATE_FIELD(TAG_3_STAT, int) + GENERATE_FIELD(TAG_4_STAT, int) + GENERATE_FIELD(TAG_5_STAT, int) + GENERATE_FIELD(TAG_6_STAT, int) + GENERATE_FIELD(TAG_7_STAT, int) + GENERATE_FIELD(TAG_8_STAT, int) + GENERATE_FIELD(TAG_9_STAT, int) + GENERATE_FIELD(TAG_10_STAT, int) + GENERATE_FIELD(TAG_11_STAT, int) + GENERATE_FIELD(TAG_12_STAT, int) + GENERATE_FIELD(TAG_13_STAT, int) + GENERATE_FIELD(TAG_14_STAT, int) + GENERATE_FIELD(TAG_15_STAT, int) + GENERATE_FIELD(TAG_16_STAT, int) + GENERATE_FIELD(TAG_17_STAT, int) + GENERATE_FIELD(INVALID_RETURN_TAG, int) +END_REGISTER(CP_MIU_TAG_STAT) + +START_REGISTER(CP_CMD_INDEX) + GENERATE_FIELD(CMD_INDEX, int) + GENERATE_FIELD(CMD_QUEUE_SEL, int) +END_REGISTER(CP_CMD_INDEX) + +START_REGISTER(CP_CMD_DATA) + GENERATE_FIELD(CMD_DATA, int) +END_REGISTER(CP_CMD_DATA) + +START_REGISTER(CP_ME_CNTL) + GENERATE_FIELD(ME_STATMUX, int) + GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(ME_HALT, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(PROG_CNT_SIZE, int) +END_REGISTER(CP_ME_CNTL) + +START_REGISTER(CP_ME_STATUS) + GENERATE_FIELD(ME_DEBUG_DATA, int) +END_REGISTER(CP_ME_STATUS) + +START_REGISTER(CP_ME_RAM_WADDR) + GENERATE_FIELD(ME_RAM_WADDR, int) +END_REGISTER(CP_ME_RAM_WADDR) + +START_REGISTER(CP_ME_RAM_RADDR) + GENERATE_FIELD(ME_RAM_RADDR, int) +END_REGISTER(CP_ME_RAM_RADDR) + +START_REGISTER(CP_ME_RAM_DATA) + GENERATE_FIELD(ME_RAM_DATA, int) +END_REGISTER(CP_ME_RAM_DATA) + +START_REGISTER(CP_ME_RDADDR) + GENERATE_FIELD(ME_RDADDR, int) +END_REGISTER(CP_ME_RDADDR) + +START_REGISTER(CP_DEBUG) + GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int) + GENERATE_FIELD(PREDICATE_DISABLE, int) + GENERATE_FIELD(PROG_END_PTR_ENABLE, int) + GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int) + GENERATE_FIELD(PREFETCH_PASS_NOPS, int) + GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int) + GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int) + GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int) + GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int) +END_REGISTER(CP_DEBUG) + +START_REGISTER(SCRATCH_REG0) + GENERATE_FIELD(SCRATCH_REG0, int) +END_REGISTER(SCRATCH_REG0) + +START_REGISTER(SCRATCH_REG1) + GENERATE_FIELD(SCRATCH_REG1, int) +END_REGISTER(SCRATCH_REG1) + +START_REGISTER(SCRATCH_REG2) + GENERATE_FIELD(SCRATCH_REG2, int) +END_REGISTER(SCRATCH_REG2) + +START_REGISTER(SCRATCH_REG3) + GENERATE_FIELD(SCRATCH_REG3, int) +END_REGISTER(SCRATCH_REG3) + +START_REGISTER(SCRATCH_REG4) + GENERATE_FIELD(SCRATCH_REG4, int) +END_REGISTER(SCRATCH_REG4) + +START_REGISTER(SCRATCH_REG5) + GENERATE_FIELD(SCRATCH_REG5, int) +END_REGISTER(SCRATCH_REG5) + +START_REGISTER(SCRATCH_REG6) + GENERATE_FIELD(SCRATCH_REG6, int) +END_REGISTER(SCRATCH_REG6) + +START_REGISTER(SCRATCH_REG7) + GENERATE_FIELD(SCRATCH_REG7, int) +END_REGISTER(SCRATCH_REG7) + +START_REGISTER(SCRATCH_UMSK) + GENERATE_FIELD(SCRATCH_UMSK, int) + GENERATE_FIELD(SCRATCH_SWAP, int) +END_REGISTER(SCRATCH_UMSK) + +START_REGISTER(SCRATCH_ADDR) + GENERATE_FIELD(SCRATCH_ADDR, hex) +END_REGISTER(SCRATCH_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_SRC) + GENERATE_FIELD(VS_DONE_SWM, int) + GENERATE_FIELD(VS_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_EVENT_SRC) + +START_REGISTER(CP_ME_VS_EVENT_ADDR) + GENERATE_FIELD(VS_DONE_SWAP, int) + GENERATE_FIELD(VS_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_DATA) + GENERATE_FIELD(VS_DONE_DATA, int) +END_REGISTER(CP_ME_VS_EVENT_DATA) + +START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + GENERATE_FIELD(VS_DONE_SWAP_SWM, int) + GENERATE_FIELD(VS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + GENERATE_FIELD(VS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_PS_EVENT_SRC) + GENERATE_FIELD(PS_DONE_SWM, int) + GENERATE_FIELD(PS_DONE_CNTR, int) +END_REGISTER(CP_ME_PS_EVENT_SRC) + +START_REGISTER(CP_ME_PS_EVENT_ADDR) + GENERATE_FIELD(PS_DONE_SWAP, int) + GENERATE_FIELD(PS_DONE_ADDR, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR) + +START_REGISTER(CP_ME_PS_EVENT_DATA) + GENERATE_FIELD(PS_DONE_DATA, int) +END_REGISTER(CP_ME_PS_EVENT_DATA) + +START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + GENERATE_FIELD(PS_DONE_SWAP_SWM, int) + GENERATE_FIELD(PS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + GENERATE_FIELD(PS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_CF_EVENT_SRC) + GENERATE_FIELD(CF_DONE_SRC, int) +END_REGISTER(CP_ME_CF_EVENT_SRC) + +START_REGISTER(CP_ME_CF_EVENT_ADDR) + GENERATE_FIELD(CF_DONE_SWAP, int) + GENERATE_FIELD(CF_DONE_ADDR, int) +END_REGISTER(CP_ME_CF_EVENT_ADDR) + +START_REGISTER(CP_ME_CF_EVENT_DATA) + GENERATE_FIELD(CF_DONE_DATA, int) +END_REGISTER(CP_ME_CF_EVENT_DATA) + +START_REGISTER(CP_ME_NRT_ADDR) + GENERATE_FIELD(NRT_WRITE_SWAP, int) + GENERATE_FIELD(NRT_WRITE_ADDR, int) +END_REGISTER(CP_ME_NRT_ADDR) + +START_REGISTER(CP_ME_NRT_DATA) + GENERATE_FIELD(NRT_WRITE_DATA, int) +END_REGISTER(CP_ME_NRT_DATA) + +START_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + GENERATE_FIELD(VS_FETCH_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + +START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + GENERATE_FIELD(VS_FETCH_DONE_SWAP, int) + GENERATE_FIELD(VS_FETCH_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + +START_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + GENERATE_FIELD(VS_FETCH_DONE_DATA, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + +START_REGISTER(CP_INT_CNTL) + GENERATE_FIELD(SW_INT_MASK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int) + GENERATE_FIELD(OPCODE_ERROR_MASK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int) + GENERATE_FIELD(IB_ERROR_MASK, int) + GENERATE_FIELD(IB2_INT_MASK, int) + GENERATE_FIELD(IB1_INT_MASK, int) + GENERATE_FIELD(RB_INT_MASK, int) +END_REGISTER(CP_INT_CNTL) + +START_REGISTER(CP_INT_STATUS) + GENERATE_FIELD(SW_INT_STAT, int) + GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int) + GENERATE_FIELD(OPCODE_ERROR_STAT, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int) + GENERATE_FIELD(IB_ERROR_STAT, int) + GENERATE_FIELD(IB2_INT_STAT, int) + GENERATE_FIELD(IB1_INT_STAT, int) + GENERATE_FIELD(RB_INT_STAT, int) +END_REGISTER(CP_INT_STATUS) + +START_REGISTER(CP_INT_ACK) + GENERATE_FIELD(SW_INT_ACK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int) + GENERATE_FIELD(OPCODE_ERROR_ACK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int) + GENERATE_FIELD(IB_ERROR_ACK, int) + GENERATE_FIELD(IB2_INT_ACK, int) + GENERATE_FIELD(IB1_INT_ACK, int) + GENERATE_FIELD(RB_INT_ACK, int) +END_REGISTER(CP_INT_ACK) + +START_REGISTER(CP_PFP_UCODE_ADDR) + GENERATE_FIELD(UCODE_ADDR, hex) +END_REGISTER(CP_PFP_UCODE_ADDR) + +START_REGISTER(CP_PFP_UCODE_DATA) + GENERATE_FIELD(UCODE_DATA, hex) +END_REGISTER(CP_PFP_UCODE_DATA) + +START_REGISTER(CP_PERFMON_CNTL) + GENERATE_FIELD(PERFMON_STATE, int) + GENERATE_FIELD(PERFMON_ENABLE_MODE, int) +END_REGISTER(CP_PERFMON_CNTL) + +START_REGISTER(CP_PERFCOUNTER_SELECT) + GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL) +END_REGISTER(CP_PERFCOUNTER_SELECT) + +START_REGISTER(CP_PERFCOUNTER_LO) + GENERATE_FIELD(PERFCOUNT_LO, int) +END_REGISTER(CP_PERFCOUNTER_LO) + +START_REGISTER(CP_PERFCOUNTER_HI) + GENERATE_FIELD(PERFCOUNT_HI, int) +END_REGISTER(CP_PERFCOUNTER_HI) + +START_REGISTER(CP_BIN_MASK_LO) + GENERATE_FIELD(BIN_MASK_LO, int) +END_REGISTER(CP_BIN_MASK_LO) + +START_REGISTER(CP_BIN_MASK_HI) + GENERATE_FIELD(BIN_MASK_HI, int) +END_REGISTER(CP_BIN_MASK_HI) + +START_REGISTER(CP_BIN_SELECT_LO) + GENERATE_FIELD(BIN_SELECT_LO, int) +END_REGISTER(CP_BIN_SELECT_LO) + +START_REGISTER(CP_BIN_SELECT_HI) + GENERATE_FIELD(BIN_SELECT_HI, int) +END_REGISTER(CP_BIN_SELECT_HI) + +START_REGISTER(CP_NV_FLAGS_0) + GENERATE_FIELD(DISCARD_0, int) + GENERATE_FIELD(END_RCVD_0, int) + GENERATE_FIELD(DISCARD_1, int) + GENERATE_FIELD(END_RCVD_1, int) + GENERATE_FIELD(DISCARD_2, int) + GENERATE_FIELD(END_RCVD_2, int) + GENERATE_FIELD(DISCARD_3, int) + GENERATE_FIELD(END_RCVD_3, int) + GENERATE_FIELD(DISCARD_4, int) + GENERATE_FIELD(END_RCVD_4, int) + GENERATE_FIELD(DISCARD_5, int) + GENERATE_FIELD(END_RCVD_5, int) + GENERATE_FIELD(DISCARD_6, int) + GENERATE_FIELD(END_RCVD_6, int) + GENERATE_FIELD(DISCARD_7, int) + GENERATE_FIELD(END_RCVD_7, int) + GENERATE_FIELD(DISCARD_8, int) + GENERATE_FIELD(END_RCVD_8, int) + GENERATE_FIELD(DISCARD_9, int) + GENERATE_FIELD(END_RCVD_9, int) + GENERATE_FIELD(DISCARD_10, int) + GENERATE_FIELD(END_RCVD_10, int) + GENERATE_FIELD(DISCARD_11, int) + GENERATE_FIELD(END_RCVD_11, int) + GENERATE_FIELD(DISCARD_12, int) + GENERATE_FIELD(END_RCVD_12, int) + GENERATE_FIELD(DISCARD_13, int) + GENERATE_FIELD(END_RCVD_13, int) + GENERATE_FIELD(DISCARD_14, int) + GENERATE_FIELD(END_RCVD_14, int) + GENERATE_FIELD(DISCARD_15, int) + GENERATE_FIELD(END_RCVD_15, int) +END_REGISTER(CP_NV_FLAGS_0) + +START_REGISTER(CP_NV_FLAGS_1) + GENERATE_FIELD(DISCARD_16, int) + GENERATE_FIELD(END_RCVD_16, int) + GENERATE_FIELD(DISCARD_17, int) + GENERATE_FIELD(END_RCVD_17, int) + GENERATE_FIELD(DISCARD_18, int) + GENERATE_FIELD(END_RCVD_18, int) + GENERATE_FIELD(DISCARD_19, int) + GENERATE_FIELD(END_RCVD_19, int) + GENERATE_FIELD(DISCARD_20, int) + GENERATE_FIELD(END_RCVD_20, int) + GENERATE_FIELD(DISCARD_21, int) + GENERATE_FIELD(END_RCVD_21, int) + GENERATE_FIELD(DISCARD_22, int) + GENERATE_FIELD(END_RCVD_22, int) + GENERATE_FIELD(DISCARD_23, int) + GENERATE_FIELD(END_RCVD_23, int) + GENERATE_FIELD(DISCARD_24, int) + GENERATE_FIELD(END_RCVD_24, int) + GENERATE_FIELD(DISCARD_25, int) + GENERATE_FIELD(END_RCVD_25, int) + GENERATE_FIELD(DISCARD_26, int) + GENERATE_FIELD(END_RCVD_26, int) + GENERATE_FIELD(DISCARD_27, int) + GENERATE_FIELD(END_RCVD_27, int) + GENERATE_FIELD(DISCARD_28, int) + GENERATE_FIELD(END_RCVD_28, int) + GENERATE_FIELD(DISCARD_29, int) + GENERATE_FIELD(END_RCVD_29, int) + GENERATE_FIELD(DISCARD_30, int) + GENERATE_FIELD(END_RCVD_30, int) + GENERATE_FIELD(DISCARD_31, int) + GENERATE_FIELD(END_RCVD_31, int) +END_REGISTER(CP_NV_FLAGS_1) + +START_REGISTER(CP_NV_FLAGS_2) + GENERATE_FIELD(DISCARD_32, int) + GENERATE_FIELD(END_RCVD_32, int) + GENERATE_FIELD(DISCARD_33, int) + GENERATE_FIELD(END_RCVD_33, int) + GENERATE_FIELD(DISCARD_34, int) + GENERATE_FIELD(END_RCVD_34, int) + GENERATE_FIELD(DISCARD_35, int) + GENERATE_FIELD(END_RCVD_35, int) + GENERATE_FIELD(DISCARD_36, int) + GENERATE_FIELD(END_RCVD_36, int) + GENERATE_FIELD(DISCARD_37, int) + GENERATE_FIELD(END_RCVD_37, int) + GENERATE_FIELD(DISCARD_38, int) + GENERATE_FIELD(END_RCVD_38, int) + GENERATE_FIELD(DISCARD_39, int) + GENERATE_FIELD(END_RCVD_39, int) + GENERATE_FIELD(DISCARD_40, int) + GENERATE_FIELD(END_RCVD_40, int) + GENERATE_FIELD(DISCARD_41, int) + GENERATE_FIELD(END_RCVD_41, int) + GENERATE_FIELD(DISCARD_42, int) + GENERATE_FIELD(END_RCVD_42, int) + GENERATE_FIELD(DISCARD_43, int) + GENERATE_FIELD(END_RCVD_43, int) + GENERATE_FIELD(DISCARD_44, int) + GENERATE_FIELD(END_RCVD_44, int) + GENERATE_FIELD(DISCARD_45, int) + GENERATE_FIELD(END_RCVD_45, int) + GENERATE_FIELD(DISCARD_46, int) + GENERATE_FIELD(END_RCVD_46, int) + GENERATE_FIELD(DISCARD_47, int) + GENERATE_FIELD(END_RCVD_47, int) +END_REGISTER(CP_NV_FLAGS_2) + +START_REGISTER(CP_NV_FLAGS_3) + GENERATE_FIELD(DISCARD_48, int) + GENERATE_FIELD(END_RCVD_48, int) + GENERATE_FIELD(DISCARD_49, int) + GENERATE_FIELD(END_RCVD_49, int) + GENERATE_FIELD(DISCARD_50, int) + GENERATE_FIELD(END_RCVD_50, int) + GENERATE_FIELD(DISCARD_51, int) + GENERATE_FIELD(END_RCVD_51, int) + GENERATE_FIELD(DISCARD_52, int) + GENERATE_FIELD(END_RCVD_52, int) + GENERATE_FIELD(DISCARD_53, int) + GENERATE_FIELD(END_RCVD_53, int) + GENERATE_FIELD(DISCARD_54, int) + GENERATE_FIELD(END_RCVD_54, int) + GENERATE_FIELD(DISCARD_55, int) + GENERATE_FIELD(END_RCVD_55, int) + GENERATE_FIELD(DISCARD_56, int) + GENERATE_FIELD(END_RCVD_56, int) + GENERATE_FIELD(DISCARD_57, int) + GENERATE_FIELD(END_RCVD_57, int) + GENERATE_FIELD(DISCARD_58, int) + GENERATE_FIELD(END_RCVD_58, int) + GENERATE_FIELD(DISCARD_59, int) + GENERATE_FIELD(END_RCVD_59, int) + GENERATE_FIELD(DISCARD_60, int) + GENERATE_FIELD(END_RCVD_60, int) + GENERATE_FIELD(DISCARD_61, int) + GENERATE_FIELD(END_RCVD_61, int) + GENERATE_FIELD(DISCARD_62, int) + GENERATE_FIELD(END_RCVD_62, int) + GENERATE_FIELD(DISCARD_63, int) + GENERATE_FIELD(END_RCVD_63, int) +END_REGISTER(CP_NV_FLAGS_3) + +START_REGISTER(CP_STATE_DEBUG_INDEX) + GENERATE_FIELD(STATE_DEBUG_INDEX, int) +END_REGISTER(CP_STATE_DEBUG_INDEX) + +START_REGISTER(CP_STATE_DEBUG_DATA) + GENERATE_FIELD(STATE_DEBUG_DATA, int) +END_REGISTER(CP_STATE_DEBUG_DATA) + +START_REGISTER(CP_PROG_COUNTER) + GENERATE_FIELD(COUNTER, int) +END_REGISTER(CP_PROG_COUNTER) + +START_REGISTER(CP_STAT) + GENERATE_FIELD(MIU_WR_BUSY, int) + GENERATE_FIELD(MIU_RD_REQ_BUSY, int) + GENERATE_FIELD(MIU_RD_RETURN_BUSY, int) + GENERATE_FIELD(RBIU_BUSY, int) + GENERATE_FIELD(RCIU_BUSY, int) + GENERATE_FIELD(CSF_RING_BUSY, int) + GENERATE_FIELD(CSF_INDIRECTS_BUSY, int) + GENERATE_FIELD(CSF_INDIRECT2_BUSY, int) + GENERATE_FIELD(CSF_ST_BUSY, int) + GENERATE_FIELD(CSF_BUSY, int) + GENERATE_FIELD(RING_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int) + GENERATE_FIELD(ST_QUEUE_BUSY, int) + GENERATE_FIELD(PFP_BUSY, int) + GENERATE_FIELD(MEQ_RING_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int) + GENERATE_FIELD(MIU_WC_STALL, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(_3D_BUSY, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(ME_WC_BUSY, int) + GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int) + GENERATE_FIELD(CP_BUSY, int) +END_REGISTER(CP_STAT) + +START_REGISTER(BIOS_0_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_0_SCRATCH) + +START_REGISTER(BIOS_1_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_1_SCRATCH) + +START_REGISTER(BIOS_2_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_2_SCRATCH) + +START_REGISTER(BIOS_3_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_3_SCRATCH) + +START_REGISTER(BIOS_4_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_4_SCRATCH) + +START_REGISTER(BIOS_5_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_5_SCRATCH) + +START_REGISTER(BIOS_6_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_6_SCRATCH) + +START_REGISTER(BIOS_7_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_7_SCRATCH) + +START_REGISTER(BIOS_8_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_8_SCRATCH) + +START_REGISTER(BIOS_9_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_9_SCRATCH) + +START_REGISTER(BIOS_10_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_10_SCRATCH) + +START_REGISTER(BIOS_11_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_11_SCRATCH) + +START_REGISTER(BIOS_12_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_12_SCRATCH) + +START_REGISTER(BIOS_13_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_13_SCRATCH) + +START_REGISTER(BIOS_14_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_14_SCRATCH) + +START_REGISTER(BIOS_15_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_15_SCRATCH) + +START_REGISTER(COHER_SIZE_PM4) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_PM4) + +START_REGISTER(COHER_BASE_PM4) + GENERATE_FIELD(BASE, int) +END_REGISTER(COHER_BASE_PM4) + +START_REGISTER(COHER_STATUS_PM4) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_PM4) + +START_REGISTER(COHER_SIZE_HOST) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_HOST) + +START_REGISTER(COHER_BASE_HOST) + GENERATE_FIELD(BASE, hex) +END_REGISTER(COHER_BASE_HOST) + +START_REGISTER(COHER_STATUS_HOST) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_HOST) + +START_REGISTER(COHER_DEST_BASE_0) + GENERATE_FIELD(DEST_BASE_0, hex) +END_REGISTER(COHER_DEST_BASE_0) + +START_REGISTER(COHER_DEST_BASE_1) + GENERATE_FIELD(DEST_BASE_1, hex) +END_REGISTER(COHER_DEST_BASE_1) + +START_REGISTER(COHER_DEST_BASE_2) + GENERATE_FIELD(DEST_BASE_2, hex) +END_REGISTER(COHER_DEST_BASE_2) + +START_REGISTER(COHER_DEST_BASE_3) + GENERATE_FIELD(DEST_BASE_3, hex) +END_REGISTER(COHER_DEST_BASE_3) + +START_REGISTER(COHER_DEST_BASE_4) + GENERATE_FIELD(DEST_BASE_4, hex) +END_REGISTER(COHER_DEST_BASE_4) + +START_REGISTER(COHER_DEST_BASE_5) + GENERATE_FIELD(DEST_BASE_5, hex) +END_REGISTER(COHER_DEST_BASE_5) + +START_REGISTER(COHER_DEST_BASE_6) + GENERATE_FIELD(DEST_BASE_6, hex) +END_REGISTER(COHER_DEST_BASE_6) + +START_REGISTER(COHER_DEST_BASE_7) + GENERATE_FIELD(DEST_BASE_7, hex) +END_REGISTER(COHER_DEST_BASE_7) + +START_REGISTER(RB_SURFACE_INFO) + GENERATE_FIELD(SURFACE_PITCH, uint) + GENERATE_FIELD(MSAA_SAMPLES, MSAASamples) +END_REGISTER(RB_SURFACE_INFO) + +START_REGISTER(RB_COLOR_INFO) + GENERATE_FIELD(COLOR_FORMAT, ColorformatX) + GENERATE_FIELD(COLOR_ROUND_MODE, uint) + GENERATE_FIELD(COLOR_LINEAR, bool) + GENERATE_FIELD(COLOR_ENDIAN, uint) + GENERATE_FIELD(COLOR_SWAP, uint) + GENERATE_FIELD(COLOR_BASE, uint) +END_REGISTER(RB_COLOR_INFO) + +START_REGISTER(RB_DEPTH_INFO) + GENERATE_FIELD(DEPTH_FORMAT, DepthformatX) + GENERATE_FIELD(DEPTH_BASE, uint) +END_REGISTER(RB_DEPTH_INFO) + +START_REGISTER(RB_STENCILREFMASK) + GENERATE_FIELD(STENCILREF, hex) + GENERATE_FIELD(STENCILMASK, hex) + GENERATE_FIELD(STENCILWRITEMASK, hex) + GENERATE_FIELD(RESERVED0, bool) + GENERATE_FIELD(RESERVED1, bool) +END_REGISTER(RB_STENCILREFMASK) + +START_REGISTER(RB_ALPHA_REF) + GENERATE_FIELD(ALPHA_REF, float) +END_REGISTER(RB_ALPHA_REF) + +START_REGISTER(RB_COLOR_MASK) + GENERATE_FIELD(WRITE_RED, bool) + GENERATE_FIELD(WRITE_GREEN, bool) + GENERATE_FIELD(WRITE_BLUE, bool) + GENERATE_FIELD(WRITE_ALPHA, bool) + GENERATE_FIELD(RESERVED2, bool) + GENERATE_FIELD(RESERVED3, bool) +END_REGISTER(RB_COLOR_MASK) + +START_REGISTER(RB_BLEND_RED) + GENERATE_FIELD(BLEND_RED, uint) +END_REGISTER(RB_BLEND_RED) + +START_REGISTER(RB_BLEND_GREEN) + GENERATE_FIELD(BLEND_GREEN, uint) +END_REGISTER(RB_BLEND_GREEN) + +START_REGISTER(RB_BLEND_BLUE) + GENERATE_FIELD(BLEND_BLUE, uint) +END_REGISTER(RB_BLEND_BLUE) + +START_REGISTER(RB_BLEND_ALPHA) + GENERATE_FIELD(BLEND_ALPHA, uint) +END_REGISTER(RB_BLEND_ALPHA) + +START_REGISTER(RB_FOG_COLOR) + GENERATE_FIELD(FOG_RED, uint) + GENERATE_FIELD(FOG_GREEN, uint) + GENERATE_FIELD(FOG_BLUE, uint) +END_REGISTER(RB_FOG_COLOR) + +START_REGISTER(RB_STENCILREFMASK_BF) + GENERATE_FIELD(STENCILREF_BF, hex) + GENERATE_FIELD(STENCILMASK_BF, hex) + GENERATE_FIELD(STENCILWRITEMASK_BF, hex) + GENERATE_FIELD(RESERVED4, bool) + GENERATE_FIELD(RESERVED5, bool) +END_REGISTER(RB_STENCILREFMASK_BF) + +START_REGISTER(RB_DEPTHCONTROL) + GENERATE_FIELD(STENCIL_ENABLE, bool) + GENERATE_FIELD(Z_ENABLE, bool) + GENERATE_FIELD(Z_WRITE_ENABLE, bool) + GENERATE_FIELD(EARLY_Z_ENABLE, bool) + GENERATE_FIELD(ZFUNC, CompareFrag) + GENERATE_FIELD(BACKFACE_ENABLE, bool) + GENERATE_FIELD(STENCILFUNC, CompareRef) + GENERATE_FIELD(STENCILFAIL, StencilOp) + GENERATE_FIELD(STENCILZPASS, StencilOp) + GENERATE_FIELD(STENCILZFAIL, StencilOp) + GENERATE_FIELD(STENCILFUNC_BF, CompareRef) + GENERATE_FIELD(STENCILFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILZPASS_BF, StencilOp) + GENERATE_FIELD(STENCILZFAIL_BF, StencilOp) +END_REGISTER(RB_DEPTHCONTROL) + +START_REGISTER(RB_BLENDCONTROL) + GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX) + GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX) + GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX) + GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX) + GENERATE_FIELD(BLEND_FORCE_ENABLE, bool) + GENERATE_FIELD(BLEND_FORCE, bool) +END_REGISTER(RB_BLENDCONTROL) + +START_REGISTER(RB_COLORCONTROL) + GENERATE_FIELD(ALPHA_FUNC, CompareRef) + GENERATE_FIELD(ALPHA_TEST_ENABLE, bool) + GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool) + GENERATE_FIELD(BLEND_DISABLE, bool) + GENERATE_FIELD(FOG_ENABLE, bool) + GENERATE_FIELD(VS_EXPORTS_FOG, bool) + GENERATE_FIELD(ROP_CODE, uint) + GENERATE_FIELD(DITHER_MODE, DitherModeX) + GENERATE_FIELD(DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(PIXEL_FOG, bool) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex) +END_REGISTER(RB_COLORCONTROL) + +START_REGISTER(RB_MODECONTROL) + GENERATE_FIELD(EDRAM_MODE, EdramMode) +END_REGISTER(RB_MODECONTROL) + +START_REGISTER(RB_COLOR_DEST_MASK) + GENERATE_FIELD(COLOR_DEST_MASK, uint) +END_REGISTER(RB_COLOR_DEST_MASK) + +START_REGISTER(RB_COPY_CONTROL) + GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect) + GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool) + GENERATE_FIELD(CLEAR_MASK, uint) +END_REGISTER(RB_COPY_CONTROL) + +START_REGISTER(RB_COPY_DEST_BASE) + GENERATE_FIELD(COPY_DEST_BASE, uint) +END_REGISTER(RB_COPY_DEST_BASE) + +START_REGISTER(RB_COPY_DEST_PITCH) + GENERATE_FIELD(COPY_DEST_PITCH, uint) +END_REGISTER(RB_COPY_DEST_PITCH) + +START_REGISTER(RB_COPY_DEST_INFO) + GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian) + GENERATE_FIELD(COPY_DEST_LINEAR, uint) + GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX) + GENERATE_FIELD(COPY_DEST_SWAP, uint) + GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX) + GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(COPY_MASK_WRITE_RED, hex) + GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex) + GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex) + GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex) +END_REGISTER(RB_COPY_DEST_INFO) + +START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + GENERATE_FIELD(OFFSET_X, uint) + GENERATE_FIELD(OFFSET_Y, uint) +END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + +START_REGISTER(RB_DEPTH_CLEAR) + GENERATE_FIELD(DEPTH_CLEAR, uint) +END_REGISTER(RB_DEPTH_CLEAR) + +START_REGISTER(RB_SAMPLE_COUNT_CTL) + GENERATE_FIELD(RESET_SAMPLE_COUNT, bool) + GENERATE_FIELD(COPY_SAMPLE_COUNT, bool) +END_REGISTER(RB_SAMPLE_COUNT_CTL) + +START_REGISTER(RB_SAMPLE_COUNT_ADDR) + GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint) +END_REGISTER(RB_SAMPLE_COUNT_ADDR) + +START_REGISTER(RB_BC_CONTROL) + GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint) + GENERATE_FIELD(DISABLE_EDRAM_CAM, bool) + GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool) + GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool) + GENERATE_FIELD(AZ_THROTTLE_COUNT, uint) + GENERATE_FIELD(ENABLE_CRC_UPDATE, bool) + GENERATE_FIELD(CRC_MODE, bool) + GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool) + GENERATE_FIELD(DISABLE_ACCUM, bool) + GENERATE_FIELD(ACCUM_ALLOC_MASK, uint) + GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool) + GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int) + GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(CRC_SYSTEM, bool) + GENERATE_FIELD(RESERVED6, bool) +END_REGISTER(RB_BC_CONTROL) + +START_REGISTER(RB_EDRAM_INFO) + GENERATE_FIELD(EDRAM_SIZE, EdramSizeX) + GENERATE_FIELD(EDRAM_MAPPING_MODE, uint) + GENERATE_FIELD(EDRAM_RANGE, hex) +END_REGISTER(RB_EDRAM_INFO) + +START_REGISTER(RB_CRC_RD_PORT) + GENERATE_FIELD(CRC_DATA, hex) +END_REGISTER(RB_CRC_RD_PORT) + +START_REGISTER(RB_CRC_CONTROL) + GENERATE_FIELD(CRC_RD_ADVANCE, bool) +END_REGISTER(RB_CRC_CONTROL) + +START_REGISTER(RB_CRC_MASK) + GENERATE_FIELD(CRC_MASK, hex) +END_REGISTER(RB_CRC_MASK) + +START_REGISTER(RB_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT) +END_REGISTER(RB_PERFCOUNTER0_SELECT) + +START_REGISTER(RB_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_LOW) + +START_REGISTER(RB_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_HI) + +START_REGISTER(RB_TOTAL_SAMPLES) + GENERATE_FIELD(TOTAL_SAMPLES, int) +END_REGISTER(RB_TOTAL_SAMPLES) + +START_REGISTER(RB_ZPASS_SAMPLES) + GENERATE_FIELD(ZPASS_SAMPLES, int) +END_REGISTER(RB_ZPASS_SAMPLES) + +START_REGISTER(RB_ZFAIL_SAMPLES) + GENERATE_FIELD(ZFAIL_SAMPLES, int) +END_REGISTER(RB_ZFAIL_SAMPLES) + +START_REGISTER(RB_SFAIL_SAMPLES) + GENERATE_FIELD(SFAIL_SAMPLES, int) +END_REGISTER(RB_SFAIL_SAMPLES) + +START_REGISTER(RB_DEBUG_0) + GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_Z1_FULL, bool) + GENERATE_FIELD(RDREQ_Z0_FULL, bool) + GENERATE_FIELD(RDREQ_C1_FULL, bool) + GENERATE_FIELD(RDREQ_C0_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool) + GENERATE_FIELD(WRREQ_Z1_FULL, bool) + GENERATE_FIELD(WRREQ_Z0_FULL, bool) + GENERATE_FIELD(WRREQ_C1_FULL, bool) + GENERATE_FIELD(WRREQ_C0_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool) + GENERATE_FIELD(C_SX_LAT_FULL, bool) + GENERATE_FIELD(C_SX_CMD_FULL, bool) + GENERATE_FIELD(C_EZ_TILE_FULL, bool) + GENERATE_FIELD(C_REQ_FULL, bool) + GENERATE_FIELD(C_MASK_FULL, bool) + GENERATE_FIELD(EZ_INFSAMP_FULL, bool) +END_REGISTER(RB_DEBUG_0) + +START_REGISTER(RB_DEBUG_1) + GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z1_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z0_EMPTY, bool) + GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool) + GENERATE_FIELD(C_SX_LAT_EMPTY, bool) + GENERATE_FIELD(C_SX_CMD_EMPTY, bool) + GENERATE_FIELD(C_EZ_TILE_EMPTY, bool) + GENERATE_FIELD(C_REQ_EMPTY, bool) + GENERATE_FIELD(C_MASK_EMPTY, bool) + GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool) +END_REGISTER(RB_DEBUG_1) + +START_REGISTER(RB_DEBUG_2) + GENERATE_FIELD(TILE_FIFO_COUNT, bool) + GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool) + GENERATE_FIELD(MEM_EXPORT_FLAG, bool) + GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool) + GENERATE_FIELD(CURRENT_TILE_EVENT, bool) + GENERATE_FIELD(EZ_INFTILE_FULL, bool) + GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool) + GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool) + GENERATE_FIELD(Z0_MASK_FULL, bool) + GENERATE_FIELD(Z1_MASK_FULL, bool) + GENERATE_FIELD(Z0_REQ_FULL, bool) + GENERATE_FIELD(Z1_REQ_FULL, bool) + GENERATE_FIELD(Z_SAMP_FULL, bool) + GENERATE_FIELD(Z_TILE_FULL, bool) + GENERATE_FIELD(EZ_INFTILE_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool) + GENERATE_FIELD(Z0_MASK_EMPTY, bool) + GENERATE_FIELD(Z1_MASK_EMPTY, bool) + GENERATE_FIELD(Z0_REQ_EMPTY, bool) + GENERATE_FIELD(Z1_REQ_EMPTY, bool) + GENERATE_FIELD(Z_SAMP_EMPTY, bool) + GENERATE_FIELD(Z_TILE_EMPTY, bool) +END_REGISTER(RB_DEBUG_2) + +START_REGISTER(RB_DEBUG_3) + GENERATE_FIELD(ACCUM_VALID, bool) + GENERATE_FIELD(ACCUM_FLUSHING, bool) + GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool) + GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool) + GENERATE_FIELD(SHD_FULL, bool) + GENERATE_FIELD(SHD_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool) + GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool) + GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool) + GENERATE_FIELD(ZEXP_LOWER_FULL, bool) + GENERATE_FIELD(ZEXP_UPPER_FULL, bool) +END_REGISTER(RB_DEBUG_3) + +START_REGISTER(RB_DEBUG_4) + GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool) + GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool) + GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool) +END_REGISTER(RB_DEBUG_4) + +START_REGISTER(RB_FLAG_CONTROL) + GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool) +END_REGISTER(RB_FLAG_CONTROL) + +START_REGISTER(RB_BC_SPARES) + GENERATE_FIELD(RESERVED, bool) +END_REGISTER(RB_BC_SPARES) + +START_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray) + GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray) + GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray) + GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX) +END_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + +START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX) +END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h new file mode 100644 index 000000000000..0e32e421d0a3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h @@ -0,0 +1,95 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _R400IPT_H_ +#define _R400IPT_H_ + +// Hand-generated list from Yamato_PM4_Spec.doc + +#define PM4_PACKET0_NOP 0x00000000 // Empty type-0 packet header +#define PM4_PACKET1_NOP 0x40000000 // Empty type-1 packet header +#define PM4_PACKET2_NOP 0x80000000 // Empty type-2 packet header (reserved) + +#define PM4_COUNT_SHIFT 16 +#define PM4_COUNT_MASK +#define PM4_PACKET_COUNT(__x) ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000) +// Type 3 packet headers + +#define PM4_PACKET3_NOP 0xC0001000 // Do nothing. +#define PM4_PACKET3_IB_PREFETCH_END 0xC0001700 // Internal Packet Used Only by CP +#define PM4_PACKET3_SUBBLK_PREFETCH 0xC0001F00 // Internal Packet Used Only by CP + +#define PM4_PACKET3_INSTR_PREFETCH 0xC0002000 // Internal Packet Used Only by CP +#define PM4_PACKET3_REG_RMW 0xC0002100 // Register Read-Modify-Write New for R400 +#define PM4_PACKET3_DRAW_INDX 0xC0002200 // Initiate fetch of index buffer New for R400 +#define PM4_PACKET3_VIZ_QUERY 0xC0002300 // Begin/End initiator for Viz Query extent processing New for R400 +#define PM4_PACKET3_SET_STATE 0xC0002500 // Fetch State Sub-Blocks and Initiate Shader Code DMAs New for R400 +#define PM4_PACKET3_WAIT_FOR_IDLE 0xC0002600 // Wait for the engine to be idle. +#define PM4_PACKET3_IM_LOAD 0xC0002700 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_IM_LOAD_IMMEDIATE 0xC0002B00 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_SET_CONSTANT 0xC0002D00 // Load Constant Into Chip & Shadow to Memory New for R400 +#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT 0xC0002E00 // Load All Constants from a Location in Memory New for R400 +#define PM4_PACKET3_LOAD_ALU_CONSTANT 0xC0002F00 // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants + +#define PM4_PACKET3_DRAW_INDX_BIN 0xC0003400 // Initiate fetch of index buffer and BIN info used for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2_BIN 0xC0003500 // Draw using supplied indices and initiate fetch of BIN info for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2 0xC0003600 // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt +#define PM4_PACKET3_INDIRECT_BUFFER_PFD 0xC0003700 +#define PM4_PACKET3_INVALIDATE_STATE 0xC0003B00 // Selective Invalidation of State Pointers New for R400 +#define PM4_PACKET3_WAIT_REG_MEM 0xC0003C00 // Wait Until a Register or Memory Location is a Specific Value. New for R400 +#define PM4_PACKET3_MEM_WRITE 0xC0003D00 // Write DWORD to Memory For Synchronization New for R400 +#define PM4_PACKET3_REG_TO_MEM 0xC0003E00 // Reads Register in Chip and Writes to Memory New for R400 +#define PM4_PACKET3_INDIRECT_BUFFER 0xC0003F00 // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer. Supported + +#define PM4_PACKET3_CP_INTERRUPT 0xC0004000 // Generate Interrupt from the Command Stream New for R400 +#define PM4_PACKET3_COND_EXEC 0xC0004400 // Conditional execution of a sequence of packets +#define PM4_PACKET3_COND_WRITE 0xC0004500 // Conditional Write to Memory New for R400 +#define PM4_PACKET3_EVENT_WRITE 0xC0004600 // Generate An Event that Creates a Write to Memory when Completed New for R400 +#define PM4_PACKET3_INSTR_MATCH 0xC0004700 // Internal Packet Used Only by CP +#define PM4_PACKET3_ME_INIT 0xC0004800 // Initialize CP's Micro Engine New for R400 +#define PM4_PACKET3_CONST_PREFETCH 0xC0004900 // Internal packet used only by CP +#define PM4_PACKET3_MEM_WRITE_CNTR 0xC0004F00 + +#define PM4_PACKET3_SET_BIN_MASK 0xC0005000 // Sets the 64-bit BIN_MASK register in the PFP +#define PM4_PACKET3_SET_BIN_SELECT 0xC0005100 // Sets the 64-bit BIN_SELECT register in the PFP +#define PM4_PACKET3_WAIT_REG_EQ 0xC0005200 // Wait until a register location is equal to a specific value +#define PM4_PACKET3_WAIT_REG_GTE 0xC0005300 // Wait until a register location is greater than or equal to a specific value +#define PM4_PACKET3_INCR_UPDT_STATE 0xC0005500 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_CONST 0xC0005600 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_INSTR 0xC0005700 // Internal Packet Used Only by CP +#define PM4_PACKET3_EVENT_WRITE_SHD 0xC0005800 // Generate a VS|PS_Done Event. +#define PM4_PACKET3_EVENT_WRITE_CFL 0xC0005900 // Generate a Cach Flush Done Event +#define PM4_PACKET3_EVENT_WRITE_ZPD 0xC0005B00 // Generate a Cach Flush Done Event +#define PM4_PACKET3_WAIT_UNTIL_READ 0xC0005C00 // Wait Until a Read completes. +#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE 0xC0005D00 // Wait Until all Base/Size writes from an IB_PFD packet have completed. +#define PM4_PACKET3_CONTEXT_UPDATE 0xC0005E00 // Updates the current context if needed. + + /****** New Opcodes For R400 (all decode values are TBD) ******/ + + +#endif // _R400IPT_H_ diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h new file mode 100644 index 000000000000..52ced9af774c --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h @@ -0,0 +1,5908 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_MASK_HEADER) +#define _yamato_MASK_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_XY_FMT 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_Z_FMT 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__VTX_W0_FMT 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF 0x00000800L + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE 0x00010000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR 0x00200000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN 0x00400000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK 0x00800000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN 0x00800000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN 0x01000000L + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA 0x00000001L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_CL_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_SC_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__PIX_CENTER 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR_MASK 0xffffffe0L + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_FRONT 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__CULL_BACK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__FACE 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE 0x00002000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK 0x00008000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE 0x00008000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE 0x00010000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK 0x00040000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE 0x00040000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA 0x00200000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK 0x00800000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE 0x00800000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L +#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS_MASK 0x10000000L +#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS 0x10000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK 0x20000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS 0x20000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK 0x80000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE 0x80000000L + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x00007fffL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0x7fff0000L + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK_MASK 0x0000ffffL + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL_MASK 0x000000ffL +#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK 0x00000100L +#define PA_SC_LINE_CNTL__USE_BRES_CNTL 0x00000100L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__LAST_PIXEL 0x00000400L + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x3fff0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE 0x80000000L + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x3fff0000L + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0x7fff0000L + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0x7fff0000L + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK 0x0000003eL +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK 0x00000080L +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z 0x00000080L + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK 0xffffffffL + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +#define PA_CL_CNTL_STATUS__CL_BUSY 0x80000000L + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +#define PA_SU_CNTL_STATUS__SU_BUSY 0x80000000L + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY_MASK 0x80000000L +#define PA_SC_CNTL_STATUS__SC_BUSY 0x80000000L + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00000008L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full 0x00000008L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full 0x00000020L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00000080L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full 0x00000080L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00000800L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full 0x00000800L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00002000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full 0x00002000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full 0x00020000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full 0x00080000L +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xfff00000L + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00380000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff000000L + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK 0x001fffffL +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK 0x7f000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK 0x00000007L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK 0x00000070L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK 0x000fff00L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK 0x00000007L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK 0x00000070L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event 0x00000080L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK 0xffffff00L + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK 0x00000006L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK 0x00030000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK 0xf0000000L + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK 0x00000001L +#define CLIPPER_DEBUG_REG09__clprim_in_back_event 0x00000001L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK 0x000000c0L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK 0x00003000L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK 0x000c0000L +#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK 0x00100000L +#define CLIPPER_DEBUG_REG09__prim_back_valid 0x00100000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK 0x20000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full 0x20000000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK 0x00000030L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK 0x00000c00L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK 0x00030000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK 0x00180000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK 0xfffffff0L + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK 0x00200000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid 0x00200000L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK 0xffc00000L + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK 0x000007f0L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK 0x00003800L +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK 0xf8000000L + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK 0x00000380L +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x00001c00L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK 0x0000e000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx 0x00010000L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK 0x00060000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x00780000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3f800000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel 0x80000000L + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK 0x00000003L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK 0x0000000cL +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK 0x00000780L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00007000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector 0x00008000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK 0x000f0000L +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG1__aux_sel 0x00100000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK 0x00600000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK 0x01800000L +#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK 0xfe000000L + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent_MASK 0x00000001L +#define SXIFCCG_DEBUG_REG2__sx_sent 0x00000001L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK 0x00000002L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3 0x00000002L +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_aux 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x000001f8L +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x0000fe00L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2 0x00010000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx 0x00020000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK 0x000c0000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK 0x03c00000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x04000000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded 0x04000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK 0xe0000000L + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK 0x00000010L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3 0x00000010L +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x000000e0L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK 0x00000f00L +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00003000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full 0x00008000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK 0x00030000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x00080000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full 0x00080000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x00200000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full 0x00200000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK 0xffc00000L + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000001fL +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x000007e0L +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00000800L +#define SETUP_DEBUG_REG0__ge_stallb 0x00000800L +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00001000L +#define SETUP_DEBUG_REG0__geom_enable 0x00001000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00004000L +#define SETUP_DEBUG_REG0__su_clip_rtr 0x00004000L +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00008000L +#define SETUP_DEBUG_REG0__pfifo_busy 0x00008000L +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00010000L +#define SETUP_DEBUG_REG0__su_cntl_busy 0x00010000L +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00020000L +#define SETUP_DEBUG_REG0__geom_busy 0x00020000L + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00000800L +#define SETUP_DEBUG_REG4__null_prim_gated 0x00000800L +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00001000L +#define SETUP_DEBUG_REG4__backfacing_gated 0x00001000L +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x0000e000L +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00010000L +#define SETUP_DEBUG_REG4__clipped_gated 0x00010000L +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x000e0000L +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00100000L +#define SETUP_DEBUG_REG4__xmajor_gated 0x00100000L +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x00600000L +#define SETUP_DEBUG_REG4__type_gated_MASK 0x03800000L +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x04000000L +#define SETUP_DEBUG_REG4__fpov_gated 0x04000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK 0x08000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated 0x08000000L +#define SETUP_DEBUG_REG4__event_gated_MASK 0x10000000L +#define SETUP_DEBUG_REG4__event_gated 0x10000000L +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x20000000L +#define SETUP_DEBUG_REG4__eop_gated 0x20000000L + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x003ff800L +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x00c00000L +#define SETUP_DEBUG_REG5__event_id_gated_MASK 0x1f000000L + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000001fL + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1_MASK 0x00000001L +#define SC_DEBUG_0__pa_freeze_b1 0x00000001L +#define SC_DEBUG_0__pa_sc_valid_MASK 0x00000002L +#define SC_DEBUG_0__pa_sc_valid 0x00000002L +#define SC_DEBUG_0__pa_sc_phase_MASK 0x0000001cL +#define SC_DEBUG_0__cntx_cnt_MASK 0x00000fe0L +#define SC_DEBUG_0__decr_cntx_cnt_MASK 0x00001000L +#define SC_DEBUG_0__decr_cntx_cnt 0x00001000L +#define SC_DEBUG_0__incr_cntx_cnt_MASK 0x00002000L +#define SC_DEBUG_0__incr_cntx_cnt 0x00002000L +#define SC_DEBUG_0__trigger_MASK 0x80000000L +#define SC_DEBUG_0__trigger 0x80000000L + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state_MASK 0x00000007L +#define SC_DEBUG_1__em1_data_ready_MASK 0x00000008L +#define SC_DEBUG_1__em1_data_ready 0x00000008L +#define SC_DEBUG_1__em2_data_ready_MASK 0x00000010L +#define SC_DEBUG_1__em2_data_ready 0x00000010L +#define SC_DEBUG_1__move_em1_to_em2_MASK 0x00000020L +#define SC_DEBUG_1__move_em1_to_em2 0x00000020L +#define SC_DEBUG_1__ef_data_ready_MASK 0x00000040L +#define SC_DEBUG_1__ef_data_ready 0x00000040L +#define SC_DEBUG_1__ef_state_MASK 0x00000180L +#define SC_DEBUG_1__pipe_valid_MASK 0x00000200L +#define SC_DEBUG_1__pipe_valid 0x00000200L +#define SC_DEBUG_1__trigger_MASK 0x80000000L +#define SC_DEBUG_1__trigger 0x80000000L + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly_MASK 0x00000001L +#define SC_DEBUG_2__rc_rtr_dly 0x00000001L +#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK 0x00000002L +#define SC_DEBUG_2__qmask_ff_alm_full_d1 0x00000002L +#define SC_DEBUG_2__pipe_freeze_b_MASK 0x00000008L +#define SC_DEBUG_2__pipe_freeze_b 0x00000008L +#define SC_DEBUG_2__prim_rts_MASK 0x00000010L +#define SC_DEBUG_2__prim_rts 0x00000010L +#define SC_DEBUG_2__next_prim_rts_dly_MASK 0x00000020L +#define SC_DEBUG_2__next_prim_rts_dly 0x00000020L +#define SC_DEBUG_2__next_prim_rtr_dly_MASK 0x00000040L +#define SC_DEBUG_2__next_prim_rtr_dly 0x00000040L +#define SC_DEBUG_2__pre_stage1_rts_d1_MASK 0x00000080L +#define SC_DEBUG_2__pre_stage1_rts_d1 0x00000080L +#define SC_DEBUG_2__stage0_rts_MASK 0x00000100L +#define SC_DEBUG_2__stage0_rts 0x00000100L +#define SC_DEBUG_2__phase_rts_dly_MASK 0x00000200L +#define SC_DEBUG_2__phase_rts_dly 0x00000200L +#define SC_DEBUG_2__end_of_prim_s1_dly_MASK 0x00008000L +#define SC_DEBUG_2__end_of_prim_s1_dly 0x00008000L +#define SC_DEBUG_2__pass_empty_prim_s1_MASK 0x00010000L +#define SC_DEBUG_2__pass_empty_prim_s1 0x00010000L +#define SC_DEBUG_2__event_id_s1_MASK 0x003e0000L +#define SC_DEBUG_2__event_s1_MASK 0x00400000L +#define SC_DEBUG_2__event_s1 0x00400000L +#define SC_DEBUG_2__trigger_MASK 0x80000000L +#define SC_DEBUG_2__trigger 0x80000000L + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1_MASK 0x000007ffL +#define SC_DEBUG_3__y_curr_s1_MASK 0x003ff800L +#define SC_DEBUG_3__trigger_MASK 0x80000000L +#define SC_DEBUG_3__trigger 0x80000000L + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1_MASK 0x00003fffL +#define SC_DEBUG_4__y_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_4__y_dir_s1_MASK 0x10000000L +#define SC_DEBUG_4__y_dir_s1 0x10000000L +#define SC_DEBUG_4__trigger_MASK 0x80000000L +#define SC_DEBUG_4__trigger 0x80000000L + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1_MASK 0x00003fffL +#define SC_DEBUG_5__x_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_5__x_dir_s1_MASK 0x10000000L +#define SC_DEBUG_5__x_dir_s1 0x10000000L +#define SC_DEBUG_5__trigger_MASK 0x80000000L +#define SC_DEBUG_5__trigger 0x80000000L + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty_MASK 0x00000001L +#define SC_DEBUG_6__z_ff_empty 0x00000001L +#define SC_DEBUG_6__qmcntl_ff_empty_MASK 0x00000002L +#define SC_DEBUG_6__qmcntl_ff_empty 0x00000002L +#define SC_DEBUG_6__xy_ff_empty_MASK 0x00000004L +#define SC_DEBUG_6__xy_ff_empty 0x00000004L +#define SC_DEBUG_6__event_flag_MASK 0x00000008L +#define SC_DEBUG_6__event_flag 0x00000008L +#define SC_DEBUG_6__z_mask_needed_MASK 0x00000010L +#define SC_DEBUG_6__z_mask_needed 0x00000010L +#define SC_DEBUG_6__state_MASK 0x000000e0L +#define SC_DEBUG_6__state_delayed_MASK 0x00000700L +#define SC_DEBUG_6__data_valid_MASK 0x00000800L +#define SC_DEBUG_6__data_valid 0x00000800L +#define SC_DEBUG_6__data_valid_d_MASK 0x00001000L +#define SC_DEBUG_6__data_valid_d 0x00001000L +#define SC_DEBUG_6__tilex_delayed_MASK 0x003fe000L +#define SC_DEBUG_6__tiley_delayed_MASK 0x7fc00000L +#define SC_DEBUG_6__trigger_MASK 0x80000000L +#define SC_DEBUG_6__trigger 0x80000000L + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag_MASK 0x00000001L +#define SC_DEBUG_7__event_flag 0x00000001L +#define SC_DEBUG_7__deallocate_MASK 0x0000000eL +#define SC_DEBUG_7__fposition_MASK 0x00000010L +#define SC_DEBUG_7__fposition 0x00000010L +#define SC_DEBUG_7__sr_prim_we_MASK 0x00000020L +#define SC_DEBUG_7__sr_prim_we 0x00000020L +#define SC_DEBUG_7__last_tile_MASK 0x00000040L +#define SC_DEBUG_7__last_tile 0x00000040L +#define SC_DEBUG_7__tile_ff_we_MASK 0x00000080L +#define SC_DEBUG_7__tile_ff_we 0x00000080L +#define SC_DEBUG_7__qs_data_valid_MASK 0x00000100L +#define SC_DEBUG_7__qs_data_valid 0x00000100L +#define SC_DEBUG_7__qs_q0_y_MASK 0x00000600L +#define SC_DEBUG_7__qs_q0_x_MASK 0x00001800L +#define SC_DEBUG_7__qs_q0_valid_MASK 0x00002000L +#define SC_DEBUG_7__qs_q0_valid 0x00002000L +#define SC_DEBUG_7__prim_ff_we_MASK 0x00004000L +#define SC_DEBUG_7__prim_ff_we 0x00004000L +#define SC_DEBUG_7__tile_ff_re_MASK 0x00008000L +#define SC_DEBUG_7__tile_ff_re 0x00008000L +#define SC_DEBUG_7__fw_prim_data_valid_MASK 0x00010000L +#define SC_DEBUG_7__fw_prim_data_valid 0x00010000L +#define SC_DEBUG_7__last_quad_of_tile_MASK 0x00020000L +#define SC_DEBUG_7__last_quad_of_tile 0x00020000L +#define SC_DEBUG_7__first_quad_of_tile_MASK 0x00040000L +#define SC_DEBUG_7__first_quad_of_tile 0x00040000L +#define SC_DEBUG_7__first_quad_of_prim_MASK 0x00080000L +#define SC_DEBUG_7__first_quad_of_prim 0x00080000L +#define SC_DEBUG_7__new_prim_MASK 0x00100000L +#define SC_DEBUG_7__new_prim 0x00100000L +#define SC_DEBUG_7__load_new_tile_data_MASK 0x00200000L +#define SC_DEBUG_7__load_new_tile_data 0x00200000L +#define SC_DEBUG_7__state_MASK 0x00c00000L +#define SC_DEBUG_7__fifos_ready_MASK 0x01000000L +#define SC_DEBUG_7__fifos_ready 0x01000000L +#define SC_DEBUG_7__trigger_MASK 0x80000000L +#define SC_DEBUG_7__trigger 0x80000000L + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last_MASK 0x00000001L +#define SC_DEBUG_8__sample_last 0x00000001L +#define SC_DEBUG_8__sample_mask_MASK 0x0000001eL +#define SC_DEBUG_8__sample_y_MASK 0x00000060L +#define SC_DEBUG_8__sample_x_MASK 0x00000180L +#define SC_DEBUG_8__sample_send_MASK 0x00000200L +#define SC_DEBUG_8__sample_send 0x00000200L +#define SC_DEBUG_8__next_cycle_MASK 0x00000c00L +#define SC_DEBUG_8__ez_sample_ff_full_MASK 0x00001000L +#define SC_DEBUG_8__ez_sample_ff_full 0x00001000L +#define SC_DEBUG_8__rb_sc_samp_rtr_MASK 0x00002000L +#define SC_DEBUG_8__rb_sc_samp_rtr 0x00002000L +#define SC_DEBUG_8__num_samples_MASK 0x0000c000L +#define SC_DEBUG_8__last_quad_of_tile_MASK 0x00010000L +#define SC_DEBUG_8__last_quad_of_tile 0x00010000L +#define SC_DEBUG_8__last_quad_of_prim_MASK 0x00020000L +#define SC_DEBUG_8__last_quad_of_prim 0x00020000L +#define SC_DEBUG_8__first_quad_of_prim_MASK 0x00040000L +#define SC_DEBUG_8__first_quad_of_prim 0x00040000L +#define SC_DEBUG_8__sample_we_MASK 0x00080000L +#define SC_DEBUG_8__sample_we 0x00080000L +#define SC_DEBUG_8__fposition_MASK 0x00100000L +#define SC_DEBUG_8__fposition 0x00100000L +#define SC_DEBUG_8__event_id_MASK 0x03e00000L +#define SC_DEBUG_8__event_flag_MASK 0x04000000L +#define SC_DEBUG_8__event_flag 0x04000000L +#define SC_DEBUG_8__fw_prim_data_valid_MASK 0x08000000L +#define SC_DEBUG_8__fw_prim_data_valid 0x08000000L +#define SC_DEBUG_8__trigger_MASK 0x80000000L +#define SC_DEBUG_8__trigger 0x80000000L + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send_MASK 0x00000001L +#define SC_DEBUG_9__rb_sc_send 0x00000001L +#define SC_DEBUG_9__rb_sc_ez_mask_MASK 0x0000001eL +#define SC_DEBUG_9__fifo_data_ready_MASK 0x00000020L +#define SC_DEBUG_9__fifo_data_ready 0x00000020L +#define SC_DEBUG_9__early_z_enable_MASK 0x00000040L +#define SC_DEBUG_9__early_z_enable 0x00000040L +#define SC_DEBUG_9__mask_state_MASK 0x00000180L +#define SC_DEBUG_9__next_ez_mask_MASK 0x01fffe00L +#define SC_DEBUG_9__mask_ready_MASK 0x02000000L +#define SC_DEBUG_9__mask_ready 0x02000000L +#define SC_DEBUG_9__drop_sample_MASK 0x04000000L +#define SC_DEBUG_9__drop_sample 0x04000000L +#define SC_DEBUG_9__fetch_new_sample_data_MASK 0x08000000L +#define SC_DEBUG_9__fetch_new_sample_data 0x08000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK 0x10000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask 0x10000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK 0x40000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data 0x40000000L +#define SC_DEBUG_9__trigger_MASK 0x80000000L +#define SC_DEBUG_9__trigger 0x80000000L + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask_MASK 0x0000ffffL +#define SC_DEBUG_10__trigger_MASK 0x80000000L +#define SC_DEBUG_10__trigger 0x80000000L + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready_MASK 0x00000001L +#define SC_DEBUG_11__ez_sample_data_ready 0x00000001L +#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK 0x00000002L +#define SC_DEBUG_11__pkr_fetch_new_sample_data 0x00000002L +#define SC_DEBUG_11__ez_prim_data_ready_MASK 0x00000004L +#define SC_DEBUG_11__ez_prim_data_ready 0x00000004L +#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK 0x00000008L +#define SC_DEBUG_11__pkr_fetch_new_prim_data 0x00000008L +#define SC_DEBUG_11__iterator_input_fz_MASK 0x00000010L +#define SC_DEBUG_11__iterator_input_fz 0x00000010L +#define SC_DEBUG_11__packer_send_quads_MASK 0x00000020L +#define SC_DEBUG_11__packer_send_quads 0x00000020L +#define SC_DEBUG_11__packer_send_cmd_MASK 0x00000040L +#define SC_DEBUG_11__packer_send_cmd 0x00000040L +#define SC_DEBUG_11__packer_send_event_MASK 0x00000080L +#define SC_DEBUG_11__packer_send_event 0x00000080L +#define SC_DEBUG_11__next_state_MASK 0x00000700L +#define SC_DEBUG_11__state_MASK 0x00003800L +#define SC_DEBUG_11__stall_MASK 0x00004000L +#define SC_DEBUG_11__stall 0x00004000L +#define SC_DEBUG_11__trigger_MASK 0x80000000L +#define SC_DEBUG_11__trigger 0x80000000L + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff_MASK 0x00000001L +#define SC_DEBUG_12__SQ_iterator_free_buff 0x00000001L +#define SC_DEBUG_12__event_id_MASK 0x0000003eL +#define SC_DEBUG_12__event_flag_MASK 0x00000040L +#define SC_DEBUG_12__event_flag 0x00000040L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK 0x00000080L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly 0x00000080L +#define SC_DEBUG_12__itercmdfifo_full_MASK 0x00000100L +#define SC_DEBUG_12__itercmdfifo_full 0x00000100L +#define SC_DEBUG_12__itercmdfifo_empty_MASK 0x00000200L +#define SC_DEBUG_12__itercmdfifo_empty 0x00000200L +#define SC_DEBUG_12__iter_ds_one_clk_command_MASK 0x00000400L +#define SC_DEBUG_12__iter_ds_one_clk_command 0x00000400L +#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_prim0 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_vector_MASK 0x00001000L +#define SC_DEBUG_12__iter_ds_end_of_vector 0x00001000L +#define SC_DEBUG_12__iter_qdhit0_MASK 0x00002000L +#define SC_DEBUG_12__iter_qdhit0 0x00002000L +#define SC_DEBUG_12__bc_use_centers_reg_MASK 0x00004000L +#define SC_DEBUG_12__bc_use_centers_reg 0x00004000L +#define SC_DEBUG_12__bc_output_xy_reg_MASK 0x00008000L +#define SC_DEBUG_12__bc_output_xy_reg 0x00008000L +#define SC_DEBUG_12__iter_phase_out_MASK 0x00030000L +#define SC_DEBUG_12__iter_phase_reg_MASK 0x000c0000L +#define SC_DEBUG_12__iterator_SP_valid_MASK 0x00100000L +#define SC_DEBUG_12__iterator_SP_valid 0x00100000L +#define SC_DEBUG_12__eopv_reg_MASK 0x00200000L +#define SC_DEBUG_12__eopv_reg 0x00200000L +#define SC_DEBUG_12__one_clk_cmd_reg_MASK 0x00400000L +#define SC_DEBUG_12__one_clk_cmd_reg 0x00400000L +#define SC_DEBUG_12__iter_dx_end_of_prim_MASK 0x00800000L +#define SC_DEBUG_12__iter_dx_end_of_prim 0x00800000L +#define SC_DEBUG_12__trigger_MASK 0x80000000L +#define SC_DEBUG_12__trigger 0x80000000L + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define GFX_COPY_STATE__SRC_STATE_ID 0x00000001L + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK 0x0000003fL +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x000000c0L +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK 0x00000300L +#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK 0x00000800L +#define VGT_DRAW_INITIATOR__INDEX_SIZE 0x00000800L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00001000L +#define VGT_DRAW_INITIATOR__NOT_EOP 0x00001000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK 0x00002000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX 0x00002000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK 0x00004000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE 0x00004000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK 0x00008000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE 0x00008000L +#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK 0xffff0000L + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_DMA_SIZE__SWAP_MODE_MASK 0xc0000000L + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK 0xffffffffL + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_BIN_SIZE__FACENESS_FETCH_MASK 0x40000000L +#define VGT_BIN_SIZE__FACENESS_FETCH 0x40000000L +#define VGT_BIN_SIZE__FACENESS_RESET_MASK 0x80000000L +#define VGT_BIN_SIZE__FACENESS_RESET 0x80000000L + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK 0x000001c0L + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK 0x000001c0L + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0x00ffffffL + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0x00ffffffL + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0x00ffffffL + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x00000007L + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x00000003L + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0x00ffffffL + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC_MASK 0x0000ffffL + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000001fL + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define VGT_LAST_COPY_STATE__SRC_STATE_ID 0x00000001L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00010000L +#define VGT_LAST_COPY_STATE__DST_STATE_ID 0x00010000L + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000001fL + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_BUSY 0x00000001L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY 0x00000004L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY 0x00000008L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY 0x00000010L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY 0x00000020L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_PT_BUSY 0x00000040L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY 0x00000100L + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy_MASK 0x00000001L +#define VGT_DEBUG_REG0__te_grp_busy 0x00000001L +#define VGT_DEBUG_REG0__pt_grp_busy_MASK 0x00000002L +#define VGT_DEBUG_REG0__pt_grp_busy 0x00000002L +#define VGT_DEBUG_REG0__vr_grp_busy_MASK 0x00000004L +#define VGT_DEBUG_REG0__vr_grp_busy 0x00000004L +#define VGT_DEBUG_REG0__dma_request_busy_MASK 0x00000008L +#define VGT_DEBUG_REG0__dma_request_busy 0x00000008L +#define VGT_DEBUG_REG0__out_busy_MASK 0x00000010L +#define VGT_DEBUG_REG0__out_busy 0x00000010L +#define VGT_DEBUG_REG0__grp_backend_busy_MASK 0x00000020L +#define VGT_DEBUG_REG0__grp_backend_busy 0x00000020L +#define VGT_DEBUG_REG0__grp_busy_MASK 0x00000040L +#define VGT_DEBUG_REG0__grp_busy 0x00000040L +#define VGT_DEBUG_REG0__dma_busy_MASK 0x00000080L +#define VGT_DEBUG_REG0__dma_busy 0x00000080L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK 0x00000100L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy 0x00000100L +#define VGT_DEBUG_REG0__rbiu_busy_MASK 0x00000200L +#define VGT_DEBUG_REG0__rbiu_busy 0x00000200L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK 0x00000800L +#define VGT_DEBUG_REG0__vgt_no_dma_busy 0x00000800L +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_extended 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00002000L +#define VGT_DEBUG_REG0__vgt_busy 0x00002000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK 0x00004000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out 0x00004000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK 0x00010000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy 0x00010000L + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read_MASK 0x00000001L +#define VGT_DEBUG_REG1__out_te_data_read 0x00000001L +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x00000002L +#define VGT_DEBUG_REG1__te_out_data_valid 0x00000002L +#define VGT_DEBUG_REG1__out_pt_prim_read_MASK 0x00000004L +#define VGT_DEBUG_REG1__out_pt_prim_read 0x00000004L +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00000008L +#define VGT_DEBUG_REG1__pt_out_prim_valid 0x00000008L +#define VGT_DEBUG_REG1__out_pt_data_read_MASK 0x00000010L +#define VGT_DEBUG_REG1__out_pt_data_read 0x00000010L +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00000020L +#define VGT_DEBUG_REG1__pt_out_indx_valid 0x00000020L +#define VGT_DEBUG_REG1__out_vr_prim_read_MASK 0x00000040L +#define VGT_DEBUG_REG1__out_vr_prim_read 0x00000040L +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00000080L +#define VGT_DEBUG_REG1__vr_out_prim_valid 0x00000080L +#define VGT_DEBUG_REG1__out_vr_indx_read_MASK 0x00000100L +#define VGT_DEBUG_REG1__out_vr_indx_read 0x00000100L +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00000200L +#define VGT_DEBUG_REG1__vr_out_indx_valid 0x00000200L +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00000400L +#define VGT_DEBUG_REG1__te_grp_read 0x00000400L +#define VGT_DEBUG_REG1__grp_te_valid_MASK 0x00000800L +#define VGT_DEBUG_REG1__grp_te_valid 0x00000800L +#define VGT_DEBUG_REG1__pt_grp_read_MASK 0x00001000L +#define VGT_DEBUG_REG1__pt_grp_read 0x00001000L +#define VGT_DEBUG_REG1__grp_pt_valid_MASK 0x00002000L +#define VGT_DEBUG_REG1__grp_pt_valid 0x00002000L +#define VGT_DEBUG_REG1__vr_grp_read_MASK 0x00004000L +#define VGT_DEBUG_REG1__vr_grp_read 0x00004000L +#define VGT_DEBUG_REG1__grp_vr_valid_MASK 0x00008000L +#define VGT_DEBUG_REG1__grp_vr_valid 0x00008000L +#define VGT_DEBUG_REG1__grp_dma_read_MASK 0x00010000L +#define VGT_DEBUG_REG1__grp_dma_read 0x00010000L +#define VGT_DEBUG_REG1__dma_grp_valid_MASK 0x00020000L +#define VGT_DEBUG_REG1__dma_grp_valid 0x00020000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK 0x00040000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read 0x00040000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK 0x00080000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid 0x00080000L +#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG1__MH_VGT_rtr 0x00100000L +#define VGT_DEBUG_REG1__VGT_MH_send_MASK 0x00200000L +#define VGT_DEBUG_REG1__VGT_MH_send 0x00200000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK 0x00400000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr 0x00400000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK 0x00800000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send 0x00800000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr 0x01000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK 0x02000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send 0x02000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr 0x04000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK 0x08000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send 0x08000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr 0x10000000L +#define VGT_DEBUG_REG1__VGT_SQ_send_MASK 0x20000000L +#define VGT_DEBUG_REG1__VGT_SQ_send 0x20000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK 0x40000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q 0x40000000L + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en_MASK 0x00000001L +#define VGT_DEBUG_REG3__vgt_clk_en 0x00000001L +#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK 0x00000002L +#define VGT_DEBUG_REG3__reg_fifos_clk_en 0x00000002L + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG6__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG6__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG6__input_data_valid 0x00000400L +#define VGT_DEBUG_REG6__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG6__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG6__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG6__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG6__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG6__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG6__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG6__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG6__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG6__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG6__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG6__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG6__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG6__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG6__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG6__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG6__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG6__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG6__extract_vector 0x02000000L +#define VGT_DEBUG_REG6__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG6__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG6__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG6__destination_rtr 0x08000000L +#define VGT_DEBUG_REG6__grp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG6__grp_trigger 0x10000000L + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG7__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG7__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG7__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG8__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG8__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG8__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG8__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG9__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG9__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG9__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG9__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG9__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG9__grp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG9__grp_trigger 0x40000000L + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L +#define VGT_DEBUG_REG10__di_state_sel_q_MASK 0x00000010L +#define VGT_DEBUG_REG10__di_state_sel_q 0x00000010L +#define VGT_DEBUG_REG10__last_decr_of_packet_MASK 0x00000020L +#define VGT_DEBUG_REG10__last_decr_of_packet 0x00000020L +#define VGT_DEBUG_REG10__bin_valid_MASK 0x00000040L +#define VGT_DEBUG_REG10__bin_valid 0x00000040L +#define VGT_DEBUG_REG10__read_block_MASK 0x00000080L +#define VGT_DEBUG_REG10__read_block 0x00000080L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK 0x00000100L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read 0x00000100L +#define VGT_DEBUG_REG10__last_bit_enable_q_MASK 0x00000200L +#define VGT_DEBUG_REG10__last_bit_enable_q 0x00000200L +#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK 0x00000400L +#define VGT_DEBUG_REG10__last_bit_end_di_q 0x00000400L +#define VGT_DEBUG_REG10__selected_data_MASK 0x0007f800L +#define VGT_DEBUG_REG10__mask_input_data_MASK 0x07f80000L +#define VGT_DEBUG_REG10__gap_q_MASK 0x08000000L +#define VGT_DEBUG_REG10__gap_q 0x08000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK 0x40000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x 0x40000000L +#define VGT_DEBUG_REG10__grp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG10__grp_trigger 0x80000000L + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG12__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG12__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG12__input_data_valid 0x00000400L +#define VGT_DEBUG_REG12__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG12__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG12__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG12__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG12__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG12__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG12__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG12__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG12__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG12__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG12__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG12__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG12__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG12__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG12__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG12__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG12__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG12__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG12__extract_vector 0x02000000L +#define VGT_DEBUG_REG12__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG12__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG12__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG12__destination_rtr 0x08000000L +#define VGT_DEBUG_REG12__bgrp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG12__bgrp_trigger 0x10000000L + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG13__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG13__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG13__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG14__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG14__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG14__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG14__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG15__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG15__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG15__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG15__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG15__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG15__bgrp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG15__bgrp_trigger 0x40000000L + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty 0x00000002L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK 0x00000004L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read 0x00000004L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we 0x00000008L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK 0x00000080L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we 0x00000080L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK 0x00000100L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill 0x00000100L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK 0x00000200L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid 0x00000200L +#define VGT_DEBUG_REG16__rst_last_bit_MASK 0x00000400L +#define VGT_DEBUG_REG16__rst_last_bit 0x00000400L +#define VGT_DEBUG_REG16__current_state_q_MASK 0x00000800L +#define VGT_DEBUG_REG16__current_state_q 0x00000800L +#define VGT_DEBUG_REG16__old_state_q_MASK 0x00001000L +#define VGT_DEBUG_REG16__old_state_q 0x00001000L +#define VGT_DEBUG_REG16__old_state_en_MASK 0x00002000L +#define VGT_DEBUG_REG16__old_state_en 0x00002000L +#define VGT_DEBUG_REG16__prev_last_bit_q_MASK 0x00004000L +#define VGT_DEBUG_REG16__prev_last_bit_q 0x00004000L +#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK 0x00008000L +#define VGT_DEBUG_REG16__dbl_last_bit_q 0x00008000L +#define VGT_DEBUG_REG16__last_bit_block_q_MASK 0x00010000L +#define VGT_DEBUG_REG16__last_bit_block_q 0x00010000L +#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK 0x00020000L +#define VGT_DEBUG_REG16__ast_bit_block2_q 0x00020000L +#define VGT_DEBUG_REG16__load_empty_reg_MASK 0x00040000L +#define VGT_DEBUG_REG16__load_empty_reg 0x00040000L +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK 0x07f80000L +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable 0x20000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK 0x40000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q 0x40000000L +#define VGT_DEBUG_REG16__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG16__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q_MASK 0x00000001L +#define VGT_DEBUG_REG17__save_read_q 0x00000001L +#define VGT_DEBUG_REG17__extend_read_q_MASK 0x00000002L +#define VGT_DEBUG_REG17__extend_read_q 0x00000002L +#define VGT_DEBUG_REG17__grp_indx_size_MASK 0x0000000cL +#define VGT_DEBUG_REG17__cull_prim_true_MASK 0x00000010L +#define VGT_DEBUG_REG17__cull_prim_true 0x00000010L +#define VGT_DEBUG_REG17__reset_bit2_q_MASK 0x00000020L +#define VGT_DEBUG_REG17__reset_bit2_q 0x00000020L +#define VGT_DEBUG_REG17__reset_bit1_q_MASK 0x00000040L +#define VGT_DEBUG_REG17__reset_bit1_q 0x00000040L +#define VGT_DEBUG_REG17__first_reg_first_q_MASK 0x00000080L +#define VGT_DEBUG_REG17__first_reg_first_q 0x00000080L +#define VGT_DEBUG_REG17__check_second_reg_MASK 0x00000100L +#define VGT_DEBUG_REG17__check_second_reg 0x00000100L +#define VGT_DEBUG_REG17__check_first_reg_MASK 0x00000200L +#define VGT_DEBUG_REG17__check_first_reg 0x00000200L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK 0x00000400L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata 0x00000400L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK 0x00001000L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q 0x00001000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK 0x00004000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q 0x00004000L +#define VGT_DEBUG_REG17__to_second_reg_q_MASK 0x00008000L +#define VGT_DEBUG_REG17__to_second_reg_q 0x00008000L +#define VGT_DEBUG_REG17__roll_over_msk_q_MASK 0x00010000L +#define VGT_DEBUG_REG17__roll_over_msk_q 0x00010000L +#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK 0x00fe0000L +#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK 0x7f000000L +#define VGT_DEBUG_REG17__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG17__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK 0x0000003fL +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK 0x00000fc0L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000L +#define VGT_DEBUG_REG18__dma_mem_full_MASK 0x00008000L +#define VGT_DEBUG_REG18__dma_mem_full 0x00008000L +#define VGT_DEBUG_REG18__dma_ram_re_MASK 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_re 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_we_MASK 0x00020000L +#define VGT_DEBUG_REG18__dma_ram_we 0x00020000L +#define VGT_DEBUG_REG18__dma_mem_empty_MASK 0x00040000L +#define VGT_DEBUG_REG18__dma_mem_empty 0x00040000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK 0x00100000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we 0x00100000L +#define VGT_DEBUG_REG18__bin_mem_full_MASK 0x00200000L +#define VGT_DEBUG_REG18__bin_mem_full 0x00200000L +#define VGT_DEBUG_REG18__bin_ram_we_MASK 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_we 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_re_MASK 0x00800000L +#define VGT_DEBUG_REG18__bin_ram_re 0x00800000L +#define VGT_DEBUG_REG18__bin_mem_empty_MASK 0x01000000L +#define VGT_DEBUG_REG18__bin_mem_empty 0x01000000L +#define VGT_DEBUG_REG18__start_bin_req_MASK 0x02000000L +#define VGT_DEBUG_REG18__start_bin_req 0x02000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK 0x04000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used 0x04000000L +#define VGT_DEBUG_REG18__dma_req_xfer_MASK 0x08000000L +#define VGT_DEBUG_REG18__dma_req_xfer 0x08000000L +#define VGT_DEBUG_REG18__have_valid_bin_req_MASK 0x10000000L +#define VGT_DEBUG_REG18__have_valid_bin_req 0x10000000L +#define VGT_DEBUG_REG18__have_valid_dma_req_MASK 0x20000000L +#define VGT_DEBUG_REG18__have_valid_dma_req 0x20000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK 0x00000001L +#define VGT_DEBUG_REG20__prim_side_indx_valid 0x00000001L +#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_empty 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_re 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_we 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG20__indx_side_fifo_full 0x00000010L +#define VGT_DEBUG_REG20__prim_buffer_empty_MASK 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_empty 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_re_MASK 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_re 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_we_MASK 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_we 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_full_MASK 0x00000100L +#define VGT_DEBUG_REG20__prim_buffer_full 0x00000100L +#define VGT_DEBUG_REG20__indx_buffer_empty_MASK 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_empty 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_re_MASK 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_re 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_we_MASK 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_we 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_full_MASK 0x00001000L +#define VGT_DEBUG_REG20__indx_buffer_full 0x00001000L +#define VGT_DEBUG_REG20__hold_prim_MASK 0x00002000L +#define VGT_DEBUG_REG20__hold_prim 0x00002000L +#define VGT_DEBUG_REG20__sent_cnt_MASK 0x0003c000L +#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK 0x00040000L +#define VGT_DEBUG_REG20__start_of_vtx_vector 0x00040000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK 0x00080000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim 0x00080000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK 0x00100000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim 0x00100000L +#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK 0x03e00000L +#define VGT_DEBUG_REG20__out_trigger_MASK 0x04000000L +#define VGT_DEBUG_REG20__out_trigger 0x04000000L + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK 0x00000001L +#define VGT_DEBUG_REG21__null_terminate_vtx_vector 0x00000001L +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK 0x0000000eL +#define VGT_DEBUG_REG21__alloc_counter_q_MASK 0x00000070L +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK 0x00000380L +#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK 0x00003c00L +#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK 0x0003c000L +#define VGT_DEBUG_REG21__new_packet_q_MASK 0x00040000L +#define VGT_DEBUG_REG21__new_packet_q 0x00040000L +#define VGT_DEBUG_REG21__new_allocate_q_MASK 0x00080000L +#define VGT_DEBUG_REG21__new_allocate_q 0x00080000L +#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK 0x00300000L +#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK 0x00400000L +#define VGT_DEBUG_REG21__inserted_null_prim_q 0x00400000L +#define VGT_DEBUG_REG21__insert_null_prim_MASK 0x00800000L +#define VGT_DEBUG_REG21__insert_null_prim 0x00800000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK 0x01000000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux 0x01000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK 0x02000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux 0x02000000L +#define VGT_DEBUG_REG21__buffered_thread_size_MASK 0x04000000L +#define VGT_DEBUG_REG21__buffered_thread_size 0x04000000L +#define VGT_DEBUG_REG21__out_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG21__out_trigger 0x80000000L + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC_MASK 0xffffffffL + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE_MASK 0x00000001L +#define TC_CNTL_STATUS__L2_INVALIDATE 0x00000001L +#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK 0x000c0000L +#define TC_CNTL_STATUS__TC_BUSY_MASK 0x80000000L +#define TC_CNTL_STATUS__TC_BUSY 0x80000000L + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE_MASK 0xffffffffL + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE_MASK 0xffffffffL + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL +#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK 0x00000100L +#define TCM_CHICKEN__ETC_COLOR_ENDIAN 0x00000100L +#define TCM_CHICKEN__SPARE_MASK 0xfffffe00L + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK 0x00000007L +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK 0x00000038L + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK 0x00000001L +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY 0x00000001L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK 0x00000002L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY 0x00000002L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK 0x00000004L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY 0x00000004L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK 0x00000008L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY 0x00000008L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK 0x00000040L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY 0x00000040L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK 0x00000400L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY 0x00000400L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK 0x00001000L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY 0x00001000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK 0x00002000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY 0x00002000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK 0x00004000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY 0x00004000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK 0x00008000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY 0x00008000L +#define TPC_CNTL_STATUS__TF_TW_RTS_MASK 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_RTS 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_RTR_MASK 0x00080000L +#define TPC_CNTL_STATUS__TF_TW_RTR 0x00080000L +#define TPC_CNTL_STATUS__TW_TA_RTS_MASK 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_RTS 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_RTR_MASK 0x00800000L +#define TPC_CNTL_STATUS__TW_TA_RTR 0x00800000L +#define TPC_CNTL_STATUS__TA_TB_RTS_MASK 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_RTS 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_RTR_MASK 0x08000000L +#define TPC_CNTL_STATUS__TA_TB_RTR 0x08000000L +#define TPC_CNTL_STATUS__TA_TF_RTS_MASK 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_RTS 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK 0x20000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN 0x20000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK 0x40000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC 0x40000000L +#define TPC_CNTL_STATUS__TPC_BUSY_MASK 0x80000000L +#define TPC_CNTL_STATUS__TPC_BUSY 0x80000000L + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL_MASK 0x00000003L +#define TPC_DEBUG0__IC_CTR_MASK 0x0000000cL +#define TPC_DEBUG0__WALKER_CNTL_MASK 0x000000f0L +#define TPC_DEBUG0__ALIGNER_CNTL_MASK 0x00000700L +#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK 0x00001000L +#define TPC_DEBUG0__PREV_TC_STATE_VALID 0x00001000L +#define TPC_DEBUG0__WALKER_STATE_MASK 0x03ff0000L +#define TPC_DEBUG0__ALIGNER_STATE_MASK 0x0c000000L +#define TPC_DEBUG0__REG_CLK_EN_MASK 0x20000000L +#define TPC_DEBUG0__REG_CLK_EN 0x20000000L +#define TPC_DEBUG0__TPC_CLK_EN_MASK 0x40000000L +#define TPC_DEBUG0__TPC_CLK_EN 0x40000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK 0x80000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP 0x80000000L + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED_MASK 0x00000001L +#define TPC_DEBUG1__UNUSED 0x00000001L + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION_MASK 0x00000001L +#define TPC_CHICKEN__BLEND_PRECISION 0x00000001L +#define TPC_CHICKEN__SPARE_MASK 0xfffffffeL + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK 0x00000001L +#define TP0_CNTL_STATUS__TP_INPUT_BUSY 0x00000001L +#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_BUSY 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK 0x00000004L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY 0x00000004L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK 0x00000008L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY 0x00000008L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK 0x00000020L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY 0x00000020L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK 0x00000040L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY 0x00000040L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK 0x00000080L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY 0x00000080L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK 0x00000100L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY 0x00000100L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK 0x00000200L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY 0x00000200L +#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK 0x00000400L +#define TP0_CNTL_STATUS__TP_TT_BUSY 0x00000400L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK 0x00000800L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY 0x00000800L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK 0x00001000L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY 0x00001000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK 0x00002000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY 0x00002000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK 0x00004000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY 0x00004000L +#define TP0_CNTL_STATUS__IN_LC_RTS_MASK 0x00010000L +#define TP0_CNTL_STATUS__IN_LC_RTS 0x00010000L +#define TP0_CNTL_STATUS__LC_LA_RTS_MASK 0x00020000L +#define TP0_CNTL_STATUS__LC_LA_RTS 0x00020000L +#define TP0_CNTL_STATUS__LA_FL_RTS_MASK 0x00040000L +#define TP0_CNTL_STATUS__LA_FL_RTS 0x00040000L +#define TP0_CNTL_STATUS__FL_TA_RTS_MASK 0x00080000L +#define TP0_CNTL_STATUS__FL_TA_RTS 0x00080000L +#define TP0_CNTL_STATUS__TA_FA_RTS_MASK 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_RTS 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK 0x00200000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS 0x00200000L +#define TP0_CNTL_STATUS__FA_AL_RTS_MASK 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_RTS 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK 0x00800000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS 0x00800000L +#define TP0_CNTL_STATUS__AL_TF_RTS_MASK 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_RTS 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK 0x02000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS 0x02000000L +#define TP0_CNTL_STATUS__TF_TB_RTS_MASK 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_RTS 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK 0x08000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS 0x08000000L +#define TP0_CNTL_STATUS__TB_TT_RTS_MASK 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_RTS 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK 0x20000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET 0x20000000L +#define TP0_CNTL_STATUS__TB_TO_RTS_MASK 0x40000000L +#define TP0_CNTL_STATUS__TB_TO_RTS 0x40000000L +#define TP0_CNTL_STATUS__TP_BUSY_MASK 0x80000000L +#define TP0_CNTL_STATUS__TP_BUSY 0x80000000L + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL_MASK 0x00000003L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK 0x00000008L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP 0x00000008L +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0L +#define TP0_DEBUG__REG_CLK_EN_MASK 0x00200000L +#define TP0_DEBUG__REG_CLK_EN 0x00200000L +#define TP0_DEBUG__PERF_CLK_EN_MASK 0x00400000L +#define TP0_DEBUG__PERF_CLK_EN 0x00400000L +#define TP0_DEBUG__TP_CLK_EN_MASK 0x00800000L +#define TP0_DEBUG__TP_CLK_EN 0x00800000L +#define TP0_DEBUG__Q_WALKER_CNTL_MASK 0x0f000000L +#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK 0x70000000L + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE_MASK 0x00000001L +#define TP0_CHICKEN__TT_MODE 0x00000001L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK 0x00000002L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE 0x00000002L +#define TP0_CHICKEN__SPARE_MASK 0xfffffffcL + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr_MASK 0x00000040L +#define TCF_DEBUG__not_MH_TC_rtr 0x00000040L +#define TCF_DEBUG__TC_MH_send_MASK 0x00000080L +#define TCF_DEBUG__TC_MH_send 0x00000080L +#define TCF_DEBUG__not_FG0_rtr_MASK 0x00000100L +#define TCF_DEBUG__not_FG0_rtr 0x00000100L +#define TCF_DEBUG__not_TCB_TCO_rtr_MASK 0x00001000L +#define TCF_DEBUG__not_TCB_TCO_rtr 0x00001000L +#define TCF_DEBUG__TCB_ff_stall_MASK 0x00002000L +#define TCF_DEBUG__TCB_ff_stall 0x00002000L +#define TCF_DEBUG__TCB_miss_stall_MASK 0x00004000L +#define TCF_DEBUG__TCB_miss_stall 0x00004000L +#define TCF_DEBUG__TCA_TCB_stall_MASK 0x00008000L +#define TCF_DEBUG__TCA_TCB_stall 0x00008000L +#define TCF_DEBUG__PF0_stall_MASK 0x00010000L +#define TCF_DEBUG__PF0_stall 0x00010000L +#define TCF_DEBUG__TP0_full_MASK 0x00100000L +#define TCF_DEBUG__TP0_full 0x00100000L +#define TCF_DEBUG__TPC_full_MASK 0x01000000L +#define TCF_DEBUG__TPC_full 0x01000000L +#define TCF_DEBUG__not_TPC_rtr_MASK 0x02000000L +#define TCF_DEBUG__not_TPC_rtr 0x02000000L +#define TCF_DEBUG__tca_state_rts_MASK 0x04000000L +#define TCF_DEBUG__tca_state_rts 0x04000000L +#define TCF_DEBUG__tca_rts_MASK 0x08000000L +#define TCF_DEBUG__tca_rts 0x08000000L + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full_MASK 0x00000001L +#define TCA_FIFO_DEBUG__tp0_full 0x00000001L +#define TCA_FIFO_DEBUG__tpc_full_MASK 0x00000010L +#define TCA_FIFO_DEBUG__tpc_full 0x00000010L +#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK 0x00000020L +#define TCA_FIFO_DEBUG__load_tpc_fifo 0x00000020L +#define TCA_FIFO_DEBUG__load_tp_fifos_MASK 0x00000040L +#define TCA_FIFO_DEBUG__load_tp_fifos 0x00000040L +#define TCA_FIFO_DEBUG__FW_full_MASK 0x00000080L +#define TCA_FIFO_DEBUG__FW_full 0x00000080L +#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK 0x00000100L +#define TCA_FIFO_DEBUG__not_FW_rtr0 0x00000100L +#define TCA_FIFO_DEBUG__FW_rts0_MASK 0x00001000L +#define TCA_FIFO_DEBUG__FW_rts0 0x00001000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK 0x00010000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr 0x00010000L +#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK 0x00020000L +#define TCA_FIFO_DEBUG__FW_tpc_rts 0x00020000L + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK 0x00000001L +#define TCA_PROBE_DEBUG__ProbeFilter_stall 0x00000001L + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts_MASK 0x00001000L +#define TCA_TPC_DEBUG__captue_state_rts 0x00001000L +#define TCA_TPC_DEBUG__capture_tca_rts_MASK 0x00002000L +#define TCA_TPC_DEBUG__capture_tca_rts 0x00002000L + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512_MASK 0x00000001L +#define TCB_CORE_DEBUG__access512 0x00000001L +#define TCB_CORE_DEBUG__tiled_MASK 0x00000002L +#define TCB_CORE_DEBUG__tiled 0x00000002L +#define TCB_CORE_DEBUG__opcode_MASK 0x00000070L +#define TCB_CORE_DEBUG__format_MASK 0x00003f00L +#define TCB_CORE_DEBUG__sector_format_MASK 0x001f0000L +#define TCB_CORE_DEBUG__sector_format512_MASK 0x07000000L + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG0_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG0_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG0_DEBUG__miss_stall 0x00800000L +#define TCB_TAG0_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG0_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG1_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG1_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG1_DEBUG__miss_stall 0x00800000L +#define TCB_TAG1_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG1_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG2_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG2_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG2_DEBUG__miss_stall 0x00800000L +#define TCB_TAG2_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG2_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG3_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG3_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG3_DEBUG__miss_stall 0x00800000L +#define TCB_TAG3_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG3_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q 0x10000000L + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK 0x00000030L +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK 0x000000c0L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK 0x00007000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK 0x000f0000L + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK 0x0000fff0L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK 0x001f0000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK 0x0c000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK 0x40000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR 0x40000000L + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty_MASK 0x00010000L +#define TCD_INPUT0_DEBUG__empty 0x00010000L +#define TCD_INPUT0_DEBUG__full_MASK 0x00020000L +#define TCD_INPUT0_DEBUG__full 0x00020000L +#define TCD_INPUT0_DEBUG__valid_q1_MASK 0x00100000L +#define TCD_INPUT0_DEBUG__valid_q1 0x00100000L +#define TCD_INPUT0_DEBUG__cnt_q1_MASK 0x00600000L +#define TCD_INPUT0_DEBUG__last_send_q1_MASK 0x00800000L +#define TCD_INPUT0_DEBUG__last_send_q1 0x00800000L +#define TCD_INPUT0_DEBUG__ip_send_MASK 0x01000000L +#define TCD_INPUT0_DEBUG__ip_send 0x01000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK 0x04000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy 0x04000000L + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK 0x00000003L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_stall 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK 0x00000040L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate 0x00000040L + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__pstate 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK 0x20000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send 0x20000000L + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK 0x00000010L +#define TCD_DXTC_ARB_DEBUG__n0_stall 0x00000010L +#define TCD_DXTC_ARB_DEBUG__pstate_MASK 0x00000020L +#define TCD_DXTC_ARB_DEBUG__pstate 0x00000020L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK 0x00000180L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK 0x00000e00L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK 0x0003f000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK 0x3ffc0000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK 0x40000000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send 0x40000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK 0x80000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types 0x80000000L + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK 0x00000400L +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr 0x00000400L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK 0x00000800L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr 0x00000800L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK 0x00020000L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr 0x00020000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK 0x00040000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr 0x00040000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK 0x00080000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr 0x00080000L +#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK 0x80000000L +#define TCD_STALLS_DEBUG__not_incoming_rtr 0x80000000L + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK 0x00000020L +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR 0x00000020L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK 0x00000040L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR 0x00000040L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK 0x00000080L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d 0x00000080L + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK 0x000000ffL +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK 0x00000400L +#define TCO_QUAD0_DEBUG0__rl_sg_rts 0x00000400L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK 0x00002000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts 0x00002000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK 0x00010000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q 0x00010000L +#define TCO_QUAD0_DEBUG0__read_cache_q_MASK 0x01000000L +#define TCO_QUAD0_DEBUG0__read_cache_q 0x01000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK 0x02000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR 0x02000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK 0x20000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0 0x20000000L +#define TCO_QUAD0_DEBUG0__busy_MASK 0x40000000L +#define TCO_QUAD0_DEBUG0__busy 0x40000000L + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy_MASK 0x00000001L +#define TCO_QUAD0_DEBUG1__fifo_busy 0x00000001L +#define TCO_QUAD0_DEBUG1__empty_MASK 0x00000002L +#define TCO_QUAD0_DEBUG1__empty 0x00000002L +#define TCO_QUAD0_DEBUG1__full_MASK 0x00000004L +#define TCO_QUAD0_DEBUG1__full 0x00000004L +#define TCO_QUAD0_DEBUG1__write_enable_MASK 0x00000008L +#define TCO_QUAD0_DEBUG1__write_enable 0x00000008L +#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK 0x000007f0L +#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK 0x0003f800L +#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK 0x00100000L +#define TCO_QUAD0_DEBUG1__cache_read_busy 0x00100000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK 0x00200000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy 0x00200000L +#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK 0x00400000L +#define TCO_QUAD0_DEBUG1__input_quad_busy 0x00400000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK 0x00800000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy 0x00800000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK 0x02000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q 0x02000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK 0x08000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts 0x08000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK 0x20000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts 0x20000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK 0x40000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc 0x40000000L + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK 0x000007f0L +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK 0x0007f000L + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK 0x00000003L +#define SQ_FLOW_CONTROL__ONE_THREAD_MASK 0x00000010L +#define SQ_FLOW_CONTROL__ONE_THREAD 0x00000010L +#define SQ_FLOW_CONTROL__ONE_ALU_MASK 0x00000100L +#define SQ_FLOW_CONTROL__ONE_ALU 0x00000100L +#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK 0x0000f000L +#define SQ_FLOW_CONTROL__NO_PV_PS_MASK 0x00010000L +#define SQ_FLOW_CONTROL__NO_PV_PS 0x00010000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK 0x00020000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT 0x00020000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK 0x00040000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE 0x00040000L +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK 0x00180000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK 0x00200000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY 0x00200000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK 0x00400000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY 0x00400000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK 0x00800000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT 0x00800000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK 0x01000000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT 0x01000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK 0x02000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY 0x02000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK 0x04000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION 0x04000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC 0x08000000L + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK 0x00000fffL +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK 0x0fff0000L + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK 0x01ff0000L + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT_MASK 0x000000ffL +#define SQ_EO_RT__EO_TSTATE_RT_MASK 0x00ff0000L + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK 0x000007ffL +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK 0x000ff000L +#define SQ_DEBUG_MISC__DB_READ_CTX_MASK 0x00100000L +#define SQ_DEBUG_MISC__DB_READ_CTX 0x00100000L +#define SQ_DEBUG_MISC__RESERVED_MASK 0x00600000L +#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK 0x01800000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK 0x10000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3 0x10000000L + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK 0x000000ffL +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK 0x0000ff00L +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK 0x00ff0000L +#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK 0xff000000L + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK 0x000000ffL + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L +#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK 0x000c0000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK 0x00000001L +#define SQ_INT_CNTL__PS_WATCHDOG_MASK 0x00000001L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK 0x00000002L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK 0x00000002L + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK 0x00000001L +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT 0x00000001L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK 0x00000002L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT 0x00000002L + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK 0x00000001L +#define SQ_INT_ACK__PS_WATCHDOG_ACK 0x00000001L +#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK 0x00000002L +#define SQ_INT_ACK__VS_WATCHDOG_ACK 0x00000002L + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK 0x00000007L +#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK 0x00000008L +#define SQ_DEBUG_INPUT_FSM__RESERVED 0x00000008L +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK 0x000000f0L +#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK 0x00000700L +#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_INPUT_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK 0x00007000L +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK 0x000f8000L +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK 0x0ff00000L + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK 0x000000e0L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK 0x0000e000L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK 0x00030000L +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK 0x000c0000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK 0x00800000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE 0x00800000L + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP_MASK 0x00000007L +#define SQ_DEBUG_TP_FSM__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_TP_FSM__RESERVED0 0x00000008L +#define SQ_DEBUG_TP_FSM__CF_TP_MASK 0x000000f0L +#define SQ_DEBUG_TP_FSM__IF_TP_MASK 0x00000700L +#define SQ_DEBUG_TP_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_TP_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_TP_FSM__TIS_TP_MASK 0x00003000L +#define SQ_DEBUG_TP_FSM__RESERVED2_MASK 0x0000c000L +#define SQ_DEBUG_TP_FSM__GS_TP_MASK 0x00030000L +#define SQ_DEBUG_TP_FSM__RESERVED3_MASK 0x000c0000L +#define SQ_DEBUG_TP_FSM__FCR_TP_MASK 0x00300000L +#define SQ_DEBUG_TP_FSM__RESERVED4_MASK 0x00c00000L +#define SQ_DEBUG_TP_FSM__FCS_TP_MASK 0x03000000L +#define SQ_DEBUG_TP_FSM__RESERVED5_MASK 0x0c000000L +#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK 0x0000000fL +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK 0x00000ff0L +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK 0x00007000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000L + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK 0x00000001L +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER 0x00000001L +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK 0x0000001eL +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK 0x00000020L +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR 0x00000020L +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK 0x000001c0L +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK 0x00003e00L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK 0x00004000L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT 0x00004000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK 0x00008000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON 0x00008000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK 0x00010000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY 0x00010000L +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK 0x0ffe0000L + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_VTX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_VTX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_VTX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_VTX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_PIX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_PIX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_PIX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_PIX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK 0x60000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC 0x80000000L + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK 0x0000000fL +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK 0x000000f0L +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK 0x00000f00L +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK 0x0000f000L +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK 0x000f0000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK 0x00100000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL 0x00100000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK 0x00200000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q 0x00200000L + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK 0x0000ffffL + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK 0xffffffffL + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK 0x0000003fL +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK 0x00000fc0L +#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK 0x0007f000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK 0x01f80000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK 0x7e000000L +#define SQ_DEBUG_PIX_TB_0__BUSY_MASK 0x80000000L +#define SQ_DEBUG_PIX_TB_0__BUSY 0x80000000L + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL 0x00000040L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP 0x00000080L +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL 0x00004000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA 0x00008000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK 0x000f0000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK 0x00f00000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP 0x01000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK 0xfc000000L + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK 0x00000003L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK 0x0000000cL +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK 0x00000030L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK 0x000000c0L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK 0x00000300L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK 0x00000c00L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK 0x00003000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK 0x0000c000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK 0x00030000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK 0x000c0000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK 0x00300000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK 0x00c00000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK 0x04000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD 0x04000000L +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK 0x18000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR 0x20000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS 0x80000000L + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C 0x00000080L +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B 0x00008000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK 0x003f0000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK 0x00800000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A 0x00800000L +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK 0x1f000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK 0x000001ffL +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK 0x00000e00L +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK 0x00007000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK 0x01ff0000L +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK 0x0e000000L +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK 0x70000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK 0x0000fc00L +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK 0x001f0000L +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK 0xffe00000L + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK 0x000007ffL +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK 0xfc000000L + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK 0x0000001fL +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK 0x07ffffe0L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK 0x00001c00L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK 0xffff8000L + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK 0x1c000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK 0xc0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK 0x0001ffffL +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK 0x0000000fL +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK 0xfffffff0L + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK 0x000000ffL +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK 0x00000600L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK 0x000f0000L +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK 0xfff00000L + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK 0x00ffffffL +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK 0x06000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK 0x30000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK 0xc0000000L + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK 0x00003000L +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK 0x0000c000L +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK 0x00030000L +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK 0x001c0000L +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK 0x00e00000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK 0x03000000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK 0x60000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK 0x000001fcL +#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK 0x0000fe00L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK 0x001f0000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK 0x03e00000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK 0x7c000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK 0x06000000L +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK 0xc0000000L + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK 0x003f0000L +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK 0x3f800000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK 0x000000ffL +#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK 0x00ff0000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE_MASK 0x00000001L +#define SQ_CONSTANT_VFETCH_0__TYPE 0x00000001L +#define SQ_CONSTANT_VFETCH_0__STATE_MASK 0x00000002L +#define SQ_CONSTANT_VFETCH_0__STATE 0x00000002L +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK 0x00000003L +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE_MASK 0xffffffffL + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE_MASK 0xffffffffL + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_VS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_PS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK 0x000007ffL +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK 0x007ff000L + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK 0x0000ffffL +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK 0xffff0000L + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK 0x0000003fL +#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK 0x00003f00L +#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK 0x00010000L +#define SQ_PROGRAM_CNTL__VS_RESOURCE 0x00010000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK 0x00020000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE 0x00020000L +#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK 0x00040000L +#define SQ_PROGRAM_CNTL__PARAM_GEN 0x00040000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK 0x00080000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX 0x00080000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK 0x00f00000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK 0x07000000L +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK 0x78000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK 0x80000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX 0x80000000L + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK 0x0000000fL +#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK 0x000000f0L +#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK 0x00000f00L +#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK 0x0000f000L +#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK 0x000f0000L +#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK 0x00f00000L +#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK 0x0f000000L +#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK 0xf0000000L + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK 0x0000000fL +#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK 0x000000f0L +#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK 0x00000f00L +#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK 0x0000f000L +#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK 0x000f0000L +#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK 0x00f00000L +#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK 0x0f000000L +#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK 0xf0000000L + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE_MASK 0x000001ffL +#define SQ_VS_CONST__SIZE_MASK 0x001ff000L + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE_MASK 0x000001ffL +#define SQ_PS_CONST__SIZE_MASK 0x001ff000L + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK 0x00000001L +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE 0x00000001L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK 0x00000002L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY 0x00000002L +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK 0x0000000cL +#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK 0x0000ff00L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK 0x00010000L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF 0x00010000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK 0x00020000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE 0x00020000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK 0x00040000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL 0x00040000L + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE_MASK 0x00000007L + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_ON 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK 0x0007ff00L +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK 0xff000000L + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_PIX 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK 0x00000002L +#define SQ_DEBUG_MISC_1__DB_ON_VTX 0x00000002L +#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK 0x0000ff00L +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK 0x07ff0000L + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK 0x0000003fL +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK 0x00000040L +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY 0x00000040L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK 0x00000100L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE 0x00000100L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK 0x00000200L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL 0x00000200L +#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK 0x00001c00L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK 0x00002000L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE 0x00002000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK 0x00004000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE 0x00004000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK 0x003f0000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK 0x00400000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE 0x00400000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK 0x00800000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE 0x00800000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK 0x01000000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE 0x01000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK 0x02000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE 0x02000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK 0x04000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE 0x04000000L + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK 0x00000007L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK 0x00000070L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK 0x00000700L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK 0x00007000L + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_MASK__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT 0x00000004L + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID_MASK 0x00000007L +#define MH_AXI_ERROR__AXI_READ_ERROR_MASK 0x00000008L +#define MH_AXI_ERROR__AXI_READ_ERROR 0x00000008L +#define MH_AXI_ERROR__AXI_WRITE_ID_MASK 0x00000070L +#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK 0x00000080L +#define MH_AXI_ERROR__AXI_WRITE_ERROR 0x00000080L + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX_MASK 0x0000003fL + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA_MASK 0xffffffffL + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK 0x00000001L +#define MH_AXI_HALT_CONTROL__AXI_HALT 0x00000001L + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY_MASK 0x00000001L +#define MH_DEBUG_REG00__MH_BUSY 0x00000001L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK 0x00000002L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING 0x00000002L +#define MH_DEBUG_REG00__CP_REQUEST_MASK 0x00000004L +#define MH_DEBUG_REG00__CP_REQUEST 0x00000004L +#define MH_DEBUG_REG00__VGT_REQUEST_MASK 0x00000008L +#define MH_DEBUG_REG00__VGT_REQUEST 0x00000008L +#define MH_DEBUG_REG00__TC_REQUEST_MASK 0x00000010L +#define MH_DEBUG_REG00__TC_REQUEST 0x00000010L +#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_EMPTY 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_FULL_MASK 0x00000040L +#define MH_DEBUG_REG00__TC_CAM_FULL 0x00000040L +#define MH_DEBUG_REG00__TCD_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG00__TCD_EMPTY 0x00000080L +#define MH_DEBUG_REG00__TCD_FULL_MASK 0x00000100L +#define MH_DEBUG_REG00__TCD_FULL 0x00000100L +#define MH_DEBUG_REG00__RB_REQUEST_MASK 0x00000200L +#define MH_DEBUG_REG00__RB_REQUEST 0x00000200L +#define MH_DEBUG_REG00__PA_REQUEST_MASK 0x00000400L +#define MH_DEBUG_REG00__PA_REQUEST 0x00000400L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK 0x00000800L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE 0x00000800L +#define MH_DEBUG_REG00__ARQ_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG00__ARQ_EMPTY 0x00001000L +#define MH_DEBUG_REG00__ARQ_FULL_MASK 0x00002000L +#define MH_DEBUG_REG00__ARQ_FULL 0x00002000L +#define MH_DEBUG_REG00__WDB_EMPTY_MASK 0x00004000L +#define MH_DEBUG_REG00__WDB_EMPTY 0x00004000L +#define MH_DEBUG_REG00__WDB_FULL_MASK 0x00008000L +#define MH_DEBUG_REG00__WDB_FULL 0x00008000L +#define MH_DEBUG_REG00__AXI_AVALID_MASK 0x00010000L +#define MH_DEBUG_REG00__AXI_AVALID 0x00010000L +#define MH_DEBUG_REG00__AXI_AREADY_MASK 0x00020000L +#define MH_DEBUG_REG00__AXI_AREADY 0x00020000L +#define MH_DEBUG_REG00__AXI_ARVALID_MASK 0x00040000L +#define MH_DEBUG_REG00__AXI_ARVALID 0x00040000L +#define MH_DEBUG_REG00__AXI_ARREADY_MASK 0x00080000L +#define MH_DEBUG_REG00__AXI_ARREADY 0x00080000L +#define MH_DEBUG_REG00__AXI_WVALID_MASK 0x00100000L +#define MH_DEBUG_REG00__AXI_WVALID 0x00100000L +#define MH_DEBUG_REG00__AXI_WREADY_MASK 0x00200000L +#define MH_DEBUG_REG00__AXI_WREADY 0x00200000L +#define MH_DEBUG_REG00__AXI_RVALID_MASK 0x00400000L +#define MH_DEBUG_REG00__AXI_RVALID 0x00400000L +#define MH_DEBUG_REG00__AXI_RREADY_MASK 0x00800000L +#define MH_DEBUG_REG00__AXI_RREADY 0x00800000L +#define MH_DEBUG_REG00__AXI_BVALID_MASK 0x01000000L +#define MH_DEBUG_REG00__AXI_BVALID 0x01000000L +#define MH_DEBUG_REG00__AXI_BREADY_MASK 0x02000000L +#define MH_DEBUG_REG00__AXI_BREADY 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK 0x08000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK 0x08000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK 0x10000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA 0x10000000L + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q_MASK 0x00000001L +#define MH_DEBUG_REG01__CP_SEND_q 0x00000001L +#define MH_DEBUG_REG01__CP_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG01__CP_RTR_q 0x00000002L +#define MH_DEBUG_REG01__CP_WRITE_q_MASK 0x00000004L +#define MH_DEBUG_REG01__CP_WRITE_q 0x00000004L +#define MH_DEBUG_REG01__CP_TAG_q_MASK 0x00000038L +#define MH_DEBUG_REG01__CP_BLEN_q_MASK 0x00000040L +#define MH_DEBUG_REG01__CP_BLEN_q 0x00000040L +#define MH_DEBUG_REG01__VGT_SEND_q_MASK 0x00000080L +#define MH_DEBUG_REG01__VGT_SEND_q 0x00000080L +#define MH_DEBUG_REG01__VGT_RTR_q_MASK 0x00000100L +#define MH_DEBUG_REG01__VGT_RTR_q 0x00000100L +#define MH_DEBUG_REG01__VGT_TAG_q_MASK 0x00000200L +#define MH_DEBUG_REG01__VGT_TAG_q 0x00000200L +#define MH_DEBUG_REG01__TC_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG01__TC_SEND_q 0x00000400L +#define MH_DEBUG_REG01__TC_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG01__TC_RTR_q 0x00000800L +#define MH_DEBUG_REG01__TC_BLEN_q_MASK 0x00001000L +#define MH_DEBUG_REG01__TC_BLEN_q 0x00001000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK 0x00004000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q 0x00004000L +#define MH_DEBUG_REG01__TC_MH_written_MASK 0x00008000L +#define MH_DEBUG_REG01__TC_MH_written 0x00008000L +#define MH_DEBUG_REG01__RB_SEND_q_MASK 0x00010000L +#define MH_DEBUG_REG01__RB_SEND_q 0x00010000L +#define MH_DEBUG_REG01__RB_RTR_q_MASK 0x00020000L +#define MH_DEBUG_REG01__RB_RTR_q 0x00020000L +#define MH_DEBUG_REG01__PA_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG01__PA_SEND_q 0x00040000L +#define MH_DEBUG_REG01__PA_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG01__PA_RTR_q 0x00080000L + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG02__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG02__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG02__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG02__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_rlast 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_tag_MASK 0x00000070L +#define MH_DEBUG_REG02__RDC_RID_MASK 0x00000380L +#define MH_DEBUG_REG02__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG02__MH_CP_writeclean_MASK 0x00001000L +#define MH_DEBUG_REG02__MH_CP_writeclean 0x00001000L +#define MH_DEBUG_REG02__MH_RB_writeclean_MASK 0x00002000L +#define MH_DEBUG_REG02__MH_RB_writeclean 0x00002000L +#define MH_DEBUG_REG02__MH_PA_writeclean_MASK 0x00004000L +#define MH_DEBUG_REG02__MH_PA_writeclean 0x00004000L +#define MH_DEBUG_REG02__BRC_BID_MASK 0x00038000L +#define MH_DEBUG_REG02__BRC_BRESP_MASK 0x000c0000L + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG05__CP_MH_send 0x00000001L +#define MH_DEBUG_REG05__CP_MH_write_MASK 0x00000002L +#define MH_DEBUG_REG05__CP_MH_write 0x00000002L +#define MH_DEBUG_REG05__CP_MH_tag_MASK 0x0000001cL +#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be_MASK 0x000000ffL +#define MH_DEBUG_REG08__RB_MH_be_MASK 0x0000ff00L +#define MH_DEBUG_REG08__PA_MH_be_MASK 0x00ff0000L + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK 0x00000007L +#define MH_DEBUG_REG09__VGT_MH_send_MASK 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_send 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_tagbe 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG10__TC_MH_send_MASK 0x00000004L +#define MH_DEBUG_REG10__TC_MH_send 0x00000004L +#define MH_DEBUG_REG10__TC_MH_mask_MASK 0x00000018L +#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info_MASK 0x01ffffffL +#define MH_DEBUG_REG11__TC_MH_send_MASK 0x02000000L +#define MH_DEBUG_REG11__TC_MH_send 0x02000000L + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK 0x01ffffffL +#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK 0x02000000L +#define MH_DEBUG_REG12__MH_TC_mcinfo_send 0x02000000L +#define MH_DEBUG_REG12__TC_MH_written_MASK 0x04000000L +#define MH_DEBUG_REG12__TC_MH_written 0x04000000L + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_SEND 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK 0x00000018L +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK 0x01ffffffL +#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK 0x02000000L +#define MH_DEBUG_REG14__TC_ROQ_SEND 0x02000000L + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG15__RB_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG15__RB_MH_send 0x00000010L +#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG18__PA_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG18__PA_MH_send 0x00000010L +#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG21__AVALID_q 0x00000001L +#define MH_DEBUG_REG21__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG21__AREADY_q 0x00000002L +#define MH_DEBUG_REG21__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG21__ALEN_q_2_0_MASK 0x000000e0L +#define MH_DEBUG_REG21__ARVALID_q_MASK 0x00000100L +#define MH_DEBUG_REG21__ARVALID_q 0x00000100L +#define MH_DEBUG_REG21__ARREADY_q_MASK 0x00000200L +#define MH_DEBUG_REG21__ARREADY_q 0x00000200L +#define MH_DEBUG_REG21__ARID_q_MASK 0x00001c00L +#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK 0x00006000L +#define MH_DEBUG_REG21__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG21__RVALID_q 0x00008000L +#define MH_DEBUG_REG21__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG21__RREADY_q 0x00010000L +#define MH_DEBUG_REG21__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG21__RLAST_q 0x00020000L +#define MH_DEBUG_REG21__RID_q_MASK 0x001c0000L +#define MH_DEBUG_REG21__WVALID_q_MASK 0x00200000L +#define MH_DEBUG_REG21__WVALID_q 0x00200000L +#define MH_DEBUG_REG21__WREADY_q_MASK 0x00400000L +#define MH_DEBUG_REG21__WREADY_q 0x00400000L +#define MH_DEBUG_REG21__WLAST_q_MASK 0x00800000L +#define MH_DEBUG_REG21__WLAST_q 0x00800000L +#define MH_DEBUG_REG21__WID_q_MASK 0x07000000L +#define MH_DEBUG_REG21__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG21__BVALID_q 0x08000000L +#define MH_DEBUG_REG21__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG21__BREADY_q 0x10000000L +#define MH_DEBUG_REG21__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG22__AVALID_q 0x00000001L +#define MH_DEBUG_REG22__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG22__AREADY_q 0x00000002L +#define MH_DEBUG_REG22__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG22__ALEN_q_1_0_MASK 0x00000060L +#define MH_DEBUG_REG22__ARVALID_q_MASK 0x00000080L +#define MH_DEBUG_REG22__ARVALID_q 0x00000080L +#define MH_DEBUG_REG22__ARREADY_q_MASK 0x00000100L +#define MH_DEBUG_REG22__ARREADY_q 0x00000100L +#define MH_DEBUG_REG22__ARID_q_MASK 0x00000e00L +#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK 0x00001000L +#define MH_DEBUG_REG22__ARLEN_q_1_1 0x00001000L +#define MH_DEBUG_REG22__WVALID_q_MASK 0x00002000L +#define MH_DEBUG_REG22__WVALID_q 0x00002000L +#define MH_DEBUG_REG22__WREADY_q_MASK 0x00004000L +#define MH_DEBUG_REG22__WREADY_q 0x00004000L +#define MH_DEBUG_REG22__WLAST_q_MASK 0x00008000L +#define MH_DEBUG_REG22__WLAST_q 0x00008000L +#define MH_DEBUG_REG22__WID_q_MASK 0x00070000L +#define MH_DEBUG_REG22__WSTRB_q_MASK 0x07f80000L +#define MH_DEBUG_REG22__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG22__BVALID_q 0x08000000L +#define MH_DEBUG_REG22__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG22__BREADY_q 0x10000000L +#define MH_DEBUG_REG22__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK 0x00000001L +#define MH_DEBUG_REG23__ARC_CTRL_RE_q 0x00000001L +#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK 0x0000000eL +#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG24__REG_A_MASK 0x0000fffcL +#define MH_DEBUG_REG24__REG_RE_MASK 0x00010000L +#define MH_DEBUG_REG24__REG_RE 0x00010000L +#define MH_DEBUG_REG24__REG_WE_MASK 0x00020000L +#define MH_DEBUG_REG24__REG_WE 0x00020000L +#define MH_DEBUG_REG24__BLOCK_RS_MASK 0x00040000L +#define MH_DEBUG_REG24__BLOCK_RS 0x00040000L + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD_MASK 0xffffffffL + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy_MASK 0x00000001L +#define MH_DEBUG_REG26__MH_RBBM_busy 0x00000001L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK 0x00000008L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int 0x00000008L +#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK 0x00000010L +#define MH_DEBUG_REG26__GAT_CLK_ENA 0x00000010L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK 0x00000020L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override 0x00000020L +#define MH_DEBUG_REG26__CNT_q_MASK 0x00000fc0L +#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK 0x00001000L +#define MH_DEBUG_REG26__TCD_EMPTY_q 0x00001000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY 0x00002000L +#define MH_DEBUG_REG26__MH_BUSY_d_MASK 0x00004000L +#define MH_DEBUG_REG26__MH_BUSY_d 0x00004000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK 0x00008000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY 0x00008000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC 0x00020000L +#define MH_DEBUG_REG26__CP_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG26__CP_SEND_q 0x00040000L +#define MH_DEBUG_REG26__CP_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG26__CP_RTR_q 0x00080000L +#define MH_DEBUG_REG26__VGT_SEND_q_MASK 0x00100000L +#define MH_DEBUG_REG26__VGT_SEND_q 0x00100000L +#define MH_DEBUG_REG26__VGT_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG26__VGT_RTR_q 0x00200000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK 0x00800000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q 0x00800000L +#define MH_DEBUG_REG26__RB_SEND_q_MASK 0x01000000L +#define MH_DEBUG_REG26__RB_SEND_q 0x01000000L +#define MH_DEBUG_REG26__RB_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG26__RB_RTR_q 0x02000000L +#define MH_DEBUG_REG26__PA_SEND_q_MASK 0x04000000L +#define MH_DEBUG_REG26__PA_SEND_q 0x04000000L +#define MH_DEBUG_REG26__PA_RTR_q_MASK 0x08000000L +#define MH_DEBUG_REG26__PA_RTR_q 0x08000000L +#define MH_DEBUG_REG26__RDC_VALID_MASK 0x10000000L +#define MH_DEBUG_REG26__RDC_VALID 0x10000000L +#define MH_DEBUG_REG26__RDC_RLAST_MASK 0x20000000L +#define MH_DEBUG_REG26__RDC_RLAST 0x20000000L +#define MH_DEBUG_REG26__TLBMISS_VALID_MASK 0x40000000L +#define MH_DEBUG_REG26__TLBMISS_VALID 0x40000000L +#define MH_DEBUG_REG26__BRC_VALID_MASK 0x80000000L +#define MH_DEBUG_REG26__BRC_VALID 0x80000000L + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK 0x00000038L +#define MH_DEBUG_REG27__EFF1_WINNER_MASK 0x000001c0L +#define MH_DEBUG_REG27__ARB_WINNER_MASK 0x00000e00L +#define MH_DEBUG_REG27__ARB_WINNER_q_MASK 0x00007000L +#define MH_DEBUG_REG27__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG27__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG27__KILL_EFF1_MASK 0x00010000L +#define MH_DEBUG_REG27__KILL_EFF1 0x00010000L +#define MH_DEBUG_REG27__ARB_HOLD_MASK 0x00020000L +#define MH_DEBUG_REG27__ARB_HOLD 0x00020000L +#define MH_DEBUG_REG27__ARB_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG27__ARB_RTR_q 0x00040000L +#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK 0x00080000L +#define MH_DEBUG_REG27__CP_SEND_QUAL 0x00080000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK 0x00100000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL 0x00100000L +#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_QUAL 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK 0x00400000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL 0x00400000L +#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK 0x00800000L +#define MH_DEBUG_REG27__RB_SEND_QUAL 0x00800000L +#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK 0x01000000L +#define MH_DEBUG_REG27__PA_SEND_QUAL 0x01000000L +#define MH_DEBUG_REG27__ARB_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG27__ARB_QUAL 0x02000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK 0x04000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ 0x04000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK 0x08000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ 0x08000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK 0x10000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ 0x10000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK 0x20000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ 0x20000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK 0x40000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q 0x40000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK 0x80000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q 0x80000000L + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG28__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK 0x00000040L +#define MH_DEBUG_REG28__CP_SEND_QUAL 0x00000040L +#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK 0x00000080L +#define MH_DEBUG_REG28__VGT_SEND_QUAL 0x00000080L +#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_QUAL 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK 0x00000200L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL 0x00000200L +#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK 0x00000400L +#define MH_DEBUG_REG28__RB_SEND_QUAL 0x00000400L +#define MH_DEBUG_REG28__ARB_QUAL_MASK 0x00000800L +#define MH_DEBUG_REG28__ARB_QUAL 0x00000800L +#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK 0x00001000L +#define MH_DEBUG_REG28__CP_EFF1_REQ 0x00001000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK 0x00002000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ 0x00002000L +#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK 0x00004000L +#define MH_DEBUG_REG28__TC_EFF1_REQ 0x00004000L +#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK 0x00008000L +#define MH_DEBUG_REG28__RB_EFF1_REQ 0x00008000L +#define MH_DEBUG_REG28__EFF1_WIN_MASK 0x00010000L +#define MH_DEBUG_REG28__EFF1_WIN 0x00010000L +#define MH_DEBUG_REG28__KILL_EFF1_MASK 0x00020000L +#define MH_DEBUG_REG28__KILL_EFF1 0x00020000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK 0x00040000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q 0x00040000L +#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK 0x00080000L +#define MH_DEBUG_REG28__TC_ARB_HOLD 0x00080000L +#define MH_DEBUG_REG28__ARB_HOLD_MASK 0x00100000L +#define MH_DEBUG_REG28__ARB_HOLD 0x00100000L +#define MH_DEBUG_REG28__ARB_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG28__ARB_RTR_q 0x00200000L +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000L + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK 0x00000007L +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK 0x00000038L +#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK 0x000001c0L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK 0x00000200L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d 0x00000200L +#define MH_DEBUG_REG29__ARB_HOLD_MASK 0x00000400L +#define MH_DEBUG_REG29__ARB_HOLD 0x00000400L +#define MH_DEBUG_REG29__ARB_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG29__ARB_RTR_q 0x00000800L +#define MH_DEBUG_REG29__CLNT_REQ_MASK 0x0001f000L +#define MH_DEBUG_REG29__RECENT_d_0_MASK 0x000e0000L +#define MH_DEBUG_REG29__RECENT_d_1_MASK 0x00700000L +#define MH_DEBUG_REG29__RECENT_d_2_MASK 0x03800000L +#define MH_DEBUG_REG29__RECENT_d_3_MASK 0x1c000000L +#define MH_DEBUG_REG29__RECENT_d_4_MASK 0xe0000000L + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK 0x00000001L +#define MH_DEBUG_REG30__TC_ARB_HOLD 0x00000001L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK 0x00000002L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK 0x00000004L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK 0x00000004L +#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK 0x00000008L +#define MH_DEBUG_REG30__TCD_NEARFULL_q 0x00000008L +#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_IP_q 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK 0x000000e0L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q 0x00000400L +#define MH_DEBUG_REG30__TC_MH_written_MASK 0x00000800L +#define MH_DEBUG_REG30__TC_MH_written 0x00000800L +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK 0x0007f000L +#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK 0x00080000L +#define MH_DEBUG_REG30__WBURST_ACTIVE 0x00080000L +#define MH_DEBUG_REG30__WLAST_q_MASK 0x00100000L +#define MH_DEBUG_REG30__WLAST_q 0x00100000L +#define MH_DEBUG_REG30__WBURST_IP_q_MASK 0x00200000L +#define MH_DEBUG_REG30__WBURST_IP_q 0x00200000L +#define MH_DEBUG_REG30__WBURST_CNT_q_MASK 0x01c00000L +#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG30__CP_SEND_QUAL 0x02000000L +#define MH_DEBUG_REG30__CP_MH_write_MASK 0x04000000L +#define MH_DEBUG_REG30__CP_MH_write 0x04000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK 0x08000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL 0x08000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK 0x10000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL 0x10000000L +#define MH_DEBUG_REG30__ARB_WINNER_MASK 0xe0000000L + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK 0x03ffffffL +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000L + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG32__ROQ_MARK_q_MASK 0x0000ff00L +#define MH_DEBUG_REG32__ROQ_VALID_q_MASK 0x00ff0000L +#define MH_DEBUG_REG32__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG32__TC_MH_send 0x01000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG32__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG32__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG33__ROQ_MARK_d_MASK 0x0000ff00L +#define MH_DEBUG_REG33__ROQ_VALID_d_MASK 0x00ff0000L +#define MH_DEBUG_REG33__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG33__TC_MH_send 0x01000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG33__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG33__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK 0x000000ffL +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK 0x0000ff00L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK 0xff000000L + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG35__TC_MH_send 0x00000001L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK 0x00000004L +#define MH_DEBUG_REG35__ROQ_MARK_q_0 0x00000004L +#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK 0x00000008L +#define MH_DEBUG_REG35__ROQ_VALID_q_0 0x00000008L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK 0x00000010L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0 0x00000010L +#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK 0xffffffe0L + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG36__TC_MH_send 0x00000001L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK 0x00000004L +#define MH_DEBUG_REG36__ROQ_MARK_q_1 0x00000004L +#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK 0x00000008L +#define MH_DEBUG_REG36__ROQ_VALID_q_1 0x00000008L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK 0x00000010L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1 0x00000010L +#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK 0xffffffe0L + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG37__TC_MH_send 0x00000001L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK 0x00000004L +#define MH_DEBUG_REG37__ROQ_MARK_q_2 0x00000004L +#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK 0x00000008L +#define MH_DEBUG_REG37__ROQ_VALID_q_2 0x00000008L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK 0x00000010L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2 0x00000010L +#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK 0xffffffe0L + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG38__TC_MH_send 0x00000001L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK 0x00000004L +#define MH_DEBUG_REG38__ROQ_MARK_q_3 0x00000004L +#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK 0x00000008L +#define MH_DEBUG_REG38__ROQ_VALID_q_3 0x00000008L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK 0x00000010L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3 0x00000010L +#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK 0xffffffe0L + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG39__TC_MH_send 0x00000001L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK 0x00000004L +#define MH_DEBUG_REG39__ROQ_MARK_q_4 0x00000004L +#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK 0x00000008L +#define MH_DEBUG_REG39__ROQ_VALID_q_4 0x00000008L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK 0x00000010L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4 0x00000010L +#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK 0xffffffe0L + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG40__TC_MH_send 0x00000001L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK 0x00000004L +#define MH_DEBUG_REG40__ROQ_MARK_q_5 0x00000004L +#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK 0x00000008L +#define MH_DEBUG_REG40__ROQ_VALID_q_5 0x00000008L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK 0x00000010L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5 0x00000010L +#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK 0xffffffe0L + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG41__TC_MH_send 0x00000001L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK 0x00000004L +#define MH_DEBUG_REG41__ROQ_MARK_q_6 0x00000004L +#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK 0x00000008L +#define MH_DEBUG_REG41__ROQ_VALID_q_6 0x00000008L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK 0x00000010L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6 0x00000010L +#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK 0xffffffe0L + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG42__TC_MH_send 0x00000001L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK 0x00000004L +#define MH_DEBUG_REG42__ROQ_MARK_q_7 0x00000004L +#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK 0x00000008L +#define MH_DEBUG_REG42__ROQ_VALID_q_7 0x00000008L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK 0x00000010L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7 0x00000010L +#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK 0xffffffe0L + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG43__ARB_REG_WE_q 0x00000001L +#define MH_DEBUG_REG43__ARB_WE_MASK 0x00000002L +#define MH_DEBUG_REG43__ARB_WE 0x00000002L +#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG43__ARB_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG43__ARB_RTR_q_MASK 0x00000008L +#define MH_DEBUG_REG43__ARB_RTR_q 0x00000008L +#define MH_DEBUG_REG43__ARB_REG_RTR_MASK 0x00000010L +#define MH_DEBUG_REG43__ARB_REG_RTR 0x00000010L +#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK 0x00000020L +#define MH_DEBUG_REG43__WDAT_BURST_RTR 0x00000020L +#define MH_DEBUG_REG43__MMU_RTR_MASK 0x00000040L +#define MH_DEBUG_REG43__MMU_RTR 0x00000040L +#define MH_DEBUG_REG43__ARB_ID_q_MASK 0x00000380L +#define MH_DEBUG_REG43__ARB_WRITE_q_MASK 0x00000400L +#define MH_DEBUG_REG43__ARB_WRITE_q 0x00000400L +#define MH_DEBUG_REG43__ARB_BLEN_q_MASK 0x00000800L +#define MH_DEBUG_REG43__ARB_BLEN_q 0x00000800L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY 0x00001000L +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK 0x0000e000L +#define MH_DEBUG_REG43__MMU_WE_MASK 0x00010000L +#define MH_DEBUG_REG43__MMU_WE 0x00010000L +#define MH_DEBUG_REG43__ARQ_RTR_MASK 0x00020000L +#define MH_DEBUG_REG43__ARQ_RTR 0x00020000L +#define MH_DEBUG_REG43__MMU_ID_MASK 0x001c0000L +#define MH_DEBUG_REG43__MMU_WRITE_MASK 0x00200000L +#define MH_DEBUG_REG43__MMU_WRITE 0x00200000L +#define MH_DEBUG_REG43__MMU_BLEN_MASK 0x00400000L +#define MH_DEBUG_REG43__MMU_BLEN 0x00400000L +#define MH_DEBUG_REG43__WBURST_IP_q_MASK 0x00800000L +#define MH_DEBUG_REG43__WBURST_IP_q 0x00800000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK 0x01000000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q 0x01000000L +#define MH_DEBUG_REG43__WDB_WE_MASK 0x02000000L +#define MH_DEBUG_REG43__WDB_WE 0x02000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK 0x08000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3 0x08000000L + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG44__ARB_WE 0x00000001L +#define MH_DEBUG_REG44__ARB_ID_q_MASK 0x0000000eL +#define MH_DEBUG_REG44__ARB_VAD_q_MASK 0xfffffff0L + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE_MASK 0x00000001L +#define MH_DEBUG_REG45__MMU_WE 0x00000001L +#define MH_DEBUG_REG45__MMU_ID_MASK 0x0000000eL +#define MH_DEBUG_REG45__MMU_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG46__WDAT_REG_WE_q 0x00000001L +#define MH_DEBUG_REG46__WDB_WE_MASK 0x00000002L +#define MH_DEBUG_REG46__WDB_WE 0x00000002L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK 0x00000008L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4 0x00000008L +#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK 0x00000ff0L +#define MH_DEBUG_REG46__ARB_WLAST_MASK 0x00001000L +#define MH_DEBUG_REG46__ARB_WLAST 0x00001000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY 0x00002000L +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK 0x0007c000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK 0x00080000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q 0x00080000L +#define MH_DEBUG_REG46__WDB_WDC_WID_MASK 0x00700000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK 0xff000000L + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK 0x00000001L +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY 0x00000001L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK 0x00000002L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY 0x00000002L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK 0x00000008L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE 0x00000008L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK 0x00000010L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS 0x00000010L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK 0x00000020L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q 0x00000020L +#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_q 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK 0x00001f80L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q 0x00002000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK 0x00004000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q 0x00004000L +#define MH_DEBUG_REG49__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG49__RVALID_q 0x00008000L +#define MH_DEBUG_REG49__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG49__RREADY_q 0x00010000L +#define MH_DEBUG_REG49__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG49__RLAST_q 0x00020000L +#define MH_DEBUG_REG49__BVALID_q_MASK 0x00040000L +#define MH_DEBUG_REG49__BVALID_q 0x00040000L +#define MH_DEBUG_REG49__BREADY_q_MASK 0x00080000L +#define MH_DEBUG_REG49__BREADY_q 0x00080000L + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG50__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG50__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG50__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG50__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK 0x00000008L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND 0x00000008L +#define MH_DEBUG_REG50__TLBMISS_VALID_MASK 0x00000010L +#define MH_DEBUG_REG50__TLBMISS_VALID 0x00000010L +#define MH_DEBUG_REG50__RDC_VALID_MASK 0x00000020L +#define MH_DEBUG_REG50__RDC_VALID 0x00000020L +#define MH_DEBUG_REG50__RDC_RID_MASK 0x000001c0L +#define MH_DEBUG_REG50__RDC_RLAST_MASK 0x00000200L +#define MH_DEBUG_REG50__RDC_RLAST 0x00000200L +#define MH_DEBUG_REG50__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK 0x00001000L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS 0x00001000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q 0x00002000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK 0x00004000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q 0x00004000L +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK 0x00200000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE 0x00200000L +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK 0x0fc00000L +#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK 0x10000000L +#define MH_DEBUG_REG50__CNT_HOLD_q1 0x10000000L +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000L + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK 0xffffffffL + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003L +#define MH_DEBUG_REG52__ARB_WE_MASK 0x00000004L +#define MH_DEBUG_REG52__ARB_WE 0x00000004L +#define MH_DEBUG_REG52__MMU_RTR_MASK 0x00000008L +#define MH_DEBUG_REG52__MMU_RTR 0x00000008L +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0L +#define MH_DEBUG_REG52__ARB_ID_q_MASK 0x1c000000L +#define MH_DEBUG_REG52__ARB_WRITE_q_MASK 0x20000000L +#define MH_DEBUG_REG52__ARB_WRITE_q 0x20000000L +#define MH_DEBUG_REG52__client_behavior_q_MASK 0xc0000000L + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid_MASK 0x00000001L +#define MH_DEBUG_REG53__stage1_valid 0x00000001L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK 0x00000002L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q 0x00000002L +#define MH_DEBUG_REG53__pa_in_mpu_range_MASK 0x00000004L +#define MH_DEBUG_REG53__pa_in_mpu_range 0x00000004L +#define MH_DEBUG_REG53__tag_match_q_MASK 0x00000008L +#define MH_DEBUG_REG53__tag_match_q 0x00000008L +#define MH_DEBUG_REG53__tag_miss_q_MASK 0x00000010L +#define MH_DEBUG_REG53__tag_miss_q 0x00000010L +#define MH_DEBUG_REG53__va_in_range_q_MASK 0x00000020L +#define MH_DEBUG_REG53__va_in_range_q 0x00000020L +#define MH_DEBUG_REG53__MMU_MISS_MASK 0x00000040L +#define MH_DEBUG_REG53__MMU_MISS 0x00000040L +#define MH_DEBUG_REG53__MMU_READ_MISS_MASK 0x00000080L +#define MH_DEBUG_REG53__MMU_READ_MISS 0x00000080L +#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK 0x00000100L +#define MH_DEBUG_REG53__MMU_WRITE_MISS 0x00000100L +#define MH_DEBUG_REG53__MMU_HIT_MASK 0x00000200L +#define MH_DEBUG_REG53__MMU_HIT 0x00000200L +#define MH_DEBUG_REG53__MMU_READ_HIT_MASK 0x00000400L +#define MH_DEBUG_REG53__MMU_READ_HIT 0x00000400L +#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK 0x00000800L +#define MH_DEBUG_REG53__MMU_WRITE_HIT 0x00000800L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT 0x00008000L +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK 0xffff0000L + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR_MASK 0x00000001L +#define MH_DEBUG_REG54__ARQ_RTR 0x00000001L +#define MH_DEBUG_REG54__MMU_WE_MASK 0x00000002L +#define MH_DEBUG_REG54__MMU_WE 0x00000002L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK 0x00000004L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q 0x00000004L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK 0x00000008L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS 0x00000008L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK 0x00000010L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND 0x00000010L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH 0x00000020L +#define MH_DEBUG_REG54__pa_in_mpu_range_MASK 0x00000040L +#define MH_DEBUG_REG54__pa_in_mpu_range 0x00000040L +#define MH_DEBUG_REG54__stage1_valid_MASK 0x00000080L +#define MH_DEBUG_REG54__stage1_valid 0x00000080L +#define MH_DEBUG_REG54__stage2_valid_MASK 0x00000100L +#define MH_DEBUG_REG54__stage2_valid 0x00000100L +#define MH_DEBUG_REG54__client_behavior_q_MASK 0x00000600L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK 0x00000800L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q 0x00000800L +#define MH_DEBUG_REG54__tag_match_q_MASK 0x00001000L +#define MH_DEBUG_REG54__tag_match_q 0x00001000L +#define MH_DEBUG_REG54__tag_miss_q_MASK 0x00002000L +#define MH_DEBUG_REG54__tag_miss_q 0x00002000L +#define MH_DEBUG_REG54__va_in_range_q_MASK 0x00004000L +#define MH_DEBUG_REG54__va_in_range_q 0x00004000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK 0x00008000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q 0x00008000L +#define MH_DEBUG_REG54__TAG_valid_q_MASK 0xffff0000L + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA_MASK 0x00001fffL +#define MH_DEBUG_REG55__TAG_valid_q_0_MASK 0x00002000L +#define MH_DEBUG_REG55__TAG_valid_q_0 0x00002000L +#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG55__TAG1_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG55__TAG_valid_q_1_MASK 0x20000000L +#define MH_DEBUG_REG55__TAG_valid_q_1 0x20000000L + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA_MASK 0x00001fffL +#define MH_DEBUG_REG56__TAG_valid_q_2_MASK 0x00002000L +#define MH_DEBUG_REG56__TAG_valid_q_2 0x00002000L +#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG56__TAG3_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG56__TAG_valid_q_3_MASK 0x20000000L +#define MH_DEBUG_REG56__TAG_valid_q_3 0x20000000L + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA_MASK 0x00001fffL +#define MH_DEBUG_REG57__TAG_valid_q_4_MASK 0x00002000L +#define MH_DEBUG_REG57__TAG_valid_q_4 0x00002000L +#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG57__TAG5_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG57__TAG_valid_q_5_MASK 0x20000000L +#define MH_DEBUG_REG57__TAG_valid_q_5 0x20000000L + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA_MASK 0x00001fffL +#define MH_DEBUG_REG58__TAG_valid_q_6_MASK 0x00002000L +#define MH_DEBUG_REG58__TAG_valid_q_6 0x00002000L +#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG58__TAG7_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG58__TAG_valid_q_7_MASK 0x20000000L +#define MH_DEBUG_REG58__TAG_valid_q_7 0x20000000L + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA_MASK 0x00001fffL +#define MH_DEBUG_REG59__TAG_valid_q_8_MASK 0x00002000L +#define MH_DEBUG_REG59__TAG_valid_q_8 0x00002000L +#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG59__TAG9_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG59__TAG_valid_q_9_MASK 0x20000000L +#define MH_DEBUG_REG59__TAG_valid_q_9 0x20000000L + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA_MASK 0x00001fffL +#define MH_DEBUG_REG60__TAG_valid_q_10_MASK 0x00002000L +#define MH_DEBUG_REG60__TAG_valid_q_10 0x00002000L +#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG60__TAG11_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG60__TAG_valid_q_11_MASK 0x20000000L +#define MH_DEBUG_REG60__TAG_valid_q_11 0x20000000L + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA_MASK 0x00001fffL +#define MH_DEBUG_REG61__TAG_valid_q_12_MASK 0x00002000L +#define MH_DEBUG_REG61__TAG_valid_q_12 0x00002000L +#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG61__TAG13_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG61__TAG_valid_q_13_MASK 0x20000000L +#define MH_DEBUG_REG61__TAG_valid_q_13 0x20000000L + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA_MASK 0x00001fffL +#define MH_DEBUG_REG62__TAG_valid_q_14_MASK 0x00002000L +#define MH_DEBUG_REG62__TAG_valid_q_14 0x00002000L +#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG62__TAG15_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG62__TAG_valid_q_15_MASK 0x20000000L +#define MH_DEBUG_REG62__TAG_valid_q_15 0x20000000L + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE_MASK 0x00000001L +#define MH_MMU_CONFIG__MMU_ENABLE 0x00000001L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK 0x00000002L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE 0x00000002L +#define MH_MMU_CONFIG__RESERVED1_MASK 0x0000000cL +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK 0x00000030L +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK 0x000000c0L +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK 0x00000300L +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00L +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK 0x00003000L +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000L +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK 0x00030000L +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000L +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000L +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK 0x00c00000L +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK 0x03000000L + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK 0x00000fffL +#define MH_MMU_VA_RANGE__VA_BASE_MASK 0xfffff000L + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE_MASK 0xfffff000L + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK 0x00000001L +#define MH_MMU_PAGE_FAULT__PAGE_FAULT 0x00000001L +#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK 0x00000002L +#define MH_MMU_PAGE_FAULT__OP_TYPE 0x00000002L +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK 0x0000000cL +#define MH_MMU_PAGE_FAULT__AXI_ID_MASK 0x00000070L +#define MH_MMU_PAGE_FAULT__RESERVED1_MASK 0x00000080L +#define MH_MMU_PAGE_FAULT__RESERVED1 0x00000080L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE 0x00000100L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK 0x00000200L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE 0x00000200L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK 0x00000400L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR 0x00000400L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK 0x00000800L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR 0x00000800L +#define MH_MMU_PAGE_FAULT__REQ_VA_MASK 0xfffff000L + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK 0xffffffe0L + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_ALL 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK 0x00000002L +#define MH_MMU_INVALIDATE__INVALIDATE_TC 0x00000002L + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE_MASK 0xfffff000L + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END_MASK 0xfffff000L + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK 0x00000002L +#define WAIT_UNTIL__WAIT_RE_VSYNC 0x00000002L +#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK 0x00000004L +#define WAIT_UNTIL__WAIT_FE_VSYNC 0x00000004L +#define WAIT_UNTIL__WAIT_VSYNC_MASK 0x00000008L +#define WAIT_UNTIL__WAIT_VSYNC 0x00000008L +#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID0 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID1 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK 0x00000040L +#define WAIT_UNTIL__WAIT_DSPLY_ID2 0x00000040L +#define WAIT_UNTIL__WAIT_CMDFIFO_MASK 0x00000400L +#define WAIT_UNTIL__WAIT_CMDFIFO 0x00000400L +#define WAIT_UNTIL__WAIT_2D_IDLE_MASK 0x00004000L +#define WAIT_UNTIL__WAIT_2D_IDLE 0x00004000L +#define WAIT_UNTIL__WAIT_3D_IDLE_MASK 0x00008000L +#define WAIT_UNTIL__WAIT_3D_IDLE 0x00008000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK 0x00010000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN 0x00010000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK 0x00020000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN 0x00020000L +#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK 0x00f00000L + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020L + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL +#define RBBM_STATUS__TC_BUSY_MASK 0x00000020L +#define RBBM_STATUS__TC_BUSY 0x00000020L +#define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L +#define RBBM_STATUS__HIRQ_PENDING 0x00000100L +#define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L +#define RBBM_STATUS__CPRQ_PENDING 0x00000200L +#define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L +#define RBBM_STATUS__CFRQ_PENDING 0x00000400L +#define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L +#define RBBM_STATUS__PFRQ_PENDING 0x00000800L +#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L +#define RBBM_STATUS__VGT_BUSY_NO_DMA 0x00001000L +#define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L +#define RBBM_STATUS__RBBM_WU_BUSY 0x00004000L +#define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L +#define RBBM_STATUS__CP_NRT_BUSY 0x00010000L +#define RBBM_STATUS__MH_BUSY_MASK 0x00040000L +#define RBBM_STATUS__MH_BUSY 0x00040000L +#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L +#define RBBM_STATUS__MH_COHERENCY_BUSY 0x00080000L +#define RBBM_STATUS__SX_BUSY_MASK 0x00200000L +#define RBBM_STATUS__SX_BUSY 0x00200000L +#define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L +#define RBBM_STATUS__TPC_BUSY 0x00400000L +#define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L +#define RBBM_STATUS__SC_CNTX_BUSY 0x01000000L +#define RBBM_STATUS__PA_BUSY_MASK 0x02000000L +#define RBBM_STATUS__PA_BUSY 0x02000000L +#define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L +#define RBBM_STATUS__VGT_BUSY 0x04000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY 0x08000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY 0x10000000L +#define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L +#define RBBM_STATUS__RB_CNTX_BUSY 0x40000000L +#define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +#define RBBM_STATUS__GUI_ACTIVE 0x80000000L + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2 0x00000004L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK 0x00000008L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID 0x00000008L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK 0x00000040L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2 0x00000040L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK 0x00000080L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL 0x00000080L +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK 0x00000300L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK 0x00001000L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2 0x00001000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK 0x00002000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL 0x00002000L +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK 0x0000c000L +#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK 0x00030000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK 0x00400000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2 0x00400000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK 0x00800000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL 0x00800000L +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK 0x03000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK 0x10000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2 0x10000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK 0x20000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL 0x20000000L +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK 0xc0000000L + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK 0x00000003L +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK 0x00000300L +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK 0x00030000L +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK 0x03000000L + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST_MASK 0xffffffffL + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK 0x0000ffffL +#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK 0x00ff0000L +#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK 0xff000000L + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK 0xffffffffL + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0_MASK 0x000000ffL + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1_MASK 0x0000000fL +#define RBBM_PERIPHID1__DESIGNER0_MASK 0x000000f0L + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1_MASK 0x0000000fL +#define RBBM_PERIPHID2__REVISION_MASK 0x000000f0L + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK 0x00000003L +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK 0x0000000cL +#define RBBM_PERIPHID3__MH_INTERFACE_MASK 0x00000030L +#define RBBM_PERIPHID3__CONTINUATION_MASK 0x00000080L +#define RBBM_PERIPHID3__CONTINUATION 0x00000080L + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL +#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK 0x0001ff00L + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000001fL +#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK 0x000003e0L + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_PA 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_MH 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_BC 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_SX 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK 0x00010000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT 0x00010000L + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE 0x00004000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE 0x00010000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE 0x00200000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE 0x01000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK 0x02000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE 0x02000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK 0x08000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE 0x08000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000L + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE 0x00000800L + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK 0x0000ffffL +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK 0x01000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP 0x01000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK 0x02000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI 0x02000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE 0x20000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE 0x40000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK 0x80000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE 0x80000000L + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK 0x00000001L +#define NQWAIT_UNTIL__WAIT_GUI_IDLE 0x00000001L + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK 0xffffffffL + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK 0x0000003fL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK 0x00000f00L +#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK 0x00001000L +#define RBBM_DEBUG_CNTL__SW_ENABLE 0x00001000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK 0x0f000000L +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK 0xf0000000L + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR_MASK 0x00000002L +#define RBBM_DEBUG__IGNORE_RTR 0x00000002L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI 0x00000010L +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK 0x00010000L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI 0x00010000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI 0x00020000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI 0x00040000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI 0x00080000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK 0x00100000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR 0x00100000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK 0x00200000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR 0x00200000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK 0x00400000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR 0x00400000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK 0x01000000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR 0x01000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK 0x80000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY 0x80000000L + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS_MASK 0x0001fffcL +#define RBBM_READ_ERROR__READ_REQUESTER_MASK 0x40000000L +#define RBBM_READ_ERROR__READ_REQUESTER 0x40000000L +#define RBBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define RBBM_READ_ERROR__READ_ERROR 0x80000000L + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ffL + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L +#define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK 0x00000002L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK 0x00080000L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L +#define RBBM_INT_STATUS__RDERR_INT_STAT 0x00000001L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK 0x00000002L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT 0x00000002L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK 0x00080000L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT 0x00080000L + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L +#define RBBM_INT_ACK__RDERR_INT_ACK 0x00000001L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK 0x00000002L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK 0x00000002L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK 0x00080000L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK 0x00080000L + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK 0x00000020L +#define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L +#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK 0x04000000L +#define MASTER_INT_SIGNAL__SQ_INT_STAT 0x04000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK 0x40000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK 0x80000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK 0x0000003fL + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0x0000ffffL + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE_MASK 0xffffffe0L + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB_CNTL__RB_POLL_EN_MASK 0x00100000L +#define CP_RB_CNTL__RB_POLL_EN 0x00100000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_NO_UPDATE 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA 0x80000000L + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK 0x00000003L +#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK 0xfffffffcL + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE_MASK 0xfffffffcL + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE_MASK 0xfffffffcL + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE_MASK 0xfffffffcL + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK 0x0000000fL +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK 0x00000f00L +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK 0x000f0000L + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END_MASK 0x001f0000L +#define CP_MEQ_THRESHOLDS__ROQ_END_MASK 0x1f000000L + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK 0x0000007fL +#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK 0x00007f00L +#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK 0x007f0000L + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST_MASK 0x0000007fL + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x0000001fL + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK 0x0000007fL +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK 0x007f0000L + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK 0x0000007fL +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK 0x007f0000L + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK 0x0000007fL +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK 0x007f0000L + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK 0x00000007L +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK 0x00000700L + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK 0x0000007fL +#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK 0x007f0000L + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK 0x00000001L +#define CP_MIU_TAG_STAT__TAG_0_STAT 0x00000001L +#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK 0x00000002L +#define CP_MIU_TAG_STAT__TAG_1_STAT 0x00000002L +#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK 0x00000004L +#define CP_MIU_TAG_STAT__TAG_2_STAT 0x00000004L +#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK 0x00000008L +#define CP_MIU_TAG_STAT__TAG_3_STAT 0x00000008L +#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK 0x00000010L +#define CP_MIU_TAG_STAT__TAG_4_STAT 0x00000010L +#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK 0x00000020L +#define CP_MIU_TAG_STAT__TAG_5_STAT 0x00000020L +#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK 0x00000040L +#define CP_MIU_TAG_STAT__TAG_6_STAT 0x00000040L +#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK 0x00000080L +#define CP_MIU_TAG_STAT__TAG_7_STAT 0x00000080L +#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK 0x00000100L +#define CP_MIU_TAG_STAT__TAG_8_STAT 0x00000100L +#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK 0x00000200L +#define CP_MIU_TAG_STAT__TAG_9_STAT 0x00000200L +#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK 0x00000400L +#define CP_MIU_TAG_STAT__TAG_10_STAT 0x00000400L +#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK 0x00000800L +#define CP_MIU_TAG_STAT__TAG_11_STAT 0x00000800L +#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK 0x00001000L +#define CP_MIU_TAG_STAT__TAG_12_STAT 0x00001000L +#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK 0x00002000L +#define CP_MIU_TAG_STAT__TAG_13_STAT 0x00002000L +#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK 0x00004000L +#define CP_MIU_TAG_STAT__TAG_14_STAT 0x00004000L +#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK 0x00008000L +#define CP_MIU_TAG_STAT__TAG_15_STAT 0x00008000L +#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK 0x00010000L +#define CP_MIU_TAG_STAT__TAG_16_STAT 0x00010000L +#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK 0x00020000L +#define CP_MIU_TAG_STAT__TAG_17_STAT 0x00020000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK 0x80000000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG 0x80000000L + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x0000007fL +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX_MASK 0x0000ffffL +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000L +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY 0x02000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY 0x04000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_HALT 0x10000000L +#define CP_ME_CNTL__ME_BUSY_MASK 0x20000000L +#define CP_ME_CNTL__ME_BUSY 0x20000000L +#define CP_ME_CNTL__PROG_CNT_SIZE_MASK 0x80000000L +#define CP_ME_CNTL__PROG_CNT_SIZE 0x80000000L + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA_MASK 0xffffffffL + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x000003ffL + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000003ffL + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR_MASK 0xffffffffL + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffffL +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__PREDICATE_DISABLE 0x00800000L +#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK 0x01000000L +#define CP_DEBUG__PROG_END_PTR_ENABLE 0x01000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK 0x02000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE 0x02000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK 0x04000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS 0x04000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK 0x08000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE 0x08000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK 0x10000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE 0x10000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL 0x40000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK 0x80000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE 0x80000000L + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK_MASK 0x000000ffL +#define SCRATCH_UMSK__SCRATCH_SWAP_MASK 0x00030000L + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR_MASK 0xffffffe0L + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR 0x00000002L + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR 0x00000002L + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK 0x00000001L +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC 0x00000001L + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK 0x00000003L +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK 0xffffffffL + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK 0x00000003L +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK 0xfffffffcL + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK 0xffffffffL + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK 0x00000001L +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR 0x00000001L + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK 0xffffffffL + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK_MASK 0x00080000L +#define CP_INT_CNTL__SW_INT_MASK 0x00080000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK 0x00800000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK 0x01000000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK 0x02000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L +#define CP_INT_CNTL__IB_ERROR_MASK_MASK 0x08000000L +#define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L +#define CP_INT_CNTL__IB2_INT_MASK_MASK 0x20000000L +#define CP_INT_CNTL__IB2_INT_MASK 0x20000000L +#define CP_INT_CNTL__IB1_INT_MASK_MASK 0x40000000L +#define CP_INT_CNTL__IB1_INT_MASK 0x40000000L +#define CP_INT_CNTL__RB_INT_MASK_MASK 0x80000000L +#define CP_INT_CNTL__RB_INT_MASK 0x80000000L + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__SW_INT_STAT 0x00080000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK 0x00800000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK 0x01000000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT 0x01000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK 0x02000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT 0x02000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT 0x04000000L +#define CP_INT_STATUS__IB_ERROR_STAT_MASK 0x08000000L +#define CP_INT_STATUS__IB_ERROR_STAT 0x08000000L +#define CP_INT_STATUS__IB2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__IB2_INT_STAT 0x20000000L +#define CP_INT_STATUS__IB1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__IB1_INT_STAT 0x40000000L +#define CP_INT_STATUS__RB_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS__RB_INT_STAT 0x80000000L + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK_MASK 0x00080000L +#define CP_INT_ACK__SW_INT_ACK 0x00080000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK 0x00800000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK 0x00800000L +#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK 0x01000000L +#define CP_INT_ACK__OPCODE_ERROR_ACK 0x01000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK 0x02000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK 0x02000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK 0x04000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK 0x04000000L +#define CP_INT_ACK__IB_ERROR_ACK_MASK 0x08000000L +#define CP_INT_ACK__IB_ERROR_ACK 0x08000000L +#define CP_INT_ACK__IB2_INT_ACK_MASK 0x20000000L +#define CP_INT_ACK__IB2_INT_ACK 0x20000000L +#define CP_INT_ACK__IB1_INT_ACK_MASK 0x40000000L +#define CP_INT_ACK__IB1_INT_ACK 0x40000000L +#define CP_INT_ACK__RB_INT_ACK_MASK 0x80000000L +#define CP_INT_ACK__RB_INT_ACK 0x80000000L + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000001ffL + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0x00ffffffL + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK 0x0000003fL + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK 0xffffffffL + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK 0x0000ffffL + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK 0xffffffffL + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK 0xffffffffL + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK 0xffffffffL + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK 0xffffffffL + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0_MASK 0x00000001L +#define CP_NV_FLAGS_0__DISCARD_0 0x00000001L +#define CP_NV_FLAGS_0__END_RCVD_0_MASK 0x00000002L +#define CP_NV_FLAGS_0__END_RCVD_0 0x00000002L +#define CP_NV_FLAGS_0__DISCARD_1_MASK 0x00000004L +#define CP_NV_FLAGS_0__DISCARD_1 0x00000004L +#define CP_NV_FLAGS_0__END_RCVD_1_MASK 0x00000008L +#define CP_NV_FLAGS_0__END_RCVD_1 0x00000008L +#define CP_NV_FLAGS_0__DISCARD_2_MASK 0x00000010L +#define CP_NV_FLAGS_0__DISCARD_2 0x00000010L +#define CP_NV_FLAGS_0__END_RCVD_2_MASK 0x00000020L +#define CP_NV_FLAGS_0__END_RCVD_2 0x00000020L +#define CP_NV_FLAGS_0__DISCARD_3_MASK 0x00000040L +#define CP_NV_FLAGS_0__DISCARD_3 0x00000040L +#define CP_NV_FLAGS_0__END_RCVD_3_MASK 0x00000080L +#define CP_NV_FLAGS_0__END_RCVD_3 0x00000080L +#define CP_NV_FLAGS_0__DISCARD_4_MASK 0x00000100L +#define CP_NV_FLAGS_0__DISCARD_4 0x00000100L +#define CP_NV_FLAGS_0__END_RCVD_4_MASK 0x00000200L +#define CP_NV_FLAGS_0__END_RCVD_4 0x00000200L +#define CP_NV_FLAGS_0__DISCARD_5_MASK 0x00000400L +#define CP_NV_FLAGS_0__DISCARD_5 0x00000400L +#define CP_NV_FLAGS_0__END_RCVD_5_MASK 0x00000800L +#define CP_NV_FLAGS_0__END_RCVD_5 0x00000800L +#define CP_NV_FLAGS_0__DISCARD_6_MASK 0x00001000L +#define CP_NV_FLAGS_0__DISCARD_6 0x00001000L +#define CP_NV_FLAGS_0__END_RCVD_6_MASK 0x00002000L +#define CP_NV_FLAGS_0__END_RCVD_6 0x00002000L +#define CP_NV_FLAGS_0__DISCARD_7_MASK 0x00004000L +#define CP_NV_FLAGS_0__DISCARD_7 0x00004000L +#define CP_NV_FLAGS_0__END_RCVD_7_MASK 0x00008000L +#define CP_NV_FLAGS_0__END_RCVD_7 0x00008000L +#define CP_NV_FLAGS_0__DISCARD_8_MASK 0x00010000L +#define CP_NV_FLAGS_0__DISCARD_8 0x00010000L +#define CP_NV_FLAGS_0__END_RCVD_8_MASK 0x00020000L +#define CP_NV_FLAGS_0__END_RCVD_8 0x00020000L +#define CP_NV_FLAGS_0__DISCARD_9_MASK 0x00040000L +#define CP_NV_FLAGS_0__DISCARD_9 0x00040000L +#define CP_NV_FLAGS_0__END_RCVD_9_MASK 0x00080000L +#define CP_NV_FLAGS_0__END_RCVD_9 0x00080000L +#define CP_NV_FLAGS_0__DISCARD_10_MASK 0x00100000L +#define CP_NV_FLAGS_0__DISCARD_10 0x00100000L +#define CP_NV_FLAGS_0__END_RCVD_10_MASK 0x00200000L +#define CP_NV_FLAGS_0__END_RCVD_10 0x00200000L +#define CP_NV_FLAGS_0__DISCARD_11_MASK 0x00400000L +#define CP_NV_FLAGS_0__DISCARD_11 0x00400000L +#define CP_NV_FLAGS_0__END_RCVD_11_MASK 0x00800000L +#define CP_NV_FLAGS_0__END_RCVD_11 0x00800000L +#define CP_NV_FLAGS_0__DISCARD_12_MASK 0x01000000L +#define CP_NV_FLAGS_0__DISCARD_12 0x01000000L +#define CP_NV_FLAGS_0__END_RCVD_12_MASK 0x02000000L +#define CP_NV_FLAGS_0__END_RCVD_12 0x02000000L +#define CP_NV_FLAGS_0__DISCARD_13_MASK 0x04000000L +#define CP_NV_FLAGS_0__DISCARD_13 0x04000000L +#define CP_NV_FLAGS_0__END_RCVD_13_MASK 0x08000000L +#define CP_NV_FLAGS_0__END_RCVD_13 0x08000000L +#define CP_NV_FLAGS_0__DISCARD_14_MASK 0x10000000L +#define CP_NV_FLAGS_0__DISCARD_14 0x10000000L +#define CP_NV_FLAGS_0__END_RCVD_14_MASK 0x20000000L +#define CP_NV_FLAGS_0__END_RCVD_14 0x20000000L +#define CP_NV_FLAGS_0__DISCARD_15_MASK 0x40000000L +#define CP_NV_FLAGS_0__DISCARD_15 0x40000000L +#define CP_NV_FLAGS_0__END_RCVD_15_MASK 0x80000000L +#define CP_NV_FLAGS_0__END_RCVD_15 0x80000000L + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16_MASK 0x00000001L +#define CP_NV_FLAGS_1__DISCARD_16 0x00000001L +#define CP_NV_FLAGS_1__END_RCVD_16_MASK 0x00000002L +#define CP_NV_FLAGS_1__END_RCVD_16 0x00000002L +#define CP_NV_FLAGS_1__DISCARD_17_MASK 0x00000004L +#define CP_NV_FLAGS_1__DISCARD_17 0x00000004L +#define CP_NV_FLAGS_1__END_RCVD_17_MASK 0x00000008L +#define CP_NV_FLAGS_1__END_RCVD_17 0x00000008L +#define CP_NV_FLAGS_1__DISCARD_18_MASK 0x00000010L +#define CP_NV_FLAGS_1__DISCARD_18 0x00000010L +#define CP_NV_FLAGS_1__END_RCVD_18_MASK 0x00000020L +#define CP_NV_FLAGS_1__END_RCVD_18 0x00000020L +#define CP_NV_FLAGS_1__DISCARD_19_MASK 0x00000040L +#define CP_NV_FLAGS_1__DISCARD_19 0x00000040L +#define CP_NV_FLAGS_1__END_RCVD_19_MASK 0x00000080L +#define CP_NV_FLAGS_1__END_RCVD_19 0x00000080L +#define CP_NV_FLAGS_1__DISCARD_20_MASK 0x00000100L +#define CP_NV_FLAGS_1__DISCARD_20 0x00000100L +#define CP_NV_FLAGS_1__END_RCVD_20_MASK 0x00000200L +#define CP_NV_FLAGS_1__END_RCVD_20 0x00000200L +#define CP_NV_FLAGS_1__DISCARD_21_MASK 0x00000400L +#define CP_NV_FLAGS_1__DISCARD_21 0x00000400L +#define CP_NV_FLAGS_1__END_RCVD_21_MASK 0x00000800L +#define CP_NV_FLAGS_1__END_RCVD_21 0x00000800L +#define CP_NV_FLAGS_1__DISCARD_22_MASK 0x00001000L +#define CP_NV_FLAGS_1__DISCARD_22 0x00001000L +#define CP_NV_FLAGS_1__END_RCVD_22_MASK 0x00002000L +#define CP_NV_FLAGS_1__END_RCVD_22 0x00002000L +#define CP_NV_FLAGS_1__DISCARD_23_MASK 0x00004000L +#define CP_NV_FLAGS_1__DISCARD_23 0x00004000L +#define CP_NV_FLAGS_1__END_RCVD_23_MASK 0x00008000L +#define CP_NV_FLAGS_1__END_RCVD_23 0x00008000L +#define CP_NV_FLAGS_1__DISCARD_24_MASK 0x00010000L +#define CP_NV_FLAGS_1__DISCARD_24 0x00010000L +#define CP_NV_FLAGS_1__END_RCVD_24_MASK 0x00020000L +#define CP_NV_FLAGS_1__END_RCVD_24 0x00020000L +#define CP_NV_FLAGS_1__DISCARD_25_MASK 0x00040000L +#define CP_NV_FLAGS_1__DISCARD_25 0x00040000L +#define CP_NV_FLAGS_1__END_RCVD_25_MASK 0x00080000L +#define CP_NV_FLAGS_1__END_RCVD_25 0x00080000L +#define CP_NV_FLAGS_1__DISCARD_26_MASK 0x00100000L +#define CP_NV_FLAGS_1__DISCARD_26 0x00100000L +#define CP_NV_FLAGS_1__END_RCVD_26_MASK 0x00200000L +#define CP_NV_FLAGS_1__END_RCVD_26 0x00200000L +#define CP_NV_FLAGS_1__DISCARD_27_MASK 0x00400000L +#define CP_NV_FLAGS_1__DISCARD_27 0x00400000L +#define CP_NV_FLAGS_1__END_RCVD_27_MASK 0x00800000L +#define CP_NV_FLAGS_1__END_RCVD_27 0x00800000L +#define CP_NV_FLAGS_1__DISCARD_28_MASK 0x01000000L +#define CP_NV_FLAGS_1__DISCARD_28 0x01000000L +#define CP_NV_FLAGS_1__END_RCVD_28_MASK 0x02000000L +#define CP_NV_FLAGS_1__END_RCVD_28 0x02000000L +#define CP_NV_FLAGS_1__DISCARD_29_MASK 0x04000000L +#define CP_NV_FLAGS_1__DISCARD_29 0x04000000L +#define CP_NV_FLAGS_1__END_RCVD_29_MASK 0x08000000L +#define CP_NV_FLAGS_1__END_RCVD_29 0x08000000L +#define CP_NV_FLAGS_1__DISCARD_30_MASK 0x10000000L +#define CP_NV_FLAGS_1__DISCARD_30 0x10000000L +#define CP_NV_FLAGS_1__END_RCVD_30_MASK 0x20000000L +#define CP_NV_FLAGS_1__END_RCVD_30 0x20000000L +#define CP_NV_FLAGS_1__DISCARD_31_MASK 0x40000000L +#define CP_NV_FLAGS_1__DISCARD_31 0x40000000L +#define CP_NV_FLAGS_1__END_RCVD_31_MASK 0x80000000L +#define CP_NV_FLAGS_1__END_RCVD_31 0x80000000L + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32_MASK 0x00000001L +#define CP_NV_FLAGS_2__DISCARD_32 0x00000001L +#define CP_NV_FLAGS_2__END_RCVD_32_MASK 0x00000002L +#define CP_NV_FLAGS_2__END_RCVD_32 0x00000002L +#define CP_NV_FLAGS_2__DISCARD_33_MASK 0x00000004L +#define CP_NV_FLAGS_2__DISCARD_33 0x00000004L +#define CP_NV_FLAGS_2__END_RCVD_33_MASK 0x00000008L +#define CP_NV_FLAGS_2__END_RCVD_33 0x00000008L +#define CP_NV_FLAGS_2__DISCARD_34_MASK 0x00000010L +#define CP_NV_FLAGS_2__DISCARD_34 0x00000010L +#define CP_NV_FLAGS_2__END_RCVD_34_MASK 0x00000020L +#define CP_NV_FLAGS_2__END_RCVD_34 0x00000020L +#define CP_NV_FLAGS_2__DISCARD_35_MASK 0x00000040L +#define CP_NV_FLAGS_2__DISCARD_35 0x00000040L +#define CP_NV_FLAGS_2__END_RCVD_35_MASK 0x00000080L +#define CP_NV_FLAGS_2__END_RCVD_35 0x00000080L +#define CP_NV_FLAGS_2__DISCARD_36_MASK 0x00000100L +#define CP_NV_FLAGS_2__DISCARD_36 0x00000100L +#define CP_NV_FLAGS_2__END_RCVD_36_MASK 0x00000200L +#define CP_NV_FLAGS_2__END_RCVD_36 0x00000200L +#define CP_NV_FLAGS_2__DISCARD_37_MASK 0x00000400L +#define CP_NV_FLAGS_2__DISCARD_37 0x00000400L +#define CP_NV_FLAGS_2__END_RCVD_37_MASK 0x00000800L +#define CP_NV_FLAGS_2__END_RCVD_37 0x00000800L +#define CP_NV_FLAGS_2__DISCARD_38_MASK 0x00001000L +#define CP_NV_FLAGS_2__DISCARD_38 0x00001000L +#define CP_NV_FLAGS_2__END_RCVD_38_MASK 0x00002000L +#define CP_NV_FLAGS_2__END_RCVD_38 0x00002000L +#define CP_NV_FLAGS_2__DISCARD_39_MASK 0x00004000L +#define CP_NV_FLAGS_2__DISCARD_39 0x00004000L +#define CP_NV_FLAGS_2__END_RCVD_39_MASK 0x00008000L +#define CP_NV_FLAGS_2__END_RCVD_39 0x00008000L +#define CP_NV_FLAGS_2__DISCARD_40_MASK 0x00010000L +#define CP_NV_FLAGS_2__DISCARD_40 0x00010000L +#define CP_NV_FLAGS_2__END_RCVD_40_MASK 0x00020000L +#define CP_NV_FLAGS_2__END_RCVD_40 0x00020000L +#define CP_NV_FLAGS_2__DISCARD_41_MASK 0x00040000L +#define CP_NV_FLAGS_2__DISCARD_41 0x00040000L +#define CP_NV_FLAGS_2__END_RCVD_41_MASK 0x00080000L +#define CP_NV_FLAGS_2__END_RCVD_41 0x00080000L +#define CP_NV_FLAGS_2__DISCARD_42_MASK 0x00100000L +#define CP_NV_FLAGS_2__DISCARD_42 0x00100000L +#define CP_NV_FLAGS_2__END_RCVD_42_MASK 0x00200000L +#define CP_NV_FLAGS_2__END_RCVD_42 0x00200000L +#define CP_NV_FLAGS_2__DISCARD_43_MASK 0x00400000L +#define CP_NV_FLAGS_2__DISCARD_43 0x00400000L +#define CP_NV_FLAGS_2__END_RCVD_43_MASK 0x00800000L +#define CP_NV_FLAGS_2__END_RCVD_43 0x00800000L +#define CP_NV_FLAGS_2__DISCARD_44_MASK 0x01000000L +#define CP_NV_FLAGS_2__DISCARD_44 0x01000000L +#define CP_NV_FLAGS_2__END_RCVD_44_MASK 0x02000000L +#define CP_NV_FLAGS_2__END_RCVD_44 0x02000000L +#define CP_NV_FLAGS_2__DISCARD_45_MASK 0x04000000L +#define CP_NV_FLAGS_2__DISCARD_45 0x04000000L +#define CP_NV_FLAGS_2__END_RCVD_45_MASK 0x08000000L +#define CP_NV_FLAGS_2__END_RCVD_45 0x08000000L +#define CP_NV_FLAGS_2__DISCARD_46_MASK 0x10000000L +#define CP_NV_FLAGS_2__DISCARD_46 0x10000000L +#define CP_NV_FLAGS_2__END_RCVD_46_MASK 0x20000000L +#define CP_NV_FLAGS_2__END_RCVD_46 0x20000000L +#define CP_NV_FLAGS_2__DISCARD_47_MASK 0x40000000L +#define CP_NV_FLAGS_2__DISCARD_47 0x40000000L +#define CP_NV_FLAGS_2__END_RCVD_47_MASK 0x80000000L +#define CP_NV_FLAGS_2__END_RCVD_47 0x80000000L + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48_MASK 0x00000001L +#define CP_NV_FLAGS_3__DISCARD_48 0x00000001L +#define CP_NV_FLAGS_3__END_RCVD_48_MASK 0x00000002L +#define CP_NV_FLAGS_3__END_RCVD_48 0x00000002L +#define CP_NV_FLAGS_3__DISCARD_49_MASK 0x00000004L +#define CP_NV_FLAGS_3__DISCARD_49 0x00000004L +#define CP_NV_FLAGS_3__END_RCVD_49_MASK 0x00000008L +#define CP_NV_FLAGS_3__END_RCVD_49 0x00000008L +#define CP_NV_FLAGS_3__DISCARD_50_MASK 0x00000010L +#define CP_NV_FLAGS_3__DISCARD_50 0x00000010L +#define CP_NV_FLAGS_3__END_RCVD_50_MASK 0x00000020L +#define CP_NV_FLAGS_3__END_RCVD_50 0x00000020L +#define CP_NV_FLAGS_3__DISCARD_51_MASK 0x00000040L +#define CP_NV_FLAGS_3__DISCARD_51 0x00000040L +#define CP_NV_FLAGS_3__END_RCVD_51_MASK 0x00000080L +#define CP_NV_FLAGS_3__END_RCVD_51 0x00000080L +#define CP_NV_FLAGS_3__DISCARD_52_MASK 0x00000100L +#define CP_NV_FLAGS_3__DISCARD_52 0x00000100L +#define CP_NV_FLAGS_3__END_RCVD_52_MASK 0x00000200L +#define CP_NV_FLAGS_3__END_RCVD_52 0x00000200L +#define CP_NV_FLAGS_3__DISCARD_53_MASK 0x00000400L +#define CP_NV_FLAGS_3__DISCARD_53 0x00000400L +#define CP_NV_FLAGS_3__END_RCVD_53_MASK 0x00000800L +#define CP_NV_FLAGS_3__END_RCVD_53 0x00000800L +#define CP_NV_FLAGS_3__DISCARD_54_MASK 0x00001000L +#define CP_NV_FLAGS_3__DISCARD_54 0x00001000L +#define CP_NV_FLAGS_3__END_RCVD_54_MASK 0x00002000L +#define CP_NV_FLAGS_3__END_RCVD_54 0x00002000L +#define CP_NV_FLAGS_3__DISCARD_55_MASK 0x00004000L +#define CP_NV_FLAGS_3__DISCARD_55 0x00004000L +#define CP_NV_FLAGS_3__END_RCVD_55_MASK 0x00008000L +#define CP_NV_FLAGS_3__END_RCVD_55 0x00008000L +#define CP_NV_FLAGS_3__DISCARD_56_MASK 0x00010000L +#define CP_NV_FLAGS_3__DISCARD_56 0x00010000L +#define CP_NV_FLAGS_3__END_RCVD_56_MASK 0x00020000L +#define CP_NV_FLAGS_3__END_RCVD_56 0x00020000L +#define CP_NV_FLAGS_3__DISCARD_57_MASK 0x00040000L +#define CP_NV_FLAGS_3__DISCARD_57 0x00040000L +#define CP_NV_FLAGS_3__END_RCVD_57_MASK 0x00080000L +#define CP_NV_FLAGS_3__END_RCVD_57 0x00080000L +#define CP_NV_FLAGS_3__DISCARD_58_MASK 0x00100000L +#define CP_NV_FLAGS_3__DISCARD_58 0x00100000L +#define CP_NV_FLAGS_3__END_RCVD_58_MASK 0x00200000L +#define CP_NV_FLAGS_3__END_RCVD_58 0x00200000L +#define CP_NV_FLAGS_3__DISCARD_59_MASK 0x00400000L +#define CP_NV_FLAGS_3__DISCARD_59 0x00400000L +#define CP_NV_FLAGS_3__END_RCVD_59_MASK 0x00800000L +#define CP_NV_FLAGS_3__END_RCVD_59 0x00800000L +#define CP_NV_FLAGS_3__DISCARD_60_MASK 0x01000000L +#define CP_NV_FLAGS_3__DISCARD_60 0x01000000L +#define CP_NV_FLAGS_3__END_RCVD_60_MASK 0x02000000L +#define CP_NV_FLAGS_3__END_RCVD_60 0x02000000L +#define CP_NV_FLAGS_3__DISCARD_61_MASK 0x04000000L +#define CP_NV_FLAGS_3__DISCARD_61 0x04000000L +#define CP_NV_FLAGS_3__END_RCVD_61_MASK 0x08000000L +#define CP_NV_FLAGS_3__END_RCVD_61 0x08000000L +#define CP_NV_FLAGS_3__DISCARD_62_MASK 0x10000000L +#define CP_NV_FLAGS_3__DISCARD_62 0x10000000L +#define CP_NV_FLAGS_3__END_RCVD_62_MASK 0x20000000L +#define CP_NV_FLAGS_3__END_RCVD_62 0x20000000L +#define CP_NV_FLAGS_3__DISCARD_63_MASK 0x40000000L +#define CP_NV_FLAGS_3__DISCARD_63 0x40000000L +#define CP_NV_FLAGS_3__END_RCVD_63_MASK 0x80000000L +#define CP_NV_FLAGS_3__END_RCVD_63 0x80000000L + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK 0x0000001fL + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK 0xffffffffL + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER_MASK 0xffffffffL + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY_MASK 0x00000001L +#define CP_STAT__MIU_WR_BUSY 0x00000001L +#define CP_STAT__MIU_RD_REQ_BUSY_MASK 0x00000002L +#define CP_STAT__MIU_RD_REQ_BUSY 0x00000002L +#define CP_STAT__MIU_RD_RETURN_BUSY_MASK 0x00000004L +#define CP_STAT__MIU_RD_RETURN_BUSY 0x00000004L +#define CP_STAT__RBIU_BUSY_MASK 0x00000008L +#define CP_STAT__RBIU_BUSY 0x00000008L +#define CP_STAT__RCIU_BUSY_MASK 0x00000010L +#define CP_STAT__RCIU_BUSY 0x00000010L +#define CP_STAT__CSF_RING_BUSY_MASK 0x00000020L +#define CP_STAT__CSF_RING_BUSY 0x00000020L +#define CP_STAT__CSF_INDIRECTS_BUSY_MASK 0x00000040L +#define CP_STAT__CSF_INDIRECTS_BUSY 0x00000040L +#define CP_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_STAT__CSF_INDIRECT2_BUSY 0x00000080L +#define CP_STAT__CSF_ST_BUSY_MASK 0x00000200L +#define CP_STAT__CSF_ST_BUSY 0x00000200L +#define CP_STAT__CSF_BUSY_MASK 0x00000400L +#define CP_STAT__CSF_BUSY 0x00000400L +#define CP_STAT__RING_QUEUE_BUSY_MASK 0x00000800L +#define CP_STAT__RING_QUEUE_BUSY 0x00000800L +#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK 0x00001000L +#define CP_STAT__INDIRECTS_QUEUE_BUSY 0x00001000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK 0x00002000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY 0x00002000L +#define CP_STAT__ST_QUEUE_BUSY_MASK 0x00010000L +#define CP_STAT__ST_QUEUE_BUSY 0x00010000L +#define CP_STAT__PFP_BUSY_MASK 0x00020000L +#define CP_STAT__PFP_BUSY 0x00020000L +#define CP_STAT__MEQ_RING_BUSY_MASK 0x00040000L +#define CP_STAT__MEQ_RING_BUSY 0x00040000L +#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK 0x00080000L +#define CP_STAT__MEQ_INDIRECTS_BUSY 0x00080000L +#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK 0x00100000L +#define CP_STAT__MEQ_INDIRECT2_BUSY 0x00100000L +#define CP_STAT__MIU_WC_STALL_MASK 0x00200000L +#define CP_STAT__MIU_WC_STALL 0x00200000L +#define CP_STAT__CP_NRT_BUSY_MASK 0x00400000L +#define CP_STAT__CP_NRT_BUSY 0x00400000L +#define CP_STAT___3D_BUSY_MASK 0x00800000L +#define CP_STAT___3D_BUSY 0x00800000L +#define CP_STAT__ME_BUSY_MASK 0x04000000L +#define CP_STAT__ME_BUSY 0x04000000L +#define CP_STAT__ME_WC_BUSY_MASK 0x20000000L +#define CP_STAT__ME_WC_BUSY 0x20000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +#define CP_STAT__CP_BUSY 0x80000000L + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE_MASK 0xffffffffL + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE_MASK 0xffffffffL + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_PM4__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_PM4__STATUS_MASK 0x80000000L +#define COHER_STATUS_PM4__STATUS 0x80000000L + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE_MASK 0xffffffffL + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE_MASK 0xffffffffL + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_HOST__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_HOST__STATUS_MASK 0x80000000L +#define COHER_STATUS_HOST__STATUS 0x80000000L + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0_MASK 0xfffff000L + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1_MASK 0xfffff000L + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2_MASK 0xfffff000L + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3_MASK 0xfffff000L + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4_MASK 0xfffff000L + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5_MASK 0xfffff000L + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6_MASK 0xfffff000L + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7_MASK 0xfffff000L + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH_MASK 0x00003fffL +#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK 0x0000c000L + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL +#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK 0x00000030L +#define RB_COLOR_INFO__COLOR_LINEAR_MASK 0x00000040L +#define RB_COLOR_INFO__COLOR_LINEAR 0x00000040L +#define RB_COLOR_INFO__COLOR_ENDIAN_MASK 0x00000180L +#define RB_COLOR_INFO__COLOR_SWAP_MASK 0x00000600L +#define RB_COLOR_INFO__COLOR_BASE_MASK 0xfffff000L + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK 0x00000001L +#define RB_DEPTH_INFO__DEPTH_FORMAT 0x00000001L +#define RB_DEPTH_INFO__DEPTH_BASE_MASK 0xfffff000L + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF_MASK 0x000000ffL +#define RB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L +#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L +#define RB_STENCILREFMASK__RESERVED0_MASK 0x01000000L +#define RB_STENCILREFMASK__RESERVED0 0x01000000L +#define RB_STENCILREFMASK__RESERVED1_MASK 0x02000000L +#define RB_STENCILREFMASK__RESERVED1 0x02000000L + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF_MASK 0xffffffffL + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED_MASK 0x00000001L +#define RB_COLOR_MASK__WRITE_RED 0x00000001L +#define RB_COLOR_MASK__WRITE_GREEN_MASK 0x00000002L +#define RB_COLOR_MASK__WRITE_GREEN 0x00000002L +#define RB_COLOR_MASK__WRITE_BLUE_MASK 0x00000004L +#define RB_COLOR_MASK__WRITE_BLUE 0x00000004L +#define RB_COLOR_MASK__WRITE_ALPHA_MASK 0x00000008L +#define RB_COLOR_MASK__WRITE_ALPHA 0x00000008L +#define RB_COLOR_MASK__RESERVED2_MASK 0x00000010L +#define RB_COLOR_MASK__RESERVED2 0x00000010L +#define RB_COLOR_MASK__RESERVED3_MASK 0x00000020L +#define RB_COLOR_MASK__RESERVED3 0x00000020L + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED_MASK 0x000000ffL + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN_MASK 0x000000ffL + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE_MASK 0x000000ffL + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK 0x000000ffL + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED_MASK 0x000000ffL +#define RB_FOG_COLOR__FOG_GREEN_MASK 0x0000ff00L +#define RB_FOG_COLOR__FOG_BLUE_MASK 0x00ff0000L + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK 0x000000ffL +#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L +#define RB_STENCILREFMASK_BF__RESERVED4_MASK 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED4 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED5_MASK 0x02000000L +#define RB_STENCILREFMASK_BF__RESERVED5 0x02000000L + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define RB_DEPTHCONTROL__STENCIL_ENABLE 0x00000001L +#define RB_DEPTHCONTROL__Z_ENABLE_MASK 0x00000002L +#define RB_DEPTHCONTROL__Z_ENABLE 0x00000002L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE 0x00000004L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK 0x00000008L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE 0x00000008L +#define RB_DEPTHCONTROL__ZFUNC_MASK 0x00000070L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE 0x00000080L +#define RB_DEPTHCONTROL__STENCILFUNC_MASK 0x00000700L +#define RB_DEPTHCONTROL__STENCILFAIL_MASK 0x00003800L +#define RB_DEPTHCONTROL__STENCILZPASS_MASK 0x0001c000L +#define RB_DEPTHCONTROL__STENCILZFAIL_MASK 0x000e0000L +#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK 0x03800000L +#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK 0x1c000000L +#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK 0xe0000000L + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_MASK 0x40000000L +#define RB_BLENDCONTROL__BLEND_FORCE 0x40000000L + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC_MASK 0x00000007L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK 0x00000008L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE 0x00000008L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK 0x00000010L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE 0x00000010L +#define RB_COLORCONTROL__BLEND_DISABLE_MASK 0x00000020L +#define RB_COLORCONTROL__BLEND_DISABLE 0x00000020L +#define RB_COLORCONTROL__FOG_ENABLE_MASK 0x00000040L +#define RB_COLORCONTROL__FOG_ENABLE 0x00000040L +#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK 0x00000080L +#define RB_COLORCONTROL__VS_EXPORTS_FOG 0x00000080L +#define RB_COLORCONTROL__ROP_CODE_MASK 0x00000f00L +#define RB_COLORCONTROL__DITHER_MODE_MASK 0x00003000L +#define RB_COLORCONTROL__DITHER_TYPE_MASK 0x0000c000L +#define RB_COLORCONTROL__PIXEL_FOG_MASK 0x00010000L +#define RB_COLORCONTROL__PIXEL_FOG 0x00010000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK 0x03000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK 0x30000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000L + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE_MASK 0x00000007L + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK 0xffffffffL + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK 0x00000007L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000008L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE 0x00000008L +#define RB_COPY_CONTROL__CLEAR_MASK_MASK 0x000000f0L + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK 0xfffff000L + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK 0x000001ffL + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK 0x00000007L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK 0x000000f0L +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK 0x00000300L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK 0x00000c00L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK 0x00003000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK 0x00020000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA 0x00020000L + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK 0x00001fffL +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK 0x03ffe000L + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK 0x00000001L +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT 0x00000001L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK 0x00000002L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT 0x00000002L + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK 0xffffffffL + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001L +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE 0x00000001L +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK 0x00000006L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK 0x00000008L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM 0x00000008L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP 0x00000020L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP 0x00000040L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK 0x00000080L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE 0x00000080L +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK 0x00001f00L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK 0x00004000L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE 0x00004000L +#define RB_BC_CONTROL__CRC_MODE_MASK 0x00008000L +#define RB_BC_CONTROL__CRC_MODE 0x00008000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK 0x00010000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS 0x00010000L +#define RB_BC_CONTROL__DISABLE_ACCUM_MASK 0x00020000L +#define RB_BC_CONTROL__DISABLE_ACCUM 0x00020000L +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK 0x003c0000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE 0x00400000L +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000L +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000L +#define RB_BC_CONTROL__CRC_SYSTEM_MASK 0x40000000L +#define RB_BC_CONTROL__CRC_SYSTEM 0x40000000L +#define RB_BC_CONTROL__RESERVED6_MASK 0x80000000L +#define RB_BC_CONTROL__RESERVED6 0x80000000L + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK 0x00000030L +#define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA_MASK 0xffffffffL + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK 0x00000001L +#define RB_CRC_CONTROL__CRC_RD_ADVANCE 0x00000001L + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK_MASK 0xffffffffL + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK 0xffffffffL + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK 0xffffffffL + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK 0xffffffffL + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK 0xffffffffL + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL 0x00000008L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK 0x00000010L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL 0x00000010L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK 0x00000020L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL 0x00000020L +#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK 0x00000040L +#define RB_DEBUG_0__RDREQ_Z1_FULL 0x00000040L +#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK 0x00000080L +#define RB_DEBUG_0__RDREQ_Z0_FULL 0x00000080L +#define RB_DEBUG_0__RDREQ_C1_FULL_MASK 0x00000100L +#define RB_DEBUG_0__RDREQ_C1_FULL 0x00000100L +#define RB_DEBUG_0__RDREQ_C0_FULL_MASK 0x00000200L +#define RB_DEBUG_0__RDREQ_C0_FULL 0x00000200L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL 0x00000800L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL 0x00002000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK 0x00008000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL 0x00008000L +#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK 0x00010000L +#define RB_DEBUG_0__WRREQ_Z1_FULL 0x00010000L +#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK 0x00020000L +#define RB_DEBUG_0__WRREQ_Z0_FULL 0x00020000L +#define RB_DEBUG_0__WRREQ_C1_FULL_MASK 0x00040000L +#define RB_DEBUG_0__WRREQ_C1_FULL 0x00040000L +#define RB_DEBUG_0__WRREQ_C0_FULL_MASK 0x00080000L +#define RB_DEBUG_0__WRREQ_C0_FULL 0x00080000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL 0x00200000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK 0x00800000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL 0x00800000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL 0x01000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK 0x02000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL 0x02000000L +#define RB_DEBUG_0__C_SX_LAT_FULL_MASK 0x04000000L +#define RB_DEBUG_0__C_SX_LAT_FULL 0x04000000L +#define RB_DEBUG_0__C_SX_CMD_FULL_MASK 0x08000000L +#define RB_DEBUG_0__C_SX_CMD_FULL 0x08000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK 0x10000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL 0x10000000L +#define RB_DEBUG_0__C_REQ_FULL_MASK 0x20000000L +#define RB_DEBUG_0__C_REQ_FULL 0x20000000L +#define RB_DEBUG_0__C_MASK_FULL_MASK 0x40000000L +#define RB_DEBUG_0__C_MASK_FULL 0x40000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK 0x80000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL 0x80000000L + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK 0x00000001L +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY 0x00000001L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK 0x00000002L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY 0x00000002L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK 0x00000004L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY 0x00000004L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK 0x00000008L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY 0x00000008L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY 0x00000010L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY 0x00000020L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK 0x00000040L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY 0x00000040L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK 0x00000080L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY 0x00000080L +#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK 0x00000100L +#define RB_DEBUG_1__RDREQ_C1_EMPTY 0x00000100L +#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK 0x00000200L +#define RB_DEBUG_1__RDREQ_C0_EMPTY 0x00000200L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY 0x00000800L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY 0x00002000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK 0x00008000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY 0x00008000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK 0x00010000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY 0x00010000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK 0x00020000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY 0x00020000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK 0x00040000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY 0x00040000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK 0x00080000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY 0x00080000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY 0x00200000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY 0x00800000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY 0x01000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY 0x02000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK 0x04000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY 0x04000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK 0x08000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY 0x08000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK 0x10000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY 0x10000000L +#define RB_DEBUG_1__C_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_1__C_REQ_EMPTY 0x20000000L +#define RB_DEBUG_1__C_MASK_EMPTY_MASK 0x40000000L +#define RB_DEBUG_1__C_MASK_EMPTY 0x40000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK 0x80000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY 0x80000000L + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK 0x0000000fL +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK 0x000007f0L +#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK 0x00000800L +#define RB_DEBUG_2__MEM_EXPORT_FLAG 0x00000800L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK 0x00001000L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG 0x00001000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK 0x00002000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT 0x00002000L +#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK 0x00004000L +#define RB_DEBUG_2__EZ_INFTILE_FULL 0x00004000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK 0x00008000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL 0x00008000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK 0x00010000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL 0x00010000L +#define RB_DEBUG_2__Z0_MASK_FULL_MASK 0x00020000L +#define RB_DEBUG_2__Z0_MASK_FULL 0x00020000L +#define RB_DEBUG_2__Z1_MASK_FULL_MASK 0x00040000L +#define RB_DEBUG_2__Z1_MASK_FULL 0x00040000L +#define RB_DEBUG_2__Z0_REQ_FULL_MASK 0x00080000L +#define RB_DEBUG_2__Z0_REQ_FULL 0x00080000L +#define RB_DEBUG_2__Z1_REQ_FULL_MASK 0x00100000L +#define RB_DEBUG_2__Z1_REQ_FULL 0x00100000L +#define RB_DEBUG_2__Z_SAMP_FULL_MASK 0x00200000L +#define RB_DEBUG_2__Z_SAMP_FULL 0x00200000L +#define RB_DEBUG_2__Z_TILE_FULL_MASK 0x00400000L +#define RB_DEBUG_2__Z_TILE_FULL 0x00400000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK 0x00800000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY 0x00800000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK 0x01000000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY 0x01000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY 0x02000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK 0x04000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY 0x04000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK 0x08000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY 0x08000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK 0x10000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY 0x10000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY 0x20000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK 0x40000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY 0x40000000L +#define RB_DEBUG_2__Z_TILE_EMPTY_MASK 0x80000000L +#define RB_DEBUG_2__Z_TILE_EMPTY 0x80000000L + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID_MASK 0x0000000fL +#define RB_DEBUG_3__ACCUM_FLUSHING_MASK 0x000000f0L +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK 0x00004000L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID 0x00004000L +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK 0x00078000L +#define RB_DEBUG_3__SHD_FULL_MASK 0x00080000L +#define RB_DEBUG_3__SHD_FULL 0x00080000L +#define RB_DEBUG_3__SHD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_3__SHD_EMPTY 0x00100000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK 0x01000000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL 0x01000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY 0x02000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK 0x04000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY 0x04000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK 0x08000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL 0x08000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK 0x10000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL 0x10000000L + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK 0x00000001L +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG 0x00000001L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK 0x00000002L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG 0x00000002L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG 0x00000004L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG 0x00000008L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY 0x00000010L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY 0x00000020L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK 0x00000040L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL 0x00000040L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK 0x00000080L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL 0x00000080L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW 0x00000100L +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK 0x00001e00L + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK 0x00000001L +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR 0x00000001L + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED_MASK 0xffffffffL + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK 0x00000600L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h new file mode 100644 index 000000000000..83be5f82ed8c --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h @@ -0,0 +1,591 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamato_OFFSET_HEADER +#define _yamato_OFFSET_HEADER + + +// Registers from PA block + +#define mmPA_CL_VPORT_XSCALE 0x210F +#define mmPA_CL_VPORT_XOFFSET 0x2110 +#define mmPA_CL_VPORT_YSCALE 0x2111 +#define mmPA_CL_VPORT_YOFFSET 0x2112 +#define mmPA_CL_VPORT_ZSCALE 0x2113 +#define mmPA_CL_VPORT_ZOFFSET 0x2114 +#define mmPA_CL_VTE_CNTL 0x2206 +#define mmPA_CL_CLIP_CNTL 0x2204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0x2303 +#define mmPA_CL_GB_VERT_DISC_ADJ 0x2304 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x2305 +#define mmPA_CL_GB_HORZ_DISC_ADJ 0x2306 +#define mmPA_CL_ENHANCE 0x0C85 +#define mmPA_SC_ENHANCE 0x0CA5 +#define mmPA_SU_VTX_CNTL 0x2302 +#define mmPA_SU_POINT_SIZE 0x2280 +#define mmPA_SU_POINT_MINMAX 0x2281 +#define mmPA_SU_LINE_CNTL 0x2282 +#define mmPA_SU_FACE_DATA 0x0C86 +#define mmPA_SU_SC_MODE_CNTL 0x2205 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 +#define mmPA_SU_PERFCOUNTER0_SELECT 0x0C88 +#define mmPA_SU_PERFCOUNTER1_SELECT 0x0C89 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x0C8A +#define mmPA_SU_PERFCOUNTER3_SELECT 0x0C8B +#define mmPA_SU_PERFCOUNTER0_LOW 0x0C8C +#define mmPA_SU_PERFCOUNTER0_HI 0x0C8D +#define mmPA_SU_PERFCOUNTER1_LOW 0x0C8E +#define mmPA_SU_PERFCOUNTER1_HI 0x0C8F +#define mmPA_SU_PERFCOUNTER2_LOW 0x0C90 +#define mmPA_SU_PERFCOUNTER2_HI 0x0C91 +#define mmPA_SU_PERFCOUNTER3_LOW 0x0C92 +#define mmPA_SU_PERFCOUNTER3_HI 0x0C93 +#define mmPA_SC_WINDOW_OFFSET 0x2080 +#define mmPA_SC_AA_CONFIG 0x2301 +#define mmPA_SC_AA_MASK 0x2312 +#define mmPA_SC_LINE_STIPPLE 0x2283 +#define mmPA_SC_LINE_CNTL 0x2300 +#define mmPA_SC_WINDOW_SCISSOR_TL 0x2081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0x2082 +#define mmPA_SC_SCREEN_SCISSOR_TL 0x200E +#define mmPA_SC_SCREEN_SCISSOR_BR 0x200F +#define mmPA_SC_VIZ_QUERY 0x2293 +#define mmPA_SC_VIZ_QUERY_STATUS 0x0C44 +#define mmPA_SC_LINE_STIPPLE_STATE 0x0C40 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x0C98 +#define mmPA_SC_PERFCOUNTER0_LOW 0x0C99 +#define mmPA_SC_PERFCOUNTER0_HI 0x0C9A +#define mmPA_CL_CNTL_STATUS 0x0C84 +#define mmPA_SU_CNTL_STATUS 0x0C94 +#define mmPA_SC_CNTL_STATUS 0x0CA4 +#define mmPA_SU_DEBUG_CNTL 0x0C80 +#define mmPA_SU_DEBUG_DATA 0x0C81 +#define mmPA_SC_DEBUG_CNTL 0x0C82 +#define mmPA_SC_DEBUG_DATA 0x0C83 + + +// Registers from VGT block + +#define mmGFX_COPY_STATE 0x21F4 +#define mmVGT_DRAW_INITIATOR 0x21FC +#define mmVGT_EVENT_INITIATOR 0x21F9 +#define mmVGT_DMA_BASE 0x21FA +#define mmVGT_DMA_SIZE 0x21FB +#define mmVGT_BIN_BASE 0x21FE +#define mmVGT_BIN_SIZE 0x21FF +#define mmVGT_CURRENT_BIN_ID_MIN 0x2207 +#define mmVGT_CURRENT_BIN_ID_MAX 0x2203 +#define mmVGT_IMMED_DATA 0x21FD +#define mmVGT_MAX_VTX_INDX 0x2100 +#define mmVGT_MIN_VTX_INDX 0x2101 +#define mmVGT_INDX_OFFSET 0x2102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 +#define mmVGT_OUT_DEALLOC_CNTL 0x2317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103 +#define mmVGT_ENHANCE 0x2294 +#define mmVGT_VTX_VECT_EJECT_REG 0x0C2C +#define mmVGT_LAST_COPY_STATE 0x0C30 +#define mmVGT_DEBUG_CNTL 0x0C38 +#define mmVGT_DEBUG_DATA 0x0C39 +#define mmVGT_CNTL_STATUS 0x0C3C +#define mmVGT_CRC_SQ_DATA 0x0C3A +#define mmVGT_CRC_SQ_CTRL 0x0C3B +#define mmVGT_PERFCOUNTER0_SELECT 0x0C48 +#define mmVGT_PERFCOUNTER1_SELECT 0x0C49 +#define mmVGT_PERFCOUNTER2_SELECT 0x0C4A +#define mmVGT_PERFCOUNTER3_SELECT 0x0C4B +#define mmVGT_PERFCOUNTER0_LOW 0x0C4C +#define mmVGT_PERFCOUNTER1_LOW 0x0C4E +#define mmVGT_PERFCOUNTER2_LOW 0x0C50 +#define mmVGT_PERFCOUNTER3_LOW 0x0C52 +#define mmVGT_PERFCOUNTER0_HI 0x0C4D +#define mmVGT_PERFCOUNTER1_HI 0x0C4F +#define mmVGT_PERFCOUNTER2_HI 0x0C51 +#define mmVGT_PERFCOUNTER3_HI 0x0C53 + + +// Registers from TP block + +#define mmTC_CNTL_STATUS 0x0E00 +#define mmTCR_CHICKEN 0x0E02 +#define mmTCF_CHICKEN 0x0E03 +#define mmTCM_CHICKEN 0x0E04 +#define mmTCR_PERFCOUNTER0_SELECT 0x0E05 +#define mmTCR_PERFCOUNTER1_SELECT 0x0E08 +#define mmTCR_PERFCOUNTER0_HI 0x0E06 +#define mmTCR_PERFCOUNTER1_HI 0x0E09 +#define mmTCR_PERFCOUNTER0_LOW 0x0E07 +#define mmTCR_PERFCOUNTER1_LOW 0x0E0A +#define mmTP_TC_CLKGATE_CNTL 0x0E17 +#define mmTPC_CNTL_STATUS 0x0E18 +#define mmTPC_DEBUG0 0x0E19 +#define mmTPC_DEBUG1 0x0E1A +#define mmTPC_CHICKEN 0x0E1B +#define mmTP0_CNTL_STATUS 0x0E1C +#define mmTP0_DEBUG 0x0E1D +#define mmTP0_CHICKEN 0x0E1E +#define mmTP0_PERFCOUNTER0_SELECT 0x0E1F +#define mmTP0_PERFCOUNTER0_HI 0x0E20 +#define mmTP0_PERFCOUNTER0_LOW 0x0E21 +#define mmTP0_PERFCOUNTER1_SELECT 0x0E22 +#define mmTP0_PERFCOUNTER1_HI 0x0E23 +#define mmTP0_PERFCOUNTER1_LOW 0x0E24 +#define mmTCM_PERFCOUNTER0_SELECT 0x0E54 +#define mmTCM_PERFCOUNTER1_SELECT 0x0E57 +#define mmTCM_PERFCOUNTER0_HI 0x0E55 +#define mmTCM_PERFCOUNTER1_HI 0x0E58 +#define mmTCM_PERFCOUNTER0_LOW 0x0E56 +#define mmTCM_PERFCOUNTER1_LOW 0x0E59 +#define mmTCF_PERFCOUNTER0_SELECT 0x0E5A +#define mmTCF_PERFCOUNTER1_SELECT 0x0E5D +#define mmTCF_PERFCOUNTER2_SELECT 0x0E60 +#define mmTCF_PERFCOUNTER3_SELECT 0x0E63 +#define mmTCF_PERFCOUNTER4_SELECT 0x0E66 +#define mmTCF_PERFCOUNTER5_SELECT 0x0E69 +#define mmTCF_PERFCOUNTER6_SELECT 0x0E6C +#define mmTCF_PERFCOUNTER7_SELECT 0x0E6F +#define mmTCF_PERFCOUNTER8_SELECT 0x0E72 +#define mmTCF_PERFCOUNTER9_SELECT 0x0E75 +#define mmTCF_PERFCOUNTER10_SELECT 0x0E78 +#define mmTCF_PERFCOUNTER11_SELECT 0x0E7B +#define mmTCF_PERFCOUNTER0_HI 0x0E5B +#define mmTCF_PERFCOUNTER1_HI 0x0E5E +#define mmTCF_PERFCOUNTER2_HI 0x0E61 +#define mmTCF_PERFCOUNTER3_HI 0x0E64 +#define mmTCF_PERFCOUNTER4_HI 0x0E67 +#define mmTCF_PERFCOUNTER5_HI 0x0E6A +#define mmTCF_PERFCOUNTER6_HI 0x0E6D +#define mmTCF_PERFCOUNTER7_HI 0x0E70 +#define mmTCF_PERFCOUNTER8_HI 0x0E73 +#define mmTCF_PERFCOUNTER9_HI 0x0E76 +#define mmTCF_PERFCOUNTER10_HI 0x0E79 +#define mmTCF_PERFCOUNTER11_HI 0x0E7C +#define mmTCF_PERFCOUNTER0_LOW 0x0E5C +#define mmTCF_PERFCOUNTER1_LOW 0x0E5F +#define mmTCF_PERFCOUNTER2_LOW 0x0E62 +#define mmTCF_PERFCOUNTER3_LOW 0x0E65 +#define mmTCF_PERFCOUNTER4_LOW 0x0E68 +#define mmTCF_PERFCOUNTER5_LOW 0x0E6B +#define mmTCF_PERFCOUNTER6_LOW 0x0E6E +#define mmTCF_PERFCOUNTER7_LOW 0x0E71 +#define mmTCF_PERFCOUNTER8_LOW 0x0E74 +#define mmTCF_PERFCOUNTER9_LOW 0x0E77 +#define mmTCF_PERFCOUNTER10_LOW 0x0E7A +#define mmTCF_PERFCOUNTER11_LOW 0x0E7D +#define mmTCF_DEBUG 0x0EC0 +#define mmTCA_FIFO_DEBUG 0x0EC1 +#define mmTCA_PROBE_DEBUG 0x0EC2 +#define mmTCA_TPC_DEBUG 0x0EC3 +#define mmTCB_CORE_DEBUG 0x0EC4 +#define mmTCB_TAG0_DEBUG 0x0EC5 +#define mmTCB_TAG1_DEBUG 0x0EC6 +#define mmTCB_TAG2_DEBUG 0x0EC7 +#define mmTCB_TAG3_DEBUG 0x0EC8 +#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9 +#define mmTCB_FETCH_GEN_WALKER_DEBUG 0x0ECB +#define mmTCB_FETCH_GEN_PIPE0_DEBUG 0x0ECC +#define mmTCD_INPUT0_DEBUG 0x0ED0 +#define mmTCD_DEGAMMA_DEBUG 0x0ED4 +#define mmTCD_DXTMUX_SCTARB_DEBUG 0x0ED5 +#define mmTCD_DXTC_ARB_DEBUG 0x0ED6 +#define mmTCD_STALLS_DEBUG 0x0ED7 +#define mmTCO_STALLS_DEBUG 0x0EE0 +#define mmTCO_QUAD0_DEBUG0 0x0EE1 +#define mmTCO_QUAD0_DEBUG1 0x0EE2 + + +// Registers from TC block + + + +// Registers from SQ block + +#define mmSQ_GPR_MANAGEMENT 0x0D00 +#define mmSQ_FLOW_CONTROL 0x0D01 +#define mmSQ_INST_STORE_MANAGMENT 0x0D02 +#define mmSQ_RESOURCE_MANAGMENT 0x0D03 +#define mmSQ_EO_RT 0x0D04 +#define mmSQ_DEBUG_MISC 0x0D05 +#define mmSQ_ACTIVITY_METER_CNTL 0x0D06 +#define mmSQ_ACTIVITY_METER_STATUS 0x0D07 +#define mmSQ_INPUT_ARB_PRIORITY 0x0D08 +#define mmSQ_THREAD_ARB_PRIORITY 0x0D09 +#define mmSQ_VS_WATCHDOG_TIMER 0x0D0A +#define mmSQ_PS_WATCHDOG_TIMER 0x0D0B +#define mmSQ_INT_CNTL 0x0D34 +#define mmSQ_INT_STATUS 0x0D35 +#define mmSQ_INT_ACK 0x0D36 +#define mmSQ_DEBUG_INPUT_FSM 0x0DAE +#define mmSQ_DEBUG_CONST_MGR_FSM 0x0DAF +#define mmSQ_DEBUG_TP_FSM 0x0DB0 +#define mmSQ_DEBUG_FSM_ALU_0 0x0DB1 +#define mmSQ_DEBUG_FSM_ALU_1 0x0DB2 +#define mmSQ_DEBUG_EXP_ALLOC 0x0DB3 +#define mmSQ_DEBUG_PTR_BUFF 0x0DB4 +#define mmSQ_DEBUG_GPR_VTX 0x0DB5 +#define mmSQ_DEBUG_GPR_PIX 0x0DB6 +#define mmSQ_DEBUG_TB_STATUS_SEL 0x0DB7 +#define mmSQ_DEBUG_VTX_TB_0 0x0DB8 +#define mmSQ_DEBUG_VTX_TB_1 0x0DB9 +#define mmSQ_DEBUG_VTX_TB_STATUS_REG 0x0DBA +#define mmSQ_DEBUG_VTX_TB_STATE_MEM 0x0DBB +#define mmSQ_DEBUG_PIX_TB_0 0x0DBC +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0 +#define mmSQ_DEBUG_PIX_TB_STATE_MEM 0x0DC1 +#define mmSQ_PERFCOUNTER0_SELECT 0x0DC8 +#define mmSQ_PERFCOUNTER1_SELECT 0x0DC9 +#define mmSQ_PERFCOUNTER2_SELECT 0x0DCA +#define mmSQ_PERFCOUNTER3_SELECT 0x0DCB +#define mmSQ_PERFCOUNTER0_LOW 0x0DCC +#define mmSQ_PERFCOUNTER0_HI 0x0DCD +#define mmSQ_PERFCOUNTER1_LOW 0x0DCE +#define mmSQ_PERFCOUNTER1_HI 0x0DCF +#define mmSQ_PERFCOUNTER2_LOW 0x0DD0 +#define mmSQ_PERFCOUNTER2_HI 0x0DD1 +#define mmSQ_PERFCOUNTER3_LOW 0x0DD2 +#define mmSQ_PERFCOUNTER3_HI 0x0DD3 +#define mmSX_PERFCOUNTER0_SELECT 0x0DD4 +#define mmSX_PERFCOUNTER0_LOW 0x0DD8 +#define mmSX_PERFCOUNTER0_HI 0x0DD9 +#define mmSQ_INSTRUCTION_ALU_0 0x5000 +#define mmSQ_INSTRUCTION_ALU_1 0x5001 +#define mmSQ_INSTRUCTION_ALU_2 0x5002 +#define mmSQ_INSTRUCTION_CF_EXEC_0 0x5080 +#define mmSQ_INSTRUCTION_CF_EXEC_1 0x5081 +#define mmSQ_INSTRUCTION_CF_EXEC_2 0x5082 +#define mmSQ_INSTRUCTION_CF_LOOP_0 0x5083 +#define mmSQ_INSTRUCTION_CF_LOOP_1 0x5084 +#define mmSQ_INSTRUCTION_CF_LOOP_2 0x5085 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088 +#define mmSQ_INSTRUCTION_CF_ALLOC_0 0x5089 +#define mmSQ_INSTRUCTION_CF_ALLOC_1 0x508A +#define mmSQ_INSTRUCTION_CF_ALLOC_2 0x508B +#define mmSQ_INSTRUCTION_TFETCH_0 0x5043 +#define mmSQ_INSTRUCTION_TFETCH_1 0x5044 +#define mmSQ_INSTRUCTION_TFETCH_2 0x5045 +#define mmSQ_INSTRUCTION_VFETCH_0 0x5040 +#define mmSQ_INSTRUCTION_VFETCH_1 0x5041 +#define mmSQ_INSTRUCTION_VFETCH_2 0x5042 +#define mmSQ_CONSTANT_0 0x4000 +#define mmSQ_CONSTANT_1 0x4001 +#define mmSQ_CONSTANT_2 0x4002 +#define mmSQ_CONSTANT_3 0x4003 +#define mmSQ_FETCH_0 0x4800 +#define mmSQ_FETCH_1 0x4801 +#define mmSQ_FETCH_2 0x4802 +#define mmSQ_FETCH_3 0x4803 +#define mmSQ_FETCH_4 0x4804 +#define mmSQ_FETCH_5 0x4805 +#define mmSQ_CONSTANT_VFETCH_0 0x4806 +#define mmSQ_CONSTANT_VFETCH_1 0x4808 +#define mmSQ_CONSTANT_T2 0x480C +#define mmSQ_CONSTANT_T3 0x4812 +#define mmSQ_CF_BOOLEANS 0x4900 +#define mmSQ_CF_LOOP 0x4908 +#define mmSQ_CONSTANT_RT_0 0x4940 +#define mmSQ_CONSTANT_RT_1 0x4941 +#define mmSQ_CONSTANT_RT_2 0x4942 +#define mmSQ_CONSTANT_RT_3 0x4943 +#define mmSQ_FETCH_RT_0 0x4D40 +#define mmSQ_FETCH_RT_1 0x4D41 +#define mmSQ_FETCH_RT_2 0x4D42 +#define mmSQ_FETCH_RT_3 0x4D43 +#define mmSQ_FETCH_RT_4 0x4D44 +#define mmSQ_FETCH_RT_5 0x4D45 +#define mmSQ_CF_RT_BOOLEANS 0x4E00 +#define mmSQ_CF_RT_LOOP 0x4E14 +#define mmSQ_VS_PROGRAM 0x21F7 +#define mmSQ_PS_PROGRAM 0x21F6 +#define mmSQ_CF_PROGRAM_SIZE 0x2315 +#define mmSQ_INTERPOLATOR_CNTL 0x2182 +#define mmSQ_PROGRAM_CNTL 0x2180 +#define mmSQ_WRAPPING_0 0x2183 +#define mmSQ_WRAPPING_1 0x2184 +#define mmSQ_VS_CONST 0x2307 +#define mmSQ_PS_CONST 0x2308 +#define mmSQ_CONTEXT_MISC 0x2181 +#define mmSQ_CF_RD_BASE 0x21F5 +#define mmSQ_DEBUG_MISC_0 0x2309 +#define mmSQ_DEBUG_MISC_1 0x230A + + +// Registers from SX block + + + +// Registers from MH block + +#define mmMH_ARBITER_CONFIG 0x0A40 +#define mmMH_CLNT_AXI_ID_REUSE 0x0A41 +#define mmMH_INTERRUPT_MASK 0x0A42 +#define mmMH_INTERRUPT_STATUS 0x0A43 +#define mmMH_INTERRUPT_CLEAR 0x0A44 +#define mmMH_AXI_ERROR 0x0A45 +#define mmMH_PERFCOUNTER0_SELECT 0x0A46 +#define mmMH_PERFCOUNTER1_SELECT 0x0A4A +#define mmMH_PERFCOUNTER0_CONFIG 0x0A47 +#define mmMH_PERFCOUNTER1_CONFIG 0x0A4B +#define mmMH_PERFCOUNTER0_LOW 0x0A48 +#define mmMH_PERFCOUNTER1_LOW 0x0A4C +#define mmMH_PERFCOUNTER0_HI 0x0A49 +#define mmMH_PERFCOUNTER1_HI 0x0A4D +#define mmMH_DEBUG_CTRL 0x0A4E +#define mmMH_DEBUG_DATA 0x0A4F +#define mmMH_AXI_HALT_CONTROL 0x0A50 +#define mmMH_MMU_CONFIG 0x0040 +#define mmMH_MMU_VA_RANGE 0x0041 +#define mmMH_MMU_PT_BASE 0x0042 +#define mmMH_MMU_PAGE_FAULT 0x0043 +#define mmMH_MMU_TRAN_ERROR 0x0044 +#define mmMH_MMU_INVALIDATE 0x0045 +#define mmMH_MMU_MPU_BASE 0x0046 +#define mmMH_MMU_MPU_END 0x0047 + + +// Registers from RBBM block + +#define mmWAIT_UNTIL 0x05C8 +#define mmRBBM_ISYNC_CNTL 0x05C9 +#define mmRBBM_STATUS 0x05D0 +#define mmRBBM_DSPLY 0x0391 +#define mmRBBM_RENDER_LATEST 0x0392 +#define mmRBBM_RTL_RELEASE 0x0000 +#define mmRBBM_PATCH_RELEASE 0x0001 +#define mmRBBM_AUXILIARY_CONFIG 0x0002 +#define mmRBBM_PERIPHID0 0x03F8 +#define mmRBBM_PERIPHID1 0x03F9 +#define mmRBBM_PERIPHID2 0x03FA +#define mmRBBM_PERIPHID3 0x03FB +#define mmRBBM_CNTL 0x003B +#define mmRBBM_SKEW_CNTL 0x003D +#define mmRBBM_SOFT_RESET 0x003C +#define mmRBBM_PM_OVERRIDE1 0x039C +#define mmRBBM_PM_OVERRIDE2 0x039D +#define mmGC_SYS_IDLE 0x039E +#define mmNQWAIT_UNTIL 0x0394 +#define mmRBBM_DEBUG_OUT 0x03A0 +#define mmRBBM_DEBUG_CNTL 0x03A1 +#define mmRBBM_DEBUG 0x039B +#define mmRBBM_READ_ERROR 0x03B3 +#define mmRBBM_WAIT_IDLE_CLOCKS 0x03B2 +#define mmRBBM_INT_CNTL 0x03B4 +#define mmRBBM_INT_STATUS 0x03B5 +#define mmRBBM_INT_ACK 0x03B6 +#define mmMASTER_INT_SIGNAL 0x03B7 +#define mmRBBM_PERFCOUNTER1_SELECT 0x0395 +#define mmRBBM_PERFCOUNTER1_LO 0x0397 +#define mmRBBM_PERFCOUNTER1_HI 0x0398 + + +// Registers from CP block + +#define mmCP_RB_BASE 0x01C0 +#define mmCP_RB_CNTL 0x01C1 +#define mmCP_RB_RPTR_ADDR 0x01C3 +#define mmCP_RB_RPTR 0x01C4 +#define mmCP_RB_RPTR_WR 0x01C7 +#define mmCP_RB_WPTR 0x01C5 +#define mmCP_RB_WPTR_DELAY 0x01C6 +#define mmCP_RB_WPTR_BASE 0x01C8 +#define mmCP_IB1_BASE 0x0458 +#define mmCP_IB1_BUFSZ 0x0459 +#define mmCP_IB2_BASE 0x045A +#define mmCP_IB2_BUFSZ 0x045B +#define mmCP_ST_BASE 0x044D +#define mmCP_ST_BUFSZ 0x044E +#define mmCP_QUEUE_THRESHOLDS 0x01D5 +#define mmCP_MEQ_THRESHOLDS 0x01D6 +#define mmCP_CSQ_AVAIL 0x01D7 +#define mmCP_STQ_AVAIL 0x01D8 +#define mmCP_MEQ_AVAIL 0x01D9 +#define mmCP_CSQ_RB_STAT 0x01FD +#define mmCP_CSQ_IB1_STAT 0x01FE +#define mmCP_CSQ_IB2_STAT 0x01FF +#define mmCP_NON_PREFETCH_CNTRS 0x0440 +#define mmCP_STQ_ST_STAT 0x0443 +#define mmCP_MEQ_STAT 0x044F +#define mmCP_MIU_TAG_STAT 0x0452 +#define mmCP_CMD_INDEX 0x01DA +#define mmCP_CMD_DATA 0x01DB +#define mmCP_ME_CNTL 0x01F6 +#define mmCP_ME_STATUS 0x01F7 +#define mmCP_ME_RAM_WADDR 0x01F8 +#define mmCP_ME_RAM_RADDR 0x01F9 +#define mmCP_ME_RAM_DATA 0x01FA +#define mmCP_ME_RDADDR 0x01EA +#define mmCP_DEBUG 0x01FC +#define mmSCRATCH_REG0 0x0578 +#define mmGUI_SCRATCH_REG0 0x0578 +#define mmSCRATCH_REG1 0x0579 +#define mmGUI_SCRATCH_REG1 0x0579 +#define mmSCRATCH_REG2 0x057A +#define mmGUI_SCRATCH_REG2 0x057A +#define mmSCRATCH_REG3 0x057B +#define mmGUI_SCRATCH_REG3 0x057B +#define mmSCRATCH_REG4 0x057C +#define mmGUI_SCRATCH_REG4 0x057C +#define mmSCRATCH_REG5 0x057D +#define mmGUI_SCRATCH_REG5 0x057D +#define mmSCRATCH_REG6 0x057E +#define mmGUI_SCRATCH_REG6 0x057E +#define mmSCRATCH_REG7 0x057F +#define mmGUI_SCRATCH_REG7 0x057F +#define mmSCRATCH_UMSK 0x01DC +#define mmSCRATCH_ADDR 0x01DD +#define mmCP_ME_VS_EVENT_SRC 0x0600 +#define mmCP_ME_VS_EVENT_ADDR 0x0601 +#define mmCP_ME_VS_EVENT_DATA 0x0602 +#define mmCP_ME_VS_EVENT_ADDR_SWM 0x0603 +#define mmCP_ME_VS_EVENT_DATA_SWM 0x0604 +#define mmCP_ME_PS_EVENT_SRC 0x0605 +#define mmCP_ME_PS_EVENT_ADDR 0x0606 +#define mmCP_ME_PS_EVENT_DATA 0x0607 +#define mmCP_ME_PS_EVENT_ADDR_SWM 0x0608 +#define mmCP_ME_PS_EVENT_DATA_SWM 0x0609 +#define mmCP_ME_CF_EVENT_SRC 0x060A +#define mmCP_ME_CF_EVENT_ADDR 0x060B +#define mmCP_ME_CF_EVENT_DATA 0x060C +#define mmCP_ME_NRT_ADDR 0x060D +#define mmCP_ME_NRT_DATA 0x060E +#define mmCP_ME_VS_FETCH_DONE_SRC 0x0612 +#define mmCP_ME_VS_FETCH_DONE_ADDR 0x0613 +#define mmCP_ME_VS_FETCH_DONE_DATA 0x0614 +#define mmCP_INT_CNTL 0x01F2 +#define mmCP_INT_STATUS 0x01F3 +#define mmCP_INT_ACK 0x01F4 +#define mmCP_PFP_UCODE_ADDR 0x00C0 +#define mmCP_PFP_UCODE_DATA 0x00C1 +#define mmCP_PERFMON_CNTL 0x0444 +#define mmCP_PERFCOUNTER_SELECT 0x0445 +#define mmCP_PERFCOUNTER_LO 0x0446 +#define mmCP_PERFCOUNTER_HI 0x0447 +#define mmCP_BIN_MASK_LO 0x0454 +#define mmCP_BIN_MASK_HI 0x0455 +#define mmCP_BIN_SELECT_LO 0x0456 +#define mmCP_BIN_SELECT_HI 0x0457 +#define mmCP_NV_FLAGS_0 0x01EE +#define mmCP_NV_FLAGS_1 0x01EF +#define mmCP_NV_FLAGS_2 0x01F0 +#define mmCP_NV_FLAGS_3 0x01F1 +#define mmCP_STATE_DEBUG_INDEX 0x01EC +#define mmCP_STATE_DEBUG_DATA 0x01ED +#define mmCP_PROG_COUNTER 0x044B +#define mmCP_STAT 0x047F +#define mmBIOS_0_SCRATCH 0x0004 +#define mmBIOS_1_SCRATCH 0x0005 +#define mmBIOS_2_SCRATCH 0x0006 +#define mmBIOS_3_SCRATCH 0x0007 +#define mmBIOS_4_SCRATCH 0x0008 +#define mmBIOS_5_SCRATCH 0x0009 +#define mmBIOS_6_SCRATCH 0x000A +#define mmBIOS_7_SCRATCH 0x000B +#define mmBIOS_8_SCRATCH 0x0580 +#define mmBIOS_9_SCRATCH 0x0581 +#define mmBIOS_10_SCRATCH 0x0582 +#define mmBIOS_11_SCRATCH 0x0583 +#define mmBIOS_12_SCRATCH 0x0584 +#define mmBIOS_13_SCRATCH 0x0585 +#define mmBIOS_14_SCRATCH 0x0586 +#define mmBIOS_15_SCRATCH 0x0587 +#define mmCOHER_SIZE_PM4 0x0A29 +#define mmCOHER_BASE_PM4 0x0A2A +#define mmCOHER_STATUS_PM4 0x0A2B +#define mmCOHER_SIZE_HOST 0x0A2F +#define mmCOHER_BASE_HOST 0x0A30 +#define mmCOHER_STATUS_HOST 0x0A31 +#define mmCOHER_DEST_BASE_0 0x2006 +#define mmCOHER_DEST_BASE_1 0x2007 +#define mmCOHER_DEST_BASE_2 0x2008 +#define mmCOHER_DEST_BASE_3 0x2009 +#define mmCOHER_DEST_BASE_4 0x200A +#define mmCOHER_DEST_BASE_5 0x200B +#define mmCOHER_DEST_BASE_6 0x200C +#define mmCOHER_DEST_BASE_7 0x200D + + +// Registers from SC block + + + +// Registers from BC block + +#define mmRB_SURFACE_INFO 0x2000 +#define mmRB_COLOR_INFO 0x2001 +#define mmRB_DEPTH_INFO 0x2002 +#define mmRB_STENCILREFMASK 0x210D +#define mmRB_ALPHA_REF 0x210E +#define mmRB_COLOR_MASK 0x2104 +#define mmRB_BLEND_RED 0x2105 +#define mmRB_BLEND_GREEN 0x2106 +#define mmRB_BLEND_BLUE 0x2107 +#define mmRB_BLEND_ALPHA 0x2108 +#define mmRB_FOG_COLOR 0x2109 +#define mmRB_STENCILREFMASK_BF 0x210C +#define mmRB_DEPTHCONTROL 0x2200 +#define mmRB_BLENDCONTROL 0x2201 +#define mmRB_COLORCONTROL 0x2202 +#define mmRB_MODECONTROL 0x2208 +#define mmRB_COLOR_DEST_MASK 0x2326 +#define mmRB_COPY_CONTROL 0x2318 +#define mmRB_COPY_DEST_BASE 0x2319 +#define mmRB_COPY_DEST_PITCH 0x231A +#define mmRB_COPY_DEST_INFO 0x231B +#define mmRB_COPY_DEST_PIXEL_OFFSET 0x231C +#define mmRB_DEPTH_CLEAR 0x231D +#define mmRB_SAMPLE_COUNT_CTL 0x2324 +#define mmRB_SAMPLE_COUNT_ADDR 0x2325 +#define mmRB_BC_CONTROL 0x0F01 +#define mmRB_EDRAM_INFO 0x0F02 +#define mmRB_CRC_RD_PORT 0x0F0C +#define mmRB_CRC_CONTROL 0x0F0D +#define mmRB_CRC_MASK 0x0F0E +#define mmRB_PERFCOUNTER0_SELECT 0x0F04 +#define mmRB_PERFCOUNTER0_LOW 0x0F08 +#define mmRB_PERFCOUNTER0_HI 0x0F09 +#define mmRB_TOTAL_SAMPLES 0x0F0F +#define mmRB_ZPASS_SAMPLES 0x0F10 +#define mmRB_ZFAIL_SAMPLES 0x0F11 +#define mmRB_SFAIL_SAMPLES 0x0F12 +#define mmRB_DEBUG_0 0x0F26 +#define mmRB_DEBUG_1 0x0F27 +#define mmRB_DEBUG_2 0x0F28 +#define mmRB_DEBUG_3 0x0F29 +#define mmRB_DEBUG_4 0x0F2A +#define mmRB_FLAG_CONTROL 0x0F2B +#define mmRB_BC_SPARES 0x0F2C +#define mmBC_DUMMY_CRAYRB_ENUMS 0x0F15 +#define mmBC_DUMMY_CRAYRB_MOREENUMS 0x0F16 +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h new file mode 100644 index 000000000000..17379dcfa0e7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h @@ -0,0 +1,223 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_RANDOM_HEADER) +#define _yamato_RANDOM_HEADER + +/************************************************************* + * THIS FILE IS AUTOMATICALLY CREATED. DO NOT EDIT THIS FILE. + *************************************************************/ +/******************************************************* + * PA Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * VGT Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * RBBM Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * CP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +#endif /*_yamato_RANDOM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h new file mode 100644 index 000000000000..bcc28f133b08 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h @@ -0,0 +1,14280 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_REG_HEADER) +#define _yamato_REG_HEADER + + union PA_CL_VPORT_XSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_XOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VTE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_X_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int : 2; + unsigned int VTX_XY_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int PERFCOUNTER_REF : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_XY_FMT : 1; + unsigned int : 2; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_X_SCALE_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CLIP_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int CLIP_DISABLE : 1; + unsigned int : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int W_NAN_RETAIN : 1; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int W_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int : 1; + unsigned int CLIP_DISABLE : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int CLIP_VTX_REORDER_ENA : 1; + unsigned int : 27; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 27; + unsigned int CLIP_VTX_REORDER_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int : 28; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_VTX_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PIX_CENTER : 1; + unsigned int ROUND_MODE : 2; + unsigned int QUANT_MODE : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int QUANT_MODE : 3; + unsigned int ROUND_MODE : 2; + unsigned int PIX_CENTER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int HEIGHT : 16; + unsigned int WIDTH : 16; +#else /* !defined(qLittleEndian) */ + unsigned int WIDTH : 16; + unsigned int HEIGHT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_MINMAX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_SIZE : 16; + unsigned int MAX_SIZE : 16; +#else /* !defined(qLittleEndian) */ + unsigned int MAX_SIZE : 16; + unsigned int MIN_SIZE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int WIDTH : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int WIDTH : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_FACE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int BASE_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_SC_MODE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int CULL_FRONT : 1; + unsigned int CULL_BACK : 1; + unsigned int FACE : 1; + unsigned int POLY_MODE : 2; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int : 1; + unsigned int CLAMPED_FACENESS : 1; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int FACE_WRITE_ENABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACE_WRITE_ENABLE : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int CLAMPED_FACENESS : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLY_MODE : 2; + unsigned int FACE : 1; + unsigned int CULL_BACK : 1; + unsigned int CULL_FRONT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int WINDOW_X_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_X_OFFSET : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MSAA_NUM_SAMPLES : 3; + unsigned int : 10; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 10; + unsigned int MSAA_NUM_SAMPLES : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AA_MASK : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int AA_MASK : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE { + struct { +#if defined(qLittleEndian) + unsigned int LINE_PATTERN : 16; + unsigned int REPEAT_COUNT : 8; + unsigned int : 4; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int : 4; + unsigned int REPEAT_COUNT : 8; + unsigned int LINE_PATTERN : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int BRES_CNTL : 8; + unsigned int USE_BRES_CNTL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int LAST_PIXEL : 1; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int LAST_PIXEL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int USE_BRES_CNTL : 1; + unsigned int BRES_CNTL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 14; + unsigned int : 2; + unsigned int TL_Y : 14; + unsigned int : 1; + unsigned int WINDOW_OFFSET_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int WINDOW_OFFSET_DISABLE : 1; + unsigned int : 1; + unsigned int TL_Y : 14; + unsigned int : 2; + unsigned int TL_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 14; + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; + unsigned int BR_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 15; + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; + unsigned int TL_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 15; + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; + unsigned int BR_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY { + struct { +#if defined(qLittleEndian) + unsigned int VIZ_QUERY_ENA : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int : 1; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int VIZ_QUERY_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int STATUS_BITS : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS_BITS : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE_STATE { + struct { +#if defined(qLittleEndian) + unsigned int CURRENT_PTR : 4; + unsigned int : 4; + unsigned int CURRENT_COUNT : 8; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int CURRENT_COUNT : 8; + unsigned int : 4; + unsigned int CURRENT_PTR : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int CL_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CL_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SU_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SU_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SC_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SU_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SU_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int clip_ga_bc_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ALWAYS_ZERO : 12; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 12; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_ga_bc_fifo_write : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int clip_to_outsm_end_of_packet : 1; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_vert_vte_valid : 3; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int ALWAYS_ZERO : 8; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 8; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int clip_vert_vte_valid : 3; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_end_of_packet : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO1 : 21; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; +#else /* !defined(qLittleEndian) */ + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO1 : 21; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO0 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 6; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO3 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO0 : 24; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 24; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO2 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 4; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int clprim_in_back_event : 1; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int prim_back_valid : 1; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_fifo_full : 1; + unsigned int clip_priority_seq_indx_load : 2; +#else /* !defined(qLittleEndian) */ + unsigned int clip_priority_seq_indx_load : 2; + unsigned int outsm_clr_fifo_full : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int prim_back_valid : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_event : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_event_id : 6; +#else /* !defined(qLittleEndian) */ + unsigned int clprim_in_back_event_id : 6; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int vertval_bits_vertex_vertex_store_msb : 4; + unsigned int ALWAYS_ZERO : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 28; + unsigned int vertval_bits_vertex_vertex_store_msb : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int clip_priority_available_vte_out_clip : 2; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int primic_to_clprim_valid : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int primic_to_clprim_valid : 1; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_priority_available_vte_out_clip : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int sm0_clip_vert_cnt : 4; + unsigned int sm0_prim_end_state : 7; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_current_state : 7; + unsigned int ALWAYS_ZERO0 : 5; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 5; + unsigned int sm0_current_state : 7; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_prim_end_state : 7; + unsigned int sm0_clip_vert_cnt : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int nan_kill_flag : 4; + unsigned int position_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_aux_sel : 1; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_rd_aux_sel : 1; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int position_address : 3; + unsigned int nan_kill_flag : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 2; + unsigned int sx_to_pa_empty : 2; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int sx_pending_advance : 1; + unsigned int sx_receive_indx : 3; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int pasx_req_cnt : 2; + unsigned int param_cache_base : 7; +#else /* !defined(qLittleEndian) */ + unsigned int param_cache_base : 7; + unsigned int pasx_req_cnt : 2; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int sx_receive_indx : 3; + unsigned int sx_pending_advance : 1; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int sx_to_pa_empty : 2; + unsigned int ALWAYS_ZERO3 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int sx_sent : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_aux : 1; + unsigned int sx_request_indx : 6; + unsigned int req_active_verts : 7; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int req_active_verts_loaded : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_contents : 3; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_fifo_contents : 3; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int req_active_verts_loaded : 1; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int req_active_verts : 7; + unsigned int sx_request_indx : 6; + unsigned int sx_aux : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_sent : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vertex_fifo_entriesavailable : 4; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int current_state : 2; + unsigned int vertex_fifo_empty : 1; + unsigned int vertex_fifo_full : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vertex_fifo_full : 1; + unsigned int vertex_fifo_empty : 1; + unsigned int current_state : 2; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int vertex_fifo_entriesavailable : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int su_cntl_state : 5; + unsigned int pmode_state : 6; + unsigned int ge_stallb : 1; + unsigned int geom_enable : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int su_clip_rtr : 1; + unsigned int pfifo_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int geom_busy : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int geom_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int pfifo_busy : 1; + unsigned int su_clip_rtr : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int geom_enable : 1; + unsigned int ge_stallb : 1; + unsigned int pmode_state : 6; + unsigned int su_cntl_state : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort0_gated_17_4 : 14; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int y_sort0_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort1_gated_17_4 : 14; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int y_sort1_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort2_gated_17_4 : 14; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int y_sort2_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort0_gated : 11; + unsigned int null_prim_gated : 1; + unsigned int backfacing_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int clipped_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int xmajor_gated : 1; + unsigned int diamond_rule_gated : 2; + unsigned int type_gated : 3; + unsigned int fpov_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int event_gated : 1; + unsigned int eop_gated : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int eop_gated : 1; + unsigned int event_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int fpov_gated : 1; + unsigned int type_gated : 3; + unsigned int diamond_rule_gated : 2; + unsigned int xmajor_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int clipped_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int backfacing_gated : 1; + unsigned int null_prim_gated : 1; + unsigned int attr_indx_sort0_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort2_gated : 11; + unsigned int attr_indx_sort1_gated : 11; + unsigned int provoking_vtx_gated : 2; + unsigned int event_id_gated : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int event_id_gated : 5; + unsigned int provoking_vtx_gated : 2; + unsigned int attr_indx_sort1_gated : 11; + unsigned int attr_indx_sort2_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SC_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SC_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int pa_freeze_b1 : 1; + unsigned int pa_sc_valid : 1; + unsigned int pa_sc_phase : 3; + unsigned int cntx_cnt : 7; + unsigned int decr_cntx_cnt : 1; + unsigned int incr_cntx_cnt : 1; + unsigned int : 17; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 17; + unsigned int incr_cntx_cnt : 1; + unsigned int decr_cntx_cnt : 1; + unsigned int cntx_cnt : 7; + unsigned int pa_sc_phase : 3; + unsigned int pa_sc_valid : 1; + unsigned int pa_freeze_b1 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int em_state : 3; + unsigned int em1_data_ready : 1; + unsigned int em2_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int ef_data_ready : 1; + unsigned int ef_state : 2; + unsigned int pipe_valid : 1; + unsigned int : 21; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 21; + unsigned int pipe_valid : 1; + unsigned int ef_state : 2; + unsigned int ef_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int em2_data_ready : 1; + unsigned int em1_data_ready : 1; + unsigned int em_state : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int rc_rtr_dly : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int : 1; + unsigned int pipe_freeze_b : 1; + unsigned int prim_rts : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int stage0_rts : 1; + unsigned int phase_rts_dly : 1; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : 1; + unsigned int pass_empty_prim_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int event_s1 : 1; + unsigned int : 8; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 8; + unsigned int event_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int pass_empty_prim_s1 : 1; + unsigned int end_of_prim_s1_dly : 1; + unsigned int : 5; + unsigned int phase_rts_dly : 1; + unsigned int stage0_rts : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int prim_rts : 1; + unsigned int pipe_freeze_b : 1; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int rc_rtr_dly : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int x_curr_s1 : 11; + unsigned int y_curr_s1 : 11; + unsigned int : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 9; + unsigned int y_curr_s1 : 11; + unsigned int x_curr_s1 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int y_end_s1 : 14; + unsigned int y_start_s1 : 14; + unsigned int y_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int y_dir_s1 : 1; + unsigned int y_start_s1 : 14; + unsigned int y_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_5 { + struct { +#if defined(qLittleEndian) + unsigned int x_end_s1 : 14; + unsigned int x_start_s1 : 14; + unsigned int x_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int x_dir_s1 : 1; + unsigned int x_start_s1 : 14; + unsigned int x_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_6 { + struct { +#if defined(qLittleEndian) + unsigned int z_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int xy_ff_empty : 1; + unsigned int event_flag : 1; + unsigned int z_mask_needed : 1; + unsigned int state : 3; + unsigned int state_delayed : 3; + unsigned int data_valid : 1; + unsigned int data_valid_d : 1; + unsigned int tilex_delayed : 9; + unsigned int tiley_delayed : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int tiley_delayed : 9; + unsigned int tilex_delayed : 9; + unsigned int data_valid_d : 1; + unsigned int data_valid : 1; + unsigned int state_delayed : 3; + unsigned int state : 3; + unsigned int z_mask_needed : 1; + unsigned int event_flag : 1; + unsigned int xy_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int z_ff_empty : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_7 { + struct { +#if defined(qLittleEndian) + unsigned int event_flag : 1; + unsigned int deallocate : 3; + unsigned int fposition : 1; + unsigned int sr_prim_we : 1; + unsigned int last_tile : 1; + unsigned int tile_ff_we : 1; + unsigned int qs_data_valid : 1; + unsigned int qs_q0_y : 2; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_valid : 1; + unsigned int prim_ff_we : 1; + unsigned int tile_ff_re : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int last_quad_of_tile : 1; + unsigned int first_quad_of_tile : 1; + unsigned int first_quad_of_prim : 1; + unsigned int new_prim : 1; + unsigned int load_new_tile_data : 1; + unsigned int state : 2; + unsigned int fifos_ready : 1; + unsigned int : 6; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 6; + unsigned int fifos_ready : 1; + unsigned int state : 2; + unsigned int load_new_tile_data : 1; + unsigned int new_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int first_quad_of_tile : 1; + unsigned int last_quad_of_tile : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int tile_ff_re : 1; + unsigned int prim_ff_we : 1; + unsigned int qs_q0_valid : 1; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_y : 2; + unsigned int qs_data_valid : 1; + unsigned int tile_ff_we : 1; + unsigned int last_tile : 1; + unsigned int sr_prim_we : 1; + unsigned int fposition : 1; + unsigned int deallocate : 3; + unsigned int event_flag : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_8 { + struct { +#if defined(qLittleEndian) + unsigned int sample_last : 1; + unsigned int sample_mask : 4; + unsigned int sample_y : 2; + unsigned int sample_x : 2; + unsigned int sample_send : 1; + unsigned int next_cycle : 2; + unsigned int ez_sample_ff_full : 1; + unsigned int rb_sc_samp_rtr : 1; + unsigned int num_samples : 2; + unsigned int last_quad_of_tile : 1; + unsigned int last_quad_of_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int sample_we : 1; + unsigned int fposition : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int : 3; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 3; + unsigned int fw_prim_data_valid : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int fposition : 1; + unsigned int sample_we : 1; + unsigned int first_quad_of_prim : 1; + unsigned int last_quad_of_prim : 1; + unsigned int last_quad_of_tile : 1; + unsigned int num_samples : 2; + unsigned int rb_sc_samp_rtr : 1; + unsigned int ez_sample_ff_full : 1; + unsigned int next_cycle : 2; + unsigned int sample_send : 1; + unsigned int sample_x : 2; + unsigned int sample_y : 2; + unsigned int sample_mask : 4; + unsigned int sample_last : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_9 { + struct { +#if defined(qLittleEndian) + unsigned int rb_sc_send : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int fifo_data_ready : 1; + unsigned int early_z_enable : 1; + unsigned int mask_state : 2; + unsigned int next_ez_mask : 16; + unsigned int mask_ready : 1; + unsigned int drop_sample : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int drop_sample : 1; + unsigned int mask_ready : 1; + unsigned int next_ez_mask : 16; + unsigned int mask_state : 2; + unsigned int early_z_enable : 1; + unsigned int fifo_data_ready : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int rb_sc_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_10 { + struct { +#if defined(qLittleEndian) + unsigned int combined_sample_mask : 16; + unsigned int : 15; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 15; + unsigned int combined_sample_mask : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_11 { + struct { +#if defined(qLittleEndian) + unsigned int ez_sample_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int iterator_input_fz : 1; + unsigned int packer_send_quads : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_event : 1; + unsigned int next_state : 3; + unsigned int state : 3; + unsigned int stall : 1; + unsigned int : 16; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 16; + unsigned int stall : 1; + unsigned int state : 3; + unsigned int next_state : 3; + unsigned int packer_send_event : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_quads : 1; + unsigned int iterator_input_fz : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_sample_data_ready : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_12 { + struct { +#if defined(qLittleEndian) + unsigned int SQ_iterator_free_buff : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_qdhit0 : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int bc_output_xy_reg : 1; + unsigned int iter_phase_out : 2; + unsigned int iter_phase_reg : 2; + unsigned int iterator_SP_valid : 1; + unsigned int eopv_reg : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int iter_dx_end_of_prim : 1; + unsigned int : 7; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int eopv_reg : 1; + unsigned int iterator_SP_valid : 1; + unsigned int iter_phase_reg : 2; + unsigned int iter_phase_out : 2; + unsigned int bc_output_xy_reg : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int iter_qdhit0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int SQ_iterator_free_buff : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GFX_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DRAW_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_TYPE : 6; + unsigned int SOURCE_SELECT : 2; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int : 1; + unsigned int INDEX_SIZE : 1; + unsigned int NOT_EOP : 1; + unsigned int SMALL_INDEX : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int NUM_INDICES : 16; +#else /* !defined(qLittleEndian) */ + unsigned int NUM_INDICES : 16; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int SMALL_INDEX : 1; + unsigned int NOT_EOP : 1; + unsigned int INDEX_SIZE : 1; + unsigned int : 1; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int SOURCE_SELECT : 2; + unsigned int PRIM_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_EVENT_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int EVENT_TYPE : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int EVENT_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int SWAP_MODE : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SWAP_MODE : 2; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BIN_BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int FACENESS_FETCH : 1; + unsigned int FACENESS_RESET : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACENESS_RESET : 1; + unsigned int FACENESS_FETCH : 1; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MIN { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MAX { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_IMMED_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MAX_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MAX_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MAX_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MIN_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MIN_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_INDX_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int INDX_OFFSET : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int INDX_OFFSET : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VERTEX_REUSE_BLOCK_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_REUSE_DEPTH : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int VTX_REUSE_DEPTH : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_OUT_DEALLOC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int DEALLOC_DIST : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DEALLOC_DIST : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MULTI_PRIM_IB_RESET_INDX { + struct { +#if defined(qLittleEndian) + unsigned int RESET_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int RESET_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int MISC : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MISC : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VTX_VECT_EJECT_REG { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_COUNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int PRIM_COUNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_LAST_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VGT_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int VGT_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int VGT_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int te_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int out_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int grp_busy : 1; + unsigned int dma_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int rbiu_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int VGT_RBBM_busy : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int VGT_RBBM_busy : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int vgt_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int rbiu_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int dma_busy : 1; + unsigned int grp_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int out_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int te_grp_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int out_te_data_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int te_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_SQ_send : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int VGT_SQ_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int te_grp_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_te_data_read : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vgt_clk_en : 1; + unsigned int reg_fifos_clk_en : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int reg_fifos_clk_en : 1; + unsigned int vgt_clk_en : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int grp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int grp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG8 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG9 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int grp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int grp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int temp_derived_di_prim_type_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int di_state_sel_q : 1; + unsigned int last_decr_of_packet : 1; + unsigned int bin_valid : 1; + unsigned int read_block : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int last_bit_enable_q : 1; + unsigned int last_bit_end_di_q : 1; + unsigned int selected_data : 8; + unsigned int mask_input_data : 8; + unsigned int gap_q : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int grp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int grp_trigger : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int gap_q : 1; + unsigned int mask_input_data : 8; + unsigned int selected_data : 8; + unsigned int last_bit_end_di_q : 1; + unsigned int last_bit_enable_q : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int read_block : 1; + unsigned int bin_valid : 1; + unsigned int last_decr_of_packet : 1; + unsigned int di_state_sel_q : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_prim_type_t0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int bgrp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int bgrp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int bgrp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int bgrp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int bgrp_cull_fetch_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int rst_last_bit : 1; + unsigned int current_state_q : 1; + unsigned int old_state_q : 1; + unsigned int old_state_en : 1; + unsigned int prev_last_bit_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int load_empty_reg : 1; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int load_empty_reg : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int prev_last_bit_q : 1; + unsigned int old_state_en : 1; + unsigned int old_state_q : 1; + unsigned int current_state_q : 1; + unsigned int rst_last_bit : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int bgrp_cull_fetch_fifo_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int save_read_q : 1; + unsigned int extend_read_q : 1; + unsigned int grp_indx_size : 2; + unsigned int cull_prim_true : 1; + unsigned int reset_bit2_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int first_reg_first_q : 1; + unsigned int check_second_reg : 1; + unsigned int check_first_reg : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int roll_over_msk_q : 1; + unsigned int max_msk_ptr_q : 7; + unsigned int min_msk_ptr_q : 7; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int min_msk_ptr_q : 7; + unsigned int max_msk_ptr_q : 7; + unsigned int roll_over_msk_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int check_first_reg : 1; + unsigned int check_second_reg : 1; + unsigned int first_reg_first_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int reset_bit2_q : 1; + unsigned int cull_prim_true : 1; + unsigned int grp_indx_size : 2; + unsigned int extend_read_q : 1; + unsigned int save_read_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int dma_data_fifo_mem_raddr : 6; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_mem_full : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int bin_mem_full : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_mem_empty : 1; + unsigned int start_bin_req : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int dma_req_xfer : 1; + unsigned int have_valid_bin_req : 1; + unsigned int have_valid_dma_req : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int have_valid_dma_req : 1; + unsigned int have_valid_bin_req : 1; + unsigned int dma_req_xfer : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int start_bin_req : 1; + unsigned int bin_mem_empty : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_mem_full : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_mem_full : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_data_fifo_mem_raddr : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int prim_side_indx_valid : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int prim_buffer_empty : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_full : 1; + unsigned int indx_buffer_empty : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_full : 1; + unsigned int hold_prim : 1; + unsigned int sent_cnt : 4; + unsigned int start_of_vtx_vector : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int out_trigger : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int out_trigger : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int start_of_vtx_vector : 1; + unsigned int sent_cnt : 4; + unsigned int hold_prim : 1; + unsigned int indx_buffer_full : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_empty : 1; + unsigned int prim_buffer_full : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_empty : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int prim_side_indx_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int null_terminate_vtx_vector : 1; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int alloc_counter_q : 3; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_dealloc_distance_q : 4; + unsigned int new_packet_q : 1; + unsigned int new_allocate_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int inserted_null_prim_q : 1; + unsigned int insert_null_prim : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_thread_size : 1; + unsigned int : 4; + unsigned int out_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int out_trigger : 1; + unsigned int : 4; + unsigned int buffered_thread_size : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int insert_null_prim : 1; + unsigned int inserted_null_prim_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int new_allocate_q : 1; + unsigned int new_packet_q : 1; + unsigned int curr_dealloc_distance_q : 4; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int alloc_counter_q : 3; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int null_terminate_vtx_vector : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int L2_INVALIDATE : 1; + unsigned int : 17; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 11; + unsigned int TC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_BUSY : 1; + unsigned int : 11; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 17; + unsigned int L2_INVALIDATE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int SPARE : 23; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 23; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP_TC_CLKGATE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TP_BUSY_EXTEND : 3; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int TP_BUSY_EXTEND : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TPC_INPUT_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int : 1; + unsigned int TF_TW_RTR : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int : 1; + unsigned int TA_TB_RTR : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TPC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TPC_BUSY : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TB_RTR : 1; + unsigned int : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TF_TW_RTR : 1; + unsigned int : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int LOD_CNTL : 2; + unsigned int IC_CTR : 2; + unsigned int WALKER_CNTL : 4; + unsigned int ALIGNER_CNTL : 3; + unsigned int : 1; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 3; + unsigned int WALKER_STATE : 10; + unsigned int ALIGNER_STATE : 2; + unsigned int : 1; + unsigned int REG_CLK_EN : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int SQ_TP_WAKEUP : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SQ_TP_WAKEUP : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int : 1; + unsigned int ALIGNER_STATE : 2; + unsigned int WALKER_STATE : 10; + unsigned int : 3; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 1; + unsigned int ALIGNER_CNTL : 3; + unsigned int WALKER_CNTL : 4; + unsigned int IC_CTR : 2; + unsigned int LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int UNUSED : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int UNUSED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_PRECISION : 1; + unsigned int SPARE : 31; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 31; + unsigned int BLEND_PRECISION : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TP_INPUT_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int : 1; + unsigned int IN_LC_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TP_BUSY : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int IN_LC_RTS : 1; + unsigned int : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int Q_LOD_CNTL : 2; + unsigned int : 1; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int REG_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int TP_CLK_EN : 1; + unsigned int Q_WALKER_CNTL : 4; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int Q_WALKER_CNTL : 4; + unsigned int TP_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int : 1; + unsigned int Q_LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TT_MODE : 1; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int SPARE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 30; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int TT_MODE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 6; + unsigned int not_MH_TC_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_FG0_rtr : 1; + unsigned int : 3; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int TCB_ff_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int PF0_stall : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int TPC_full : 1; + unsigned int not_TPC_rtr : 1; + unsigned int tca_state_rts : 1; + unsigned int tca_rts : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int tca_rts : 1; + unsigned int tca_state_rts : 1; + unsigned int not_TPC_rtr : 1; + unsigned int TPC_full : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int PF0_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCB_ff_stall : 1; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int : 3; + unsigned int not_FG0_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_MH_TC_rtr : 1; + unsigned int : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_FIFO_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tp0_full : 1; + unsigned int : 3; + unsigned int tpc_full : 1; + unsigned int load_tpc_fifo : 1; + unsigned int load_tp_fifos : 1; + unsigned int FW_full : 1; + unsigned int not_FW_rtr0 : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_tpc_rtr : 1; + unsigned int FW_tpc_rts : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int FW_tpc_rts : 1; + unsigned int not_FW_tpc_rtr : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_rtr0 : 1; + unsigned int FW_full : 1; + unsigned int load_tp_fifos : 1; + unsigned int load_tpc_fifo : 1; + unsigned int tpc_full : 1; + unsigned int : 3; + unsigned int tp0_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_PROBE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int ProbeFilter_stall : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int ProbeFilter_stall : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_TPC_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int captue_state_rts : 1; + unsigned int capture_tca_rts : 1; + unsigned int : 18; +#else /* !defined(qLittleEndian) */ + unsigned int : 18; + unsigned int capture_tca_rts : 1; + unsigned int captue_state_rts : 1; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_CORE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int access512 : 1; + unsigned int tiled : 1; + unsigned int : 2; + unsigned int opcode : 3; + unsigned int : 1; + unsigned int format : 6; + unsigned int : 2; + unsigned int sector_format : 5; + unsigned int : 3; + unsigned int sector_format512 : 3; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int sector_format512 : 3; + unsigned int : 3; + unsigned int sector_format : 5; + unsigned int : 2; + unsigned int format : 6; + unsigned int : 1; + unsigned int opcode : 3; + unsigned int : 2; + unsigned int tiled : 1; + unsigned int access512 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG1_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG2_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG3_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int left_done : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int no_sectors_to_go : 1; + unsigned int update_left : 1; + unsigned int sector_mask_left_count_q : 5; + unsigned int sector_mask_left_q : 16; + unsigned int valid_left_q : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int valid_left_q : 1; + unsigned int sector_mask_left_q : 16; + unsigned int sector_mask_left_count_q : 5; + unsigned int update_left : 1; + unsigned int no_sectors_to_go : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int left_done : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_WALKER_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int quad_sel_left : 2; + unsigned int set_sel_left : 2; + unsigned int : 3; + unsigned int right_eq_left : 1; + unsigned int ff_fg_type512 : 3; + unsigned int busy : 1; + unsigned int setquads_to_send : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int setquads_to_send : 4; + unsigned int busy : 1; + unsigned int ff_fg_type512 : 3; + unsigned int right_eq_left : 1; + unsigned int : 3; + unsigned int set_sel_left : 2; + unsigned int quad_sel_left : 2; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_PIPE0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tc0_arb_rts : 1; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc_arb_format : 12; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_request_type : 2; + unsigned int busy : 1; + unsigned int fgo_busy : 1; + unsigned int ga_busy : 1; + unsigned int mc_sel_q : 2; + unsigned int valid_q : 1; + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; + unsigned int valid_q : 1; + unsigned int mc_sel_q : 2; + unsigned int ga_busy : 1; + unsigned int fgo_busy : 1; + unsigned int busy : 1; + unsigned int tc_arb_request_type : 2; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_format : 12; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc0_arb_rts : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_INPUT0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int : 2; + unsigned int valid_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int last_send_q1 : 1; + unsigned int ip_send : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ipbuf_busy : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int ipbuf_busy : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ip_send : 1; + unsigned int last_send_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int valid_q1 : 1; + unsigned int : 2; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DEGAMMA_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int dgmm_ftfconv_dgmmen : 2; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_pstate : 1; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int dgmm_pstate : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ftfconv_dgmmen : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTMUX_SCTARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 9; + unsigned int pstate : 1; + unsigned int sctrmx_rtr : 1; + unsigned int dxtc_rtr : 1; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : 1; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dcmp_mux_send : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int dcmp_mux_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int sctrarb_multcyl_send : 1; + unsigned int : 3; + unsigned int dxtc_rtr : 1; + unsigned int sctrmx_rtr : 1; + unsigned int pstate : 1; + unsigned int : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTC_ARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int n0_stall : 1; + unsigned int pstate : 1; + unsigned int arb_dcmp01_last_send : 1; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_send : 1; + unsigned int n0_dxt2_4_types : 1; +#else /* !defined(qLittleEndian) */ + unsigned int n0_dxt2_4_types : 1; + unsigned int arb_dcmp01_send : 1; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_last_send : 1; + unsigned int pstate : 1; + unsigned int n0_stall : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int : 11; + unsigned int not_incoming_rtr : 1; +#else /* !defined(qLittleEndian) */ + unsigned int not_incoming_rtr : 1; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int rl_sg_sector_format : 8; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int : 2; + unsigned int stageN1_valid_q : 1; + unsigned int : 7; + unsigned int read_cache_q : 1; + unsigned int cache_read_RTR : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int busy : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int busy : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int cache_read_RTR : 1; + unsigned int read_cache_q : 1; + unsigned int : 7; + unsigned int stageN1_valid_q : 1; + unsigned int : 2; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_sector_format : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int fifo_busy : 1; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int write_enable : 1; + unsigned int fifo_write_ptr : 7; + unsigned int fifo_read_ptr : 7; + unsigned int : 2; + unsigned int cache_read_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int cache_read_busy : 1; + unsigned int : 2; + unsigned int fifo_read_ptr : 7; + unsigned int fifo_write_ptr : 7; + unsigned int write_enable : 1; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int fifo_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_GPR_MANAGEMENT { + struct { +#if defined(qLittleEndian) + unsigned int REG_DYNAMIC : 1; + unsigned int : 3; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 1; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 1; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 3; + unsigned int REG_DYNAMIC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FLOW_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int INPUT_ARBITRATION_POLICY : 2; + unsigned int : 2; + unsigned int ONE_THREAD : 1; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int CF_WR_BASE : 4; + unsigned int NO_PV_PS : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_PV_PS : 1; + unsigned int CF_WR_BASE : 4; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int ONE_THREAD : 1; + unsigned int : 2; + unsigned int INPUT_ARBITRATION_POLICY : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INST_STORE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int INST_BASE_PIX : 12; + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; + unsigned int INST_BASE_PIX : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_RESOURCE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int VTX_THREAD_BUF_ENTRIES : 8; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int VTX_THREAD_BUF_ENTRIES : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_EO_RT { + struct { +#if defined(qLittleEndian) + unsigned int EO_CONSTANTS_RT : 8; + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; + unsigned int EO_CONSTANTS_RT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC { + struct { +#if defined(qLittleEndian) + unsigned int DB_ALUCST_SIZE : 11; + unsigned int : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int DB_READ_CTX : 1; + unsigned int RESERVED : 2; + unsigned int DB_READ_MEMORY : 2; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_READ_MEMORY : 2; + unsigned int RESERVED : 2; + unsigned int DB_READ_CTX : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int : 1; + unsigned int DB_ALUCST_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TIMEBASE : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int SPARE : 8; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int TIMEBASE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PERCENT_BUSY : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERCENT_BUSY : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INPUT_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_THREAD_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int RESERVED : 2; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int RESERVED : 2; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_MASK : 1; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int PS_WATCHDOG_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_TIMEOUT : 1; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int PS_WATCHDOG_TIMEOUT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_ACK : 1; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int PS_WATCHDOG_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_INPUT_FSM { + struct { +#if defined(qLittleEndian) + unsigned int VC_VSR_LD : 3; + unsigned int RESERVED : 1; + unsigned int VC_GPR_LD : 4; + unsigned int PC_PISM : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_AS : 3; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_GPR_SIZE : 8; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PC_GPR_SIZE : 8; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_AS : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_PISM : 3; + unsigned int VC_GPR_LD : 4; + unsigned int RESERVED : 1; + unsigned int VC_VSR_LD : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_CONST_MGR_FSM { + struct { +#if defined(qLittleEndian) + unsigned int TEX_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int TEX_CONST_EVENT_STATE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TP_FSM { + struct { +#if defined(qLittleEndian) + unsigned int EX_TP : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_TP : 4; + unsigned int IF_TP : 3; + unsigned int RESERVED1 : 1; + unsigned int TIS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED5 : 2; + unsigned int ARB_TR_TP : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_TP : 3; + unsigned int RESERVED5 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int TIS_TP : 2; + unsigned int RESERVED1 : 1; + unsigned int IF_TP : 3; + unsigned int CF_TP : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_TP : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_EXP_ALLOC { + struct { +#if defined(qLittleEndian) + unsigned int POS_BUF_AVAIL : 4; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int EA_BUF_AVAIL : 3; + unsigned int RESERVED : 1; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int RESERVED : 1; + unsigned int EA_BUF_AVAIL : 3; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int POS_BUF_AVAIL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PTR_BUFF { + struct { +#if defined(qLittleEndian) + unsigned int END_OF_BUFFER : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int SC_EVENT_ID : 5; + unsigned int QUAL_EVENT : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int EF_EMPTY : 1; + unsigned int VTX_SYNC_CNT : 11; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int VTX_SYNC_CNT : 11; + unsigned int EF_EMPTY : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int QUAL_EVENT : 1; + unsigned int SC_EVENT_ID : 5; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int END_OF_BUFFER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_VTX { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int VTX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_PIX { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int PIX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TB_STATUS_SEL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TB_STATUS_REG_SEL : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int : 1; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int DISABLE_STRICT_CTX_SYNC : 1; +#else /* !defined(qLittleEndian) */ + unsigned int DISABLE_STRICT_CTX_SYNC : 1; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATUS_REG_SEL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int VTX_HEAD_PTR_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int SX_EVENT_FULL : 1; + unsigned int BUSY_Q : 1; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int BUSY_Q : 1; + unsigned int SX_EVENT_FULL : 1; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int VTX_HEAD_PTR_Q : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_1 { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_PTR : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int VS_DONE_PTR : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATUS_REG { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATUS_REG : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATUS_REG : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_HEAD_PTR : 6; + unsigned int TAIL_PTR : 6; + unsigned int FULL_CNT : 7; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BUSY : 1; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int FULL_CNT : 7; + unsigned int TAIL_PTR : 6; + unsigned int PIX_HEAD_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_1 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_2 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_3 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int VECTOR_RESULT : 6; + unsigned int VECTOR_DST_REL : 1; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int SCALAR_DST_REL : 1; + unsigned int EXPORT_DATA : 1; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_CLAMP : 1; + unsigned int SCALAR_OPCODE : 6; +#else /* !defined(qLittleEndian) */ + unsigned int SCALAR_OPCODE : 6; + unsigned int SCALAR_CLAMP : 1; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int EXPORT_DATA : 1; + unsigned int SCALAR_DST_REL : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int VECTOR_DST_REL : 1; + unsigned int VECTOR_RESULT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int PRED_SELECT : 2; + unsigned int RELATIVE_ADDR : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int CONST_0_REL_ABS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CONST_0_REL_ABS : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int RELATIVE_ADDR : 1; + unsigned int PRED_SELECT : 2; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_R : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_2 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_REG_PTR : 6; + unsigned int REG_SELECT_C : 1; + unsigned int REG_ABS_MOD_C : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_SELECT_B : 1; + unsigned int REG_ABS_MOD_B : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_SELECT_A : 1; + unsigned int REG_ABS_MOD_A : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int SRC_C_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_A_SEL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_A_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_C_SEL : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int REG_ABS_MOD_A : 1; + unsigned int REG_SELECT_A : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_ABS_MOD_B : 1; + unsigned int REG_SELECT_B : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_ABS_MOD_C : 1; + unsigned int REG_SELECT_C : 1; + unsigned int SRC_C_REG_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_1 { + struct { +#if defined(qLittleEndian) + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; +#else /* !defined(qLittleEndian) */ + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_2 { + struct { +#if defined(qLittleEndian) + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 6; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_1 : 11; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 11; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_0 : 6; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 11; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 6; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED_0 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_2 { + struct { +#if defined(qLittleEndian) + unsigned int LOOP_ID : 5; + unsigned int RESERVED : 22; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED : 22; + unsigned int LOOP_ID : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 3; + unsigned int FORCE_CALL : 1; + unsigned int PREDICATED_JMP : 1; + unsigned int RESERVED_1 : 17; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 17; + unsigned int PREDICATED_JMP : 1; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_0 : 3; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 1; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 3; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_2 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_2 : 2; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_1 : 3; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 17; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED : 17; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_0 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 4; + unsigned int RESERVED : 28; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 28; + unsigned int SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 8; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; + unsigned int SIZE : 4; + unsigned int RESERVED_1 : 12; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 12; + unsigned int SIZE : 4; + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 24; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int CONST_INDEX : 5; + unsigned int TX_COORD_DENORM : 1; + unsigned int SRC_SEL_X : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_Z : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL_Z : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_X : 2; + unsigned int TX_COORD_DENORM : 1; + unsigned int CONST_INDEX : 5; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int MAG_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MIP_FILTER : 2; + unsigned int ANISO_FILTER : 3; + unsigned int ARBITRARY_FILTER : 3; + unsigned int VOL_MAG_FILTER : 2; + unsigned int VOL_MIN_FILTER : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int USE_REG_LOD : 2; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int USE_REG_LOD : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int VOL_MIN_FILTER : 2; + unsigned int VOL_MAG_FILTER : 2; + unsigned int ARBITRARY_FILTER : 3; + unsigned int ANISO_FILTER : 3; + unsigned int MIP_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MAG_FILTER : 2; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int USE_REG_GRADIENTS : 1; + unsigned int SAMPLE_LOCATION : 1; + unsigned int LOD_BIAS : 7; + unsigned int UNUSED : 7; + unsigned int OFFSET_X : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_Z : 5; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int OFFSET_Z : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_X : 5; + unsigned int UNUSED : 7; + unsigned int LOD_BIAS : 7; + unsigned int SAMPLE_LOCATION : 1; + unsigned int USE_REG_GRADIENTS : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int MUST_BE_ONE : 1; + unsigned int CONST_INDEX : 5; + unsigned int CONST_INDEX_SEL : 2; + unsigned int : 3; + unsigned int SRC_SEL : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL : 2; + unsigned int : 3; + unsigned int CONST_INDEX_SEL : 2; + unsigned int CONST_INDEX : 5; + unsigned int MUST_BE_ONE : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int STRIDE : 8; + unsigned int : 8; + unsigned int OFFSET : 8; + unsigned int : 7; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int : 7; + unsigned int OFFSET : 8; + unsigned int : 8; + unsigned int STRIDE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int TYPE : 1; + unsigned int STATE : 1; + unsigned int BASE_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDRESS : 30; + unsigned int STATE : 1; + unsigned int TYPE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int ENDIAN_SWAP : 2; + unsigned int LIMIT_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int LIMIT_ADDRESS : 30; + unsigned int ENDIAN_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_PROGRAM_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int VS_CF_SIZE : 11; + unsigned int : 1; + unsigned int PS_CF_SIZE : 11; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int PS_CF_SIZE : 11; + unsigned int : 1; + unsigned int VS_CF_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INTERPOLATOR_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_SHADE : 16; + unsigned int SAMPLING_PATTERN : 16; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLING_PATTERN : 16; + unsigned int PARAM_SHADE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PROGRAM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VS_NUM_REG : 6; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_RESOURCE : 1; + unsigned int PS_RESOURCE : 1; + unsigned int PARAM_GEN : 1; + unsigned int GEN_INDEX_PIX : 1; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int PS_EXPORT_MODE : 4; + unsigned int GEN_INDEX_VTX : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GEN_INDEX_VTX : 1; + unsigned int PS_EXPORT_MODE : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int GEN_INDEX_PIX : 1; + unsigned int PARAM_GEN : 1; + unsigned int PS_RESOURCE : 1; + unsigned int VS_RESOURCE : 1; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_NUM_REG : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_0 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_0 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_7 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_7 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_0 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_1 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_8 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_15 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_15 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_8 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONTEXT_MISC { + struct { +#if defined(qLittleEndian) + unsigned int INST_PRED_OPTIMIZE : 1; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int : 4; + unsigned int PARAM_GEN_POS : 8; + unsigned int PERFCOUNTER_REF : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int TX_CACHE_SEL : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int TX_CACHE_SEL : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int PARAM_GEN_POS : 8; + unsigned int : 4; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int INST_PRED_OPTIMIZE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RD_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RD_BASE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int RD_BASE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_0 { + struct { +#if defined(qLittleEndian) + unsigned int DB_PROB_ON : 1; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 5; + unsigned int DB_PROB_COUNT : 8; +#else /* !defined(qLittleEndian) */ + unsigned int DB_PROB_COUNT : 8; + unsigned int : 5; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ON : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_1 { + struct { +#if defined(qLittleEndian) + unsigned int DB_ON_PIX : 1; + unsigned int DB_ON_VTX : 1; + unsigned int : 6; + unsigned int DB_INST_COUNT : 8; + unsigned int DB_BREAK_ADDR : 11; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int DB_BREAK_ADDR : 11; + unsigned int DB_INST_COUNT : 8; + unsigned int : 6; + unsigned int DB_ON_VTX : 1; + unsigned int DB_ON_PIX : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_ARBITER_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int SAME_PAGE_LIMIT : 6; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L2_ARB_CONTROL : 1; + unsigned int PAGE_SIZE : 3; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int PAGE_SIZE : 3; + unsigned int L2_ARB_CONTROL : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int SAME_PAGE_LIMIT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_CLNT_AXI_ID_REUSE { + struct { +#if defined(qLittleEndian) + unsigned int CPw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int PAw_ID : 3; + unsigned int : 17; +#else /* !defined(qLittleEndian) */ + unsigned int : 17; + unsigned int PAw_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int CPw_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_READ_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int INDEX : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int INDEX : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_HALT_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int AXI_HALT : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int AXI_HALT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int MH_BUSY : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int CP_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int TC_REQUEST : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TCD_FULL : 1; + unsigned int RB_REQUEST : 1; + unsigned int PA_REQUEST : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int WDB_FULL : 1; + unsigned int AXI_AVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int AXI_RDY_ENA : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_AVALID : 1; + unsigned int WDB_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int PA_REQUEST : 1; + unsigned int RB_REQUEST : 1; + unsigned int TCD_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int CP_REQUEST : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int MH_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_WRITE_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_BLEN_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_written : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_BLEN_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_WRITE_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_CLNT_tag : 3; + unsigned int RDC_RID : 3; + unsigned int RDC_RRESP : 2; + unsigned int MH_CP_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_PA_writeclean : 1; + unsigned int BRC_BID : 3; + unsigned int BRC_BRESP : 2; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BRC_BRESP : 2; + unsigned int BRC_BID : 3; + unsigned int MH_PA_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_CP_writeclean : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RID : 3; + unsigned int MH_CLNT_tag : 3; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_send : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_ad_31_5 : 27; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG06 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG07 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG08 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int PA_MH_be : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int PA_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int CP_MH_be : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 3; + unsigned int VGT_MH_send : 1; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int VGT_MH_ad_31_5 : 27; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_send : 1; + unsigned int ALWAYS_ZERO : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_MH_addr_31_5 : 27; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_send : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_info : 25; + unsigned int TC_MH_send : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_info : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int MH_TC_mcinfo : 25; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int TC_MH_written : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int TC_MH_written : 1; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int MH_TC_mcinfo : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_ADDR_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_ADDR_31_5 : 27; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ROQ_INFO : 25; + unsigned int TC_ROQ_SEND : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_INFO : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int RB_MH_send : 1; + unsigned int RB_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_addr_31_5 : 27; + unsigned int RB_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int PA_MH_send : 1; + unsigned int PA_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_addr_31_5 : 27; + unsigned int PA_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG19 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_2_0 : 3; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_0 : 2; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int RID_q : 3; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int RID_q : 3; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int ARLEN_q_1_0 : 2; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_2_0 : 3; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG22 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_1_0 : 2; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_1 : 1; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int WSTRB_q : 8; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WSTRB_q : 8; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int ARLEN_q_1_1 : 1; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_1_0 : 2; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG23 { + struct { +#if defined(qLittleEndian) + unsigned int ARC_CTRL_RE_q : 1; + unsigned int CTRL_ARC_ID : 3; + unsigned int CTRL_ARC_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int CTRL_ARC_PAD : 28; + unsigned int CTRL_ARC_ID : 3; + unsigned int ARC_CTRL_RE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG24 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int REG_A : 14; + unsigned int REG_RE : 1; + unsigned int REG_WE : 1; + unsigned int BLOCK_RS : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BLOCK_RS : 1; + unsigned int REG_WE : 1; + unsigned int REG_RE : 1; + unsigned int REG_A : 14; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG25 { + struct { +#if defined(qLittleEndian) + unsigned int REG_WD : 32; +#else /* !defined(qLittleEndian) */ + unsigned int REG_WD : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG26 { + struct { +#if defined(qLittleEndian) + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int CNT_q : 6; + unsigned int TCD_EMPTY_q : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int BRC_VALID : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BRC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int RDC_VALID : 1; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TCD_EMPTY_q : 1; + unsigned int CNT_q : 6; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_RBBM_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG27 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_FP_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int ARB_WINNER_q : 3; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int ARB_WINNER_q : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF2_FP_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG28 { + struct { +#if defined(qLittleEndian) + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; +#else /* !defined(qLittleEndian) */ + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG29 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int LEAST_RECENT_d : 3; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CLNT_REQ : 5; + unsigned int RECENT_d_0 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_4 : 3; +#else /* !defined(qLittleEndian) */ + unsigned int RECENT_d_4 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_0 : 3; + unsigned int CLNT_REQ : 5; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int LEAST_RECENT_d : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int EFF2_LRU_WINNER_out : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG30 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ARB_HOLD : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int WBURST_ACTIVE : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WINNER : 3; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int WBURST_IP_q : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_ACTIVE : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ARB_HOLD : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG31 { + struct { +#if defined(qLittleEndian) + unsigned int RF_ARBITER_CONFIG_q : 26; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int RF_ARBITER_CONFIG_q : 26; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG32 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int ROQ_VALID_q : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG33 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int ROQ_VALID_d : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_d : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG34 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int NON_SAME_ROW_BANK_REQ : 8; +#else /* !defined(qLittleEndian) */ + unsigned int NON_SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int SAME_ROW_BANK_WIN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG35 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_ADDR_0 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_0 : 27; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG36 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_ADDR_1 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_1 : 27; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG37 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_ADDR_2 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_2 : 27; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG38 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_ADDR_3 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_3 : 27; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG39 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_ADDR_4 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_4 : 27; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG40 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_ADDR_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_5 : 27; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG41 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_ADDR_6 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_6 : 27; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG42 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_ADDR_7 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_7 : 27; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG43 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_REG_WE_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int MMU_RTR : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_WRITE : 1; + unsigned int MMU_BLEN : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int MMU_BLEN : 1; + unsigned int MMU_WRITE : 1; + unsigned int MMU_ID : 3; + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int MMU_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG44 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_VAD_q : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_VAD_q : 28; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG45 { + struct { +#if defined(qLittleEndian) + unsigned int MMU_WE : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_PAD : 28; + unsigned int MMU_ID : 3; + unsigned int MMU_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG46 { + struct { +#if defined(qLittleEndian) + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int ARB_WLAST : 1; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WSTRB : 8; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WSTRB : 8; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int ARB_WLAST : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG47 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG48 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG49 { + struct { +#if defined(qLittleEndian) + unsigned int CTRL_ARC_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int INFLT_LIMIT_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int INFLT_LIMIT_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int CTRL_ARC_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG50 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RRESP : 2; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int CNT_HOLD_q1 : 1; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int CNT_HOLD_q1 : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG51 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_PAGE_FAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RF_MMU_PAGE_FAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG52 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int client_behavior_q : 2; +#else /* !defined(qLittleEndian) */ + unsigned int client_behavior_q : 2; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG53 { + struct { +#if defined(qLittleEndian) + unsigned int stage1_valid : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int MMU_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int REQ_VA_OFFSET_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA_OFFSET_q : 16; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_MISS : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int stage1_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG54 { + struct { +#if defined(qLittleEndian) + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int stage1_valid : 1; + unsigned int stage2_valid : 1; + unsigned int client_behavior_q : 2; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int TAG_valid_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int TAG_valid_q : 16; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int client_behavior_q : 2; + unsigned int stage2_valid : 1; + unsigned int stage1_valid : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG55 { + struct { +#if defined(qLittleEndian) + unsigned int TAG0_VA : 13; + unsigned int TAG_valid_q_0 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG1_VA : 13; + unsigned int TAG_valid_q_1 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_1 : 1; + unsigned int TAG1_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_0 : 1; + unsigned int TAG0_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG56 { + struct { +#if defined(qLittleEndian) + unsigned int TAG2_VA : 13; + unsigned int TAG_valid_q_2 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG3_VA : 13; + unsigned int TAG_valid_q_3 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_3 : 1; + unsigned int TAG3_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_2 : 1; + unsigned int TAG2_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG57 { + struct { +#if defined(qLittleEndian) + unsigned int TAG4_VA : 13; + unsigned int TAG_valid_q_4 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG5_VA : 13; + unsigned int TAG_valid_q_5 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_5 : 1; + unsigned int TAG5_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_4 : 1; + unsigned int TAG4_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG58 { + struct { +#if defined(qLittleEndian) + unsigned int TAG6_VA : 13; + unsigned int TAG_valid_q_6 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG7_VA : 13; + unsigned int TAG_valid_q_7 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_7 : 1; + unsigned int TAG7_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_6 : 1; + unsigned int TAG6_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG59 { + struct { +#if defined(qLittleEndian) + unsigned int TAG8_VA : 13; + unsigned int TAG_valid_q_8 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG9_VA : 13; + unsigned int TAG_valid_q_9 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_9 : 1; + unsigned int TAG9_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_8 : 1; + unsigned int TAG8_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG60 { + struct { +#if defined(qLittleEndian) + unsigned int TAG10_VA : 13; + unsigned int TAG_valid_q_10 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG11_VA : 13; + unsigned int TAG_valid_q_11 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_11 : 1; + unsigned int TAG11_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_10 : 1; + unsigned int TAG10_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG61 { + struct { +#if defined(qLittleEndian) + unsigned int TAG12_VA : 13; + unsigned int TAG_valid_q_12 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG13_VA : 13; + unsigned int TAG_valid_q_13 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_13 : 1; + unsigned int TAG13_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_12 : 1; + unsigned int TAG12_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG62 { + struct { +#if defined(qLittleEndian) + unsigned int TAG14_VA : 13; + unsigned int TAG_valid_q_14 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG15_VA : 13; + unsigned int TAG_valid_q_15 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_15 : 1; + unsigned int TAG15_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_14 : 1; + unsigned int TAG14_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG63 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MMU_ENABLE : 1; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int RESERVED1 : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int RESERVED1 : 2; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int MMU_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_VA_RANGE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_64KB_REGIONS : 12; + unsigned int VA_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int VA_BASE : 20; + unsigned int NUM_64KB_REGIONS : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PT_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int PT_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int PT_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PAGE_FAULT { + struct { +#if defined(qLittleEndian) + unsigned int PAGE_FAULT : 1; + unsigned int OP_TYPE : 1; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int AXI_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int REQ_VA : 20; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA : 20; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int RESERVED1 : 1; + unsigned int AXI_ID : 3; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int OP_TYPE : 1; + unsigned int PAGE_FAULT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_TRAN_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int TRAN_ERROR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TRAN_ERROR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_INVALIDATE { + struct { +#if defined(qLittleEndian) + unsigned int INVALIDATE_ALL : 1; + unsigned int INVALIDATE_TC : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int INVALIDATE_TC : 1; + unsigned int INVALIDATE_ALL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_END { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_END : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_END : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union WAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_2D_IDLE : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int : 2; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 2; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLE : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_ISYNC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int CMDFIFO_AVAIL : 5; + unsigned int TC_BUSY : 1; + unsigned int : 2; + unsigned int HIRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int MH_BUSY : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int : 1; + unsigned int SX_BUSY : 1; + unsigned int TPC_BUSY : 1; + unsigned int : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int GUI_ACTIVE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GUI_ACTIVE : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int TPC_BUSY : 1; + unsigned int SX_BUSY : 1; + unsigned int : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int MH_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int HIRQ_PENDING : 1; + unsigned int : 2; + unsigned int TC_BUSY : 1; + unsigned int CMDFIFO_AVAIL : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DSPLY { + struct { +#if defined(qLittleEndian) + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int : 2; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_NUM_BUFS : 2; +#else /* !defined(qLittleEndian) */ + unsigned int DMI_CH4_NUM_BUFS : 2; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RENDER_LATEST { + struct { +#if defined(qLittleEndian) + unsigned int DMI_CH1_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH1_BUFFER_ID : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RTL_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int CHANGELIST : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CHANGELIST : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PATCH_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int PATCH_REVISION : 16; + unsigned int PATCH_SELECTION : 8; + unsigned int CUSTOMER_ID : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CUSTOMER_ID : 8; + unsigned int PATCH_SELECTION : 8; + unsigned int PATCH_REVISION : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_AUXILIARY_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID0 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER0 : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PARTNUMBER0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID1 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER1 : 4; + unsigned int DESIGNER0 : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int DESIGNER0 : 4; + unsigned int PARTNUMBER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID2 { + struct { +#if defined(qLittleEndian) + unsigned int DESIGNER1 : 4; + unsigned int REVISION : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int REVISION : 4; + unsigned int DESIGNER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID3 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_HOST_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int MH_INTERFACE : 2; + unsigned int : 1; + unsigned int CONTINUATION : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CONTINUATION : 1; + unsigned int : 1; + unsigned int MH_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int RBBM_HOST_INTERFACE : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int READ_TIMEOUT : 8; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int READ_TIMEOUT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SKEW_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SKEW_TOP_THRESHOLD : 5; + unsigned int SKEW_COUNT : 5; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int SKEW_COUNT : 5; + unsigned int SKEW_TOP_THRESHOLD : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SOFT_RESET { + struct { +#if defined(qLittleEndian) + unsigned int SOFT_RESET_CP : 1; + unsigned int : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_SX : 1; + unsigned int : 5; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 2; + unsigned int SOFT_RESET_SC : 1; + unsigned int SOFT_RESET_VGT : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int SOFT_RESET_VGT : 1; + unsigned int SOFT_RESET_SC : 1; + unsigned int : 2; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 5; + unsigned int SOFT_RESET_SX : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int : 1; + unsigned int SOFT_RESET_CP : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE1 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE2 { + struct { +#if defined(qLittleEndian) + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GC_SYS_IDLE { + struct { +#if defined(qLittleEndian) + unsigned int GC_SYS_IDLE_DELAY : 16; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int : 2; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int : 3; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_IDLE_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GC_SYS_IDLE_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int : 3; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int : 2; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int GC_SYS_IDLE_DELAY : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union NQWAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_GUI_IDLE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int WAIT_GUI_IDLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_OUT { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_BUS_OUT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEBUG_BUS_OUT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int SW_ENABLE : 1; + unsigned int : 3; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int GPIO_BYTE_LANE_ENB : 4; +#else /* !defined(qLittleEndian) */ + unsigned int GPIO_BYTE_LANE_ENB : 4; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 3; + unsigned int SW_ENABLE : 1; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int SUB_BLOCK_ADDR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int IGNORE_RTR : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int : 3; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 4; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int : 6; + unsigned int IGNORE_SX_RBBM_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int IGNORE_SX_RBBM_BUSY : 1; + unsigned int : 6; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int : 4; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 3; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_RTR : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_READ_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int READ_ADDRESS : 15; + unsigned int : 13; + unsigned int READ_REQUESTER : 1; + unsigned int READ_ERROR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int READ_ERROR : 1; + unsigned int READ_REQUESTER : 1; + unsigned int : 13; + unsigned int READ_ADDRESS : 15; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_WAIT_IDLE_CLOCKS { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_MASK : 1; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int RDERR_INT_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_STAT : 1; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int RDERR_INT_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_ACK : 1; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int RDERR_INT_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MASTER_INT_SIGNAL { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int MH_INT_STAT : 1; + unsigned int : 20; + unsigned int SQ_INT_STAT : 1; + unsigned int : 3; + unsigned int CP_INT_STAT : 1; + unsigned int RBBM_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RBBM_INT_STAT : 1; + unsigned int CP_INT_STAT : 1; + unsigned int : 3; + unsigned int SQ_INT_STAT : 1; + unsigned int : 20; + unsigned int MH_INT_STAT : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERF_COUNT1_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT1_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT1_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int RB_BASE : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BASE : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RB_BUFSZ : 6; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_POLL_EN : 1; + unsigned int : 6; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 3; + unsigned int RB_RPTR_WR_ENA : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_WR_ENA : 1; + unsigned int : 3; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 6; + unsigned int RB_POLL_EN : 1; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int RB_BUFSZ : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_SWAP : 2; + unsigned int RB_RPTR_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_ADDR : 30; + unsigned int RB_RPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_WR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_WR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR_WR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_WPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_DELAY { + struct { +#if defined(qLittleEndian) + unsigned int PRE_WRITE_TIMER : 28; + unsigned int PRE_WRITE_LIMIT : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PRE_WRITE_LIMIT : 4; + unsigned int PRE_WRITE_TIMER : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR_SWAP : 2; + unsigned int RB_WPTR_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_WPTR_BASE : 30; + unsigned int RB_WPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB1_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB1_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB1_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB1_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB2_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB2_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB2_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB2_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int ST_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int ST_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int ST_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int ST_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_QUEUE_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_IB1_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_ST_START : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int CSQ_ST_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_IB1_START : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int MEQ_END : 5; + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; + unsigned int MEQ_END : 5; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_CNT_RING : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_RING : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int STQ_CNT_ST : 7; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int STQ_CNT_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_CNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int MEQ_CNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_RB_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_PRIMARY : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB1_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT1 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB2_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT2 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NON_PREFETCH_CNTRS { + struct { +#if defined(qLittleEndian) + unsigned int IB1_COUNTER : 3; + unsigned int : 5; + unsigned int IB2_COUNTER : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int IB2_COUNTER : 3; + unsigned int : 5; + unsigned int IB1_COUNTER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_ST_STAT { + struct { +#if defined(qLittleEndian) + unsigned int STQ_RPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_RPTR_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_RPTR : 10; + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; + unsigned int MEQ_RPTR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MIU_TAG_STAT { + struct { +#if defined(qLittleEndian) + unsigned int TAG_0_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_17_STAT : 1; + unsigned int : 13; + unsigned int INVALID_RETURN_TAG : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INVALID_RETURN_TAG : 1; + unsigned int : 13; + unsigned int TAG_17_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_0_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int CMD_INDEX : 7; + unsigned int : 9; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 9; + unsigned int CMD_INDEX : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CMD_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CMD_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int ME_STATMUX : 16; + unsigned int : 9; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 1; + unsigned int ME_HALT : 1; + unsigned int ME_BUSY : 1; + unsigned int : 1; + unsigned int PROG_CNT_SIZE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PROG_CNT_SIZE : 1; + unsigned int : 1; + unsigned int ME_BUSY : 1; + unsigned int ME_HALT : 1; + unsigned int : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 9; + unsigned int ME_STATMUX : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int ME_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_WADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_WADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_WADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_RADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_RADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_RADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_DATA { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RAM_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RDADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RDADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RDADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; + unsigned int PREDICATE_DISABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int MIU_WRITE_PACK_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MIU_WRITE_PACK_DISABLE : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int PREDICATE_DISABLE : 1; + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG4 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG4 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG5 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG5 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG6 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG6 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG7 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG7 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_UMSK { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_UMSK : 8; + unsigned int : 8; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 8; + unsigned int SCRATCH_UMSK : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int SCRATCH_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWM : 1; + unsigned int VS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_DONE_CNTR : 1; + unsigned int VS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP : 2; + unsigned int VS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR : 30; + unsigned int VS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP_SWM : 2; + unsigned int VS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR_SWM : 30; + unsigned int VS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWM : 1; + unsigned int PS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int PS_DONE_CNTR : 1; + unsigned int PS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP : 2; + unsigned int PS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR : 30; + unsigned int PS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP_SWM : 2; + unsigned int PS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR_SWM : 30; + unsigned int PS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SRC : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CF_DONE_SRC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SWAP : 2; + unsigned int CF_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_ADDR : 30; + unsigned int CF_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_SWAP : 2; + unsigned int NRT_WRITE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_ADDR : 30; + unsigned int NRT_WRITE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_CNTR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int VS_FETCH_DONE_CNTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_SWAP : 2; + unsigned int VS_FETCH_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_ADDR : 30; + unsigned int VS_FETCH_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_MASK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int RB_INT_MASK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int : 3; + unsigned int SW_INT_MASK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_STAT : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int RB_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int : 3; + unsigned int SW_INT_STAT : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_ACK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int RB_INT_ACK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int : 3; + unsigned int SW_INT_ACK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_ADDR : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int UCODE_ADDR : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_DATA : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int UCODE_DATA : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFMON_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PERFMON_STATE : 4; + unsigned int : 4; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 4; + unsigned int PERFMON_STATE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERFCOUNT_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNT_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_0 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_0 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_15 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_15 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_1 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_16 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_31 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_31 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_16 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_2 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_32 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_47 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_47 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_32 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_3 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_48 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_63 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_63 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_48 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_INDEX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int STATE_DEBUG_INDEX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATE_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PROG_COUNTER { + struct { +#if defined(qLittleEndian) + unsigned int COUNTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COUNTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MIU_WR_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int _3D_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int ME_WC_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int CP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CP_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int ME_WC_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int _3D_BUSY : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_WR_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_0_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_1_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_2_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_3_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_4_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_5_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_6_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_7_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_8_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_9_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_10_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_11_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_12_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_13_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_14_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_15_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_HOST { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_0 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_0 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_0 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_1 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_1 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_1 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_2 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_2 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_2 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_3 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_3 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_3 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_4 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_4 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_4 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_5 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_5 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_5 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_6 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_6 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_6 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_7 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_7 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_7 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SURFACE_INFO { + struct { +#if defined(qLittleEndian) + unsigned int SURFACE_PITCH : 14; + unsigned int MSAA_SAMPLES : 2; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MSAA_SAMPLES : 2; + unsigned int SURFACE_PITCH : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_FORMAT : 4; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_SWAP : 2; + unsigned int : 1; + unsigned int COLOR_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_BASE : 20; + unsigned int : 1; + unsigned int COLOR_SWAP : 2; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_FORMAT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_INFO { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_FORMAT : 1; + unsigned int : 11; + unsigned int DEPTH_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_BASE : 20; + unsigned int : 11; + unsigned int DEPTH_FORMAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int RESERVED0 : 1; + unsigned int RESERVED1 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED1 : 1; + unsigned int RESERVED0 : 1; + unsigned int STENCILWRITEMASK : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILREF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ALPHA_REF { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_REF : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_REF : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_MASK { + struct { +#if defined(qLittleEndian) + unsigned int WRITE_RED : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int RESERVED2 : 1; + unsigned int RESERVED3 : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int RESERVED3 : 1; + unsigned int RESERVED2 : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_RED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_RED { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_RED : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_GREEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_GREEN : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_GREEN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_BLUE { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_BLUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_BLUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_ALPHA { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_ALPHA : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_ALPHA : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FOG_COLOR { + struct { +#if defined(qLittleEndian) + unsigned int FOG_RED : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_BLUE : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int FOG_BLUE : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK_BF { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int RESERVED4 : 1; + unsigned int RESERVED5 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED5 : 1; + unsigned int RESERVED4 : 1; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILREF_BF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTHCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int STENCIL_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int STENCILFUNC : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILZFAIL_BF : 3; +#else /* !defined(qLittleEndian) */ + unsigned int STENCILZFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int STENCIL_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLENDCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_SRCBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int BLEND_FORCE : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BLEND_FORCE : 1; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_SRCBLEND : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLORCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_FUNC : 3; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int FOG_ENABLE : 1; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int ROP_CODE : 4; + unsigned int DITHER_MODE : 2; + unsigned int DITHER_TYPE : 2; + unsigned int PIXEL_FOG : 1; + unsigned int : 7; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int : 7; + unsigned int PIXEL_FOG : 1; + unsigned int DITHER_TYPE : 2; + unsigned int DITHER_MODE : 2; + unsigned int ROP_CODE : 4; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int FOG_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_FUNC : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_MODECONTROL { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_MODE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int EDRAM_MODE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_DEST_MASK { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_DEST_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_DEST_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COPY_SAMPLE_SELECT : 3; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int CLEAR_MASK : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CLEAR_MASK : 4; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int COPY_SAMPLE_SELECT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int COPY_DEST_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COPY_DEST_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PITCH { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_PITCH : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int COPY_DEST_PITCH : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_ENDIAN : 3; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_ENDIAN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PIXEL_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET_X : 13; + unsigned int OFFSET_Y : 13; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int OFFSET_Y : 13; + unsigned int OFFSET_X : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_CLEAR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_CLEAR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_CTL { + struct { +#if defined(qLittleEndian) + unsigned int RESET_SAMPLE_COUNT : 1; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int RESET_SAMPLE_COUNT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int SAMPLE_COUNT_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLE_COUNT_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int CRC_MODE : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int DISABLE_ACCUM : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int RESERVED6 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED6 : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int DISABLE_ACCUM : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int CRC_MODE : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_EDRAM_INFO { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_SIZE : 4; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int : 8; + unsigned int EDRAM_RANGE : 18; +#else /* !defined(qLittleEndian) */ + unsigned int EDRAM_RANGE : 18; + unsigned int : 8; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int EDRAM_SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_RD_PORT { + struct { +#if defined(qLittleEndian) + unsigned int CRC_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int CRC_RD_ADVANCE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CRC_RD_ADVANCE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_MASK { + struct { +#if defined(qLittleEndian) + unsigned int CRC_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_TOTAL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int TOTAL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int TOTAL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZPASS_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZPASS_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZPASS_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int SFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int EZ_INFSAMP_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_Z1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int EZ_INFSAMP_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_Z1_CMD_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int TILE_FIFO_COUNT : 4; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z_TILE_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int Z_TILE_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int TILE_FIFO_COUNT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_VALID : 4; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int SHD_FULL : 1; + unsigned int SHD_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int SHD_EMPTY : 1; + unsigned int SHD_FULL : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_VALID : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int GMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int : 19; +#else /* !defined(qLittleEndian) */ + unsigned int : 19; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int GMEM_RD_ACCESS_FLAG : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FLAG_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_FLAG_CLEAR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int DEBUG_FLAG_CLEAR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_SPARES { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_ENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_MOREENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h new file mode 100644 index 000000000000..69677996b133 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h @@ -0,0 +1,4184 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_SHIFT_HEADER) +#define _yamato_SHIFT_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT 0x00000016 +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT 0x00000017 +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT 0x00000018 + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT 0x00000005 + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT 0x0000000f +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT 0x00000012 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT 0x00000017 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT 0x00000019 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a +#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS__SHIFT 0x0000001c +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT 0x0000001d +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT 0x0000001e +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT 0x0000001f + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT 0x00000000 +#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT 0x00000008 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT 0x00000000 +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT 0x00000001 +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT 0x00000007 + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT 0x0000001f + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000014 + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000018 + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT 0x00000008 + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT 0x0000001c + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT 0x00000004 + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT 0x00000016 + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT 0x0000001b + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x0000000a +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT 0x0000000d +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001f + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT 0x0000000b +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT 0x00000019 + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT 0x00000001 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000003 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT 0x00000016 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT 0x0000001b +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x00000005 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT 0x00000008 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x0000000e +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT 0x00000016 + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000005 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000b +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000c +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT 0x0000000d +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x0000000e +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x0000000f +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000010 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000011 + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000c +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x0000000d +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000010 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000011 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000014 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000015 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x00000017 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001a +#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT 0x0000001b +#define SETUP_DEBUG_REG4__event_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001d + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x00000016 +#define SETUP_DEBUG_REG5__event_id_gated__SHIFT 0x00000018 + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1__SHIFT 0x00000000 +#define SC_DEBUG_0__pa_sc_valid__SHIFT 0x00000001 +#define SC_DEBUG_0__pa_sc_phase__SHIFT 0x00000002 +#define SC_DEBUG_0__cntx_cnt__SHIFT 0x00000005 +#define SC_DEBUG_0__decr_cntx_cnt__SHIFT 0x0000000c +#define SC_DEBUG_0__incr_cntx_cnt__SHIFT 0x0000000d +#define SC_DEBUG_0__trigger__SHIFT 0x0000001f + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state__SHIFT 0x00000000 +#define SC_DEBUG_1__em1_data_ready__SHIFT 0x00000003 +#define SC_DEBUG_1__em2_data_ready__SHIFT 0x00000004 +#define SC_DEBUG_1__move_em1_to_em2__SHIFT 0x00000005 +#define SC_DEBUG_1__ef_data_ready__SHIFT 0x00000006 +#define SC_DEBUG_1__ef_state__SHIFT 0x00000007 +#define SC_DEBUG_1__pipe_valid__SHIFT 0x00000009 +#define SC_DEBUG_1__trigger__SHIFT 0x0000001f + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly__SHIFT 0x00000000 +#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT 0x00000001 +#define SC_DEBUG_2__pipe_freeze_b__SHIFT 0x00000003 +#define SC_DEBUG_2__prim_rts__SHIFT 0x00000004 +#define SC_DEBUG_2__next_prim_rts_dly__SHIFT 0x00000005 +#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT 0x00000006 +#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT 0x00000007 +#define SC_DEBUG_2__stage0_rts__SHIFT 0x00000008 +#define SC_DEBUG_2__phase_rts_dly__SHIFT 0x00000009 +#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT 0x0000000f +#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT 0x00000010 +#define SC_DEBUG_2__event_id_s1__SHIFT 0x00000011 +#define SC_DEBUG_2__event_s1__SHIFT 0x00000016 +#define SC_DEBUG_2__trigger__SHIFT 0x0000001f + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1__SHIFT 0x00000000 +#define SC_DEBUG_3__y_curr_s1__SHIFT 0x0000000b +#define SC_DEBUG_3__trigger__SHIFT 0x0000001f + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_4__y_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_4__y_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_4__trigger__SHIFT 0x0000001f + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_5__x_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_5__x_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_5__trigger__SHIFT 0x0000001f + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty__SHIFT 0x00000000 +#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT 0x00000001 +#define SC_DEBUG_6__xy_ff_empty__SHIFT 0x00000002 +#define SC_DEBUG_6__event_flag__SHIFT 0x00000003 +#define SC_DEBUG_6__z_mask_needed__SHIFT 0x00000004 +#define SC_DEBUG_6__state__SHIFT 0x00000005 +#define SC_DEBUG_6__state_delayed__SHIFT 0x00000008 +#define SC_DEBUG_6__data_valid__SHIFT 0x0000000b +#define SC_DEBUG_6__data_valid_d__SHIFT 0x0000000c +#define SC_DEBUG_6__tilex_delayed__SHIFT 0x0000000d +#define SC_DEBUG_6__tiley_delayed__SHIFT 0x00000016 +#define SC_DEBUG_6__trigger__SHIFT 0x0000001f + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag__SHIFT 0x00000000 +#define SC_DEBUG_7__deallocate__SHIFT 0x00000001 +#define SC_DEBUG_7__fposition__SHIFT 0x00000004 +#define SC_DEBUG_7__sr_prim_we__SHIFT 0x00000005 +#define SC_DEBUG_7__last_tile__SHIFT 0x00000006 +#define SC_DEBUG_7__tile_ff_we__SHIFT 0x00000007 +#define SC_DEBUG_7__qs_data_valid__SHIFT 0x00000008 +#define SC_DEBUG_7__qs_q0_y__SHIFT 0x00000009 +#define SC_DEBUG_7__qs_q0_x__SHIFT 0x0000000b +#define SC_DEBUG_7__qs_q0_valid__SHIFT 0x0000000d +#define SC_DEBUG_7__prim_ff_we__SHIFT 0x0000000e +#define SC_DEBUG_7__tile_ff_re__SHIFT 0x0000000f +#define SC_DEBUG_7__fw_prim_data_valid__SHIFT 0x00000010 +#define SC_DEBUG_7__last_quad_of_tile__SHIFT 0x00000011 +#define SC_DEBUG_7__first_quad_of_tile__SHIFT 0x00000012 +#define SC_DEBUG_7__first_quad_of_prim__SHIFT 0x00000013 +#define SC_DEBUG_7__new_prim__SHIFT 0x00000014 +#define SC_DEBUG_7__load_new_tile_data__SHIFT 0x00000015 +#define SC_DEBUG_7__state__SHIFT 0x00000016 +#define SC_DEBUG_7__fifos_ready__SHIFT 0x00000018 +#define SC_DEBUG_7__trigger__SHIFT 0x0000001f + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last__SHIFT 0x00000000 +#define SC_DEBUG_8__sample_mask__SHIFT 0x00000001 +#define SC_DEBUG_8__sample_y__SHIFT 0x00000005 +#define SC_DEBUG_8__sample_x__SHIFT 0x00000007 +#define SC_DEBUG_8__sample_send__SHIFT 0x00000009 +#define SC_DEBUG_8__next_cycle__SHIFT 0x0000000a +#define SC_DEBUG_8__ez_sample_ff_full__SHIFT 0x0000000c +#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT 0x0000000d +#define SC_DEBUG_8__num_samples__SHIFT 0x0000000e +#define SC_DEBUG_8__last_quad_of_tile__SHIFT 0x00000010 +#define SC_DEBUG_8__last_quad_of_prim__SHIFT 0x00000011 +#define SC_DEBUG_8__first_quad_of_prim__SHIFT 0x00000012 +#define SC_DEBUG_8__sample_we__SHIFT 0x00000013 +#define SC_DEBUG_8__fposition__SHIFT 0x00000014 +#define SC_DEBUG_8__event_id__SHIFT 0x00000015 +#define SC_DEBUG_8__event_flag__SHIFT 0x0000001a +#define SC_DEBUG_8__fw_prim_data_valid__SHIFT 0x0000001b +#define SC_DEBUG_8__trigger__SHIFT 0x0000001f + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send__SHIFT 0x00000000 +#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT 0x00000001 +#define SC_DEBUG_9__fifo_data_ready__SHIFT 0x00000005 +#define SC_DEBUG_9__early_z_enable__SHIFT 0x00000006 +#define SC_DEBUG_9__mask_state__SHIFT 0x00000007 +#define SC_DEBUG_9__next_ez_mask__SHIFT 0x00000009 +#define SC_DEBUG_9__mask_ready__SHIFT 0x00000019 +#define SC_DEBUG_9__drop_sample__SHIFT 0x0000001a +#define SC_DEBUG_9__fetch_new_sample_data__SHIFT 0x0000001b +#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT 0x0000001c +#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT 0x0000001d +#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT 0x0000001e +#define SC_DEBUG_9__trigger__SHIFT 0x0000001f + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask__SHIFT 0x00000000 +#define SC_DEBUG_10__trigger__SHIFT 0x0000001f + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready__SHIFT 0x00000000 +#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT 0x00000001 +#define SC_DEBUG_11__ez_prim_data_ready__SHIFT 0x00000002 +#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT 0x00000003 +#define SC_DEBUG_11__iterator_input_fz__SHIFT 0x00000004 +#define SC_DEBUG_11__packer_send_quads__SHIFT 0x00000005 +#define SC_DEBUG_11__packer_send_cmd__SHIFT 0x00000006 +#define SC_DEBUG_11__packer_send_event__SHIFT 0x00000007 +#define SC_DEBUG_11__next_state__SHIFT 0x00000008 +#define SC_DEBUG_11__state__SHIFT 0x0000000b +#define SC_DEBUG_11__stall__SHIFT 0x0000000e +#define SC_DEBUG_11__trigger__SHIFT 0x0000001f + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT 0x00000000 +#define SC_DEBUG_12__event_id__SHIFT 0x00000001 +#define SC_DEBUG_12__event_flag__SHIFT 0x00000006 +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT 0x00000007 +#define SC_DEBUG_12__itercmdfifo_full__SHIFT 0x00000008 +#define SC_DEBUG_12__itercmdfifo_empty__SHIFT 0x00000009 +#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT 0x0000000a +#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT 0x0000000b +#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT 0x0000000c +#define SC_DEBUG_12__iter_qdhit0__SHIFT 0x0000000d +#define SC_DEBUG_12__bc_use_centers_reg__SHIFT 0x0000000e +#define SC_DEBUG_12__bc_output_xy_reg__SHIFT 0x0000000f +#define SC_DEBUG_12__iter_phase_out__SHIFT 0x00000010 +#define SC_DEBUG_12__iter_phase_reg__SHIFT 0x00000012 +#define SC_DEBUG_12__iterator_SP_valid__SHIFT 0x00000014 +#define SC_DEBUG_12__eopv_reg__SHIFT 0x00000015 +#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT 0x00000016 +#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT 0x00000017 +#define SC_DEBUG_12__trigger__SHIFT 0x0000001f + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000006 +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT 0x00000008 +#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT 0x0000000b +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x0000000c +#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT 0x0000000d +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT 0x0000000e +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT 0x0000000f +#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT 0x00000010 + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_DMA_SIZE__SWAP_MODE__SHIFT 0x0000001e + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT 0x00000000 + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT 0x0000001e +#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT 0x0000001f + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT 0x00000006 + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT 0x00000006 + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x00000000 + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 +#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT 0x00000001 +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT 0x00000002 +#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT 0x00000003 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000004 +#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT 0x00000005 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000006 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000007 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000008 + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT 0x00000001 +#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT 0x00000002 +#define VGT_DEBUG_REG0__dma_request_busy__SHIFT 0x00000003 +#define VGT_DEBUG_REG0__out_busy__SHIFT 0x00000004 +#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT 0x00000005 +#define VGT_DEBUG_REG0__grp_busy__SHIFT 0x00000006 +#define VGT_DEBUG_REG0__dma_busy__SHIFT 0x00000007 +#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT 0x00000008 +#define VGT_DEBUG_REG0__rbiu_busy__SHIFT 0x00000009 +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT 0x0000000a +#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT 0x0000000b +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0000000c +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x0000000d +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT 0x0000000e +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT 0x0000000f +#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT 0x00000010 + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read__SHIFT 0x00000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000001 +#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000003 +#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT 0x00000004 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000005 +#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT 0x00000006 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000007 +#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000a +#define VGT_DEBUG_REG1__grp_te_valid__SHIFT 0x0000000b +#define VGT_DEBUG_REG1__pt_grp_read__SHIFT 0x0000000c +#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__vr_grp_read__SHIFT 0x0000000e +#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT 0x0000000f +#define VGT_DEBUG_REG1__grp_dma_read__SHIFT 0x00000010 +#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT 0x00000011 +#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT 0x00000012 +#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT 0x00000013 +#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT 0x00000015 +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT 0x00000016 +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT 0x00000017 +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT 0x00000019 +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT 0x0000001b +#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT 0x0000001d +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT 0x0000001e + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT 0x00000000 +#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT 0x00000001 + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG6__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG6__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG6__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG6__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG6__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG6__grp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG7__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG8__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG8__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG8__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG9__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG9__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG9__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG9__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG9__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG9__grp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000 +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001 +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002 +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003 +#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT 0x00000005 +#define VGT_DEBUG_REG10__bin_valid__SHIFT 0x00000006 +#define VGT_DEBUG_REG10__read_block__SHIFT 0x00000007 +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG10__selected_data__SHIFT 0x0000000b +#define VGT_DEBUG_REG10__mask_input_data__SHIFT 0x00000013 +#define VGT_DEBUG_REG10__gap_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT 0x0000001c +#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT 0x0000001d +#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT 0x0000001e +#define VGT_DEBUG_REG10__grp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG12__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG12__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG12__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG12__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG12__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG13__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG14__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG14__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG14__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG15__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG15__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG15__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG15__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG15__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT 0x00000000 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT 0x00000008 +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG16__rst_last_bit__SHIFT 0x0000000a +#define VGT_DEBUG_REG16__current_state_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG16__old_state_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG16__old_state_en__SHIFT 0x0000000d +#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG16__load_empty_reg__SHIFT 0x00000012 +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT 0x00000013 +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG17__extend_read_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG17__grp_indx_size__SHIFT 0x00000002 +#define VGT_DEBUG_REG17__cull_prim_true__SHIFT 0x00000004 +#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG17__check_second_reg__SHIFT 0x00000008 +#define VGT_DEBUG_REG17__check_first_reg__SHIFT 0x00000009 +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT 0x00000006 +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d +#define VGT_DEBUG_REG18__dma_mem_full__SHIFT 0x0000000f +#define VGT_DEBUG_REG18__dma_ram_re__SHIFT 0x00000010 +#define VGT_DEBUG_REG18__dma_ram_we__SHIFT 0x00000011 +#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT 0x00000013 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT 0x00000014 +#define VGT_DEBUG_REG18__bin_mem_full__SHIFT 0x00000015 +#define VGT_DEBUG_REG18__bin_ram_we__SHIFT 0x00000016 +#define VGT_DEBUG_REG18__bin_ram_re__SHIFT 0x00000017 +#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT 0x00000018 +#define VGT_DEBUG_REG18__start_bin_req__SHIFT 0x00000019 +#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT 0x0000001a +#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT 0x0000001b +#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT 0x0000001c +#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT 0x0000001d +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT 0x00000000 +#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT 0x00000002 +#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT 0x00000006 +#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT 0x00000008 +#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT 0x0000000a +#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT 0x0000000b +#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT 0x0000000c +#define VGT_DEBUG_REG20__hold_prim__SHIFT 0x0000000d +#define VGT_DEBUG_REG20__sent_cnt__SHIFT 0x0000000e +#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT 0x00000012 +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT 0x00000013 +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT 0x00000014 +#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT 0x00000015 +#define VGT_DEBUG_REG20__out_trigger__SHIFT 0x0000001a + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT 0x00000000 +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001 +#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG21__new_packet_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG21__new_allocate_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT 0x00000014 +#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG21__insert_null_prim__SHIFT 0x00000017 +#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT 0x00000018 +#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT 0x00000019 +#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT 0x0000001a +#define VGT_DEBUG_REG21__out_trigger__SHIFT 0x0000001f + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC__SHIFT 0x00000000 + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT 0x00000000 +#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT 0x00000012 +#define TC_CNTL_STATUS__TC_BUSY__SHIFT 0x0000001f + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000 +#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT 0x00000008 +#define TCM_CHICKEN__SPARE__SHIFT 0x00000009 + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT 0x00000000 +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT 0x00000003 + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT 0x00000000 +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT 0x00000001 +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT 0x00000002 +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT 0x00000003 +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT 0x00000004 +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT 0x00000005 +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT 0x00000006 +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT 0x00000008 +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT 0x00000009 +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT 0x0000000a +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT 0x0000000c +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT 0x0000000d +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT 0x0000000e +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT 0x0000000f +#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT 0x00000010 +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT 0x00000011 +#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT 0x00000013 +#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT 0x00000014 +#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT 0x00000015 +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT 0x00000016 +#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT 0x00000017 +#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT 0x00000018 +#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT 0x00000019 +#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT 0x0000001b +#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT 0x0000001c +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT 0x0000001d +#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT 0x0000001e +#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT 0x0000001f + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL__SHIFT 0x00000000 +#define TPC_DEBUG0__IC_CTR__SHIFT 0x00000002 +#define TPC_DEBUG0__WALKER_CNTL__SHIFT 0x00000004 +#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT 0x00000008 +#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT 0x0000000c +#define TPC_DEBUG0__WALKER_STATE__SHIFT 0x00000010 +#define TPC_DEBUG0__ALIGNER_STATE__SHIFT 0x0000001a +#define TPC_DEBUG0__REG_CLK_EN__SHIFT 0x0000001d +#define TPC_DEBUG0__TPC_CLK_EN__SHIFT 0x0000001e +#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT 0x0000001f + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED__SHIFT 0x00000000 + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION__SHIFT 0x00000000 +#define TPC_CHICKEN__SPARE__SHIFT 0x00000001 + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT 0x00000000 +#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT 0x00000001 +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT 0x00000002 +#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT 0x00000003 +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT 0x00000004 +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT 0x00000005 +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT 0x00000006 +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT 0x00000007 +#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT 0x00000008 +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT 0x00000009 +#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT 0x0000000a +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT 0x0000000b +#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT 0x0000000c +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT 0x0000000d +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT 0x0000000e +#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT 0x00000010 +#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT 0x00000011 +#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT 0x00000012 +#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT 0x00000013 +#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT 0x00000014 +#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT 0x00000015 +#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT 0x00000016 +#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT 0x00000017 +#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT 0x00000018 +#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT 0x00000019 +#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT 0x0000001a +#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT 0x0000001b +#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT 0x0000001c +#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT 0x0000001d +#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT 0x0000001e +#define TP0_CNTL_STATUS__TP_BUSY__SHIFT 0x0000001f + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL__SHIFT 0x00000000 +#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT 0x00000003 +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT 0x00000004 +#define TP0_DEBUG__REG_CLK_EN__SHIFT 0x00000015 +#define TP0_DEBUG__PERF_CLK_EN__SHIFT 0x00000016 +#define TP0_DEBUG__TP_CLK_EN__SHIFT 0x00000017 +#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT 0x00000018 +#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT 0x0000001c + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE__SHIFT 0x00000000 +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT 0x00000001 +#define TP0_CHICKEN__SPARE__SHIFT 0x00000002 + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr__SHIFT 0x00000006 +#define TCF_DEBUG__TC_MH_send__SHIFT 0x00000007 +#define TCF_DEBUG__not_FG0_rtr__SHIFT 0x00000008 +#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT 0x0000000c +#define TCF_DEBUG__TCB_ff_stall__SHIFT 0x0000000d +#define TCF_DEBUG__TCB_miss_stall__SHIFT 0x0000000e +#define TCF_DEBUG__TCA_TCB_stall__SHIFT 0x0000000f +#define TCF_DEBUG__PF0_stall__SHIFT 0x00000010 +#define TCF_DEBUG__TP0_full__SHIFT 0x00000014 +#define TCF_DEBUG__TPC_full__SHIFT 0x00000018 +#define TCF_DEBUG__not_TPC_rtr__SHIFT 0x00000019 +#define TCF_DEBUG__tca_state_rts__SHIFT 0x0000001a +#define TCF_DEBUG__tca_rts__SHIFT 0x0000001b + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full__SHIFT 0x00000000 +#define TCA_FIFO_DEBUG__tpc_full__SHIFT 0x00000004 +#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT 0x00000005 +#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT 0x00000006 +#define TCA_FIFO_DEBUG__FW_full__SHIFT 0x00000007 +#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT 0x00000008 +#define TCA_FIFO_DEBUG__FW_rts0__SHIFT 0x0000000c +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT 0x00000010 +#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT 0x00000011 + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT 0x00000000 + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts__SHIFT 0x0000000c +#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT 0x0000000d + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512__SHIFT 0x00000000 +#define TCB_CORE_DEBUG__tiled__SHIFT 0x00000001 +#define TCB_CORE_DEBUG__opcode__SHIFT 0x00000004 +#define TCB_CORE_DEBUG__format__SHIFT 0x00000008 +#define TCB_CORE_DEBUG__sector_format__SHIFT 0x00000010 +#define TCB_CORE_DEBUG__sector_format512__SHIFT 0x00000018 + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG0_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG0_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG1_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG1_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG2_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG2_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG3_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG3_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT 0x00000004 +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT 0x0000000b +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT 0x0000000c +#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT 0x0000000f +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010 + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT 0x00000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT 0x00000002 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015 +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT 0x00000017 +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT 0x00000018 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT 0x00000019 +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT 0x0000001a +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT 0x0000001c +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT 0x0000001e + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty__SHIFT 0x00000010 +#define TCD_INPUT0_DEBUG__full__SHIFT 0x00000011 +#define TCD_INPUT0_DEBUG__valid_q1__SHIFT 0x00000014 +#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT 0x00000015 +#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT 0x00000017 +#define TCD_INPUT0_DEBUG__ip_send__SHIFT 0x00000018 +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT 0x00000019 +#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT 0x0000001a + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT 0x00000000 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT 0x00000002 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT 0x00000003 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT 0x00000004 +#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT 0x00000005 +#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT 0x00000006 + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT 0x00000009 +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT 0x0000000a +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT 0x0000000b +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT 0x00000014 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT 0x0000001c +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT 0x0000001d + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT 0x00000004 +#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT 0x00000005 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT 0x00000006 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT 0x00000007 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT 0x00000009 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT 0x0000000c +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT 0x00000012 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT 0x0000001e +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT 0x0000001f + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT 0x0000000a +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT 0x0000000b +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT 0x00000011 +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT 0x00000012 +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT 0x00000013 +#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT 0x0000001f + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT 0x00000005 +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT 0x00000006 +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT 0x00000007 + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT 0x00000008 +#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT 0x00000009 +#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT 0x0000000a +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT 0x0000000c +#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT 0x0000000d +#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT 0x00000010 +#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG0__busy__SHIFT 0x0000001e + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG1__empty__SHIFT 0x00000001 +#define TCO_QUAD0_DEBUG1__full__SHIFT 0x00000002 +#define TCO_QUAD0_DEBUG1__write_enable__SHIFT 0x00000003 +#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT 0x00000004 +#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT 0x00000014 +#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT 0x00000015 +#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT 0x00000016 +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT 0x00000017 +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT 0x0000001e + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT 0x00000000 +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT 0x00000004 +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT 0x0000000c + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT 0x00000000 +#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT 0x00000004 +#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT 0x00000008 +#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT 0x0000000c +#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT 0x00000010 +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT 0x00000011 +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT 0x00000012 +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013 +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT 0x00000015 +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT 0x00000016 +#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT 0x00000017 +#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT 0x00000018 +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT 0x00000019 +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT 0x0000001b + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT 0x00000000 +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT 0x00000010 + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000 +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008 +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT 0x00000010 + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT 0x00000000 +#define SQ_EO_RT__EO_TSTATE_RT__SHIFT 0x00000010 + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT 0x00000000 +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT 0x0000000c +#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT 0x00000014 +#define SQ_DEBUG_MISC__RESERVED__SHIFT 0x00000015 +#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT 0x00000017 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT 0x00000019 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT 0x0000001a +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT 0x0000001b +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT 0x0000001c + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT 0x00000000 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT 0x00000008 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT 0x00000010 +#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT 0x00000018 + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT 0x00000000 + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 +#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT 0x00000012 +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014 +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015 +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016 + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT 0x00000000 +#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT 0x00000001 + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT 0x00000000 +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT 0x00000001 + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT 0x00000000 +#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT 0x00000001 + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT 0x00000000 +#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT 0x00000003 +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT 0x00000004 +#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT 0x00000008 +#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT 0x0000000c +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT 0x0000000f +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT 0x00000014 + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT 0x00000005 +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT 0x0000000d +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010 +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017 + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT 0x00000000 +#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT 0x00000004 +#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT 0x00000008 +#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT 0x0000000c +#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT 0x0000000e +#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT 0x00000010 +#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT 0x00000012 +#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT 0x00000014 +#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT 0x00000016 +#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT 0x00000018 +#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT 0x0000001a +#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT 0x00000000 +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT 0x00000004 +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT 0x0000000c +#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT 0x0000000f +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT 0x00000010 + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT 0x00000000 +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT 0x00000001 +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT 0x00000005 +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT 0x00000006 +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT 0x00000009 +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT 0x0000000e +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT 0x0000000f +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT 0x00000010 +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT 0x00000011 + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017 +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT 0x0000001d +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT 0x00000000 +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT 0x00000004 +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT 0x00000008 +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT 0x00000010 +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT 0x00000014 +#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT 0x00000015 + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT 0x00000006 +#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT 0x00000013 +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT 0x00000019 +#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT 0x0000001f + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT 0x0000001a + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT 0x00000002 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT 0x00000004 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT 0x0000000a +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT 0x0000000c +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT 0x00000012 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT 0x0000001a +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT 0x0000001b +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT 0x0000001f + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT 0x00000017 +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT 0x00000013 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT 0x00000014 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT 0x00000015 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT 0x00000016 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT 0x00000017 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT 0x0000001e +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT 0x00000003 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT 0x00000006 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT 0x00000007 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT 0x00000015 + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT 0x0000001a + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT 0x0000000f + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT 0x0000001e + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT 0x00000004 + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT 0x00000014 + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT 0x00000013 +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT 0x00000019 +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT 0x0000001e + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT 0x0000000e +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT 0x00000018 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT 0x0000001d +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT 0x00000013 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT 0x00000019 +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT 0x0000001e + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT 0x00000017 +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT 0x00000001 +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE__SHIFT 0x00000000 + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE__SHIFT 0x00000000 + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_VS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_PS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT 0x00000000 +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT 0x0000000c + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT 0x00000000 +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT 0x00000010 + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT 0x00000000 +#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT 0x00000008 +#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT 0x00000010 +#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT 0x00000011 +#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT 0x00000012 +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT 0x00000013 +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT 0x00000014 +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT 0x00000018 +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT 0x0000001b +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT 0x0000001f + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT 0x00000000 +#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT 0x00000004 +#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT 0x00000008 +#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT 0x0000000c +#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT 0x00000010 +#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT 0x00000014 +#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT 0x00000018 +#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT 0x0000001c + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT 0x00000000 +#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT 0x00000004 +#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT 0x00000008 +#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT 0x0000000c +#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT 0x00000010 +#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT 0x00000014 +#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT 0x00000018 +#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT 0x0000001c + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE__SHIFT 0x00000000 +#define SQ_VS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE__SHIFT 0x00000000 +#define SQ_PS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT 0x00000000 +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT 0x00000001 +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT 0x00000002 +#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT 0x00000008 +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT 0x00000010 +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT 0x00000011 +#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT 0x00000012 + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE__SHIFT 0x00000000 + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT 0x00000004 +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT 0x00000018 + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT 0x00000001 +#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT 0x00000010 + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT 0x00000000 +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 +#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT 0x00000000 +#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT 0x00000003 +#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT 0x00000004 +#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT 0x00000007 +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT 0x00000008 +#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT 0x0000000b +#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT 0x0000000c + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID__SHIFT 0x00000000 +#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT 0x00000003 +#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT 0x00000004 +#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT 0x00000007 + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX__SHIFT 0x00000000 + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT 0x00000000 + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY__SHIFT 0x00000000 +#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT 0x00000001 +#define MH_DEBUG_REG00__CP_REQUEST__SHIFT 0x00000002 +#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT 0x00000003 +#define MH_DEBUG_REG00__TC_REQUEST__SHIFT 0x00000004 +#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT 0x00000005 +#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT 0x00000006 +#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG00__TCD_FULL__SHIFT 0x00000008 +#define MH_DEBUG_REG00__RB_REQUEST__SHIFT 0x00000009 +#define MH_DEBUG_REG00__PA_REQUEST__SHIFT 0x0000000a +#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT 0x0000000b +#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG00__ARQ_FULL__SHIFT 0x0000000d +#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT 0x0000000e +#define MH_DEBUG_REG00__WDB_FULL__SHIFT 0x0000000f +#define MH_DEBUG_REG00__AXI_AVALID__SHIFT 0x00000010 +#define MH_DEBUG_REG00__AXI_AREADY__SHIFT 0x00000011 +#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT 0x00000012 +#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT 0x00000013 +#define MH_DEBUG_REG00__AXI_WVALID__SHIFT 0x00000014 +#define MH_DEBUG_REG00__AXI_WREADY__SHIFT 0x00000015 +#define MH_DEBUG_REG00__AXI_RVALID__SHIFT 0x00000016 +#define MH_DEBUG_REG00__AXI_RREADY__SHIFT 0x00000017 +#define MH_DEBUG_REG00__AXI_BVALID__SHIFT 0x00000018 +#define MH_DEBUG_REG00__AXI_BREADY__SHIFT 0x00000019 +#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT 0x0000001b +#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT 0x0000001c + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q__SHIFT 0x00000000 +#define MH_DEBUG_REG01__CP_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG01__CP_TAG_q__SHIFT 0x00000003 +#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT 0x00000006 +#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT 0x00000007 +#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT 0x00000008 +#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG01__TC_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG01__TC_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT 0x0000000c +#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT 0x0000000d +#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT 0x0000000e +#define MH_DEBUG_REG01__TC_MH_written__SHIFT 0x0000000f +#define MH_DEBUG_REG01__RB_SEND_q__SHIFT 0x00000010 +#define MH_DEBUG_REG01__RB_RTR_q__SHIFT 0x00000011 +#define MH_DEBUG_REG01__PA_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG01__PA_RTR_q__SHIFT 0x00000013 + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT 0x00000003 +#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT 0x00000004 +#define MH_DEBUG_REG02__RDC_RID__SHIFT 0x00000007 +#define MH_DEBUG_REG02__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT 0x0000000c +#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT 0x0000000d +#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT 0x0000000e +#define MH_DEBUG_REG02__BRC_BID__SHIFT 0x0000000f +#define MH_DEBUG_REG02__BRC_BRESP__SHIFT 0x00000012 + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG05__CP_MH_write__SHIFT 0x00000001 +#define MH_DEBUG_REG05__CP_MH_tag__SHIFT 0x00000002 +#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be__SHIFT 0x00000000 +#define MH_DEBUG_REG08__RB_MH_be__SHIFT 0x00000008 +#define MH_DEBUG_REG08__PA_MH_be__SHIFT 0x00000010 + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG09__VGT_MH_send__SHIFT 0x00000003 +#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT 0x00000004 +#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG10__TC_MH_send__SHIFT 0x00000002 +#define MH_DEBUG_REG10__TC_MH_mask__SHIFT 0x00000003 +#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info__SHIFT 0x00000000 +#define MH_DEBUG_REG11__TC_MH_send__SHIFT 0x00000019 + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT 0x00000000 +#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT 0x00000019 +#define MH_DEBUG_REG12__TC_MH_written__SHIFT 0x0000001a + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT 0x00000002 +#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT 0x00000003 +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT 0x00000000 +#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT 0x00000019 + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG15__RB_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG18__PA_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG21__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG21__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT 0x00000005 +#define MH_DEBUG_REG21__ARVALID_q__SHIFT 0x00000008 +#define MH_DEBUG_REG21__ARREADY_q__SHIFT 0x00000009 +#define MH_DEBUG_REG21__ARID_q__SHIFT 0x0000000a +#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT 0x0000000d +#define MH_DEBUG_REG21__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG21__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG21__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG21__RID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG21__WVALID_q__SHIFT 0x00000015 +#define MH_DEBUG_REG21__WREADY_q__SHIFT 0x00000016 +#define MH_DEBUG_REG21__WLAST_q__SHIFT 0x00000017 +#define MH_DEBUG_REG21__WID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG21__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG21__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG21__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG22__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG22__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT 0x00000005 +#define MH_DEBUG_REG22__ARVALID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG22__ARREADY_q__SHIFT 0x00000008 +#define MH_DEBUG_REG22__ARID_q__SHIFT 0x00000009 +#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT 0x0000000c +#define MH_DEBUG_REG22__WVALID_q__SHIFT 0x0000000d +#define MH_DEBUG_REG22__WREADY_q__SHIFT 0x0000000e +#define MH_DEBUG_REG22__WLAST_q__SHIFT 0x0000000f +#define MH_DEBUG_REG22__WID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG22__WSTRB_q__SHIFT 0x00000013 +#define MH_DEBUG_REG22__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG22__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG22__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG24__REG_A__SHIFT 0x00000002 +#define MH_DEBUG_REG24__REG_RE__SHIFT 0x00000010 +#define MH_DEBUG_REG24__REG_WE__SHIFT 0x00000011 +#define MH_DEBUG_REG24__BLOCK_RS__SHIFT 0x00000012 + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD__SHIFT 0x00000000 + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT 0x00000000 +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT 0x00000001 +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT 0x00000002 +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT 0x00000003 +#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT 0x00000004 +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT 0x00000005 +#define MH_DEBUG_REG26__CNT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT 0x0000000c +#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT 0x0000000e +#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT 0x0000000f +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010 +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011 +#define MH_DEBUG_REG26__CP_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG26__CP_RTR_q__SHIFT 0x00000013 +#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT 0x00000014 +#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT 0x00000017 +#define MH_DEBUG_REG26__RB_SEND_q__SHIFT 0x00000018 +#define MH_DEBUG_REG26__RB_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG26__PA_SEND_q__SHIFT 0x0000001a +#define MH_DEBUG_REG26__PA_RTR_q__SHIFT 0x0000001b +#define MH_DEBUG_REG26__RDC_VALID__SHIFT 0x0000001c +#define MH_DEBUG_REG26__RDC_RLAST__SHIFT 0x0000001d +#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT 0x0000001e +#define MH_DEBUG_REG26__BRC_VALID__SHIFT 0x0000001f + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT 0x00000003 +#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT 0x00000006 +#define MH_DEBUG_REG27__ARB_WINNER__SHIFT 0x00000009 +#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT 0x0000000c +#define MH_DEBUG_REG27__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG27__KILL_EFF1__SHIFT 0x00000010 +#define MH_DEBUG_REG27__ARB_HOLD__SHIFT 0x00000011 +#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT 0x00000013 +#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT 0x00000014 +#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT 0x00000015 +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT 0x00000016 +#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT 0x00000017 +#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT 0x00000018 +#define MH_DEBUG_REG27__ARB_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT 0x0000001b +#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT 0x0000001c +#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT 0x0000001d +#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT 0x0000001e +#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT 0x0000001f + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG28__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT 0x00000006 +#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT 0x00000007 +#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT 0x00000008 +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT 0x00000009 +#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT 0x0000000a +#define MH_DEBUG_REG28__ARB_QUAL__SHIFT 0x0000000b +#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT 0x0000000d +#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT 0x0000000e +#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT 0x0000000f +#define MH_DEBUG_REG28__EFF1_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG28__KILL_EFF1__SHIFT 0x00000011 +#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT 0x00000012 +#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT 0x00000013 +#define MH_DEBUG_REG28__ARB_HOLD__SHIFT 0x00000014 +#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT 0x00000016 + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT 0x00000000 +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT 0x00000003 +#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT 0x00000006 +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT 0x00000009 +#define MH_DEBUG_REG29__ARB_HOLD__SHIFT 0x0000000a +#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG29__CLNT_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG29__RECENT_d_0__SHIFT 0x00000011 +#define MH_DEBUG_REG29__RECENT_d_1__SHIFT 0x00000014 +#define MH_DEBUG_REG29__RECENT_d_2__SHIFT 0x00000017 +#define MH_DEBUG_REG29__RECENT_d_3__SHIFT 0x0000001a +#define MH_DEBUG_REG29__RECENT_d_4__SHIFT 0x0000001d + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT 0x00000000 +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT 0x00000001 +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT 0x00000002 +#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT 0x00000003 +#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT 0x00000004 +#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT 0x00000005 +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008 +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG30__TC_MH_written__SHIFT 0x0000000b +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT 0x00000013 +#define MH_DEBUG_REG30__WLAST_q__SHIFT 0x00000014 +#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT 0x00000015 +#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG30__CP_MH_write__SHIFT 0x0000001a +#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT 0x0000001b +#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT 0x0000001c +#define MH_DEBUG_REG30__ARB_WINNER__SHIFT 0x0000001d + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT 0x00000008 +#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG32__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG32__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT 0x00000008 +#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT 0x00000010 +#define MH_DEBUG_REG33__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG33__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT 0x00000000 +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT 0x00000008 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT 0x00000018 + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT 0x00000002 +#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT 0x00000003 +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT 0x00000004 +#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT 0x00000005 + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT 0x00000002 +#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT 0x00000003 +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT 0x00000004 +#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT 0x00000005 + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT 0x00000002 +#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT 0x00000003 +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT 0x00000004 +#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT 0x00000005 + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT 0x00000002 +#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT 0x00000003 +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT 0x00000004 +#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT 0x00000005 + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT 0x00000002 +#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT 0x00000003 +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT 0x00000004 +#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT 0x00000005 + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT 0x00000002 +#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT 0x00000003 +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT 0x00000004 +#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT 0x00000005 + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT 0x00000002 +#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT 0x00000003 +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT 0x00000004 +#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT 0x00000005 + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT 0x00000002 +#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT 0x00000003 +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT 0x00000004 +#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT 0x00000005 + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG43__ARB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT 0x00000003 +#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT 0x00000004 +#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT 0x00000005 +#define MH_DEBUG_REG43__MMU_RTR__SHIFT 0x00000006 +#define MH_DEBUG_REG43__ARB_ID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT 0x0000000a +#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT 0x0000000b +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT 0x0000000d +#define MH_DEBUG_REG43__MMU_WE__SHIFT 0x00000010 +#define MH_DEBUG_REG43__ARQ_RTR__SHIFT 0x00000011 +#define MH_DEBUG_REG43__MMU_ID__SHIFT 0x00000012 +#define MH_DEBUG_REG43__MMU_WRITE__SHIFT 0x00000015 +#define MH_DEBUG_REG43__MMU_BLEN__SHIFT 0x00000016 +#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT 0x00000017 +#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT 0x00000018 +#define MH_DEBUG_REG43__WDB_WE__SHIFT 0x00000019 +#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT 0x0000001a +#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT 0x0000001b + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG44__ARB_ID_q__SHIFT 0x00000001 +#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT 0x00000004 + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG45__MMU_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG45__MMU_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG46__WDB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT 0x00000003 +#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT 0x00000004 +#define MH_DEBUG_REG46__ARB_WLAST__SHIFT 0x0000000c +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT 0x0000000e +#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT 0x00000013 +#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT 0x00000014 +#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT 0x00000017 +#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT 0x00000018 + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT 0x00000000 +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT 0x00000001 +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT 0x00000002 +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT 0x00000003 +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT 0x00000004 +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT 0x00000007 +#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT 0x0000000e +#define MH_DEBUG_REG49__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG49__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG49__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG49__BVALID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG49__BREADY_q__SHIFT 0x00000013 + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT 0x00000003 +#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT 0x00000004 +#define MH_DEBUG_REG50__RDC_VALID__SHIFT 0x00000005 +#define MH_DEBUG_REG50__RDC_RID__SHIFT 0x00000006 +#define MH_DEBUG_REG50__RDC_RLAST__SHIFT 0x00000009 +#define MH_DEBUG_REG50__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT 0x0000000c +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT 0x0000000e +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT 0x0000000f +#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT 0x00000015 +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT 0x0000001c +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT 0x00000000 +#define MH_DEBUG_REG52__ARB_WE__SHIFT 0x00000002 +#define MH_DEBUG_REG52__MMU_RTR__SHIFT 0x00000003 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT 0x00000004 +#define MH_DEBUG_REG52__ARB_ID_q__SHIFT 0x0000001a +#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT 0x0000001d +#define MH_DEBUG_REG52__client_behavior_q__SHIFT 0x0000001e + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid__SHIFT 0x00000000 +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT 0x00000001 +#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT 0x00000002 +#define MH_DEBUG_REG53__tag_match_q__SHIFT 0x00000003 +#define MH_DEBUG_REG53__tag_miss_q__SHIFT 0x00000004 +#define MH_DEBUG_REG53__va_in_range_q__SHIFT 0x00000005 +#define MH_DEBUG_REG53__MMU_MISS__SHIFT 0x00000006 +#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT 0x00000007 +#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT 0x00000008 +#define MH_DEBUG_REG53__MMU_HIT__SHIFT 0x00000009 +#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT 0x0000000a +#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT 0x0000000b +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT 0x0000000c +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT 0x0000000d +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT 0x0000000e +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT 0x0000000f +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT 0x00000010 + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR__SHIFT 0x00000000 +#define MH_DEBUG_REG54__MMU_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT 0x00000003 +#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT 0x00000004 +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005 +#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT 0x00000006 +#define MH_DEBUG_REG54__stage1_valid__SHIFT 0x00000007 +#define MH_DEBUG_REG54__stage2_valid__SHIFT 0x00000008 +#define MH_DEBUG_REG54__client_behavior_q__SHIFT 0x00000009 +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT 0x0000000b +#define MH_DEBUG_REG54__tag_match_q__SHIFT 0x0000000c +#define MH_DEBUG_REG54__tag_miss_q__SHIFT 0x0000000d +#define MH_DEBUG_REG54__va_in_range_q__SHIFT 0x0000000e +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT 0x0000000f +#define MH_DEBUG_REG54__TAG_valid_q__SHIFT 0x00000010 + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT 0x0000000d +#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG55__TAG1_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT 0x0000001d + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT 0x0000000d +#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG56__TAG3_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT 0x0000001d + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT 0x0000000d +#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG57__TAG5_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT 0x0000001d + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT 0x0000000d +#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG58__TAG7_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT 0x0000001d + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT 0x0000000d +#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG59__TAG9_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT 0x0000001d + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT 0x0000000d +#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG60__TAG11_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT 0x0000001d + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT 0x0000000d +#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG61__TAG13_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT 0x0000001d + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT 0x0000000d +#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG62__TAG15_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT 0x0000001d + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT 0x00000000 +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT 0x00000001 +#define MH_MMU_CONFIG__RESERVED1__SHIFT 0x00000002 +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004 +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006 +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008 +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010 +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012 +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014 +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016 +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT 0x00000018 + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT 0x00000000 +#define MH_MMU_VA_RANGE__VA_BASE__SHIFT 0x0000000c + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE__SHIFT 0x0000000c + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT 0x00000000 +#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT 0x00000001 +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT 0x00000002 +#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT 0x00000004 +#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT 0x00000007 +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008 +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT 0x00000009 +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT 0x0000000a +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT 0x0000000b +#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT 0x0000000c + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT 0x00000005 + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT 0x00000000 +#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT 0x00000001 + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT 0x0000000c + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END__SHIFT 0x0000000c + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT 0x00000001 +#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT 0x00000002 +#define WAIT_UNTIL__WAIT_VSYNC__SHIFT 0x00000003 +#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT 0x00000004 +#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT 0x00000005 +#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT 0x00000006 +#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT 0x0000000a +#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT 0x0000000e +#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT 0x0000000f +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT 0x00000010 +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT 0x00000011 +#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT 0x00000014 + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT 0x00000004 +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT 0x00000005 + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0x00000000 +#define RBBM_STATUS__TC_BUSY__SHIFT 0x00000005 +#define RBBM_STATUS__HIRQ_PENDING__SHIFT 0x00000008 +#define RBBM_STATUS__CPRQ_PENDING__SHIFT 0x00000009 +#define RBBM_STATUS__CFRQ_PENDING__SHIFT 0x0000000a +#define RBBM_STATUS__PFRQ_PENDING__SHIFT 0x0000000b +#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT 0x0000000c +#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT 0x0000000e +#define RBBM_STATUS__CP_NRT_BUSY__SHIFT 0x00000010 +#define RBBM_STATUS__MH_BUSY__SHIFT 0x00000012 +#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT 0x00000013 +#define RBBM_STATUS__SX_BUSY__SHIFT 0x00000015 +#define RBBM_STATUS__TPC_BUSY__SHIFT 0x00000016 +#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT 0x00000018 +#define RBBM_STATUS__PA_BUSY__SHIFT 0x00000019 +#define RBBM_STATUS__VGT_BUSY__SHIFT 0x0000001a +#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT 0x0000001b +#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT 0x0000001c +#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT 0x0000001e +#define RBBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT 0x00000000 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT 0x00000001 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT 0x00000002 +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT 0x00000003 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT 0x00000004 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT 0x00000005 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT 0x00000006 +#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT 0x00000007 +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT 0x00000008 +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT 0x0000000a +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT 0x0000000b +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT 0x0000000c +#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT 0x0000000d +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT 0x0000000e +#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT 0x00000010 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT 0x00000014 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT 0x00000015 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT 0x00000016 +#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT 0x00000017 +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT 0x00000018 +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT 0x0000001a +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT 0x0000001b +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT 0x0000001c +#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT 0x0000001d +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT 0x0000001e + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT 0x00000000 +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT 0x00000008 +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT 0x00000010 +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT 0x00000018 + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT 0x00000000 + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT 0x00000000 +#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT 0x00000010 +#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT 0x00000018 + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT 0x00000000 + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT 0x00000000 + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT 0x00000000 +#define RBBM_PERIPHID1__DESIGNER0__SHIFT 0x00000004 + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1__SHIFT 0x00000000 +#define RBBM_PERIPHID2__REVISION__SHIFT 0x00000004 + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT 0x00000000 +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT 0x00000002 +#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT 0x00000004 +#define RBBM_PERIPHID3__CONTINUATION__SHIFT 0x00000007 + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT 0x00000008 + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 +#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000005 + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 +#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT 0x00000002 +#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT 0x00000003 +#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT 0x00000004 +#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT 0x00000005 +#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT 0x00000006 +#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT 0x0000000c +#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT 0x0000000f +#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT 0x00000010 + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010 +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011 +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012 +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013 +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT 0x00000014 +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000015 +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT 0x00000016 +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000017 +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018 +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT 0x00000019 +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001a +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT 0x0000001b +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT 0x0000001c +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001d +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT 0x0000001e +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT 0x0000000b + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT 0x00000000 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT 0x00000010 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT 0x00000018 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT 0x00000019 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT 0x0000001d +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT 0x0000001e +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT 0x0000001f + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT 0x00000000 + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT 0x00000000 + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT 0x00000000 +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT 0x00000008 +#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT 0x0000000c +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT 0x00000010 +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT 0x00000018 +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT 0x0000001c + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR__SHIFT 0x00000001 +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT 0x00000002 +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT 0x00000003 +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT 0x00000004 +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT 0x00000008 +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT 0x00000010 +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000011 +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000012 +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000013 +#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT 0x00000014 +#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT 0x00000015 +#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT 0x00000016 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT 0x00000017 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT 0x00000018 +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT 0x0000001f + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT 0x0000001e +#define RBBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000 + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT 0x00000001 +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT 0x00000013 + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT 0x00000001 +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT 0x00000013 + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT 0x00000001 +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT 0x00000013 + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT 0x00000005 +#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT 0x0000001a +#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT 0x0000001e +#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT 0x0000001f + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x00000005 + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT 0x00000002 + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE__SHIFT 0x00000002 + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE__SHIFT 0x00000002 + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE__SHIFT 0x00000002 + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT 0x00000008 +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT 0x00000010 + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT 0x00000010 +#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT 0x00000018 + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT 0x00000000 +#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT 0x00000008 +#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT 0x00000010 + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT 0x00000000 + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT 0x00000010 + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT 0x00000010 + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT 0x00000010 + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT 0x00000000 +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT 0x00000008 + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT 0x00000000 +#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT 0x00000010 + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT 0x00000000 +#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT 0x00000001 +#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT 0x00000002 +#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT 0x00000003 +#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT 0x00000004 +#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT 0x00000005 +#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT 0x00000006 +#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT 0x00000007 +#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT 0x00000008 +#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT 0x00000009 +#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT 0x0000000a +#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT 0x0000000b +#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT 0x0000000c +#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT 0x0000000d +#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT 0x0000000e +#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT 0x0000000f +#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT 0x00000010 +#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT 0x00000011 +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT 0x0000001f + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX__SHIFT 0x00000000 +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT 0x00000019 +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT 0x0000001a +#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c +#define CP_ME_CNTL__ME_BUSY__SHIFT 0x0000001d +#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT 0x0000001f + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT 0x00000000 + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR__SHIFT 0x00000000 + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT 0x00000000 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x00000017 +#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT 0x00000018 +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT 0x00000019 +#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT 0x0000001a +#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT 0x0000001b +#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT 0x0000001c +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT 0x0000001e +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT 0x0000001f + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT 0x00000000 +#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT 0x00000010 + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT 0x00000005 + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT 0x00000000 +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT 0x00000002 + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000 + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK__SHIFT 0x00000013 +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT 0x00000017 +#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT 0x00000018 +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT 0x00000019 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT 0x0000001a +#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT 0x0000001b +#define CP_INT_CNTL__IB2_INT_MASK__SHIFT 0x0000001d +#define CP_INT_CNTL__IB1_INT_MASK__SHIFT 0x0000001e +#define CP_INT_CNTL__RB_INT_MASK__SHIFT 0x0000001f + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT 0x00000019 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS__IB2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS__IB1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS__RB_INT_STAT__SHIFT 0x0000001f + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK__SHIFT 0x00000013 +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT 0x00000017 +#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT 0x00000018 +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT 0x00000019 +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT 0x0000001a +#define CP_INT_ACK__IB_ERROR_ACK__SHIFT 0x0000001b +#define CP_INT_ACK__IB2_INT_ACK__SHIFT 0x0000001d +#define CP_INT_ACK__IB1_INT_ACK__SHIFT 0x0000001e +#define CP_INT_ACK__RB_INT_ACK__SHIFT 0x0000001f + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT 0x00000000 + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT 0x00000000 + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT 0x00000000 + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT 0x00000000 + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT 0x00000000 + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT 0x00000000 + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT 0x00000000 + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0__SHIFT 0x00000000 +#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT 0x00000001 +#define CP_NV_FLAGS_0__DISCARD_1__SHIFT 0x00000002 +#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT 0x00000003 +#define CP_NV_FLAGS_0__DISCARD_2__SHIFT 0x00000004 +#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT 0x00000005 +#define CP_NV_FLAGS_0__DISCARD_3__SHIFT 0x00000006 +#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT 0x00000007 +#define CP_NV_FLAGS_0__DISCARD_4__SHIFT 0x00000008 +#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT 0x00000009 +#define CP_NV_FLAGS_0__DISCARD_5__SHIFT 0x0000000a +#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT 0x0000000b +#define CP_NV_FLAGS_0__DISCARD_6__SHIFT 0x0000000c +#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT 0x0000000d +#define CP_NV_FLAGS_0__DISCARD_7__SHIFT 0x0000000e +#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT 0x0000000f +#define CP_NV_FLAGS_0__DISCARD_8__SHIFT 0x00000010 +#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT 0x00000011 +#define CP_NV_FLAGS_0__DISCARD_9__SHIFT 0x00000012 +#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT 0x00000013 +#define CP_NV_FLAGS_0__DISCARD_10__SHIFT 0x00000014 +#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT 0x00000015 +#define CP_NV_FLAGS_0__DISCARD_11__SHIFT 0x00000016 +#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT 0x00000017 +#define CP_NV_FLAGS_0__DISCARD_12__SHIFT 0x00000018 +#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT 0x00000019 +#define CP_NV_FLAGS_0__DISCARD_13__SHIFT 0x0000001a +#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT 0x0000001b +#define CP_NV_FLAGS_0__DISCARD_14__SHIFT 0x0000001c +#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT 0x0000001d +#define CP_NV_FLAGS_0__DISCARD_15__SHIFT 0x0000001e +#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT 0x0000001f + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16__SHIFT 0x00000000 +#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT 0x00000001 +#define CP_NV_FLAGS_1__DISCARD_17__SHIFT 0x00000002 +#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT 0x00000003 +#define CP_NV_FLAGS_1__DISCARD_18__SHIFT 0x00000004 +#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT 0x00000005 +#define CP_NV_FLAGS_1__DISCARD_19__SHIFT 0x00000006 +#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT 0x00000007 +#define CP_NV_FLAGS_1__DISCARD_20__SHIFT 0x00000008 +#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT 0x00000009 +#define CP_NV_FLAGS_1__DISCARD_21__SHIFT 0x0000000a +#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT 0x0000000b +#define CP_NV_FLAGS_1__DISCARD_22__SHIFT 0x0000000c +#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT 0x0000000d +#define CP_NV_FLAGS_1__DISCARD_23__SHIFT 0x0000000e +#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT 0x0000000f +#define CP_NV_FLAGS_1__DISCARD_24__SHIFT 0x00000010 +#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT 0x00000011 +#define CP_NV_FLAGS_1__DISCARD_25__SHIFT 0x00000012 +#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT 0x00000013 +#define CP_NV_FLAGS_1__DISCARD_26__SHIFT 0x00000014 +#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT 0x00000015 +#define CP_NV_FLAGS_1__DISCARD_27__SHIFT 0x00000016 +#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT 0x00000017 +#define CP_NV_FLAGS_1__DISCARD_28__SHIFT 0x00000018 +#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT 0x00000019 +#define CP_NV_FLAGS_1__DISCARD_29__SHIFT 0x0000001a +#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT 0x0000001b +#define CP_NV_FLAGS_1__DISCARD_30__SHIFT 0x0000001c +#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT 0x0000001d +#define CP_NV_FLAGS_1__DISCARD_31__SHIFT 0x0000001e +#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT 0x0000001f + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32__SHIFT 0x00000000 +#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT 0x00000001 +#define CP_NV_FLAGS_2__DISCARD_33__SHIFT 0x00000002 +#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT 0x00000003 +#define CP_NV_FLAGS_2__DISCARD_34__SHIFT 0x00000004 +#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT 0x00000005 +#define CP_NV_FLAGS_2__DISCARD_35__SHIFT 0x00000006 +#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT 0x00000007 +#define CP_NV_FLAGS_2__DISCARD_36__SHIFT 0x00000008 +#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT 0x00000009 +#define CP_NV_FLAGS_2__DISCARD_37__SHIFT 0x0000000a +#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT 0x0000000b +#define CP_NV_FLAGS_2__DISCARD_38__SHIFT 0x0000000c +#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT 0x0000000d +#define CP_NV_FLAGS_2__DISCARD_39__SHIFT 0x0000000e +#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT 0x0000000f +#define CP_NV_FLAGS_2__DISCARD_40__SHIFT 0x00000010 +#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT 0x00000011 +#define CP_NV_FLAGS_2__DISCARD_41__SHIFT 0x00000012 +#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT 0x00000013 +#define CP_NV_FLAGS_2__DISCARD_42__SHIFT 0x00000014 +#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT 0x00000015 +#define CP_NV_FLAGS_2__DISCARD_43__SHIFT 0x00000016 +#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT 0x00000017 +#define CP_NV_FLAGS_2__DISCARD_44__SHIFT 0x00000018 +#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT 0x00000019 +#define CP_NV_FLAGS_2__DISCARD_45__SHIFT 0x0000001a +#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT 0x0000001b +#define CP_NV_FLAGS_2__DISCARD_46__SHIFT 0x0000001c +#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT 0x0000001d +#define CP_NV_FLAGS_2__DISCARD_47__SHIFT 0x0000001e +#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT 0x0000001f + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48__SHIFT 0x00000000 +#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT 0x00000001 +#define CP_NV_FLAGS_3__DISCARD_49__SHIFT 0x00000002 +#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT 0x00000003 +#define CP_NV_FLAGS_3__DISCARD_50__SHIFT 0x00000004 +#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT 0x00000005 +#define CP_NV_FLAGS_3__DISCARD_51__SHIFT 0x00000006 +#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT 0x00000007 +#define CP_NV_FLAGS_3__DISCARD_52__SHIFT 0x00000008 +#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT 0x00000009 +#define CP_NV_FLAGS_3__DISCARD_53__SHIFT 0x0000000a +#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT 0x0000000b +#define CP_NV_FLAGS_3__DISCARD_54__SHIFT 0x0000000c +#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT 0x0000000d +#define CP_NV_FLAGS_3__DISCARD_55__SHIFT 0x0000000e +#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT 0x0000000f +#define CP_NV_FLAGS_3__DISCARD_56__SHIFT 0x00000010 +#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT 0x00000011 +#define CP_NV_FLAGS_3__DISCARD_57__SHIFT 0x00000012 +#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT 0x00000013 +#define CP_NV_FLAGS_3__DISCARD_58__SHIFT 0x00000014 +#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT 0x00000015 +#define CP_NV_FLAGS_3__DISCARD_59__SHIFT 0x00000016 +#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT 0x00000017 +#define CP_NV_FLAGS_3__DISCARD_60__SHIFT 0x00000018 +#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT 0x00000019 +#define CP_NV_FLAGS_3__DISCARD_61__SHIFT 0x0000001a +#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT 0x0000001b +#define CP_NV_FLAGS_3__DISCARD_62__SHIFT 0x0000001c +#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT 0x0000001d +#define CP_NV_FLAGS_3__DISCARD_63__SHIFT 0x0000001e +#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT 0x0000001f + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT 0x00000000 + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT 0x00000000 + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER__SHIFT 0x00000000 + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY__SHIFT 0x00000000 +#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT 0x00000001 +#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT 0x00000002 +#define CP_STAT__RBIU_BUSY__SHIFT 0x00000003 +#define CP_STAT__RCIU_BUSY__SHIFT 0x00000004 +#define CP_STAT__CSF_RING_BUSY__SHIFT 0x00000005 +#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT 0x00000006 +#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x00000007 +#define CP_STAT__CSF_ST_BUSY__SHIFT 0x00000009 +#define CP_STAT__CSF_BUSY__SHIFT 0x0000000a +#define CP_STAT__RING_QUEUE_BUSY__SHIFT 0x0000000b +#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT 0x0000000c +#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT 0x0000000d +#define CP_STAT__ST_QUEUE_BUSY__SHIFT 0x00000010 +#define CP_STAT__PFP_BUSY__SHIFT 0x00000011 +#define CP_STAT__MEQ_RING_BUSY__SHIFT 0x00000012 +#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT 0x00000013 +#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT 0x00000014 +#define CP_STAT__MIU_WC_STALL__SHIFT 0x00000015 +#define CP_STAT__CP_NRT_BUSY__SHIFT 0x00000016 +#define CP_STAT___3D_BUSY__SHIFT 0x00000017 +#define CP_STAT__ME_BUSY__SHIFT 0x0000001a +#define CP_STAT__ME_WC_BUSY__SHIFT 0x0000001d +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT 0x0000001e +#define CP_STAT__CP_BUSY__SHIFT 0x0000001f + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE__SHIFT 0x00000000 + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE__SHIFT 0x00000000 + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_PM4__STATUS__SHIFT 0x0000001f + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE__SHIFT 0x00000000 + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE__SHIFT 0x00000000 + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_HOST__STATUS__SHIFT 0x0000001f + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT 0x0000000c + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT 0x0000000c + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT 0x0000000c + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT 0x0000000c + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT 0x0000000c + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT 0x0000000c + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT 0x0000000c + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT 0x0000000c + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT 0x00000000 +#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT 0x0000000e + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000 +#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT 0x00000004 +#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT 0x00000006 +#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT 0x00000007 +#define RB_COLOR_INFO__COLOR_SWAP__SHIFT 0x00000009 +#define RB_COLOR_INFO__COLOR_BASE__SHIFT 0x0000000c + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT 0x00000000 +#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT 0x0000000c + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF__SHIFT 0x00000000 +#define RB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 +#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 +#define RB_STENCILREFMASK__RESERVED0__SHIFT 0x00000018 +#define RB_STENCILREFMASK__RESERVED1__SHIFT 0x00000019 + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF__SHIFT 0x00000000 + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED__SHIFT 0x00000000 +#define RB_COLOR_MASK__WRITE_GREEN__SHIFT 0x00000001 +#define RB_COLOR_MASK__WRITE_BLUE__SHIFT 0x00000002 +#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT 0x00000003 +#define RB_COLOR_MASK__RESERVED2__SHIFT 0x00000004 +#define RB_COLOR_MASK__RESERVED3__SHIFT 0x00000005 + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED__SHIFT 0x00000000 +#define RB_FOG_COLOR__FOG_GREEN__SHIFT 0x00000008 +#define RB_FOG_COLOR__FOG_BLUE__SHIFT 0x00000010 + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT 0x00000000 +#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 +#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT 0x00000018 +#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT 0x00000019 + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT 0x00000000 +#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT 0x00000001 +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT 0x00000003 +#define RB_DEPTHCONTROL__ZFUNC__SHIFT 0x00000004 +#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 +#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT 0x00000008 +#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT 0x0000000b +#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT 0x0000000e +#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT 0x00000011 +#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT 0x00000014 +#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT 0x00000017 +#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT 0x0000001a +#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT 0x0000001d + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT 0x0000001d +#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT 0x0000001e + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT 0x00000000 +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT 0x00000003 +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000004 +#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT 0x00000005 +#define RB_COLORCONTROL__FOG_ENABLE__SHIFT 0x00000006 +#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT 0x00000007 +#define RB_COLORCONTROL__ROP_CODE__SHIFT 0x00000008 +#define RB_COLORCONTROL__DITHER_MODE__SHIFT 0x0000000c +#define RB_COLORCONTROL__DITHER_TYPE__SHIFT 0x0000000e +#define RB_COLORCONTROL__PIXEL_FOG__SHIFT 0x00000010 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000018 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000001a +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000001c +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000001e + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE__SHIFT 0x00000000 + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT 0x00000000 + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT 0x00000000 +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000003 +#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT 0x00000004 + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT 0x0000000c + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT 0x00000000 + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT 0x00000000 +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT 0x00000003 +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004 +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT 0x00000008 +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT 0x0000000a +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT 0x0000000c +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT 0x0000000e +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT 0x0000000f +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT 0x00000010 +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT 0x00000011 + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT 0x00000000 +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT 0x0000000d + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT 0x00000000 +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT 0x00000001 + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT 0x00000000 + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT 0x00000000 +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT 0x00000001 +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT 0x00000003 +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004 +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT 0x00000005 +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT 0x00000006 +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT 0x00000007 +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT 0x00000008 +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT 0x0000000e +#define RB_BC_CONTROL__CRC_MODE__SHIFT 0x0000000f +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT 0x00000010 +#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT 0x00000011 +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT 0x00000012 +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT 0x00000016 +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT 0x00000017 +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT 0x0000001b +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d +#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT 0x0000001e +#define RB_BC_CONTROL__RESERVED6__SHIFT 0x0000001f + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT 0x00000000 +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004 +#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA__SHIFT 0x00000000 + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT 0x00000000 + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT 0x00000000 + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT 0x00000000 + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT 0x00000000 +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT 0x00000001 +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT 0x00000002 +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT 0x00000003 +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT 0x00000004 +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT 0x00000005 +#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT 0x00000006 +#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT 0x00000007 +#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT 0x00000008 +#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT 0x00000009 +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT 0x0000000a +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT 0x0000000b +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT 0x0000000c +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT 0x0000000d +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT 0x0000000e +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT 0x0000000f +#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT 0x00000010 +#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT 0x00000011 +#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT 0x00000012 +#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT 0x00000013 +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT 0x00000014 +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT 0x00000015 +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT 0x00000016 +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT 0x00000017 +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT 0x00000018 +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT 0x00000019 +#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT 0x0000001a +#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT 0x0000001b +#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT 0x0000001c +#define RB_DEBUG_0__C_REQ_FULL__SHIFT 0x0000001d +#define RB_DEBUG_0__C_MASK_FULL__SHIFT 0x0000001e +#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT 0x0000001f + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT 0x00000000 +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT 0x00000001 +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT 0x00000002 +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT 0x00000003 +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT 0x00000006 +#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT 0x00000007 +#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT 0x00000008 +#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT 0x00000009 +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT 0x0000000a +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT 0x0000000b +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT 0x0000000c +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT 0x0000000d +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT 0x0000000e +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT 0x0000000f +#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT 0x00000010 +#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT 0x00000011 +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT 0x00000012 +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT 0x00000013 +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT 0x00000000 +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT 0x00000004 +#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT 0x0000000b +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT 0x0000000c +#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT 0x0000000d +#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT 0x0000000e +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT 0x0000000f +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT 0x00000010 +#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT 0x00000011 +#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT 0x00000012 +#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT 0x00000013 +#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT 0x00000014 +#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT 0x00000015 +#define RB_DEBUG_2__Z_TILE_FULL__SHIFT 0x00000016 +#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID__SHIFT 0x00000000 +#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT 0x00000004 +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT 0x00000008 +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT 0x0000000e +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT 0x0000000f +#define RB_DEBUG_3__SHD_FULL__SHIFT 0x00000013 +#define RB_DEBUG_3__SHD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT 0x00000017 +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT 0x00000018 +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT 0x0000001b +#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT 0x0000001c + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT 0x00000000 +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT 0x00000001 +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT 0x00000002 +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT 0x00000003 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT 0x00000006 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT 0x00000007 +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT 0x00000008 +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT 0x00000009 + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT 0x00000000 + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED__SHIFT 0x00000000 + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT 0x00000009 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000 + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h new file mode 100644 index 000000000000..78d4924ef79d --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h @@ -0,0 +1,52583 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_CP_FIDDLE_H) +#define _CP_FIDDLE_H + + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * CP_RB_BASE struct + */ + +#define CP_RB_BASE_RB_BASE_SIZE 27 + +#define CP_RB_BASE_RB_BASE_SHIFT 5 + +#define CP_RB_BASE_RB_BASE_MASK 0xffffffe0 + +#define CP_RB_BASE_MASK \ + (CP_RB_BASE_RB_BASE_MASK) + +#define CP_RB_BASE(rb_base) \ + ((rb_base << CP_RB_BASE_RB_BASE_SHIFT)) + +#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \ + ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT) + +#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \ + cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int : 5; + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + } cp_rb_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + unsigned int : 5; + } cp_rb_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_base_t f; +} cp_rb_base_u; + + +/* + * CP_RB_CNTL struct + */ + +#define CP_RB_CNTL_RB_BUFSZ_SIZE 6 +#define CP_RB_CNTL_RB_BLKSZ_SIZE 6 +#define CP_RB_CNTL_BUF_SWAP_SIZE 2 +#define CP_RB_CNTL_RB_POLL_EN_SIZE 1 +#define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1 + +#define CP_RB_CNTL_RB_BUFSZ_SHIFT 0 +#define CP_RB_CNTL_RB_BLKSZ_SHIFT 8 +#define CP_RB_CNTL_BUF_SWAP_SHIFT 16 +#define CP_RB_CNTL_RB_POLL_EN_SHIFT 20 +#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT 27 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31 + +#define CP_RB_CNTL_RB_BUFSZ_MASK 0x0000003f +#define CP_RB_CNTL_RB_BLKSZ_MASK 0x00003f00 +#define CP_RB_CNTL_BUF_SWAP_MASK 0x00030000 +#define CP_RB_CNTL_RB_POLL_EN_MASK 0x00100000 +#define CP_RB_CNTL_RB_NO_UPDATE_MASK 0x08000000 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000 + +#define CP_RB_CNTL_MASK \ + (CP_RB_CNTL_RB_BUFSZ_MASK | \ + CP_RB_CNTL_RB_BLKSZ_MASK | \ + CP_RB_CNTL_BUF_SWAP_MASK | \ + CP_RB_CNTL_RB_POLL_EN_MASK | \ + CP_RB_CNTL_RB_NO_UPDATE_MASK | \ + CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) + +#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \ + ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \ + (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \ + (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \ + (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \ + (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \ + (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)) + +#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 6; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 3; + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + } cp_rb_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + unsigned int : 3; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 6; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + } cp_rb_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_cntl_t f; +} cp_rb_cntl_u; + + +/* + * CP_RB_RPTR_ADDR struct + */ + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc + +#define CP_RB_RPTR_ADDR_MASK \ + (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \ + CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) + +#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \ + ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \ + (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)) + +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + } cp_rb_rptr_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + } cp_rb_rptr_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_addr_t f; +} cp_rb_rptr_addr_u; + + +/* + * CP_RB_RPTR struct + */ + +#define CP_RB_RPTR_RB_RPTR_SIZE 20 + +#define CP_RB_RPTR_RB_RPTR_SHIFT 0 + +#define CP_RB_RPTR_RB_RPTR_MASK 0x000fffff + +#define CP_RB_RPTR_MASK \ + (CP_RB_RPTR_RB_RPTR_MASK) + +#define CP_RB_RPTR(rb_rptr) \ + ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)) + +#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \ + ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT) + +#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \ + cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + unsigned int : 12; + } cp_rb_rptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int : 12; + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + } cp_rb_rptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_t f; +} cp_rb_rptr_u; + + +/* + * CP_RB_RPTR_WR struct + */ + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE 20 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK 0x000fffff + +#define CP_RB_RPTR_WR_MASK \ + (CP_RB_RPTR_WR_RB_RPTR_WR_MASK) + +#define CP_RB_RPTR_WR(rb_rptr_wr) \ + ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)) + +#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \ + ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \ + cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + unsigned int : 12; + } cp_rb_rptr_wr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int : 12; + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + } cp_rb_rptr_wr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_wr_t f; +} cp_rb_rptr_wr_u; + + +/* + * CP_RB_WPTR struct + */ + +#define CP_RB_WPTR_RB_WPTR_SIZE 20 + +#define CP_RB_WPTR_RB_WPTR_SHIFT 0 + +#define CP_RB_WPTR_RB_WPTR_MASK 0x000fffff + +#define CP_RB_WPTR_MASK \ + (CP_RB_WPTR_RB_WPTR_MASK) + +#define CP_RB_WPTR(rb_wptr) \ + ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)) + +#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \ + ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT) + +#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \ + cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + unsigned int : 12; + } cp_rb_wptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int : 12; + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + } cp_rb_wptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_t f; +} cp_rb_wptr_u; + + +/* + * CP_RB_WPTR_DELAY struct + */ + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000 + +#define CP_RB_WPTR_DELAY_MASK \ + (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \ + CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) + +#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \ + ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \ + (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)) + +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + } cp_rb_wptr_delay_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + } cp_rb_wptr_delay_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_delay_t f; +} cp_rb_wptr_delay_u; + + +/* + * CP_RB_WPTR_BASE struct + */ + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc + +#define CP_RB_WPTR_BASE_MASK \ + (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \ + CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) + +#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \ + ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \ + (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)) + +#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + } cp_rb_wptr_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + } cp_rb_wptr_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_base_t f; +} cp_rb_wptr_base_u; + + +/* + * CP_IB1_BASE struct + */ + +#define CP_IB1_BASE_IB1_BASE_SIZE 30 + +#define CP_IB1_BASE_IB1_BASE_SHIFT 2 + +#define CP_IB1_BASE_IB1_BASE_MASK 0xfffffffc + +#define CP_IB1_BASE_MASK \ + (CP_IB1_BASE_IB1_BASE_MASK) + +#define CP_IB1_BASE(ib1_base) \ + ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)) + +#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \ + ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT) + +#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \ + cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int : 2; + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + } cp_ib1_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + unsigned int : 2; + } cp_ib1_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_base_t f; +} cp_ib1_base_u; + + +/* + * CP_IB1_BUFSZ struct + */ + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE 20 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT 0 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK 0x000fffff + +#define CP_IB1_BUFSZ_MASK \ + (CP_IB1_BUFSZ_IB1_BUFSZ_MASK) + +#define CP_IB1_BUFSZ(ib1_bufsz) \ + ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)) + +#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \ + ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \ + cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib1_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int : 12; + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + } cp_ib1_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_bufsz_t f; +} cp_ib1_bufsz_u; + + +/* + * CP_IB2_BASE struct + */ + +#define CP_IB2_BASE_IB2_BASE_SIZE 30 + +#define CP_IB2_BASE_IB2_BASE_SHIFT 2 + +#define CP_IB2_BASE_IB2_BASE_MASK 0xfffffffc + +#define CP_IB2_BASE_MASK \ + (CP_IB2_BASE_IB2_BASE_MASK) + +#define CP_IB2_BASE(ib2_base) \ + ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)) + +#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \ + ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT) + +#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \ + cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int : 2; + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + } cp_ib2_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + unsigned int : 2; + } cp_ib2_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_base_t f; +} cp_ib2_base_u; + + +/* + * CP_IB2_BUFSZ struct + */ + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE 20 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT 0 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK 0x000fffff + +#define CP_IB2_BUFSZ_MASK \ + (CP_IB2_BUFSZ_IB2_BUFSZ_MASK) + +#define CP_IB2_BUFSZ(ib2_bufsz) \ + ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)) + +#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \ + ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \ + cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib2_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int : 12; + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + } cp_ib2_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_bufsz_t f; +} cp_ib2_bufsz_u; + + +/* + * CP_ST_BASE struct + */ + +#define CP_ST_BASE_ST_BASE_SIZE 30 + +#define CP_ST_BASE_ST_BASE_SHIFT 2 + +#define CP_ST_BASE_ST_BASE_MASK 0xfffffffc + +#define CP_ST_BASE_MASK \ + (CP_ST_BASE_ST_BASE_MASK) + +#define CP_ST_BASE(st_base) \ + ((st_base << CP_ST_BASE_ST_BASE_SHIFT)) + +#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \ + ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT) + +#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \ + cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int : 2; + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + } cp_st_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + unsigned int : 2; + } cp_st_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_base_t f; +} cp_st_base_u; + + +/* + * CP_ST_BUFSZ struct + */ + +#define CP_ST_BUFSZ_ST_BUFSZ_SIZE 20 + +#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT 0 + +#define CP_ST_BUFSZ_ST_BUFSZ_MASK 0x000fffff + +#define CP_ST_BUFSZ_MASK \ + (CP_ST_BUFSZ_ST_BUFSZ_MASK) + +#define CP_ST_BUFSZ(st_bufsz) \ + ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)) + +#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \ + ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \ + cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + unsigned int : 12; + } cp_st_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int : 12; + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + } cp_st_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_bufsz_t f; +} cp_st_bufsz_u; + + +/* + * CP_QUEUE_THRESHOLDS struct + */ + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000 + +#define CP_QUEUE_THRESHOLDS_MASK \ + (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) + +#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \ + ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \ + (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \ + (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)) + +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 12; + } cp_queue_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int : 12; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + } cp_queue_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_queue_thresholds_t f; +} cp_queue_thresholds_u; + + +/* + * CP_MEQ_THRESHOLDS struct + */ + +#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5 +#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5 + +#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16 +#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24 + +#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000 +#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000 + +#define CP_MEQ_THRESHOLDS_MASK \ + (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \ + CP_MEQ_THRESHOLDS_ROQ_END_MASK) + +#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \ + ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \ + (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)) + +#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 16; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + } cp_meq_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 16; + } cp_meq_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_thresholds_t f; +} cp_meq_thresholds_u; + + +/* + * CP_CSQ_AVAIL struct + */ + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE 7 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK 0x00007f00 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK 0x007f0000 + +#define CP_CSQ_AVAIL_MASK \ + (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) + +#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \ + ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \ + (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \ + (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)) + +#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 9; + } cp_csq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int : 9; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + } cp_csq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_avail_t f; +} cp_csq_avail_u; + + +/* + * CP_STQ_AVAIL struct + */ + +#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE 7 + +#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT 0 + +#define CP_STQ_AVAIL_STQ_CNT_ST_MASK 0x0000007f + +#define CP_STQ_AVAIL_MASK \ + (CP_STQ_AVAIL_STQ_CNT_ST_MASK) + +#define CP_STQ_AVAIL(stq_cnt_st) \ + ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)) + +#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \ + ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \ + cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + unsigned int : 25; + } cp_stq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int : 25; + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + } cp_stq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_avail_t f; +} cp_stq_avail_u; + + +/* + * CP_MEQ_AVAIL struct + */ + +#define CP_MEQ_AVAIL_MEQ_CNT_SIZE 5 + +#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT 0 + +#define CP_MEQ_AVAIL_MEQ_CNT_MASK 0x0000001f + +#define CP_MEQ_AVAIL_MASK \ + (CP_MEQ_AVAIL_MEQ_CNT_MASK) + +#define CP_MEQ_AVAIL(meq_cnt) \ + ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)) + +#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \ + ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \ + cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + unsigned int : 27; + } cp_meq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int : 27; + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + } cp_meq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_avail_t f; +} cp_meq_avail_u; + + +/* + * CP_CSQ_RB_STAT struct + */ + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000 + +#define CP_CSQ_RB_STAT_MASK \ + (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \ + CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) + +#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \ + ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \ + (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)) + +#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + } cp_csq_rb_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + } cp_csq_rb_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_rb_stat_t f; +} cp_csq_rb_stat_u; + + +/* + * CP_CSQ_IB1_STAT struct + */ + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000 + +#define CP_CSQ_IB1_STAT_MASK \ + (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \ + CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) + +#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \ + ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \ + (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)) + +#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + } cp_csq_ib1_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + } cp_csq_ib1_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib1_stat_t f; +} cp_csq_ib1_stat_u; + + +/* + * CP_CSQ_IB2_STAT struct + */ + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000 + +#define CP_CSQ_IB2_STAT_MASK \ + (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \ + CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) + +#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \ + ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \ + (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)) + +#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + } cp_csq_ib2_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + } cp_csq_ib2_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib2_stat_t f; +} cp_csq_ib2_stat_u; + + +/* + * CP_NON_PREFETCH_CNTRS struct + */ + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700 + +#define CP_NON_PREFETCH_CNTRS_MASK \ + (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \ + CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) + +#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \ + ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \ + (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)) + +#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 21; + } cp_non_prefetch_cntrs_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int : 21; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + } cp_non_prefetch_cntrs_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_non_prefetch_cntrs_t f; +} cp_non_prefetch_cntrs_u; + + +/* + * CP_STQ_ST_STAT struct + */ + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f +#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000 + +#define CP_STQ_ST_STAT_MASK \ + (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \ + CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) + +#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \ + ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \ + (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)) + +#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + } cp_stq_st_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + } cp_stq_st_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_st_stat_t f; +} cp_stq_st_stat_u; + + +/* + * CP_MEQ_STAT struct + */ + +#define CP_MEQ_STAT_MEQ_RPTR_SIZE 10 +#define CP_MEQ_STAT_MEQ_WPTR_SIZE 10 + +#define CP_MEQ_STAT_MEQ_RPTR_SHIFT 0 +#define CP_MEQ_STAT_MEQ_WPTR_SHIFT 16 + +#define CP_MEQ_STAT_MEQ_RPTR_MASK 0x000003ff +#define CP_MEQ_STAT_MEQ_WPTR_MASK 0x03ff0000 + +#define CP_MEQ_STAT_MASK \ + (CP_MEQ_STAT_MEQ_RPTR_MASK | \ + CP_MEQ_STAT_MEQ_WPTR_MASK) + +#define CP_MEQ_STAT(meq_rptr, meq_wptr) \ + ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \ + (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)) + +#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + } cp_meq_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + } cp_meq_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_stat_t f; +} cp_meq_stat_u; + + +/* + * CP_MIU_TAG_STAT struct + */ + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001 +#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002 +#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004 +#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008 +#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010 +#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020 +#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040 +#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080 +#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100 +#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200 +#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400 +#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800 +#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000 +#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000 +#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000 +#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000 +#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000 +#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000 + +#define CP_MIU_TAG_STAT_MASK \ + (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \ + CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) + +#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \ + ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \ + (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \ + (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \ + (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \ + (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \ + (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \ + (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \ + (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \ + (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \ + (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \ + (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \ + (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \ + (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \ + (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \ + (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \ + (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \ + (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \ + (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \ + (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)) + +#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int : 13; + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + } cp_miu_tag_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + unsigned int : 13; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + } cp_miu_tag_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_miu_tag_stat_t f; +} cp_miu_tag_stat_u; + + +/* + * CP_CMD_INDEX struct + */ + +#define CP_CMD_INDEX_CMD_INDEX_SIZE 7 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2 + +#define CP_CMD_INDEX_CMD_INDEX_SHIFT 0 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16 + +#define CP_CMD_INDEX_CMD_INDEX_MASK 0x0000007f +#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000 + +#define CP_CMD_INDEX_MASK \ + (CP_CMD_INDEX_CMD_INDEX_MASK | \ + CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) + +#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \ + ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \ + (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)) + +#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + unsigned int : 9; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 14; + } cp_cmd_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int : 14; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 9; + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + } cp_cmd_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_index_t f; +} cp_cmd_index_u; + + +/* + * CP_CMD_DATA struct + */ + +#define CP_CMD_DATA_CMD_DATA_SIZE 32 + +#define CP_CMD_DATA_CMD_DATA_SHIFT 0 + +#define CP_CMD_DATA_CMD_DATA_MASK 0xffffffff + +#define CP_CMD_DATA_MASK \ + (CP_CMD_DATA_CMD_DATA_MASK) + +#define CP_CMD_DATA(cmd_data) \ + ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)) + +#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \ + ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT) + +#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \ + cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_data_t f; +} cp_cmd_data_u; + + +/* + * CP_ME_CNTL struct + */ + +#define CP_ME_CNTL_ME_STATMUX_SIZE 16 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_ME_HALT_SIZE 1 +#define CP_ME_CNTL_ME_BUSY_SIZE 1 +#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE 1 + +#define CP_ME_CNTL_ME_STATMUX_SHIFT 0 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26 +#define CP_ME_CNTL_ME_HALT_SHIFT 28 +#define CP_ME_CNTL_ME_BUSY_SHIFT 29 +#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31 + +#define CP_ME_CNTL_ME_STATMUX_MASK 0x0000ffff +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000 +#define CP_ME_CNTL_ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL_ME_BUSY_MASK 0x20000000 +#define CP_ME_CNTL_PROG_CNT_SIZE_MASK 0x80000000 + +#define CP_ME_CNTL_MASK \ + (CP_ME_CNTL_ME_STATMUX_MASK | \ + CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_ME_HALT_MASK | \ + CP_ME_CNTL_ME_BUSY_MASK | \ + CP_ME_CNTL_PROG_CNT_SIZE_MASK) + +#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \ + ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \ + (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \ + (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \ + (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)) + +#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + unsigned int : 9; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 1; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int : 1; + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + } cp_me_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + unsigned int : 1; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int : 1; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 9; + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + } cp_me_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cntl_t f; +} cp_me_cntl_u; + + +/* + * CP_ME_STATUS struct + */ + +#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32 + +#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0 + +#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff + +#define CP_ME_STATUS_MASK \ + (CP_ME_STATUS_ME_DEBUG_DATA_MASK) + +#define CP_ME_STATUS(me_debug_data) \ + ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)) + +#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \ + ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \ + cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_status_t f; +} cp_me_status_u; + + +/* + * CP_ME_RAM_WADDR struct + */ + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff + +#define CP_ME_RAM_WADDR_MASK \ + (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) + +#define CP_ME_RAM_WADDR(me_ram_waddr) \ + ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)) + +#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \ + ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \ + cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + unsigned int : 22; + } cp_me_ram_waddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int : 22; + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + } cp_me_ram_waddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_waddr_t f; +} cp_me_ram_waddr_u; + + +/* + * CP_ME_RAM_RADDR struct + */ + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff + +#define CP_ME_RAM_RADDR_MASK \ + (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) + +#define CP_ME_RAM_RADDR(me_ram_raddr) \ + ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)) + +#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \ + ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \ + cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + unsigned int : 22; + } cp_me_ram_raddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int : 22; + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + } cp_me_ram_raddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_raddr_t f; +} cp_me_ram_raddr_u; + + +/* + * CP_ME_RAM_DATA struct + */ + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff + +#define CP_ME_RAM_DATA_MASK \ + (CP_ME_RAM_DATA_ME_RAM_DATA_MASK) + +#define CP_ME_RAM_DATA(me_ram_data) \ + ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)) + +#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \ + ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \ + cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_data_t f; +} cp_me_ram_data_u; + + +/* + * CP_ME_RDADDR struct + */ + +#define CP_ME_RDADDR_ME_RDADDR_SIZE 32 + +#define CP_ME_RDADDR_ME_RDADDR_SHIFT 0 + +#define CP_ME_RDADDR_ME_RDADDR_MASK 0xffffffff + +#define CP_ME_RDADDR_MASK \ + (CP_ME_RDADDR_ME_RDADDR_MASK) + +#define CP_ME_RDADDR(me_rdaddr) \ + ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)) + +#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \ + ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \ + cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_rdaddr_t f; +} cp_me_rdaddr_u; + + +/* + * CP_DEBUG struct + */ + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23 +#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0 +#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff +#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000 +#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000 +#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000 + +#define CP_DEBUG_MASK \ + (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \ + CP_DEBUG_PREDICATE_DISABLE_MASK | \ + CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \ + CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \ + CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \ + CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \ + CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \ + CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \ + CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) + +#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \ + ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \ + (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \ + (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \ + (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \ + (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \ + (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \ + (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \ + (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \ + (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)) + +#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \ + ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \ + ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int : 1; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + } cp_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int : 1; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + } cp_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_debug_t f; +} cp_debug_u; + + +/* + * SCRATCH_REG0 struct + */ + +#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32 + +#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0 + +#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff + +#define SCRATCH_REG0_MASK \ + (SCRATCH_REG0_SCRATCH_REG0_MASK) + +#define SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)) + +#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \ + scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg0_t f; +} scratch_reg0_u; + + +/* + * SCRATCH_REG1 struct + */ + +#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32 + +#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0 + +#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff + +#define SCRATCH_REG1_MASK \ + (SCRATCH_REG1_SCRATCH_REG1_MASK) + +#define SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)) + +#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \ + scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg1_t f; +} scratch_reg1_u; + + +/* + * SCRATCH_REG2 struct + */ + +#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32 + +#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0 + +#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff + +#define SCRATCH_REG2_MASK \ + (SCRATCH_REG2_SCRATCH_REG2_MASK) + +#define SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)) + +#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \ + scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg2_t f; +} scratch_reg2_u; + + +/* + * SCRATCH_REG3 struct + */ + +#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32 + +#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0 + +#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff + +#define SCRATCH_REG3_MASK \ + (SCRATCH_REG3_SCRATCH_REG3_MASK) + +#define SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)) + +#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \ + scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg3_t f; +} scratch_reg3_u; + + +/* + * SCRATCH_REG4 struct + */ + +#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32 + +#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0 + +#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff + +#define SCRATCH_REG4_MASK \ + (SCRATCH_REG4_SCRATCH_REG4_MASK) + +#define SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)) + +#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \ + scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg4_t f; +} scratch_reg4_u; + + +/* + * SCRATCH_REG5 struct + */ + +#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32 + +#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0 + +#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff + +#define SCRATCH_REG5_MASK \ + (SCRATCH_REG5_SCRATCH_REG5_MASK) + +#define SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)) + +#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \ + scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg5_t f; +} scratch_reg5_u; + + +/* + * SCRATCH_REG6 struct + */ + +#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32 + +#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0 + +#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff + +#define SCRATCH_REG6_MASK \ + (SCRATCH_REG6_SCRATCH_REG6_MASK) + +#define SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)) + +#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \ + scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg6_t f; +} scratch_reg6_u; + + +/* + * SCRATCH_REG7 struct + */ + +#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32 + +#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0 + +#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff + +#define SCRATCH_REG7_MASK \ + (SCRATCH_REG7_SCRATCH_REG7_MASK) + +#define SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)) + +#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \ + scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg7_t f; +} scratch_reg7_u; + + +/* + * SCRATCH_UMSK struct + */ + +#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8 +#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2 + +#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0 +#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16 + +#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff +#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000 + +#define SCRATCH_UMSK_MASK \ + (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \ + SCRATCH_UMSK_SCRATCH_SWAP_MASK) + +#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \ + ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \ + (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)) + +#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + unsigned int : 8; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 14; + } scratch_umsk_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int : 14; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 8; + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + } scratch_umsk_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_umsk_t f; +} scratch_umsk_u; + + +/* + * SCRATCH_ADDR struct + */ + +#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27 + +#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5 + +#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0 + +#define SCRATCH_ADDR_MASK \ + (SCRATCH_ADDR_SCRATCH_ADDR_MASK) + +#define SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)) + +#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \ + scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int : 5; + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + } scratch_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + unsigned int : 5; + } scratch_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_addr_t f; +} scratch_addr_u; + + +/* + * CP_ME_VS_EVENT_SRC struct + */ + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_VS_EVENT_SRC_MASK \ + (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \ + CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) + +#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \ + ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \ + (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_vs_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int : 30; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + } cp_me_vs_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_src_t f; +} cp_me_vs_event_src_u; + + +/* + * CP_ME_VS_EVENT_ADDR struct + */ + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_MASK \ + (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \ + CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) + +#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \ + ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \ + (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + } cp_me_vs_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + } cp_me_vs_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_t f; +} cp_me_vs_event_addr_u; + + +/* + * CP_ME_VS_EVENT_DATA struct + */ + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_MASK \ + (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) + +#define CP_ME_VS_EVENT_DATA(vs_done_data) \ + ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \ + ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \ + cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_t f; +} cp_me_vs_event_data_u; + + +/* + * CP_ME_VS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_SWM_MASK \ + (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \ + CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) + +#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \ + ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \ + (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_swm_t f; +} cp_me_vs_event_addr_swm_u; + + +/* + * CP_ME_VS_EVENT_DATA_SWM struct + */ + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_SWM_MASK \ + (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) + +#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \ + ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \ + ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \ + cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_swm_t f; +} cp_me_vs_event_data_swm_u; + + +/* + * CP_ME_PS_EVENT_SRC struct + */ + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_PS_EVENT_SRC_MASK \ + (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \ + CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) + +#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \ + ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \ + (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)) + +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_ps_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int : 30; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + } cp_me_ps_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_src_t f; +} cp_me_ps_event_src_u; + + +/* + * CP_ME_PS_EVENT_ADDR struct + */ + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_MASK \ + (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \ + CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) + +#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \ + ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \ + (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + } cp_me_ps_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + } cp_me_ps_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_t f; +} cp_me_ps_event_addr_u; + + +/* + * CP_ME_PS_EVENT_DATA struct + */ + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_MASK \ + (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) + +#define CP_ME_PS_EVENT_DATA(ps_done_data) \ + ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \ + ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \ + cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_t f; +} cp_me_ps_event_data_u; + + +/* + * CP_ME_PS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_SWM_MASK \ + (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \ + CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) + +#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \ + ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \ + (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_swm_t f; +} cp_me_ps_event_addr_swm_u; + + +/* + * CP_ME_PS_EVENT_DATA_SWM struct + */ + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_SWM_MASK \ + (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) + +#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \ + ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \ + ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \ + cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_swm_t f; +} cp_me_ps_event_data_swm_u; + + +/* + * CP_ME_CF_EVENT_SRC struct + */ + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001 + +#define CP_ME_CF_EVENT_SRC_MASK \ + (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) + +#define CP_ME_CF_EVENT_SRC(cf_done_src) \ + ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)) + +#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \ + ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \ + cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + unsigned int : 31; + } cp_me_cf_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int : 31; + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + } cp_me_cf_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_src_t f; +} cp_me_cf_event_src_u; + + +/* + * CP_ME_CF_EVENT_ADDR struct + */ + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_CF_EVENT_ADDR_MASK \ + (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \ + CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) + +#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \ + ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \ + (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)) + +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + } cp_me_cf_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + } cp_me_cf_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_addr_t f; +} cp_me_cf_event_addr_u; + + +/* + * CP_ME_CF_EVENT_DATA struct + */ + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff + +#define CP_ME_CF_EVENT_DATA_MASK \ + (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) + +#define CP_ME_CF_EVENT_DATA(cf_done_data) \ + ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)) + +#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \ + ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \ + cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_data_t f; +} cp_me_cf_event_data_u; + + +/* + * CP_ME_NRT_ADDR struct + */ + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc + +#define CP_ME_NRT_ADDR_MASK \ + (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \ + CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) + +#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \ + ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \ + (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)) + +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + } cp_me_nrt_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + } cp_me_nrt_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_addr_t f; +} cp_me_nrt_addr_u; + + +/* + * CP_ME_NRT_DATA struct + */ + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff + +#define CP_ME_NRT_DATA_MASK \ + (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) + +#define CP_ME_NRT_DATA(nrt_write_data) \ + ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)) + +#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \ + ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \ + cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_data_t f; +} cp_me_nrt_data_u; + + +/* + * CP_ME_VS_FETCH_DONE_SRC struct + */ + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001 + +#define CP_ME_VS_FETCH_DONE_SRC_MASK \ + (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) + +#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \ + ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \ + ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \ + cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + unsigned int : 31; + } cp_me_vs_fetch_done_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int : 31; + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + } cp_me_vs_fetch_done_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_src_t f; +} cp_me_vs_fetch_done_src_u; + + +/* + * CP_ME_VS_FETCH_DONE_ADDR struct + */ + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_FETCH_DONE_ADDR_MASK \ + (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \ + CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) + +#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \ + ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \ + (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_addr_t f; +} cp_me_vs_fetch_done_addr_u; + + +/* + * CP_ME_VS_FETCH_DONE_DATA struct + */ + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_FETCH_DONE_DATA_MASK \ + (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) + +#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \ + ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \ + ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \ + cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_data_t f; +} cp_me_vs_fetch_done_data_u; + + +/* + * CP_INT_CNTL struct + */ + +#define CP_INT_CNTL_SW_INT_MASK_SIZE 1 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB2_INT_MASK_SIZE 1 +#define CP_INT_CNTL_IB1_INT_MASK_SIZE 1 +#define CP_INT_CNTL_RB_INT_MASK_SIZE 1 + +#define CP_INT_CNTL_SW_INT_MASK_SHIFT 19 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26 +#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27 +#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29 +#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30 +#define CP_INT_CNTL_RB_INT_MASK_SHIFT 31 + +#define CP_INT_CNTL_SW_INT_MASK_MASK 0x00080000 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000 +#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000 +#define CP_INT_CNTL_IB2_INT_MASK_MASK 0x20000000 +#define CP_INT_CNTL_IB1_INT_MASK_MASK 0x40000000 +#define CP_INT_CNTL_RB_INT_MASK_MASK 0x80000000 + +#define CP_INT_CNTL_MASK \ + (CP_INT_CNTL_SW_INT_MASK_MASK | \ + CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \ + CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB2_INT_MASK_MASK | \ + CP_INT_CNTL_IB1_INT_MASK_MASK | \ + CP_INT_CNTL_RB_INT_MASK_MASK) + +#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \ + ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \ + (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \ + (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \ + (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \ + (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \ + (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \ + (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \ + (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \ + (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)) + +#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int : 19; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int : 1; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + } cp_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int : 1; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int : 3; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 19; + } cp_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_cntl_t f; +} cp_int_cntl_u; + + +/* + * CP_INT_STATUS struct + */ + +#define CP_INT_STATUS_SW_INT_STAT_SIZE 1 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1 +#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1 +#define CP_INT_STATUS_RB_INT_STAT_SIZE 1 + +#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26 +#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27 +#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29 +#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30 +#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31 + +#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000 +#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000 +#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000 + +#define CP_INT_STATUS_MASK \ + (CP_INT_STATUS_SW_INT_STAT_MASK | \ + CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \ + CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB2_INT_STAT_MASK | \ + CP_INT_STATUS_IB1_INT_STAT_MASK | \ + CP_INT_STATUS_RB_INT_STAT_MASK) + +#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \ + ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \ + (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \ + (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \ + (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \ + (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \ + (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \ + (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \ + (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \ + (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)) + +#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int : 19; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int : 1; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + } cp_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int : 1; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int : 3; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 19; + } cp_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_status_t f; +} cp_int_status_u; + + +/* + * CP_INT_ACK struct + */ + +#define CP_INT_ACK_SW_INT_ACK_SIZE 1 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB2_INT_ACK_SIZE 1 +#define CP_INT_ACK_IB1_INT_ACK_SIZE 1 +#define CP_INT_ACK_RB_INT_ACK_SIZE 1 + +#define CP_INT_ACK_SW_INT_ACK_SHIFT 19 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26 +#define CP_INT_ACK_IB_ERROR_ACK_SHIFT 27 +#define CP_INT_ACK_IB2_INT_ACK_SHIFT 29 +#define CP_INT_ACK_IB1_INT_ACK_SHIFT 30 +#define CP_INT_ACK_RB_INT_ACK_SHIFT 31 + +#define CP_INT_ACK_SW_INT_ACK_MASK 0x00080000 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000 +#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000 +#define CP_INT_ACK_IB_ERROR_ACK_MASK 0x08000000 +#define CP_INT_ACK_IB2_INT_ACK_MASK 0x20000000 +#define CP_INT_ACK_IB1_INT_ACK_MASK 0x40000000 +#define CP_INT_ACK_RB_INT_ACK_MASK 0x80000000 + +#define CP_INT_ACK_MASK \ + (CP_INT_ACK_SW_INT_ACK_MASK | \ + CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \ + CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \ + CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \ + CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \ + CP_INT_ACK_IB_ERROR_ACK_MASK | \ + CP_INT_ACK_IB2_INT_ACK_MASK | \ + CP_INT_ACK_IB1_INT_ACK_MASK | \ + CP_INT_ACK_RB_INT_ACK_MASK) + +#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \ + ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \ + (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \ + (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \ + (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \ + (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \ + (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \ + (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \ + (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \ + (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)) + +#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT) + +#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int : 19; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int : 1; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + } cp_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int : 1; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int : 3; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 19; + } cp_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_ack_t f; +} cp_int_ack_u; + + +/* + * CP_PFP_UCODE_ADDR struct + */ + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff + +#define CP_PFP_UCODE_ADDR_MASK \ + (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) + +#define CP_PFP_UCODE_ADDR(ucode_addr) \ + ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)) + +#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \ + ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \ + cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + unsigned int : 23; + } cp_pfp_ucode_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int : 23; + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + } cp_pfp_ucode_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_addr_t f; +} cp_pfp_ucode_addr_u; + + +/* + * CP_PFP_UCODE_DATA struct + */ + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff + +#define CP_PFP_UCODE_DATA_MASK \ + (CP_PFP_UCODE_DATA_UCODE_DATA_MASK) + +#define CP_PFP_UCODE_DATA(ucode_data) \ + ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)) + +#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \ + ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \ + cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + unsigned int : 8; + } cp_pfp_ucode_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int : 8; + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + } cp_pfp_ucode_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_data_t f; +} cp_pfp_ucode_data_u; + + +/* + * CP_PERFMON_CNTL struct + */ + +#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2 + +#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8 + +#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300 + +#define CP_PERFMON_CNTL_MASK \ + (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \ + CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) + +#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \ + ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \ + (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)) + +#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + unsigned int : 4; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 22; + } cp_perfmon_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int : 22; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 4; + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + } cp_perfmon_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfmon_cntl_t f; +} cp_perfmon_cntl_u; + + +/* + * CP_PERFCOUNTER_SELECT struct + */ + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f + +#define CP_PERFCOUNTER_SELECT_MASK \ + (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) + +#define CP_PERFCOUNTER_SELECT(perfcount_sel) \ + ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)) + +#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \ + ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \ + cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + unsigned int : 26; + } cp_perfcounter_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int : 26; + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + } cp_perfcounter_select_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_select_t f; +} cp_perfcounter_select_u; + + +/* + * CP_PERFCOUNTER_LO struct + */ + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff + +#define CP_PERFCOUNTER_LO_MASK \ + (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) + +#define CP_PERFCOUNTER_LO(perfcount_lo) \ + ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)) + +#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \ + ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \ + cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_lo_t f; +} cp_perfcounter_lo_u; + + +/* + * CP_PERFCOUNTER_HI struct + */ + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff + +#define CP_PERFCOUNTER_HI_MASK \ + (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) + +#define CP_PERFCOUNTER_HI(perfcount_hi) \ + ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)) + +#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \ + ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \ + cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + unsigned int : 16; + } cp_perfcounter_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int : 16; + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + } cp_perfcounter_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_hi_t f; +} cp_perfcounter_hi_u; + + +/* + * CP_BIN_MASK_LO struct + */ + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff + +#define CP_BIN_MASK_LO_MASK \ + (CP_BIN_MASK_LO_BIN_MASK_LO_MASK) + +#define CP_BIN_MASK_LO(bin_mask_lo) \ + ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)) + +#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \ + ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \ + cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_lo_t f; +} cp_bin_mask_lo_u; + + +/* + * CP_BIN_MASK_HI struct + */ + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff + +#define CP_BIN_MASK_HI_MASK \ + (CP_BIN_MASK_HI_BIN_MASK_HI_MASK) + +#define CP_BIN_MASK_HI(bin_mask_hi) \ + ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)) + +#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \ + ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \ + cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_hi_t f; +} cp_bin_mask_hi_u; + + +/* + * CP_BIN_SELECT_LO struct + */ + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff + +#define CP_BIN_SELECT_LO_MASK \ + (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) + +#define CP_BIN_SELECT_LO(bin_select_lo) \ + ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)) + +#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \ + ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \ + cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_lo_t f; +} cp_bin_select_lo_u; + + +/* + * CP_BIN_SELECT_HI struct + */ + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff + +#define CP_BIN_SELECT_HI_MASK \ + (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) + +#define CP_BIN_SELECT_HI(bin_select_hi) \ + ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)) + +#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \ + ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \ + cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_hi_t f; +} cp_bin_select_hi_u; + + +/* + * CP_NV_FLAGS_0 struct + */ + +#define CP_NV_FLAGS_0_DISCARD_0_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_0_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_1_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_1_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_2_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_2_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_3_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_3_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_4_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_4_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_5_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_5_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_6_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_6_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_7_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_7_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_8_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_8_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_9_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_9_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_10_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_11_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_12_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_13_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_14_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_15_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1 + +#define CP_NV_FLAGS_0_DISCARD_0_SHIFT 0 +#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1 +#define CP_NV_FLAGS_0_DISCARD_1_SHIFT 2 +#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3 +#define CP_NV_FLAGS_0_DISCARD_2_SHIFT 4 +#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5 +#define CP_NV_FLAGS_0_DISCARD_3_SHIFT 6 +#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7 +#define CP_NV_FLAGS_0_DISCARD_4_SHIFT 8 +#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9 +#define CP_NV_FLAGS_0_DISCARD_5_SHIFT 10 +#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11 +#define CP_NV_FLAGS_0_DISCARD_6_SHIFT 12 +#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13 +#define CP_NV_FLAGS_0_DISCARD_7_SHIFT 14 +#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15 +#define CP_NV_FLAGS_0_DISCARD_8_SHIFT 16 +#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17 +#define CP_NV_FLAGS_0_DISCARD_9_SHIFT 18 +#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19 +#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20 +#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21 +#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22 +#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23 +#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24 +#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25 +#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26 +#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27 +#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28 +#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29 +#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30 +#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31 + +#define CP_NV_FLAGS_0_DISCARD_0_MASK 0x00000001 +#define CP_NV_FLAGS_0_END_RCVD_0_MASK 0x00000002 +#define CP_NV_FLAGS_0_DISCARD_1_MASK 0x00000004 +#define CP_NV_FLAGS_0_END_RCVD_1_MASK 0x00000008 +#define CP_NV_FLAGS_0_DISCARD_2_MASK 0x00000010 +#define CP_NV_FLAGS_0_END_RCVD_2_MASK 0x00000020 +#define CP_NV_FLAGS_0_DISCARD_3_MASK 0x00000040 +#define CP_NV_FLAGS_0_END_RCVD_3_MASK 0x00000080 +#define CP_NV_FLAGS_0_DISCARD_4_MASK 0x00000100 +#define CP_NV_FLAGS_0_END_RCVD_4_MASK 0x00000200 +#define CP_NV_FLAGS_0_DISCARD_5_MASK 0x00000400 +#define CP_NV_FLAGS_0_END_RCVD_5_MASK 0x00000800 +#define CP_NV_FLAGS_0_DISCARD_6_MASK 0x00001000 +#define CP_NV_FLAGS_0_END_RCVD_6_MASK 0x00002000 +#define CP_NV_FLAGS_0_DISCARD_7_MASK 0x00004000 +#define CP_NV_FLAGS_0_END_RCVD_7_MASK 0x00008000 +#define CP_NV_FLAGS_0_DISCARD_8_MASK 0x00010000 +#define CP_NV_FLAGS_0_END_RCVD_8_MASK 0x00020000 +#define CP_NV_FLAGS_0_DISCARD_9_MASK 0x00040000 +#define CP_NV_FLAGS_0_END_RCVD_9_MASK 0x00080000 +#define CP_NV_FLAGS_0_DISCARD_10_MASK 0x00100000 +#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000 +#define CP_NV_FLAGS_0_DISCARD_11_MASK 0x00400000 +#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000 +#define CP_NV_FLAGS_0_DISCARD_12_MASK 0x01000000 +#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000 +#define CP_NV_FLAGS_0_DISCARD_13_MASK 0x04000000 +#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000 +#define CP_NV_FLAGS_0_DISCARD_14_MASK 0x10000000 +#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000 +#define CP_NV_FLAGS_0_DISCARD_15_MASK 0x40000000 +#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000 + +#define CP_NV_FLAGS_0_MASK \ + (CP_NV_FLAGS_0_DISCARD_0_MASK | \ + CP_NV_FLAGS_0_END_RCVD_0_MASK | \ + CP_NV_FLAGS_0_DISCARD_1_MASK | \ + CP_NV_FLAGS_0_END_RCVD_1_MASK | \ + CP_NV_FLAGS_0_DISCARD_2_MASK | \ + CP_NV_FLAGS_0_END_RCVD_2_MASK | \ + CP_NV_FLAGS_0_DISCARD_3_MASK | \ + CP_NV_FLAGS_0_END_RCVD_3_MASK | \ + CP_NV_FLAGS_0_DISCARD_4_MASK | \ + CP_NV_FLAGS_0_END_RCVD_4_MASK | \ + CP_NV_FLAGS_0_DISCARD_5_MASK | \ + CP_NV_FLAGS_0_END_RCVD_5_MASK | \ + CP_NV_FLAGS_0_DISCARD_6_MASK | \ + CP_NV_FLAGS_0_END_RCVD_6_MASK | \ + CP_NV_FLAGS_0_DISCARD_7_MASK | \ + CP_NV_FLAGS_0_END_RCVD_7_MASK | \ + CP_NV_FLAGS_0_DISCARD_8_MASK | \ + CP_NV_FLAGS_0_END_RCVD_8_MASK | \ + CP_NV_FLAGS_0_DISCARD_9_MASK | \ + CP_NV_FLAGS_0_END_RCVD_9_MASK | \ + CP_NV_FLAGS_0_DISCARD_10_MASK | \ + CP_NV_FLAGS_0_END_RCVD_10_MASK | \ + CP_NV_FLAGS_0_DISCARD_11_MASK | \ + CP_NV_FLAGS_0_END_RCVD_11_MASK | \ + CP_NV_FLAGS_0_DISCARD_12_MASK | \ + CP_NV_FLAGS_0_END_RCVD_12_MASK | \ + CP_NV_FLAGS_0_DISCARD_13_MASK | \ + CP_NV_FLAGS_0_END_RCVD_13_MASK | \ + CP_NV_FLAGS_0_DISCARD_14_MASK | \ + CP_NV_FLAGS_0_END_RCVD_14_MASK | \ + CP_NV_FLAGS_0_DISCARD_15_MASK | \ + CP_NV_FLAGS_0_END_RCVD_15_MASK) + +#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \ + ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \ + (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \ + (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \ + (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \ + (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \ + (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \ + (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \ + (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \ + (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \ + (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \ + (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \ + (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \ + (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \ + (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \ + (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \ + (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \ + (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \ + (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \ + (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \ + (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \ + (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \ + (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \ + (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \ + (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \ + (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \ + (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \ + (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \ + (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \ + (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \ + (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \ + (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \ + (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)) + +#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + } cp_nv_flags_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + } cp_nv_flags_0_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_0_t f; +} cp_nv_flags_0_u; + + +/* + * CP_NV_FLAGS_1 struct + */ + +#define CP_NV_FLAGS_1_DISCARD_16_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_17_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_18_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_19_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_20_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_21_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_22_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_23_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_24_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_25_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_26_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_27_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_28_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_29_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_30_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_31_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1 + +#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0 +#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1 +#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2 +#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3 +#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4 +#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5 +#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6 +#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7 +#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8 +#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9 +#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10 +#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11 +#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12 +#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13 +#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14 +#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15 +#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16 +#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17 +#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18 +#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19 +#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20 +#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21 +#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22 +#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23 +#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24 +#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25 +#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26 +#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27 +#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28 +#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29 +#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30 +#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31 + +#define CP_NV_FLAGS_1_DISCARD_16_MASK 0x00000001 +#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002 +#define CP_NV_FLAGS_1_DISCARD_17_MASK 0x00000004 +#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008 +#define CP_NV_FLAGS_1_DISCARD_18_MASK 0x00000010 +#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020 +#define CP_NV_FLAGS_1_DISCARD_19_MASK 0x00000040 +#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080 +#define CP_NV_FLAGS_1_DISCARD_20_MASK 0x00000100 +#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200 +#define CP_NV_FLAGS_1_DISCARD_21_MASK 0x00000400 +#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800 +#define CP_NV_FLAGS_1_DISCARD_22_MASK 0x00001000 +#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000 +#define CP_NV_FLAGS_1_DISCARD_23_MASK 0x00004000 +#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000 +#define CP_NV_FLAGS_1_DISCARD_24_MASK 0x00010000 +#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000 +#define CP_NV_FLAGS_1_DISCARD_25_MASK 0x00040000 +#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000 +#define CP_NV_FLAGS_1_DISCARD_26_MASK 0x00100000 +#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000 +#define CP_NV_FLAGS_1_DISCARD_27_MASK 0x00400000 +#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000 +#define CP_NV_FLAGS_1_DISCARD_28_MASK 0x01000000 +#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000 +#define CP_NV_FLAGS_1_DISCARD_29_MASK 0x04000000 +#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000 +#define CP_NV_FLAGS_1_DISCARD_30_MASK 0x10000000 +#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000 +#define CP_NV_FLAGS_1_DISCARD_31_MASK 0x40000000 +#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000 + +#define CP_NV_FLAGS_1_MASK \ + (CP_NV_FLAGS_1_DISCARD_16_MASK | \ + CP_NV_FLAGS_1_END_RCVD_16_MASK | \ + CP_NV_FLAGS_1_DISCARD_17_MASK | \ + CP_NV_FLAGS_1_END_RCVD_17_MASK | \ + CP_NV_FLAGS_1_DISCARD_18_MASK | \ + CP_NV_FLAGS_1_END_RCVD_18_MASK | \ + CP_NV_FLAGS_1_DISCARD_19_MASK | \ + CP_NV_FLAGS_1_END_RCVD_19_MASK | \ + CP_NV_FLAGS_1_DISCARD_20_MASK | \ + CP_NV_FLAGS_1_END_RCVD_20_MASK | \ + CP_NV_FLAGS_1_DISCARD_21_MASK | \ + CP_NV_FLAGS_1_END_RCVD_21_MASK | \ + CP_NV_FLAGS_1_DISCARD_22_MASK | \ + CP_NV_FLAGS_1_END_RCVD_22_MASK | \ + CP_NV_FLAGS_1_DISCARD_23_MASK | \ + CP_NV_FLAGS_1_END_RCVD_23_MASK | \ + CP_NV_FLAGS_1_DISCARD_24_MASK | \ + CP_NV_FLAGS_1_END_RCVD_24_MASK | \ + CP_NV_FLAGS_1_DISCARD_25_MASK | \ + CP_NV_FLAGS_1_END_RCVD_25_MASK | \ + CP_NV_FLAGS_1_DISCARD_26_MASK | \ + CP_NV_FLAGS_1_END_RCVD_26_MASK | \ + CP_NV_FLAGS_1_DISCARD_27_MASK | \ + CP_NV_FLAGS_1_END_RCVD_27_MASK | \ + CP_NV_FLAGS_1_DISCARD_28_MASK | \ + CP_NV_FLAGS_1_END_RCVD_28_MASK | \ + CP_NV_FLAGS_1_DISCARD_29_MASK | \ + CP_NV_FLAGS_1_END_RCVD_29_MASK | \ + CP_NV_FLAGS_1_DISCARD_30_MASK | \ + CP_NV_FLAGS_1_END_RCVD_30_MASK | \ + CP_NV_FLAGS_1_DISCARD_31_MASK | \ + CP_NV_FLAGS_1_END_RCVD_31_MASK) + +#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \ + ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \ + (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \ + (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \ + (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \ + (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \ + (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \ + (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \ + (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \ + (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \ + (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \ + (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \ + (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \ + (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \ + (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \ + (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \ + (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \ + (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \ + (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \ + (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \ + (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \ + (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \ + (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \ + (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \ + (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \ + (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \ + (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \ + (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \ + (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \ + (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \ + (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \ + (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \ + (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)) + +#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + } cp_nv_flags_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + } cp_nv_flags_1_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_1_t f; +} cp_nv_flags_1_u; + + +/* + * CP_NV_FLAGS_2 struct + */ + +#define CP_NV_FLAGS_2_DISCARD_32_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_33_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_34_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_35_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_36_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_37_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_38_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_39_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_40_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_41_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_42_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_43_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_44_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_45_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_46_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_47_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1 + +#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0 +#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1 +#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2 +#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3 +#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4 +#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5 +#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6 +#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7 +#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8 +#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9 +#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10 +#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11 +#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12 +#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13 +#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14 +#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15 +#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16 +#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17 +#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18 +#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19 +#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20 +#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21 +#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22 +#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23 +#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24 +#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25 +#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26 +#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27 +#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28 +#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29 +#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30 +#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31 + +#define CP_NV_FLAGS_2_DISCARD_32_MASK 0x00000001 +#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002 +#define CP_NV_FLAGS_2_DISCARD_33_MASK 0x00000004 +#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008 +#define CP_NV_FLAGS_2_DISCARD_34_MASK 0x00000010 +#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020 +#define CP_NV_FLAGS_2_DISCARD_35_MASK 0x00000040 +#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080 +#define CP_NV_FLAGS_2_DISCARD_36_MASK 0x00000100 +#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200 +#define CP_NV_FLAGS_2_DISCARD_37_MASK 0x00000400 +#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800 +#define CP_NV_FLAGS_2_DISCARD_38_MASK 0x00001000 +#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000 +#define CP_NV_FLAGS_2_DISCARD_39_MASK 0x00004000 +#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000 +#define CP_NV_FLAGS_2_DISCARD_40_MASK 0x00010000 +#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000 +#define CP_NV_FLAGS_2_DISCARD_41_MASK 0x00040000 +#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000 +#define CP_NV_FLAGS_2_DISCARD_42_MASK 0x00100000 +#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000 +#define CP_NV_FLAGS_2_DISCARD_43_MASK 0x00400000 +#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000 +#define CP_NV_FLAGS_2_DISCARD_44_MASK 0x01000000 +#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000 +#define CP_NV_FLAGS_2_DISCARD_45_MASK 0x04000000 +#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000 +#define CP_NV_FLAGS_2_DISCARD_46_MASK 0x10000000 +#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000 +#define CP_NV_FLAGS_2_DISCARD_47_MASK 0x40000000 +#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000 + +#define CP_NV_FLAGS_2_MASK \ + (CP_NV_FLAGS_2_DISCARD_32_MASK | \ + CP_NV_FLAGS_2_END_RCVD_32_MASK | \ + CP_NV_FLAGS_2_DISCARD_33_MASK | \ + CP_NV_FLAGS_2_END_RCVD_33_MASK | \ + CP_NV_FLAGS_2_DISCARD_34_MASK | \ + CP_NV_FLAGS_2_END_RCVD_34_MASK | \ + CP_NV_FLAGS_2_DISCARD_35_MASK | \ + CP_NV_FLAGS_2_END_RCVD_35_MASK | \ + CP_NV_FLAGS_2_DISCARD_36_MASK | \ + CP_NV_FLAGS_2_END_RCVD_36_MASK | \ + CP_NV_FLAGS_2_DISCARD_37_MASK | \ + CP_NV_FLAGS_2_END_RCVD_37_MASK | \ + CP_NV_FLAGS_2_DISCARD_38_MASK | \ + CP_NV_FLAGS_2_END_RCVD_38_MASK | \ + CP_NV_FLAGS_2_DISCARD_39_MASK | \ + CP_NV_FLAGS_2_END_RCVD_39_MASK | \ + CP_NV_FLAGS_2_DISCARD_40_MASK | \ + CP_NV_FLAGS_2_END_RCVD_40_MASK | \ + CP_NV_FLAGS_2_DISCARD_41_MASK | \ + CP_NV_FLAGS_2_END_RCVD_41_MASK | \ + CP_NV_FLAGS_2_DISCARD_42_MASK | \ + CP_NV_FLAGS_2_END_RCVD_42_MASK | \ + CP_NV_FLAGS_2_DISCARD_43_MASK | \ + CP_NV_FLAGS_2_END_RCVD_43_MASK | \ + CP_NV_FLAGS_2_DISCARD_44_MASK | \ + CP_NV_FLAGS_2_END_RCVD_44_MASK | \ + CP_NV_FLAGS_2_DISCARD_45_MASK | \ + CP_NV_FLAGS_2_END_RCVD_45_MASK | \ + CP_NV_FLAGS_2_DISCARD_46_MASK | \ + CP_NV_FLAGS_2_END_RCVD_46_MASK | \ + CP_NV_FLAGS_2_DISCARD_47_MASK | \ + CP_NV_FLAGS_2_END_RCVD_47_MASK) + +#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \ + ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \ + (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \ + (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \ + (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \ + (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \ + (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \ + (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \ + (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \ + (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \ + (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \ + (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \ + (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \ + (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \ + (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \ + (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \ + (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \ + (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \ + (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \ + (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \ + (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \ + (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \ + (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \ + (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \ + (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \ + (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \ + (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \ + (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \ + (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \ + (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \ + (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \ + (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \ + (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)) + +#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + } cp_nv_flags_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + } cp_nv_flags_2_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_2_t f; +} cp_nv_flags_2_u; + + +/* + * CP_NV_FLAGS_3 struct + */ + +#define CP_NV_FLAGS_3_DISCARD_48_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_49_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_50_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_51_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_52_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_53_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_54_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_55_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_56_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_57_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_58_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_59_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_60_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_61_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_62_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_63_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1 + +#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0 +#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1 +#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2 +#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3 +#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4 +#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5 +#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6 +#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7 +#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8 +#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9 +#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10 +#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11 +#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12 +#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13 +#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14 +#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15 +#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16 +#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17 +#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18 +#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19 +#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20 +#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21 +#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22 +#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23 +#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24 +#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25 +#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26 +#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27 +#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28 +#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29 +#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30 +#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31 + +#define CP_NV_FLAGS_3_DISCARD_48_MASK 0x00000001 +#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002 +#define CP_NV_FLAGS_3_DISCARD_49_MASK 0x00000004 +#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008 +#define CP_NV_FLAGS_3_DISCARD_50_MASK 0x00000010 +#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020 +#define CP_NV_FLAGS_3_DISCARD_51_MASK 0x00000040 +#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080 +#define CP_NV_FLAGS_3_DISCARD_52_MASK 0x00000100 +#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200 +#define CP_NV_FLAGS_3_DISCARD_53_MASK 0x00000400 +#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800 +#define CP_NV_FLAGS_3_DISCARD_54_MASK 0x00001000 +#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000 +#define CP_NV_FLAGS_3_DISCARD_55_MASK 0x00004000 +#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000 +#define CP_NV_FLAGS_3_DISCARD_56_MASK 0x00010000 +#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000 +#define CP_NV_FLAGS_3_DISCARD_57_MASK 0x00040000 +#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000 +#define CP_NV_FLAGS_3_DISCARD_58_MASK 0x00100000 +#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000 +#define CP_NV_FLAGS_3_DISCARD_59_MASK 0x00400000 +#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000 +#define CP_NV_FLAGS_3_DISCARD_60_MASK 0x01000000 +#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000 +#define CP_NV_FLAGS_3_DISCARD_61_MASK 0x04000000 +#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000 +#define CP_NV_FLAGS_3_DISCARD_62_MASK 0x10000000 +#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000 +#define CP_NV_FLAGS_3_DISCARD_63_MASK 0x40000000 +#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000 + +#define CP_NV_FLAGS_3_MASK \ + (CP_NV_FLAGS_3_DISCARD_48_MASK | \ + CP_NV_FLAGS_3_END_RCVD_48_MASK | \ + CP_NV_FLAGS_3_DISCARD_49_MASK | \ + CP_NV_FLAGS_3_END_RCVD_49_MASK | \ + CP_NV_FLAGS_3_DISCARD_50_MASK | \ + CP_NV_FLAGS_3_END_RCVD_50_MASK | \ + CP_NV_FLAGS_3_DISCARD_51_MASK | \ + CP_NV_FLAGS_3_END_RCVD_51_MASK | \ + CP_NV_FLAGS_3_DISCARD_52_MASK | \ + CP_NV_FLAGS_3_END_RCVD_52_MASK | \ + CP_NV_FLAGS_3_DISCARD_53_MASK | \ + CP_NV_FLAGS_3_END_RCVD_53_MASK | \ + CP_NV_FLAGS_3_DISCARD_54_MASK | \ + CP_NV_FLAGS_3_END_RCVD_54_MASK | \ + CP_NV_FLAGS_3_DISCARD_55_MASK | \ + CP_NV_FLAGS_3_END_RCVD_55_MASK | \ + CP_NV_FLAGS_3_DISCARD_56_MASK | \ + CP_NV_FLAGS_3_END_RCVD_56_MASK | \ + CP_NV_FLAGS_3_DISCARD_57_MASK | \ + CP_NV_FLAGS_3_END_RCVD_57_MASK | \ + CP_NV_FLAGS_3_DISCARD_58_MASK | \ + CP_NV_FLAGS_3_END_RCVD_58_MASK | \ + CP_NV_FLAGS_3_DISCARD_59_MASK | \ + CP_NV_FLAGS_3_END_RCVD_59_MASK | \ + CP_NV_FLAGS_3_DISCARD_60_MASK | \ + CP_NV_FLAGS_3_END_RCVD_60_MASK | \ + CP_NV_FLAGS_3_DISCARD_61_MASK | \ + CP_NV_FLAGS_3_END_RCVD_61_MASK | \ + CP_NV_FLAGS_3_DISCARD_62_MASK | \ + CP_NV_FLAGS_3_END_RCVD_62_MASK | \ + CP_NV_FLAGS_3_DISCARD_63_MASK | \ + CP_NV_FLAGS_3_END_RCVD_63_MASK) + +#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \ + ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \ + (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \ + (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \ + (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \ + (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \ + (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \ + (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \ + (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \ + (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \ + (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \ + (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \ + (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \ + (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \ + (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \ + (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \ + (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \ + (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \ + (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \ + (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \ + (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \ + (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \ + (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \ + (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \ + (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \ + (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \ + (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \ + (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \ + (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \ + (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \ + (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \ + (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \ + (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)) + +#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + } cp_nv_flags_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + } cp_nv_flags_3_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_3_t f; +} cp_nv_flags_3_u; + + +/* + * CP_STATE_DEBUG_INDEX struct + */ + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f + +#define CP_STATE_DEBUG_INDEX_MASK \ + (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) + +#define CP_STATE_DEBUG_INDEX(state_debug_index) \ + ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)) + +#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \ + ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \ + cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + unsigned int : 27; + } cp_state_debug_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int : 27; + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + } cp_state_debug_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_index_t f; +} cp_state_debug_index_u; + + +/* + * CP_STATE_DEBUG_DATA struct + */ + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff + +#define CP_STATE_DEBUG_DATA_MASK \ + (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) + +#define CP_STATE_DEBUG_DATA(state_debug_data) \ + ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)) + +#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \ + ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \ + cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_data_t f; +} cp_state_debug_data_u; + + +/* + * CP_PROG_COUNTER struct + */ + +#define CP_PROG_COUNTER_COUNTER_SIZE 32 + +#define CP_PROG_COUNTER_COUNTER_SHIFT 0 + +#define CP_PROG_COUNTER_COUNTER_MASK 0xffffffff + +#define CP_PROG_COUNTER_MASK \ + (CP_PROG_COUNTER_COUNTER_MASK) + +#define CP_PROG_COUNTER(counter) \ + ((counter << CP_PROG_COUNTER_COUNTER_SHIFT)) + +#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \ + ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT) + +#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \ + cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_prog_counter_t f; +} cp_prog_counter_u; + + +/* + * CP_STAT struct + */ + +#define CP_STAT_MIU_WR_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_REQ_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1 +#define CP_STAT_RBIU_BUSY_SIZE 1 +#define CP_STAT_RCIU_BUSY_SIZE 1 +#define CP_STAT_CSF_RING_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_CSF_ST_BUSY_SIZE 1 +#define CP_STAT_CSF_BUSY_SIZE 1 +#define CP_STAT_RING_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1 +#define CP_STAT_ST_QUEUE_BUSY_SIZE 1 +#define CP_STAT_PFP_BUSY_SIZE 1 +#define CP_STAT_MEQ_RING_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_STALL_SIZE 1 +#define CP_STAT_CP_NRT_BUSY_SIZE 1 +#define CP_STAT__3D_BUSY_SIZE 1 +#define CP_STAT_ME_BUSY_SIZE 1 +#define CP_STAT_ME_WC_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1 +#define CP_STAT_CP_BUSY_SIZE 1 + +#define CP_STAT_MIU_WR_BUSY_SHIFT 0 +#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2 +#define CP_STAT_RBIU_BUSY_SHIFT 3 +#define CP_STAT_RCIU_BUSY_SHIFT 4 +#define CP_STAT_CSF_RING_BUSY_SHIFT 5 +#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6 +#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7 +#define CP_STAT_CSF_ST_BUSY_SHIFT 9 +#define CP_STAT_CSF_BUSY_SHIFT 10 +#define CP_STAT_RING_QUEUE_BUSY_SHIFT 11 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13 +#define CP_STAT_ST_QUEUE_BUSY_SHIFT 16 +#define CP_STAT_PFP_BUSY_SHIFT 17 +#define CP_STAT_MEQ_RING_BUSY_SHIFT 18 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20 +#define CP_STAT_MIU_WC_STALL_SHIFT 21 +#define CP_STAT_CP_NRT_BUSY_SHIFT 22 +#define CP_STAT__3D_BUSY_SHIFT 23 +#define CP_STAT_ME_BUSY_SHIFT 26 +#define CP_STAT_ME_WC_BUSY_SHIFT 29 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30 +#define CP_STAT_CP_BUSY_SHIFT 31 + +#define CP_STAT_MIU_WR_BUSY_MASK 0x00000001 +#define CP_STAT_MIU_RD_REQ_BUSY_MASK 0x00000002 +#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004 +#define CP_STAT_RBIU_BUSY_MASK 0x00000008 +#define CP_STAT_RCIU_BUSY_MASK 0x00000010 +#define CP_STAT_CSF_RING_BUSY_MASK 0x00000020 +#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040 +#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080 +#define CP_STAT_CSF_ST_BUSY_MASK 0x00000200 +#define CP_STAT_CSF_BUSY_MASK 0x00000400 +#define CP_STAT_RING_QUEUE_BUSY_MASK 0x00000800 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000 +#define CP_STAT_ST_QUEUE_BUSY_MASK 0x00010000 +#define CP_STAT_PFP_BUSY_MASK 0x00020000 +#define CP_STAT_MEQ_RING_BUSY_MASK 0x00040000 +#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000 +#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000 +#define CP_STAT_MIU_WC_STALL_MASK 0x00200000 +#define CP_STAT_CP_NRT_BUSY_MASK 0x00400000 +#define CP_STAT__3D_BUSY_MASK 0x00800000 +#define CP_STAT_ME_BUSY_MASK 0x04000000 +#define CP_STAT_ME_WC_BUSY_MASK 0x20000000 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000 +#define CP_STAT_CP_BUSY_MASK 0x80000000 + +#define CP_STAT_MASK \ + (CP_STAT_MIU_WR_BUSY_MASK | \ + CP_STAT_MIU_RD_REQ_BUSY_MASK | \ + CP_STAT_MIU_RD_RETURN_BUSY_MASK | \ + CP_STAT_RBIU_BUSY_MASK | \ + CP_STAT_RCIU_BUSY_MASK | \ + CP_STAT_CSF_RING_BUSY_MASK | \ + CP_STAT_CSF_INDIRECTS_BUSY_MASK | \ + CP_STAT_CSF_INDIRECT2_BUSY_MASK | \ + CP_STAT_CSF_ST_BUSY_MASK | \ + CP_STAT_CSF_BUSY_MASK | \ + CP_STAT_RING_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \ + CP_STAT_ST_QUEUE_BUSY_MASK | \ + CP_STAT_PFP_BUSY_MASK | \ + CP_STAT_MEQ_RING_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \ + CP_STAT_MIU_WC_STALL_MASK | \ + CP_STAT_CP_NRT_BUSY_MASK | \ + CP_STAT__3D_BUSY_MASK | \ + CP_STAT_ME_BUSY_MASK | \ + CP_STAT_ME_WC_BUSY_MASK | \ + CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \ + CP_STAT_CP_BUSY_MASK) + +#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \ + ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \ + (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \ + (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \ + (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \ + (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \ + (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \ + (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \ + (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \ + (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \ + (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \ + (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \ + (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \ + (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \ + (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \ + (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \ + (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \ + (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \ + (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \ + (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \ + (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \ + (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \ + (me_busy << CP_STAT_ME_BUSY_SHIFT) | \ + (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \ + (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \ + (cp_busy << CP_STAT_CP_BUSY_SHIFT)) + +#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_GET_RBIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_GET_RCIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_GET_CSF_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_PFP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_GET__3D_BUSY(cp_stat) \ + ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_GET_ME_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_GET_CP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT) + +#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + } cp_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + } cp_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stat_t f; +} cp_stat_u; + + +/* + * BIOS_0_SCRATCH struct + */ + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_0_SCRATCH_MASK \ + (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_0_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \ + ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \ + bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_0_scratch_t f; +} bios_0_scratch_u; + + +/* + * BIOS_1_SCRATCH struct + */ + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_1_SCRATCH_MASK \ + (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_1_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \ + ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \ + bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_1_scratch_t f; +} bios_1_scratch_u; + + +/* + * BIOS_2_SCRATCH struct + */ + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_2_SCRATCH_MASK \ + (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_2_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \ + ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \ + bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_2_scratch_t f; +} bios_2_scratch_u; + + +/* + * BIOS_3_SCRATCH struct + */ + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_3_SCRATCH_MASK \ + (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_3_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \ + ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \ + bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_3_scratch_t f; +} bios_3_scratch_u; + + +/* + * BIOS_4_SCRATCH struct + */ + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_4_SCRATCH_MASK \ + (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_4_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \ + ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \ + bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_4_scratch_t f; +} bios_4_scratch_u; + + +/* + * BIOS_5_SCRATCH struct + */ + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_5_SCRATCH_MASK \ + (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_5_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \ + ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \ + bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_5_scratch_t f; +} bios_5_scratch_u; + + +/* + * BIOS_6_SCRATCH struct + */ + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_6_SCRATCH_MASK \ + (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_6_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \ + ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \ + bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_6_scratch_t f; +} bios_6_scratch_u; + + +/* + * BIOS_7_SCRATCH struct + */ + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_7_SCRATCH_MASK \ + (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_7_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \ + ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \ + bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_7_scratch_t f; +} bios_7_scratch_u; + + +/* + * BIOS_8_SCRATCH struct + */ + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_8_SCRATCH_MASK \ + (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_8_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \ + ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \ + bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_8_scratch_t f; +} bios_8_scratch_u; + + +/* + * BIOS_9_SCRATCH struct + */ + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_9_SCRATCH_MASK \ + (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_9_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \ + ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \ + bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_9_scratch_t f; +} bios_9_scratch_u; + + +/* + * BIOS_10_SCRATCH struct + */ + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_10_SCRATCH_MASK \ + (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_10_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \ + ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \ + bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_10_scratch_t f; +} bios_10_scratch_u; + + +/* + * BIOS_11_SCRATCH struct + */ + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_11_SCRATCH_MASK \ + (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_11_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \ + ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \ + bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_11_scratch_t f; +} bios_11_scratch_u; + + +/* + * BIOS_12_SCRATCH struct + */ + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_12_SCRATCH_MASK \ + (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_12_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \ + ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \ + bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_12_scratch_t f; +} bios_12_scratch_u; + + +/* + * BIOS_13_SCRATCH struct + */ + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_13_SCRATCH_MASK \ + (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_13_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \ + ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \ + bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_13_scratch_t f; +} bios_13_scratch_u; + + +/* + * BIOS_14_SCRATCH struct + */ + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_14_SCRATCH_MASK \ + (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_14_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \ + ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \ + bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_14_scratch_t f; +} bios_14_scratch_u; + + +/* + * BIOS_15_SCRATCH struct + */ + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_15_SCRATCH_MASK \ + (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_15_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \ + ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \ + bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_15_scratch_t f; +} bios_15_scratch_u; + + +/* + * COHER_SIZE_PM4 struct + */ + +#define COHER_SIZE_PM4_SIZE_SIZE 32 + +#define COHER_SIZE_PM4_SIZE_SHIFT 0 + +#define COHER_SIZE_PM4_SIZE_MASK 0xffffffff + +#define COHER_SIZE_PM4_MASK \ + (COHER_SIZE_PM4_SIZE_MASK) + +#define COHER_SIZE_PM4(size) \ + ((size << COHER_SIZE_PM4_SIZE_SHIFT)) + +#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \ + ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT) + +#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \ + coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_pm4_t f; +} coher_size_pm4_u; + + +/* + * COHER_BASE_PM4 struct + */ + +#define COHER_BASE_PM4_BASE_SIZE 32 + +#define COHER_BASE_PM4_BASE_SHIFT 0 + +#define COHER_BASE_PM4_BASE_MASK 0xffffffff + +#define COHER_BASE_PM4_MASK \ + (COHER_BASE_PM4_BASE_MASK) + +#define COHER_BASE_PM4(base) \ + ((base << COHER_BASE_PM4_BASE_SHIFT)) + +#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \ + ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT) + +#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \ + coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_pm4_t f; +} coher_base_pm4_u; + + +/* + * COHER_STATUS_PM4 struct + */ + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_PM4_STATUS_SIZE 1 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_PM4_STATUS_SHIFT 31 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_PM4_STATUS_MASK 0x80000000 + +#define COHER_STATUS_PM4_MASK \ + (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \ + COHER_STATUS_PM4_STATUS_MASK) + +#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_PM4_STATUS_SHIFT)) + +#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT) + +#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + } coher_status_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + } coher_status_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_pm4_t f; +} coher_status_pm4_u; + + +/* + * COHER_SIZE_HOST struct + */ + +#define COHER_SIZE_HOST_SIZE_SIZE 32 + +#define COHER_SIZE_HOST_SIZE_SHIFT 0 + +#define COHER_SIZE_HOST_SIZE_MASK 0xffffffff + +#define COHER_SIZE_HOST_MASK \ + (COHER_SIZE_HOST_SIZE_MASK) + +#define COHER_SIZE_HOST(size) \ + ((size << COHER_SIZE_HOST_SIZE_SHIFT)) + +#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \ + ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT) + +#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \ + coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_host_t f; +} coher_size_host_u; + + +/* + * COHER_BASE_HOST struct + */ + +#define COHER_BASE_HOST_BASE_SIZE 32 + +#define COHER_BASE_HOST_BASE_SHIFT 0 + +#define COHER_BASE_HOST_BASE_MASK 0xffffffff + +#define COHER_BASE_HOST_MASK \ + (COHER_BASE_HOST_BASE_MASK) + +#define COHER_BASE_HOST(base) \ + ((base << COHER_BASE_HOST_BASE_SHIFT)) + +#define COHER_BASE_HOST_GET_BASE(coher_base_host) \ + ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT) + +#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \ + coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_host_t f; +} coher_base_host_u; + + +/* + * COHER_STATUS_HOST struct + */ + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_HOST_STATUS_SIZE 1 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_HOST_STATUS_SHIFT 31 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_HOST_STATUS_MASK 0x80000000 + +#define COHER_STATUS_HOST_MASK \ + (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \ + COHER_STATUS_HOST_STATUS_MASK) + +#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_HOST_STATUS_SHIFT)) + +#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT) + +#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + } coher_status_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + } coher_status_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_host_t f; +} coher_status_host_u; + + +/* + * COHER_DEST_BASE_0 struct + */ + +#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20 + +#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12 + +#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000 + +#define COHER_DEST_BASE_0_MASK \ + (COHER_DEST_BASE_0_DEST_BASE_0_MASK) + +#define COHER_DEST_BASE_0(dest_base_0) \ + ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)) + +#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \ + ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \ + coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int : 12; + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + } coher_dest_base_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + unsigned int : 12; + } coher_dest_base_0_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_0_t f; +} coher_dest_base_0_u; + + +/* + * COHER_DEST_BASE_1 struct + */ + +#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20 + +#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12 + +#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000 + +#define COHER_DEST_BASE_1_MASK \ + (COHER_DEST_BASE_1_DEST_BASE_1_MASK) + +#define COHER_DEST_BASE_1(dest_base_1) \ + ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)) + +#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \ + ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \ + coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int : 12; + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + } coher_dest_base_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + unsigned int : 12; + } coher_dest_base_1_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_1_t f; +} coher_dest_base_1_u; + + +/* + * COHER_DEST_BASE_2 struct + */ + +#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20 + +#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12 + +#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000 + +#define COHER_DEST_BASE_2_MASK \ + (COHER_DEST_BASE_2_DEST_BASE_2_MASK) + +#define COHER_DEST_BASE_2(dest_base_2) \ + ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)) + +#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \ + ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \ + coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int : 12; + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + } coher_dest_base_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + unsigned int : 12; + } coher_dest_base_2_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_2_t f; +} coher_dest_base_2_u; + + +/* + * COHER_DEST_BASE_3 struct + */ + +#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20 + +#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12 + +#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000 + +#define COHER_DEST_BASE_3_MASK \ + (COHER_DEST_BASE_3_DEST_BASE_3_MASK) + +#define COHER_DEST_BASE_3(dest_base_3) \ + ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)) + +#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \ + ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \ + coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int : 12; + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + } coher_dest_base_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + unsigned int : 12; + } coher_dest_base_3_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_3_t f; +} coher_dest_base_3_u; + + +/* + * COHER_DEST_BASE_4 struct + */ + +#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20 + +#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12 + +#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000 + +#define COHER_DEST_BASE_4_MASK \ + (COHER_DEST_BASE_4_DEST_BASE_4_MASK) + +#define COHER_DEST_BASE_4(dest_base_4) \ + ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)) + +#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \ + ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \ + coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int : 12; + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + } coher_dest_base_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + unsigned int : 12; + } coher_dest_base_4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_4_t f; +} coher_dest_base_4_u; + + +/* + * COHER_DEST_BASE_5 struct + */ + +#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20 + +#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12 + +#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000 + +#define COHER_DEST_BASE_5_MASK \ + (COHER_DEST_BASE_5_DEST_BASE_5_MASK) + +#define COHER_DEST_BASE_5(dest_base_5) \ + ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)) + +#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \ + ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \ + coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int : 12; + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + } coher_dest_base_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + unsigned int : 12; + } coher_dest_base_5_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_5_t f; +} coher_dest_base_5_u; + + +/* + * COHER_DEST_BASE_6 struct + */ + +#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20 + +#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12 + +#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000 + +#define COHER_DEST_BASE_6_MASK \ + (COHER_DEST_BASE_6_DEST_BASE_6_MASK) + +#define COHER_DEST_BASE_6(dest_base_6) \ + ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)) + +#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \ + ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \ + coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int : 12; + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + } coher_dest_base_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + unsigned int : 12; + } coher_dest_base_6_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_6_t f; +} coher_dest_base_6_u; + + +/* + * COHER_DEST_BASE_7 struct + */ + +#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20 + +#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12 + +#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000 + +#define COHER_DEST_BASE_7_MASK \ + (COHER_DEST_BASE_7_DEST_BASE_7_MASK) + +#define COHER_DEST_BASE_7(dest_base_7) \ + ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)) + +#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \ + ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \ + coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int : 12; + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + } coher_dest_base_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + unsigned int : 12; + } coher_dest_base_7_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_7_t f; +} coher_dest_base_7_u; + + +#endif + + +#if !defined (_RBBM_FIDDLE_H) +#define _RBBM_FIDDLE_H + +/***************************************************************************************************************** + * + * rbbm_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * WAIT_UNTIL struct + */ + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1 +#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2 +#define WAIT_UNTIL_WAIT_VSYNC_SHIFT 3 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6 +#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT 10 +#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT 14 +#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT 15 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK 0x00000002 +#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK 0x00000004 +#define WAIT_UNTIL_WAIT_VSYNC_MASK 0x00000008 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040 +#define WAIT_UNTIL_WAIT_CMDFIFO_MASK 0x00000400 +#define WAIT_UNTIL_WAIT_2D_IDLE_MASK 0x00004000 +#define WAIT_UNTIL_WAIT_3D_IDLE_MASK 0x00008000 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000 + +#define WAIT_UNTIL_MASK \ + (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \ + WAIT_UNTIL_WAIT_CMDFIFO_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \ + WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) + +#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \ + ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \ + (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \ + (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \ + (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \ + (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \ + (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \ + (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \ + (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \ + (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \ + (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \ + (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \ + (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)) + +#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \ + ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 1; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int : 2; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 8; + } wait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 8; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 2; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int : 1; + } wait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + wait_until_t f; +} wait_until_u; + + +/* + * RBBM_ISYNC_CNTL struct + */ + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020 + +#define RBBM_ISYNC_CNTL_MASK \ + (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \ + RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) + +#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \ + ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \ + (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)) + +#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 4; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int : 26; + } rbbm_isync_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 26; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int : 4; + } rbbm_isync_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_isync_cntl_t f; +} rbbm_isync_cntl_u; + + +/* + * RBBM_STATUS struct + */ + +#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5 +#define RBBM_STATUS_TC_BUSY_SIZE 1 +#define RBBM_STATUS_HIRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CPRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_PFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1 +#define RBBM_STATUS_RBBM_WU_BUSY_SIZE 1 +#define RBBM_STATUS_CP_NRT_BUSY_SIZE 1 +#define RBBM_STATUS_MH_BUSY_SIZE 1 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1 +#define RBBM_STATUS_SX_BUSY_SIZE 1 +#define RBBM_STATUS_TPC_BUSY_SIZE 1 +#define RBBM_STATUS_SC_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_PA_BUSY_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1 +#define RBBM_STATUS_RB_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_GUI_ACTIVE_SIZE 1 + +#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0 +#define RBBM_STATUS_TC_BUSY_SHIFT 5 +#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8 +#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9 +#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10 +#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12 +#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14 +#define RBBM_STATUS_CP_NRT_BUSY_SHIFT 16 +#define RBBM_STATUS_MH_BUSY_SHIFT 18 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19 +#define RBBM_STATUS_SX_BUSY_SHIFT 21 +#define RBBM_STATUS_TPC_BUSY_SHIFT 22 +#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24 +#define RBBM_STATUS_PA_BUSY_SHIFT 25 +#define RBBM_STATUS_VGT_BUSY_SHIFT 26 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28 +#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30 +#define RBBM_STATUS_GUI_ACTIVE_SHIFT 31 + +#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f +#define RBBM_STATUS_TC_BUSY_MASK 0x00000020 +#define RBBM_STATUS_HIRQ_PENDING_MASK 0x00000100 +#define RBBM_STATUS_CPRQ_PENDING_MASK 0x00000200 +#define RBBM_STATUS_CFRQ_PENDING_MASK 0x00000400 +#define RBBM_STATUS_PFRQ_PENDING_MASK 0x00000800 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000 +#define RBBM_STATUS_RBBM_WU_BUSY_MASK 0x00004000 +#define RBBM_STATUS_CP_NRT_BUSY_MASK 0x00010000 +#define RBBM_STATUS_MH_BUSY_MASK 0x00040000 +#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000 +#define RBBM_STATUS_SX_BUSY_MASK 0x00200000 +#define RBBM_STATUS_TPC_BUSY_MASK 0x00400000 +#define RBBM_STATUS_SC_CNTX_BUSY_MASK 0x01000000 +#define RBBM_STATUS_PA_BUSY_MASK 0x02000000 +#define RBBM_STATUS_VGT_BUSY_MASK 0x04000000 +#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000 +#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000 +#define RBBM_STATUS_RB_CNTX_BUSY_MASK 0x40000000 +#define RBBM_STATUS_GUI_ACTIVE_MASK 0x80000000 + +#define RBBM_STATUS_MASK \ + (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \ + RBBM_STATUS_TC_BUSY_MASK | \ + RBBM_STATUS_HIRQ_PENDING_MASK | \ + RBBM_STATUS_CPRQ_PENDING_MASK | \ + RBBM_STATUS_CFRQ_PENDING_MASK | \ + RBBM_STATUS_PFRQ_PENDING_MASK | \ + RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \ + RBBM_STATUS_RBBM_WU_BUSY_MASK | \ + RBBM_STATUS_CP_NRT_BUSY_MASK | \ + RBBM_STATUS_MH_BUSY_MASK | \ + RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \ + RBBM_STATUS_SX_BUSY_MASK | \ + RBBM_STATUS_TPC_BUSY_MASK | \ + RBBM_STATUS_SC_CNTX_BUSY_MASK | \ + RBBM_STATUS_PA_BUSY_MASK | \ + RBBM_STATUS_VGT_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \ + RBBM_STATUS_RB_CNTX_BUSY_MASK | \ + RBBM_STATUS_GUI_ACTIVE_MASK) + +#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \ + ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \ + (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \ + (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \ + (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \ + (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \ + (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \ + (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \ + (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \ + (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \ + (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \ + (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \ + (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \ + (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \ + (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \ + (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \ + (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \ + (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \ + (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \ + (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \ + (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)) + +#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int : 2; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int : 1; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int : 1; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int : 1; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + } rbbm_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int : 2; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + } rbbm_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_status_t f; +} rbbm_status_u; + + +/* + * RBBM_DSPLY struct + */ + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000 + +#define RBBM_DSPLY_MASK \ + (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \ + RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) + +#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \ + ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \ + (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \ + (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \ + (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \ + (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \ + (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \ + (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \ + (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \ + (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \ + (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \ + (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \ + (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \ + (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \ + (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \ + (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \ + (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \ + (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \ + (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \ + (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \ + (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \ + (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \ + (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \ + (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \ + (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \ + (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)) + +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int : 2; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + } rbbm_dsply_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int : 2; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + } rbbm_dsply_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_dsply_t f; +} rbbm_dsply_u; + + +/* + * RBBM_RENDER_LATEST struct + */ + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000 + +#define RBBM_RENDER_LATEST_MASK \ + (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) + +#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \ + ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \ + (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \ + (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \ + (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)) + +#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + } rbbm_render_latest_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + } rbbm_render_latest_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_render_latest_t f; +} rbbm_render_latest_u; + + +/* + * RBBM_RTL_RELEASE struct + */ + +#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32 + +#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0 + +#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff + +#define RBBM_RTL_RELEASE_MASK \ + (RBBM_RTL_RELEASE_CHANGELIST_MASK) + +#define RBBM_RTL_RELEASE(changelist) \ + ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)) + +#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \ + ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \ + rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_rtl_release_t f; +} rbbm_rtl_release_u; + + +/* + * RBBM_PATCH_RELEASE struct + */ + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000 + +#define RBBM_PATCH_RELEASE_MASK \ + (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \ + RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \ + RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) + +#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \ + ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \ + (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \ + (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)) + +#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + } rbbm_patch_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + } rbbm_patch_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_patch_release_t f; +} rbbm_patch_release_u; + + +/* + * RBBM_AUXILIARY_CONFIG struct + */ + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff + +#define RBBM_AUXILIARY_CONFIG_MASK \ + (RBBM_AUXILIARY_CONFIG_RESERVED_MASK) + +#define RBBM_AUXILIARY_CONFIG(reserved) \ + ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)) + +#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \ + ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \ + rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_auxiliary_config_t f; +} rbbm_auxiliary_config_u; + + +/* + * RBBM_PERIPHID0 struct + */ + +#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8 + +#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0 + +#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff + +#define RBBM_PERIPHID0_MASK \ + (RBBM_PERIPHID0_PARTNUMBER0_MASK) + +#define RBBM_PERIPHID0(partnumber0) \ + ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)) + +#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \ + ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \ + rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + unsigned int : 24; + } rbbm_periphid0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int : 24; + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + } rbbm_periphid0_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid0_t f; +} rbbm_periphid0_u; + + +/* + * RBBM_PERIPHID1 struct + */ + +#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4 +#define RBBM_PERIPHID1_DESIGNER0_SIZE 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0 +#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f +#define RBBM_PERIPHID1_DESIGNER0_MASK 0x000000f0 + +#define RBBM_PERIPHID1_MASK \ + (RBBM_PERIPHID1_PARTNUMBER1_MASK | \ + RBBM_PERIPHID1_DESIGNER0_MASK) + +#define RBBM_PERIPHID1(partnumber1, designer0) \ + ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \ + (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)) + +#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int : 24; + } rbbm_periphid1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int : 24; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + } rbbm_periphid1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid1_t f; +} rbbm_periphid1_u; + + +/* + * RBBM_PERIPHID2 struct + */ + +#define RBBM_PERIPHID2_DESIGNER1_SIZE 4 +#define RBBM_PERIPHID2_REVISION_SIZE 4 + +#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0 +#define RBBM_PERIPHID2_REVISION_SHIFT 4 + +#define RBBM_PERIPHID2_DESIGNER1_MASK 0x0000000f +#define RBBM_PERIPHID2_REVISION_MASK 0x000000f0 + +#define RBBM_PERIPHID2_MASK \ + (RBBM_PERIPHID2_DESIGNER1_MASK | \ + RBBM_PERIPHID2_REVISION_MASK) + +#define RBBM_PERIPHID2(designer1, revision) \ + ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \ + (revision << RBBM_PERIPHID2_REVISION_SHIFT)) + +#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT) + +#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int : 24; + } rbbm_periphid2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int : 24; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + } rbbm_periphid2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid2_t f; +} rbbm_periphid2_u; + + +/* + * RBBM_PERIPHID3 struct + */ + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_CONTINUATION_SIZE 1 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4 +#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c +#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030 +#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080 + +#define RBBM_PERIPHID3_MASK \ + (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \ + RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \ + RBBM_PERIPHID3_MH_INTERFACE_MASK | \ + RBBM_PERIPHID3_CONTINUATION_MASK) + +#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \ + ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \ + (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \ + (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \ + (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)) + +#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int : 1; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 24; + } rbbm_periphid3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int : 24; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 1; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + } rbbm_periphid3_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid3_t f; +} rbbm_periphid3_u; + + +/* + * RBBM_CNTL struct + */ + +#define RBBM_CNTL_READ_TIMEOUT_SIZE 8 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9 + +#define RBBM_CNTL_READ_TIMEOUT_SHIFT 0 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8 + +#define RBBM_CNTL_READ_TIMEOUT_MASK 0x000000ff +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00 + +#define RBBM_CNTL_MASK \ + (RBBM_CNTL_READ_TIMEOUT_MASK | \ + RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) + +#define RBBM_CNTL(read_timeout, regclk_deassert_time) \ + ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \ + (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)) + +#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int : 15; + } rbbm_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int : 15; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + } rbbm_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_cntl_t f; +} rbbm_cntl_u; + + +/* + * RBBM_SKEW_CNTL struct + */ + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f +#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0 + +#define RBBM_SKEW_CNTL_MASK \ + (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \ + RBBM_SKEW_CNTL_SKEW_COUNT_MASK) + +#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \ + ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \ + (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)) + +#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int : 22; + } rbbm_skew_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int : 22; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + } rbbm_skew_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_skew_cntl_t f; +} rbbm_skew_cntl_u; + + +/* + * RBBM_SOFT_RESET struct + */ + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000 + +#define RBBM_SOFT_RESET_MASK \ + (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) + +#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \ + ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \ + (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \ + (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \ + (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \ + (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \ + (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \ + (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \ + (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \ + (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)) + +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + unsigned int : 1; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int : 5; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 2; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int : 15; + } rbbm_soft_reset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int : 15; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int : 2; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 5; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int : 1; + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + } rbbm_soft_reset_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_soft_reset_t f; +} rbbm_soft_reset_u; + + +/* + * RBBM_PM_OVERRIDE1 struct + */ + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000 + +#define RBBM_PM_OVERRIDE1_MASK \ + (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \ + ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \ + (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override1_t f; +} rbbm_pm_override1_u; + + +/* + * RBBM_PM_OVERRIDE2 struct + */ + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800 + +#define RBBM_PM_OVERRIDE2_MASK \ + (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \ + ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \ + (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \ + (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int : 20; + } rbbm_pm_override2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int : 20; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override2_t f; +} rbbm_pm_override2_u; + + +/* + * GC_SYS_IDLE struct + */ + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000 + +#define GC_SYS_IDLE_MASK \ + (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) + +#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \ + ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \ + (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \ + (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \ + (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \ + (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \ + (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \ + (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)) + +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int : 2; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int : 3; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + } gc_sys_idle_t; + +#else // !BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int : 3; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int : 2; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + } gc_sys_idle_t; + +#endif + +typedef union { + unsigned int val : 32; + gc_sys_idle_t f; +} gc_sys_idle_u; + + +/* + * NQWAIT_UNTIL struct + */ + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001 + +#define NQWAIT_UNTIL_MASK \ + (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) + +#define NQWAIT_UNTIL(wait_gui_idle) \ + ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)) + +#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \ + ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \ + nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + unsigned int : 31; + } nqwait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int : 31; + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + } nqwait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + nqwait_until_t f; +} nqwait_until_u; + + +/* + * RBBM_DEBUG_OUT struct + */ + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff + +#define RBBM_DEBUG_OUT_MASK \ + (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) + +#define RBBM_DEBUG_OUT(debug_bus_out) \ + ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)) + +#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \ + ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \ + rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_out_t f; +} rbbm_debug_out_u; + + +/* + * RBBM_DEBUG_CNTL struct + */ + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00 +#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000 + +#define RBBM_DEBUG_CNTL_MASK \ + (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) + +#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \ + ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \ + (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \ + (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \ + (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \ + (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \ + (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)) + +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int : 3; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + } rbbm_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 3; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + } rbbm_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_cntl_t f; +} rbbm_debug_cntl_u; + + +/* + * RBBM_DEBUG struct + */ + +#define RBBM_DEBUG_IGNORE_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1 + +#define RBBM_DEBUG_IGNORE_RTR_SHIFT 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31 + +#define RBBM_DEBUG_IGNORE_RTR_MASK 0x00000002 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000 + +#define RBBM_DEBUG_MASK \ + (RBBM_DEBUG_IGNORE_RTR_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \ + RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \ + RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \ + RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) + +#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \ + ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \ + (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \ + (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \ + (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \ + (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \ + (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \ + (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \ + (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \ + (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \ + (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \ + (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \ + (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)) + +#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int : 1; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int : 3; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 4; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int : 6; + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + } rbbm_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + unsigned int : 6; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int : 4; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 3; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int : 1; + } rbbm_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_t f; +} rbbm_debug_u; + + +/* + * RBBM_READ_ERROR struct + */ + +#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15 +#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1 +#define RBBM_READ_ERROR_READ_ERROR_SIZE 1 + +#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2 +#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30 +#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31 + +#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc +#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000 +#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000 + +#define RBBM_READ_ERROR_MASK \ + (RBBM_READ_ERROR_READ_ADDRESS_MASK | \ + RBBM_READ_ERROR_READ_REQUESTER_MASK | \ + RBBM_READ_ERROR_READ_ERROR_MASK) + +#define RBBM_READ_ERROR(read_address, read_requester, read_error) \ + ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \ + (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \ + (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)) + +#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int : 2; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 13; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + } rbbm_read_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int : 13; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 2; + } rbbm_read_error_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_read_error_t f; +} rbbm_read_error_u; + + +/* + * RBBM_WAIT_IDLE_CLOCKS struct + */ + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff + +#define RBBM_WAIT_IDLE_CLOCKS_MASK \ + (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) + +#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \ + ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)) + +#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \ + ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \ + rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + unsigned int : 24; + } rbbm_wait_idle_clocks_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int : 24; + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + } rbbm_wait_idle_clocks_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_wait_idle_clocks_t f; +} rbbm_wait_idle_clocks_u; + + +/* + * RBBM_INT_CNTL struct + */ + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000 + +#define RBBM_INT_CNTL_MASK \ + (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \ + RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \ + RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) + +#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \ + ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \ + (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \ + (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)) + +#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 12; + } rbbm_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int : 12; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + } rbbm_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_cntl_t f; +} rbbm_int_cntl_u; + + +/* + * RBBM_INT_STATUS struct + */ + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000 + +#define RBBM_INT_STATUS_MASK \ + (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \ + RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \ + RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) + +#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \ + ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \ + (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \ + (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)) + +#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 12; + } rbbm_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int : 12; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + } rbbm_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_status_t f; +} rbbm_int_status_u; + + +/* + * RBBM_INT_ACK struct + */ + +#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1 + +#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19 + +#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000 + +#define RBBM_INT_ACK_MASK \ + (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \ + RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \ + RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) + +#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \ + ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \ + (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \ + (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)) + +#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 12; + } rbbm_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int : 12; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + } rbbm_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_ack_t f; +} rbbm_int_ack_u; + + +/* + * MASTER_INT_SIGNAL struct + */ + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000 +#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000 + +#define MASTER_INT_SIGNAL_MASK \ + (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) + +#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \ + ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \ + (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \ + (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \ + (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)) + +#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int : 5; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 20; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 3; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + } master_int_signal_t; + +#else // !BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int : 3; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 20; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 5; + } master_int_signal_t; + +#endif + +typedef union { + unsigned int val : 32; + master_int_signal_t f; +} master_int_signal_u; + + +/* + * RBBM_PERFCOUNTER1_SELECT struct + */ + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f + +#define RBBM_PERFCOUNTER1_SELECT_MASK \ + (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) + +#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \ + ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)) + +#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \ + ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \ + rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + unsigned int : 26; + } rbbm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int : 26; + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + } rbbm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_select_t f; +} rbbm_perfcounter1_select_u; + + +/* + * RBBM_PERFCOUNTER1_LO struct + */ + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff + +#define RBBM_PERFCOUNTER1_LO_MASK \ + (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) + +#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \ + ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)) + +#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \ + ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \ + rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_lo_t f; +} rbbm_perfcounter1_lo_u; + + +/* + * RBBM_PERFCOUNTER1_HI struct + */ + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff + +#define RBBM_PERFCOUNTER1_HI_MASK \ + (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) + +#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \ + ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)) + +#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \ + ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \ + rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + unsigned int : 16; + } rbbm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + } rbbm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_hi_t f; +} rbbm_perfcounter1_hi_u; + + +#endif + + +#if !defined (_MH_FIDDLE_H) +#define _MH_FIDDLE_H + +/***************************************************************************************************************** + * + * mh_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * MH_ARBITER_CONFIG struct + */ + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200 +#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000 + +#define MH_ARBITER_CONFIG_MASK \ + (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \ + MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \ + MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \ + MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \ + MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) + +#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \ + ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \ + (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \ + (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \ + (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \ + (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \ + (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \ + (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \ + (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \ + (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \ + (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \ + (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \ + (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \ + (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \ + (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)) + +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int : 5; + } mh_arbiter_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int : 5; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + } mh_arbiter_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_arbiter_config_t f; +} mh_arbiter_config_u; + + +/* + * MH_CLNT_AXI_ID_REUSE struct + */ + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000 + +#define MH_CLNT_AXI_ID_REUSE_MASK \ + (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \ + MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \ + MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \ + MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) + +#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \ + ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \ + (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \ + (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \ + (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \ + (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \ + (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \ + (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)) + +#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int : 17; + } mh_clnt_axi_id_reuse_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int : 17; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + } mh_clnt_axi_id_reuse_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_clnt_axi_id_reuse_t f; +} mh_clnt_axi_id_reuse_u; + + +/* + * MH_INTERRUPT_MASK struct + */ + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_MASK_MASK \ + (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + } mh_interrupt_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_mask_t f; +} mh_interrupt_mask_u; + + +/* + * MH_INTERRUPT_STATUS struct + */ + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_STATUS_MASK \ + (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + } mh_interrupt_status_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_status_t f; +} mh_interrupt_status_u; + + +/* + * MH_INTERRUPT_CLEAR struct + */ + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_CLEAR_MASK \ + (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + } mh_interrupt_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_clear_t f; +} mh_interrupt_clear_u; + + +/* + * MH_AXI_ERROR struct + */ + +#define MH_AXI_ERROR_AXI_READ_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1 +#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1 + +#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3 +#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7 + +#define MH_AXI_ERROR_AXI_READ_ID_MASK 0x00000007 +#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008 +#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080 + +#define MH_AXI_ERROR_MASK \ + (MH_AXI_ERROR_AXI_READ_ID_MASK | \ + MH_AXI_ERROR_AXI_READ_ERROR_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ID_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) + +#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \ + ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \ + (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \ + (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)) + +#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int : 24; + } mh_axi_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int : 24; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + } mh_axi_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_error_t f; +} mh_axi_error_u; + + +/* + * MH_PERFCOUNTER0_SELECT struct + */ + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER0_SELECT_MASK \ + (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \ + ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \ + mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } mh_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_select_t f; +} mh_perfcounter0_select_u; + + +/* + * MH_PERFCOUNTER1_SELECT struct + */ + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER1_SELECT_MASK \ + (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \ + ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \ + mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } mh_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_select_t f; +} mh_perfcounter1_select_u; + + +/* + * MH_PERFCOUNTER0_CONFIG struct + */ + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER0_CONFIG_MASK \ + (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER0_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \ + ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \ + mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter0_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + } mh_perfcounter0_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_config_t f; +} mh_perfcounter0_config_u; + + +/* + * MH_PERFCOUNTER1_CONFIG struct + */ + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER1_CONFIG_MASK \ + (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER1_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \ + ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \ + mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter1_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + } mh_perfcounter1_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_config_t f; +} mh_perfcounter1_config_u; + + +/* + * MH_PERFCOUNTER0_LOW struct + */ + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER0_LOW_MASK \ + (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER0_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \ + ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \ + mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_low_t f; +} mh_perfcounter0_low_u; + + +/* + * MH_PERFCOUNTER1_LOW struct + */ + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER1_LOW_MASK \ + (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER1_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \ + ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \ + mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_low_t f; +} mh_perfcounter1_low_u; + + +/* + * MH_PERFCOUNTER0_HI struct + */ + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER0_HI_MASK \ + (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER0_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \ + ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \ + mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_hi_t f; +} mh_perfcounter0_hi_u; + + +/* + * MH_PERFCOUNTER1_HI struct + */ + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER1_HI_MASK \ + (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER1_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \ + ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \ + mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_hi_t f; +} mh_perfcounter1_hi_u; + + +/* + * MH_DEBUG_CTRL struct + */ + +#define MH_DEBUG_CTRL_INDEX_SIZE 6 + +#define MH_DEBUG_CTRL_INDEX_SHIFT 0 + +#define MH_DEBUG_CTRL_INDEX_MASK 0x0000003f + +#define MH_DEBUG_CTRL_MASK \ + (MH_DEBUG_CTRL_INDEX_MASK) + +#define MH_DEBUG_CTRL(index) \ + ((index << MH_DEBUG_CTRL_INDEX_SHIFT)) + +#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \ + ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT) + +#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \ + mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + unsigned int : 26; + } mh_debug_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int : 26; + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + } mh_debug_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_ctrl_t f; +} mh_debug_ctrl_u; + + +/* + * MH_DEBUG_DATA struct + */ + +#define MH_DEBUG_DATA_DATA_SIZE 32 + +#define MH_DEBUG_DATA_DATA_SHIFT 0 + +#define MH_DEBUG_DATA_DATA_MASK 0xffffffff + +#define MH_DEBUG_DATA_MASK \ + (MH_DEBUG_DATA_DATA_MASK) + +#define MH_DEBUG_DATA(data) \ + ((data << MH_DEBUG_DATA_DATA_SHIFT)) + +#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \ + ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT) + +#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \ + mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_data_t f; +} mh_debug_data_u; + + +/* + * MH_AXI_HALT_CONTROL struct + */ + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001 + +#define MH_AXI_HALT_CONTROL_MASK \ + (MH_AXI_HALT_CONTROL_AXI_HALT_MASK) + +#define MH_AXI_HALT_CONTROL(axi_halt) \ + ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)) + +#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \ + ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \ + mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + unsigned int : 31; + } mh_axi_halt_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int : 31; + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + } mh_axi_halt_control_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_halt_control_t f; +} mh_axi_halt_control_u; + + +/* + * MH_DEBUG_REG00 struct + */ + +#define MH_DEBUG_REG00_MH_BUSY_SIZE 1 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1 +#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1 +#define MH_DEBUG_REG00_TCD_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TCD_FULL_SIZE 1 +#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1 +#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_ARQ_FULL_SIZE 1 +#define MH_DEBUG_REG00_WDB_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_WDB_FULL_SIZE 1 +#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1 + +#define MH_DEBUG_REG00_MH_BUSY_SHIFT 0 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1 +#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2 +#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3 +#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5 +#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6 +#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7 +#define MH_DEBUG_REG00_TCD_FULL_SHIFT 8 +#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9 +#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11 +#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12 +#define MH_DEBUG_REG00_ARQ_FULL_SHIFT 13 +#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14 +#define MH_DEBUG_REG00_WDB_FULL_SHIFT 15 +#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16 +#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17 +#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18 +#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19 +#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20 +#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21 +#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22 +#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23 +#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24 +#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28 + +#define MH_DEBUG_REG00_MH_BUSY_MASK 0x00000001 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002 +#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004 +#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008 +#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020 +#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040 +#define MH_DEBUG_REG00_TCD_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG00_TCD_FULL_MASK 0x00000100 +#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200 +#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800 +#define MH_DEBUG_REG00_ARQ_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG00_ARQ_FULL_MASK 0x00002000 +#define MH_DEBUG_REG00_WDB_EMPTY_MASK 0x00004000 +#define MH_DEBUG_REG00_WDB_FULL_MASK 0x00008000 +#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000 +#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000 +#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000 +#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000 +#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000 +#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000 +#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000 +#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000 +#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000 +#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000 +#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000 +#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000 +#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000 + +#define MH_DEBUG_REG00_MASK \ + (MH_DEBUG_REG00_MH_BUSY_MASK | \ + MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \ + MH_DEBUG_REG00_CP_REQUEST_MASK | \ + MH_DEBUG_REG00_VGT_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \ + MH_DEBUG_REG00_TC_CAM_FULL_MASK | \ + MH_DEBUG_REG00_TCD_EMPTY_MASK | \ + MH_DEBUG_REG00_TCD_FULL_MASK | \ + MH_DEBUG_REG00_RB_REQUEST_MASK | \ + MH_DEBUG_REG00_PA_REQUEST_MASK | \ + MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \ + MH_DEBUG_REG00_ARQ_EMPTY_MASK | \ + MH_DEBUG_REG00_ARQ_FULL_MASK | \ + MH_DEBUG_REG00_WDB_EMPTY_MASK | \ + MH_DEBUG_REG00_WDB_FULL_MASK | \ + MH_DEBUG_REG00_AXI_AVALID_MASK | \ + MH_DEBUG_REG00_AXI_AREADY_MASK | \ + MH_DEBUG_REG00_AXI_ARVALID_MASK | \ + MH_DEBUG_REG00_AXI_ARREADY_MASK | \ + MH_DEBUG_REG00_AXI_WVALID_MASK | \ + MH_DEBUG_REG00_AXI_WREADY_MASK | \ + MH_DEBUG_REG00_AXI_RVALID_MASK | \ + MH_DEBUG_REG00_AXI_RREADY_MASK | \ + MH_DEBUG_REG00_AXI_BVALID_MASK | \ + MH_DEBUG_REG00_AXI_BREADY_MASK | \ + MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \ + MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \ + MH_DEBUG_REG00_AXI_RDY_ENA_MASK) + +#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \ + ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \ + (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \ + (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \ + (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \ + (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \ + (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \ + (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \ + (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \ + (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \ + (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \ + (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \ + (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \ + (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \ + (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \ + (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \ + (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \ + (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \ + (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \ + (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \ + (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \ + (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \ + (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \ + (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \ + (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \ + (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \ + (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \ + (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \ + (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \ + (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)) + +#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int : 3; + } mh_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int : 3; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + } mh_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg00_t f; +} mh_debug_reg00_u; + + +/* + * MH_DEBUG_REG01 struct + */ + +#define MH_DEBUG_REG01_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1 +#define MH_DEBUG_REG01_CP_TAG_q_SIZE 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_TAG_q_SIZE 1 +#define MH_DEBUG_REG01_TC_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG01_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_PA_RTR_q_SIZE 1 + +#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0 +#define MH_DEBUG_REG01_CP_RTR_q_SHIFT 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2 +#define MH_DEBUG_REG01_CP_TAG_q_SHIFT 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6 +#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7 +#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8 +#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9 +#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10 +#define MH_DEBUG_REG01_TC_RTR_q_SHIFT 11 +#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14 +#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15 +#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16 +#define MH_DEBUG_REG01_RB_RTR_q_SHIFT 17 +#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18 +#define MH_DEBUG_REG01_PA_RTR_q_SHIFT 19 + +#define MH_DEBUG_REG01_CP_SEND_q_MASK 0x00000001 +#define MH_DEBUG_REG01_CP_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004 +#define MH_DEBUG_REG01_CP_TAG_q_MASK 0x00000038 +#define MH_DEBUG_REG01_CP_BLEN_q_MASK 0x00000040 +#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080 +#define MH_DEBUG_REG01_VGT_RTR_q_MASK 0x00000100 +#define MH_DEBUG_REG01_VGT_TAG_q_MASK 0x00000200 +#define MH_DEBUG_REG01_TC_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG01_TC_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG01_TC_BLEN_q_MASK 0x00001000 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000 +#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000 +#define MH_DEBUG_REG01_RB_SEND_q_MASK 0x00010000 +#define MH_DEBUG_REG01_RB_RTR_q_MASK 0x00020000 +#define MH_DEBUG_REG01_PA_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG01_PA_RTR_q_MASK 0x00080000 + +#define MH_DEBUG_REG01_MASK \ + (MH_DEBUG_REG01_CP_SEND_q_MASK | \ + MH_DEBUG_REG01_CP_RTR_q_MASK | \ + MH_DEBUG_REG01_CP_WRITE_q_MASK | \ + MH_DEBUG_REG01_CP_TAG_q_MASK | \ + MH_DEBUG_REG01_CP_BLEN_q_MASK | \ + MH_DEBUG_REG01_VGT_SEND_q_MASK | \ + MH_DEBUG_REG01_VGT_RTR_q_MASK | \ + MH_DEBUG_REG01_VGT_TAG_q_MASK | \ + MH_DEBUG_REG01_TC_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_BLEN_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_MH_written_MASK | \ + MH_DEBUG_REG01_RB_SEND_q_MASK | \ + MH_DEBUG_REG01_RB_RTR_q_MASK | \ + MH_DEBUG_REG01_PA_SEND_q_MASK | \ + MH_DEBUG_REG01_PA_RTR_q_MASK) + +#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \ + ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \ + (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \ + (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \ + (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \ + (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \ + (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \ + (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \ + (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)) + +#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int : 12; + } mh_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int : 12; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + } mh_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg01_t f; +} mh_debug_reg01_u; + + +/* + * MH_DEBUG_REG02 struct + */ + +#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3 +#define MH_DEBUG_REG02_RDC_RID_SIZE 3 +#define MH_DEBUG_REG02_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1 +#define MH_DEBUG_REG02_BRC_BID_SIZE 3 +#define MH_DEBUG_REG02_BRC_BRESP_SIZE 2 + +#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3 +#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4 +#define MH_DEBUG_REG02_RDC_RID_SHIFT 7 +#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12 +#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13 +#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14 +#define MH_DEBUG_REG02_BRC_BID_SHIFT 15 +#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18 + +#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008 +#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070 +#define MH_DEBUG_REG02_RDC_RID_MASK 0x00000380 +#define MH_DEBUG_REG02_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000 +#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000 +#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000 +#define MH_DEBUG_REG02_BRC_BID_MASK 0x00038000 +#define MH_DEBUG_REG02_BRC_BRESP_MASK 0x000c0000 + +#define MH_DEBUG_REG02_MASK \ + (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG02_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \ + MH_DEBUG_REG02_MH_CLNT_tag_MASK | \ + MH_DEBUG_REG02_RDC_RID_MASK | \ + MH_DEBUG_REG02_RDC_RRESP_MASK | \ + MH_DEBUG_REG02_MH_CP_writeclean_MASK | \ + MH_DEBUG_REG02_MH_RB_writeclean_MASK | \ + MH_DEBUG_REG02_MH_PA_writeclean_MASK | \ + MH_DEBUG_REG02_BRC_BID_MASK | \ + MH_DEBUG_REG02_BRC_BRESP_MASK) + +#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \ + ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \ + (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \ + (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \ + (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \ + (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \ + (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \ + (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \ + (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)) + +#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int : 12; + } mh_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int : 12; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + } mh_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg02_t f; +} mh_debug_reg02_u; + + +/* + * MH_DEBUG_REG03 struct + */ + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG03_MASK \ + (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) + +#define MH_DEBUG_REG03(mh_clnt_data_31_0) \ + ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)) + +#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \ + ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \ + mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg03_t f; +} mh_debug_reg03_u; + + +/* + * MH_DEBUG_REG04 struct + */ + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG04_MASK \ + (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) + +#define MH_DEBUG_REG04(mh_clnt_data_63_32) \ + ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)) + +#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \ + ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \ + mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg04_t f; +} mh_debug_reg04_u; + + +/* + * MH_DEBUG_REG05 struct + */ + +#define MH_DEBUG_REG05_CP_MH_send_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_tag_SIZE 3 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0 +#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1 +#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002 +#define MH_DEBUG_REG05_CP_MH_tag_MASK 0x0000001c +#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG05_MASK \ + (MH_DEBUG_REG05_CP_MH_send_MASK | \ + MH_DEBUG_REG05_CP_MH_write_MASK | \ + MH_DEBUG_REG05_CP_MH_tag_MASK | \ + MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \ + ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \ + (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \ + (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + } mh_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + } mh_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg05_t f; +} mh_debug_reg05_u; + + +/* + * MH_DEBUG_REG06 struct + */ + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG06_MASK \ + (MH_DEBUG_REG06_CP_MH_data_31_0_MASK) + +#define MH_DEBUG_REG06(cp_mh_data_31_0) \ + ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \ + ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \ + mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg06_t f; +} mh_debug_reg06_u; + + +/* + * MH_DEBUG_REG07 struct + */ + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG07_MASK \ + (MH_DEBUG_REG07_CP_MH_data_63_32_MASK) + +#define MH_DEBUG_REG07(cp_mh_data_63_32) \ + ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \ + ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \ + mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg07_t f; +} mh_debug_reg07_u; + + +/* + * MH_DEBUG_REG08 struct + */ + +#define MH_DEBUG_REG08_CP_MH_be_SIZE 8 +#define MH_DEBUG_REG08_RB_MH_be_SIZE 8 +#define MH_DEBUG_REG08_PA_MH_be_SIZE 8 + +#define MH_DEBUG_REG08_CP_MH_be_SHIFT 0 +#define MH_DEBUG_REG08_RB_MH_be_SHIFT 8 +#define MH_DEBUG_REG08_PA_MH_be_SHIFT 16 + +#define MH_DEBUG_REG08_CP_MH_be_MASK 0x000000ff +#define MH_DEBUG_REG08_RB_MH_be_MASK 0x0000ff00 +#define MH_DEBUG_REG08_PA_MH_be_MASK 0x00ff0000 + +#define MH_DEBUG_REG08_MASK \ + (MH_DEBUG_REG08_CP_MH_be_MASK | \ + MH_DEBUG_REG08_RB_MH_be_MASK | \ + MH_DEBUG_REG08_PA_MH_be_MASK) + +#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \ + ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \ + (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \ + (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)) + +#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int : 8; + } mh_debug_reg08_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int : 8; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + } mh_debug_reg08_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg08_t f; +} mh_debug_reg08_u; + + +/* + * MH_DEBUG_REG09 struct + */ + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3 +#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007 +#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008 +#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG09_MASK \ + (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG09_VGT_MH_send_MASK | \ + MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \ + MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \ + ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \ + (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \ + (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \ + (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + } mh_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + } mh_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg09_t f; +} mh_debug_reg09_u; + + +/* + * MH_DEBUG_REG10 struct + */ + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2 +#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004 +#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG10_MASK \ + (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG10_TC_MH_send_MASK | \ + MH_DEBUG_REG10_TC_MH_mask_MASK | \ + MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \ + (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \ + (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + } mh_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + } mh_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg10_t f; +} mh_debug_reg10_u; + + +/* + * MH_DEBUG_REG11 struct + */ + +#define MH_DEBUG_REG11_TC_MH_info_SIZE 25 +#define MH_DEBUG_REG11_TC_MH_send_SIZE 1 + +#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0 +#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25 + +#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff +#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000 + +#define MH_DEBUG_REG11_MASK \ + (MH_DEBUG_REG11_TC_MH_info_MASK | \ + MH_DEBUG_REG11_TC_MH_send_MASK) + +#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \ + ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)) + +#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int : 6; + } mh_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int : 6; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + } mh_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg11_t f; +} mh_debug_reg11_u; + + +/* + * MH_DEBUG_REG12 struct + */ + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1 +#define MH_DEBUG_REG12_TC_MH_written_SIZE 1 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25 +#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000 +#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000 + +#define MH_DEBUG_REG12_MASK \ + (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \ + MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \ + MH_DEBUG_REG12_TC_MH_written_MASK) + +#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \ + ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \ + (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)) + +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int : 5; + } mh_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int : 5; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + } mh_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg12_t f; +} mh_debug_reg12_u; + + +/* + * MH_DEBUG_REG13 struct + */ + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004 +#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG13_MASK \ + (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \ + MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \ + MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) + +#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \ + ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \ + (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \ + (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)) + +#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + } mh_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + } mh_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg13_t f; +} mh_debug_reg13_u; + + +/* + * MH_DEBUG_REG14 struct + */ + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff +#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000 + +#define MH_DEBUG_REG14_MASK \ + (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \ + MH_DEBUG_REG14_TC_ROQ_SEND_MASK) + +#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \ + ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)) + +#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int : 6; + } mh_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int : 6; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + } mh_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg14_t f; +} mh_debug_reg14_u; + + +/* + * MH_DEBUG_REG15 struct + */ + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG15_RB_MH_send_SIZE 1 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG15_MASK \ + (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG15_RB_MH_send_MASK | \ + MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \ + (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \ + (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + } mh_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + } mh_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg15_t f; +} mh_debug_reg15_u; + + +/* + * MH_DEBUG_REG16 struct + */ + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG16_MASK \ + (MH_DEBUG_REG16_RB_MH_data_31_0_MASK) + +#define MH_DEBUG_REG16(rb_mh_data_31_0) \ + ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \ + ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \ + mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg16_t f; +} mh_debug_reg16_u; + + +/* + * MH_DEBUG_REG17 struct + */ + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG17_MASK \ + (MH_DEBUG_REG17_RB_MH_data_63_32_MASK) + +#define MH_DEBUG_REG17(rb_mh_data_63_32) \ + ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg17_t f; +} mh_debug_reg17_u; + + +/* + * MH_DEBUG_REG18 struct + */ + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG18_PA_MH_send_SIZE 1 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG18_MASK \ + (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG18_PA_MH_send_MASK | \ + MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \ + (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \ + (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + } mh_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + } mh_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg18_t f; +} mh_debug_reg18_u; + + +/* + * MH_DEBUG_REG19 struct + */ + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG19_MASK \ + (MH_DEBUG_REG19_PA_MH_data_31_0_MASK) + +#define MH_DEBUG_REG19(pa_mh_data_31_0) \ + ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg19_t f; +} mh_debug_reg19_u; + + +/* + * MH_DEBUG_REG20 struct + */ + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG20_MASK \ + (MH_DEBUG_REG20_PA_MH_data_63_32_MASK) + +#define MH_DEBUG_REG20(pa_mh_data_63_32) \ + ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg20_t f; +} mh_debug_reg20_u; + + +/* + * MH_DEBUG_REG21 struct + */ + +#define MH_DEBUG_REG21_AVALID_q_SIZE 1 +#define MH_DEBUG_REG21_AREADY_q_SIZE 1 +#define MH_DEBUG_REG21_AID_q_SIZE 3 +#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3 +#define MH_DEBUG_REG21_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG21_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG21_ARID_q_SIZE 3 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG21_RVALID_q_SIZE 1 +#define MH_DEBUG_REG21_RREADY_q_SIZE 1 +#define MH_DEBUG_REG21_RLAST_q_SIZE 1 +#define MH_DEBUG_REG21_RID_q_SIZE 3 +#define MH_DEBUG_REG21_WVALID_q_SIZE 1 +#define MH_DEBUG_REG21_WREADY_q_SIZE 1 +#define MH_DEBUG_REG21_WLAST_q_SIZE 1 +#define MH_DEBUG_REG21_WID_q_SIZE 3 +#define MH_DEBUG_REG21_BVALID_q_SIZE 1 +#define MH_DEBUG_REG21_BREADY_q_SIZE 1 +#define MH_DEBUG_REG21_BID_q_SIZE 3 + +#define MH_DEBUG_REG21_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG21_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG21_AID_q_SHIFT 2 +#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5 +#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8 +#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9 +#define MH_DEBUG_REG21_ARID_q_SHIFT 10 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13 +#define MH_DEBUG_REG21_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG21_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG21_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG21_RID_q_SHIFT 18 +#define MH_DEBUG_REG21_WVALID_q_SHIFT 21 +#define MH_DEBUG_REG21_WREADY_q_SHIFT 22 +#define MH_DEBUG_REG21_WLAST_q_SHIFT 23 +#define MH_DEBUG_REG21_WID_q_SHIFT 24 +#define MH_DEBUG_REG21_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG21_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG21_BID_q_SHIFT 29 + +#define MH_DEBUG_REG21_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG21_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG21_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0 +#define MH_DEBUG_REG21_ARVALID_q_MASK 0x00000100 +#define MH_DEBUG_REG21_ARREADY_q_MASK 0x00000200 +#define MH_DEBUG_REG21_ARID_q_MASK 0x00001c00 +#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000 +#define MH_DEBUG_REG21_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG21_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG21_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG21_RID_q_MASK 0x001c0000 +#define MH_DEBUG_REG21_WVALID_q_MASK 0x00200000 +#define MH_DEBUG_REG21_WREADY_q_MASK 0x00400000 +#define MH_DEBUG_REG21_WLAST_q_MASK 0x00800000 +#define MH_DEBUG_REG21_WID_q_MASK 0x07000000 +#define MH_DEBUG_REG21_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG21_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG21_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG21_MASK \ + (MH_DEBUG_REG21_AVALID_q_MASK | \ + MH_DEBUG_REG21_AREADY_q_MASK | \ + MH_DEBUG_REG21_AID_q_MASK | \ + MH_DEBUG_REG21_ALEN_q_2_0_MASK | \ + MH_DEBUG_REG21_ARVALID_q_MASK | \ + MH_DEBUG_REG21_ARREADY_q_MASK | \ + MH_DEBUG_REG21_ARID_q_MASK | \ + MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \ + MH_DEBUG_REG21_RVALID_q_MASK | \ + MH_DEBUG_REG21_RREADY_q_MASK | \ + MH_DEBUG_REG21_RLAST_q_MASK | \ + MH_DEBUG_REG21_RID_q_MASK | \ + MH_DEBUG_REG21_WVALID_q_MASK | \ + MH_DEBUG_REG21_WREADY_q_MASK | \ + MH_DEBUG_REG21_WLAST_q_MASK | \ + MH_DEBUG_REG21_WID_q_MASK | \ + MH_DEBUG_REG21_BVALID_q_MASK | \ + MH_DEBUG_REG21_BREADY_q_MASK | \ + MH_DEBUG_REG21_BID_q_MASK) + +#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \ + (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \ + (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \ + (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)) + +#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT) + +#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + } mh_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + } mh_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg21_t f; +} mh_debug_reg21_u; + + +/* + * MH_DEBUG_REG22 struct + */ + +#define MH_DEBUG_REG22_AVALID_q_SIZE 1 +#define MH_DEBUG_REG22_AREADY_q_SIZE 1 +#define MH_DEBUG_REG22_AID_q_SIZE 3 +#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG22_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG22_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG22_ARID_q_SIZE 3 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1 +#define MH_DEBUG_REG22_WVALID_q_SIZE 1 +#define MH_DEBUG_REG22_WREADY_q_SIZE 1 +#define MH_DEBUG_REG22_WLAST_q_SIZE 1 +#define MH_DEBUG_REG22_WID_q_SIZE 3 +#define MH_DEBUG_REG22_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG22_BVALID_q_SIZE 1 +#define MH_DEBUG_REG22_BREADY_q_SIZE 1 +#define MH_DEBUG_REG22_BID_q_SIZE 3 + +#define MH_DEBUG_REG22_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG22_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG22_AID_q_SHIFT 2 +#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5 +#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7 +#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8 +#define MH_DEBUG_REG22_ARID_q_SHIFT 9 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12 +#define MH_DEBUG_REG22_WVALID_q_SHIFT 13 +#define MH_DEBUG_REG22_WREADY_q_SHIFT 14 +#define MH_DEBUG_REG22_WLAST_q_SHIFT 15 +#define MH_DEBUG_REG22_WID_q_SHIFT 16 +#define MH_DEBUG_REG22_WSTRB_q_SHIFT 19 +#define MH_DEBUG_REG22_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG22_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG22_BID_q_SHIFT 29 + +#define MH_DEBUG_REG22_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG22_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG22_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060 +#define MH_DEBUG_REG22_ARVALID_q_MASK 0x00000080 +#define MH_DEBUG_REG22_ARREADY_q_MASK 0x00000100 +#define MH_DEBUG_REG22_ARID_q_MASK 0x00000e00 +#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000 +#define MH_DEBUG_REG22_WVALID_q_MASK 0x00002000 +#define MH_DEBUG_REG22_WREADY_q_MASK 0x00004000 +#define MH_DEBUG_REG22_WLAST_q_MASK 0x00008000 +#define MH_DEBUG_REG22_WID_q_MASK 0x00070000 +#define MH_DEBUG_REG22_WSTRB_q_MASK 0x07f80000 +#define MH_DEBUG_REG22_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG22_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG22_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG22_MASK \ + (MH_DEBUG_REG22_AVALID_q_MASK | \ + MH_DEBUG_REG22_AREADY_q_MASK | \ + MH_DEBUG_REG22_AID_q_MASK | \ + MH_DEBUG_REG22_ALEN_q_1_0_MASK | \ + MH_DEBUG_REG22_ARVALID_q_MASK | \ + MH_DEBUG_REG22_ARREADY_q_MASK | \ + MH_DEBUG_REG22_ARID_q_MASK | \ + MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \ + MH_DEBUG_REG22_WVALID_q_MASK | \ + MH_DEBUG_REG22_WREADY_q_MASK | \ + MH_DEBUG_REG22_WLAST_q_MASK | \ + MH_DEBUG_REG22_WID_q_MASK | \ + MH_DEBUG_REG22_WSTRB_q_MASK | \ + MH_DEBUG_REG22_BVALID_q_MASK | \ + MH_DEBUG_REG22_BREADY_q_MASK | \ + MH_DEBUG_REG22_BID_q_MASK) + +#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \ + (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \ + (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \ + (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)) + +#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT) + +#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + } mh_debug_reg22_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + } mh_debug_reg22_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg22_t f; +} mh_debug_reg22_u; + + +/* + * MH_DEBUG_REG23 struct + */ + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001 +#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e +#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG23_MASK \ + (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) + +#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \ + ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \ + (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \ + (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)) + +#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + } mh_debug_reg23_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + } mh_debug_reg23_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg23_t f; +} mh_debug_reg23_u; + + +/* + * MH_DEBUG_REG24 struct + */ + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG24_REG_A_SIZE 14 +#define MH_DEBUG_REG24_REG_RE_SIZE 1 +#define MH_DEBUG_REG24_REG_WE_SIZE 1 +#define MH_DEBUG_REG24_BLOCK_RS_SIZE 1 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG24_REG_A_SHIFT 2 +#define MH_DEBUG_REG24_REG_RE_SHIFT 16 +#define MH_DEBUG_REG24_REG_WE_SHIFT 17 +#define MH_DEBUG_REG24_BLOCK_RS_SHIFT 18 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG24_REG_A_MASK 0x0000fffc +#define MH_DEBUG_REG24_REG_RE_MASK 0x00010000 +#define MH_DEBUG_REG24_REG_WE_MASK 0x00020000 +#define MH_DEBUG_REG24_BLOCK_RS_MASK 0x00040000 + +#define MH_DEBUG_REG24_MASK \ + (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG24_REG_A_MASK | \ + MH_DEBUG_REG24_REG_RE_MASK | \ + MH_DEBUG_REG24_REG_WE_MASK | \ + MH_DEBUG_REG24_BLOCK_RS_MASK) + +#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \ + ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \ + (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \ + (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \ + (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \ + (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)) + +#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int : 13; + } mh_debug_reg24_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int : 13; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + } mh_debug_reg24_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg24_t f; +} mh_debug_reg24_u; + + +/* + * MH_DEBUG_REG25 struct + */ + +#define MH_DEBUG_REG25_REG_WD_SIZE 32 + +#define MH_DEBUG_REG25_REG_WD_SHIFT 0 + +#define MH_DEBUG_REG25_REG_WD_MASK 0xffffffff + +#define MH_DEBUG_REG25_MASK \ + (MH_DEBUG_REG25_REG_WD_MASK) + +#define MH_DEBUG_REG25(reg_wd) \ + ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)) + +#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT) + +#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg25_t f; +} mh_debug_reg25_u; + + +/* + * MH_DEBUG_REG26 struct + */ + +#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1 +#define MH_DEBUG_REG26_CNT_q_SIZE 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG26_MH_BUSY_d_SIZE 1 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 +#define MH_DEBUG_REG26_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG26_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_PA_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG26_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG26_BRC_VALID_SIZE 1 + +#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5 +#define MH_DEBUG_REG26_CNT_q_SHIFT 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13 +#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17 +#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18 +#define MH_DEBUG_REG26_CP_RTR_q_SHIFT 19 +#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20 +#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23 +#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24 +#define MH_DEBUG_REG26_RB_RTR_q_SHIFT 25 +#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26 +#define MH_DEBUG_REG26_PA_RTR_q_SHIFT 27 +#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28 +#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29 +#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30 +#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31 + +#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008 +#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020 +#define MH_DEBUG_REG26_CNT_q_MASK 0x00000fc0 +#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG26_MH_BUSY_d_MASK 0x00004000 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000 +#define MH_DEBUG_REG26_CP_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG26_CP_RTR_q_MASK 0x00080000 +#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000 +#define MH_DEBUG_REG26_VGT_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000 +#define MH_DEBUG_REG26_RB_SEND_q_MASK 0x01000000 +#define MH_DEBUG_REG26_RB_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG26_PA_SEND_q_MASK 0x04000000 +#define MH_DEBUG_REG26_PA_RTR_q_MASK 0x08000000 +#define MH_DEBUG_REG26_RDC_VALID_MASK 0x10000000 +#define MH_DEBUG_REG26_RDC_RLAST_MASK 0x20000000 +#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000 +#define MH_DEBUG_REG26_BRC_VALID_MASK 0x80000000 + +#define MH_DEBUG_REG26_MASK \ + (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \ + MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \ + MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \ + MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \ + MH_DEBUG_REG26_CNT_q_MASK | \ + MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG26_MH_BUSY_d_MASK | \ + MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \ + MH_DEBUG_REG26_CP_SEND_q_MASK | \ + MH_DEBUG_REG26_CP_RTR_q_MASK | \ + MH_DEBUG_REG26_VGT_SEND_q_MASK | \ + MH_DEBUG_REG26_VGT_RTR_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG26_RB_SEND_q_MASK | \ + MH_DEBUG_REG26_RB_RTR_q_MASK | \ + MH_DEBUG_REG26_PA_SEND_q_MASK | \ + MH_DEBUG_REG26_PA_RTR_q_MASK | \ + MH_DEBUG_REG26_RDC_VALID_MASK | \ + MH_DEBUG_REG26_RDC_RLAST_MASK | \ + MH_DEBUG_REG26_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG26_BRC_VALID_MASK) + +#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \ + ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \ + (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \ + (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \ + (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \ + (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \ + (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \ + (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \ + (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \ + (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \ + (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \ + (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \ + (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \ + (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)) + +#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + } mh_debug_reg26_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + } mh_debug_reg26_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg26_t f; +} mh_debug_reg26_u; + + +/* + * MH_DEBUG_REG27 struct + */ + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG27_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG27_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG27_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6 +#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9 +#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12 +#define MH_DEBUG_REG27_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16 +#define MH_DEBUG_REG27_ARB_HOLD_SHIFT 17 +#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24 +#define MH_DEBUG_REG27_ARB_QUAL_SHIFT 25 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038 +#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0 +#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00 +#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000 +#define MH_DEBUG_REG27_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG27_KILL_EFF1_MASK 0x00010000 +#define MH_DEBUG_REG27_ARB_HOLD_MASK 0x00020000 +#define MH_DEBUG_REG27_ARB_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000 +#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000 +#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000 +#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000 +#define MH_DEBUG_REG27_ARB_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000 +#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000 +#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000 +#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000 + +#define MH_DEBUG_REG27_MASK \ + (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \ + MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG27_EFF1_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_q_MASK | \ + MH_DEBUG_REG27_EFF1_WIN_MASK | \ + MH_DEBUG_REG27_KILL_EFF1_MASK | \ + MH_DEBUG_REG27_ARB_HOLD_MASK | \ + MH_DEBUG_REG27_ARB_RTR_q_MASK | \ + MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_ARB_QUAL_MASK | \ + MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG27_TCHOLD_IP_q_MASK) + +#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \ + ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \ + (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \ + (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \ + (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \ + (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)) + +#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + } mh_debug_reg27_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + } mh_debug_reg27_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg27_t f; +} mh_debug_reg27_u; + + +/* + * MH_DEBUG_REG28 struct + */ + +#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG28_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10 + +#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0 +#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10 +#define MH_DEBUG_REG28_ARB_QUAL_SHIFT 11 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15 +#define MH_DEBUG_REG28_EFF1_WIN_SHIFT 16 +#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19 +#define MH_DEBUG_REG28_ARB_HOLD_SHIFT 20 +#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22 + +#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080 +#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200 +#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400 +#define MH_DEBUG_REG28_ARB_QUAL_MASK 0x00000800 +#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000 +#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000 +#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000 +#define MH_DEBUG_REG28_EFF1_WIN_MASK 0x00010000 +#define MH_DEBUG_REG28_KILL_EFF1_MASK 0x00020000 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000 +#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000 +#define MH_DEBUG_REG28_ARB_HOLD_MASK 0x00100000 +#define MH_DEBUG_REG28_ARB_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000 + +#define MH_DEBUG_REG28_MASK \ + (MH_DEBUG_REG28_EFF1_WINNER_MASK | \ + MH_DEBUG_REG28_ARB_WINNER_MASK | \ + MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_ARB_QUAL_MASK | \ + MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_EFF1_WIN_MASK | \ + MH_DEBUG_REG28_KILL_EFF1_MASK | \ + MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_RTR_q_MASK | \ + MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) + +#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \ + ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \ + (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \ + (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \ + (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \ + (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)) + +#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + } mh_debug_reg28_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + } mh_debug_reg28_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg28_t f; +} mh_debug_reg28_u; + + +/* + * MH_DEBUG_REG29 struct + */ + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1 +#define MH_DEBUG_REG29_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG29_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG29_CLNT_REQ_SIZE 5 +#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9 +#define MH_DEBUG_REG29_ARB_HOLD_SHIFT 10 +#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11 +#define MH_DEBUG_REG29_CLNT_REQ_SHIFT 12 +#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17 +#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20 +#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23 +#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26 +#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038 +#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200 +#define MH_DEBUG_REG29_ARB_HOLD_MASK 0x00000400 +#define MH_DEBUG_REG29_ARB_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG29_CLNT_REQ_MASK 0x0001f000 +#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000 +#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000 +#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000 +#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000 +#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000 + +#define MH_DEBUG_REG29_MASK \ + (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \ + MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \ + MH_DEBUG_REG29_ARB_HOLD_MASK | \ + MH_DEBUG_REG29_ARB_RTR_q_MASK | \ + MH_DEBUG_REG29_CLNT_REQ_MASK | \ + MH_DEBUG_REG29_RECENT_d_0_MASK | \ + MH_DEBUG_REG29_RECENT_d_1_MASK | \ + MH_DEBUG_REG29_RECENT_d_2_MASK | \ + MH_DEBUG_REG29_RECENT_d_3_MASK | \ + MH_DEBUG_REG29_RECENT_d_4_MASK) + +#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \ + ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \ + (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \ + (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \ + (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \ + (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \ + (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \ + (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \ + (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \ + (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \ + (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \ + (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)) + +#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + } mh_debug_reg29_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + } mh_debug_reg29_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg29_t f; +} mh_debug_reg29_u; + + +/* + * MH_DEBUG_REG30 struct + */ + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG30_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1 +#define MH_DEBUG_REG30_WLAST_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10 +#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19 +#define MH_DEBUG_REG30_WLAST_q_SHIFT 20 +#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21 +#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25 +#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28 +#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008 +#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000 +#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000 +#define MH_DEBUG_REG30_WLAST_q_MASK 0x00100000 +#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000 +#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000 +#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000 +#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000 +#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000 +#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000 + +#define MH_DEBUG_REG30_MASK \ + (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \ + MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG30_TC_MH_written_MASK | \ + MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \ + MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \ + MH_DEBUG_REG30_WLAST_q_MASK | \ + MH_DEBUG_REG30_WBURST_IP_q_MASK | \ + MH_DEBUG_REG30_WBURST_CNT_q_MASK | \ + MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_CP_MH_write_MASK | \ + MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_ARB_WINNER_MASK) + +#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \ + ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \ + (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \ + (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \ + (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \ + (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \ + (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \ + (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \ + (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \ + (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \ + (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)) + +#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + } mh_debug_reg30_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + } mh_debug_reg30_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg30_t f; +} mh_debug_reg30_u; + + +/* + * MH_DEBUG_REG31 struct + */ + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000 + +#define MH_DEBUG_REG31_MASK \ + (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \ + MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \ + ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 3; + } mh_debug_reg31_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int : 3; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + } mh_debug_reg31_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg31_t f; +} mh_debug_reg31_u; + + +/* + * MH_DEBUG_REG32 struct + */ + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8 +#define MH_DEBUG_REG32_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG32_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16 +#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00 +#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000 +#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG32_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG32_MASK \ + (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG32_ROQ_MARK_q_MASK | \ + MH_DEBUG_REG32_ROQ_VALID_q_MASK | \ + MH_DEBUG_REG32_TC_MH_send_MASK | \ + MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG32_KILL_EFF1_MASK | \ + MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG32_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \ + (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + } mh_debug_reg32_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg32_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg32_t f; +} mh_debug_reg32_u; + + +/* + * MH_DEBUG_REG33 struct + */ + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8 +#define MH_DEBUG_REG33_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG33_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16 +#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00 +#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000 +#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG33_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG33_MASK \ + (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG33_ROQ_MARK_d_MASK | \ + MH_DEBUG_REG33_ROQ_VALID_d_MASK | \ + MH_DEBUG_REG33_TC_MH_send_MASK | \ + MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG33_KILL_EFF1_MASK | \ + MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG33_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \ + (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + } mh_debug_reg33_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg33_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg33_t f; +} mh_debug_reg33_u; + + +/* + * MH_DEBUG_REG34 struct + */ + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000 + +#define MH_DEBUG_REG34_MASK \ + (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) + +#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \ + ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \ + (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \ + (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \ + (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)) + +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + } mh_debug_reg34_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + } mh_debug_reg34_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg34_t f; +} mh_debug_reg34_u; + + +/* + * MH_DEBUG_REG35 struct + */ + +#define MH_DEBUG_REG35_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27 + +#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5 + +#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010 +#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0 + +#define MH_DEBUG_REG35_MASK \ + (MH_DEBUG_REG35_TC_MH_send_MASK | \ + MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \ + MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_ADDR_0_MASK) + +#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \ + ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \ + (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \ + (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \ + (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)) + +#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + } mh_debug_reg35_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + } mh_debug_reg35_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg35_t f; +} mh_debug_reg35_u; + + +/* + * MH_DEBUG_REG36 struct + */ + +#define MH_DEBUG_REG36_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27 + +#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5 + +#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010 +#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0 + +#define MH_DEBUG_REG36_MASK \ + (MH_DEBUG_REG36_TC_MH_send_MASK | \ + MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \ + MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_ADDR_1_MASK) + +#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \ + ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \ + (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \ + (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \ + (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)) + +#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + } mh_debug_reg36_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + } mh_debug_reg36_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg36_t f; +} mh_debug_reg36_u; + + +/* + * MH_DEBUG_REG37 struct + */ + +#define MH_DEBUG_REG37_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27 + +#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5 + +#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010 +#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0 + +#define MH_DEBUG_REG37_MASK \ + (MH_DEBUG_REG37_TC_MH_send_MASK | \ + MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \ + MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_ADDR_2_MASK) + +#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \ + ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \ + (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \ + (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \ + (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)) + +#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + } mh_debug_reg37_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + } mh_debug_reg37_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg37_t f; +} mh_debug_reg37_u; + + +/* + * MH_DEBUG_REG38 struct + */ + +#define MH_DEBUG_REG38_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27 + +#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5 + +#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010 +#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0 + +#define MH_DEBUG_REG38_MASK \ + (MH_DEBUG_REG38_TC_MH_send_MASK | \ + MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \ + MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_ADDR_3_MASK) + +#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \ + ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \ + (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \ + (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \ + (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)) + +#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + } mh_debug_reg38_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + } mh_debug_reg38_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg38_t f; +} mh_debug_reg38_u; + + +/* + * MH_DEBUG_REG39 struct + */ + +#define MH_DEBUG_REG39_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27 + +#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5 + +#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010 +#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0 + +#define MH_DEBUG_REG39_MASK \ + (MH_DEBUG_REG39_TC_MH_send_MASK | \ + MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \ + MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_ADDR_4_MASK) + +#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \ + ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \ + (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \ + (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \ + (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)) + +#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + } mh_debug_reg39_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + } mh_debug_reg39_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg39_t f; +} mh_debug_reg39_u; + + +/* + * MH_DEBUG_REG40 struct + */ + +#define MH_DEBUG_REG40_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27 + +#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5 + +#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010 +#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG40_MASK \ + (MH_DEBUG_REG40_TC_MH_send_MASK | \ + MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \ + MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_ADDR_5_MASK) + +#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \ + ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \ + (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \ + (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \ + (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)) + +#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + } mh_debug_reg40_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + } mh_debug_reg40_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg40_t f; +} mh_debug_reg40_u; + + +/* + * MH_DEBUG_REG41 struct + */ + +#define MH_DEBUG_REG41_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27 + +#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5 + +#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010 +#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0 + +#define MH_DEBUG_REG41_MASK \ + (MH_DEBUG_REG41_TC_MH_send_MASK | \ + MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \ + MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_ADDR_6_MASK) + +#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \ + ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \ + (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \ + (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \ + (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)) + +#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + } mh_debug_reg41_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + } mh_debug_reg41_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg41_t f; +} mh_debug_reg41_u; + + +/* + * MH_DEBUG_REG42 struct + */ + +#define MH_DEBUG_REG42_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27 + +#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5 + +#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010 +#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0 + +#define MH_DEBUG_REG42_MASK \ + (MH_DEBUG_REG42_TC_MH_send_MASK | \ + MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \ + MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_ADDR_7_MASK) + +#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \ + ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \ + (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \ + (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \ + (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)) + +#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + } mh_debug_reg42_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + } mh_debug_reg42_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg42_t f; +} mh_debug_reg42_u; + + +/* + * MH_DEBUG_REG43 struct + */ + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_WE_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG43_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3 +#define MH_DEBUG_REG43_MMU_WE_SIZE 1 +#define MH_DEBUG_REG43_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_ID_SIZE 3 +#define MH_DEBUG_REG43_MMU_WRITE_SIZE 1 +#define MH_DEBUG_REG43_MMU_BLEN_SIZE 1 +#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_WDB_WE_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG43_ARB_WE_SHIFT 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3 +#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5 +#define MH_DEBUG_REG43_MMU_RTR_SHIFT 6 +#define MH_DEBUG_REG43_ARB_ID_q_SHIFT 7 +#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10 +#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13 +#define MH_DEBUG_REG43_MMU_WE_SHIFT 16 +#define MH_DEBUG_REG43_ARQ_RTR_SHIFT 17 +#define MH_DEBUG_REG43_MMU_ID_SHIFT 18 +#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21 +#define MH_DEBUG_REG43_MMU_BLEN_SHIFT 22 +#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24 +#define MH_DEBUG_REG43_WDB_WE_SHIFT 25 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG43_ARB_WE_MASK 0x00000002 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG43_ARB_RTR_q_MASK 0x00000008 +#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020 +#define MH_DEBUG_REG43_MMU_RTR_MASK 0x00000040 +#define MH_DEBUG_REG43_ARB_ID_q_MASK 0x00000380 +#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400 +#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000 +#define MH_DEBUG_REG43_MMU_WE_MASK 0x00010000 +#define MH_DEBUG_REG43_ARQ_RTR_MASK 0x00020000 +#define MH_DEBUG_REG43_MMU_ID_MASK 0x001c0000 +#define MH_DEBUG_REG43_MMU_WRITE_MASK 0x00200000 +#define MH_DEBUG_REG43_MMU_BLEN_MASK 0x00400000 +#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000 +#define MH_DEBUG_REG43_WDB_WE_MASK 0x02000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000 + +#define MH_DEBUG_REG43_MASK \ + (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \ + MH_DEBUG_REG43_ARB_WE_MASK | \ + MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \ + MH_DEBUG_REG43_ARB_RTR_q_MASK | \ + MH_DEBUG_REG43_ARB_REG_RTR_MASK | \ + MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \ + MH_DEBUG_REG43_MMU_RTR_MASK | \ + MH_DEBUG_REG43_ARB_ID_q_MASK | \ + MH_DEBUG_REG43_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG43_ARB_BLEN_q_MASK | \ + MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG43_MMU_WE_MASK | \ + MH_DEBUG_REG43_ARQ_RTR_MASK | \ + MH_DEBUG_REG43_MMU_ID_MASK | \ + MH_DEBUG_REG43_MMU_WRITE_MASK | \ + MH_DEBUG_REG43_MMU_BLEN_MASK | \ + MH_DEBUG_REG43_WBURST_IP_q_MASK | \ + MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG43_WDB_WE_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) + +#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \ + ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \ + (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \ + (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \ + (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \ + (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \ + (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \ + (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \ + (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \ + (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \ + (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \ + (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \ + (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \ + (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)) + +#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int : 4; + } mh_debug_reg43_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int : 4; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + } mh_debug_reg43_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg43_t f; +} mh_debug_reg43_u; + + +/* + * MH_DEBUG_REG44 struct + */ + +#define MH_DEBUG_REG44_ARB_WE_SIZE 1 +#define MH_DEBUG_REG44_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG44_ARB_VAD_q_SIZE 28 + +#define MH_DEBUG_REG44_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG44_ARB_ID_q_SHIFT 1 +#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4 + +#define MH_DEBUG_REG44_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG44_ARB_ID_q_MASK 0x0000000e +#define MH_DEBUG_REG44_ARB_VAD_q_MASK 0xfffffff0 + +#define MH_DEBUG_REG44_MASK \ + (MH_DEBUG_REG44_ARB_WE_MASK | \ + MH_DEBUG_REG44_ARB_ID_q_MASK | \ + MH_DEBUG_REG44_ARB_VAD_q_MASK) + +#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \ + ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \ + (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)) + +#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + } mh_debug_reg44_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + } mh_debug_reg44_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg44_t f; +} mh_debug_reg44_u; + + +/* + * MH_DEBUG_REG45 struct + */ + +#define MH_DEBUG_REG45_MMU_WE_SIZE 1 +#define MH_DEBUG_REG45_MMU_ID_SIZE 3 +#define MH_DEBUG_REG45_MMU_PAD_SIZE 28 + +#define MH_DEBUG_REG45_MMU_WE_SHIFT 0 +#define MH_DEBUG_REG45_MMU_ID_SHIFT 1 +#define MH_DEBUG_REG45_MMU_PAD_SHIFT 4 + +#define MH_DEBUG_REG45_MMU_WE_MASK 0x00000001 +#define MH_DEBUG_REG45_MMU_ID_MASK 0x0000000e +#define MH_DEBUG_REG45_MMU_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG45_MASK \ + (MH_DEBUG_REG45_MMU_WE_MASK | \ + MH_DEBUG_REG45_MMU_ID_MASK | \ + MH_DEBUG_REG45_MMU_PAD_MASK) + +#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \ + ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \ + (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \ + (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)) + +#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + } mh_debug_reg45_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + } mh_debug_reg45_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg45_t f; +} mh_debug_reg45_u; + + +/* + * MH_DEBUG_REG46 struct + */ + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WE_SIZE 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG46_ARB_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG46_WDB_WE_SHIFT 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4 +#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19 +#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG46_WDB_WE_MASK 0x00000002 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008 +#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0 +#define MH_DEBUG_REG46_ARB_WLAST_MASK 0x00001000 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000 +#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000 + +#define MH_DEBUG_REG46_MASK \ + (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG46_WDB_WE_MASK | \ + MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \ + MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \ + MH_DEBUG_REG46_ARB_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WID_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) + +#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \ + ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \ + (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \ + (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \ + (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \ + (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \ + (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \ + (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \ + (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \ + (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \ + (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)) + +#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + } mh_debug_reg46_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + } mh_debug_reg46_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg46_t f; +} mh_debug_reg46_u; + + +/* + * MH_DEBUG_REG47 struct + */ + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG47_MASK \ + (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) + +#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \ + ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)) + +#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg47_t f; +} mh_debug_reg47_u; + + +/* + * MH_DEBUG_REG48 struct + */ + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG48_MASK \ + (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) + +#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \ + ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)) + +#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg48_t f; +} mh_debug_reg48_u; + + +/* + * MH_DEBUG_REG49 struct + */ + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RVALID_q_SIZE 1 +#define MH_DEBUG_REG49_RREADY_q_SIZE 1 +#define MH_DEBUG_REG49_RLAST_q_SIZE 1 +#define MH_DEBUG_REG49_BVALID_q_SIZE 1 +#define MH_DEBUG_REG49_BREADY_q_SIZE 1 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14 +#define MH_DEBUG_REG49_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG49_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG49_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG49_BVALID_q_SHIFT 18 +#define MH_DEBUG_REG49_BREADY_q_SHIFT 19 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000 +#define MH_DEBUG_REG49_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG49_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG49_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG49_BVALID_q_MASK 0x00040000 +#define MH_DEBUG_REG49_BREADY_q_MASK 0x00080000 + +#define MH_DEBUG_REG49_MASK \ + (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \ + MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \ + MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \ + MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RVALID_q_MASK | \ + MH_DEBUG_REG49_RREADY_q_MASK | \ + MH_DEBUG_REG49_RLAST_q_MASK | \ + MH_DEBUG_REG49_BVALID_q_MASK | \ + MH_DEBUG_REG49_BREADY_q_MASK) + +#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \ + ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \ + (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \ + (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \ + (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \ + (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \ + (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)) + +#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT) + +#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int : 12; + } mh_debug_reg49_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int : 12; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + } mh_debug_reg49_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg49_t f; +} mh_debug_reg49_u; + + +/* + * MH_DEBUG_REG50 struct + */ + +#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_RID_SIZE 3 +#define MH_DEBUG_REG50_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG50_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3 +#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4 +#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5 +#define MH_DEBUG_REG50_RDC_RID_SHIFT 6 +#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9 +#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29 + +#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008 +#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010 +#define MH_DEBUG_REG50_RDC_VALID_MASK 0x00000020 +#define MH_DEBUG_REG50_RDC_RID_MASK 0x000001c0 +#define MH_DEBUG_REG50_RDC_RLAST_MASK 0x00000200 +#define MH_DEBUG_REG50_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000 +#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000 + +#define MH_DEBUG_REG50_MASK \ + (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG50_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG50_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG50_RDC_VALID_MASK | \ + MH_DEBUG_REG50_RDC_RID_MASK | \ + MH_DEBUG_REG50_RDC_RLAST_MASK | \ + MH_DEBUG_REG50_RDC_RRESP_MASK | \ + MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \ + MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \ + MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \ + MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \ + MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \ + ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \ + (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \ + (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \ + (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \ + (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \ + (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + } mh_debug_reg50_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + } mh_debug_reg50_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg50_t f; +} mh_debug_reg50_u; + + +/* + * MH_DEBUG_REG51 struct + */ + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff + +#define MH_DEBUG_REG51_MASK \ + (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) + +#define MH_DEBUG_REG51(rf_mmu_page_fault) \ + ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)) + +#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg51_t f; +} mh_debug_reg51_u; + + +/* + * MH_DEBUG_REG52 struct + */ + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2 +#define MH_DEBUG_REG52_ARB_WE_SIZE 1 +#define MH_DEBUG_REG52_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22 +#define MH_DEBUG_REG52_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG52_client_behavior_q_SIZE 2 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0 +#define MH_DEBUG_REG52_ARB_WE_SHIFT 2 +#define MH_DEBUG_REG52_MMU_RTR_SHIFT 3 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4 +#define MH_DEBUG_REG52_ARB_ID_q_SHIFT 26 +#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29 +#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003 +#define MH_DEBUG_REG52_ARB_WE_MASK 0x00000004 +#define MH_DEBUG_REG52_MMU_RTR_MASK 0x00000008 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0 +#define MH_DEBUG_REG52_ARB_ID_q_MASK 0x1c000000 +#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000 +#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000 + +#define MH_DEBUG_REG52_MASK \ + (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \ + MH_DEBUG_REG52_ARB_WE_MASK | \ + MH_DEBUG_REG52_MMU_RTR_MASK | \ + MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \ + MH_DEBUG_REG52_ARB_ID_q_MASK | \ + MH_DEBUG_REG52_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG52_client_behavior_q_MASK) + +#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \ + ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \ + (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \ + (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)) + +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + } mh_debug_reg52_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + } mh_debug_reg52_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg52_t f; +} mh_debug_reg52_u; + + +/* + * MH_DEBUG_REG53 struct + */ + +#define MH_DEBUG_REG53_stage1_valid_SIZE 1 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG53_tag_match_q_SIZE 1 +#define MH_DEBUG_REG53_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG53_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG53_MMU_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16 + +#define MH_DEBUG_REG53_stage1_valid_SHIFT 0 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2 +#define MH_DEBUG_REG53_tag_match_q_SHIFT 3 +#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4 +#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5 +#define MH_DEBUG_REG53_MMU_MISS_SHIFT 6 +#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8 +#define MH_DEBUG_REG53_MMU_HIT_SHIFT 9 +#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16 + +#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002 +#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004 +#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008 +#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010 +#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020 +#define MH_DEBUG_REG53_MMU_MISS_MASK 0x00000040 +#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100 +#define MH_DEBUG_REG53_MMU_HIT_MASK 0x00000200 +#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000 + +#define MH_DEBUG_REG53_MASK \ + (MH_DEBUG_REG53_stage1_valid_MASK | \ + MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG53_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG53_tag_match_q_MASK | \ + MH_DEBUG_REG53_tag_miss_q_MASK | \ + MH_DEBUG_REG53_va_in_range_q_MASK | \ + MH_DEBUG_REG53_MMU_MISS_MASK | \ + MH_DEBUG_REG53_MMU_READ_MISS_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \ + MH_DEBUG_REG53_MMU_HIT_MASK | \ + MH_DEBUG_REG53_MMU_READ_HIT_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \ + MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) + +#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \ + ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \ + (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \ + (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \ + (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \ + (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \ + (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \ + (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \ + (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \ + (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \ + (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \ + (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \ + (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)) + +#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + } mh_debug_reg53_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + } mh_debug_reg53_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg53_t f; +} mh_debug_reg53_u; + + +/* + * MH_DEBUG_REG54 struct + */ + +#define MH_DEBUG_REG54_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG54_MMU_WE_SIZE 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1 +#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG54_stage1_valid_SIZE 1 +#define MH_DEBUG_REG54_stage2_valid_SIZE 1 +#define MH_DEBUG_REG54_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG54_tag_match_q_SIZE 1 +#define MH_DEBUG_REG54_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG54_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1 +#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16 + +#define MH_DEBUG_REG54_ARQ_RTR_SHIFT 0 +#define MH_DEBUG_REG54_MMU_WE_SHIFT 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5 +#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6 +#define MH_DEBUG_REG54_stage1_valid_SHIFT 7 +#define MH_DEBUG_REG54_stage2_valid_SHIFT 8 +#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11 +#define MH_DEBUG_REG54_tag_match_q_SHIFT 12 +#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13 +#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15 +#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16 + +#define MH_DEBUG_REG54_ARQ_RTR_MASK 0x00000001 +#define MH_DEBUG_REG54_MMU_WE_MASK 0x00000002 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020 +#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040 +#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080 +#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100 +#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800 +#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000 +#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000 +#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000 +#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000 + +#define MH_DEBUG_REG54_MASK \ + (MH_DEBUG_REG54_ARQ_RTR_MASK | \ + MH_DEBUG_REG54_MMU_WE_MASK | \ + MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \ + MH_DEBUG_REG54_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG54_stage1_valid_MASK | \ + MH_DEBUG_REG54_stage2_valid_MASK | \ + MH_DEBUG_REG54_client_behavior_q_MASK | \ + MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG54_tag_match_q_MASK | \ + MH_DEBUG_REG54_tag_miss_q_MASK | \ + MH_DEBUG_REG54_va_in_range_q_MASK | \ + MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_MASK) + +#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \ + ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \ + (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \ + (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \ + (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \ + (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \ + (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \ + (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)) + +#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + } mh_debug_reg54_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + } mh_debug_reg54_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg54_t f; +} mh_debug_reg54_u; + + +/* + * MH_DEBUG_REG55 struct + */ + +#define MH_DEBUG_REG55_TAG0_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG55_TAG1_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1 + +#define MH_DEBUG_REG55_TAG0_VA_SHIFT 0 +#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG55_TAG1_VA_SHIFT 16 +#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29 + +#define MH_DEBUG_REG55_TAG0_VA_MASK 0x00001fff +#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000 +#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG55_TAG1_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000 + +#define MH_DEBUG_REG55_MASK \ + (MH_DEBUG_REG55_TAG0_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_0_MASK | \ + MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG55_TAG1_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_1_MASK) + +#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \ + ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \ + (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \ + (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \ + (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \ + (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)) + +#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int : 2; + } mh_debug_reg55_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int : 2; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + } mh_debug_reg55_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg55_t f; +} mh_debug_reg55_u; + + +/* + * MH_DEBUG_REG56 struct + */ + +#define MH_DEBUG_REG56_TAG2_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG56_TAG3_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1 + +#define MH_DEBUG_REG56_TAG2_VA_SHIFT 0 +#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG56_TAG3_VA_SHIFT 16 +#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29 + +#define MH_DEBUG_REG56_TAG2_VA_MASK 0x00001fff +#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000 +#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG56_TAG3_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000 + +#define MH_DEBUG_REG56_MASK \ + (MH_DEBUG_REG56_TAG2_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_2_MASK | \ + MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG56_TAG3_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_3_MASK) + +#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \ + ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \ + (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \ + (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \ + (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \ + (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)) + +#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int : 2; + } mh_debug_reg56_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int : 2; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + } mh_debug_reg56_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg56_t f; +} mh_debug_reg56_u; + + +/* + * MH_DEBUG_REG57 struct + */ + +#define MH_DEBUG_REG57_TAG4_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG57_TAG5_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1 + +#define MH_DEBUG_REG57_TAG4_VA_SHIFT 0 +#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG57_TAG5_VA_SHIFT 16 +#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29 + +#define MH_DEBUG_REG57_TAG4_VA_MASK 0x00001fff +#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000 +#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG57_TAG5_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000 + +#define MH_DEBUG_REG57_MASK \ + (MH_DEBUG_REG57_TAG4_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_4_MASK | \ + MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG57_TAG5_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_5_MASK) + +#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \ + ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \ + (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \ + (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \ + (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \ + (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)) + +#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int : 2; + } mh_debug_reg57_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int : 2; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + } mh_debug_reg57_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg57_t f; +} mh_debug_reg57_u; + + +/* + * MH_DEBUG_REG58 struct + */ + +#define MH_DEBUG_REG58_TAG6_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG58_TAG7_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1 + +#define MH_DEBUG_REG58_TAG6_VA_SHIFT 0 +#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG58_TAG7_VA_SHIFT 16 +#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29 + +#define MH_DEBUG_REG58_TAG6_VA_MASK 0x00001fff +#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000 +#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG58_TAG7_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000 + +#define MH_DEBUG_REG58_MASK \ + (MH_DEBUG_REG58_TAG6_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_6_MASK | \ + MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG58_TAG7_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_7_MASK) + +#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \ + ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \ + (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \ + (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \ + (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \ + (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)) + +#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int : 2; + } mh_debug_reg58_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int : 2; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + } mh_debug_reg58_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg58_t f; +} mh_debug_reg58_u; + + +/* + * MH_DEBUG_REG59 struct + */ + +#define MH_DEBUG_REG59_TAG8_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG59_TAG9_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1 + +#define MH_DEBUG_REG59_TAG8_VA_SHIFT 0 +#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG59_TAG9_VA_SHIFT 16 +#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29 + +#define MH_DEBUG_REG59_TAG8_VA_MASK 0x00001fff +#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000 +#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG59_TAG9_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000 + +#define MH_DEBUG_REG59_MASK \ + (MH_DEBUG_REG59_TAG8_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_8_MASK | \ + MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG59_TAG9_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_9_MASK) + +#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \ + ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \ + (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \ + (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \ + (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \ + (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)) + +#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int : 2; + } mh_debug_reg59_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int : 2; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + } mh_debug_reg59_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg59_t f; +} mh_debug_reg59_u; + + +/* + * MH_DEBUG_REG60 struct + */ + +#define MH_DEBUG_REG60_TAG10_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG60_TAG11_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1 + +#define MH_DEBUG_REG60_TAG10_VA_SHIFT 0 +#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG60_TAG11_VA_SHIFT 16 +#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29 + +#define MH_DEBUG_REG60_TAG10_VA_MASK 0x00001fff +#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000 +#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG60_TAG11_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000 + +#define MH_DEBUG_REG60_MASK \ + (MH_DEBUG_REG60_TAG10_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_10_MASK | \ + MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG60_TAG11_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_11_MASK) + +#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \ + ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \ + (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \ + (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \ + (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \ + (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)) + +#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int : 2; + } mh_debug_reg60_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int : 2; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + } mh_debug_reg60_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg60_t f; +} mh_debug_reg60_u; + + +/* + * MH_DEBUG_REG61 struct + */ + +#define MH_DEBUG_REG61_TAG12_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG61_TAG13_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1 + +#define MH_DEBUG_REG61_TAG12_VA_SHIFT 0 +#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG61_TAG13_VA_SHIFT 16 +#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29 + +#define MH_DEBUG_REG61_TAG12_VA_MASK 0x00001fff +#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000 +#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG61_TAG13_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000 + +#define MH_DEBUG_REG61_MASK \ + (MH_DEBUG_REG61_TAG12_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_12_MASK | \ + MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG61_TAG13_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_13_MASK) + +#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \ + ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \ + (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \ + (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \ + (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \ + (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)) + +#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int : 2; + } mh_debug_reg61_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int : 2; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + } mh_debug_reg61_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg61_t f; +} mh_debug_reg61_u; + + +/* + * MH_DEBUG_REG62 struct + */ + +#define MH_DEBUG_REG62_TAG14_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG62_TAG15_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1 + +#define MH_DEBUG_REG62_TAG14_VA_SHIFT 0 +#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG62_TAG15_VA_SHIFT 16 +#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29 + +#define MH_DEBUG_REG62_TAG14_VA_MASK 0x00001fff +#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000 +#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG62_TAG15_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000 + +#define MH_DEBUG_REG62_MASK \ + (MH_DEBUG_REG62_TAG14_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_14_MASK | \ + MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG62_TAG15_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_15_MASK) + +#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \ + ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \ + (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \ + (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \ + (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \ + (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)) + +#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int : 2; + } mh_debug_reg62_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int : 2; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + } mh_debug_reg62_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg62_t f; +} mh_debug_reg62_u; + + +/* + * MH_DEBUG_REG63 struct + */ + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG63_MASK \ + (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG63(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \ + ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \ + mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg63_t f; +} mh_debug_reg63_u; + + +/* + * MH_MMU_CONFIG struct + */ + +#define MH_MMU_CONFIG_MMU_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_RESERVED1_SIZE 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2 + +#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1 +#define MH_MMU_CONFIG_RESERVED1_SHIFT 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24 + +#define MH_MMU_CONFIG_MMU_ENABLE_MASK 0x00000001 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002 +#define MH_MMU_CONFIG_RESERVED1_MASK 0x0000000c +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000 + +#define MH_MMU_CONFIG_MASK \ + (MH_MMU_CONFIG_MMU_ENABLE_MASK | \ + MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \ + MH_MMU_CONFIG_RESERVED1_MASK | \ + MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) + +#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \ + ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \ + (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \ + (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \ + (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \ + (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \ + (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)) + +#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int : 6; + } mh_mmu_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int : 6; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + } mh_mmu_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_config_t f; +} mh_mmu_config_u; + + +/* + * MH_MMU_VA_RANGE struct + */ + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12 +#define MH_MMU_VA_RANGE_VA_BASE_SIZE 20 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0 +#define MH_MMU_VA_RANGE_VA_BASE_SHIFT 12 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff +#define MH_MMU_VA_RANGE_VA_BASE_MASK 0xfffff000 + +#define MH_MMU_VA_RANGE_MASK \ + (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \ + MH_MMU_VA_RANGE_VA_BASE_MASK) + +#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \ + ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \ + (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)) + +#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + } mh_mmu_va_range_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + } mh_mmu_va_range_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_va_range_t f; +} mh_mmu_va_range_u; + + +/* + * MH_MMU_PT_BASE struct + */ + +#define MH_MMU_PT_BASE_PT_BASE_SIZE 20 + +#define MH_MMU_PT_BASE_PT_BASE_SHIFT 12 + +#define MH_MMU_PT_BASE_PT_BASE_MASK 0xfffff000 + +#define MH_MMU_PT_BASE_MASK \ + (MH_MMU_PT_BASE_PT_BASE_MASK) + +#define MH_MMU_PT_BASE(pt_base) \ + ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)) + +#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \ + ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \ + mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int : 12; + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + } mh_mmu_pt_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + unsigned int : 12; + } mh_mmu_pt_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_pt_base_t f; +} mh_mmu_pt_base_u; + + +/* + * MH_MMU_PAGE_FAULT struct + */ + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE 3 +#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE 20 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4 +#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11 +#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001 +#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c +#define MH_MMU_PAGE_FAULT_AXI_ID_MASK 0x00000070 +#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800 +#define MH_MMU_PAGE_FAULT_REQ_VA_MASK 0xfffff000 + +#define MH_MMU_PAGE_FAULT_MASK \ + (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \ + MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \ + MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \ + MH_MMU_PAGE_FAULT_AXI_ID_MASK | \ + MH_MMU_PAGE_FAULT_RESERVED1_MASK | \ + MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_REQ_VA_MASK) + +#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \ + ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \ + (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \ + (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \ + (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \ + (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \ + (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \ + (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \ + (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)) + +#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + } mh_mmu_page_fault_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + } mh_mmu_page_fault_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_page_fault_t f; +} mh_mmu_page_fault_u; + + +/* + * MH_MMU_TRAN_ERROR struct + */ + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0 + +#define MH_MMU_TRAN_ERROR_MASK \ + (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) + +#define MH_MMU_TRAN_ERROR(tran_error) \ + ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)) + +#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \ + ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \ + mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int : 5; + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + } mh_mmu_tran_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + unsigned int : 5; + } mh_mmu_tran_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_tran_error_t f; +} mh_mmu_tran_error_u; + + +/* + * MH_MMU_INVALIDATE struct + */ + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002 + +#define MH_MMU_INVALIDATE_MASK \ + (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) + +#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \ + ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)) + +#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int : 30; + } mh_mmu_invalidate_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int : 30; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + } mh_mmu_invalidate_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_invalidate_t f; +} mh_mmu_invalidate_u; + + +/* + * MH_MMU_MPU_BASE struct + */ + +#define MH_MMU_MPU_BASE_MPU_BASE_SIZE 20 + +#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12 + +#define MH_MMU_MPU_BASE_MPU_BASE_MASK 0xfffff000 + +#define MH_MMU_MPU_BASE_MASK \ + (MH_MMU_MPU_BASE_MPU_BASE_MASK) + +#define MH_MMU_MPU_BASE(mpu_base) \ + ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)) + +#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \ + ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \ + mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int : 12; + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + } mh_mmu_mpu_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + unsigned int : 12; + } mh_mmu_mpu_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_base_t f; +} mh_mmu_mpu_base_u; + + +/* + * MH_MMU_MPU_END struct + */ + +#define MH_MMU_MPU_END_MPU_END_SIZE 20 + +#define MH_MMU_MPU_END_MPU_END_SHIFT 12 + +#define MH_MMU_MPU_END_MPU_END_MASK 0xfffff000 + +#define MH_MMU_MPU_END_MASK \ + (MH_MMU_MPU_END_MPU_END_MASK) + +#define MH_MMU_MPU_END(mpu_end) \ + ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)) + +#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \ + ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT) + +#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \ + mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int : 12; + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + } mh_mmu_mpu_end_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + unsigned int : 12; + } mh_mmu_mpu_end_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_end_t f; +} mh_mmu_mpu_end_u; + + +#endif + + +#if !defined (_PA_FIDDLE_H) +#define _PA_FIDDLE_H + +/***************************************************************************************************************** + * + * pa_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * PA_CL_VPORT_XSCALE struct + */ + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_XSCALE_MASK \ + (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) + +#define PA_CL_VPORT_XSCALE(vport_xscale) \ + ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)) + +#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \ + ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \ + pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xscale_t f; +} pa_cl_vport_xscale_u; + + +/* + * PA_CL_VPORT_XOFFSET struct + */ + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_XOFFSET_MASK \ + (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) + +#define PA_CL_VPORT_XOFFSET(vport_xoffset) \ + ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)) + +#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \ + ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \ + pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xoffset_t f; +} pa_cl_vport_xoffset_u; + + +/* + * PA_CL_VPORT_YSCALE struct + */ + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_YSCALE_MASK \ + (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) + +#define PA_CL_VPORT_YSCALE(vport_yscale) \ + ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)) + +#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \ + ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \ + pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yscale_t f; +} pa_cl_vport_yscale_u; + + +/* + * PA_CL_VPORT_YOFFSET struct + */ + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_YOFFSET_MASK \ + (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) + +#define PA_CL_VPORT_YOFFSET(vport_yoffset) \ + ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)) + +#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \ + ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \ + pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yoffset_t f; +} pa_cl_vport_yoffset_u; + + +/* + * PA_CL_VPORT_ZSCALE struct + */ + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_ZSCALE_MASK \ + (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) + +#define PA_CL_VPORT_ZSCALE(vport_zscale) \ + ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)) + +#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \ + ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \ + pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zscale_t f; +} pa_cl_vport_zscale_u; + + +/* + * PA_CL_VPORT_ZOFFSET struct + */ + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_ZOFFSET_MASK \ + (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) + +#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \ + ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)) + +#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \ + ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \ + pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zoffset_t f; +} pa_cl_vport_zoffset_u; + + +/* + * PA_CL_VTE_CNTL struct + */ + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK 0x00000200 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800 + +#define PA_CL_VTE_CNTL_MASK \ + (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \ + PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) + +#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \ + ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \ + (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \ + (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \ + (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \ + (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \ + (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \ + (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \ + (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \ + (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \ + (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)) + +#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int : 2; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int : 20; + } pa_cl_vte_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int : 20; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int : 2; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + } pa_cl_vte_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vte_cntl_t f; +} pa_cl_vte_cntl_u; + + +/* + * PA_CL_CLIP_CNTL struct + */ + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000 + +#define PA_CL_CLIP_CNTL_MASK \ + (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \ + PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \ + PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \ + PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \ + PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \ + PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) + +#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \ + ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \ + (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \ + (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \ + (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \ + (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \ + (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \ + (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \ + (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)) + +#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 16; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 1; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int : 7; + } pa_cl_clip_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 7; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int : 1; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 16; + } pa_cl_clip_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_clip_cntl_t f; +} pa_cl_clip_cntl_u; + + +/* + * PA_CL_GB_VERT_CLIP_ADJ struct + */ + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_CLIP_ADJ_MASK \ + (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \ + ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \ + pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_clip_adj_t f; +} pa_cl_gb_vert_clip_adj_u; + + +/* + * PA_CL_GB_VERT_DISC_ADJ struct + */ + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_DISC_ADJ_MASK \ + (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \ + ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \ + pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_disc_adj_t f; +} pa_cl_gb_vert_disc_adj_u; + + +/* + * PA_CL_GB_HORZ_CLIP_ADJ struct + */ + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \ + (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \ + ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \ + pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_clip_adj_t f; +} pa_cl_gb_horz_clip_adj_u; + + +/* + * PA_CL_GB_HORZ_DISC_ADJ struct + */ + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_DISC_ADJ_MASK \ + (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \ + ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \ + pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_disc_adj_t f; +} pa_cl_gb_horz_disc_adj_u; + + +/* + * PA_CL_ENHANCE struct + */ + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0 +#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001 +#define PA_CL_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_CL_ENHANCE_MASK \ + (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \ + PA_CL_ENHANCE_ECO_SPARE3_MASK | \ + PA_CL_ENHANCE_ECO_SPARE2_MASK | \ + PA_CL_ENHANCE_ECO_SPARE1_MASK | \ + PA_CL_ENHANCE_ECO_SPARE0_MASK) + +#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \ + (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + unsigned int : 27; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + } pa_cl_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 27; + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + } pa_cl_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_enhance_t f; +} pa_cl_enhance_u; + + +/* + * PA_SC_ENHANCE struct + */ + +#define PA_SC_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_SC_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_SC_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_SC_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_SC_ENHANCE_MASK \ + (PA_SC_ENHANCE_ECO_SPARE3_MASK | \ + PA_SC_ENHANCE_ECO_SPARE2_MASK | \ + PA_SC_ENHANCE_ECO_SPARE1_MASK | \ + PA_SC_ENHANCE_ECO_SPARE0_MASK) + +#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int : 28; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + } pa_sc_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 28; + } pa_sc_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_enhance_t f; +} pa_sc_enhance_u; + + +/* + * PA_SU_VTX_CNTL struct + */ + +#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1 +#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2 +#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0 +#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1 +#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001 +#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006 +#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038 + +#define PA_SU_VTX_CNTL_MASK \ + (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \ + PA_SU_VTX_CNTL_ROUND_MODE_MASK | \ + PA_SU_VTX_CNTL_QUANT_MODE_MASK) + +#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \ + ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \ + (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \ + (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)) + +#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int : 26; + } pa_su_vtx_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int : 26; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + } pa_su_vtx_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_vtx_cntl_t f; +} pa_su_vtx_cntl_u; + + +/* + * PA_SU_POINT_SIZE struct + */ + +#define PA_SU_POINT_SIZE_HEIGHT_SIZE 16 +#define PA_SU_POINT_SIZE_WIDTH_SIZE 16 + +#define PA_SU_POINT_SIZE_HEIGHT_SHIFT 0 +#define PA_SU_POINT_SIZE_WIDTH_SHIFT 16 + +#define PA_SU_POINT_SIZE_HEIGHT_MASK 0x0000ffff +#define PA_SU_POINT_SIZE_WIDTH_MASK 0xffff0000 + +#define PA_SU_POINT_SIZE_MASK \ + (PA_SU_POINT_SIZE_HEIGHT_MASK | \ + PA_SU_POINT_SIZE_WIDTH_MASK) + +#define PA_SU_POINT_SIZE(height, width) \ + ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \ + (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)) + +#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + } pa_su_point_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + } pa_su_point_size_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_size_t f; +} pa_su_point_size_u; + + +/* + * PA_SU_POINT_MINMAX struct + */ + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff +#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000 + +#define PA_SU_POINT_MINMAX_MASK \ + (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \ + PA_SU_POINT_MINMAX_MAX_SIZE_MASK) + +#define PA_SU_POINT_MINMAX(min_size, max_size) \ + ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \ + (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)) + +#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + } pa_su_point_minmax_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + } pa_su_point_minmax_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_minmax_t f; +} pa_su_point_minmax_u; + + +/* + * PA_SU_LINE_CNTL struct + */ + +#define PA_SU_LINE_CNTL_WIDTH_SIZE 16 + +#define PA_SU_LINE_CNTL_WIDTH_SHIFT 0 + +#define PA_SU_LINE_CNTL_WIDTH_MASK 0x0000ffff + +#define PA_SU_LINE_CNTL_MASK \ + (PA_SU_LINE_CNTL_WIDTH_MASK) + +#define PA_SU_LINE_CNTL(width) \ + ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT)) + +#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \ + ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \ + pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + unsigned int : 16; + } pa_su_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int : 16; + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + } pa_su_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_line_cntl_t f; +} pa_su_line_cntl_u; + + +/* + * PA_SU_FACE_DATA struct + */ + +#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27 + +#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5 + +#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0 + +#define PA_SU_FACE_DATA_MASK \ + (PA_SU_FACE_DATA_BASE_ADDR_MASK) + +#define PA_SU_FACE_DATA(base_addr) \ + ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)) + +#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \ + ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \ + pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int : 5; + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + } pa_su_face_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + unsigned int : 5; + } pa_su_face_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_face_data_t f; +} pa_su_face_data_u; + + +/* + * PA_SU_SC_MODE_CNTL struct + */ + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1 +#define PA_SU_SC_MODE_CNTL_FACE_SHIFT 2 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26 +#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT 28 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002 +#define PA_SU_SC_MODE_CNTL_FACE_MASK 0x00000004 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000 +#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK 0x10000000 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000 + +#define PA_SU_SC_MODE_CNTL_MASK \ + (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \ + PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \ + PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \ + PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \ + PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \ + PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK | \ + PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) + +#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, clamped_faceness, zero_area_faceness, face_kill_enable, face_write_enable) \ + ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \ + (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \ + (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \ + (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \ + (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \ + (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \ + (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \ + (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \ + (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \ + (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \ + (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \ + (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \ + (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \ + (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \ + (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \ + (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \ + (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \ + (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \ + (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) | \ + (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \ + (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \ + (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)) + +#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CLAMPED_FACENESS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CLAMPED_FACENESS(pa_su_sc_mode_cntl_reg, clamped_faceness) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) | (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int : 1; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int : 1; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int : 1; + unsigned int clamped_faceness : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + } pa_su_sc_mode_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int clamped_faceness : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int : 1; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int : 1; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + } pa_su_sc_mode_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_sc_mode_cntl_t f; +} pa_su_sc_mode_cntl_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \ + (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \ + ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \ + pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_scale_t f; +} pa_su_poly_offset_front_scale_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \ + ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \ + pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_offset_t f; +} pa_su_poly_offset_front_offset_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \ + (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \ + ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \ + pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_scale_t f; +} pa_su_poly_offset_back_scale_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \ + ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \ + pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_offset_t f; +} pa_su_poly_offset_back_offset_u; + + +/* + * PA_SU_PERFCOUNTER0_SELECT struct + */ + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER0_SELECT_MASK \ + (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \ + ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \ + pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_select_t f; +} pa_su_perfcounter0_select_u; + + +/* + * PA_SU_PERFCOUNTER1_SELECT struct + */ + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER1_SELECT_MASK \ + (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \ + ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \ + pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_select_t f; +} pa_su_perfcounter1_select_u; + + +/* + * PA_SU_PERFCOUNTER2_SELECT struct + */ + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER2_SELECT_MASK \ + (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \ + ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \ + pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_select_t f; +} pa_su_perfcounter2_select_u; + + +/* + * PA_SU_PERFCOUNTER3_SELECT struct + */ + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER3_SELECT_MASK \ + (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \ + ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \ + pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_select_t f; +} pa_su_perfcounter3_select_u; + + +/* + * PA_SU_PERFCOUNTER0_LOW struct + */ + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER0_LOW_MASK \ + (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \ + ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \ + pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_low_t f; +} pa_su_perfcounter0_low_u; + + +/* + * PA_SU_PERFCOUNTER0_HI struct + */ + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER0_HI_MASK \ + (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \ + ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \ + pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_hi_t f; +} pa_su_perfcounter0_hi_u; + + +/* + * PA_SU_PERFCOUNTER1_LOW struct + */ + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER1_LOW_MASK \ + (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \ + ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \ + pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_low_t f; +} pa_su_perfcounter1_low_u; + + +/* + * PA_SU_PERFCOUNTER1_HI struct + */ + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER1_HI_MASK \ + (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \ + ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \ + pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_hi_t f; +} pa_su_perfcounter1_hi_u; + + +/* + * PA_SU_PERFCOUNTER2_LOW struct + */ + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER2_LOW_MASK \ + (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \ + ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \ + pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_low_t f; +} pa_su_perfcounter2_low_u; + + +/* + * PA_SU_PERFCOUNTER2_HI struct + */ + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER2_HI_MASK \ + (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \ + ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \ + pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_hi_t f; +} pa_su_perfcounter2_hi_u; + + +/* + * PA_SU_PERFCOUNTER3_LOW struct + */ + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER3_LOW_MASK \ + (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \ + ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \ + pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_low_t f; +} pa_su_perfcounter3_low_u; + + +/* + * PA_SU_PERFCOUNTER3_HI struct + */ + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER3_HI_MASK \ + (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \ + ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \ + pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_hi_t f; +} pa_su_perfcounter3_hi_u; + + +/* + * PA_SC_WINDOW_OFFSET struct + */ + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000 + +#define PA_SC_WINDOW_OFFSET_MASK \ + (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \ + PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) + +#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \ + ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \ + (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)) + +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + } pa_sc_window_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + } pa_sc_window_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_offset_t f; +} pa_sc_window_offset_u; + + +/* + * PA_SC_AA_CONFIG struct + */ + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000 + +#define PA_SC_AA_CONFIG_MASK \ + (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \ + PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) + +#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \ + ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \ + (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)) + +#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + unsigned int : 10; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 15; + } pa_sc_aa_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int : 15; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 10; + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + } pa_sc_aa_config_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_config_t f; +} pa_sc_aa_config_u; + + +/* + * PA_SC_AA_MASK struct + */ + +#define PA_SC_AA_MASK_AA_MASK_SIZE 16 + +#define PA_SC_AA_MASK_AA_MASK_SHIFT 0 + +#define PA_SC_AA_MASK_AA_MASK_MASK 0x0000ffff + +#define PA_SC_AA_MASK_MASK \ + (PA_SC_AA_MASK_AA_MASK_MASK) + +#define PA_SC_AA_MASK(aa_mask) \ + ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)) + +#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \ + ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT) + +#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \ + pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + unsigned int : 16; + } pa_sc_aa_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int : 16; + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + } pa_sc_aa_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_mask_t f; +} pa_sc_aa_mask_u; + + +/* + * PA_SC_LINE_STIPPLE struct + */ + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000 + +#define PA_SC_LINE_STIPPLE_MASK \ + (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \ + PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \ + PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \ + PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) + +#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \ + ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \ + (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \ + (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \ + (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)) + +#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int : 4; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int : 1; + } pa_sc_line_stipple_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int : 1; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int : 4; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + } pa_sc_line_stipple_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_t f; +} pa_sc_line_stipple_u; + + +/* + * PA_SC_LINE_CNTL struct + */ + +#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1 + +#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10 + +#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200 +#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400 + +#define PA_SC_LINE_CNTL_MASK \ + (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \ + PA_SC_LINE_CNTL_LAST_PIXEL_MASK) + +#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \ + ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \ + (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \ + (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \ + (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)) + +#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int : 21; + } pa_sc_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int : 21; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + } pa_sc_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_cntl_t f; +} pa_sc_line_cntl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_TL struct + */ + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000 + +#define PA_SC_WINDOW_SCISSOR_TL_MASK \ + (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) + +#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \ + ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \ + (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + unsigned int : 2; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + } pa_sc_window_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 2; + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + } pa_sc_window_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_tl_t f; +} pa_sc_window_scissor_tl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_BR struct + */ + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000 + +#define PA_SC_WINDOW_SCISSOR_BR_MASK \ + (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \ + PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + } pa_sc_window_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + } pa_sc_window_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_br_t f; +} pa_sc_window_scissor_br_u; + + +/* + * PA_SC_SCREEN_SCISSOR_TL struct + */ + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_TL_MASK \ + (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \ + PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \ + ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + } pa_sc_screen_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_tl_t f; +} pa_sc_screen_scissor_tl_u; + + +/* + * PA_SC_SCREEN_SCISSOR_BR struct + */ + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_BR_MASK \ + (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \ + PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + } pa_sc_screen_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_br_t f; +} pa_sc_screen_scissor_br_u; + + +/* + * PA_SC_VIZ_QUERY struct + */ + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080 + +#define PA_SC_VIZ_QUERY_MASK \ + (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \ + PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \ + PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) + +#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \ + ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \ + (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \ + (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)) + +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int : 1; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 24; + } pa_sc_viz_query_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int : 24; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 1; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + } pa_sc_viz_query_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_t f; +} pa_sc_viz_query_u; + + +/* + * PA_SC_VIZ_QUERY_STATUS struct + */ + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff + +#define PA_SC_VIZ_QUERY_STATUS_MASK \ + (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) + +#define PA_SC_VIZ_QUERY_STATUS(status_bits) \ + ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)) + +#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \ + ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \ + pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_status_t f; +} pa_sc_viz_query_status_u; + + +/* + * PA_SC_LINE_STIPPLE_STATE struct + */ + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00 + +#define PA_SC_LINE_STIPPLE_STATE_MASK \ + (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \ + PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) + +#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \ + ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \ + (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)) + +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + unsigned int : 4; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 16; + } pa_sc_line_stipple_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int : 16; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 4; + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + } pa_sc_line_stipple_state_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_state_t f; +} pa_sc_line_stipple_state_u; + + +/* + * PA_SC_PERFCOUNTER0_SELECT struct + */ + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SC_PERFCOUNTER0_SELECT_MASK \ + (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \ + ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \ + pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_sc_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_sc_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_select_t f; +} pa_sc_perfcounter0_select_u; + + +/* + * PA_SC_PERFCOUNTER0_LOW struct + */ + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SC_PERFCOUNTER0_LOW_MASK \ + (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \ + ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \ + pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_low_t f; +} pa_sc_perfcounter0_low_u; + + +/* + * PA_SC_PERFCOUNTER0_HI struct + */ + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SC_PERFCOUNTER0_HI_MASK \ + (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \ + ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \ + pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_sc_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_hi_t f; +} pa_sc_perfcounter0_hi_u; + + +/* + * PA_CL_CNTL_STATUS struct + */ + +#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1 + +#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31 + +#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000 + +#define PA_CL_CNTL_STATUS_MASK \ + (PA_CL_CNTL_STATUS_CL_BUSY_MASK) + +#define PA_CL_CNTL_STATUS(cl_busy) \ + ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)) + +#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \ + ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \ + pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int : 31; + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + } pa_cl_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + unsigned int : 31; + } pa_cl_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_cntl_status_t f; +} pa_cl_cntl_status_u; + + +/* + * PA_SU_CNTL_STATUS struct + */ + +#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1 + +#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31 + +#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000 + +#define PA_SU_CNTL_STATUS_MASK \ + (PA_SU_CNTL_STATUS_SU_BUSY_MASK) + +#define PA_SU_CNTL_STATUS(su_busy) \ + ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)) + +#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \ + ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \ + pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int : 31; + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + } pa_su_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + unsigned int : 31; + } pa_su_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_cntl_status_t f; +} pa_su_cntl_status_u; + + +/* + * PA_SC_CNTL_STATUS struct + */ + +#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1 + +#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31 + +#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000 + +#define PA_SC_CNTL_STATUS_MASK \ + (PA_SC_CNTL_STATUS_SC_BUSY_MASK) + +#define PA_SC_CNTL_STATUS(sc_busy) \ + ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)) + +#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \ + ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \ + pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int : 31; + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + } pa_sc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + unsigned int : 31; + } pa_sc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_cntl_status_t f; +} pa_sc_cntl_status_u; + + +/* + * PA_SU_DEBUG_CNTL struct + */ + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f + +#define PA_SU_DEBUG_CNTL_MASK \ + (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) + +#define PA_SU_DEBUG_CNTL(su_debug_indx) \ + ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)) + +#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \ + ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \ + pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_su_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int : 27; + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + } pa_su_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_cntl_t f; +} pa_su_debug_cntl_u; + + +/* + * PA_SU_DEBUG_DATA struct + */ + +#define PA_SU_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SU_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SU_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SU_DEBUG_DATA_MASK \ + (PA_SU_DEBUG_DATA_DATA_MASK) + +#define PA_SU_DEBUG_DATA(data) \ + ((data << PA_SU_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \ + ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT) + +#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \ + pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_data_t f; +} pa_su_debug_data_u; + + +/* + * CLIPPER_DEBUG_REG00 struct + */ + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000 + +#define CLIPPER_DEBUG_REG00_MASK \ + (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \ + ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \ + (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \ + (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \ + (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \ + (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \ + (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \ + (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \ + (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \ + (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \ + (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \ + (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \ + (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \ + (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \ + (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \ + (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \ + (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \ + (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \ + (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \ + (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \ + (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + } clipper_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + } clipper_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg00_t f; +} clipper_debug_reg00_u; + + +/* + * CLIPPER_DEBUG_REG01 struct + */ + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000 + +#define CLIPPER_DEBUG_REG01_MASK \ + (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \ + CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \ + ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \ + (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \ + (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \ + (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \ + (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \ + (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \ + (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + } clipper_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + } clipper_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg01_t f; +} clipper_debug_reg01_u; + + +/* + * CLIPPER_DEBUG_REG02 struct + */ + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 + +#define CLIPPER_DEBUG_REG02_MASK \ + (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \ + CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) + +#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \ + ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \ + (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)) + +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + } clipper_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + } clipper_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg02_t f; +} clipper_debug_reg02_u; + + +/* + * CLIPPER_DEBUG_REG03 struct + */ + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG03_MASK \ + (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \ + ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + } clipper_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg03_t f; +} clipper_debug_reg03_u; + + +/* + * CLIPPER_DEBUG_REG04 struct + */ + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00 + +#define CLIPPER_DEBUG_REG04_MASK \ + (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \ + ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + } clipper_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg04_t f; +} clipper_debug_reg04_u; + + +/* + * CLIPPER_DEBUG_REG05 struct + */ + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000 + +#define CLIPPER_DEBUG_REG05_MASK \ + (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \ + ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \ + (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + } clipper_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg05_t f; +} clipper_debug_reg05_u; + + +/* + * CLIPPER_DEBUG_REG09 struct + */ + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000 +#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000 + +#define CLIPPER_DEBUG_REG09_MASK \ + (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \ + CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) + +#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \ + ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \ + (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \ + (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \ + (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \ + (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \ + (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \ + (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \ + (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \ + (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \ + (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \ + (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)) + +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + } clipper_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + } clipper_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg09_t f; +} clipper_debug_reg09_u; + + +/* + * CLIPPER_DEBUG_REG10 struct + */ + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG10_MASK \ + (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) + +#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \ + ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \ + (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \ + (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \ + (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \ + (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)) + +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + } clipper_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + } clipper_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg10_t f; +} clipper_debug_reg10_u; + + +/* + * CLIPPER_DEBUG_REG11 struct + */ + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0 + +#define CLIPPER_DEBUG_REG11_MASK \ + (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \ + CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \ + ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + } clipper_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + } clipper_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg11_t f; +} clipper_debug_reg11_u; + + +/* + * CLIPPER_DEBUG_REG12 struct + */ + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000 + +#define CLIPPER_DEBUG_REG12_MASK \ + (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \ + CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \ + ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \ + (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \ + (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \ + (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \ + (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \ + (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + } clipper_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg12_t f; +} clipper_debug_reg12_u; + + +/* + * CLIPPER_DEBUG_REG13 struct + */ + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000 +#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000 + +#define CLIPPER_DEBUG_REG13_MASK \ + (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \ + CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \ + ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \ + (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \ + (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \ + (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \ + (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \ + (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + } clipper_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg13_t f; +} clipper_debug_reg13_u; + + +/* + * SXIFCCG_DEBUG_REG0 struct + */ + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4 +#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3 +#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0 +#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380 +#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000 + +#define SXIFCCG_DEBUG_REG0_MASK \ + (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \ + SXIFCCG_DEBUG_REG0_position_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG0_point_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) + +#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \ + ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \ + (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \ + (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \ + (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \ + (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \ + (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \ + (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \ + (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)) + +#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + } sxifccg_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + } sxifccg_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg0_t f; +} sxifccg_debug_reg0_u; + + +/* + * SXIFCCG_DEBUG_REG1 struct + */ + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4 +#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c +#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000 +#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000 +#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000 + +#define SXIFCCG_DEBUG_REG1_MASK \ + (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \ + SXIFCCG_DEBUG_REG1_available_positions_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \ + SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \ + SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG1_aux_sel_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \ + SXIFCCG_DEBUG_REG1_param_cache_base_MASK) + +#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \ + ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \ + (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \ + (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \ + (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \ + (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \ + (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \ + (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \ + (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)) + +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + } sxifccg_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + } sxifccg_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg1_t f; +} sxifccg_debug_reg1_u; + + +/* + * SXIFCCG_DEBUG_REG2 struct + */ + +#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3 + +#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29 + +#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002 +#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8 +#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000 + +#define SXIFCCG_DEBUG_REG2_MASK \ + (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG2_sx_aux_MASK | \ + SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) + +#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \ + ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \ + (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \ + (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \ + (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \ + (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \ + (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \ + (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \ + (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \ + (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \ + (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)) + +#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + } sxifccg_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + } sxifccg_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg2_t f; +} sxifccg_debug_reg2_u; + + +/* + * SXIFCCG_DEBUG_REG3 struct + */ + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4 +#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8 +#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010 +#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00 +#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000 + +#define SXIFCCG_DEBUG_REG3_MASK \ + (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG3_available_positions_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG3_current_state_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) + +#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \ + ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \ + (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \ + (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \ + (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \ + (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \ + (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \ + (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \ + (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)) + +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + } sxifccg_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + } sxifccg_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg3_t f; +} sxifccg_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG0 struct + */ + +#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5 +#define SETUP_DEBUG_REG0_pmode_state_SIZE 6 +#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1 +#define SETUP_DEBUG_REG0_geom_enable_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1 +#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1 +#define SETUP_DEBUG_REG0_geom_busy_SIZE 1 + +#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0 +#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5 +#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11 +#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13 +#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14 +#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15 +#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16 +#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17 + +#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f +#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0 +#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800 +#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000 +#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000 +#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000 +#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000 +#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000 + +#define SETUP_DEBUG_REG0_MASK \ + (SETUP_DEBUG_REG0_su_cntl_state_MASK | \ + SETUP_DEBUG_REG0_pmode_state_MASK | \ + SETUP_DEBUG_REG0_ge_stallb_MASK | \ + SETUP_DEBUG_REG0_geom_enable_MASK | \ + SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \ + SETUP_DEBUG_REG0_su_clip_rtr_MASK | \ + SETUP_DEBUG_REG0_pfifo_busy_MASK | \ + SETUP_DEBUG_REG0_su_cntl_busy_MASK | \ + SETUP_DEBUG_REG0_geom_busy_MASK) + +#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \ + ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \ + (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \ + (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \ + (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \ + (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \ + (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \ + (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \ + (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \ + (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)) + +#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int : 14; + } setup_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int : 14; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + } setup_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg0_t f; +} setup_debug_reg0_u; + + +/* + * SETUP_DEBUG_REG1 struct + */ + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG1_MASK \ + (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \ + SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) + +#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \ + ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \ + (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + } setup_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg1_t f; +} setup_debug_reg1_u; + + +/* + * SETUP_DEBUG_REG2 struct + */ + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG2_MASK \ + (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \ + SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) + +#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \ + ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \ + (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + } setup_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg2_t f; +} setup_debug_reg2_u; + + +/* + * SETUP_DEBUG_REG3 struct + */ + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG3_MASK \ + (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \ + SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) + +#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \ + ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \ + (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + } setup_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg3_t f; +} setup_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG4 struct + */ + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11 +#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1 +#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3 +#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3 +#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2 +#define SETUP_DEBUG_REG4_type_gated_SIZE 3 +#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_event_gated_SIZE 1 +#define SETUP_DEBUG_REG4_eop_gated_SIZE 1 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0 +#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11 +#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12 +#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13 +#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17 +#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21 +#define SETUP_DEBUG_REG4_type_gated_SHIFT 23 +#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27 +#define SETUP_DEBUG_REG4_event_gated_SHIFT 28 +#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800 +#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000 +#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000 +#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000 +#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000 +#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000 +#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000 +#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000 +#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000 +#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000 + +#define SETUP_DEBUG_REG4_MASK \ + (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \ + SETUP_DEBUG_REG4_null_prim_gated_MASK | \ + SETUP_DEBUG_REG4_backfacing_gated_MASK | \ + SETUP_DEBUG_REG4_st_indx_gated_MASK | \ + SETUP_DEBUG_REG4_clipped_gated_MASK | \ + SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \ + SETUP_DEBUG_REG4_xmajor_gated_MASK | \ + SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \ + SETUP_DEBUG_REG4_type_gated_MASK | \ + SETUP_DEBUG_REG4_fpov_gated_MASK | \ + SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \ + SETUP_DEBUG_REG4_event_gated_MASK | \ + SETUP_DEBUG_REG4_eop_gated_MASK) + +#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \ + ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \ + (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \ + (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \ + (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \ + (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \ + (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \ + (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \ + (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \ + (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \ + (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \ + (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \ + (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \ + (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)) + +#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int : 2; + } setup_debug_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int : 2; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + } setup_debug_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg4_t f; +} setup_debug_reg4_u; + + +/* + * SETUP_DEBUG_REG5 struct + */ + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2 +#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22 +#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000 +#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000 + +#define SETUP_DEBUG_REG5_MASK \ + (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \ + SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \ + SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \ + SETUP_DEBUG_REG5_event_id_gated_MASK) + +#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \ + ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \ + (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \ + (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \ + (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)) + +#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int : 3; + } setup_debug_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int : 3; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + } setup_debug_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg5_t f; +} setup_debug_reg5_u; + + +/* + * PA_SC_DEBUG_CNTL struct + */ + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f + +#define PA_SC_DEBUG_CNTL_MASK \ + (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) + +#define PA_SC_DEBUG_CNTL(sc_debug_indx) \ + ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)) + +#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \ + ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \ + pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_sc_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int : 27; + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + } pa_sc_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_cntl_t f; +} pa_sc_debug_cntl_u; + + +/* + * PA_SC_DEBUG_DATA struct + */ + +#define PA_SC_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SC_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SC_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SC_DEBUG_DATA_MASK \ + (PA_SC_DEBUG_DATA_DATA_MASK) + +#define PA_SC_DEBUG_DATA(data) \ + ((data << PA_SC_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \ + ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT) + +#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \ + pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_data_t f; +} pa_sc_debug_data_u; + + +/* + * SC_DEBUG_0 struct + */ + +#define SC_DEBUG_0_pa_freeze_b1_SIZE 1 +#define SC_DEBUG_0_pa_sc_valid_SIZE 1 +#define SC_DEBUG_0_pa_sc_phase_SIZE 3 +#define SC_DEBUG_0_cntx_cnt_SIZE 7 +#define SC_DEBUG_0_decr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_incr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_trigger_SIZE 1 + +#define SC_DEBUG_0_pa_freeze_b1_SHIFT 0 +#define SC_DEBUG_0_pa_sc_valid_SHIFT 1 +#define SC_DEBUG_0_pa_sc_phase_SHIFT 2 +#define SC_DEBUG_0_cntx_cnt_SHIFT 5 +#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12 +#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13 +#define SC_DEBUG_0_trigger_SHIFT 31 + +#define SC_DEBUG_0_pa_freeze_b1_MASK 0x00000001 +#define SC_DEBUG_0_pa_sc_valid_MASK 0x00000002 +#define SC_DEBUG_0_pa_sc_phase_MASK 0x0000001c +#define SC_DEBUG_0_cntx_cnt_MASK 0x00000fe0 +#define SC_DEBUG_0_decr_cntx_cnt_MASK 0x00001000 +#define SC_DEBUG_0_incr_cntx_cnt_MASK 0x00002000 +#define SC_DEBUG_0_trigger_MASK 0x80000000 + +#define SC_DEBUG_0_MASK \ + (SC_DEBUG_0_pa_freeze_b1_MASK | \ + SC_DEBUG_0_pa_sc_valid_MASK | \ + SC_DEBUG_0_pa_sc_phase_MASK | \ + SC_DEBUG_0_cntx_cnt_MASK | \ + SC_DEBUG_0_decr_cntx_cnt_MASK | \ + SC_DEBUG_0_incr_cntx_cnt_MASK | \ + SC_DEBUG_0_trigger_MASK) + +#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \ + ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \ + (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \ + (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \ + (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \ + (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \ + (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \ + (trigger << SC_DEBUG_0_trigger_SHIFT)) + +#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_trigger(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT) + +#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int : 17; + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + } sc_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + unsigned int : 17; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + } sc_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_0_t f; +} sc_debug_0_u; + + +/* + * SC_DEBUG_1 struct + */ + +#define SC_DEBUG_1_em_state_SIZE 3 +#define SC_DEBUG_1_em1_data_ready_SIZE 1 +#define SC_DEBUG_1_em2_data_ready_SIZE 1 +#define SC_DEBUG_1_move_em1_to_em2_SIZE 1 +#define SC_DEBUG_1_ef_data_ready_SIZE 1 +#define SC_DEBUG_1_ef_state_SIZE 2 +#define SC_DEBUG_1_pipe_valid_SIZE 1 +#define SC_DEBUG_1_trigger_SIZE 1 + +#define SC_DEBUG_1_em_state_SHIFT 0 +#define SC_DEBUG_1_em1_data_ready_SHIFT 3 +#define SC_DEBUG_1_em2_data_ready_SHIFT 4 +#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5 +#define SC_DEBUG_1_ef_data_ready_SHIFT 6 +#define SC_DEBUG_1_ef_state_SHIFT 7 +#define SC_DEBUG_1_pipe_valid_SHIFT 9 +#define SC_DEBUG_1_trigger_SHIFT 31 + +#define SC_DEBUG_1_em_state_MASK 0x00000007 +#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008 +#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010 +#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020 +#define SC_DEBUG_1_ef_data_ready_MASK 0x00000040 +#define SC_DEBUG_1_ef_state_MASK 0x00000180 +#define SC_DEBUG_1_pipe_valid_MASK 0x00000200 +#define SC_DEBUG_1_trigger_MASK 0x80000000 + +#define SC_DEBUG_1_MASK \ + (SC_DEBUG_1_em_state_MASK | \ + SC_DEBUG_1_em1_data_ready_MASK | \ + SC_DEBUG_1_em2_data_ready_MASK | \ + SC_DEBUG_1_move_em1_to_em2_MASK | \ + SC_DEBUG_1_ef_data_ready_MASK | \ + SC_DEBUG_1_ef_state_MASK | \ + SC_DEBUG_1_pipe_valid_MASK | \ + SC_DEBUG_1_trigger_MASK) + +#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \ + ((em_state << SC_DEBUG_1_em_state_SHIFT) | \ + (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \ + (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \ + (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \ + (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \ + (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \ + (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \ + (trigger << SC_DEBUG_1_trigger_SHIFT)) + +#define SC_DEBUG_1_GET_em_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_GET_trigger(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT) + +#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int : 21; + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + } sc_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + unsigned int : 21; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + } sc_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_1_t f; +} sc_debug_1_u; + + +/* + * SC_DEBUG_2 struct + */ + +#define SC_DEBUG_2_rc_rtr_dly_SIZE 1 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1 +#define SC_DEBUG_2_pipe_freeze_b_SIZE 1 +#define SC_DEBUG_2_prim_rts_SIZE 1 +#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1 +#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1 +#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1 +#define SC_DEBUG_2_stage0_rts_SIZE 1 +#define SC_DEBUG_2_phase_rts_dly_SIZE 1 +#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1 +#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1 +#define SC_DEBUG_2_event_id_s1_SIZE 5 +#define SC_DEBUG_2_event_s1_SIZE 1 +#define SC_DEBUG_2_trigger_SIZE 1 + +#define SC_DEBUG_2_rc_rtr_dly_SHIFT 0 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1 +#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3 +#define SC_DEBUG_2_prim_rts_SHIFT 4 +#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5 +#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6 +#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7 +#define SC_DEBUG_2_stage0_rts_SHIFT 8 +#define SC_DEBUG_2_phase_rts_dly_SHIFT 9 +#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15 +#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16 +#define SC_DEBUG_2_event_id_s1_SHIFT 17 +#define SC_DEBUG_2_event_s1_SHIFT 22 +#define SC_DEBUG_2_trigger_SHIFT 31 + +#define SC_DEBUG_2_rc_rtr_dly_MASK 0x00000001 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002 +#define SC_DEBUG_2_pipe_freeze_b_MASK 0x00000008 +#define SC_DEBUG_2_prim_rts_MASK 0x00000010 +#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020 +#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040 +#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080 +#define SC_DEBUG_2_stage0_rts_MASK 0x00000100 +#define SC_DEBUG_2_phase_rts_dly_MASK 0x00000200 +#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000 +#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000 +#define SC_DEBUG_2_event_id_s1_MASK 0x003e0000 +#define SC_DEBUG_2_event_s1_MASK 0x00400000 +#define SC_DEBUG_2_trigger_MASK 0x80000000 + +#define SC_DEBUG_2_MASK \ + (SC_DEBUG_2_rc_rtr_dly_MASK | \ + SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \ + SC_DEBUG_2_pipe_freeze_b_MASK | \ + SC_DEBUG_2_prim_rts_MASK | \ + SC_DEBUG_2_next_prim_rts_dly_MASK | \ + SC_DEBUG_2_next_prim_rtr_dly_MASK | \ + SC_DEBUG_2_pre_stage1_rts_d1_MASK | \ + SC_DEBUG_2_stage0_rts_MASK | \ + SC_DEBUG_2_phase_rts_dly_MASK | \ + SC_DEBUG_2_end_of_prim_s1_dly_MASK | \ + SC_DEBUG_2_pass_empty_prim_s1_MASK | \ + SC_DEBUG_2_event_id_s1_MASK | \ + SC_DEBUG_2_event_s1_MASK | \ + SC_DEBUG_2_trigger_MASK) + +#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \ + ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \ + (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \ + (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \ + (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \ + (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \ + (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \ + (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \ + (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \ + (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \ + (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \ + (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \ + (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \ + (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \ + (trigger << SC_DEBUG_2_trigger_SHIFT)) + +#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_GET_trigger(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT) + +#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int : 1; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int : 8; + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + } sc_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + unsigned int : 8; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int : 5; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + } sc_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_2_t f; +} sc_debug_2_u; + + +/* + * SC_DEBUG_3 struct + */ + +#define SC_DEBUG_3_x_curr_s1_SIZE 11 +#define SC_DEBUG_3_y_curr_s1_SIZE 11 +#define SC_DEBUG_3_trigger_SIZE 1 + +#define SC_DEBUG_3_x_curr_s1_SHIFT 0 +#define SC_DEBUG_3_y_curr_s1_SHIFT 11 +#define SC_DEBUG_3_trigger_SHIFT 31 + +#define SC_DEBUG_3_x_curr_s1_MASK 0x000007ff +#define SC_DEBUG_3_y_curr_s1_MASK 0x003ff800 +#define SC_DEBUG_3_trigger_MASK 0x80000000 + +#define SC_DEBUG_3_MASK \ + (SC_DEBUG_3_x_curr_s1_MASK | \ + SC_DEBUG_3_y_curr_s1_MASK | \ + SC_DEBUG_3_trigger_MASK) + +#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \ + ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \ + (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \ + (trigger << SC_DEBUG_3_trigger_SHIFT)) + +#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_trigger(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT) + +#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int : 9; + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + } sc_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + unsigned int : 9; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + } sc_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_3_t f; +} sc_debug_3_u; + + +/* + * SC_DEBUG_4 struct + */ + +#define SC_DEBUG_4_y_end_s1_SIZE 14 +#define SC_DEBUG_4_y_start_s1_SIZE 14 +#define SC_DEBUG_4_y_dir_s1_SIZE 1 +#define SC_DEBUG_4_trigger_SIZE 1 + +#define SC_DEBUG_4_y_end_s1_SHIFT 0 +#define SC_DEBUG_4_y_start_s1_SHIFT 14 +#define SC_DEBUG_4_y_dir_s1_SHIFT 28 +#define SC_DEBUG_4_trigger_SHIFT 31 + +#define SC_DEBUG_4_y_end_s1_MASK 0x00003fff +#define SC_DEBUG_4_y_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_4_y_dir_s1_MASK 0x10000000 +#define SC_DEBUG_4_trigger_MASK 0x80000000 + +#define SC_DEBUG_4_MASK \ + (SC_DEBUG_4_y_end_s1_MASK | \ + SC_DEBUG_4_y_start_s1_MASK | \ + SC_DEBUG_4_y_dir_s1_MASK | \ + SC_DEBUG_4_trigger_MASK) + +#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \ + ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \ + (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \ + (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_4_trigger_SHIFT)) + +#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_GET_trigger(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT) + +#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + } sc_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + unsigned int : 2; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + } sc_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_4_t f; +} sc_debug_4_u; + + +/* + * SC_DEBUG_5 struct + */ + +#define SC_DEBUG_5_x_end_s1_SIZE 14 +#define SC_DEBUG_5_x_start_s1_SIZE 14 +#define SC_DEBUG_5_x_dir_s1_SIZE 1 +#define SC_DEBUG_5_trigger_SIZE 1 + +#define SC_DEBUG_5_x_end_s1_SHIFT 0 +#define SC_DEBUG_5_x_start_s1_SHIFT 14 +#define SC_DEBUG_5_x_dir_s1_SHIFT 28 +#define SC_DEBUG_5_trigger_SHIFT 31 + +#define SC_DEBUG_5_x_end_s1_MASK 0x00003fff +#define SC_DEBUG_5_x_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_5_x_dir_s1_MASK 0x10000000 +#define SC_DEBUG_5_trigger_MASK 0x80000000 + +#define SC_DEBUG_5_MASK \ + (SC_DEBUG_5_x_end_s1_MASK | \ + SC_DEBUG_5_x_start_s1_MASK | \ + SC_DEBUG_5_x_dir_s1_MASK | \ + SC_DEBUG_5_trigger_MASK) + +#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \ + ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \ + (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \ + (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_5_trigger_SHIFT)) + +#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_GET_trigger(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT) + +#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + } sc_debug_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + unsigned int : 2; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + } sc_debug_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_5_t f; +} sc_debug_5_u; + + +/* + * SC_DEBUG_6 struct + */ + +#define SC_DEBUG_6_z_ff_empty_SIZE 1 +#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1 +#define SC_DEBUG_6_xy_ff_empty_SIZE 1 +#define SC_DEBUG_6_event_flag_SIZE 1 +#define SC_DEBUG_6_z_mask_needed_SIZE 1 +#define SC_DEBUG_6_state_SIZE 3 +#define SC_DEBUG_6_state_delayed_SIZE 3 +#define SC_DEBUG_6_data_valid_SIZE 1 +#define SC_DEBUG_6_data_valid_d_SIZE 1 +#define SC_DEBUG_6_tilex_delayed_SIZE 9 +#define SC_DEBUG_6_tiley_delayed_SIZE 9 +#define SC_DEBUG_6_trigger_SIZE 1 + +#define SC_DEBUG_6_z_ff_empty_SHIFT 0 +#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1 +#define SC_DEBUG_6_xy_ff_empty_SHIFT 2 +#define SC_DEBUG_6_event_flag_SHIFT 3 +#define SC_DEBUG_6_z_mask_needed_SHIFT 4 +#define SC_DEBUG_6_state_SHIFT 5 +#define SC_DEBUG_6_state_delayed_SHIFT 8 +#define SC_DEBUG_6_data_valid_SHIFT 11 +#define SC_DEBUG_6_data_valid_d_SHIFT 12 +#define SC_DEBUG_6_tilex_delayed_SHIFT 13 +#define SC_DEBUG_6_tiley_delayed_SHIFT 22 +#define SC_DEBUG_6_trigger_SHIFT 31 + +#define SC_DEBUG_6_z_ff_empty_MASK 0x00000001 +#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002 +#define SC_DEBUG_6_xy_ff_empty_MASK 0x00000004 +#define SC_DEBUG_6_event_flag_MASK 0x00000008 +#define SC_DEBUG_6_z_mask_needed_MASK 0x00000010 +#define SC_DEBUG_6_state_MASK 0x000000e0 +#define SC_DEBUG_6_state_delayed_MASK 0x00000700 +#define SC_DEBUG_6_data_valid_MASK 0x00000800 +#define SC_DEBUG_6_data_valid_d_MASK 0x00001000 +#define SC_DEBUG_6_tilex_delayed_MASK 0x003fe000 +#define SC_DEBUG_6_tiley_delayed_MASK 0x7fc00000 +#define SC_DEBUG_6_trigger_MASK 0x80000000 + +#define SC_DEBUG_6_MASK \ + (SC_DEBUG_6_z_ff_empty_MASK | \ + SC_DEBUG_6_qmcntl_ff_empty_MASK | \ + SC_DEBUG_6_xy_ff_empty_MASK | \ + SC_DEBUG_6_event_flag_MASK | \ + SC_DEBUG_6_z_mask_needed_MASK | \ + SC_DEBUG_6_state_MASK | \ + SC_DEBUG_6_state_delayed_MASK | \ + SC_DEBUG_6_data_valid_MASK | \ + SC_DEBUG_6_data_valid_d_MASK | \ + SC_DEBUG_6_tilex_delayed_MASK | \ + SC_DEBUG_6_tiley_delayed_MASK | \ + SC_DEBUG_6_trigger_MASK) + +#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \ + ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \ + (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \ + (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \ + (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \ + (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \ + (state << SC_DEBUG_6_state_SHIFT) | \ + (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \ + (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \ + (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \ + (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \ + (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \ + (trigger << SC_DEBUG_6_trigger_SHIFT)) + +#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_GET_state(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_GET_trigger(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT) + +#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + } sc_debug_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + } sc_debug_6_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_6_t f; +} sc_debug_6_u; + + +/* + * SC_DEBUG_7 struct + */ + +#define SC_DEBUG_7_event_flag_SIZE 1 +#define SC_DEBUG_7_deallocate_SIZE 3 +#define SC_DEBUG_7_fposition_SIZE 1 +#define SC_DEBUG_7_sr_prim_we_SIZE 1 +#define SC_DEBUG_7_last_tile_SIZE 1 +#define SC_DEBUG_7_tile_ff_we_SIZE 1 +#define SC_DEBUG_7_qs_data_valid_SIZE 1 +#define SC_DEBUG_7_qs_q0_y_SIZE 2 +#define SC_DEBUG_7_qs_q0_x_SIZE 2 +#define SC_DEBUG_7_qs_q0_valid_SIZE 1 +#define SC_DEBUG_7_prim_ff_we_SIZE 1 +#define SC_DEBUG_7_tile_ff_re_SIZE 1 +#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_7_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_7_new_prim_SIZE 1 +#define SC_DEBUG_7_load_new_tile_data_SIZE 1 +#define SC_DEBUG_7_state_SIZE 2 +#define SC_DEBUG_7_fifos_ready_SIZE 1 +#define SC_DEBUG_7_trigger_SIZE 1 + +#define SC_DEBUG_7_event_flag_SHIFT 0 +#define SC_DEBUG_7_deallocate_SHIFT 1 +#define SC_DEBUG_7_fposition_SHIFT 4 +#define SC_DEBUG_7_sr_prim_we_SHIFT 5 +#define SC_DEBUG_7_last_tile_SHIFT 6 +#define SC_DEBUG_7_tile_ff_we_SHIFT 7 +#define SC_DEBUG_7_qs_data_valid_SHIFT 8 +#define SC_DEBUG_7_qs_q0_y_SHIFT 9 +#define SC_DEBUG_7_qs_q0_x_SHIFT 11 +#define SC_DEBUG_7_qs_q0_valid_SHIFT 13 +#define SC_DEBUG_7_prim_ff_we_SHIFT 14 +#define SC_DEBUG_7_tile_ff_re_SHIFT 15 +#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16 +#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17 +#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18 +#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19 +#define SC_DEBUG_7_new_prim_SHIFT 20 +#define SC_DEBUG_7_load_new_tile_data_SHIFT 21 +#define SC_DEBUG_7_state_SHIFT 22 +#define SC_DEBUG_7_fifos_ready_SHIFT 24 +#define SC_DEBUG_7_trigger_SHIFT 31 + +#define SC_DEBUG_7_event_flag_MASK 0x00000001 +#define SC_DEBUG_7_deallocate_MASK 0x0000000e +#define SC_DEBUG_7_fposition_MASK 0x00000010 +#define SC_DEBUG_7_sr_prim_we_MASK 0x00000020 +#define SC_DEBUG_7_last_tile_MASK 0x00000040 +#define SC_DEBUG_7_tile_ff_we_MASK 0x00000080 +#define SC_DEBUG_7_qs_data_valid_MASK 0x00000100 +#define SC_DEBUG_7_qs_q0_y_MASK 0x00000600 +#define SC_DEBUG_7_qs_q0_x_MASK 0x00001800 +#define SC_DEBUG_7_qs_q0_valid_MASK 0x00002000 +#define SC_DEBUG_7_prim_ff_we_MASK 0x00004000 +#define SC_DEBUG_7_tile_ff_re_MASK 0x00008000 +#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000 +#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000 +#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000 +#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000 +#define SC_DEBUG_7_new_prim_MASK 0x00100000 +#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000 +#define SC_DEBUG_7_state_MASK 0x00c00000 +#define SC_DEBUG_7_fifos_ready_MASK 0x01000000 +#define SC_DEBUG_7_trigger_MASK 0x80000000 + +#define SC_DEBUG_7_MASK \ + (SC_DEBUG_7_event_flag_MASK | \ + SC_DEBUG_7_deallocate_MASK | \ + SC_DEBUG_7_fposition_MASK | \ + SC_DEBUG_7_sr_prim_we_MASK | \ + SC_DEBUG_7_last_tile_MASK | \ + SC_DEBUG_7_tile_ff_we_MASK | \ + SC_DEBUG_7_qs_data_valid_MASK | \ + SC_DEBUG_7_qs_q0_y_MASK | \ + SC_DEBUG_7_qs_q0_x_MASK | \ + SC_DEBUG_7_qs_q0_valid_MASK | \ + SC_DEBUG_7_prim_ff_we_MASK | \ + SC_DEBUG_7_tile_ff_re_MASK | \ + SC_DEBUG_7_fw_prim_data_valid_MASK | \ + SC_DEBUG_7_last_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_prim_MASK | \ + SC_DEBUG_7_new_prim_MASK | \ + SC_DEBUG_7_load_new_tile_data_MASK | \ + SC_DEBUG_7_state_MASK | \ + SC_DEBUG_7_fifos_ready_MASK | \ + SC_DEBUG_7_trigger_MASK) + +#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \ + ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \ + (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \ + (fposition << SC_DEBUG_7_fposition_SHIFT) | \ + (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \ + (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \ + (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \ + (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \ + (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \ + (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \ + (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \ + (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \ + (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \ + (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \ + (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \ + (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \ + (state << SC_DEBUG_7_state_SHIFT) | \ + (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \ + (trigger << SC_DEBUG_7_trigger_SHIFT)) + +#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_GET_fposition(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_GET_state(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_GET_trigger(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT) + +#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int : 6; + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + } sc_debug_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + unsigned int : 6; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + } sc_debug_7_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_7_t f; +} sc_debug_7_u; + + +/* + * SC_DEBUG_8 struct + */ + +#define SC_DEBUG_8_sample_last_SIZE 1 +#define SC_DEBUG_8_sample_mask_SIZE 4 +#define SC_DEBUG_8_sample_y_SIZE 2 +#define SC_DEBUG_8_sample_x_SIZE 2 +#define SC_DEBUG_8_sample_send_SIZE 1 +#define SC_DEBUG_8_next_cycle_SIZE 2 +#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1 +#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1 +#define SC_DEBUG_8_num_samples_SIZE 2 +#define SC_DEBUG_8_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_8_last_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_sample_we_SIZE 1 +#define SC_DEBUG_8_fposition_SIZE 1 +#define SC_DEBUG_8_event_id_SIZE 5 +#define SC_DEBUG_8_event_flag_SIZE 1 +#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_8_trigger_SIZE 1 + +#define SC_DEBUG_8_sample_last_SHIFT 0 +#define SC_DEBUG_8_sample_mask_SHIFT 1 +#define SC_DEBUG_8_sample_y_SHIFT 5 +#define SC_DEBUG_8_sample_x_SHIFT 7 +#define SC_DEBUG_8_sample_send_SHIFT 9 +#define SC_DEBUG_8_next_cycle_SHIFT 10 +#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12 +#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13 +#define SC_DEBUG_8_num_samples_SHIFT 14 +#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16 +#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17 +#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18 +#define SC_DEBUG_8_sample_we_SHIFT 19 +#define SC_DEBUG_8_fposition_SHIFT 20 +#define SC_DEBUG_8_event_id_SHIFT 21 +#define SC_DEBUG_8_event_flag_SHIFT 26 +#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27 +#define SC_DEBUG_8_trigger_SHIFT 31 + +#define SC_DEBUG_8_sample_last_MASK 0x00000001 +#define SC_DEBUG_8_sample_mask_MASK 0x0000001e +#define SC_DEBUG_8_sample_y_MASK 0x00000060 +#define SC_DEBUG_8_sample_x_MASK 0x00000180 +#define SC_DEBUG_8_sample_send_MASK 0x00000200 +#define SC_DEBUG_8_next_cycle_MASK 0x00000c00 +#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000 +#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000 +#define SC_DEBUG_8_num_samples_MASK 0x0000c000 +#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000 +#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000 +#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000 +#define SC_DEBUG_8_sample_we_MASK 0x00080000 +#define SC_DEBUG_8_fposition_MASK 0x00100000 +#define SC_DEBUG_8_event_id_MASK 0x03e00000 +#define SC_DEBUG_8_event_flag_MASK 0x04000000 +#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000 +#define SC_DEBUG_8_trigger_MASK 0x80000000 + +#define SC_DEBUG_8_MASK \ + (SC_DEBUG_8_sample_last_MASK | \ + SC_DEBUG_8_sample_mask_MASK | \ + SC_DEBUG_8_sample_y_MASK | \ + SC_DEBUG_8_sample_x_MASK | \ + SC_DEBUG_8_sample_send_MASK | \ + SC_DEBUG_8_next_cycle_MASK | \ + SC_DEBUG_8_ez_sample_ff_full_MASK | \ + SC_DEBUG_8_rb_sc_samp_rtr_MASK | \ + SC_DEBUG_8_num_samples_MASK | \ + SC_DEBUG_8_last_quad_of_tile_MASK | \ + SC_DEBUG_8_last_quad_of_prim_MASK | \ + SC_DEBUG_8_first_quad_of_prim_MASK | \ + SC_DEBUG_8_sample_we_MASK | \ + SC_DEBUG_8_fposition_MASK | \ + SC_DEBUG_8_event_id_MASK | \ + SC_DEBUG_8_event_flag_MASK | \ + SC_DEBUG_8_fw_prim_data_valid_MASK | \ + SC_DEBUG_8_trigger_MASK) + +#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \ + ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \ + (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \ + (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \ + (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \ + (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \ + (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \ + (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \ + (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \ + (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \ + (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \ + (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \ + (fposition << SC_DEBUG_8_fposition_SHIFT) | \ + (event_id << SC_DEBUG_8_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \ + (trigger << SC_DEBUG_8_trigger_SHIFT)) + +#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_GET_fposition(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_GET_event_id(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_GET_trigger(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT) + +#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int : 3; + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + } sc_debug_8_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + unsigned int : 3; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + } sc_debug_8_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_8_t f; +} sc_debug_8_u; + + +/* + * SC_DEBUG_9 struct + */ + +#define SC_DEBUG_9_rb_sc_send_SIZE 1 +#define SC_DEBUG_9_rb_sc_ez_mask_SIZE 4 +#define SC_DEBUG_9_fifo_data_ready_SIZE 1 +#define SC_DEBUG_9_early_z_enable_SIZE 1 +#define SC_DEBUG_9_mask_state_SIZE 2 +#define SC_DEBUG_9_next_ez_mask_SIZE 16 +#define SC_DEBUG_9_mask_ready_SIZE 1 +#define SC_DEBUG_9_drop_sample_SIZE 1 +#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_9_trigger_SIZE 1 + +#define SC_DEBUG_9_rb_sc_send_SHIFT 0 +#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1 +#define SC_DEBUG_9_fifo_data_ready_SHIFT 5 +#define SC_DEBUG_9_early_z_enable_SHIFT 6 +#define SC_DEBUG_9_mask_state_SHIFT 7 +#define SC_DEBUG_9_next_ez_mask_SHIFT 9 +#define SC_DEBUG_9_mask_ready_SHIFT 25 +#define SC_DEBUG_9_drop_sample_SHIFT 26 +#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30 +#define SC_DEBUG_9_trigger_SHIFT 31 + +#define SC_DEBUG_9_rb_sc_send_MASK 0x00000001 +#define SC_DEBUG_9_rb_sc_ez_mask_MASK 0x0000001e +#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020 +#define SC_DEBUG_9_early_z_enable_MASK 0x00000040 +#define SC_DEBUG_9_mask_state_MASK 0x00000180 +#define SC_DEBUG_9_next_ez_mask_MASK 0x01fffe00 +#define SC_DEBUG_9_mask_ready_MASK 0x02000000 +#define SC_DEBUG_9_drop_sample_MASK 0x04000000 +#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000 +#define SC_DEBUG_9_trigger_MASK 0x80000000 + +#define SC_DEBUG_9_MASK \ + (SC_DEBUG_9_rb_sc_send_MASK | \ + SC_DEBUG_9_rb_sc_ez_mask_MASK | \ + SC_DEBUG_9_fifo_data_ready_MASK | \ + SC_DEBUG_9_early_z_enable_MASK | \ + SC_DEBUG_9_mask_state_MASK | \ + SC_DEBUG_9_next_ez_mask_MASK | \ + SC_DEBUG_9_mask_ready_MASK | \ + SC_DEBUG_9_drop_sample_MASK | \ + SC_DEBUG_9_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \ + SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_9_trigger_MASK) + +#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \ + ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \ + (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \ + (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \ + (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \ + (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \ + (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \ + (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \ + (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \ + (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \ + (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \ + (trigger << SC_DEBUG_9_trigger_SHIFT)) + +#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_GET_trigger(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT) + +#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + } sc_debug_9_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + } sc_debug_9_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_9_t f; +} sc_debug_9_u; + + +/* + * SC_DEBUG_10 struct + */ + +#define SC_DEBUG_10_combined_sample_mask_SIZE 16 +#define SC_DEBUG_10_trigger_SIZE 1 + +#define SC_DEBUG_10_combined_sample_mask_SHIFT 0 +#define SC_DEBUG_10_trigger_SHIFT 31 + +#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff +#define SC_DEBUG_10_trigger_MASK 0x80000000 + +#define SC_DEBUG_10_MASK \ + (SC_DEBUG_10_combined_sample_mask_MASK | \ + SC_DEBUG_10_trigger_MASK) + +#define SC_DEBUG_10(combined_sample_mask, trigger) \ + ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \ + (trigger << SC_DEBUG_10_trigger_SHIFT)) + +#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_GET_trigger(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT) + +#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + unsigned int : 15; + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + } sc_debug_10_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + unsigned int : 15; + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + } sc_debug_10_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_10_t f; +} sc_debug_10_u; + + +/* + * SC_DEBUG_11 struct + */ + +#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_11_iterator_input_fz_SIZE 1 +#define SC_DEBUG_11_packer_send_quads_SIZE 1 +#define SC_DEBUG_11_packer_send_cmd_SIZE 1 +#define SC_DEBUG_11_packer_send_event_SIZE 1 +#define SC_DEBUG_11_next_state_SIZE 3 +#define SC_DEBUG_11_state_SIZE 3 +#define SC_DEBUG_11_stall_SIZE 1 +#define SC_DEBUG_11_trigger_SIZE 1 + +#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1 +#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3 +#define SC_DEBUG_11_iterator_input_fz_SHIFT 4 +#define SC_DEBUG_11_packer_send_quads_SHIFT 5 +#define SC_DEBUG_11_packer_send_cmd_SHIFT 6 +#define SC_DEBUG_11_packer_send_event_SHIFT 7 +#define SC_DEBUG_11_next_state_SHIFT 8 +#define SC_DEBUG_11_state_SHIFT 11 +#define SC_DEBUG_11_stall_SHIFT 14 +#define SC_DEBUG_11_trigger_SHIFT 31 + +#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002 +#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008 +#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010 +#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020 +#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040 +#define SC_DEBUG_11_packer_send_event_MASK 0x00000080 +#define SC_DEBUG_11_next_state_MASK 0x00000700 +#define SC_DEBUG_11_state_MASK 0x00003800 +#define SC_DEBUG_11_stall_MASK 0x00004000 +#define SC_DEBUG_11_trigger_MASK 0x80000000 + +#define SC_DEBUG_11_MASK \ + (SC_DEBUG_11_ez_sample_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_11_ez_prim_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_11_iterator_input_fz_MASK | \ + SC_DEBUG_11_packer_send_quads_MASK | \ + SC_DEBUG_11_packer_send_cmd_MASK | \ + SC_DEBUG_11_packer_send_event_MASK | \ + SC_DEBUG_11_next_state_MASK | \ + SC_DEBUG_11_state_MASK | \ + SC_DEBUG_11_stall_MASK | \ + SC_DEBUG_11_trigger_MASK) + +#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \ + ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \ + (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \ + (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \ + (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \ + (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \ + (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \ + (next_state << SC_DEBUG_11_next_state_SHIFT) | \ + (state << SC_DEBUG_11_state_SHIFT) | \ + (stall << SC_DEBUG_11_stall_SHIFT) | \ + (trigger << SC_DEBUG_11_trigger_SHIFT)) + +#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_GET_next_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_GET_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_GET_stall(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_GET_trigger(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT) + +#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int : 16; + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + } sc_debug_11_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + unsigned int : 16; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + } sc_debug_11_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_11_t f; +} sc_debug_11_u; + + +/* + * SC_DEBUG_12 struct + */ + +#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1 +#define SC_DEBUG_12_event_id_SIZE 5 +#define SC_DEBUG_12_event_flag_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_full_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1 +#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1 +#define SC_DEBUG_12_iter_qdhit0_SIZE 1 +#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1 +#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1 +#define SC_DEBUG_12_iter_phase_out_SIZE 2 +#define SC_DEBUG_12_iter_phase_reg_SIZE 2 +#define SC_DEBUG_12_iterator_SP_valid_SIZE 1 +#define SC_DEBUG_12_eopv_reg_SIZE 1 +#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1 +#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1 +#define SC_DEBUG_12_trigger_SIZE 1 + +#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0 +#define SC_DEBUG_12_event_id_SHIFT 1 +#define SC_DEBUG_12_event_flag_SHIFT 6 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7 +#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8 +#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9 +#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11 +#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12 +#define SC_DEBUG_12_iter_qdhit0_SHIFT 13 +#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14 +#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15 +#define SC_DEBUG_12_iter_phase_out_SHIFT 16 +#define SC_DEBUG_12_iter_phase_reg_SHIFT 18 +#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20 +#define SC_DEBUG_12_eopv_reg_SHIFT 21 +#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22 +#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23 +#define SC_DEBUG_12_trigger_SHIFT 31 + +#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001 +#define SC_DEBUG_12_event_id_MASK 0x0000003e +#define SC_DEBUG_12_event_flag_MASK 0x00000040 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080 +#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100 +#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200 +#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400 +#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800 +#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000 +#define SC_DEBUG_12_iter_qdhit0_MASK 0x00002000 +#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000 +#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000 +#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000 +#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000 +#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000 +#define SC_DEBUG_12_eopv_reg_MASK 0x00200000 +#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000 +#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000 +#define SC_DEBUG_12_trigger_MASK 0x80000000 + +#define SC_DEBUG_12_MASK \ + (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \ + SC_DEBUG_12_event_id_MASK | \ + SC_DEBUG_12_event_flag_MASK | \ + SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \ + SC_DEBUG_12_itercmdfifo_full_MASK | \ + SC_DEBUG_12_itercmdfifo_empty_MASK | \ + SC_DEBUG_12_iter_ds_one_clk_command_MASK | \ + SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \ + SC_DEBUG_12_iter_ds_end_of_vector_MASK | \ + SC_DEBUG_12_iter_qdhit0_MASK | \ + SC_DEBUG_12_bc_use_centers_reg_MASK | \ + SC_DEBUG_12_bc_output_xy_reg_MASK | \ + SC_DEBUG_12_iter_phase_out_MASK | \ + SC_DEBUG_12_iter_phase_reg_MASK | \ + SC_DEBUG_12_iterator_SP_valid_MASK | \ + SC_DEBUG_12_eopv_reg_MASK | \ + SC_DEBUG_12_one_clk_cmd_reg_MASK | \ + SC_DEBUG_12_iter_dx_end_of_prim_MASK | \ + SC_DEBUG_12_trigger_MASK) + +#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \ + ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \ + (event_id << SC_DEBUG_12_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \ + (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \ + (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \ + (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \ + (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \ + (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \ + (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \ + (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \ + (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \ + (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \ + (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \ + (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \ + (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \ + (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \ + (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \ + (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \ + (trigger << SC_DEBUG_12_trigger_SHIFT)) + +#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_GET_event_id(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_GET_trigger(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT) + +#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int : 7; + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + } sc_debug_12_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + } sc_debug_12_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_12_t f; +} sc_debug_12_u; + + +#endif + + +#if !defined (_VGT_FIDDLE_H) +#define _VGT_FIDDLE_H + +/***************************************************************************************************************** + * + * vgt_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + +/* + * VGT_OUT_PRIM_TYPE enum + */ + +#define VGT_OUT_POINT 0x00000000 +#define VGT_OUT_LINE 0x00000001 +#define VGT_OUT_TRI 0x00000002 +#define VGT_OUT_RECT_V0 0x00000003 +#define VGT_OUT_RECT_V1 0x00000004 +#define VGT_OUT_RECT_V2 0x00000005 +#define VGT_OUT_RECT_V3 0x00000006 +#define VGT_OUT_RESERVED 0x00000007 +#define VGT_TE_QUAD 0x00000008 +#define VGT_TE_PRIM_INDEX_LINE 0x00000009 +#define VGT_TE_PRIM_INDEX_TRI 0x0000000a +#define VGT_TE_PRIM_INDEX_QUAD 0x0000000b + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * GFX_COPY_STATE struct + */ + +#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1 + +#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0 + +#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 + +#define GFX_COPY_STATE_MASK \ + (GFX_COPY_STATE_SRC_STATE_ID_MASK) + +#define GFX_COPY_STATE(src_state_id) \ + ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)) + +#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \ + ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \ + gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 31; + } gfx_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int : 31; + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + } gfx_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + gfx_copy_state_t f; +} gfx_copy_state_u; + + +/* + * VGT_DRAW_INITIATOR struct + */ + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1 +#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11 +#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800 +#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000 +#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000 + +#define VGT_DRAW_INITIATOR_MASK \ + (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \ + VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \ + VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \ + VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \ + VGT_DRAW_INITIATOR_NOT_EOP_MASK | \ + VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \ + VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_NUM_INDICES_MASK) + +#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \ + ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \ + (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \ + (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \ + (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \ + (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \ + (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \ + (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \ + (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \ + (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)) + +#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int : 1; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + } vgt_draw_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int : 1; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + } vgt_draw_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_draw_initiator_t f; +} vgt_draw_initiator_u; + + +/* + * VGT_EVENT_INITIATOR struct + */ + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f + +#define VGT_EVENT_INITIATOR_MASK \ + (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) + +#define VGT_EVENT_INITIATOR(event_type) \ + ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)) + +#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \ + ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \ + vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + unsigned int : 26; + } vgt_event_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int : 26; + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + } vgt_event_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_event_initiator_t f; +} vgt_event_initiator_u; + + +/* + * VGT_DMA_BASE struct + */ + +#define VGT_DMA_BASE_BASE_ADDR_SIZE 32 + +#define VGT_DMA_BASE_BASE_ADDR_SHIFT 0 + +#define VGT_DMA_BASE_BASE_ADDR_MASK 0xffffffff + +#define VGT_DMA_BASE_MASK \ + (VGT_DMA_BASE_BASE_ADDR_MASK) + +#define VGT_DMA_BASE(base_addr) \ + ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)) + +#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \ + ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \ + vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_base_t f; +} vgt_dma_base_u; + + +/* + * VGT_DMA_SIZE struct + */ + +#define VGT_DMA_SIZE_NUM_WORDS_SIZE 24 +#define VGT_DMA_SIZE_SWAP_MODE_SIZE 2 + +#define VGT_DMA_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_DMA_SIZE_SWAP_MODE_SHIFT 30 + +#define VGT_DMA_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_DMA_SIZE_SWAP_MODE_MASK 0xc0000000 + +#define VGT_DMA_SIZE_MASK \ + (VGT_DMA_SIZE_NUM_WORDS_MASK | \ + VGT_DMA_SIZE_SWAP_MODE_MASK) + +#define VGT_DMA_SIZE(num_words, swap_mode) \ + ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \ + (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)) + +#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + } vgt_dma_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + } vgt_dma_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_size_t f; +} vgt_dma_size_u; + + +/* + * VGT_BIN_BASE struct + */ + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff + +#define VGT_BIN_BASE_MASK \ + (VGT_BIN_BASE_BIN_BASE_ADDR_MASK) + +#define VGT_BIN_BASE(bin_base_addr) \ + ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)) + +#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \ + ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \ + vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_base_t f; +} vgt_bin_base_u; + + +/* + * VGT_BIN_SIZE struct + */ + +#define VGT_BIN_SIZE_NUM_WORDS_SIZE 24 +#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1 +#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1 + +#define VGT_BIN_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30 +#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31 + +#define VGT_BIN_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000 +#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000 + +#define VGT_BIN_SIZE_MASK \ + (VGT_BIN_SIZE_NUM_WORDS_MASK | \ + VGT_BIN_SIZE_FACENESS_FETCH_MASK | \ + VGT_BIN_SIZE_FACENESS_RESET_MASK) + +#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \ + ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \ + (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \ + (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)) + +#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + } vgt_bin_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + } vgt_bin_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_size_t f; +} vgt_bin_size_u; + + +/* + * VGT_CURRENT_BIN_ID_MIN struct + */ + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MIN_MASK \ + (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_min_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + } vgt_current_bin_id_min_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_min_t f; +} vgt_current_bin_id_min_u; + + +/* + * VGT_CURRENT_BIN_ID_MAX struct + */ + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MAX_MASK \ + (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_max_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + } vgt_current_bin_id_max_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_max_t f; +} vgt_current_bin_id_max_u; + + +/* + * VGT_IMMED_DATA struct + */ + +#define VGT_IMMED_DATA_DATA_SIZE 32 + +#define VGT_IMMED_DATA_DATA_SHIFT 0 + +#define VGT_IMMED_DATA_DATA_MASK 0xffffffff + +#define VGT_IMMED_DATA_MASK \ + (VGT_IMMED_DATA_DATA_MASK) + +#define VGT_IMMED_DATA(data) \ + ((data << VGT_IMMED_DATA_DATA_SHIFT)) + +#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \ + ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT) + +#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \ + vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_immed_data_t f; +} vgt_immed_data_u; + + +/* + * VGT_MAX_VTX_INDX struct + */ + +#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24 + +#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0 + +#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff + +#define VGT_MAX_VTX_INDX_MASK \ + (VGT_MAX_VTX_INDX_MAX_INDX_MASK) + +#define VGT_MAX_VTX_INDX(max_indx) \ + ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)) + +#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \ + ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \ + vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + unsigned int : 8; + } vgt_max_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int : 8; + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + } vgt_max_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_max_vtx_indx_t f; +} vgt_max_vtx_indx_u; + + +/* + * VGT_MIN_VTX_INDX struct + */ + +#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24 + +#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0 + +#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff + +#define VGT_MIN_VTX_INDX_MASK \ + (VGT_MIN_VTX_INDX_MIN_INDX_MASK) + +#define VGT_MIN_VTX_INDX(min_indx) \ + ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)) + +#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \ + ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \ + vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + unsigned int : 8; + } vgt_min_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int : 8; + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + } vgt_min_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_min_vtx_indx_t f; +} vgt_min_vtx_indx_u; + + +/* + * VGT_INDX_OFFSET struct + */ + +#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24 + +#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0 + +#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff + +#define VGT_INDX_OFFSET_MASK \ + (VGT_INDX_OFFSET_INDX_OFFSET_MASK) + +#define VGT_INDX_OFFSET(indx_offset) \ + ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)) + +#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \ + ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \ + vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + unsigned int : 8; + } vgt_indx_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int : 8; + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + } vgt_indx_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_indx_offset_t f; +} vgt_indx_offset_u; + + +/* + * VGT_VERTEX_REUSE_BLOCK_CNTL struct + */ + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \ + (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \ + ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \ + ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \ + vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + unsigned int : 29; + } vgt_vertex_reuse_block_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int : 29; + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + } vgt_vertex_reuse_block_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vertex_reuse_block_cntl_t f; +} vgt_vertex_reuse_block_cntl_u; + + +/* + * VGT_OUT_DEALLOC_CNTL struct + */ + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003 + +#define VGT_OUT_DEALLOC_CNTL_MASK \ + (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) + +#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \ + ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)) + +#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \ + ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \ + vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + unsigned int : 30; + } vgt_out_dealloc_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int : 30; + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + } vgt_out_dealloc_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_out_dealloc_cntl_t f; +} vgt_out_dealloc_cntl_u; + + +/* + * VGT_MULTI_PRIM_IB_RESET_INDX struct + */ + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff + +#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \ + (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) + +#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \ + ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \ + ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \ + vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + unsigned int : 8; + } vgt_multi_prim_ib_reset_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int : 8; + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + } vgt_multi_prim_ib_reset_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_multi_prim_ib_reset_indx_t f; +} vgt_multi_prim_ib_reset_indx_u; + + +/* + * VGT_ENHANCE struct + */ + +#define VGT_ENHANCE_MISC_SIZE 16 + +#define VGT_ENHANCE_MISC_SHIFT 0 + +#define VGT_ENHANCE_MISC_MASK 0x0000ffff + +#define VGT_ENHANCE_MASK \ + (VGT_ENHANCE_MISC_MASK) + +#define VGT_ENHANCE(misc) \ + ((misc << VGT_ENHANCE_MISC_SHIFT)) + +#define VGT_ENHANCE_GET_MISC(vgt_enhance) \ + ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT) + +#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \ + vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + unsigned int : 16; + } vgt_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int : 16; + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + } vgt_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_enhance_t f; +} vgt_enhance_u; + + +/* + * VGT_VTX_VECT_EJECT_REG struct + */ + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f + +#define VGT_VTX_VECT_EJECT_REG_MASK \ + (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) + +#define VGT_VTX_VECT_EJECT_REG(prim_count) \ + ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)) + +#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \ + ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \ + vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + unsigned int : 27; + } vgt_vtx_vect_eject_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int : 27; + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + } vgt_vtx_vect_eject_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vtx_vect_eject_reg_t f; +} vgt_vtx_vect_eject_reg_u; + + +/* + * VGT_LAST_COPY_STATE struct + */ + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000 + +#define VGT_LAST_COPY_STATE_MASK \ + (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \ + VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) + +#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \ + ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \ + (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)) + +#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + } vgt_last_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + } vgt_last_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_last_copy_state_t f; +} vgt_last_copy_state_u; + + +/* + * VGT_DEBUG_CNTL struct + */ + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f + +#define VGT_DEBUG_CNTL_MASK \ + (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) + +#define VGT_DEBUG_CNTL(vgt_debug_indx) \ + ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)) + +#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \ + ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \ + vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + unsigned int : 27; + } vgt_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int : 27; + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + } vgt_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_cntl_t f; +} vgt_debug_cntl_u; + + +/* + * VGT_DEBUG_DATA struct + */ + +#define VGT_DEBUG_DATA_DATA_SIZE 32 + +#define VGT_DEBUG_DATA_DATA_SHIFT 0 + +#define VGT_DEBUG_DATA_DATA_MASK 0xffffffff + +#define VGT_DEBUG_DATA_MASK \ + (VGT_DEBUG_DATA_DATA_MASK) + +#define VGT_DEBUG_DATA(data) \ + ((data << VGT_DEBUG_DATA_DATA_SHIFT)) + +#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \ + ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT) + +#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \ + vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_data_t f; +} vgt_debug_data_u; + + +/* + * VGT_CNTL_STATUS struct + */ + +#define VGT_CNTL_STATUS_VGT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1 + +#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8 + +#define VGT_CNTL_STATUS_VGT_BUSY_MASK 0x00000001 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100 + +#define VGT_CNTL_STATUS_MASK \ + (VGT_CNTL_STATUS_VGT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) + +#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \ + ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \ + (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \ + (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \ + (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \ + (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \ + (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \ + (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \ + (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \ + (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)) + +#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int : 23; + } vgt_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int : 23; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + } vgt_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_cntl_status_t f; +} vgt_cntl_status_u; + + +/* + * VGT_DEBUG_REG0 struct + */ + +#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_out_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1 + +#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0 +#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2 +#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3 +#define VGT_DEBUG_REG0_out_busy_SHIFT 4 +#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5 +#define VGT_DEBUG_REG0_grp_busy_SHIFT 6 +#define VGT_DEBUG_REG0_dma_busy_SHIFT 7 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8 +#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11 +#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12 +#define VGT_DEBUG_REG0_vgt_busy_SHIFT 13 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16 + +#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001 +#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002 +#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004 +#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008 +#define VGT_DEBUG_REG0_out_busy_MASK 0x00000010 +#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020 +#define VGT_DEBUG_REG0_grp_busy_MASK 0x00000040 +#define VGT_DEBUG_REG0_dma_busy_MASK 0x00000080 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100 +#define VGT_DEBUG_REG0_rbiu_busy_MASK 0x00000200 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800 +#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000 +#define VGT_DEBUG_REG0_vgt_busy_MASK 0x00002000 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000 + +#define VGT_DEBUG_REG0_MASK \ + (VGT_DEBUG_REG0_te_grp_busy_MASK | \ + VGT_DEBUG_REG0_pt_grp_busy_MASK | \ + VGT_DEBUG_REG0_vr_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_out_busy_MASK | \ + VGT_DEBUG_REG0_grp_backend_busy_MASK | \ + VGT_DEBUG_REG0_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_busy_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_vgt_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_busy_MASK | \ + VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) + +#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \ + ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \ + (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \ + (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \ + (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \ + (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \ + (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \ + (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \ + (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \ + (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \ + (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \ + (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \ + (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \ + (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \ + (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \ + (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \ + (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \ + (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)) + +#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int : 15; + } vgt_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int : 15; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + } vgt_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg0_t f; +} vgt_debug_reg0_u; + + +/* + * VGT_DEBUG_REG1 struct + */ + +#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1 +#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_te_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1 +#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1 +#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1 +#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1 + +#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0 +#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3 +#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5 +#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7 +#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9 +#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10 +#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11 +#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12 +#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13 +#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14 +#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15 +#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16 +#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20 +#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28 +#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30 + +#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001 +#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002 +#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004 +#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008 +#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010 +#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020 +#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040 +#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080 +#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100 +#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200 +#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400 +#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800 +#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000 +#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000 +#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000 +#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000 +#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000 +#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000 +#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000 +#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000 + +#define VGT_DEBUG_REG1_MASK \ + (VGT_DEBUG_REG1_out_te_data_read_MASK | \ + VGT_DEBUG_REG1_te_out_data_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_prim_read_MASK | \ + VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_data_read_MASK | \ + VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_prim_read_MASK | \ + VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_indx_read_MASK | \ + VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_te_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_te_valid_MASK | \ + VGT_DEBUG_REG1_pt_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_pt_valid_MASK | \ + VGT_DEBUG_REG1_vr_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_vr_valid_MASK | \ + VGT_DEBUG_REG1_grp_dma_read_MASK | \ + VGT_DEBUG_REG1_dma_grp_valid_MASK | \ + VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \ + VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \ + VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_MH_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \ + VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_SQ_send_MASK | \ + VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) + +#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \ + ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \ + (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \ + (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \ + (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \ + (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \ + (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \ + (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \ + (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \ + (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \ + (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \ + (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \ + (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \ + (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \ + (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \ + (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \ + (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \ + (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \ + (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \ + (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \ + (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \ + (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \ + (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \ + (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \ + (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \ + (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \ + (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \ + (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \ + (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \ + (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \ + (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \ + (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)) + +#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int : 1; + } vgt_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + } vgt_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg1_t f; +} vgt_debug_reg1_u; + + +/* + * VGT_DEBUG_REG3 struct + */ + +#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002 + +#define VGT_DEBUG_REG3_MASK \ + (VGT_DEBUG_REG3_vgt_clk_en_MASK | \ + VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) + +#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \ + ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \ + (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)) + +#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int : 30; + } vgt_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int : 30; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + } vgt_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg3_t f; +} vgt_debug_reg3_u; + + +/* + * VGT_DEBUG_REG6 struct + */ + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG6_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_extract_vector_SIZE 1 +#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG6_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG6_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG6_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG6_MASK \ + (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG6_right_word_indx_q_MASK | \ + VGT_DEBUG_REG6_input_data_valid_MASK | \ + VGT_DEBUG_REG6_input_data_xfer_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG6_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG6_shifter_first_load_MASK | \ + VGT_DEBUG_REG6_di_state_sel_q_MASK | \ + VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG6_di_event_flag_q_MASK | \ + VGT_DEBUG_REG6_read_draw_initiator_MASK | \ + VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG6_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG6_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG6_extract_vector_MASK | \ + VGT_DEBUG_REG6_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG6_destination_rtr_MASK | \ + VGT_DEBUG_REG6_grp_trigger_MASK) + +#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int : 3; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + } vgt_debug_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg6_t f; +} vgt_debug_reg6_u; + + +/* + * VGT_DEBUG_REG7 struct + */ + +#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG7_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG7_MASK \ + (VGT_DEBUG_REG7_di_index_counter_q_MASK | \ + VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG7_shift_amount_extract_MASK | \ + VGT_DEBUG_REG7_di_prim_type_q_MASK | \ + VGT_DEBUG_REG7_current_source_sel_MASK) + +#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + } vgt_debug_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + } vgt_debug_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg7_t f; +} vgt_debug_reg7_u; + + +/* + * VGT_DEBUG_REG8 struct + */ + +#define VGT_DEBUG_REG8_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG8_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG8_MASK \ + (VGT_DEBUG_REG8_current_source_sel_MASK | \ + VGT_DEBUG_REG8_left_word_indx_q_MASK | \ + VGT_DEBUG_REG8_input_data_cnt_MASK | \ + VGT_DEBUG_REG8_input_data_lsw_MASK | \ + VGT_DEBUG_REG8_input_data_msw_MASK | \ + VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg8_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + } vgt_debug_reg8_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg8_t f; +} vgt_debug_reg8_u; + + +/* + * VGT_DEBUG_REG9 struct + */ + +#define VGT_DEBUG_REG9_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG9_MASK \ + (VGT_DEBUG_REG9_next_stride_q_MASK | \ + VGT_DEBUG_REG9_next_stride_d_MASK | \ + VGT_DEBUG_REG9_current_shift_q_MASK | \ + VGT_DEBUG_REG9_current_shift_d_MASK | \ + VGT_DEBUG_REG9_current_stride_q_MASK | \ + VGT_DEBUG_REG9_current_stride_d_MASK | \ + VGT_DEBUG_REG9_grp_trigger_MASK) + +#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg9_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int : 1; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + } vgt_debug_reg9_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg9_t f; +} vgt_debug_reg9_u; + + +/* + * VGT_DEBUG_REG10 struct + */ + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG10_bin_valid_SIZE 1 +#define VGT_DEBUG_REG10_read_block_SIZE 1 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1 +#define VGT_DEBUG_REG10_selected_data_SIZE 8 +#define VGT_DEBUG_REG10_mask_input_data_SIZE 8 +#define VGT_DEBUG_REG10_gap_q_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1 +#define VGT_DEBUG_REG10_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3 +#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4 +#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5 +#define VGT_DEBUG_REG10_bin_valid_SHIFT 6 +#define VGT_DEBUG_REG10_read_block_SHIFT 7 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8 +#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10 +#define VGT_DEBUG_REG10_selected_data_SHIFT 11 +#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19 +#define VGT_DEBUG_REG10_gap_q_SHIFT 27 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30 +#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008 +#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010 +#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020 +#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040 +#define VGT_DEBUG_REG10_read_block_MASK 0x00000080 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100 +#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200 +#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400 +#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800 +#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000 +#define VGT_DEBUG_REG10_gap_q_MASK 0x08000000 +#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000 +#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000 +#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000 +#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG10_MASK \ + (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_di_state_sel_q_MASK | \ + VGT_DEBUG_REG10_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG10_bin_valid_MASK | \ + VGT_DEBUG_REG10_read_block_MASK | \ + VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \ + VGT_DEBUG_REG10_last_bit_enable_q_MASK | \ + VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \ + VGT_DEBUG_REG10_selected_data_MASK | \ + VGT_DEBUG_REG10_mask_input_data_MASK | \ + VGT_DEBUG_REG10_gap_q_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \ + VGT_DEBUG_REG10_grp_trigger_MASK) + +#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \ + ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \ + (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \ + (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \ + (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \ + (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \ + (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \ + (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \ + (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \ + (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \ + (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \ + (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \ + (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \ + (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \ + (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \ + (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + } vgt_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + } vgt_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg10_t f; +} vgt_debug_reg10_u; + + +/* + * VGT_DEBUG_REG12 struct + */ + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG12_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_extract_vector_SIZE 1 +#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG12_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG12_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG12_MASK \ + (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG12_right_word_indx_q_MASK | \ + VGT_DEBUG_REG12_input_data_valid_MASK | \ + VGT_DEBUG_REG12_input_data_xfer_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG12_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG12_shifter_first_load_MASK | \ + VGT_DEBUG_REG12_di_state_sel_q_MASK | \ + VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG12_di_event_flag_q_MASK | \ + VGT_DEBUG_REG12_read_draw_initiator_MASK | \ + VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG12_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG12_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG12_extract_vector_MASK | \ + VGT_DEBUG_REG12_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG12_destination_rtr_MASK | \ + VGT_DEBUG_REG12_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int : 3; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + } vgt_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg12_t f; +} vgt_debug_reg12_u; + + +/* + * VGT_DEBUG_REG13 struct + */ + +#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG13_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG13_MASK \ + (VGT_DEBUG_REG13_di_index_counter_q_MASK | \ + VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG13_shift_amount_extract_MASK | \ + VGT_DEBUG_REG13_di_prim_type_q_MASK | \ + VGT_DEBUG_REG13_current_source_sel_MASK) + +#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + } vgt_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + } vgt_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg13_t f; +} vgt_debug_reg13_u; + + +/* + * VGT_DEBUG_REG14 struct + */ + +#define VGT_DEBUG_REG14_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG14_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG14_MASK \ + (VGT_DEBUG_REG14_current_source_sel_MASK | \ + VGT_DEBUG_REG14_left_word_indx_q_MASK | \ + VGT_DEBUG_REG14_input_data_cnt_MASK | \ + VGT_DEBUG_REG14_input_data_lsw_MASK | \ + VGT_DEBUG_REG14_input_data_msw_MASK | \ + VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + } vgt_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg14_t f; +} vgt_debug_reg14_u; + + +/* + * VGT_DEBUG_REG15 struct + */ + +#define VGT_DEBUG_REG15_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG15_MASK \ + (VGT_DEBUG_REG15_next_stride_q_MASK | \ + VGT_DEBUG_REG15_next_stride_d_MASK | \ + VGT_DEBUG_REG15_current_shift_q_MASK | \ + VGT_DEBUG_REG15_current_shift_d_MASK | \ + VGT_DEBUG_REG15_current_stride_q_MASK | \ + VGT_DEBUG_REG15_current_stride_d_MASK | \ + VGT_DEBUG_REG15_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int : 1; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + } vgt_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg15_t f; +} vgt_debug_reg15_u; + + +/* + * VGT_DEBUG_REG16 struct + */ + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1 +#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1 +#define VGT_DEBUG_REG16_current_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_en_SIZE 1 +#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1 +#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9 +#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10 +#define VGT_DEBUG_REG16_current_state_q_SHIFT 11 +#define VGT_DEBUG_REG16_old_state_q_SHIFT 12 +#define VGT_DEBUG_REG16_old_state_en_SHIFT 13 +#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15 +#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17 +#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30 +#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200 +#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400 +#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800 +#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000 +#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000 +#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000 +#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000 +#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000 +#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000 +#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000 +#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG16_MASK \ + (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \ + VGT_DEBUG_REG16_rst_last_bit_MASK | \ + VGT_DEBUG_REG16_current_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_en_MASK | \ + VGT_DEBUG_REG16_prev_last_bit_q_MASK | \ + VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \ + VGT_DEBUG_REG16_last_bit_block_q_MASK | \ + VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \ + VGT_DEBUG_REG16_load_empty_reg_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \ + VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \ + VGT_DEBUG_REG16_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \ + ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \ + (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \ + (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \ + (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \ + (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \ + (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \ + (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \ + (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \ + (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \ + (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \ + (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \ + (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \ + (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \ + (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \ + (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \ + (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \ + (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \ + (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \ + (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \ + (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \ + (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + } vgt_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + } vgt_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg16_t f; +} vgt_debug_reg16_u; + + +/* + * VGT_DEBUG_REG17 struct + */ + +#define VGT_DEBUG_REG17_save_read_q_SIZE 1 +#define VGT_DEBUG_REG17_extend_read_q_SIZE 1 +#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2 +#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1 +#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1 +#define VGT_DEBUG_REG17_check_second_reg_SIZE 1 +#define VGT_DEBUG_REG17_check_first_reg_SIZE 1 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1 +#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG17_save_read_q_SHIFT 0 +#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1 +#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2 +#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4 +#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5 +#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6 +#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7 +#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8 +#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14 +#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15 +#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24 +#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001 +#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002 +#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c +#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010 +#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020 +#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040 +#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080 +#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100 +#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000 +#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000 +#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000 +#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000 +#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000 +#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG17_MASK \ + (VGT_DEBUG_REG17_save_read_q_MASK | \ + VGT_DEBUG_REG17_extend_read_q_MASK | \ + VGT_DEBUG_REG17_grp_indx_size_MASK | \ + VGT_DEBUG_REG17_cull_prim_true_MASK | \ + VGT_DEBUG_REG17_reset_bit2_q_MASK | \ + VGT_DEBUG_REG17_reset_bit1_q_MASK | \ + VGT_DEBUG_REG17_first_reg_first_q_MASK | \ + VGT_DEBUG_REG17_check_second_reg_MASK | \ + VGT_DEBUG_REG17_check_first_reg_MASK | \ + VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \ + VGT_DEBUG_REG17_to_second_reg_q_MASK | \ + VGT_DEBUG_REG17_roll_over_msk_q_MASK | \ + VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \ + ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \ + (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \ + (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \ + (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \ + (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \ + (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \ + (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \ + (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \ + (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \ + (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \ + (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \ + (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \ + (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \ + (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \ + (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \ + (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \ + (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \ + (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + } vgt_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + } vgt_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg17_t f; +} vgt_debug_reg17_u; + + +/* + * VGT_DEBUG_REG18 struct + */ + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_start_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1 +#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13 +#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15 +#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16 +#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17 +#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20 +#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21 +#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22 +#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23 +#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24 +#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26 +#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27 +#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28 +#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000 +#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000 +#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000 +#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000 +#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000 +#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000 +#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000 +#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000 +#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000 +#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000 +#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000 +#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000 +#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000 +#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000 + +#define VGT_DEBUG_REG18_MASK \ + (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG18_dma_mem_full_MASK | \ + VGT_DEBUG_REG18_dma_ram_re_MASK | \ + VGT_DEBUG_REG18_dma_ram_we_MASK | \ + VGT_DEBUG_REG18_dma_mem_empty_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \ + VGT_DEBUG_REG18_bin_mem_full_MASK | \ + VGT_DEBUG_REG18_bin_ram_we_MASK | \ + VGT_DEBUG_REG18_bin_ram_re_MASK | \ + VGT_DEBUG_REG18_bin_mem_empty_MASK | \ + VGT_DEBUG_REG18_start_bin_req_MASK | \ + VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \ + VGT_DEBUG_REG18_dma_req_xfer_MASK | \ + VGT_DEBUG_REG18_have_valid_bin_req_MASK | \ + VGT_DEBUG_REG18_have_valid_dma_req_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) + +#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \ + ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \ + (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \ + (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \ + (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \ + (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \ + (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \ + (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \ + (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \ + (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \ + (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \ + (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \ + (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \ + (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \ + (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \ + (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \ + (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \ + (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \ + (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \ + (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)) + +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + } vgt_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + } vgt_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg18_t f; +} vgt_debug_reg18_u; + + +/* + * VGT_DEBUG_REG20 struct + */ + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_sent_cnt_SIZE 4 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5 +#define VGT_DEBUG_REG20_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5 +#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6 +#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7 +#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8 +#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9 +#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10 +#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11 +#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12 +#define VGT_DEBUG_REG20_hold_prim_SHIFT 13 +#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21 +#define VGT_DEBUG_REG20_out_trigger_SHIFT 26 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004 +#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020 +#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040 +#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080 +#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100 +#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200 +#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400 +#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800 +#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000 +#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000 +#define VGT_DEBUG_REG20_sent_cnt_MASK 0x0003c000 +#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000 +#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000 +#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000 + +#define VGT_DEBUG_REG20_MASK \ + (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \ + VGT_DEBUG_REG20_prim_buffer_empty_MASK | \ + VGT_DEBUG_REG20_prim_buffer_re_MASK | \ + VGT_DEBUG_REG20_prim_buffer_we_MASK | \ + VGT_DEBUG_REG20_prim_buffer_full_MASK | \ + VGT_DEBUG_REG20_indx_buffer_empty_MASK | \ + VGT_DEBUG_REG20_indx_buffer_re_MASK | \ + VGT_DEBUG_REG20_indx_buffer_we_MASK | \ + VGT_DEBUG_REG20_indx_buffer_full_MASK | \ + VGT_DEBUG_REG20_hold_prim_MASK | \ + VGT_DEBUG_REG20_sent_cnt_MASK | \ + VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \ + VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \ + VGT_DEBUG_REG20_out_trigger_MASK) + +#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \ + ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \ + (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \ + (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \ + (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \ + (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \ + (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \ + (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \ + (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \ + (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \ + (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \ + (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \ + (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \ + (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \ + (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \ + (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \ + (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \ + (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \ + (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \ + (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT) + +#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int : 5; + } vgt_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int : 5; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + } vgt_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg20_t f; +} vgt_debug_reg20_u; + + +/* + * VGT_DEBUG_REG21 struct + */ + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3 +#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4 +#define VGT_DEBUG_REG21_new_packet_q_SIZE 1 +#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1 +#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1 +#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1 +#define VGT_DEBUG_REG21_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1 +#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14 +#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18 +#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22 +#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25 +#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26 +#define VGT_DEBUG_REG21_out_trigger_SHIFT 31 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e +#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380 +#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000 +#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000 +#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000 +#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000 +#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000 +#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000 +#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG21_MASK \ + (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \ + VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \ + VGT_DEBUG_REG21_alloc_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \ + VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \ + VGT_DEBUG_REG21_new_packet_q_MASK | \ + VGT_DEBUG_REG21_new_allocate_q_MASK | \ + VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \ + VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \ + VGT_DEBUG_REG21_insert_null_prim_MASK | \ + VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \ + VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \ + VGT_DEBUG_REG21_buffered_thread_size_MASK | \ + VGT_DEBUG_REG21_out_trigger_MASK) + +#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \ + ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \ + (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \ + (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \ + (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \ + (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \ + (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \ + (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \ + (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \ + (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \ + (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \ + (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \ + (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \ + (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \ + (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT) + +#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int : 4; + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + } vgt_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + unsigned int : 4; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + } vgt_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg21_t f; +} vgt_debug_reg21_u; + + +/* + * VGT_CRC_SQ_DATA struct + */ + +#define VGT_CRC_SQ_DATA_CRC_SIZE 32 + +#define VGT_CRC_SQ_DATA_CRC_SHIFT 0 + +#define VGT_CRC_SQ_DATA_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_DATA_MASK \ + (VGT_CRC_SQ_DATA_CRC_MASK) + +#define VGT_CRC_SQ_DATA(crc) \ + ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT)) + +#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \ + ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT) + +#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \ + vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_data_t f; +} vgt_crc_sq_data_u; + + +/* + * VGT_CRC_SQ_CTRL struct + */ + +#define VGT_CRC_SQ_CTRL_CRC_SIZE 32 + +#define VGT_CRC_SQ_CTRL_CRC_SHIFT 0 + +#define VGT_CRC_SQ_CTRL_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_CTRL_MASK \ + (VGT_CRC_SQ_CTRL_CRC_MASK) + +#define VGT_CRC_SQ_CTRL(crc) \ + ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)) + +#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \ + ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \ + vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_ctrl_t f; +} vgt_crc_sq_ctrl_u; + + +/* + * VGT_PERFCOUNTER0_SELECT struct + */ + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER0_SELECT_MASK \ + (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \ + ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \ + vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_select_t f; +} vgt_perfcounter0_select_u; + + +/* + * VGT_PERFCOUNTER1_SELECT struct + */ + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER1_SELECT_MASK \ + (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \ + ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \ + vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_select_t f; +} vgt_perfcounter1_select_u; + + +/* + * VGT_PERFCOUNTER2_SELECT struct + */ + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER2_SELECT_MASK \ + (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \ + ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \ + vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_select_t f; +} vgt_perfcounter2_select_u; + + +/* + * VGT_PERFCOUNTER3_SELECT struct + */ + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER3_SELECT_MASK \ + (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \ + ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \ + vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_select_t f; +} vgt_perfcounter3_select_u; + + +/* + * VGT_PERFCOUNTER0_LOW struct + */ + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER0_LOW_MASK \ + (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \ + ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \ + vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_low_t f; +} vgt_perfcounter0_low_u; + + +/* + * VGT_PERFCOUNTER1_LOW struct + */ + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER1_LOW_MASK \ + (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \ + ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \ + vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_low_t f; +} vgt_perfcounter1_low_u; + + +/* + * VGT_PERFCOUNTER2_LOW struct + */ + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER2_LOW_MASK \ + (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \ + ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \ + vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_low_t f; +} vgt_perfcounter2_low_u; + + +/* + * VGT_PERFCOUNTER3_LOW struct + */ + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER3_LOW_MASK \ + (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \ + ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \ + vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_low_t f; +} vgt_perfcounter3_low_u; + + +/* + * VGT_PERFCOUNTER0_HI struct + */ + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER0_HI_MASK \ + (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \ + ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \ + vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } vgt_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_hi_t f; +} vgt_perfcounter0_hi_u; + + +/* + * VGT_PERFCOUNTER1_HI struct + */ + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER1_HI_MASK \ + (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \ + ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \ + vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } vgt_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_hi_t f; +} vgt_perfcounter1_hi_u; + + +/* + * VGT_PERFCOUNTER2_HI struct + */ + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER2_HI_MASK \ + (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \ + ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \ + vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } vgt_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_hi_t f; +} vgt_perfcounter2_hi_u; + + +/* + * VGT_PERFCOUNTER3_HI struct + */ + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER3_HI_MASK \ + (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \ + ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \ + vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } vgt_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_hi_t f; +} vgt_perfcounter3_hi_u; + + +#endif + + +#if !defined (_SQ_FIDDLE_H) +#define _SQ_FIDDLE_H + +/***************************************************************************************************************** + * + * sq_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * SQ_GPR_MANAGEMENT struct + */ + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000 + +#define SQ_GPR_MANAGEMENT_MASK \ + (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) + +#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \ + ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \ + (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \ + (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)) + +#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + unsigned int : 3; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 1; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 13; + } sq_gpr_management_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int : 13; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 1; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 3; + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + } sq_gpr_management_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_gpr_management_t f; +} sq_gpr_management_u; + + +/* + * SQ_FLOW_CONTROL struct + */ + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1 +#define SQ_FLOW_CONTROL_ONE_ALU_SIZE 1 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4 +#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE 1 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0 +#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4 +#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT 8 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12 +#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003 +#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010 +#define SQ_FLOW_CONTROL_ONE_ALU_MASK 0x00000100 +#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000 +#define SQ_FLOW_CONTROL_NO_PV_PS_MASK 0x00010000 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000 + +#define SQ_FLOW_CONTROL_MASK \ + (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ONE_THREAD_MASK | \ + SQ_FLOW_CONTROL_ONE_ALU_MASK | \ + SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \ + SQ_FLOW_CONTROL_NO_PV_PS_MASK | \ + SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \ + SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \ + SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \ + SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \ + SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \ + SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \ + SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) + +#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \ + ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \ + (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \ + (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \ + (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \ + (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \ + (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \ + (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \ + (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \ + (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \ + (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \ + (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \ + (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \ + (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \ + (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \ + (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)) + +#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + unsigned int : 2; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int : 4; + } sq_flow_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int : 4; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 2; + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + } sq_flow_control_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_flow_control_t f; +} sq_flow_control_u; + + +/* + * SQ_INST_STORE_MANAGMENT struct + */ + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000 + +#define SQ_INST_STORE_MANAGMENT_MASK \ + (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \ + SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) + +#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \ + ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \ + (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)) + +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + } sq_inst_store_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + } sq_inst_store_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_inst_store_managment_t f; +} sq_inst_store_managment_u; + + +/* + * SQ_RESOURCE_MANAGMENT struct + */ + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000 + +#define SQ_RESOURCE_MANAGMENT_MASK \ + (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) + +#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \ + ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \ + (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \ + (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)) + +#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int : 7; + } sq_resource_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int : 7; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + } sq_resource_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_resource_managment_t f; +} sq_resource_managment_u; + + +/* + * SQ_EO_RT struct + */ + +#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE 8 +#define SQ_EO_RT_EO_TSTATE_RT_SIZE 8 + +#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0 +#define SQ_EO_RT_EO_TSTATE_RT_SHIFT 16 + +#define SQ_EO_RT_EO_CONSTANTS_RT_MASK 0x000000ff +#define SQ_EO_RT_EO_TSTATE_RT_MASK 0x00ff0000 + +#define SQ_EO_RT_MASK \ + (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \ + SQ_EO_RT_EO_TSTATE_RT_MASK) + +#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \ + ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \ + (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)) + +#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + } sq_eo_rt_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + } sq_eo_rt_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_eo_rt_t f; +} sq_eo_rt_u; + + +/* + * SQ_DEBUG_MISC struct + */ + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8 +#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1 +#define SQ_DEBUG_MISC_RESERVED_SIZE 2 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12 +#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20 +#define SQ_DEBUG_MISC_RESERVED_SHIFT 21 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000 +#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000 +#define SQ_DEBUG_MISC_RESERVED_MASK 0x00600000 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000 + +#define SQ_DEBUG_MISC_MASK \ + (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_READ_CTX_MASK | \ + SQ_DEBUG_MISC_RESERVED_MASK | \ + SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) + +#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \ + ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \ + (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \ + (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \ + (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \ + (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \ + (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \ + (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \ + (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \ + (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)) + +#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + unsigned int : 1; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int : 3; + } sq_debug_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int : 3; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int : 1; + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + } sq_debug_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_t f; +} sq_debug_misc_u; + + +/* + * SQ_ACTIVITY_METER_CNTL struct + */ + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000 +#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000 + +#define SQ_ACTIVITY_METER_CNTL_MASK \ + (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \ + SQ_ACTIVITY_METER_CNTL_SPARE_MASK) + +#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \ + ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \ + (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \ + (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \ + (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)) + +#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + } sq_activity_meter_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + } sq_activity_meter_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_cntl_t f; +} sq_activity_meter_cntl_u; + + +/* + * SQ_ACTIVITY_METER_STATUS struct + */ + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff + +#define SQ_ACTIVITY_METER_STATUS_MASK \ + (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) + +#define SQ_ACTIVITY_METER_STATUS(percent_busy) \ + ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)) + +#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \ + ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \ + sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + unsigned int : 24; + } sq_activity_meter_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int : 24; + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + } sq_activity_meter_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_status_t f; +} sq_activity_meter_status_u; + + +/* + * SQ_INPUT_ARB_PRIORITY struct + */ + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 + +#define SQ_INPUT_ARB_PRIORITY_MASK \ + (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) + +#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \ + ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)) + +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int : 14; + } sq_input_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int : 14; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_input_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_input_arb_priority_t f; +} sq_input_arb_priority_u; + + +/* + * SQ_THREAD_ARB_PRIORITY struct + */ + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000 + +#define SQ_THREAD_ARB_PRIORITY_MASK \ + (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \ + SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \ + SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) + +#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \ + ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \ + (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \ + (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \ + (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \ + (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)) + +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int : 9; + } sq_thread_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int : 9; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_thread_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_thread_arb_priority_t f; +} sq_thread_arb_priority_u; + + +/* + * SQ_VS_WATCHDOG_TIMER struct + */ + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_VS_WATCHDOG_TIMER_MASK \ + (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_vs_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_vs_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_watchdog_timer_t f; +} sq_vs_watchdog_timer_u; + + +/* + * SQ_PS_WATCHDOG_TIMER struct + */ + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_PS_WATCHDOG_TIMER_MASK \ + (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_ps_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_ps_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_watchdog_timer_t f; +} sq_ps_watchdog_timer_u; + + +/* + * SQ_INT_CNTL struct + */ + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002 + +#define SQ_INT_CNTL_MASK \ + (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \ + SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) + +#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \ + ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \ + (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)) + +#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int : 30; + } sq_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int : 30; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + } sq_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_cntl_t f; +} sq_int_cntl_u; + + +/* + * SQ_INT_STATUS struct + */ + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002 + +#define SQ_INT_STATUS_MASK \ + (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \ + SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) + +#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \ + ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \ + (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)) + +#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int : 30; + } sq_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int : 30; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + } sq_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_status_t f; +} sq_int_status_u; + + +/* + * SQ_INT_ACK struct + */ + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002 + +#define SQ_INT_ACK_MASK \ + (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \ + SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) + +#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \ + ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \ + (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)) + +#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int : 30; + } sq_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int : 30; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + } sq_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_ack_t f; +} sq_int_ack_u; + + +/* + * SQ_DEBUG_INPUT_FSM struct + */ + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007 +#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK 0x00007000 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000 + +#define SQ_DEBUG_INPUT_FSM_MASK \ + (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \ + SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) + +#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \ + ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \ + (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \ + (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \ + (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \ + (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \ + (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \ + (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \ + (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)) + +#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int : 4; + } sq_debug_input_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int : 4; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + } sq_debug_input_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_input_fsm_t f; +} sq_debug_input_fsm_u; + + +/* + * SQ_DEBUG_CONST_MGR_FSM struct + */ + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000 + +#define SQ_DEBUG_CONST_MGR_FSM_MASK \ + (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) + +#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \ + ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \ + (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \ + (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \ + (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \ + (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \ + (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \ + (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \ + (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \ + (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \ + (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)) + +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int : 8; + } sq_debug_const_mgr_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int : 8; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + } sq_debug_const_mgr_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_const_mgr_fsm_t f; +} sq_debug_const_mgr_fsm_u; + + +/* + * SQ_DEBUG_TP_FSM struct + */ + +#define SQ_DEBUG_TP_FSM_EX_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1 +#define SQ_DEBUG_TP_FSM_CF_TP_SIZE 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2 +#define SQ_DEBUG_TP_FSM_GS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3 + +#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT 0 +#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3 +#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT 8 +#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT 12 +#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14 +#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT 16 +#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18 +#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT 20 +#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22 +#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT 24 +#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28 + +#define SQ_DEBUG_TP_FSM_EX_TP_MASK 0x00000007 +#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_TP_FSM_CF_TP_MASK 0x000000f0 +#define SQ_DEBUG_TP_FSM_IF_TP_MASK 0x00000700 +#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_TP_FSM_TIS_TP_MASK 0x00003000 +#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000 +#define SQ_DEBUG_TP_FSM_GS_TP_MASK 0x00030000 +#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000 +#define SQ_DEBUG_TP_FSM_FCR_TP_MASK 0x00300000 +#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000 +#define SQ_DEBUG_TP_FSM_FCS_TP_MASK 0x03000000 +#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000 + +#define SQ_DEBUG_TP_FSM_MASK \ + (SQ_DEBUG_TP_FSM_EX_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED0_MASK | \ + SQ_DEBUG_TP_FSM_CF_TP_MASK | \ + SQ_DEBUG_TP_FSM_IF_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED1_MASK | \ + SQ_DEBUG_TP_FSM_TIS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED2_MASK | \ + SQ_DEBUG_TP_FSM_GS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED3_MASK | \ + SQ_DEBUG_TP_FSM_FCR_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED4_MASK | \ + SQ_DEBUG_TP_FSM_FCS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED5_MASK | \ + SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) + +#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \ + ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \ + (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \ + (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \ + (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \ + (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \ + (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \ + (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \ + (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \ + (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \ + (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \ + (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \ + (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \ + (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \ + (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)) + +#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int : 1; + } sq_debug_tp_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int : 1; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + } sq_debug_tp_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tp_fsm_t f; +} sq_debug_tp_fsm_u; + + +/* + * SQ_DEBUG_FSM_ALU_0 struct + */ + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_0_MASK \ + (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_0_t f; +} sq_debug_fsm_alu_0_u; + + +/* + * SQ_DEBUG_FSM_ALU_1 struct + */ + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_1_MASK \ + (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_1_t f; +} sq_debug_fsm_alu_1_u; + + +/* + * SQ_DEBUG_EXP_ALLOC struct + */ + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000 + +#define SQ_DEBUG_EXP_ALLOC_MASK \ + (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \ + SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) + +#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \ + ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \ + (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \ + (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \ + (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \ + (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)) + +#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int : 10; + } sq_debug_exp_alloc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int : 10; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + } sq_debug_exp_alloc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_exp_alloc_t f; +} sq_debug_exp_alloc_u; + + +/* + * SQ_DEBUG_PTR_BUFF struct + */ + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000 + +#define SQ_DEBUG_PTR_BUFF_MASK \ + (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \ + SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \ + SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \ + SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \ + SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \ + SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) + +#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \ + ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \ + (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \ + (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \ + (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \ + (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \ + (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \ + (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \ + (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \ + (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)) + +#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int : 4; + } sq_debug_ptr_buff_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int : 4; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + } sq_debug_ptr_buff_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_ptr_buff_t f; +} sq_debug_ptr_buff_u; + + +/* + * SQ_DEBUG_GPR_VTX struct + */ + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_VTX_MASK \ + (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) + +#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \ + ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \ + (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \ + (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \ + (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_vtx_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int : 1; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + } sq_debug_gpr_vtx_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_vtx_t f; +} sq_debug_gpr_vtx_u; + + +/* + * SQ_DEBUG_GPR_PIX struct + */ + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_PIX_MASK \ + (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) + +#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \ + ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \ + (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \ + (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \ + (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_pix_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int : 1; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + } sq_debug_gpr_pix_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_pix_t f; +} sq_debug_gpr_pix_u; + + +/* + * SQ_DEBUG_TB_STATUS_SEL struct + */ + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000 + +#define SQ_DEBUG_TB_STATUS_SEL_MASK \ + (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) + +#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \ + ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \ + (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \ + (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \ + (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \ + (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)) + +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int : 1; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + } sq_debug_tb_status_sel_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int : 1; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + } sq_debug_tb_status_sel_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tb_status_sel_t f; +} sq_debug_tb_status_sel_u; + + +/* + * SQ_DEBUG_VTX_TB_0 struct + */ + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE 1 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK 0x00200000 + +#define SQ_DEBUG_VTX_TB_0_MASK \ + (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \ + SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) + +#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \ + ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \ + (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \ + (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \ + (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \ + (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \ + (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \ + (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)) + +#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int : 10; + } sq_debug_vtx_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int : 10; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + } sq_debug_vtx_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_0_t f; +} sq_debug_vtx_tb_0_u; + + +/* + * SQ_DEBUG_VTX_TB_1 struct + */ + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff + +#define SQ_DEBUG_VTX_TB_1_MASK \ + (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) + +#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \ + ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)) + +#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \ + ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \ + sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + unsigned int : 16; + } sq_debug_vtx_tb_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int : 16; + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + } sq_debug_vtx_tb_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_1_t f; +} sq_debug_vtx_tb_1_u; + + +/* + * SQ_DEBUG_VTX_TB_STATUS_REG struct + */ + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \ + (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) + +#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \ + ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \ + ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \ + sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_status_reg_t f; +} sq_debug_vtx_tb_status_reg_u; + + +/* + * SQ_DEBUG_VTX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) + +#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \ + ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \ + ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \ + sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_state_mem_t f; +} sq_debug_vtx_tb_state_mem_u; + + +/* + * SQ_DEBUG_PIX_TB_0 struct + */ + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE 1 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25 +#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT 31 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000 +#define SQ_DEBUG_PIX_TB_0_BUSY_MASK 0x80000000 + +#define SQ_DEBUG_PIX_TB_0_MASK \ + (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_BUSY_MASK) + +#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \ + ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \ + (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \ + (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \ + (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \ + (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \ + (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)) + +#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + } sq_debug_pix_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + } sq_debug_pix_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_0_t f; +} sq_debug_pix_tb_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \ + ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \ + ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \ + sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_0_t f; +} sq_debug_pix_tb_status_reg_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \ + ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \ + ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \ + sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_1_t f; +} sq_debug_pix_tb_status_reg_1_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \ + ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \ + ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \ + sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_2_t f; +} sq_debug_pix_tb_status_reg_2_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \ + ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \ + ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \ + sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_3_t f; +} sq_debug_pix_tb_status_reg_3_u; + + +/* + * SQ_DEBUG_PIX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) + +#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \ + ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \ + ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \ + sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_state_mem_t f; +} sq_debug_pix_tb_state_mem_u; + + +/* + * SQ_PERFCOUNTER0_SELECT struct + */ + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER0_SELECT_MASK \ + (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \ + ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \ + sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sq_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_select_t f; +} sq_perfcounter0_select_u; + + +/* + * SQ_PERFCOUNTER1_SELECT struct + */ + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER1_SELECT_MASK \ + (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \ + ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \ + sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } sq_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_select_t f; +} sq_perfcounter1_select_u; + + +/* + * SQ_PERFCOUNTER2_SELECT struct + */ + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER2_SELECT_MASK \ + (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \ + ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \ + sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } sq_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_select_t f; +} sq_perfcounter2_select_u; + + +/* + * SQ_PERFCOUNTER3_SELECT struct + */ + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER3_SELECT_MASK \ + (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \ + ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \ + sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } sq_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_select_t f; +} sq_perfcounter3_select_u; + + +/* + * SQ_PERFCOUNTER0_LOW struct + */ + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER0_LOW_MASK \ + (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \ + ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \ + sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_low_t f; +} sq_perfcounter0_low_u; + + +/* + * SQ_PERFCOUNTER0_HI struct + */ + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER0_HI_MASK \ + (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \ + ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \ + sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sq_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_hi_t f; +} sq_perfcounter0_hi_u; + + +/* + * SQ_PERFCOUNTER1_LOW struct + */ + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER1_LOW_MASK \ + (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \ + ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \ + sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_low_t f; +} sq_perfcounter1_low_u; + + +/* + * SQ_PERFCOUNTER1_HI struct + */ + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER1_HI_MASK \ + (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \ + ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \ + sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } sq_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_hi_t f; +} sq_perfcounter1_hi_u; + + +/* + * SQ_PERFCOUNTER2_LOW struct + */ + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER2_LOW_MASK \ + (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \ + ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \ + sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_low_t f; +} sq_perfcounter2_low_u; + + +/* + * SQ_PERFCOUNTER2_HI struct + */ + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER2_HI_MASK \ + (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \ + ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \ + sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } sq_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_hi_t f; +} sq_perfcounter2_hi_u; + + +/* + * SQ_PERFCOUNTER3_LOW struct + */ + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER3_LOW_MASK \ + (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \ + ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \ + sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_low_t f; +} sq_perfcounter3_low_u; + + +/* + * SQ_PERFCOUNTER3_HI struct + */ + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER3_HI_MASK \ + (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \ + ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \ + sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } sq_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_hi_t f; +} sq_perfcounter3_hi_u; + + +/* + * SX_PERFCOUNTER0_SELECT struct + */ + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SX_PERFCOUNTER0_SELECT_MASK \ + (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SX_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \ + ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \ + sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sx_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sx_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_select_t f; +} sx_perfcounter0_select_u; + + +/* + * SX_PERFCOUNTER0_LOW struct + */ + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SX_PERFCOUNTER0_LOW_MASK \ + (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \ + ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \ + sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_low_t f; +} sx_perfcounter0_low_u; + + +/* + * SX_PERFCOUNTER0_HI struct + */ + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SX_PERFCOUNTER0_HI_MASK \ + (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \ + ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \ + sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sx_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sx_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_hi_t f; +} sx_perfcounter0_hi_u; + + +/* + * SQ_INSTRUCTION_ALU_0 struct + */ + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000 + +#define SQ_INSTRUCTION_ALU_0_MASK \ + (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) + +#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \ + ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \ + (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \ + (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \ + (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \ + (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \ + (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \ + (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \ + (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \ + (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \ + (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \ + (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + } sq_instruction_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + } sq_instruction_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_0_t f; +} sq_instruction_alu_0_u; + + +/* + * SQ_INSTRUCTION_ALU_1 struct + */ + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_1_MASK \ + (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \ + SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) + +#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \ + ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \ + (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \ + (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \ + (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \ + (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \ + (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \ + (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \ + (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \ + (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \ + (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \ + (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \ + (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \ + (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \ + (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \ + (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \ + (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \ + (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \ + (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)) + +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + } sq_instruction_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + } sq_instruction_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_1_t f; +} sq_instruction_alu_1_u; + + +/* + * SQ_INSTRUCTION_ALU_2 struct + */ + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_2_MASK \ + (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \ + SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) + +#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \ + ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \ + (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \ + (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \ + (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \ + (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \ + (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \ + (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \ + (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \ + (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \ + (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \ + (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \ + (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \ + (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)) + +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + } sq_instruction_alu_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + } sq_instruction_alu_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_2_t f; +} sq_instruction_alu_2_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_0 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_0_MASK \ + (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \ + ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \ + (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + } sq_instruction_cf_exec_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + } sq_instruction_cf_exec_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_0_t f; +} sq_instruction_cf_exec_0_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_1 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_1_MASK \ + (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \ + ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + } sq_instruction_cf_exec_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + } sq_instruction_cf_exec_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_1_t f; +} sq_instruction_cf_exec_1_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_2 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_EXEC_2_MASK \ + (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \ + ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \ + (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + } sq_instruction_cf_exec_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + } sq_instruction_cf_exec_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_2_t f; +} sq_instruction_cf_exec_2_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_0 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000 + +#define SQ_INSTRUCTION_CF_LOOP_0_MASK \ + (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \ + (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + } sq_instruction_cf_loop_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + } sq_instruction_cf_loop_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_0_t f; +} sq_instruction_cf_loop_0_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_1 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000 + +#define SQ_INSTRUCTION_CF_LOOP_1_MASK \ + (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + } sq_instruction_cf_loop_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + } sq_instruction_cf_loop_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_1_t f; +} sq_instruction_cf_loop_1_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_2 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_LOOP_2_MASK \ + (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \ + ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + } sq_instruction_cf_loop_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + } sq_instruction_cf_loop_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_2_t f; +} sq_instruction_cf_loop_2_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_0 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \ + (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_0_t f; +} sq_instruction_cf_jmp_call_0_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_1 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \ + ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \ + (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_1_t f; +} sq_instruction_cf_jmp_call_1_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_2 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_2_t f; +} sq_instruction_cf_jmp_call_2_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_0 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0 + +#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \ + ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + } sq_instruction_cf_alloc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + } sq_instruction_cf_alloc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_0_t f; +} sq_instruction_cf_alloc_0_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_1 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000 + +#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \ + (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + } sq_instruction_cf_alloc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + } sq_instruction_cf_alloc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_1_t f; +} sq_instruction_cf_alloc_1_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_2 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + } sq_instruction_cf_alloc_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + } sq_instruction_cf_alloc_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_2_t f; +} sq_instruction_cf_alloc_2_u; + + +/* + * SQ_INSTRUCTION_TFETCH_0 struct + */ + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000 + +#define SQ_INSTRUCTION_TFETCH_0_MASK \ + (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \ + SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) + +#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \ + ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \ + (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \ + (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \ + (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \ + (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \ + (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \ + (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + } sq_instruction_tfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + } sq_instruction_tfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_0_t f; +} sq_instruction_tfetch_0_u; + + +/* + * SQ_INSTRUCTION_TFETCH_1 struct + */ + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_1_MASK \ + (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \ + (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \ + (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \ + (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \ + (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \ + (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \ + (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \ + (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \ + (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \ + (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_tfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_tfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_1_t f; +} sq_instruction_tfetch_1_u; + + +/* + * SQ_INSTRUCTION_TFETCH_2 struct + */ + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_2_MASK \ + (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \ + SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \ + ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \ + (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \ + (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \ + (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \ + (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \ + (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \ + (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_tfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + } sq_instruction_tfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_2_t f; +} sq_instruction_tfetch_2_u; + + +/* + * SQ_INSTRUCTION_VFETCH_0 struct + */ + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000 + +#define SQ_INSTRUCTION_VFETCH_0_MASK \ + (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) + +#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \ + ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \ + (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \ + (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \ + (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \ + (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int : 3; + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + } sq_instruction_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + unsigned int : 3; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + } sq_instruction_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_0_t f; +} sq_instruction_vfetch_0_u; + + +/* + * SQ_INSTRUCTION_VFETCH_1 struct + */ + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_1_MASK \ + (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \ + SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \ + (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \ + (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \ + (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \ + (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \ + (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_1_t f; +} sq_instruction_vfetch_1_u; + + +/* + * SQ_INSTRUCTION_VFETCH_2 struct + */ + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_2_MASK \ + (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \ + SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \ + SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \ + ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \ + (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + unsigned int : 8; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 7; + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_vfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + unsigned int : 7; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 8; + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + } sq_instruction_vfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_2_t f; +} sq_instruction_vfetch_2_u; + + +/* + * SQ_CONSTANT_0 struct + */ + +#define SQ_CONSTANT_0_RED_SIZE 32 + +#define SQ_CONSTANT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_0_MASK \ + (SQ_CONSTANT_0_RED_MASK) + +#define SQ_CONSTANT_0(red) \ + ((red << SQ_CONSTANT_0_RED_SHIFT)) + +#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \ + ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT) + +#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \ + sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_0_t f; +} sq_constant_0_u; + + +/* + * SQ_CONSTANT_1 struct + */ + +#define SQ_CONSTANT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_1_MASK \ + (SQ_CONSTANT_1_GREEN_MASK) + +#define SQ_CONSTANT_1(green) \ + ((green << SQ_CONSTANT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \ + ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \ + sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_1_t f; +} sq_constant_1_u; + + +/* + * SQ_CONSTANT_2 struct + */ + +#define SQ_CONSTANT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_2_MASK \ + (SQ_CONSTANT_2_BLUE_MASK) + +#define SQ_CONSTANT_2(blue) \ + ((blue << SQ_CONSTANT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \ + ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \ + sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_2_t f; +} sq_constant_2_u; + + +/* + * SQ_CONSTANT_3 struct + */ + +#define SQ_CONSTANT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_3_MASK \ + (SQ_CONSTANT_3_ALPHA_MASK) + +#define SQ_CONSTANT_3(alpha) \ + ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \ + ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \ + sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_3_t f; +} sq_constant_3_u; + + +/* + * SQ_FETCH_0 struct + */ + +#define SQ_FETCH_0_VALUE_SIZE 32 + +#define SQ_FETCH_0_VALUE_SHIFT 0 + +#define SQ_FETCH_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_0_MASK \ + (SQ_FETCH_0_VALUE_MASK) + +#define SQ_FETCH_0(value) \ + ((value << SQ_FETCH_0_VALUE_SHIFT)) + +#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \ + ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT) + +#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \ + sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_0_t f; +} sq_fetch_0_u; + + +/* + * SQ_FETCH_1 struct + */ + +#define SQ_FETCH_1_VALUE_SIZE 32 + +#define SQ_FETCH_1_VALUE_SHIFT 0 + +#define SQ_FETCH_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_1_MASK \ + (SQ_FETCH_1_VALUE_MASK) + +#define SQ_FETCH_1(value) \ + ((value << SQ_FETCH_1_VALUE_SHIFT)) + +#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \ + ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT) + +#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \ + sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_1_t f; +} sq_fetch_1_u; + + +/* + * SQ_FETCH_2 struct + */ + +#define SQ_FETCH_2_VALUE_SIZE 32 + +#define SQ_FETCH_2_VALUE_SHIFT 0 + +#define SQ_FETCH_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_2_MASK \ + (SQ_FETCH_2_VALUE_MASK) + +#define SQ_FETCH_2(value) \ + ((value << SQ_FETCH_2_VALUE_SHIFT)) + +#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \ + ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT) + +#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \ + sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_2_t f; +} sq_fetch_2_u; + + +/* + * SQ_FETCH_3 struct + */ + +#define SQ_FETCH_3_VALUE_SIZE 32 + +#define SQ_FETCH_3_VALUE_SHIFT 0 + +#define SQ_FETCH_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_3_MASK \ + (SQ_FETCH_3_VALUE_MASK) + +#define SQ_FETCH_3(value) \ + ((value << SQ_FETCH_3_VALUE_SHIFT)) + +#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \ + ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT) + +#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \ + sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_3_t f; +} sq_fetch_3_u; + + +/* + * SQ_FETCH_4 struct + */ + +#define SQ_FETCH_4_VALUE_SIZE 32 + +#define SQ_FETCH_4_VALUE_SHIFT 0 + +#define SQ_FETCH_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_4_MASK \ + (SQ_FETCH_4_VALUE_MASK) + +#define SQ_FETCH_4(value) \ + ((value << SQ_FETCH_4_VALUE_SHIFT)) + +#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \ + ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT) + +#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \ + sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_4_t f; +} sq_fetch_4_u; + + +/* + * SQ_FETCH_5 struct + */ + +#define SQ_FETCH_5_VALUE_SIZE 32 + +#define SQ_FETCH_5_VALUE_SHIFT 0 + +#define SQ_FETCH_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_5_MASK \ + (SQ_FETCH_5_VALUE_MASK) + +#define SQ_FETCH_5(value) \ + ((value << SQ_FETCH_5_VALUE_SHIFT)) + +#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \ + ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT) + +#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \ + sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_5_t f; +} sq_fetch_5_u; + + +/* + * SQ_CONSTANT_VFETCH_0 struct + */ + +#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0 +#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001 +#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_0_MASK \ + (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \ + SQ_CONSTANT_VFETCH_0_STATE_MASK | \ + SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \ + ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \ + (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \ + (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + } sq_constant_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + } sq_constant_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_0_t f; +} sq_constant_vfetch_0_u; + + +/* + * SQ_CONSTANT_VFETCH_1 struct + */ + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_1_MASK \ + (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \ + SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \ + ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \ + (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + } sq_constant_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + } sq_constant_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_1_t f; +} sq_constant_vfetch_1_u; + + +/* + * SQ_CONSTANT_T2 struct + */ + +#define SQ_CONSTANT_T2_VALUE_SIZE 32 + +#define SQ_CONSTANT_T2_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T2_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T2_MASK \ + (SQ_CONSTANT_T2_VALUE_MASK) + +#define SQ_CONSTANT_T2(value) \ + ((value << SQ_CONSTANT_T2_VALUE_SHIFT)) + +#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \ + ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT) + +#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \ + sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t2_t f; +} sq_constant_t2_u; + + +/* + * SQ_CONSTANT_T3 struct + */ + +#define SQ_CONSTANT_T3_VALUE_SIZE 32 + +#define SQ_CONSTANT_T3_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T3_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T3_MASK \ + (SQ_CONSTANT_T3_VALUE_MASK) + +#define SQ_CONSTANT_T3(value) \ + ((value << SQ_CONSTANT_T3_VALUE_SHIFT)) + +#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \ + ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT) + +#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \ + sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t3_t f; +} sq_constant_t3_u; + + +/* + * SQ_CF_BOOLEANS struct + */ + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_BOOLEANS_MASK \ + (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_booleans_t f; +} sq_cf_booleans_u; + + +/* + * SQ_CF_LOOP struct + */ + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_LOOP_MASK \ + (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_loop_t f; +} sq_cf_loop_u; + + +/* + * SQ_CONSTANT_RT_0 struct + */ + +#define SQ_CONSTANT_RT_0_RED_SIZE 32 + +#define SQ_CONSTANT_RT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_RT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_RT_0_MASK \ + (SQ_CONSTANT_RT_0_RED_MASK) + +#define SQ_CONSTANT_RT_0(red) \ + ((red << SQ_CONSTANT_RT_0_RED_SHIFT)) + +#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \ + ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT) + +#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \ + sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_0_t f; +} sq_constant_rt_0_u; + + +/* + * SQ_CONSTANT_RT_1 struct + */ + +#define SQ_CONSTANT_RT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_RT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_RT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_RT_1_MASK \ + (SQ_CONSTANT_RT_1_GREEN_MASK) + +#define SQ_CONSTANT_RT_1(green) \ + ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \ + ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \ + sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_1_t f; +} sq_constant_rt_1_u; + + +/* + * SQ_CONSTANT_RT_2 struct + */ + +#define SQ_CONSTANT_RT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_RT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_RT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_RT_2_MASK \ + (SQ_CONSTANT_RT_2_BLUE_MASK) + +#define SQ_CONSTANT_RT_2(blue) \ + ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \ + ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \ + sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_2_t f; +} sq_constant_rt_2_u; + + +/* + * SQ_CONSTANT_RT_3 struct + */ + +#define SQ_CONSTANT_RT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_RT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_RT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_RT_3_MASK \ + (SQ_CONSTANT_RT_3_ALPHA_MASK) + +#define SQ_CONSTANT_RT_3(alpha) \ + ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \ + ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \ + sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_3_t f; +} sq_constant_rt_3_u; + + +/* + * SQ_FETCH_RT_0 struct + */ + +#define SQ_FETCH_RT_0_VALUE_SIZE 32 + +#define SQ_FETCH_RT_0_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_0_MASK \ + (SQ_FETCH_RT_0_VALUE_MASK) + +#define SQ_FETCH_RT_0(value) \ + ((value << SQ_FETCH_RT_0_VALUE_SHIFT)) + +#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \ + ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT) + +#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \ + sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_0_t f; +} sq_fetch_rt_0_u; + + +/* + * SQ_FETCH_RT_1 struct + */ + +#define SQ_FETCH_RT_1_VALUE_SIZE 32 + +#define SQ_FETCH_RT_1_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_1_MASK \ + (SQ_FETCH_RT_1_VALUE_MASK) + +#define SQ_FETCH_RT_1(value) \ + ((value << SQ_FETCH_RT_1_VALUE_SHIFT)) + +#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \ + ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT) + +#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \ + sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_1_t f; +} sq_fetch_rt_1_u; + + +/* + * SQ_FETCH_RT_2 struct + */ + +#define SQ_FETCH_RT_2_VALUE_SIZE 32 + +#define SQ_FETCH_RT_2_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_2_MASK \ + (SQ_FETCH_RT_2_VALUE_MASK) + +#define SQ_FETCH_RT_2(value) \ + ((value << SQ_FETCH_RT_2_VALUE_SHIFT)) + +#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \ + ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT) + +#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \ + sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_2_t f; +} sq_fetch_rt_2_u; + + +/* + * SQ_FETCH_RT_3 struct + */ + +#define SQ_FETCH_RT_3_VALUE_SIZE 32 + +#define SQ_FETCH_RT_3_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_3_MASK \ + (SQ_FETCH_RT_3_VALUE_MASK) + +#define SQ_FETCH_RT_3(value) \ + ((value << SQ_FETCH_RT_3_VALUE_SHIFT)) + +#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \ + ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT) + +#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \ + sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_3_t f; +} sq_fetch_rt_3_u; + + +/* + * SQ_FETCH_RT_4 struct + */ + +#define SQ_FETCH_RT_4_VALUE_SIZE 32 + +#define SQ_FETCH_RT_4_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_4_MASK \ + (SQ_FETCH_RT_4_VALUE_MASK) + +#define SQ_FETCH_RT_4(value) \ + ((value << SQ_FETCH_RT_4_VALUE_SHIFT)) + +#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \ + ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT) + +#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \ + sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_4_t f; +} sq_fetch_rt_4_u; + + +/* + * SQ_FETCH_RT_5 struct + */ + +#define SQ_FETCH_RT_5_VALUE_SIZE 32 + +#define SQ_FETCH_RT_5_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_5_MASK \ + (SQ_FETCH_RT_5_VALUE_MASK) + +#define SQ_FETCH_RT_5(value) \ + ((value << SQ_FETCH_RT_5_VALUE_SHIFT)) + +#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \ + ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT) + +#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \ + sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_5_t f; +} sq_fetch_rt_5_u; + + +/* + * SQ_CF_RT_BOOLEANS struct + */ + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_RT_BOOLEANS_MASK \ + (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_rt_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_rt_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_booleans_t f; +} sq_cf_rt_booleans_u; + + +/* + * SQ_CF_RT_LOOP struct + */ + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_RT_LOOP_MASK \ + (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_rt_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_rt_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_loop_t f; +} sq_cf_rt_loop_u; + + +/* + * SQ_VS_PROGRAM struct + */ + +#define SQ_VS_PROGRAM_BASE_SIZE 12 +#define SQ_VS_PROGRAM_SIZE_SIZE 12 + +#define SQ_VS_PROGRAM_BASE_SHIFT 0 +#define SQ_VS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_VS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_VS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_VS_PROGRAM_MASK \ + (SQ_VS_PROGRAM_BASE_MASK | \ + SQ_VS_PROGRAM_SIZE_MASK) + +#define SQ_VS_PROGRAM(base, size) \ + ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_VS_PROGRAM_SIZE_SHIFT)) + +#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT) + +#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_vs_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int : 8; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + } sq_vs_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_program_t f; +} sq_vs_program_u; + + +/* + * SQ_PS_PROGRAM struct + */ + +#define SQ_PS_PROGRAM_BASE_SIZE 12 +#define SQ_PS_PROGRAM_SIZE_SIZE 12 + +#define SQ_PS_PROGRAM_BASE_SHIFT 0 +#define SQ_PS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_PS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_PS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_PS_PROGRAM_MASK \ + (SQ_PS_PROGRAM_BASE_MASK | \ + SQ_PS_PROGRAM_SIZE_MASK) + +#define SQ_PS_PROGRAM(base, size) \ + ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_PS_PROGRAM_SIZE_SHIFT)) + +#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT) + +#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_ps_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int : 8; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + } sq_ps_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_program_t f; +} sq_ps_program_u; + + +/* + * SQ_CF_PROGRAM_SIZE struct + */ + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000 + +#define SQ_CF_PROGRAM_SIZE_MASK \ + (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \ + SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) + +#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \ + ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \ + (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)) + +#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 9; + } sq_cf_program_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int : 9; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + } sq_cf_program_size_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_program_size_t f; +} sq_cf_program_size_u; + + +/* + * SQ_INTERPOLATOR_CNTL struct + */ + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000 + +#define SQ_INTERPOLATOR_CNTL_MASK \ + (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \ + SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) + +#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \ + ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \ + (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)) + +#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + } sq_interpolator_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + } sq_interpolator_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_interpolator_cntl_t f; +} sq_interpolator_cntl_u; + + +/* + * SQ_PROGRAM_CNTL struct + */ + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f +#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000 +#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000 + +#define SQ_PROGRAM_CNTL_MASK \ + (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) + +#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \ + ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \ + (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \ + (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \ + (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \ + (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \ + (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \ + (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \ + (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \ + (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \ + (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)) + +#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + } sq_program_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + } sq_program_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_program_cntl_t f; +} sq_program_cntl_u; + + +/* + * SQ_WRAPPING_0 struct + */ + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f +#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0 +#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00 +#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000 +#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000 +#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000 +#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000 +#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000 + +#define SQ_WRAPPING_0_MASK \ + (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_7_MASK) + +#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \ + ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \ + (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \ + (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \ + (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \ + (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \ + (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \ + (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \ + (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)) + +#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + } sq_wrapping_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + } sq_wrapping_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_0_t f; +} sq_wrapping_0_u; + + +/* + * SQ_WRAPPING_1 struct + */ + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f +#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0 +#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00 +#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000 +#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000 +#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000 +#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000 +#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000 + +#define SQ_WRAPPING_1_MASK \ + (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_15_MASK) + +#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \ + ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \ + (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \ + (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \ + (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \ + (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \ + (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \ + (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \ + (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)) + +#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + } sq_wrapping_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + } sq_wrapping_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_1_t f; +} sq_wrapping_1_u; + + +/* + * SQ_VS_CONST struct + */ + +#define SQ_VS_CONST_BASE_SIZE 9 +#define SQ_VS_CONST_SIZE_SIZE 9 + +#define SQ_VS_CONST_BASE_SHIFT 0 +#define SQ_VS_CONST_SIZE_SHIFT 12 + +#define SQ_VS_CONST_BASE_MASK 0x000001ff +#define SQ_VS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_VS_CONST_MASK \ + (SQ_VS_CONST_BASE_MASK | \ + SQ_VS_CONST_SIZE_MASK) + +#define SQ_VS_CONST(base, size) \ + ((base << SQ_VS_CONST_BASE_SHIFT) | \ + (size << SQ_VS_CONST_SIZE_SHIFT)) + +#define SQ_VS_CONST_GET_BASE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT) + +#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int base : SQ_VS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_vs_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int : 11; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_VS_CONST_BASE_SIZE; + } sq_vs_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_const_t f; +} sq_vs_const_u; + + +/* + * SQ_PS_CONST struct + */ + +#define SQ_PS_CONST_BASE_SIZE 9 +#define SQ_PS_CONST_SIZE_SIZE 9 + +#define SQ_PS_CONST_BASE_SHIFT 0 +#define SQ_PS_CONST_SIZE_SHIFT 12 + +#define SQ_PS_CONST_BASE_MASK 0x000001ff +#define SQ_PS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_PS_CONST_MASK \ + (SQ_PS_CONST_BASE_MASK | \ + SQ_PS_CONST_SIZE_MASK) + +#define SQ_PS_CONST(base, size) \ + ((base << SQ_PS_CONST_BASE_SHIFT) | \ + (size << SQ_PS_CONST_SIZE_SHIFT)) + +#define SQ_PS_CONST_GET_BASE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT) + +#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int base : SQ_PS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_ps_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int : 11; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_PS_CONST_BASE_SIZE; + } sq_ps_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_const_t f; +} sq_ps_const_u; + + +/* + * SQ_CONTEXT_MISC struct + */ + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000 + +#define SQ_CONTEXT_MISC_MASK \ + (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \ + SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \ + SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \ + SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \ + SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) + +#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \ + ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \ + (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \ + (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \ + (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \ + (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \ + (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \ + (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)) + +#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int : 4; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int : 13; + } sq_context_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int : 13; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int : 4; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + } sq_context_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_context_misc_t f; +} sq_context_misc_u; + + +/* + * SQ_CF_RD_BASE struct + */ + +#define SQ_CF_RD_BASE_RD_BASE_SIZE 3 + +#define SQ_CF_RD_BASE_RD_BASE_SHIFT 0 + +#define SQ_CF_RD_BASE_RD_BASE_MASK 0x00000007 + +#define SQ_CF_RD_BASE_MASK \ + (SQ_CF_RD_BASE_RD_BASE_MASK) + +#define SQ_CF_RD_BASE(rd_base) \ + ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)) + +#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \ + ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \ + sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + unsigned int : 29; + } sq_cf_rd_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int : 29; + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + } sq_cf_rd_base_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rd_base_t f; +} sq_cf_rd_base_u; + + +/* + * SQ_DEBUG_MISC_0 struct + */ + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000 + +#define SQ_DEBUG_MISC_0_MASK \ + (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) + +#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \ + ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \ + (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \ + (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \ + (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)) + +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 5; + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + } sq_debug_misc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + unsigned int : 5; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + } sq_debug_misc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_0_t f; +} sq_debug_misc_0_u; + + +/* + * SQ_DEBUG_MISC_1 struct + */ + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000 + +#define SQ_DEBUG_MISC_1_MASK \ + (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \ + SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \ + SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \ + SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) + +#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \ + ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \ + (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \ + (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \ + (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)) + +#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int : 6; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int : 5; + } sq_debug_misc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int : 5; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int : 6; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + } sq_debug_misc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_1_t f; +} sq_debug_misc_1_u; + + +#endif + + +#if !defined (_SX_FIDDLE_H) +#define _SX_FIDDLE_H + +/***************************************************************************************************************** + * + * sx_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_TP_FIDDLE_H) +#define _TP_FIDDLE_H + +/***************************************************************************************************************** + * + * tp_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * TC_CNTL_STATUS struct + */ + +#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2 +#define TC_CNTL_STATUS_TC_BUSY_SIZE 1 + +#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18 +#define TC_CNTL_STATUS_TC_BUSY_SHIFT 31 + +#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000 +#define TC_CNTL_STATUS_TC_BUSY_MASK 0x80000000 + +#define TC_CNTL_STATUS_MASK \ + (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \ + TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \ + TC_CNTL_STATUS_TC_BUSY_MASK) + +#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \ + ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \ + (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \ + (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)) + +#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + unsigned int : 17; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 11; + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + } tc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + unsigned int : 11; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 17; + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + } tc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tc_cntl_status_t f; +} tc_cntl_status_u; + + +/* + * TCR_CHICKEN struct + */ + +#define TCR_CHICKEN_SPARE_SIZE 32 + +#define TCR_CHICKEN_SPARE_SHIFT 0 + +#define TCR_CHICKEN_SPARE_MASK 0xffffffff + +#define TCR_CHICKEN_MASK \ + (TCR_CHICKEN_SPARE_MASK) + +#define TCR_CHICKEN(spare) \ + ((spare << TCR_CHICKEN_SPARE_SHIFT)) + +#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \ + ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT) + +#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \ + tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_chicken_t f; +} tcr_chicken_u; + + +/* + * TCF_CHICKEN struct + */ + +#define TCF_CHICKEN_SPARE_SIZE 32 + +#define TCF_CHICKEN_SPARE_SHIFT 0 + +#define TCF_CHICKEN_SPARE_MASK 0xffffffff + +#define TCF_CHICKEN_MASK \ + (TCF_CHICKEN_SPARE_MASK) + +#define TCF_CHICKEN(spare) \ + ((spare << TCF_CHICKEN_SPARE_SHIFT)) + +#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \ + ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT) + +#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \ + tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_chicken_t f; +} tcf_chicken_u; + + +/* + * TCM_CHICKEN struct + */ + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1 +#define TCM_CHICKEN_SPARE_SIZE 23 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8 +#define TCM_CHICKEN_SPARE_SHIFT 9 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100 +#define TCM_CHICKEN_SPARE_MASK 0xfffffe00 + +#define TCM_CHICKEN_MASK \ + (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \ + TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \ + TCM_CHICKEN_SPARE_MASK) + +#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \ + ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \ + (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \ + (spare << TCM_CHICKEN_SPARE_SHIFT)) + +#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT) + +#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + } tcm_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + } tcm_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_chicken_t f; +} tcm_chicken_u; + + +/* + * TCR_PERFCOUNTER0_SELECT struct + */ + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER0_SELECT_MASK \ + (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \ + ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \ + tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_select_t f; +} tcr_perfcounter0_select_u; + + +/* + * TCR_PERFCOUNTER1_SELECT struct + */ + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER1_SELECT_MASK \ + (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \ + ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \ + tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_select_t f; +} tcr_perfcounter1_select_u; + + +/* + * TCR_PERFCOUNTER0_HI struct + */ + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER0_HI_MASK \ + (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \ + ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \ + tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_hi_t f; +} tcr_perfcounter0_hi_u; + + +/* + * TCR_PERFCOUNTER1_HI struct + */ + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER1_HI_MASK \ + (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \ + ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \ + tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_hi_t f; +} tcr_perfcounter1_hi_u; + + +/* + * TCR_PERFCOUNTER0_LOW struct + */ + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER0_LOW_MASK \ + (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \ + ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \ + tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_low_t f; +} tcr_perfcounter0_low_u; + + +/* + * TCR_PERFCOUNTER1_LOW struct + */ + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER1_LOW_MASK \ + (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \ + ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \ + tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_low_t f; +} tcr_perfcounter1_low_u; + + +/* + * TP_TC_CLKGATE_CNTL struct + */ + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038 + +#define TP_TC_CLKGATE_CNTL_MASK \ + (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \ + TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) + +#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \ + ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \ + (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)) + +#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int : 26; + } tp_tc_clkgate_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int : 26; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + } tp_tc_clkgate_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + tp_tc_clkgate_cntl_t f; +} tp_tc_clkgate_cntl_u; + + +/* + * TPC_CNTL_STATUS struct + */ + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BUSY_SIZE 1 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15 +#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17 +#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19 +#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22 +#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23 +#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25 +#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27 +#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30 +#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000 +#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000 +#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000 +#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000 +#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000 +#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000 +#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000 +#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000 +#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000 +#define TPC_CNTL_STATUS_TPC_BUSY_MASK 0x80000000 + +#define TPC_CNTL_STATUS_MASK \ + (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTR_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TF_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \ + TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \ + TPC_CNTL_STATUS_TPC_BUSY_MASK) + +#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \ + ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \ + (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \ + (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \ + (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \ + (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \ + (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \ + (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \ + (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \ + (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \ + (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \ + (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \ + (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \ + (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \ + (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \ + (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \ + (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \ + (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \ + (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \ + (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \ + (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \ + (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \ + (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \ + (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \ + (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \ + (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \ + (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \ + (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \ + (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)) + +#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int : 1; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int : 1; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + } tpc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int : 1; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int : 1; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + } tpc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_cntl_status_t f; +} tpc_cntl_status_u; + + +/* + * TPC_DEBUG0 struct + */ + +#define TPC_DEBUG0_LOD_CNTL_SIZE 2 +#define TPC_DEBUG0_IC_CTR_SIZE 2 +#define TPC_DEBUG0_WALKER_CNTL_SIZE 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SIZE 3 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1 +#define TPC_DEBUG0_WALKER_STATE_SIZE 10 +#define TPC_DEBUG0_ALIGNER_STATE_SIZE 2 +#define TPC_DEBUG0_REG_CLK_EN_SIZE 1 +#define TPC_DEBUG0_TPC_CLK_EN_SIZE 1 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE 1 + +#define TPC_DEBUG0_LOD_CNTL_SHIFT 0 +#define TPC_DEBUG0_IC_CTR_SHIFT 2 +#define TPC_DEBUG0_WALKER_CNTL_SHIFT 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT 8 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12 +#define TPC_DEBUG0_WALKER_STATE_SHIFT 16 +#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26 +#define TPC_DEBUG0_REG_CLK_EN_SHIFT 29 +#define TPC_DEBUG0_TPC_CLK_EN_SHIFT 30 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT 31 + +#define TPC_DEBUG0_LOD_CNTL_MASK 0x00000003 +#define TPC_DEBUG0_IC_CTR_MASK 0x0000000c +#define TPC_DEBUG0_WALKER_CNTL_MASK 0x000000f0 +#define TPC_DEBUG0_ALIGNER_CNTL_MASK 0x00000700 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000 +#define TPC_DEBUG0_WALKER_STATE_MASK 0x03ff0000 +#define TPC_DEBUG0_ALIGNER_STATE_MASK 0x0c000000 +#define TPC_DEBUG0_REG_CLK_EN_MASK 0x20000000 +#define TPC_DEBUG0_TPC_CLK_EN_MASK 0x40000000 +#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK 0x80000000 + +#define TPC_DEBUG0_MASK \ + (TPC_DEBUG0_LOD_CNTL_MASK | \ + TPC_DEBUG0_IC_CTR_MASK | \ + TPC_DEBUG0_WALKER_CNTL_MASK | \ + TPC_DEBUG0_ALIGNER_CNTL_MASK | \ + TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \ + TPC_DEBUG0_WALKER_STATE_MASK | \ + TPC_DEBUG0_ALIGNER_STATE_MASK | \ + TPC_DEBUG0_REG_CLK_EN_MASK | \ + TPC_DEBUG0_TPC_CLK_EN_MASK | \ + TPC_DEBUG0_SQ_TP_WAKEUP_MASK) + +#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \ + ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \ + (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \ + (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \ + (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \ + (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \ + (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \ + (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \ + (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \ + (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \ + (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)) + +#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int : 1; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 3; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int : 1; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + } tpc_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int : 1; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int : 3; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 1; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + } tpc_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug0_t f; +} tpc_debug0_u; + + +/* + * TPC_DEBUG1 struct + */ + +#define TPC_DEBUG1_UNUSED_SIZE 1 + +#define TPC_DEBUG1_UNUSED_SHIFT 0 + +#define TPC_DEBUG1_UNUSED_MASK 0x00000001 + +#define TPC_DEBUG1_MASK \ + (TPC_DEBUG1_UNUSED_MASK) + +#define TPC_DEBUG1(unused) \ + ((unused << TPC_DEBUG1_UNUSED_SHIFT)) + +#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \ + ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT) + +#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \ + tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + unsigned int : 31; + } tpc_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int : 31; + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + } tpc_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug1_t f; +} tpc_debug1_u; + + +/* + * TPC_CHICKEN struct + */ + +#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1 +#define TPC_CHICKEN_SPARE_SIZE 31 + +#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0 +#define TPC_CHICKEN_SPARE_SHIFT 1 + +#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001 +#define TPC_CHICKEN_SPARE_MASK 0xfffffffe + +#define TPC_CHICKEN_MASK \ + (TPC_CHICKEN_BLEND_PRECISION_MASK | \ + TPC_CHICKEN_SPARE_MASK) + +#define TPC_CHICKEN(blend_precision, spare) \ + ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \ + (spare << TPC_CHICKEN_SPARE_SHIFT)) + +#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT) + +#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + } tpc_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + } tpc_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_chicken_t f; +} tpc_chicken_u; + + +/* + * TP0_CNTL_STATUS struct + */ + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1 +#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TP_BUSY_SIZE 1 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14 +#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16 +#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17 +#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18 +#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19 +#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21 +#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23 +#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25 +#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27 +#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29 +#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30 +#define TP0_CNTL_STATUS_TP_BUSY_SHIFT 31 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200 +#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000 +#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000 +#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000 +#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000 +#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000 +#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000 +#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000 +#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000 +#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000 +#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000 +#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000 +#define TP0_CNTL_STATUS_TP_BUSY_MASK 0x80000000 + +#define TP0_CNTL_STATUS_MASK \ + (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_IN_LC_RTS_MASK | \ + TP0_CNTL_STATUS_LC_LA_RTS_MASK | \ + TP0_CNTL_STATUS_LA_FL_RTS_MASK | \ + TP0_CNTL_STATUS_FL_TA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \ + TP0_CNTL_STATUS_TB_TO_RTS_MASK | \ + TP0_CNTL_STATUS_TP_BUSY_MASK) + +#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \ + ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \ + (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \ + (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \ + (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \ + (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \ + (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \ + (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \ + (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \ + (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \ + (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \ + (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \ + (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \ + (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \ + (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \ + (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \ + (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \ + (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \ + (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \ + (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \ + (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \ + (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \ + (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \ + (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \ + (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \ + (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \ + (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \ + (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \ + (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \ + (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \ + (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \ + (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)) + +#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int : 1; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + } tp0_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int : 1; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + } tp0_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_cntl_status_t f; +} tp0_cntl_status_u; + + +/* + * TP0_DEBUG struct + */ + +#define TP0_DEBUG_Q_LOD_CNTL_SIZE 2 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE 1 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17 +#define TP0_DEBUG_REG_CLK_EN_SIZE 1 +#define TP0_DEBUG_PERF_CLK_EN_SIZE 1 +#define TP0_DEBUG_TP_CLK_EN_SIZE 1 +#define TP0_DEBUG_Q_WALKER_CNTL_SIZE 4 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE 3 + +#define TP0_DEBUG_Q_LOD_CNTL_SHIFT 0 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4 +#define TP0_DEBUG_REG_CLK_EN_SHIFT 21 +#define TP0_DEBUG_PERF_CLK_EN_SHIFT 22 +#define TP0_DEBUG_TP_CLK_EN_SHIFT 23 +#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT 24 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28 + +#define TP0_DEBUG_Q_LOD_CNTL_MASK 0x00000003 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK 0x00000008 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0 +#define TP0_DEBUG_REG_CLK_EN_MASK 0x00200000 +#define TP0_DEBUG_PERF_CLK_EN_MASK 0x00400000 +#define TP0_DEBUG_TP_CLK_EN_MASK 0x00800000 +#define TP0_DEBUG_Q_WALKER_CNTL_MASK 0x0f000000 +#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK 0x70000000 + +#define TP0_DEBUG_MASK \ + (TP0_DEBUG_Q_LOD_CNTL_MASK | \ + TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \ + TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \ + TP0_DEBUG_REG_CLK_EN_MASK | \ + TP0_DEBUG_PERF_CLK_EN_MASK | \ + TP0_DEBUG_TP_CLK_EN_MASK | \ + TP0_DEBUG_Q_WALKER_CNTL_MASK | \ + TP0_DEBUG_Q_ALIGNER_CNTL_MASK) + +#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \ + ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \ + (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \ + (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \ + (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \ + (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \ + (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \ + (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \ + (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)) + +#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + unsigned int : 1; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int : 1; + } tp0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int : 1; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int : 1; + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + } tp0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_debug_t f; +} tp0_debug_u; + + +/* + * TP0_CHICKEN struct + */ + +#define TP0_CHICKEN_TT_MODE_SIZE 1 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1 +#define TP0_CHICKEN_SPARE_SIZE 30 + +#define TP0_CHICKEN_TT_MODE_SHIFT 0 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1 +#define TP0_CHICKEN_SPARE_SHIFT 2 + +#define TP0_CHICKEN_TT_MODE_MASK 0x00000001 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002 +#define TP0_CHICKEN_SPARE_MASK 0xfffffffc + +#define TP0_CHICKEN_MASK \ + (TP0_CHICKEN_TT_MODE_MASK | \ + TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \ + TP0_CHICKEN_SPARE_MASK) + +#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \ + ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \ + (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \ + (spare << TP0_CHICKEN_SPARE_SHIFT)) + +#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT) + +#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + } tp0_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + } tp0_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_chicken_t f; +} tp0_chicken_u; + + +/* + * TP0_PERFCOUNTER0_SELECT struct + */ + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER0_SELECT_MASK \ + (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \ + ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \ + tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_select_t f; +} tp0_perfcounter0_select_u; + + +/* + * TP0_PERFCOUNTER0_HI struct + */ + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER0_HI_MASK \ + (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \ + ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \ + tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_hi_t f; +} tp0_perfcounter0_hi_u; + + +/* + * TP0_PERFCOUNTER0_LOW struct + */ + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER0_LOW_MASK \ + (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \ + ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \ + tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_low_t f; +} tp0_perfcounter0_low_u; + + +/* + * TP0_PERFCOUNTER1_SELECT struct + */ + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER1_SELECT_MASK \ + (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \ + ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \ + tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_select_t f; +} tp0_perfcounter1_select_u; + + +/* + * TP0_PERFCOUNTER1_HI struct + */ + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER1_HI_MASK \ + (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \ + ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \ + tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_hi_t f; +} tp0_perfcounter1_hi_u; + + +/* + * TP0_PERFCOUNTER1_LOW struct + */ + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER1_LOW_MASK \ + (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \ + ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \ + tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_low_t f; +} tp0_perfcounter1_low_u; + + +/* + * TCM_PERFCOUNTER0_SELECT struct + */ + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER0_SELECT_MASK \ + (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \ + ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \ + tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_select_t f; +} tcm_perfcounter0_select_u; + + +/* + * TCM_PERFCOUNTER1_SELECT struct + */ + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER1_SELECT_MASK \ + (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \ + ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \ + tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_select_t f; +} tcm_perfcounter1_select_u; + + +/* + * TCM_PERFCOUNTER0_HI struct + */ + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER0_HI_MASK \ + (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \ + ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \ + tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_hi_t f; +} tcm_perfcounter0_hi_u; + + +/* + * TCM_PERFCOUNTER1_HI struct + */ + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER1_HI_MASK \ + (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \ + ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \ + tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_hi_t f; +} tcm_perfcounter1_hi_u; + + +/* + * TCM_PERFCOUNTER0_LOW struct + */ + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER0_LOW_MASK \ + (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \ + ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \ + tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_low_t f; +} tcm_perfcounter0_low_u; + + +/* + * TCM_PERFCOUNTER1_LOW struct + */ + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER1_LOW_MASK \ + (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \ + ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \ + tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_low_t f; +} tcm_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER0_SELECT struct + */ + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER0_SELECT_MASK \ + (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \ + ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \ + tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_select_t f; +} tcf_perfcounter0_select_u; + + +/* + * TCF_PERFCOUNTER1_SELECT struct + */ + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER1_SELECT_MASK \ + (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \ + ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \ + tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_select_t f; +} tcf_perfcounter1_select_u; + + +/* + * TCF_PERFCOUNTER2_SELECT struct + */ + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER2_SELECT_MASK \ + (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \ + ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \ + tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_select_t f; +} tcf_perfcounter2_select_u; + + +/* + * TCF_PERFCOUNTER3_SELECT struct + */ + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER3_SELECT_MASK \ + (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \ + ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \ + tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_select_t f; +} tcf_perfcounter3_select_u; + + +/* + * TCF_PERFCOUNTER4_SELECT struct + */ + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER4_SELECT_MASK \ + (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \ + ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \ + tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter4_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter4_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_select_t f; +} tcf_perfcounter4_select_u; + + +/* + * TCF_PERFCOUNTER5_SELECT struct + */ + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER5_SELECT_MASK \ + (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \ + ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \ + tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter5_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter5_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_select_t f; +} tcf_perfcounter5_select_u; + + +/* + * TCF_PERFCOUNTER6_SELECT struct + */ + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER6_SELECT_MASK \ + (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \ + ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \ + tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter6_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter6_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_select_t f; +} tcf_perfcounter6_select_u; + + +/* + * TCF_PERFCOUNTER7_SELECT struct + */ + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER7_SELECT_MASK \ + (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \ + ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \ + tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter7_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter7_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_select_t f; +} tcf_perfcounter7_select_u; + + +/* + * TCF_PERFCOUNTER8_SELECT struct + */ + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER8_SELECT_MASK \ + (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \ + ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \ + tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter8_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter8_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_select_t f; +} tcf_perfcounter8_select_u; + + +/* + * TCF_PERFCOUNTER9_SELECT struct + */ + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER9_SELECT_MASK \ + (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \ + ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \ + tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter9_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter9_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_select_t f; +} tcf_perfcounter9_select_u; + + +/* + * TCF_PERFCOUNTER10_SELECT struct + */ + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER10_SELECT_MASK \ + (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \ + ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \ + tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter10_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter10_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_select_t f; +} tcf_perfcounter10_select_u; + + +/* + * TCF_PERFCOUNTER11_SELECT struct + */ + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER11_SELECT_MASK \ + (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \ + ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \ + tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter11_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter11_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_select_t f; +} tcf_perfcounter11_select_u; + + +/* + * TCF_PERFCOUNTER0_HI struct + */ + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER0_HI_MASK \ + (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \ + ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \ + tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_hi_t f; +} tcf_perfcounter0_hi_u; + + +/* + * TCF_PERFCOUNTER1_HI struct + */ + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER1_HI_MASK \ + (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \ + ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \ + tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_hi_t f; +} tcf_perfcounter1_hi_u; + + +/* + * TCF_PERFCOUNTER2_HI struct + */ + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER2_HI_MASK \ + (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \ + ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \ + tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_hi_t f; +} tcf_perfcounter2_hi_u; + + +/* + * TCF_PERFCOUNTER3_HI struct + */ + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER3_HI_MASK \ + (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \ + ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \ + tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_hi_t f; +} tcf_perfcounter3_hi_u; + + +/* + * TCF_PERFCOUNTER4_HI struct + */ + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER4_HI_MASK \ + (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \ + ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \ + tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter4_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter4_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_hi_t f; +} tcf_perfcounter4_hi_u; + + +/* + * TCF_PERFCOUNTER5_HI struct + */ + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER5_HI_MASK \ + (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \ + ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \ + tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter5_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter5_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_hi_t f; +} tcf_perfcounter5_hi_u; + + +/* + * TCF_PERFCOUNTER6_HI struct + */ + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER6_HI_MASK \ + (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \ + ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \ + tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter6_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter6_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_hi_t f; +} tcf_perfcounter6_hi_u; + + +/* + * TCF_PERFCOUNTER7_HI struct + */ + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER7_HI_MASK \ + (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \ + ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \ + tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter7_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter7_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_hi_t f; +} tcf_perfcounter7_hi_u; + + +/* + * TCF_PERFCOUNTER8_HI struct + */ + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER8_HI_MASK \ + (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \ + ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \ + tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter8_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter8_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_hi_t f; +} tcf_perfcounter8_hi_u; + + +/* + * TCF_PERFCOUNTER9_HI struct + */ + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER9_HI_MASK \ + (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \ + ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \ + tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter9_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter9_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_hi_t f; +} tcf_perfcounter9_hi_u; + + +/* + * TCF_PERFCOUNTER10_HI struct + */ + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER10_HI_MASK \ + (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \ + ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \ + tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter10_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter10_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_hi_t f; +} tcf_perfcounter10_hi_u; + + +/* + * TCF_PERFCOUNTER11_HI struct + */ + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER11_HI_MASK \ + (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \ + ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \ + tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter11_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter11_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_hi_t f; +} tcf_perfcounter11_hi_u; + + +/* + * TCF_PERFCOUNTER0_LOW struct + */ + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER0_LOW_MASK \ + (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \ + ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \ + tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_low_t f; +} tcf_perfcounter0_low_u; + + +/* + * TCF_PERFCOUNTER1_LOW struct + */ + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER1_LOW_MASK \ + (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \ + ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \ + tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_low_t f; +} tcf_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER2_LOW struct + */ + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER2_LOW_MASK \ + (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \ + ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \ + tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_low_t f; +} tcf_perfcounter2_low_u; + + +/* + * TCF_PERFCOUNTER3_LOW struct + */ + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER3_LOW_MASK \ + (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \ + ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \ + tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_low_t f; +} tcf_perfcounter3_low_u; + + +/* + * TCF_PERFCOUNTER4_LOW struct + */ + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER4_LOW_MASK \ + (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \ + ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \ + tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_low_t f; +} tcf_perfcounter4_low_u; + + +/* + * TCF_PERFCOUNTER5_LOW struct + */ + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER5_LOW_MASK \ + (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \ + ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \ + tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_low_t f; +} tcf_perfcounter5_low_u; + + +/* + * TCF_PERFCOUNTER6_LOW struct + */ + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER6_LOW_MASK \ + (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \ + ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \ + tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_low_t f; +} tcf_perfcounter6_low_u; + + +/* + * TCF_PERFCOUNTER7_LOW struct + */ + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER7_LOW_MASK \ + (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \ + ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \ + tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_low_t f; +} tcf_perfcounter7_low_u; + + +/* + * TCF_PERFCOUNTER8_LOW struct + */ + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER8_LOW_MASK \ + (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \ + ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \ + tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_low_t f; +} tcf_perfcounter8_low_u; + + +/* + * TCF_PERFCOUNTER9_LOW struct + */ + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER9_LOW_MASK \ + (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \ + ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \ + tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_low_t f; +} tcf_perfcounter9_low_u; + + +/* + * TCF_PERFCOUNTER10_LOW struct + */ + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER10_LOW_MASK \ + (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \ + ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \ + tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_low_t f; +} tcf_perfcounter10_low_u; + + +/* + * TCF_PERFCOUNTER11_LOW struct + */ + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER11_LOW_MASK \ + (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \ + ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \ + tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_low_t f; +} tcf_perfcounter11_low_u; + + +/* + * TCF_DEBUG struct + */ + +#define TCF_DEBUG_not_MH_TC_rtr_SIZE 1 +#define TCF_DEBUG_TC_MH_send_SIZE 1 +#define TCF_DEBUG_not_FG0_rtr_SIZE 1 +#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1 +#define TCF_DEBUG_TCB_ff_stall_SIZE 1 +#define TCF_DEBUG_TCB_miss_stall_SIZE 1 +#define TCF_DEBUG_TCA_TCB_stall_SIZE 1 +#define TCF_DEBUG_PF0_stall_SIZE 1 +#define TCF_DEBUG_TP0_full_SIZE 1 +#define TCF_DEBUG_TPC_full_SIZE 1 +#define TCF_DEBUG_not_TPC_rtr_SIZE 1 +#define TCF_DEBUG_tca_state_rts_SIZE 1 +#define TCF_DEBUG_tca_rts_SIZE 1 + +#define TCF_DEBUG_not_MH_TC_rtr_SHIFT 6 +#define TCF_DEBUG_TC_MH_send_SHIFT 7 +#define TCF_DEBUG_not_FG0_rtr_SHIFT 8 +#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12 +#define TCF_DEBUG_TCB_ff_stall_SHIFT 13 +#define TCF_DEBUG_TCB_miss_stall_SHIFT 14 +#define TCF_DEBUG_TCA_TCB_stall_SHIFT 15 +#define TCF_DEBUG_PF0_stall_SHIFT 16 +#define TCF_DEBUG_TP0_full_SHIFT 20 +#define TCF_DEBUG_TPC_full_SHIFT 24 +#define TCF_DEBUG_not_TPC_rtr_SHIFT 25 +#define TCF_DEBUG_tca_state_rts_SHIFT 26 +#define TCF_DEBUG_tca_rts_SHIFT 27 + +#define TCF_DEBUG_not_MH_TC_rtr_MASK 0x00000040 +#define TCF_DEBUG_TC_MH_send_MASK 0x00000080 +#define TCF_DEBUG_not_FG0_rtr_MASK 0x00000100 +#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000 +#define TCF_DEBUG_TCB_ff_stall_MASK 0x00002000 +#define TCF_DEBUG_TCB_miss_stall_MASK 0x00004000 +#define TCF_DEBUG_TCA_TCB_stall_MASK 0x00008000 +#define TCF_DEBUG_PF0_stall_MASK 0x00010000 +#define TCF_DEBUG_TP0_full_MASK 0x00100000 +#define TCF_DEBUG_TPC_full_MASK 0x01000000 +#define TCF_DEBUG_not_TPC_rtr_MASK 0x02000000 +#define TCF_DEBUG_tca_state_rts_MASK 0x04000000 +#define TCF_DEBUG_tca_rts_MASK 0x08000000 + +#define TCF_DEBUG_MASK \ + (TCF_DEBUG_not_MH_TC_rtr_MASK | \ + TCF_DEBUG_TC_MH_send_MASK | \ + TCF_DEBUG_not_FG0_rtr_MASK | \ + TCF_DEBUG_not_TCB_TCO_rtr_MASK | \ + TCF_DEBUG_TCB_ff_stall_MASK | \ + TCF_DEBUG_TCB_miss_stall_MASK | \ + TCF_DEBUG_TCA_TCB_stall_MASK | \ + TCF_DEBUG_PF0_stall_MASK | \ + TCF_DEBUG_TP0_full_MASK | \ + TCF_DEBUG_TPC_full_MASK | \ + TCF_DEBUG_not_TPC_rtr_MASK | \ + TCF_DEBUG_tca_state_rts_MASK | \ + TCF_DEBUG_tca_rts_MASK) + +#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \ + ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \ + (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \ + (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \ + (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \ + (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \ + (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \ + (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \ + (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \ + (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \ + (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \ + (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \ + (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \ + (tca_rts << TCF_DEBUG_tca_rts_SHIFT)) + +#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_GET_TP0_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_GET_TPC_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_GET_tca_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT) + +#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 6; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int : 3; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int : 4; + } tcf_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 4; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int : 3; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int : 6; + } tcf_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_debug_t f; +} tcf_debug_u; + + +/* + * TCA_FIFO_DEBUG struct + */ + +#define TCA_FIFO_DEBUG_tp0_full_SIZE 1 +#define TCA_FIFO_DEBUG_tpc_full_SIZE 1 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1 +#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1 +#define TCA_FIFO_DEBUG_FW_full_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1 +#define TCA_FIFO_DEBUG_FW_rts0_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1 + +#define TCA_FIFO_DEBUG_tp0_full_SHIFT 0 +#define TCA_FIFO_DEBUG_tpc_full_SHIFT 4 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5 +#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6 +#define TCA_FIFO_DEBUG_FW_full_SHIFT 7 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8 +#define TCA_FIFO_DEBUG_FW_rts0_SHIFT 12 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17 + +#define TCA_FIFO_DEBUG_tp0_full_MASK 0x00000001 +#define TCA_FIFO_DEBUG_tpc_full_MASK 0x00000010 +#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020 +#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040 +#define TCA_FIFO_DEBUG_FW_full_MASK 0x00000080 +#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100 +#define TCA_FIFO_DEBUG_FW_rts0_MASK 0x00001000 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000 +#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000 + +#define TCA_FIFO_DEBUG_MASK \ + (TCA_FIFO_DEBUG_tp0_full_MASK | \ + TCA_FIFO_DEBUG_tpc_full_MASK | \ + TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \ + TCA_FIFO_DEBUG_load_tp_fifos_MASK | \ + TCA_FIFO_DEBUG_FW_full_MASK | \ + TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \ + TCA_FIFO_DEBUG_FW_rts0_MASK | \ + TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \ + TCA_FIFO_DEBUG_FW_tpc_rts_MASK) + +#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \ + ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \ + (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \ + (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \ + (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \ + (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \ + (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \ + (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \ + (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \ + (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)) + +#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int : 14; + } tca_fifo_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int : 14; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + } tca_fifo_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_fifo_debug_t f; +} tca_fifo_debug_u; + + +/* + * TCA_PROBE_DEBUG struct + */ + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001 + +#define TCA_PROBE_DEBUG_MASK \ + (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) + +#define TCA_PROBE_DEBUG(probefilter_stall) \ + ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)) + +#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \ + ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \ + tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + unsigned int : 31; + } tca_probe_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int : 31; + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + } tca_probe_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_probe_debug_t f; +} tca_probe_debug_u; + + +/* + * TCA_TPC_DEBUG struct + */ + +#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1 +#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1 + +#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12 +#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13 + +#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000 +#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000 + +#define TCA_TPC_DEBUG_MASK \ + (TCA_TPC_DEBUG_captue_state_rts_MASK | \ + TCA_TPC_DEBUG_capture_tca_rts_MASK) + +#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \ + ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \ + (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)) + +#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 12; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int : 18; + } tca_tpc_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 18; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int : 12; + } tca_tpc_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_tpc_debug_t f; +} tca_tpc_debug_u; + + +/* + * TCB_CORE_DEBUG struct + */ + +#define TCB_CORE_DEBUG_access512_SIZE 1 +#define TCB_CORE_DEBUG_tiled_SIZE 1 +#define TCB_CORE_DEBUG_opcode_SIZE 3 +#define TCB_CORE_DEBUG_format_SIZE 6 +#define TCB_CORE_DEBUG_sector_format_SIZE 5 +#define TCB_CORE_DEBUG_sector_format512_SIZE 3 + +#define TCB_CORE_DEBUG_access512_SHIFT 0 +#define TCB_CORE_DEBUG_tiled_SHIFT 1 +#define TCB_CORE_DEBUG_opcode_SHIFT 4 +#define TCB_CORE_DEBUG_format_SHIFT 8 +#define TCB_CORE_DEBUG_sector_format_SHIFT 16 +#define TCB_CORE_DEBUG_sector_format512_SHIFT 24 + +#define TCB_CORE_DEBUG_access512_MASK 0x00000001 +#define TCB_CORE_DEBUG_tiled_MASK 0x00000002 +#define TCB_CORE_DEBUG_opcode_MASK 0x00000070 +#define TCB_CORE_DEBUG_format_MASK 0x00003f00 +#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000 +#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000 + +#define TCB_CORE_DEBUG_MASK \ + (TCB_CORE_DEBUG_access512_MASK | \ + TCB_CORE_DEBUG_tiled_MASK | \ + TCB_CORE_DEBUG_opcode_MASK | \ + TCB_CORE_DEBUG_format_MASK | \ + TCB_CORE_DEBUG_sector_format_MASK | \ + TCB_CORE_DEBUG_sector_format512_MASK) + +#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \ + ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \ + (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \ + (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \ + (format << TCB_CORE_DEBUG_format_SHIFT) | \ + (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \ + (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)) + +#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT) + +#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int : 2; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 1; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 2; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 3; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 5; + } tcb_core_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int : 5; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 3; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 2; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 1; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 2; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + } tcb_core_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_core_debug_t f; +} tcb_core_debug_u; + + +/* + * TCB_TAG0_DEBUG struct + */ + +#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG0_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG0_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG0_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG0_DEBUG_MASK \ + (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG0_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG0_DEBUG_miss_stall_MASK | \ + TCB_TAG0_DEBUG_num_feee_lines_MASK | \ + TCB_TAG0_DEBUG_max_misses_MASK) + +#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT) + +#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + } tcb_tag0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + } tcb_tag0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag0_debug_t f; +} tcb_tag0_debug_u; + + +/* + * TCB_TAG1_DEBUG struct + */ + +#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG1_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG1_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG1_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG1_DEBUG_MASK \ + (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG1_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG1_DEBUG_miss_stall_MASK | \ + TCB_TAG1_DEBUG_num_feee_lines_MASK | \ + TCB_TAG1_DEBUG_max_misses_MASK) + +#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT) + +#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + } tcb_tag1_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + } tcb_tag1_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag1_debug_t f; +} tcb_tag1_debug_u; + + +/* + * TCB_TAG2_DEBUG struct + */ + +#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG2_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG2_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG2_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG2_DEBUG_MASK \ + (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG2_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG2_DEBUG_miss_stall_MASK | \ + TCB_TAG2_DEBUG_num_feee_lines_MASK | \ + TCB_TAG2_DEBUG_max_misses_MASK) + +#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT) + +#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + } tcb_tag2_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + } tcb_tag2_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag2_debug_t f; +} tcb_tag2_debug_u; + + +/* + * TCB_TAG3_DEBUG struct + */ + +#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG3_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG3_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG3_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG3_DEBUG_MASK \ + (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG3_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG3_DEBUG_miss_stall_MASK | \ + TCB_TAG3_DEBUG_num_feee_lines_MASK | \ + TCB_TAG3_DEBUG_max_misses_MASK) + +#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT) + +#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + } tcb_tag3_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + } tcb_tag3_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag3_debug_t f; +} tcb_tag3_debug_u; + + +/* + * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct + */ + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \ + (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \ + ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \ + (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \ + (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \ + (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \ + (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \ + (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \ + (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \ + (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int : 3; + } tcb_fetch_gen_sector_walker0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int : 3; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + } tcb_fetch_gen_sector_walker0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_sector_walker0_debug_t f; +} tcb_fetch_gen_sector_walker0_debug_u; + + +/* + * TCB_FETCH_GEN_WALKER_DEBUG struct + */ + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000 + +#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \ + (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) + +#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \ + ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \ + (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \ + (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \ + (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \ + (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \ + (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)) + +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 4; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int : 3; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int : 12; + } tcb_fetch_gen_walker_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 12; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int : 3; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int : 4; + } tcb_fetch_gen_walker_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_walker_debug_t f; +} tcb_fetch_gen_walker_debug_u; + + +/* + * TCB_FETCH_GEN_PIPE0_DEBUG struct + */ + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \ + (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) + +#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \ + ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \ + (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \ + (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \ + (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \ + (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \ + (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \ + (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \ + (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \ + (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \ + (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \ + (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + } tcb_fetch_gen_pipe0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + } tcb_fetch_gen_pipe0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_pipe0_debug_t f; +} tcb_fetch_gen_pipe0_debug_u; + + +/* + * TCD_INPUT0_DEBUG struct + */ + +#define TCD_INPUT0_DEBUG_empty_SIZE 1 +#define TCD_INPUT0_DEBUG_full_SIZE 1 +#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_cnt_q1_SIZE 2 +#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_ip_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1 + +#define TCD_INPUT0_DEBUG_empty_SHIFT 16 +#define TCD_INPUT0_DEBUG_full_SHIFT 17 +#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20 +#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT 21 +#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23 +#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26 + +#define TCD_INPUT0_DEBUG_empty_MASK 0x00010000 +#define TCD_INPUT0_DEBUG_full_MASK 0x00020000 +#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000 +#define TCD_INPUT0_DEBUG_cnt_q1_MASK 0x00600000 +#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000 +#define TCD_INPUT0_DEBUG_ip_send_MASK 0x01000000 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000 +#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000 + +#define TCD_INPUT0_DEBUG_MASK \ + (TCD_INPUT0_DEBUG_empty_MASK | \ + TCD_INPUT0_DEBUG_full_MASK | \ + TCD_INPUT0_DEBUG_valid_q1_MASK | \ + TCD_INPUT0_DEBUG_cnt_q1_MASK | \ + TCD_INPUT0_DEBUG_last_send_q1_MASK | \ + TCD_INPUT0_DEBUG_ip_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_busy_MASK) + +#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \ + ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \ + (full << TCD_INPUT0_DEBUG_full_SHIFT) | \ + (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \ + (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \ + (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \ + (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \ + (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \ + (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)) + +#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 16; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int : 2; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int : 5; + } tcd_input0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 5; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int : 2; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int : 16; + } tcd_input0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_input0_debug_t f; +} tcd_input0_debug_u; + + +/* + * TCD_DEGAMMA_DEBUG struct + */ + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040 + +#define TCD_DEGAMMA_DEBUG_MASK \ + (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) + +#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \ + ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \ + (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \ + (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \ + (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \ + (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \ + (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)) + +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int : 25; + } tcd_degamma_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int : 25; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + } tcd_degamma_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_degamma_debug_t f; +} tcd_degamma_debug_u; + + +/* + * TCD_DXTMUX_SCTARB_DEBUG struct + */ + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000 + +#define TCD_DXTMUX_SCTARB_DEBUG_MASK \ + (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) + +#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \ + ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \ + (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \ + (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \ + (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \ + (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \ + (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \ + (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \ + (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \ + (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)) + +#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 9; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int : 2; + } tcd_dxtmux_sctarb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 2; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int : 3; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int : 9; + } tcd_dxtmux_sctarb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtmux_sctarb_debug_t f; +} tcd_dxtmux_sctarb_debug_u; + + +/* + * TCD_DXTC_ARB_DEBUG struct + */ + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4 +#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010 +#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000 + +#define TCD_DXTC_ARB_DEBUG_MASK \ + (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \ + TCD_DXTC_ARB_DEBUG_pstate_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \ + TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) + +#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \ + ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \ + (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \ + (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \ + (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \ + (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \ + (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \ + (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \ + (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \ + (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)) + +#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int : 4; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + } tcd_dxtc_arb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int : 4; + } tcd_dxtc_arb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtc_arb_debug_t f; +} tcd_dxtc_arb_debug_u; + + +/* + * TCD_STALLS_DEBUG struct + */ + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000 +#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000 + +#define TCD_STALLS_DEBUG_MASK \ + (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \ + TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \ + TCD_STALLS_DEBUG_not_incoming_rtr_MASK) + +#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \ + ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \ + (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \ + (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \ + (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \ + (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \ + (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)) + +#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int : 11; + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + } tcd_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int : 10; + } tcd_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_stalls_debug_t f; +} tcd_stalls_debug_u; + + +/* + * TCO_STALLS_DEBUG struct + */ + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080 + +#define TCO_STALLS_DEBUG_MASK \ + (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) + +#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \ + ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \ + (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \ + (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)) + +#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 5; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int : 24; + } tco_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 24; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int : 5; + } tco_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_stalls_debug_t f; +} tco_stalls_debug_u; + + +/* + * TCO_QUAD0_DEBUG0 struct + */ + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1 +#define TCO_QUAD0_DEBUG0_busy_SIZE 1 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16 +#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29 +#define TCO_QUAD0_DEBUG0_busy_SHIFT 30 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000 +#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000 +#define TCO_QUAD0_DEBUG0_busy_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG0_MASK \ + (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \ + TCO_QUAD0_DEBUG0_read_cache_q_MASK | \ + TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \ + TCO_QUAD0_DEBUG0_busy_MASK) + +#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \ + ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \ + (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \ + (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \ + (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \ + (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \ + (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \ + (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \ + (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \ + (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \ + (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \ + (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)) + +#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT) + +#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int : 2; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 7; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int : 1; + } tco_quad0_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int : 1; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int : 7; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 2; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + } tco_quad0_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug0_t f; +} tco_quad0_debug0_u; + + +/* + * TCO_QUAD0_DEBUG1 struct + */ + +#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_empty_SIZE 1 +#define TCO_QUAD0_DEBUG1_full_SIZE 1 +#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1 + +#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0 +#define TCO_QUAD0_DEBUG1_empty_SHIFT 1 +#define TCO_QUAD0_DEBUG1_full_SHIFT 2 +#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30 + +#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001 +#define TCO_QUAD0_DEBUG1_empty_MASK 0x00000002 +#define TCO_QUAD0_DEBUG1_full_MASK 0x00000004 +#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800 +#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000 +#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG1_MASK \ + (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_empty_MASK | \ + TCO_QUAD0_DEBUG1_full_MASK | \ + TCO_QUAD0_DEBUG1_write_enable_MASK | \ + TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \ + TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \ + TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \ + TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \ + TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) + +#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \ + ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \ + (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \ + (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \ + (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \ + (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \ + (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \ + (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \ + (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \ + (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \ + (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \ + (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \ + (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \ + (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)) + +#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int : 2; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int : 1; + } tco_quad0_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int : 1; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int : 2; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + } tco_quad0_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug1_t f; +} tco_quad0_debug1_u; + + +#endif + + +#if !defined (_TC_FIDDLE_H) +#define _TC_FIDDLE_H + +/***************************************************************************************************************** + * + * tc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_SC_FIDDLE_H) +#define _SC_FIDDLE_H + +/***************************************************************************************************************** + * + * sc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_BC_FIDDLE_H) +#define _BC_FIDDLE_H + +/***************************************************************************************************************** + * + * bc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * RB_SURFACE_INFO struct + */ + +#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2 + +#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14 + +#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff +#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000 + +#define RB_SURFACE_INFO_MASK \ + (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \ + RB_SURFACE_INFO_MSAA_SAMPLES_MASK) + +#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \ + ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \ + (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)) + +#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int : 16; + } rb_surface_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int : 16; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + } rb_surface_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_surface_info_t f; +} rb_surface_info_u; + + +/* + * RB_COLOR_INFO struct + */ + +#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2 +#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1 +#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2 +#define RB_COLOR_INFO_COLOR_SWAP_SIZE 2 +#define RB_COLOR_INFO_COLOR_BASE_SIZE 20 + +#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4 +#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6 +#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7 +#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9 +#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12 + +#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f +#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030 +#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040 +#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180 +#define RB_COLOR_INFO_COLOR_SWAP_MASK 0x00000600 +#define RB_COLOR_INFO_COLOR_BASE_MASK 0xfffff000 + +#define RB_COLOR_INFO_MASK \ + (RB_COLOR_INFO_COLOR_FORMAT_MASK | \ + RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \ + RB_COLOR_INFO_COLOR_LINEAR_MASK | \ + RB_COLOR_INFO_COLOR_ENDIAN_MASK | \ + RB_COLOR_INFO_COLOR_SWAP_MASK | \ + RB_COLOR_INFO_COLOR_BASE_MASK) + +#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \ + ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \ + (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \ + (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \ + (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \ + (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \ + (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)) + +#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int : 1; + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + } rb_color_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + unsigned int : 1; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + } rb_color_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_info_t f; +} rb_color_info_u; + + +/* + * RB_DEPTH_INFO struct + */ + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1 +#define RB_DEPTH_INFO_DEPTH_BASE_SIZE 20 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0 +#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001 +#define RB_DEPTH_INFO_DEPTH_BASE_MASK 0xfffff000 + +#define RB_DEPTH_INFO_MASK \ + (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \ + RB_DEPTH_INFO_DEPTH_BASE_MASK) + +#define RB_DEPTH_INFO(depth_format, depth_base) \ + ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \ + (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)) + +#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + unsigned int : 11; + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + } rb_depth_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + unsigned int : 11; + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + } rb_depth_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_info_t f; +} rb_depth_info_u; + + +/* + * RB_STENCILREFMASK struct + */ + +#define RB_STENCILREFMASK_STENCILREF_SIZE 8 +#define RB_STENCILREFMASK_STENCILMASK_SIZE 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8 +#define RB_STENCILREFMASK_RESERVED0_SIZE 1 +#define RB_STENCILREFMASK_RESERVED1_SIZE 1 + +#define RB_STENCILREFMASK_STENCILREF_SHIFT 0 +#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16 +#define RB_STENCILREFMASK_RESERVED0_SHIFT 24 +#define RB_STENCILREFMASK_RESERVED1_SHIFT 25 + +#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff +#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00 +#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000 +#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000 +#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000 + +#define RB_STENCILREFMASK_MASK \ + (RB_STENCILREFMASK_STENCILREF_MASK | \ + RB_STENCILREFMASK_STENCILMASK_MASK | \ + RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \ + RB_STENCILREFMASK_RESERVED0_MASK | \ + RB_STENCILREFMASK_RESERVED1_MASK) + +#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \ + ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \ + (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \ + (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \ + (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \ + (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)) + +#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT) + +#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int : 6; + } rb_stencilrefmask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int : 6; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + } rb_stencilrefmask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_t f; +} rb_stencilrefmask_u; + + +/* + * RB_ALPHA_REF struct + */ + +#define RB_ALPHA_REF_ALPHA_REF_SIZE 32 + +#define RB_ALPHA_REF_ALPHA_REF_SHIFT 0 + +#define RB_ALPHA_REF_ALPHA_REF_MASK 0xffffffff + +#define RB_ALPHA_REF_MASK \ + (RB_ALPHA_REF_ALPHA_REF_MASK) + +#define RB_ALPHA_REF(alpha_ref) \ + ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)) + +#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \ + ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \ + rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_alpha_ref_t f; +} rb_alpha_ref_u; + + +/* + * RB_COLOR_MASK struct + */ + +#define RB_COLOR_MASK_WRITE_RED_SIZE 1 +#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1 +#define RB_COLOR_MASK_WRITE_BLUE_SIZE 1 +#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1 +#define RB_COLOR_MASK_RESERVED2_SIZE 1 +#define RB_COLOR_MASK_RESERVED3_SIZE 1 + +#define RB_COLOR_MASK_WRITE_RED_SHIFT 0 +#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1 +#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2 +#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3 +#define RB_COLOR_MASK_RESERVED2_SHIFT 4 +#define RB_COLOR_MASK_RESERVED3_SHIFT 5 + +#define RB_COLOR_MASK_WRITE_RED_MASK 0x00000001 +#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002 +#define RB_COLOR_MASK_WRITE_BLUE_MASK 0x00000004 +#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008 +#define RB_COLOR_MASK_RESERVED2_MASK 0x00000010 +#define RB_COLOR_MASK_RESERVED3_MASK 0x00000020 + +#define RB_COLOR_MASK_MASK \ + (RB_COLOR_MASK_WRITE_RED_MASK | \ + RB_COLOR_MASK_WRITE_GREEN_MASK | \ + RB_COLOR_MASK_WRITE_BLUE_MASK | \ + RB_COLOR_MASK_WRITE_ALPHA_MASK | \ + RB_COLOR_MASK_RESERVED2_MASK | \ + RB_COLOR_MASK_RESERVED3_MASK) + +#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \ + ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \ + (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \ + (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \ + (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \ + (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \ + (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)) + +#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT) + +#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int : 26; + } rb_color_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int : 26; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + } rb_color_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_mask_t f; +} rb_color_mask_u; + + +/* + * RB_BLEND_RED struct + */ + +#define RB_BLEND_RED_BLEND_RED_SIZE 8 + +#define RB_BLEND_RED_BLEND_RED_SHIFT 0 + +#define RB_BLEND_RED_BLEND_RED_MASK 0x000000ff + +#define RB_BLEND_RED_MASK \ + (RB_BLEND_RED_BLEND_RED_MASK) + +#define RB_BLEND_RED(blend_red) \ + ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)) + +#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \ + ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT) + +#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \ + rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + unsigned int : 24; + } rb_blend_red_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int : 24; + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + } rb_blend_red_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_red_t f; +} rb_blend_red_u; + + +/* + * RB_BLEND_GREEN struct + */ + +#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8 + +#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0 + +#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff + +#define RB_BLEND_GREEN_MASK \ + (RB_BLEND_GREEN_BLEND_GREEN_MASK) + +#define RB_BLEND_GREEN(blend_green) \ + ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)) + +#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \ + ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \ + rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + unsigned int : 24; + } rb_blend_green_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int : 24; + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + } rb_blend_green_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_green_t f; +} rb_blend_green_u; + + +/* + * RB_BLEND_BLUE struct + */ + +#define RB_BLEND_BLUE_BLEND_BLUE_SIZE 8 + +#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0 + +#define RB_BLEND_BLUE_BLEND_BLUE_MASK 0x000000ff + +#define RB_BLEND_BLUE_MASK \ + (RB_BLEND_BLUE_BLEND_BLUE_MASK) + +#define RB_BLEND_BLUE(blend_blue) \ + ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)) + +#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \ + ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \ + rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + unsigned int : 24; + } rb_blend_blue_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int : 24; + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + } rb_blend_blue_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_blue_t f; +} rb_blend_blue_u; + + +/* + * RB_BLEND_ALPHA struct + */ + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff + +#define RB_BLEND_ALPHA_MASK \ + (RB_BLEND_ALPHA_BLEND_ALPHA_MASK) + +#define RB_BLEND_ALPHA(blend_alpha) \ + ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)) + +#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \ + ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \ + rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + unsigned int : 24; + } rb_blend_alpha_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int : 24; + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + } rb_blend_alpha_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_alpha_t f; +} rb_blend_alpha_u; + + +/* + * RB_FOG_COLOR struct + */ + +#define RB_FOG_COLOR_FOG_RED_SIZE 8 +#define RB_FOG_COLOR_FOG_GREEN_SIZE 8 +#define RB_FOG_COLOR_FOG_BLUE_SIZE 8 + +#define RB_FOG_COLOR_FOG_RED_SHIFT 0 +#define RB_FOG_COLOR_FOG_GREEN_SHIFT 8 +#define RB_FOG_COLOR_FOG_BLUE_SHIFT 16 + +#define RB_FOG_COLOR_FOG_RED_MASK 0x000000ff +#define RB_FOG_COLOR_FOG_GREEN_MASK 0x0000ff00 +#define RB_FOG_COLOR_FOG_BLUE_MASK 0x00ff0000 + +#define RB_FOG_COLOR_MASK \ + (RB_FOG_COLOR_FOG_RED_MASK | \ + RB_FOG_COLOR_FOG_GREEN_MASK | \ + RB_FOG_COLOR_FOG_BLUE_MASK) + +#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \ + ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \ + (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \ + (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)) + +#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int : 8; + } rb_fog_color_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int : 8; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + } rb_fog_color_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_fog_color_t f; +} rb_fog_color_u; + + +/* + * RB_STENCILREFMASK_BF struct + */ + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1 +#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16 +#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24 +#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000 +#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000 +#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000 + +#define RB_STENCILREFMASK_BF_MASK \ + (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_RESERVED4_MASK | \ + RB_STENCILREFMASK_BF_RESERVED5_MASK) + +#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \ + ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \ + (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \ + (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \ + (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \ + (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)) + +#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int : 6; + } rb_stencilrefmask_bf_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int : 6; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + } rb_stencilrefmask_bf_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_bf_t f; +} rb_stencilrefmask_bf_u; + + +/* + * RB_DEPTHCONTROL struct + */ + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_ZFUNC_SIZE 3 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0 +#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3 +#define RB_DEPTHCONTROL_ZFUNC_SHIFT 4 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7 +#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8 +#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11 +#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14 +#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001 +#define RB_DEPTHCONTROL_Z_ENABLE_MASK 0x00000002 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008 +#define RB_DEPTHCONTROL_ZFUNC_MASK 0x00000070 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080 +#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700 +#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800 +#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000 +#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000 + +#define RB_DEPTHCONTROL_MASK \ + (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \ + RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_ZFUNC_MASK | \ + RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) + +#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \ + ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \ + (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \ + (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \ + (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \ + (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \ + (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \ + (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \ + (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \ + (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \ + (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \ + (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \ + (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \ + (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \ + (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)) + +#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + } rb_depthcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + } rb_depthcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depthcontrol_t f; +} rb_depthcontrol_u; + + +/* + * RB_BLENDCONTROL struct + */ + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1 +#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29 +#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f +#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000 +#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000 + +#define RB_BLENDCONTROL_MASK \ + (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \ + RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \ + RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \ + RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_MASK) + +#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \ + ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \ + (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \ + (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \ + (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \ + (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \ + (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \ + (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \ + (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)) + +#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int : 3; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int : 1; + } rb_blendcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int : 1; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int : 3; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + } rb_blendcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blendcontrol_t f; +} rb_blendcontrol_u; + + +/* + * RB_COLORCONTROL struct + */ + +#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1 +#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1 +#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1 +#define RB_COLORCONTROL_ROP_CODE_SIZE 4 +#define RB_COLORCONTROL_DITHER_MODE_SIZE 2 +#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2 +#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2 + +#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4 +#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5 +#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7 +#define RB_COLORCONTROL_ROP_CODE_SHIFT 8 +#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12 +#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14 +#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30 + +#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010 +#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020 +#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080 +#define RB_COLORCONTROL_ROP_CODE_MASK 0x00000f00 +#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000 +#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000 +#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000 + +#define RB_COLORCONTROL_MASK \ + (RB_COLORCONTROL_ALPHA_FUNC_MASK | \ + RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \ + RB_COLORCONTROL_BLEND_DISABLE_MASK | \ + RB_COLORCONTROL_FOG_ENABLE_MASK | \ + RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \ + RB_COLORCONTROL_ROP_CODE_MASK | \ + RB_COLORCONTROL_DITHER_MODE_MASK | \ + RB_COLORCONTROL_DITHER_TYPE_MASK | \ + RB_COLORCONTROL_PIXEL_FOG_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) + +#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \ + ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \ + (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \ + (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \ + (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \ + (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \ + (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \ + (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \ + (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \ + (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \ + (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \ + (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \ + (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \ + (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \ + (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)) + +#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int : 7; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + } rb_colorcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int : 7; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + } rb_colorcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_colorcontrol_t f; +} rb_colorcontrol_u; + + +/* + * RB_MODECONTROL struct + */ + +#define RB_MODECONTROL_EDRAM_MODE_SIZE 3 + +#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0 + +#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007 + +#define RB_MODECONTROL_MASK \ + (RB_MODECONTROL_EDRAM_MODE_MASK) + +#define RB_MODECONTROL(edram_mode) \ + ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)) + +#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \ + ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \ + rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + unsigned int : 29; + } rb_modecontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int : 29; + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + } rb_modecontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_modecontrol_t f; +} rb_modecontrol_u; + + +/* + * RB_COLOR_DEST_MASK struct + */ + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff + +#define RB_COLOR_DEST_MASK_MASK \ + (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) + +#define RB_COLOR_DEST_MASK(color_dest_mask) \ + ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)) + +#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \ + ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \ + rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_dest_mask_t f; +} rb_color_dest_mask_u; + + +/* + * RB_COPY_CONTROL struct + */ + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1 +#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3 +#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008 +#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0 + +#define RB_COPY_CONTROL_MASK \ + (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \ + RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \ + RB_COPY_CONTROL_CLEAR_MASK_MASK) + +#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \ + ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \ + (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \ + (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)) + +#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int : 24; + } rb_copy_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int : 24; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + } rb_copy_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_control_t f; +} rb_copy_control_u; + + +/* + * RB_COPY_DEST_BASE struct + */ + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000 + +#define RB_COPY_DEST_BASE_MASK \ + (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) + +#define RB_COPY_DEST_BASE(copy_dest_base) \ + ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)) + +#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \ + ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \ + rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int : 12; + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + } rb_copy_dest_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + unsigned int : 12; + } rb_copy_dest_base_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_base_t f; +} rb_copy_dest_base_u; + + +/* + * RB_COPY_DEST_PITCH struct + */ + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff + +#define RB_COPY_DEST_PITCH_MASK \ + (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) + +#define RB_COPY_DEST_PITCH(copy_dest_pitch) \ + ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)) + +#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \ + ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \ + rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + unsigned int : 23; + } rb_copy_dest_pitch_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int : 23; + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + } rb_copy_dest_pitch_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pitch_t f; +} rb_copy_dest_pitch_u; + + +/* + * RB_COPY_DEST_INFO struct + */ + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000 + +#define RB_COPY_DEST_INFO_MASK \ + (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) + +#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \ + ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \ + (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \ + (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \ + (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \ + (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \ + (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \ + (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \ + (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \ + (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \ + (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int : 14; + } rb_copy_dest_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int : 14; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + } rb_copy_dest_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_info_t f; +} rb_copy_dest_info_u; + + +/* + * RB_COPY_DEST_PIXEL_OFFSET struct + */ + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000 + +#define RB_COPY_DEST_PIXEL_OFFSET_MASK \ + (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \ + RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) + +#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \ + ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \ + (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)) + +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int : 6; + } rb_copy_dest_pixel_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int : 6; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + } rb_copy_dest_pixel_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pixel_offset_t f; +} rb_copy_dest_pixel_offset_u; + + +/* + * RB_DEPTH_CLEAR struct + */ + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff + +#define RB_DEPTH_CLEAR_MASK \ + (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) + +#define RB_DEPTH_CLEAR(depth_clear) \ + ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)) + +#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \ + ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \ + rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_clear_t f; +} rb_depth_clear_u; + + +/* + * RB_SAMPLE_COUNT_CTL struct + */ + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002 + +#define RB_SAMPLE_COUNT_CTL_MASK \ + (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \ + RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) + +#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \ + ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \ + (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)) + +#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int : 30; + } rb_sample_count_ctl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int : 30; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + } rb_sample_count_ctl_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_ctl_t f; +} rb_sample_count_ctl_u; + + +/* + * RB_SAMPLE_COUNT_ADDR struct + */ + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff + +#define RB_SAMPLE_COUNT_ADDR_MASK \ + (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) + +#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \ + ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)) + +#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \ + ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \ + rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_addr_t f; +} rb_sample_count_addr_u; + + +/* + * RB_BC_CONTROL struct + */ + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1 +#define RB_BC_CONTROL_CRC_MODE_SIZE 1 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1 +#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_CRC_SYSTEM_SIZE 1 +#define RB_BC_CONTROL_RESERVED6_SIZE 1 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14 +#define RB_BC_CONTROL_CRC_MODE_SHIFT 15 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16 +#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29 +#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30 +#define RB_BC_CONTROL_RESERVED6_SHIFT 31 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000 +#define RB_BC_CONTROL_CRC_MODE_MASK 0x00008000 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000 +#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000 +#define RB_BC_CONTROL_CRC_SYSTEM_MASK 0x40000000 +#define RB_BC_CONTROL_RESERVED6_MASK 0x80000000 + +#define RB_BC_CONTROL_MASK \ + (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \ + RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \ + RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \ + RB_BC_CONTROL_CRC_MODE_MASK | \ + RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \ + RB_BC_CONTROL_DISABLE_ACCUM_MASK | \ + RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \ + RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_CRC_SYSTEM_MASK | \ + RB_BC_CONTROL_RESERVED6_MASK) + +#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \ + ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \ + (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \ + (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \ + (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \ + (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \ + (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \ + (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \ + (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \ + (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \ + (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \ + (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \ + (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \ + (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \ + (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \ + (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \ + (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \ + (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \ + (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \ + (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)) + +#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT) + +#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int : 1; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + } rb_bc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int : 1; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + } rb_bc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_control_t f; +} rb_bc_control_u; + + +/* + * RB_EDRAM_INFO struct + */ + +#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2 +#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18 + +#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4 +#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14 + +#define RB_EDRAM_INFO_EDRAM_SIZE_MASK 0x0000000f +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030 +#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000 + +#define RB_EDRAM_INFO_MASK \ + (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \ + RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \ + RB_EDRAM_INFO_EDRAM_RANGE_MASK) + +#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \ + ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \ + (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \ + (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)) + +#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int : 8; + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + } rb_edram_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + unsigned int : 8; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + } rb_edram_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_edram_info_t f; +} rb_edram_info_u; + + +/* + * RB_CRC_RD_PORT struct + */ + +#define RB_CRC_RD_PORT_CRC_DATA_SIZE 32 + +#define RB_CRC_RD_PORT_CRC_DATA_SHIFT 0 + +#define RB_CRC_RD_PORT_CRC_DATA_MASK 0xffffffff + +#define RB_CRC_RD_PORT_MASK \ + (RB_CRC_RD_PORT_CRC_DATA_MASK) + +#define RB_CRC_RD_PORT(crc_data) \ + ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)) + +#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \ + ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \ + rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_rd_port_t f; +} rb_crc_rd_port_u; + + +/* + * RB_CRC_CONTROL struct + */ + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001 + +#define RB_CRC_CONTROL_MASK \ + (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) + +#define RB_CRC_CONTROL(crc_rd_advance) \ + ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)) + +#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \ + ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \ + rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + unsigned int : 31; + } rb_crc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int : 31; + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + } rb_crc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_control_t f; +} rb_crc_control_u; + + +/* + * RB_CRC_MASK struct + */ + +#define RB_CRC_MASK_CRC_MASK_SIZE 32 + +#define RB_CRC_MASK_CRC_MASK_SHIFT 0 + +#define RB_CRC_MASK_CRC_MASK_MASK 0xffffffff + +#define RB_CRC_MASK_MASK \ + (RB_CRC_MASK_CRC_MASK_MASK) + +#define RB_CRC_MASK(crc_mask) \ + ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)) + +#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \ + ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT) + +#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \ + rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_mask_t f; +} rb_crc_mask_u; + + +/* + * RB_PERFCOUNTER0_SELECT struct + */ + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define RB_PERFCOUNTER0_SELECT_MASK \ + (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define RB_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \ + ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \ + rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } rb_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } rb_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_select_t f; +} rb_perfcounter0_select_u; + + +/* + * RB_PERFCOUNTER0_LOW struct + */ + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define RB_PERFCOUNTER0_LOW_MASK \ + (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \ + ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \ + rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_low_t f; +} rb_perfcounter0_low_u; + + +/* + * RB_PERFCOUNTER0_HI struct + */ + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define RB_PERFCOUNTER0_HI_MASK \ + (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \ + ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \ + rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } rb_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } rb_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_hi_t f; +} rb_perfcounter0_hi_u; + + +/* + * RB_TOTAL_SAMPLES struct + */ + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff + +#define RB_TOTAL_SAMPLES_MASK \ + (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) + +#define RB_TOTAL_SAMPLES(total_samples) \ + ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)) + +#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \ + ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \ + rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_total_samples_t f; +} rb_total_samples_u; + + +/* + * RB_ZPASS_SAMPLES struct + */ + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff + +#define RB_ZPASS_SAMPLES_MASK \ + (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) + +#define RB_ZPASS_SAMPLES(zpass_samples) \ + ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)) + +#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \ + ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \ + rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zpass_samples_t f; +} rb_zpass_samples_u; + + +/* + * RB_ZFAIL_SAMPLES struct + */ + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff + +#define RB_ZFAIL_SAMPLES_MASK \ + (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) + +#define RB_ZFAIL_SAMPLES(zfail_samples) \ + ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)) + +#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \ + ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \ + rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zfail_samples_t f; +} rb_zfail_samples_u; + + +/* + * RB_SFAIL_SAMPLES struct + */ + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff + +#define RB_SFAIL_SAMPLES_MASK \ + (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) + +#define RB_SFAIL_SAMPLES(sfail_samples) \ + ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)) + +#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \ + ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \ + rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sfail_samples_t f; +} rb_sfail_samples_u; + + +/* + * RB_DEBUG_0 struct + */ + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE 1 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1 +#define RB_DEBUG_0_C_REQ_FULL_SIZE 1 +#define RB_DEBUG_0_C_MASK_FULL_SIZE 1 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7 +#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8 +#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17 +#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18 +#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25 +#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26 +#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28 +#define RB_DEBUG_0_C_REQ_FULL_SHIFT 29 +#define RB_DEBUG_0_C_MASK_FULL_SHIFT 30 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020 +#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK 0x00000040 +#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK 0x00000080 +#define RB_DEBUG_0_RDREQ_C1_FULL_MASK 0x00000100 +#define RB_DEBUG_0_RDREQ_C0_FULL_MASK 0x00000200 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000 +#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK 0x00010000 +#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK 0x00020000 +#define RB_DEBUG_0_WRREQ_C1_FULL_MASK 0x00040000 +#define RB_DEBUG_0_WRREQ_C0_FULL_MASK 0x00080000 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000 +#define RB_DEBUG_0_C_SX_LAT_FULL_MASK 0x04000000 +#define RB_DEBUG_0_C_SX_CMD_FULL_MASK 0x08000000 +#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000 +#define RB_DEBUG_0_C_REQ_FULL_MASK 0x20000000 +#define RB_DEBUG_0_C_MASK_FULL_MASK 0x40000000 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000 + +#define RB_DEBUG_0_MASK \ + (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C0_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \ + RB_DEBUG_0_C_SX_LAT_FULL_MASK | \ + RB_DEBUG_0_C_SX_CMD_FULL_MASK | \ + RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \ + RB_DEBUG_0_C_REQ_FULL_MASK | \ + RB_DEBUG_0_C_MASK_FULL_MASK | \ + RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) + +#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \ + ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \ + (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \ + (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \ + (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \ + (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \ + (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \ + (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \ + (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \ + (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \ + (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \ + (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \ + (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \ + (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \ + (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \ + (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \ + (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \ + (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \ + (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \ + (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \ + (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \ + (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \ + (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \ + (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \ + (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \ + (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \ + (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \ + (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)) + +#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + } rb_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + } rb_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_0_t f; +} rb_debug_0_u; + + +/* + * RB_DEBUG_1 struct + */ + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28 +#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT 30 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000 +#define RB_DEBUG_1_C_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_1_C_MASK_EMPTY_MASK 0x40000000 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_1_MASK \ + (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \ + RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \ + RB_DEBUG_1_C_REQ_EMPTY_MASK | \ + RB_DEBUG_1_C_MASK_EMPTY_MASK | \ + RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) + +#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \ + ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \ + (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \ + (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \ + (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \ + (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \ + (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \ + (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \ + (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \ + (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \ + (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \ + (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \ + (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \ + (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \ + (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \ + (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \ + (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \ + (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \ + (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \ + (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \ + (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \ + (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \ + (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \ + (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \ + (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)) + +#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + } rb_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + } rb_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_1_t f; +} rb_debug_1_u; + + +/* + * RB_DEBUG_2 struct + */ + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_FULL_SIZE 1 +#define RB_DEBUG_2_Z_TILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE 1 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16 +#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT 17 +#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT 18 +#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT 19 +#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT 20 +#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT 21 +#define RB_DEBUG_2_Z_TILE_FULL_SHIFT 22 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT 28 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT 30 +#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT 31 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000 +#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000 +#define RB_DEBUG_2_Z0_MASK_FULL_MASK 0x00020000 +#define RB_DEBUG_2_Z1_MASK_FULL_MASK 0x00040000 +#define RB_DEBUG_2_Z0_REQ_FULL_MASK 0x00080000 +#define RB_DEBUG_2_Z1_REQ_FULL_MASK 0x00100000 +#define RB_DEBUG_2_Z_SAMP_FULL_MASK 0x00200000 +#define RB_DEBUG_2_Z_TILE_FULL_MASK 0x00400000 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK 0x04000000 +#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK 0x08000000 +#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK 0x10000000 +#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK 0x40000000 +#define RB_DEBUG_2_Z_TILE_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_2_MASK \ + (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \ + RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \ + RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \ + RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \ + RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \ + RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \ + RB_DEBUG_2_Z0_MASK_FULL_MASK | \ + RB_DEBUG_2_Z1_MASK_FULL_MASK | \ + RB_DEBUG_2_Z0_REQ_FULL_MASK | \ + RB_DEBUG_2_Z1_REQ_FULL_MASK | \ + RB_DEBUG_2_Z_SAMP_FULL_MASK | \ + RB_DEBUG_2_Z_TILE_FULL_MASK | \ + RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \ + RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \ + RB_DEBUG_2_Z_TILE_EMPTY_MASK) + +#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \ + ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \ + (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \ + (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \ + (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \ + (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \ + (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \ + (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \ + (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \ + (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \ + (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \ + (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \ + (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \ + (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \ + (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \ + (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \ + (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \ + (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \ + (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \ + (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \ + (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \ + (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \ + (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \ + (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)) + +#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + } rb_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + } rb_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_2_t f; +} rb_debug_2_u; + + +/* + * RB_DEBUG_3 struct + */ + +#define RB_DEBUG_3_ACCUM_VALID_SIZE 4 +#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4 +#define RB_DEBUG_3_SHD_FULL_SIZE 1 +#define RB_DEBUG_3_SHD_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1 + +#define RB_DEBUG_3_ACCUM_VALID_SHIFT 0 +#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15 +#define RB_DEBUG_3_SHD_FULL_SHIFT 19 +#define RB_DEBUG_3_SHD_EMPTY_SHIFT 20 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28 + +#define RB_DEBUG_3_ACCUM_VALID_MASK 0x0000000f +#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000 +#define RB_DEBUG_3_SHD_FULL_MASK 0x00080000 +#define RB_DEBUG_3_SHD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000 + +#define RB_DEBUG_3_MASK \ + (RB_DEBUG_3_ACCUM_VALID_MASK | \ + RB_DEBUG_3_ACCUM_FLUSHING_MASK | \ + RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \ + RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \ + RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \ + RB_DEBUG_3_SHD_FULL_MASK | \ + RB_DEBUG_3_SHD_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) + +#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \ + ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \ + (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \ + (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \ + (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \ + (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \ + (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \ + (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \ + (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \ + (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \ + (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \ + (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \ + (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \ + (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \ + (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \ + (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)) + +#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int : 3; + } rb_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int : 3; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + } rb_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_3_t f; +} rb_debug_3_u; + + +/* + * RB_DEBUG_4 struct + */ + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00 + +#define RB_DEBUG_4_MASK \ + (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \ + RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \ + RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) + +#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \ + ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \ + (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \ + (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \ + (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \ + (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \ + (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \ + (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \ + (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \ + (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \ + (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)) + +#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int : 19; + } rb_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int : 19; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + } rb_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_4_t f; +} rb_debug_4_u; + + +/* + * RB_FLAG_CONTROL struct + */ + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001 + +#define RB_FLAG_CONTROL_MASK \ + (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) + +#define RB_FLAG_CONTROL(debug_flag_clear) \ + ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)) + +#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \ + ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \ + rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + unsigned int : 31; + } rb_flag_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int : 31; + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + } rb_flag_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_flag_control_t f; +} rb_flag_control_u; + + +/* + * RB_BC_SPARES struct + */ + +#define RB_BC_SPARES_RESERVED_SIZE 32 + +#define RB_BC_SPARES_RESERVED_SHIFT 0 + +#define RB_BC_SPARES_RESERVED_MASK 0xffffffff + +#define RB_BC_SPARES_MASK \ + (RB_BC_SPARES_RESERVED_MASK) + +#define RB_BC_SPARES(reserved) \ + ((reserved << RB_BC_SPARES_RESERVED_SHIFT)) + +#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \ + ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT) + +#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \ + rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_spares_t f; +} rb_bc_spares_u; + + +/* + * BC_DUMMY_CRAYRB_ENUMS struct + */ + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000 + +#define BC_DUMMY_CRAYRB_ENUMS_MASK \ + (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) + +#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \ + ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \ + (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \ + (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \ + (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \ + (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \ + (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \ + (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)) + +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + } bc_dummy_crayrb_enums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + } bc_dummy_crayrb_enums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_enums_t f; +} bc_dummy_crayrb_enums_u; + + +/* + * BC_DUMMY_CRAYRB_MOREENUMS struct + */ + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003 + +#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \ + (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) + +#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \ + ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)) + +#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \ + ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \ + bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + unsigned int : 30; + } bc_dummy_crayrb_moreenums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int : 30; + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + } bc_dummy_crayrb_moreenums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_moreenums_t f; +} bc_dummy_crayrb_moreenums_u; + + +#endif + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h new file mode 100644 index 000000000000..6968abb48bd7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h @@ -0,0 +1,550 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_TYPEDEF_HEADER) +#define _yamato_TYPEDEF_HEADER + +#include "yamato_registers.h" + +typedef union PA_CL_VPORT_XSCALE regPA_CL_VPORT_XSCALE; +typedef union PA_CL_VPORT_XOFFSET regPA_CL_VPORT_XOFFSET; +typedef union PA_CL_VPORT_YSCALE regPA_CL_VPORT_YSCALE; +typedef union PA_CL_VPORT_YOFFSET regPA_CL_VPORT_YOFFSET; +typedef union PA_CL_VPORT_ZSCALE regPA_CL_VPORT_ZSCALE; +typedef union PA_CL_VPORT_ZOFFSET regPA_CL_VPORT_ZOFFSET; +typedef union PA_CL_VTE_CNTL regPA_CL_VTE_CNTL; +typedef union PA_CL_CLIP_CNTL regPA_CL_CLIP_CNTL; +typedef union PA_CL_GB_VERT_CLIP_ADJ regPA_CL_GB_VERT_CLIP_ADJ; +typedef union PA_CL_GB_VERT_DISC_ADJ regPA_CL_GB_VERT_DISC_ADJ; +typedef union PA_CL_GB_HORZ_CLIP_ADJ regPA_CL_GB_HORZ_CLIP_ADJ; +typedef union PA_CL_GB_HORZ_DISC_ADJ regPA_CL_GB_HORZ_DISC_ADJ; +typedef union PA_CL_ENHANCE regPA_CL_ENHANCE; +typedef union PA_SC_ENHANCE regPA_SC_ENHANCE; +typedef union PA_SU_VTX_CNTL regPA_SU_VTX_CNTL; +typedef union PA_SU_POINT_SIZE regPA_SU_POINT_SIZE; +typedef union PA_SU_POINT_MINMAX regPA_SU_POINT_MINMAX; +typedef union PA_SU_LINE_CNTL regPA_SU_LINE_CNTL; +typedef union PA_SU_FACE_DATA regPA_SU_FACE_DATA; +typedef union PA_SU_SC_MODE_CNTL regPA_SU_SC_MODE_CNTL; +typedef union PA_SU_POLY_OFFSET_FRONT_SCALE regPA_SU_POLY_OFFSET_FRONT_SCALE; +typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET regPA_SU_POLY_OFFSET_FRONT_OFFSET; +typedef union PA_SU_POLY_OFFSET_BACK_SCALE regPA_SU_POLY_OFFSET_BACK_SCALE; +typedef union PA_SU_POLY_OFFSET_BACK_OFFSET regPA_SU_POLY_OFFSET_BACK_OFFSET; +typedef union PA_SU_PERFCOUNTER0_SELECT regPA_SU_PERFCOUNTER0_SELECT; +typedef union PA_SU_PERFCOUNTER1_SELECT regPA_SU_PERFCOUNTER1_SELECT; +typedef union PA_SU_PERFCOUNTER2_SELECT regPA_SU_PERFCOUNTER2_SELECT; +typedef union PA_SU_PERFCOUNTER3_SELECT regPA_SU_PERFCOUNTER3_SELECT; +typedef union PA_SU_PERFCOUNTER0_LOW regPA_SU_PERFCOUNTER0_LOW; +typedef union PA_SU_PERFCOUNTER0_HI regPA_SU_PERFCOUNTER0_HI; +typedef union PA_SU_PERFCOUNTER1_LOW regPA_SU_PERFCOUNTER1_LOW; +typedef union PA_SU_PERFCOUNTER1_HI regPA_SU_PERFCOUNTER1_HI; +typedef union PA_SU_PERFCOUNTER2_LOW regPA_SU_PERFCOUNTER2_LOW; +typedef union PA_SU_PERFCOUNTER2_HI regPA_SU_PERFCOUNTER2_HI; +typedef union PA_SU_PERFCOUNTER3_LOW regPA_SU_PERFCOUNTER3_LOW; +typedef union PA_SU_PERFCOUNTER3_HI regPA_SU_PERFCOUNTER3_HI; +typedef union PA_SC_WINDOW_OFFSET regPA_SC_WINDOW_OFFSET; +typedef union PA_SC_AA_CONFIG regPA_SC_AA_CONFIG; +typedef union PA_SC_AA_MASK regPA_SC_AA_MASK; +typedef union PA_SC_LINE_STIPPLE regPA_SC_LINE_STIPPLE; +typedef union PA_SC_LINE_CNTL regPA_SC_LINE_CNTL; +typedef union PA_SC_WINDOW_SCISSOR_TL regPA_SC_WINDOW_SCISSOR_TL; +typedef union PA_SC_WINDOW_SCISSOR_BR regPA_SC_WINDOW_SCISSOR_BR; +typedef union PA_SC_SCREEN_SCISSOR_TL regPA_SC_SCREEN_SCISSOR_TL; +typedef union PA_SC_SCREEN_SCISSOR_BR regPA_SC_SCREEN_SCISSOR_BR; +typedef union PA_SC_VIZ_QUERY regPA_SC_VIZ_QUERY; +typedef union PA_SC_VIZ_QUERY_STATUS regPA_SC_VIZ_QUERY_STATUS; +typedef union PA_SC_LINE_STIPPLE_STATE regPA_SC_LINE_STIPPLE_STATE; +typedef union PA_SC_PERFCOUNTER0_SELECT regPA_SC_PERFCOUNTER0_SELECT; +typedef union PA_SC_PERFCOUNTER0_LOW regPA_SC_PERFCOUNTER0_LOW; +typedef union PA_SC_PERFCOUNTER0_HI regPA_SC_PERFCOUNTER0_HI; +typedef union PA_CL_CNTL_STATUS regPA_CL_CNTL_STATUS; +typedef union PA_SU_CNTL_STATUS regPA_SU_CNTL_STATUS; +typedef union PA_SC_CNTL_STATUS regPA_SC_CNTL_STATUS; +typedef union PA_SU_DEBUG_CNTL regPA_SU_DEBUG_CNTL; +typedef union PA_SU_DEBUG_DATA regPA_SU_DEBUG_DATA; +typedef union PA_SC_DEBUG_CNTL regPA_SC_DEBUG_CNTL; +typedef union PA_SC_DEBUG_DATA regPA_SC_DEBUG_DATA; +typedef union GFX_COPY_STATE regGFX_COPY_STATE; +typedef union VGT_DRAW_INITIATOR regVGT_DRAW_INITIATOR; +typedef union VGT_EVENT_INITIATOR regVGT_EVENT_INITIATOR; +typedef union VGT_DMA_BASE regVGT_DMA_BASE; +typedef union VGT_DMA_SIZE regVGT_DMA_SIZE; +typedef union VGT_BIN_BASE regVGT_BIN_BASE; +typedef union VGT_BIN_SIZE regVGT_BIN_SIZE; +typedef union VGT_CURRENT_BIN_ID_MIN regVGT_CURRENT_BIN_ID_MIN; +typedef union VGT_CURRENT_BIN_ID_MAX regVGT_CURRENT_BIN_ID_MAX; +typedef union VGT_IMMED_DATA regVGT_IMMED_DATA; +typedef union VGT_MAX_VTX_INDX regVGT_MAX_VTX_INDX; +typedef union VGT_MIN_VTX_INDX regVGT_MIN_VTX_INDX; +typedef union VGT_INDX_OFFSET regVGT_INDX_OFFSET; +typedef union VGT_VERTEX_REUSE_BLOCK_CNTL regVGT_VERTEX_REUSE_BLOCK_CNTL; +typedef union VGT_OUT_DEALLOC_CNTL regVGT_OUT_DEALLOC_CNTL; +typedef union VGT_MULTI_PRIM_IB_RESET_INDX regVGT_MULTI_PRIM_IB_RESET_INDX; +typedef union VGT_ENHANCE regVGT_ENHANCE; +typedef union VGT_VTX_VECT_EJECT_REG regVGT_VTX_VECT_EJECT_REG; +typedef union VGT_LAST_COPY_STATE regVGT_LAST_COPY_STATE; +typedef union VGT_DEBUG_CNTL regVGT_DEBUG_CNTL; +typedef union VGT_DEBUG_DATA regVGT_DEBUG_DATA; +typedef union VGT_CNTL_STATUS regVGT_CNTL_STATUS; +typedef union VGT_CRC_SQ_DATA regVGT_CRC_SQ_DATA; +typedef union VGT_CRC_SQ_CTRL regVGT_CRC_SQ_CTRL; +typedef union VGT_PERFCOUNTER0_SELECT regVGT_PERFCOUNTER0_SELECT; +typedef union VGT_PERFCOUNTER1_SELECT regVGT_PERFCOUNTER1_SELECT; +typedef union VGT_PERFCOUNTER2_SELECT regVGT_PERFCOUNTER2_SELECT; +typedef union VGT_PERFCOUNTER3_SELECT regVGT_PERFCOUNTER3_SELECT; +typedef union VGT_PERFCOUNTER0_LOW regVGT_PERFCOUNTER0_LOW; +typedef union VGT_PERFCOUNTER1_LOW regVGT_PERFCOUNTER1_LOW; +typedef union VGT_PERFCOUNTER2_LOW regVGT_PERFCOUNTER2_LOW; +typedef union VGT_PERFCOUNTER3_LOW regVGT_PERFCOUNTER3_LOW; +typedef union VGT_PERFCOUNTER0_HI regVGT_PERFCOUNTER0_HI; +typedef union VGT_PERFCOUNTER1_HI regVGT_PERFCOUNTER1_HI; +typedef union VGT_PERFCOUNTER2_HI regVGT_PERFCOUNTER2_HI; +typedef union VGT_PERFCOUNTER3_HI regVGT_PERFCOUNTER3_HI; +typedef union TC_CNTL_STATUS regTC_CNTL_STATUS; +typedef union TCR_CHICKEN regTCR_CHICKEN; +typedef union TCF_CHICKEN regTCF_CHICKEN; +typedef union TCM_CHICKEN regTCM_CHICKEN; +typedef union TCR_PERFCOUNTER0_SELECT regTCR_PERFCOUNTER0_SELECT; +typedef union TCR_PERFCOUNTER1_SELECT regTCR_PERFCOUNTER1_SELECT; +typedef union TCR_PERFCOUNTER0_HI regTCR_PERFCOUNTER0_HI; +typedef union TCR_PERFCOUNTER1_HI regTCR_PERFCOUNTER1_HI; +typedef union TCR_PERFCOUNTER0_LOW regTCR_PERFCOUNTER0_LOW; +typedef union TCR_PERFCOUNTER1_LOW regTCR_PERFCOUNTER1_LOW; +typedef union TP_TC_CLKGATE_CNTL regTP_TC_CLKGATE_CNTL; +typedef union TPC_CNTL_STATUS regTPC_CNTL_STATUS; +typedef union TPC_DEBUG0 regTPC_DEBUG0; +typedef union TPC_DEBUG1 regTPC_DEBUG1; +typedef union TPC_CHICKEN regTPC_CHICKEN; +typedef union TP0_CNTL_STATUS regTP0_CNTL_STATUS; +typedef union TP0_DEBUG regTP0_DEBUG; +typedef union TP0_CHICKEN regTP0_CHICKEN; +typedef union TP0_PERFCOUNTER0_SELECT regTP0_PERFCOUNTER0_SELECT; +typedef union TP0_PERFCOUNTER0_HI regTP0_PERFCOUNTER0_HI; +typedef union TP0_PERFCOUNTER0_LOW regTP0_PERFCOUNTER0_LOW; +typedef union TP0_PERFCOUNTER1_SELECT regTP0_PERFCOUNTER1_SELECT; +typedef union TP0_PERFCOUNTER1_HI regTP0_PERFCOUNTER1_HI; +typedef union TP0_PERFCOUNTER1_LOW regTP0_PERFCOUNTER1_LOW; +typedef union TCM_PERFCOUNTER0_SELECT regTCM_PERFCOUNTER0_SELECT; +typedef union TCM_PERFCOUNTER1_SELECT regTCM_PERFCOUNTER1_SELECT; +typedef union TCM_PERFCOUNTER0_HI regTCM_PERFCOUNTER0_HI; +typedef union TCM_PERFCOUNTER1_HI regTCM_PERFCOUNTER1_HI; +typedef union TCM_PERFCOUNTER0_LOW regTCM_PERFCOUNTER0_LOW; +typedef union TCM_PERFCOUNTER1_LOW regTCM_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER0_SELECT regTCF_PERFCOUNTER0_SELECT; +typedef union TCF_PERFCOUNTER1_SELECT regTCF_PERFCOUNTER1_SELECT; +typedef union TCF_PERFCOUNTER2_SELECT regTCF_PERFCOUNTER2_SELECT; +typedef union TCF_PERFCOUNTER3_SELECT regTCF_PERFCOUNTER3_SELECT; +typedef union TCF_PERFCOUNTER4_SELECT regTCF_PERFCOUNTER4_SELECT; +typedef union TCF_PERFCOUNTER5_SELECT regTCF_PERFCOUNTER5_SELECT; +typedef union TCF_PERFCOUNTER6_SELECT regTCF_PERFCOUNTER6_SELECT; +typedef union TCF_PERFCOUNTER7_SELECT regTCF_PERFCOUNTER7_SELECT; +typedef union TCF_PERFCOUNTER8_SELECT regTCF_PERFCOUNTER8_SELECT; +typedef union TCF_PERFCOUNTER9_SELECT regTCF_PERFCOUNTER9_SELECT; +typedef union TCF_PERFCOUNTER10_SELECT regTCF_PERFCOUNTER10_SELECT; +typedef union TCF_PERFCOUNTER11_SELECT regTCF_PERFCOUNTER11_SELECT; +typedef union TCF_PERFCOUNTER0_HI regTCF_PERFCOUNTER0_HI; +typedef union TCF_PERFCOUNTER1_HI regTCF_PERFCOUNTER1_HI; +typedef union TCF_PERFCOUNTER2_HI regTCF_PERFCOUNTER2_HI; +typedef union TCF_PERFCOUNTER3_HI regTCF_PERFCOUNTER3_HI; +typedef union TCF_PERFCOUNTER4_HI regTCF_PERFCOUNTER4_HI; +typedef union TCF_PERFCOUNTER5_HI regTCF_PERFCOUNTER5_HI; +typedef union TCF_PERFCOUNTER6_HI regTCF_PERFCOUNTER6_HI; +typedef union TCF_PERFCOUNTER7_HI regTCF_PERFCOUNTER7_HI; +typedef union TCF_PERFCOUNTER8_HI regTCF_PERFCOUNTER8_HI; +typedef union TCF_PERFCOUNTER9_HI regTCF_PERFCOUNTER9_HI; +typedef union TCF_PERFCOUNTER10_HI regTCF_PERFCOUNTER10_HI; +typedef union TCF_PERFCOUNTER11_HI regTCF_PERFCOUNTER11_HI; +typedef union TCF_PERFCOUNTER0_LOW regTCF_PERFCOUNTER0_LOW; +typedef union TCF_PERFCOUNTER1_LOW regTCF_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER2_LOW regTCF_PERFCOUNTER2_LOW; +typedef union TCF_PERFCOUNTER3_LOW regTCF_PERFCOUNTER3_LOW; +typedef union TCF_PERFCOUNTER4_LOW regTCF_PERFCOUNTER4_LOW; +typedef union TCF_PERFCOUNTER5_LOW regTCF_PERFCOUNTER5_LOW; +typedef union TCF_PERFCOUNTER6_LOW regTCF_PERFCOUNTER6_LOW; +typedef union TCF_PERFCOUNTER7_LOW regTCF_PERFCOUNTER7_LOW; +typedef union TCF_PERFCOUNTER8_LOW regTCF_PERFCOUNTER8_LOW; +typedef union TCF_PERFCOUNTER9_LOW regTCF_PERFCOUNTER9_LOW; +typedef union TCF_PERFCOUNTER10_LOW regTCF_PERFCOUNTER10_LOW; +typedef union TCF_PERFCOUNTER11_LOW regTCF_PERFCOUNTER11_LOW; +typedef union TCF_DEBUG regTCF_DEBUG; +typedef union TCA_FIFO_DEBUG regTCA_FIFO_DEBUG; +typedef union TCA_PROBE_DEBUG regTCA_PROBE_DEBUG; +typedef union TCA_TPC_DEBUG regTCA_TPC_DEBUG; +typedef union TCB_CORE_DEBUG regTCB_CORE_DEBUG; +typedef union TCB_TAG0_DEBUG regTCB_TAG0_DEBUG; +typedef union TCB_TAG1_DEBUG regTCB_TAG1_DEBUG; +typedef union TCB_TAG2_DEBUG regTCB_TAG2_DEBUG; +typedef union TCB_TAG3_DEBUG regTCB_TAG3_DEBUG; +typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG; +typedef union TCB_FETCH_GEN_WALKER_DEBUG regTCB_FETCH_GEN_WALKER_DEBUG; +typedef union TCB_FETCH_GEN_PIPE0_DEBUG regTCB_FETCH_GEN_PIPE0_DEBUG; +typedef union TCD_INPUT0_DEBUG regTCD_INPUT0_DEBUG; +typedef union TCD_DEGAMMA_DEBUG regTCD_DEGAMMA_DEBUG; +typedef union TCD_DXTMUX_SCTARB_DEBUG regTCD_DXTMUX_SCTARB_DEBUG; +typedef union TCD_DXTC_ARB_DEBUG regTCD_DXTC_ARB_DEBUG; +typedef union TCD_STALLS_DEBUG regTCD_STALLS_DEBUG; +typedef union TCO_STALLS_DEBUG regTCO_STALLS_DEBUG; +typedef union TCO_QUAD0_DEBUG0 regTCO_QUAD0_DEBUG0; +typedef union TCO_QUAD0_DEBUG1 regTCO_QUAD0_DEBUG1; +typedef union SQ_GPR_MANAGEMENT regSQ_GPR_MANAGEMENT; +typedef union SQ_FLOW_CONTROL regSQ_FLOW_CONTROL; +typedef union SQ_INST_STORE_MANAGMENT regSQ_INST_STORE_MANAGMENT; +typedef union SQ_RESOURCE_MANAGMENT regSQ_RESOURCE_MANAGMENT; +typedef union SQ_EO_RT regSQ_EO_RT; +typedef union SQ_DEBUG_MISC regSQ_DEBUG_MISC; +typedef union SQ_ACTIVITY_METER_CNTL regSQ_ACTIVITY_METER_CNTL; +typedef union SQ_ACTIVITY_METER_STATUS regSQ_ACTIVITY_METER_STATUS; +typedef union SQ_INPUT_ARB_PRIORITY regSQ_INPUT_ARB_PRIORITY; +typedef union SQ_THREAD_ARB_PRIORITY regSQ_THREAD_ARB_PRIORITY; +typedef union SQ_VS_WATCHDOG_TIMER regSQ_VS_WATCHDOG_TIMER; +typedef union SQ_PS_WATCHDOG_TIMER regSQ_PS_WATCHDOG_TIMER; +typedef union SQ_INT_CNTL regSQ_INT_CNTL; +typedef union SQ_INT_STATUS regSQ_INT_STATUS; +typedef union SQ_INT_ACK regSQ_INT_ACK; +typedef union SQ_DEBUG_INPUT_FSM regSQ_DEBUG_INPUT_FSM; +typedef union SQ_DEBUG_CONST_MGR_FSM regSQ_DEBUG_CONST_MGR_FSM; +typedef union SQ_DEBUG_TP_FSM regSQ_DEBUG_TP_FSM; +typedef union SQ_DEBUG_FSM_ALU_0 regSQ_DEBUG_FSM_ALU_0; +typedef union SQ_DEBUG_FSM_ALU_1 regSQ_DEBUG_FSM_ALU_1; +typedef union SQ_DEBUG_EXP_ALLOC regSQ_DEBUG_EXP_ALLOC; +typedef union SQ_DEBUG_PTR_BUFF regSQ_DEBUG_PTR_BUFF; +typedef union SQ_DEBUG_GPR_VTX regSQ_DEBUG_GPR_VTX; +typedef union SQ_DEBUG_GPR_PIX regSQ_DEBUG_GPR_PIX; +typedef union SQ_DEBUG_TB_STATUS_SEL regSQ_DEBUG_TB_STATUS_SEL; +typedef union SQ_DEBUG_VTX_TB_0 regSQ_DEBUG_VTX_TB_0; +typedef union SQ_DEBUG_VTX_TB_1 regSQ_DEBUG_VTX_TB_1; +typedef union SQ_DEBUG_VTX_TB_STATUS_REG regSQ_DEBUG_VTX_TB_STATUS_REG; +typedef union SQ_DEBUG_VTX_TB_STATE_MEM regSQ_DEBUG_VTX_TB_STATE_MEM; +typedef union SQ_DEBUG_PIX_TB_0 regSQ_DEBUG_PIX_TB_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0 regSQ_DEBUG_PIX_TB_STATUS_REG_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1 regSQ_DEBUG_PIX_TB_STATUS_REG_1; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2 regSQ_DEBUG_PIX_TB_STATUS_REG_2; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3 regSQ_DEBUG_PIX_TB_STATUS_REG_3; +typedef union SQ_DEBUG_PIX_TB_STATE_MEM regSQ_DEBUG_PIX_TB_STATE_MEM; +typedef union SQ_PERFCOUNTER0_SELECT regSQ_PERFCOUNTER0_SELECT; +typedef union SQ_PERFCOUNTER1_SELECT regSQ_PERFCOUNTER1_SELECT; +typedef union SQ_PERFCOUNTER2_SELECT regSQ_PERFCOUNTER2_SELECT; +typedef union SQ_PERFCOUNTER3_SELECT regSQ_PERFCOUNTER3_SELECT; +typedef union SQ_PERFCOUNTER0_LOW regSQ_PERFCOUNTER0_LOW; +typedef union SQ_PERFCOUNTER0_HI regSQ_PERFCOUNTER0_HI; +typedef union SQ_PERFCOUNTER1_LOW regSQ_PERFCOUNTER1_LOW; +typedef union SQ_PERFCOUNTER1_HI regSQ_PERFCOUNTER1_HI; +typedef union SQ_PERFCOUNTER2_LOW regSQ_PERFCOUNTER2_LOW; +typedef union SQ_PERFCOUNTER2_HI regSQ_PERFCOUNTER2_HI; +typedef union SQ_PERFCOUNTER3_LOW regSQ_PERFCOUNTER3_LOW; +typedef union SQ_PERFCOUNTER3_HI regSQ_PERFCOUNTER3_HI; +typedef union SX_PERFCOUNTER0_SELECT regSX_PERFCOUNTER0_SELECT; +typedef union SX_PERFCOUNTER0_LOW regSX_PERFCOUNTER0_LOW; +typedef union SX_PERFCOUNTER0_HI regSX_PERFCOUNTER0_HI; +typedef union SQ_INSTRUCTION_ALU_0 regSQ_INSTRUCTION_ALU_0; +typedef union SQ_INSTRUCTION_ALU_1 regSQ_INSTRUCTION_ALU_1; +typedef union SQ_INSTRUCTION_ALU_2 regSQ_INSTRUCTION_ALU_2; +typedef union SQ_INSTRUCTION_CF_EXEC_0 regSQ_INSTRUCTION_CF_EXEC_0; +typedef union SQ_INSTRUCTION_CF_EXEC_1 regSQ_INSTRUCTION_CF_EXEC_1; +typedef union SQ_INSTRUCTION_CF_EXEC_2 regSQ_INSTRUCTION_CF_EXEC_2; +typedef union SQ_INSTRUCTION_CF_LOOP_0 regSQ_INSTRUCTION_CF_LOOP_0; +typedef union SQ_INSTRUCTION_CF_LOOP_1 regSQ_INSTRUCTION_CF_LOOP_1; +typedef union SQ_INSTRUCTION_CF_LOOP_2 regSQ_INSTRUCTION_CF_LOOP_2; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_0 regSQ_INSTRUCTION_CF_JMP_CALL_0; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_1 regSQ_INSTRUCTION_CF_JMP_CALL_1; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_2 regSQ_INSTRUCTION_CF_JMP_CALL_2; +typedef union SQ_INSTRUCTION_CF_ALLOC_0 regSQ_INSTRUCTION_CF_ALLOC_0; +typedef union SQ_INSTRUCTION_CF_ALLOC_1 regSQ_INSTRUCTION_CF_ALLOC_1; +typedef union SQ_INSTRUCTION_CF_ALLOC_2 regSQ_INSTRUCTION_CF_ALLOC_2; +typedef union SQ_INSTRUCTION_TFETCH_0 regSQ_INSTRUCTION_TFETCH_0; +typedef union SQ_INSTRUCTION_TFETCH_1 regSQ_INSTRUCTION_TFETCH_1; +typedef union SQ_INSTRUCTION_TFETCH_2 regSQ_INSTRUCTION_TFETCH_2; +typedef union SQ_INSTRUCTION_VFETCH_0 regSQ_INSTRUCTION_VFETCH_0; +typedef union SQ_INSTRUCTION_VFETCH_1 regSQ_INSTRUCTION_VFETCH_1; +typedef union SQ_INSTRUCTION_VFETCH_2 regSQ_INSTRUCTION_VFETCH_2; +typedef union SQ_CONSTANT_0 regSQ_CONSTANT_0; +typedef union SQ_CONSTANT_1 regSQ_CONSTANT_1; +typedef union SQ_CONSTANT_2 regSQ_CONSTANT_2; +typedef union SQ_CONSTANT_3 regSQ_CONSTANT_3; +typedef union SQ_FETCH_0 regSQ_FETCH_0; +typedef union SQ_FETCH_1 regSQ_FETCH_1; +typedef union SQ_FETCH_2 regSQ_FETCH_2; +typedef union SQ_FETCH_3 regSQ_FETCH_3; +typedef union SQ_FETCH_4 regSQ_FETCH_4; +typedef union SQ_FETCH_5 regSQ_FETCH_5; +typedef union SQ_CONSTANT_VFETCH_0 regSQ_CONSTANT_VFETCH_0; +typedef union SQ_CONSTANT_VFETCH_1 regSQ_CONSTANT_VFETCH_1; +typedef union SQ_CONSTANT_T2 regSQ_CONSTANT_T2; +typedef union SQ_CONSTANT_T3 regSQ_CONSTANT_T3; +typedef union SQ_CF_BOOLEANS regSQ_CF_BOOLEANS; +typedef union SQ_CF_LOOP regSQ_CF_LOOP; +typedef union SQ_CONSTANT_RT_0 regSQ_CONSTANT_RT_0; +typedef union SQ_CONSTANT_RT_1 regSQ_CONSTANT_RT_1; +typedef union SQ_CONSTANT_RT_2 regSQ_CONSTANT_RT_2; +typedef union SQ_CONSTANT_RT_3 regSQ_CONSTANT_RT_3; +typedef union SQ_FETCH_RT_0 regSQ_FETCH_RT_0; +typedef union SQ_FETCH_RT_1 regSQ_FETCH_RT_1; +typedef union SQ_FETCH_RT_2 regSQ_FETCH_RT_2; +typedef union SQ_FETCH_RT_3 regSQ_FETCH_RT_3; +typedef union SQ_FETCH_RT_4 regSQ_FETCH_RT_4; +typedef union SQ_FETCH_RT_5 regSQ_FETCH_RT_5; +typedef union SQ_CF_RT_BOOLEANS regSQ_CF_RT_BOOLEANS; +typedef union SQ_CF_RT_LOOP regSQ_CF_RT_LOOP; +typedef union SQ_VS_PROGRAM regSQ_VS_PROGRAM; +typedef union SQ_PS_PROGRAM regSQ_PS_PROGRAM; +typedef union SQ_CF_PROGRAM_SIZE regSQ_CF_PROGRAM_SIZE; +typedef union SQ_INTERPOLATOR_CNTL regSQ_INTERPOLATOR_CNTL; +typedef union SQ_PROGRAM_CNTL regSQ_PROGRAM_CNTL; +typedef union SQ_WRAPPING_0 regSQ_WRAPPING_0; +typedef union SQ_WRAPPING_1 regSQ_WRAPPING_1; +typedef union SQ_VS_CONST regSQ_VS_CONST; +typedef union SQ_PS_CONST regSQ_PS_CONST; +typedef union SQ_CONTEXT_MISC regSQ_CONTEXT_MISC; +typedef union SQ_CF_RD_BASE regSQ_CF_RD_BASE; +typedef union SQ_DEBUG_MISC_0 regSQ_DEBUG_MISC_0; +typedef union SQ_DEBUG_MISC_1 regSQ_DEBUG_MISC_1; +typedef union MH_ARBITER_CONFIG regMH_ARBITER_CONFIG; +typedef union MH_CLNT_AXI_ID_REUSE regMH_CLNT_AXI_ID_REUSE; +typedef union MH_INTERRUPT_MASK regMH_INTERRUPT_MASK; +typedef union MH_INTERRUPT_STATUS regMH_INTERRUPT_STATUS; +typedef union MH_INTERRUPT_CLEAR regMH_INTERRUPT_CLEAR; +typedef union MH_AXI_ERROR regMH_AXI_ERROR; +typedef union MH_PERFCOUNTER0_SELECT regMH_PERFCOUNTER0_SELECT; +typedef union MH_PERFCOUNTER1_SELECT regMH_PERFCOUNTER1_SELECT; +typedef union MH_PERFCOUNTER0_CONFIG regMH_PERFCOUNTER0_CONFIG; +typedef union MH_PERFCOUNTER1_CONFIG regMH_PERFCOUNTER1_CONFIG; +typedef union MH_PERFCOUNTER0_LOW regMH_PERFCOUNTER0_LOW; +typedef union MH_PERFCOUNTER1_LOW regMH_PERFCOUNTER1_LOW; +typedef union MH_PERFCOUNTER0_HI regMH_PERFCOUNTER0_HI; +typedef union MH_PERFCOUNTER1_HI regMH_PERFCOUNTER1_HI; +typedef union MH_DEBUG_CTRL regMH_DEBUG_CTRL; +typedef union MH_DEBUG_DATA regMH_DEBUG_DATA; +typedef union MH_AXI_HALT_CONTROL regMH_AXI_HALT_CONTROL; +typedef union MH_MMU_CONFIG regMH_MMU_CONFIG; +typedef union MH_MMU_VA_RANGE regMH_MMU_VA_RANGE; +typedef union MH_MMU_PT_BASE regMH_MMU_PT_BASE; +typedef union MH_MMU_PAGE_FAULT regMH_MMU_PAGE_FAULT; +typedef union MH_MMU_TRAN_ERROR regMH_MMU_TRAN_ERROR; +typedef union MH_MMU_INVALIDATE regMH_MMU_INVALIDATE; +typedef union MH_MMU_MPU_BASE regMH_MMU_MPU_BASE; +typedef union MH_MMU_MPU_END regMH_MMU_MPU_END; +typedef union WAIT_UNTIL regWAIT_UNTIL; +typedef union RBBM_ISYNC_CNTL regRBBM_ISYNC_CNTL; +typedef union RBBM_STATUS regRBBM_STATUS; +typedef union RBBM_DSPLY regRBBM_DSPLY; +typedef union RBBM_RENDER_LATEST regRBBM_RENDER_LATEST; +typedef union RBBM_RTL_RELEASE regRBBM_RTL_RELEASE; +typedef union RBBM_PATCH_RELEASE regRBBM_PATCH_RELEASE; +typedef union RBBM_AUXILIARY_CONFIG regRBBM_AUXILIARY_CONFIG; +typedef union RBBM_PERIPHID0 regRBBM_PERIPHID0; +typedef union RBBM_PERIPHID1 regRBBM_PERIPHID1; +typedef union RBBM_PERIPHID2 regRBBM_PERIPHID2; +typedef union RBBM_PERIPHID3 regRBBM_PERIPHID3; +typedef union RBBM_CNTL regRBBM_CNTL; +typedef union RBBM_SKEW_CNTL regRBBM_SKEW_CNTL; +typedef union RBBM_SOFT_RESET regRBBM_SOFT_RESET; +typedef union RBBM_PM_OVERRIDE1 regRBBM_PM_OVERRIDE1; +typedef union RBBM_PM_OVERRIDE2 regRBBM_PM_OVERRIDE2; +typedef union GC_SYS_IDLE regGC_SYS_IDLE; +typedef union NQWAIT_UNTIL regNQWAIT_UNTIL; +typedef union RBBM_DEBUG_OUT regRBBM_DEBUG_OUT; +typedef union RBBM_DEBUG_CNTL regRBBM_DEBUG_CNTL; +typedef union RBBM_DEBUG regRBBM_DEBUG; +typedef union RBBM_READ_ERROR regRBBM_READ_ERROR; +typedef union RBBM_WAIT_IDLE_CLOCKS regRBBM_WAIT_IDLE_CLOCKS; +typedef union RBBM_INT_CNTL regRBBM_INT_CNTL; +typedef union RBBM_INT_STATUS regRBBM_INT_STATUS; +typedef union RBBM_INT_ACK regRBBM_INT_ACK; +typedef union MASTER_INT_SIGNAL regMASTER_INT_SIGNAL; +typedef union RBBM_PERFCOUNTER1_SELECT regRBBM_PERFCOUNTER1_SELECT; +typedef union RBBM_PERFCOUNTER1_LO regRBBM_PERFCOUNTER1_LO; +typedef union RBBM_PERFCOUNTER1_HI regRBBM_PERFCOUNTER1_HI; +typedef union CP_RB_BASE regCP_RB_BASE; +typedef union CP_RB_CNTL regCP_RB_CNTL; +typedef union CP_RB_RPTR_ADDR regCP_RB_RPTR_ADDR; +typedef union CP_RB_RPTR regCP_RB_RPTR; +typedef union CP_RB_RPTR_WR regCP_RB_RPTR_WR; +typedef union CP_RB_WPTR regCP_RB_WPTR; +typedef union CP_RB_WPTR_DELAY regCP_RB_WPTR_DELAY; +typedef union CP_RB_WPTR_BASE regCP_RB_WPTR_BASE; +typedef union CP_IB1_BASE regCP_IB1_BASE; +typedef union CP_IB1_BUFSZ regCP_IB1_BUFSZ; +typedef union CP_IB2_BASE regCP_IB2_BASE; +typedef union CP_IB2_BUFSZ regCP_IB2_BUFSZ; +typedef union CP_ST_BASE regCP_ST_BASE; +typedef union CP_ST_BUFSZ regCP_ST_BUFSZ; +typedef union CP_QUEUE_THRESHOLDS regCP_QUEUE_THRESHOLDS; +typedef union CP_MEQ_THRESHOLDS regCP_MEQ_THRESHOLDS; +typedef union CP_CSQ_AVAIL regCP_CSQ_AVAIL; +typedef union CP_STQ_AVAIL regCP_STQ_AVAIL; +typedef union CP_MEQ_AVAIL regCP_MEQ_AVAIL; +typedef union CP_CSQ_RB_STAT regCP_CSQ_RB_STAT; +typedef union CP_CSQ_IB1_STAT regCP_CSQ_IB1_STAT; +typedef union CP_CSQ_IB2_STAT regCP_CSQ_IB2_STAT; +typedef union CP_NON_PREFETCH_CNTRS regCP_NON_PREFETCH_CNTRS; +typedef union CP_STQ_ST_STAT regCP_STQ_ST_STAT; +typedef union CP_MEQ_STAT regCP_MEQ_STAT; +typedef union CP_MIU_TAG_STAT regCP_MIU_TAG_STAT; +typedef union CP_CMD_INDEX regCP_CMD_INDEX; +typedef union CP_CMD_DATA regCP_CMD_DATA; +typedef union CP_ME_CNTL regCP_ME_CNTL; +typedef union CP_ME_STATUS regCP_ME_STATUS; +typedef union CP_ME_RAM_WADDR regCP_ME_RAM_WADDR; +typedef union CP_ME_RAM_RADDR regCP_ME_RAM_RADDR; +typedef union CP_ME_RAM_DATA regCP_ME_RAM_DATA; +typedef union CP_ME_RDADDR regCP_ME_RDADDR; +typedef union CP_DEBUG regCP_DEBUG; +typedef union SCRATCH_REG0 regSCRATCH_REG0; +typedef union GUI_SCRATCH_REG0 regGUI_SCRATCH_REG0; +typedef union SCRATCH_REG1 regSCRATCH_REG1; +typedef union GUI_SCRATCH_REG1 regGUI_SCRATCH_REG1; +typedef union SCRATCH_REG2 regSCRATCH_REG2; +typedef union GUI_SCRATCH_REG2 regGUI_SCRATCH_REG2; +typedef union SCRATCH_REG3 regSCRATCH_REG3; +typedef union GUI_SCRATCH_REG3 regGUI_SCRATCH_REG3; +typedef union SCRATCH_REG4 regSCRATCH_REG4; +typedef union GUI_SCRATCH_REG4 regGUI_SCRATCH_REG4; +typedef union SCRATCH_REG5 regSCRATCH_REG5; +typedef union GUI_SCRATCH_REG5 regGUI_SCRATCH_REG5; +typedef union SCRATCH_REG6 regSCRATCH_REG6; +typedef union GUI_SCRATCH_REG6 regGUI_SCRATCH_REG6; +typedef union SCRATCH_REG7 regSCRATCH_REG7; +typedef union GUI_SCRATCH_REG7 regGUI_SCRATCH_REG7; +typedef union SCRATCH_UMSK regSCRATCH_UMSK; +typedef union SCRATCH_ADDR regSCRATCH_ADDR; +typedef union CP_ME_VS_EVENT_SRC regCP_ME_VS_EVENT_SRC; +typedef union CP_ME_VS_EVENT_ADDR regCP_ME_VS_EVENT_ADDR; +typedef union CP_ME_VS_EVENT_DATA regCP_ME_VS_EVENT_DATA; +typedef union CP_ME_VS_EVENT_ADDR_SWM regCP_ME_VS_EVENT_ADDR_SWM; +typedef union CP_ME_VS_EVENT_DATA_SWM regCP_ME_VS_EVENT_DATA_SWM; +typedef union CP_ME_PS_EVENT_SRC regCP_ME_PS_EVENT_SRC; +typedef union CP_ME_PS_EVENT_ADDR regCP_ME_PS_EVENT_ADDR; +typedef union CP_ME_PS_EVENT_DATA regCP_ME_PS_EVENT_DATA; +typedef union CP_ME_PS_EVENT_ADDR_SWM regCP_ME_PS_EVENT_ADDR_SWM; +typedef union CP_ME_PS_EVENT_DATA_SWM regCP_ME_PS_EVENT_DATA_SWM; +typedef union CP_ME_CF_EVENT_SRC regCP_ME_CF_EVENT_SRC; +typedef union CP_ME_CF_EVENT_ADDR regCP_ME_CF_EVENT_ADDR; +typedef union CP_ME_CF_EVENT_DATA regCP_ME_CF_EVENT_DATA; +typedef union CP_ME_NRT_ADDR regCP_ME_NRT_ADDR; +typedef union CP_ME_NRT_DATA regCP_ME_NRT_DATA; +typedef union CP_ME_VS_FETCH_DONE_SRC regCP_ME_VS_FETCH_DONE_SRC; +typedef union CP_ME_VS_FETCH_DONE_ADDR regCP_ME_VS_FETCH_DONE_ADDR; +typedef union CP_ME_VS_FETCH_DONE_DATA regCP_ME_VS_FETCH_DONE_DATA; +typedef union CP_INT_CNTL regCP_INT_CNTL; +typedef union CP_INT_STATUS regCP_INT_STATUS; +typedef union CP_INT_ACK regCP_INT_ACK; +typedef union CP_PFP_UCODE_ADDR regCP_PFP_UCODE_ADDR; +typedef union CP_PFP_UCODE_DATA regCP_PFP_UCODE_DATA; +typedef union CP_PERFMON_CNTL regCP_PERFMON_CNTL; +typedef union CP_PERFCOUNTER_SELECT regCP_PERFCOUNTER_SELECT; +typedef union CP_PERFCOUNTER_LO regCP_PERFCOUNTER_LO; +typedef union CP_PERFCOUNTER_HI regCP_PERFCOUNTER_HI; +typedef union CP_BIN_MASK_LO regCP_BIN_MASK_LO; +typedef union CP_BIN_MASK_HI regCP_BIN_MASK_HI; +typedef union CP_BIN_SELECT_LO regCP_BIN_SELECT_LO; +typedef union CP_BIN_SELECT_HI regCP_BIN_SELECT_HI; +typedef union CP_NV_FLAGS_0 regCP_NV_FLAGS_0; +typedef union CP_NV_FLAGS_1 regCP_NV_FLAGS_1; +typedef union CP_NV_FLAGS_2 regCP_NV_FLAGS_2; +typedef union CP_NV_FLAGS_3 regCP_NV_FLAGS_3; +typedef union CP_STATE_DEBUG_INDEX regCP_STATE_DEBUG_INDEX; +typedef union CP_STATE_DEBUG_DATA regCP_STATE_DEBUG_DATA; +typedef union CP_PROG_COUNTER regCP_PROG_COUNTER; +typedef union CP_STAT regCP_STAT; +typedef union BIOS_0_SCRATCH regBIOS_0_SCRATCH; +typedef union BIOS_1_SCRATCH regBIOS_1_SCRATCH; +typedef union BIOS_2_SCRATCH regBIOS_2_SCRATCH; +typedef union BIOS_3_SCRATCH regBIOS_3_SCRATCH; +typedef union BIOS_4_SCRATCH regBIOS_4_SCRATCH; +typedef union BIOS_5_SCRATCH regBIOS_5_SCRATCH; +typedef union BIOS_6_SCRATCH regBIOS_6_SCRATCH; +typedef union BIOS_7_SCRATCH regBIOS_7_SCRATCH; +typedef union BIOS_8_SCRATCH regBIOS_8_SCRATCH; +typedef union BIOS_9_SCRATCH regBIOS_9_SCRATCH; +typedef union BIOS_10_SCRATCH regBIOS_10_SCRATCH; +typedef union BIOS_11_SCRATCH regBIOS_11_SCRATCH; +typedef union BIOS_12_SCRATCH regBIOS_12_SCRATCH; +typedef union BIOS_13_SCRATCH regBIOS_13_SCRATCH; +typedef union BIOS_14_SCRATCH regBIOS_14_SCRATCH; +typedef union BIOS_15_SCRATCH regBIOS_15_SCRATCH; +typedef union COHER_SIZE_PM4 regCOHER_SIZE_PM4; +typedef union COHER_BASE_PM4 regCOHER_BASE_PM4; +typedef union COHER_STATUS_PM4 regCOHER_STATUS_PM4; +typedef union COHER_SIZE_HOST regCOHER_SIZE_HOST; +typedef union COHER_BASE_HOST regCOHER_BASE_HOST; +typedef union COHER_STATUS_HOST regCOHER_STATUS_HOST; +typedef union COHER_DEST_BASE_0 regCOHER_DEST_BASE_0; +typedef union COHER_DEST_BASE_1 regCOHER_DEST_BASE_1; +typedef union COHER_DEST_BASE_2 regCOHER_DEST_BASE_2; +typedef union COHER_DEST_BASE_3 regCOHER_DEST_BASE_3; +typedef union COHER_DEST_BASE_4 regCOHER_DEST_BASE_4; +typedef union COHER_DEST_BASE_5 regCOHER_DEST_BASE_5; +typedef union COHER_DEST_BASE_6 regCOHER_DEST_BASE_6; +typedef union COHER_DEST_BASE_7 regCOHER_DEST_BASE_7; +typedef union RB_SURFACE_INFO regRB_SURFACE_INFO; +typedef union RB_COLOR_INFO regRB_COLOR_INFO; +typedef union RB_DEPTH_INFO regRB_DEPTH_INFO; +typedef union RB_STENCILREFMASK regRB_STENCILREFMASK; +typedef union RB_ALPHA_REF regRB_ALPHA_REF; +typedef union RB_COLOR_MASK regRB_COLOR_MASK; +typedef union RB_BLEND_RED regRB_BLEND_RED; +typedef union RB_BLEND_GREEN regRB_BLEND_GREEN; +typedef union RB_BLEND_BLUE regRB_BLEND_BLUE; +typedef union RB_BLEND_ALPHA regRB_BLEND_ALPHA; +typedef union RB_FOG_COLOR regRB_FOG_COLOR; +typedef union RB_STENCILREFMASK_BF regRB_STENCILREFMASK_BF; +typedef union RB_DEPTHCONTROL regRB_DEPTHCONTROL; +typedef union RB_BLENDCONTROL regRB_BLENDCONTROL; +typedef union RB_COLORCONTROL regRB_COLORCONTROL; +typedef union RB_MODECONTROL regRB_MODECONTROL; +typedef union RB_COLOR_DEST_MASK regRB_COLOR_DEST_MASK; +typedef union RB_COPY_CONTROL regRB_COPY_CONTROL; +typedef union RB_COPY_DEST_BASE regRB_COPY_DEST_BASE; +typedef union RB_COPY_DEST_PITCH regRB_COPY_DEST_PITCH; +typedef union RB_COPY_DEST_INFO regRB_COPY_DEST_INFO; +typedef union RB_COPY_DEST_PIXEL_OFFSET regRB_COPY_DEST_PIXEL_OFFSET; +typedef union RB_DEPTH_CLEAR regRB_DEPTH_CLEAR; +typedef union RB_SAMPLE_COUNT_CTL regRB_SAMPLE_COUNT_CTL; +typedef union RB_SAMPLE_COUNT_ADDR regRB_SAMPLE_COUNT_ADDR; +typedef union RB_BC_CONTROL regRB_BC_CONTROL; +typedef union RB_EDRAM_INFO regRB_EDRAM_INFO; +typedef union RB_CRC_RD_PORT regRB_CRC_RD_PORT; +typedef union RB_CRC_CONTROL regRB_CRC_CONTROL; +typedef union RB_CRC_MASK regRB_CRC_MASK; +typedef union RB_PERFCOUNTER0_SELECT regRB_PERFCOUNTER0_SELECT; +typedef union RB_PERFCOUNTER0_LOW regRB_PERFCOUNTER0_LOW; +typedef union RB_PERFCOUNTER0_HI regRB_PERFCOUNTER0_HI; +typedef union RB_TOTAL_SAMPLES regRB_TOTAL_SAMPLES; +typedef union RB_ZPASS_SAMPLES regRB_ZPASS_SAMPLES; +typedef union RB_ZFAIL_SAMPLES regRB_ZFAIL_SAMPLES; +typedef union RB_SFAIL_SAMPLES regRB_SFAIL_SAMPLES; +typedef union RB_DEBUG_0 regRB_DEBUG_0; +typedef union RB_DEBUG_1 regRB_DEBUG_1; +typedef union RB_DEBUG_2 regRB_DEBUG_2; +typedef union RB_DEBUG_3 regRB_DEBUG_3; +typedef union RB_DEBUG_4 regRB_DEBUG_4; +typedef union RB_FLAG_CONTROL regRB_FLAG_CONTROL; +typedef union RB_BC_SPARES regRB_BC_SPARES; +typedef union BC_DUMMY_CRAYRB_ENUMS regBC_DUMMY_CRAYRB_ENUMS; +typedef union BC_DUMMY_CRAYRB_MOREENUMS regBC_DUMMY_CRAYRB_MOREENUMS; +#endif diff --git a/drivers/mxc/amd-gpu/os/include/os_types.h b/drivers/mxc/amd-gpu/os/include/os_types.h new file mode 100644 index 000000000000..e7ecd90f8952 --- /dev/null +++ b/drivers/mxc/amd-gpu/os/include/os_types.h @@ -0,0 +1,138 @@ + /* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of QUALCOMM Incorporated nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __OSTYPES_H +#define __OSTYPES_H + +////////////////////////////////////////////////////////////////////////////// +// status +////////////////////////////////////////////////////////////////////////////// +#define OS_SUCCESS 0 +#define OS_FAILURE -1 +#define OS_FAILURE_SYSTEMERROR -2 +#define OS_FAILURE_DEVICEERROR -3 +#define OS_FAILURE_OUTOFMEM -4 +#define OS_FAILURE_BADPARAM -5 +#define OS_FAILURE_NOTSUPPORTED -6 +#define OS_FAILURE_NOMOREAVAILABLE -7 +#define OS_FAILURE_NOTINITIALIZED -8 +#define OS_FAILURE_ALREADYINITIALIZED -9 +#define OS_FAILURE_TIMEOUT -10 + + +////////////////////////////////////////////////////////////////////////////// +// inline +////////////////////////////////////////////////////////////////////////////// +#ifndef OSINLINE +#ifdef _LINUX +#define OSINLINE static __inline +#else +#define OSINLINE __inline +#endif +#endif // OSINLINE + + +////////////////////////////////////////////////////////////////////////////// +// values +////////////////////////////////////////////////////////////////////////////// +#define OS_INFINITE 0xFFFFFFFF +#define OS_TLS_OUTOFINDEXES 0xFFFFFFFF +#define OS_TRUE 1 +#define OS_FALSE 0 + +#ifndef NULL +#define NULL (void *)0x0 +#endif // !NULL + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + + +// +// oshandle_t +// +typedef void * oshandle_t; +#define OS_HANDLE_NULL (oshandle_t)0x0 + +// +// os_sysinfo_t +// +typedef struct _os_sysinfo_t { + int cpu_mhz; + int cpu_type; + int cpu_version; + int os_type; + int os_version; + int sysmem_size; + int page_size; + int max_path; + int tls_slots; + int endianness; // 0 == little_endian, 1 == big_endian +} os_sysinfo_t; + + +// +// os_stats_t +// +#ifdef _LINUX +typedef long long __int64; +typedef unsigned long long __uint64; +#else +typedef unsigned __int64 __uint64; +#endif + +typedef struct _os_stats_t { + __int64 heap_allocs; + __int64 heap_frees; + __int64 heap_alloc_bytes; + __int64 shared_heap_allocs; + __int64 shared_heap_frees; + __int64 shared_heap_alloc_bytes; + __int64 objects_alloc; + __int64 objects_free; +} os_stats_t; + + +typedef enum { + OS_PROTECTION_GLOBAL, // inter process + OS_PROTECTION_LOCAL, // process local + OS_PROTECTION_NONE, // none +} os_protection_t; + +typedef struct _os_cputimer_t { + int refcount; // Reference count + int enabled; // Counter is enabled + int size; // Number of counters + __int64 start_time; // start time in cpu ticks + __int64 end_time; // end time in cpu ticks + __int64 timer_frequency; // cpu ticks per second + __int64 *counter_array; // number of ticks for each counter +} os_cputimer_t; + +#endif // __OSTYPES_H diff --git a/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h b/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h new file mode 100644 index 000000000000..a02c396c22a9 --- /dev/null +++ b/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h @@ -0,0 +1,813 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __KOSAPI_H +#define __KOSAPI_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#include "os_types.h" + + +////////////////////////////////////////////////////////////////////////////// +// entrypoint abstraction +////////////////////////////////////////////////////////////////////////////// + + +#if defined(_WIN32) && !defined (_WIN32_WCE) && !defined(__SYMBIAN32__) +#define KOS_DLLEXPORT __declspec(dllexport) +#define KOS_DLLIMPORT __declspec(dllimport) +#elif defined(_WIN32) && defined (_WIN32_WCE) +#define KOS_DLLEXPORT __declspec(dllexport) +#define KOS_DLLIMPORT +#else +#define KOS_DLLEXPORT extern +#define KOS_DLLIMPORT +#endif // _WIN32 + + +////////////////////////////////////////////////////////////////////////////// +// KOS lib entrypoints +////////////////////////////////////////////////////////////////////////////// +#ifdef __KOSLIB_EXPORTS +#define KOS_API KOS_DLLEXPORT +#else +#define KOS_API KOS_DLLIMPORT +#endif // __KOSLIB_EXPORTS + +////////////////////////////////////////////////////////////////////////////// +// assert API +////////////////////////////////////////////////////////////////////////////// +KOS_API void kos_assert_hook(const char* file, int line, int expression); + +#if defined(DEBUG) || defined(DBG) || defined (_DBG) || defined (_DEBUG) + +#if defined(_WIN32) && !defined(__SYMBIAN32__) || defined(_WIN32_WCE) +#include +#define KOS_ASSERT(expression) assert(expression) +#elif defined(_BREW) +#include +#define KOS_ASSERT(expression) kos_assert_hook(__FILE__, __LINE__, expression) +#elif defined(__SYMBIAN32__) +//#include +//#define KOS_ASSERT(expression) assert(expression) +#define KOS_ASSERT(expression) /**/ +#elif defined(__ARM__) +#define KOS_ASSERT(expression) +#elif defined(_LINUX) +#define KOS_ASSERT(expression) //kos_assert_hook(__FILE__, __LINE__, (int)(expression)) +#endif + +#else + +#define KOS_ASSERT(expression) + +#endif // DEBUG || DBG || _DBG + +#if defined(_WIN32) && defined(_DEBUG) && !defined(_WIN32_WCE) && !defined(__SYMBIAN32__) +#pragma warning ( push, 3 ) +#include +#pragma warning (pop) +#define KOS_MALLOC_DBG(size) _malloc_dbg(size, _NORMAL_BLOCK, __FILE__, __LINE__) +#else +#define KOS_MALLOC_DBG(size) kos_malloc(int size) +#endif // _WIN32 _DEBUG + +#define kos_assert(expression) KOS_ASSERT(expression) +#define kos_malloc_dbg(size) KOS_MALLOC_DBG(size) + +#ifdef UNDER_CE +#define KOS_PAGE_SIZE 0x1000 +#endif + +typedef enum mutexIndex mutexIndex_t; +////////////////////////////////////////////////////////////////////////////// +// Interprocess shared memory initialization +////////////////////////////////////////////////////////////////////////////// +// TODO: still valid? +KOS_API int kos_sharedmem_create(unsigned int map_addr, unsigned int size); +KOS_API int kos_sharedmem_destroy(void); + +////////////////////////////////////////////////////////////////////////////// +// heap API (per process) +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocate memory for a kernel side process. + * + * + * \param int size Amount of bytes to be allocated. + * \return Pointer to the reserved memory, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_malloc(int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocate memory for a kernel side process. Clears the reserved memory. + * + * + * \param int num Number of elements to allocate. + * \param int size Element size in bytes. + * \return Pointer to the reserved memory, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_calloc(int num, int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Re-allocate an existing memory for a kernel side process. + * Contents of the old block will be copied to the new block + * taking the sizes of both blocks into account. + * + * + * \param void* memblock Pointer to the old memory block. + * \param int size Size of the new block in bytes. + * \return Pointer to the new memory block, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_realloc(void* memblock, int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Free a reserved memory block from the kernel side process. + * + * + * \param void* memblock Pointer to the memory block. + *//*-------------------------------------------------------------------*/ +KOS_API void kos_free(void* memblock); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Enable automatic memory leak checking performed at program exit. + * + * + *//*-------------------------------------------------------------------*/ +KOS_API void kos_enable_memoryleakcheck(void); + + +////////////////////////////////////////////////////////////////////////////// +// shared heap API (cross process) +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocate memory that can be shared between user and kernel + * side processes. + * + * + * \param int size Amount of bytes to be allocated. + * \return Pointer to the new memory block, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_shared_malloc(int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocate memory that can be shared between user and kernel + * side processes. Clears the reserved memory. + * + * + * \param int num Number of elements to allocate. + * \param int size Element size in bytes. + * \return Pointer to the reserved memory, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_shared_calloc(int num, int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Re-allocate an existing user/kernel shared memory block. + * Contents of the old block will be copied to the new block + * taking the sizes of both blocks into account. + * + * + * \param void* ptr Pointer to the old memory block. + * \param int size Size of the new block in bytes. + * \return Pointer to the new memory block, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_shared_realloc(void* ptr, int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Free a reserved shared memory block. + * + * + * \param void* ptr Pointer to the memory block. + *//*-------------------------------------------------------------------*/ + KOS_API void kos_shared_free(void* ptr); + + +////////////////////////////////////////////////////////////////////////////// +// memory API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Copies the values of num bytes from the location pointed by src + * directly to the memory block pointed by dst. + * + * + * \param void* dst Pointer to the destination memory block. + * \param void* src Pointer to the source memory block. + * \param void* count Amount of bytes to copy. + * \return Returns the dst pointer, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_memcpy(void* dst, const void* src, int count); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Fills the destination memory block with the given value. + * + * + * \param void* dst Pointer to the destination memory block. + * \param int value Value to be written to each destination address. + * \param void* count Number of bytes to be set to the value. + * \return Returns the dst pointer, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_memset(void* dst, int value, int count); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Compares two memory blocks. + * + * + * \param void* dst Pointer to the destination memory block. + * \param void* src Pointer to the source memory block. + * \param void* count Number of bytes to compare. + * \return Zero if identical, >0 if first nonmatching byte is greater in dst. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_memcmp(void* dst, void* src, int count); + + +////////////////////////////////////////////////////////////////////////////// +// physical memory API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocates a physically contiguous memory block. + * + * + * \param void** virt_addr Pointer where to store the virtual address of the reserved block. + * \param void** phys_addr Pointer where to store the physical address of the reserved block. + * \param int pages Number of pages to reserve (default page size = 4096 bytes). + * \return Zero if ok, othervise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_alloc_physical(void** virt_addr, void** phys_addr, int pages); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Free a physically contiguous allocated memory block. + * + * + * \param void* virt_addr Virtual address of the memory block. + * \param int pages Number of pages. + * \return Zero if ok, othervise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_free_physical(void* virt_addr, int pages); + +KOS_API void kos_memoryfence(void); + + +////////////////////////////////////////////////////////////////////////////// +// string API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Perform a string copy. + * + * + * \param void* strdestination Pointer to destination memory. + * \param void* strsource Pointer to the source string. + * \return Zero if ok, othervise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API char* kos_strcpy(char* strdestination, const char* strsource); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Perform a string copy with given length. + * + * + * \param void* destination Pointer to destination memory. + * \param void* source Pointer to the source string. + * \param int length Amount of bytes to copy. + * \return Returns the destination pointer. + *//*-------------------------------------------------------------------*/ +KOS_API char* kos_strncpy(char* destination, const char* source, int length); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Append source string to destination string. + * + * + * \param void* strdestination Pointer to destination string. + * \param void* strsource Pointer to the source string. + * \return Returns the destination pointer. + *//*-------------------------------------------------------------------*/ +KOS_API char* kos_strcat(char* strdestination, const char* strsource); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Compare two strings. + * + * + * \param void* string1 Pointer to first string. + * \param void* string2 Pointer to second string. + * \param void* length Number of bytes to compare. + * \return Zero if identical, >0 if first string is lexically greater <0 if not. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_strcmp(const char* string1, const char* string2); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Compares two strings of given length. + * + * + * \param void* string1 Pointer to first string. + * \param void* string2 Pointer to second string. + * \param void* length Number of bytes to compare. + * \return Zero if identical, >0 if first string is lexically greater <0 if not. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_strncmp(const char* string1, const char* string2, int length); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Calculates the length of a string.. + * + * + * \param void* string Pointer to the string. + * \return Lenght of the string in bytes. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_strlen(const char* string); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Convert an numeric ascii string to integer value. + * + * + * \param void* string Pointer to the string. + * \return Integer value extracted from the string. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_atoi(const char* string); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Convert string to unsigned long integer. + * + * + * \param void* nptr Pointer to the string. + * \param char** endptr If not null, will be set to point to the next character after the number. + * \param int base Base defining the type of the numeric string. + * \return Unsigned integer value extracted from the string. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_strtoul(const char* nptr, char** endptr, int base); + + +////////////////////////////////////////////////////////////////////////////// +// sync API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Create a mutex instance. + * + * + * \param void* name Name string for the new mutex. + * \return Returns a handle to the mutex. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_mutex_create(const char* name); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get a handle to an already existing mutex. + * + * + * \param void* name Name string for the new mutex. + * \return Returns a handle to the mutex. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_mutex_open(const char* name); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Free the given mutex. + * + * + * \param oshandle_t mutexhandle Handle to the mutex. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_mutex_free(oshandle_t mutexhandle); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Lock the given mutex. + * + * + * \param oshandle_t mutexhandle Handle to the mutex. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_mutex_lock(oshandle_t mutexhandle); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Try to lock the given mutex, if already locked returns immediately. + * + * + * \param oshandle_t mutexhandle Handle to the mutex. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_mutex_locktry(oshandle_t mutexhandle); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Try to lock the given mutex by waiting for its release. Returns without locking if the + * mutex is already locked and cannot be acquired within the given period. + * + * + * \param oshandle_t mutexhandle Handle to the mutex. + * \param int millisecondstowait Time to wait for the mutex to be available. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_mutex_lockwait(oshandle_t mutexhandle, int millisecondstowait); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Unlock the given mutex. + * + * + * \param oshandle_t mutexhandle Handle to the mutex. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_mutex_unlock(oshandle_t mutexhandle); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Increments (increases by one) the value of the specified 32-bit variable as an atomic operation. + * + * + * \param int* ptr Pointer to the value to be incremented. + * \return Returns the new incremented value. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interlock_incr(int* ptr); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Decrements (decreases by one) the value of the specified 32-bit variable as an atomic operation. + * + * + * \param int* ptr Pointer to the value to be decremented. + * \return Returns the new decremented value. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interlock_decr(int* ptr); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Atomic replacement of a value. + * + * + * \param int* ptr Pointer to the value to be replaced. + * \param int value The new value. + * \return Returns the old value. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interlock_xchg(int* ptr, int value); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Perform an atomic compare-and-exchange operation on the specified values. Compares the two specified 32-bit values and exchanges +* with another 32-bit value based on the outcome of the comparison. + * + * + * \param int* ptr Pointer to the value to be replaced. + * \param int value The new value. + * \param int compvalue Value to be compared with. + * \return Returns the initial value of the first given parameter. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interlock_compxchg(int* ptr, int value, int compvalue); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Atomic addition of two 32-bit values. + * + * + * \param int* ptr Pointer to the target value. + * \param int value Value to be added to the target. + * \return Returns the initial value of the target. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interlock_xchgadd(int* ptr, int value); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Create an event semaphore. + * + * + * \param int a_manualReset Selection for performing reset manually (or by the system). + * \return Returns an handle to the created semaphore. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_event_create(int a_manualReset); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Destroy an event semaphore. + * + * + * \param oshandle_t a_event Handle to the semaphore. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_event_destroy(oshandle_t a_event); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Signal an event semaphore. + * + * + * \param oshandle_t a_event Handle to the semaphore. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_event_signal(oshandle_t a_event); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Reset an event semaphore. + * + * + * \param oshandle_t a_event Handle to the semaphore. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_event_reset(oshandle_t a_event); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Wait for an event semaphore to be freed and acquire it. + * + * + * \param oshandle_t a_event Handle to the semaphore. + * \param int a_milliSeconds Time to wait. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_event_wait(oshandle_t a_event, int a_milliSeconds); + + +////////////////////////////////////////////////////////////////////////////// +// interrupt handler API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Enable an interrupt with specified id. + * + * + * \param int interrupt Identification number for the interrupt. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interrupt_enable(int interrupt); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Disable an interrupt with specified id. + * + * + * \param int interrupt Identification number for the interrupt. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interrupt_disable(int interrupt); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Set the callback function for an interrupt. + * + * + * \param int interrupt Identification number for the interrupt. + * \param void* handler Pointer to the callback function. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interrupt_setcallback(int interrupt, void* handler); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Remove a callback function from an interrupt. + * + * + * \param int interrupt Identification number for the interrupt. + * \param void* handler Pointer to the callback function. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interrupt_clearcallback(int interrupt, void* handler); + + +////////////////////////////////////////////////////////////////////////////// +// thread and process API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocate an entry from the thread local storage table. + * + * + * \return Index of the reserved entry. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_tls_alloc(void); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Free an entry from the thread local storage table. + * + * + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_tls_free(unsigned int tlsindex); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Read the value of an entry in the thread local storage table. + * + * + * \param unsigned int tlsindex Index of the entry. + * \return Returns the value of the entry. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_tls_read(unsigned int tlsindex); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Write a value to an entry in the thread local storage table. + * + * + * \param unsigned int tlsindex Index of the entry. + * \param void* tlsvalue Value to be written. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_tls_write(unsigned int tlsindex, void* tlsvalue); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Put the thread to sleep for the given time period. + * + * + * \param unsigned int milliseconds Time in milliseconds. + *//*-------------------------------------------------------------------*/ +KOS_API void kos_sleep(unsigned int milliseconds); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get the id of the current process. + * + * + * \return Returns the process id. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_process_getid(void); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get the id of the current caller process. + * + * + * \return Returns the caller process id. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_callerprocess_getid(void); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get the id of the current thread. + * + * + * \return Returns the thread id. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_thread_getid(void); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Create a new thread. + * + * + * \param oshandle_t a_function Handle to the function to be executed in the thread. + * \param unsigned int* a_threadId Pointer to a value where to store the ID of the new thread. + * \return Returns an handle to the created thread. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_thread_create(oshandle_t a_function, unsigned int* a_threadId); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Destroy the given thread. + * + * + * \param oshandle_t a_task Handle to the thread to be destroyed. + *//*-------------------------------------------------------------------*/ +KOS_API void kos_thread_destroy( oshandle_t a_task ); + +////////////////////////////////////////////////////////////////////////////// +// timing API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get the current time as a timestamp. + * + * + * \return Returns the timestamp. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_timestamp(void); + + +////////////////////////////////////////////////////////////////////////////// +// libary API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Map the given library (not required an all OS'es). + * + * + * \param char* libraryname The name string of the lib. + * \return Returns a handle for the lib. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_lib_map(char* libraryname); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Unmap the given library. + * + * \param oshandle_t libhandle Handle to the lib. + * \return Returns an error code incase of an error. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_lib_unmap(oshandle_t libhandle); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get the address of a lib. + * + * \param oshandle_t libhandle Handle to the lib. + * \return Returns a pointer to the lib. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_lib_getaddr(oshandle_t libhandle, char* procname); + + +////////////////////////////////////////////////////////////////////////////// +// query API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get device system info. + * + * \param os_sysinfo_t* sysinfo Pointer to the destination sysinfo structure. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_get_sysinfo(os_sysinfo_t* sysinfo); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get system status info. + * + * \param os_stats_t* stats Pointer to the destination stats structure. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_get_stats(os_stats_t* stats); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block start + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_syncblock_start(void); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block end + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_syncblock_end(void); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block start with argument + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_syncblock_start_ex( mutexIndex_t a_index ); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block start with argument + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_syncblock_end_ex( mutexIndex_t a_index ); + +////////////////////////////////////////////////////////////////////////////// +// file API +////////////////////////////////////////////////////////////////////////////// + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Opens a file + * + * \param const char* filename Name of the file to open. + * \param const char* mode Mode used for file opening. See fopen. + * \return Returns file handle or NULL if error. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_fopen(const char* filename, const char* mode); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Writes to a file + * + * \param oshandle_t file Handle of the file to write to. + * \param const char* format Format string. See fprintf. + * \return Returns the number of bytes written + *//*-------------------------------------------------------------------*/ +KOS_API int kos_fprintf(oshandle_t file, const char* format, ...); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Closes a file + * + * \param oshandle_t file Handle of the file to close. + * \return Returns zero if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_fclose(oshandle_t file); + +#ifdef __SYMBIAN32__ +KOS_API void kos_create_dfc(void); +KOS_API void kos_signal_dfc(void); +KOS_API void kos_enter_critical_section(); +KOS_API void kos_leave_critical_section(); +#endif // __SYMBIAN32__ + +#ifdef __cplusplus +} +#endif // __cplusplus +#endif // __KOSAPI_H diff --git a/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c b/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c new file mode 100644 index 000000000000..4ead84ffe0dc --- /dev/null +++ b/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c @@ -0,0 +1,661 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "kos_libapi.h" + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +//#define KOS_STATS_ENABLE + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define KOS_MALLOC(s) kmalloc(s, GFP_KERNEL) +#define KOS_CALLOC(num, size) kcalloc(num, size, GFP_KERNEL) +#define KOS_REALLOC(p, s) krealloc(p, s, GFP_KERNEL) +#define KOS_FREE(p) kfree(p); p = 0 +#define KOS_DBGFLAGS_SET(flag) + +////////////////////////////////////////////////////////////////////////////// +// stats +////////////////////////////////////////////////////////////////////////////// +#ifdef KOS_STATS_ENABLE +os_stats_t kos_stats = {0, 0, 0, 0, 0, 0, 0, 0}; +#define KOS_STATS(x) x +#else +#define KOS_STATS(x) +#endif + +////////////////////////////////////////////////////////////////////////////// +// assert API +////////////////////////////////////////////////////////////////////////////// +KOS_API void +kos_assert_hook(const char* file, int line, int expression) +{ + if (expression) + { + return; + } + else + { + printk(KERN_ERR "Assertion failed at %s:%d!\n", file, line); + //BUG(); + } + + // put breakpoint here +} + + +////////////////////////////////////////////////////////////////////////////// +// heap API (per process) +////////////////////////////////////////////////////////////////////////////// +KOS_API void* +kos_malloc(int size) +{ + void* ptr = KOS_MALLOC(size); + + KOS_ASSERT(ptr); + KOS_STATS(kos_stats.heap_allocs++); + KOS_STATS(kos_stats.heap_alloc_bytes += size); + + return (ptr); +} + + +//---------------------------------------------------------------------------- + +KOS_API void* +kos_calloc(int num, int size) +{ + void* ptr = KOS_CALLOC(num, size); + + KOS_ASSERT(ptr); + KOS_STATS(kos_stats.heap_allocs++); + KOS_STATS(kos_stats.heap_alloc_bytes += (size * num)); + + return (ptr); +} + +//---------------------------------------------------------------------------- + +KOS_API void* +kos_realloc(void* ptr, int size) +{ + void* newptr; + + KOS_ASSERT(ptr); + newptr = KOS_REALLOC(ptr, size); + + KOS_ASSERT(newptr); + + return (newptr); +} + +//---------------------------------------------------------------------------- + +KOS_API void +kos_free(void* ptr) +{ + KOS_STATS(kos_stats.heap_frees++); + + KOS_FREE(ptr); +} + + +////////////////////////////////////////////////////////////////////////////// +// shared heap API (cross process) +////////////////////////////////////////////////////////////////////////////// +KOS_API void* +kos_shared_malloc(int size) +{ + void* ptr; + + ptr = NULL; // shared alloc + + KOS_ASSERT(ptr); + KOS_STATS(kos_stats.shared_heap_allocs++); + KOS_STATS(kos_stats.shared_heap_alloc_bytes += size); + + return (ptr); +} + +//---------------------------------------------------------------------------- + +KOS_API void* +kos_shared_calloc(int num, int size) +{ + void* ptr; + + ptr = NULL; // shared calloc + + KOS_ASSERT(ptr); + KOS_STATS(kos_stats.shared_heap_allocs++); + KOS_STATS(kos_stats.shared_heap_alloc_bytes += (size * num)); + return (ptr); +} + +//---------------------------------------------------------------------------- + +KOS_API void* +kos_shared_realloc(void* ptr, int size) +{ + void* newptr; + (void) ptr; // unreferenced formal parameter + (void) size; // unreferenced formal parameter + + newptr = NULL; // shared realloc + + KOS_ASSERT(newptr); + + return (newptr); +} + +//---------------------------------------------------------------------------- + +KOS_API void +kos_shared_free(void* ptr) +{ + (void) ptr; // unreferenced formal parameter + KOS_ASSERT(0); // not implemented + + KOS_STATS(kos_stats.shared_heap_frees++); + + // shared free +} + +////////////////////////////////////////////////////////////////////////////// +// memory access API +////////////////////////////////////////////////////////////////////////////// +KOS_API void* +kos_memcpy(void* dst, const void* src, int count) +{ + KOS_ASSERT(src); + KOS_ASSERT(dst); + return memcpy(dst, src, count); +} + +//---------------------------------------------------------------------------- + +KOS_API void* +kos_memset(void* dst, int value, int count) +{ + KOS_ASSERT(dst); + return memset(dst, value, count); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_memcmp(void* dst, void* src, int count) +{ + KOS_ASSERT(src); + KOS_ASSERT(dst); + return memcmp(dst, src, count); +} + +////////////////////////////////////////////////////////////////////////////// +// physical memory API +////////////////////////////////////////////////////////////////////////////// +KOS_API int +kos_alloc_physical(void** virt_addr, void** phys_addr, int pages) +{ + *virt_addr = dma_alloc_coherent(NULL, pages*PAGE_SIZE, (dma_addr_t*)*phys_addr, GFP_DMA | GFP_KERNEL); + return *virt_addr ? OS_SUCCESS : OS_FAILURE; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_free_physical(void* virt_addr, int pages) +{ + (void) virt_addr; // unreferenced formal parameter + (void) pages; // unreferenced formal parameter + + return (OS_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_map_physical(void** virt_addr, void** phys_addr, int pages) +{ + (void) virt_addr; // unreferenced formal parameter + (void) phys_addr; // unreferenced formal parameter + (void) pages; // unreferenced formal parameter + + return (OS_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_unmap_physical(void* virt_addr, int pages) +{ + (void) virt_addr; // unreferenced formal parameter + (void) pages; // unreferenced formal parameter + + return (OS_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KOS_API void +kos_memoryfence(void) +{ +} + +//---------------------------------------------------------------------------- + +KOS_API void +kos_enable_memoryleakcheck(void) +{ + // perform automatic leak checking at program exit + KOS_DBGFLAGS_SET(_CRTDBG_ALLOC_MEM_DF | _CRTDBG_LEAK_CHECK_DF); +} + +////////////////////////////////////////////////////////////////////////////// +// string API +////////////////////////////////////////////////////////////////////////////// + +KOS_API char* +kos_strcpy(char* strdestination, const char* strsource) +{ + KOS_ASSERT(strdestination); + KOS_ASSERT(strsource); + return strcpy(strdestination, strsource); +} + +//---------------------------------------------------------------------------- + +KOS_API char* +kos_strncpy(char* destination, const char* source, int length) +{ + KOS_ASSERT(destination); + KOS_ASSERT(source); + return strncpy(destination, source, length); +} + +//---------------------------------------------------------------------------- + +KOS_API char* +kos_strcat(char* strdestination, const char* strsource) +{ + KOS_ASSERT(strdestination); + KOS_ASSERT(strsource); + return strcat(strdestination, strsource); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_strcmp(const char* string1, const char* string2) +{ + KOS_ASSERT(string1); + KOS_ASSERT(string2); + return strcmp(string1, string2); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_strncmp(const char* string1, const char* string2, int length) +{ + KOS_ASSERT(string1); + KOS_ASSERT(string2); + return strncmp(string1, string2, length); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_strlen(const char* string) +{ + KOS_ASSERT(string); + return strlen(string); +} + +////////////////////////////////////////////////////////////////////////////// +// sync API +////////////////////////////////////////////////////////////////////////////// + +KOS_API oshandle_t +kos_mutex_create(const char *name) +{ + struct mutex *mutex = KOS_MALLOC(sizeof(struct mutex)); + if (!mutex) + return 0; + mutex_init(mutex); + return mutex; +} + +//---------------------------------------------------------------------------- + +KOS_API oshandle_t +kos_mutex_open(const char *name) +{ + // not implemented + return 0; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_mutex_free(oshandle_t mutexhandle) +{ + struct mutex *mutex = (struct mutex *)mutexhandle; + if (!mutex) + return OS_FAILURE; + KOS_FREE(mutex); + return OS_SUCCESS; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_mutex_lock(oshandle_t mutexhandle) +{ + struct mutex *mutex = (struct mutex *)mutexhandle; + if (!mutex) + return OS_FAILURE; + if (mutex_lock_interruptible(mutex) == -EINTR) + return OS_FAILURE; + return OS_SUCCESS; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_mutex_locktry(oshandle_t mutexhandle) +{ + struct mutex *mutex = (struct mutex *)mutexhandle; + if (!mutex) + return OS_FAILURE; + if (!mutex_trylock(mutex)) + return OS_FAILURE; + return OS_SUCCESS; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_mutex_unlock(oshandle_t mutexhandle) +{ + struct mutex *mutex = (struct mutex *)mutexhandle; + if (!mutex) + return OS_FAILURE; + KOS_ASSERT(mutex_is_locked(mutex)); + mutex_unlock(mutex); + return OS_SUCCESS; +} + +//---------------------------------------------------------------------------- + +KOS_API unsigned int +kos_process_getid(void) +{ + return current->tgid; +} + +//---------------------------------------------------------------------------- + +/* ------------------------------------------------------------------- *//* + * \brief Creates new event semaphore + * \param uint32 a_manualReset + * When this param is zero, system automatically resets the + * event state to nonsignaled after waiting thread has been + * released + * \return oshandle_t +*//* ------------------------------------------------------------------- */ +KOS_API oshandle_t +kos_event_create(int a_manualReset) +{ + struct completion *comp = KOS_MALLOC(sizeof(struct completion)); + + KOS_ASSERT(comp); + if(!comp) + { + return (oshandle_t)NULL; + } + + init_completion(comp); + + return (oshandle_t)comp; +} + +/* ------------------------------------------------------------------- *//* + * \brief Frees event semaphore + * \param oshandle_t a_event, event semaphore + * \return int +*//* ------------------------------------------------------------------- */ +KOS_API int +kos_event_destroy(oshandle_t a_event) +{ + struct completion *comp = (struct completion *)a_event; + + KOS_ASSERT(comp); +// KOS_ASSERT(completion_done(comp)); + + KOS_FREE(comp); + return (OS_SUCCESS); +} + +/* ------------------------------------------------------------------- *//* + * \brief Signals event semaphore + * \param oshandle_t a_event, event semaphore + * \return int +*//* ------------------------------------------------------------------- */ +KOS_API int +kos_event_signal(oshandle_t a_event) +{ + struct completion *comp = (struct completion *)a_event; + + KOS_ASSERT(comp); + complete_all(comp); // perhaps complete_all? + return (OS_SUCCESS); +} + +/* ------------------------------------------------------------------- *//* + * \brief Resets event semaphore state to nonsignaled + * \param oshandle_t a_event, event semaphore + * \return int +*//* ------------------------------------------------------------------- */ +KOS_API int +kos_event_reset(oshandle_t a_event) +{ + struct completion *comp = (struct completion *)a_event; + + KOS_ASSERT(comp); + INIT_COMPLETION(*comp); + return (OS_SUCCESS); +} + +/* ------------------------------------------------------------------- *//* + * \brief Waits event semaphore to be signaled + * \param oshandle_t a_event, event semaphore + * \return int +*//* ------------------------------------------------------------------- */ +KOS_API int +kos_event_wait(oshandle_t a_event, int a_milliSeconds) +{ + struct completion *comp = (struct completion *)a_event; + + KOS_ASSERT(comp); + if(a_milliSeconds == OS_INFINITE) + { + wait_for_completion_killable(comp); + } + else + { + // should interpret milliseconds really to jiffies? + if(!wait_for_completion_timeout(comp, msecs_to_jiffies(a_milliSeconds))) + { + return (OS_FAILURE); + } + } + return (OS_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KOS_API void +kos_sleep(unsigned int milliseconds) +{ + msleep(milliseconds); +} + +////////////////////////////////////////////////////////////////////////////// +// query API +////////////////////////////////////////////////////////////////////////////// + +static int +kos_get_endianness(void) +{ + int value; + char* ptr; + + value = 0x01FFFF00; + + ptr = (char*)&value; + + KOS_ASSERT((*ptr == 0x00) || (*ptr == 0x01)); + + return (int)*ptr; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_get_sysinfo(os_sysinfo_t* sysinfo) +{ + KOS_ASSERT(sysinfo); + if (!sysinfo) return (OS_FAILURE); + + sysinfo->cpu_mhz = 0; + sysinfo->cpu_type = 0; + sysinfo->cpu_version = 0; + sysinfo->os_type = 0; + sysinfo->os_version = 0; + sysinfo->sysmem_size = 0; + sysinfo->page_size = 0x1000; + sysinfo->max_path = PATH_MAX; +// sysinfo->tls_slots = TLS_MINIMUM_AVAILABLE - 1; + sysinfo->endianness = kos_get_endianness(); + + return (OS_SUCCESS); +} + +//---------------------------------------------------------------------------- + +#ifdef KOS_STATS_ENABLE +KOS_API int +kos_get_stats(os_stats_t* stats) +{ + kos_memcpy(stats, &kos_stats, sizeof(os_stats_t)); + return (OS_SUCCESS); +} +#else +KOS_API int +kos_get_stats(os_stats_t* stats) +{ + return (OS_FAILURE); +} +#endif // KOS_STATS + +/*-------------------------------------------------------------------*//*! + * \brief Sync block API + * Same mutex needed from different blocks of driver + *//*-------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block start + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ + +static struct mutex* syncblock_mutex = 0; + +KOS_API int kos_syncblock_start(void) +{ + int return_value; + + if(!syncblock_mutex) + { + syncblock_mutex = kos_mutex_create("syncblock"); + } + + if(syncblock_mutex) + { + return_value = kos_mutex_lock(syncblock_mutex); + } + else + { + return_value = -1; + } + + return return_value; +} +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block end + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_syncblock_end(void) +{ + int return_value; + + if(syncblock_mutex) + { + return_value = kos_mutex_unlock(syncblock_mutex); + } + else + { + return_value = -1; + } + + return return_value; +} + +KOS_API oshandle_t kos_thread_create(oshandle_t a_function, unsigned int* a_threadId) +{ + struct task_struct *task = kthread_run(a_function, 0, "kos_thread_%p", a_threadId); + *a_threadId = (unsigned int)task; + return (oshandle_t)task; +} + +KOS_API void kos_thread_destroy( oshandle_t a_task ) +{ + kthread_stop((struct task_struct *)a_task); +} diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c new file mode 100644 index 000000000000..8d452830cc08 --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c @@ -0,0 +1,579 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#include "gsl_hal.h" +#include "gsl_halconfig.h" +#include "gsl_linux_map.h" + +#include +#include +#include +#include + +#include +#include +#include +#include + +#define GSL_HAL_MEM1 0 +#define GSL_HAL_MEM2 1 +#define GSL_HAL_MEM3 2 + +/* #define GSL_HAL_DEBUG */ + +extern phys_addr_t gpu_2d_regbase; +extern int gpu_2d_regsize; +extern phys_addr_t gpu_3d_regbase; +extern int gpu_3d_regsize; +extern int gmem_size; +extern phys_addr_t gpu_reserved_mem; +extern int gpu_reserved_mem_size; +extern int gpu_2d_irq, gpu_3d_irq; + + +KGSLHAL_API int +kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]) +{ + /* allocate physically contiguous memory */ + + int i; + void *va; + + va = gsl_linux_map_alloc(virtaddr, numpages*PAGE_SIZE); + + if (!va) + return GSL_FAILURE_OUTOFMEM; + + for (i = 0; i < numpages; i++) { + scattergatterlist[i] = page_to_phys(vmalloc_to_page(va)); + va += PAGE_SIZE; + } + + return GSL_SUCCESS; +} + +/* --------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]) +{ + /* free physical memory */ + + gsl_linux_map_free(virtaddr); + + return GSL_SUCCESS; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_init(void) +{ + gsl_hal_t *hal; + unsigned long totalsize, mem1size; + unsigned int va, pa; + + if (gsl_driver.hal) { + return GSL_FAILURE_ALREADYINITIALIZED; + } + + gsl_driver.hal = (void *)kos_malloc(sizeof(gsl_hal_t)); + + if (!gsl_driver.hal) { + return GSL_FAILURE_OUTOFMEM; + } + + kos_memset(gsl_driver.hal, 0, sizeof(gsl_hal_t)); + + + /* overlay structure on hal memory */ + hal = (gsl_hal_t *) gsl_driver.hal; + + if (gpu_3d_regbase && gpu_3d_regsize && gpu_3d_irq) { + hal->has_z430 = 1; + } else { + hal->has_z430 = 0; + } + + if (gpu_2d_regbase && gpu_2d_regsize && gpu_2d_irq) { + hal->has_z160 = 1; + } else { + hal->has_z160 = 0; + } + + /* there is still some problem to enable mmu currently */ + gsl_driver.enable_mmu = 0; + + /* setup register space */ + if (hal->has_z430) { + hal->z430_regspace.mmio_phys_base = gpu_3d_regbase; + hal->z430_regspace.sizebytes = gpu_3d_regsize; + hal->z430_regspace.mmio_virt_base = (unsigned char *)ioremap(hal->z430_regspace.mmio_phys_base, hal->z430_regspace.sizebytes); + + if (hal->z430_regspace.mmio_virt_base == NULL) { + return GSL_FAILURE_SYSTEMERROR; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->z430_regspace.mmio_phys_base = 0x%p\n", __func__, (void *)hal->z430_regspace.mmio_phys_base); + printk(KERN_INFO "%s: hal->z430_regspace.mmio_virt_base = 0x%p\n", __func__, (void *)hal->z430_regspace.mmio_virt_base); + printk(KERN_INFO "%s: hal->z430_regspace.sizebytes = 0x%08x\n", __func__, hal->z430_regspace.sizebytes); +#endif + } + + if (hal->has_z160) { + hal->z160_regspace.mmio_phys_base = gpu_2d_regbase; + hal->z160_regspace.sizebytes = gpu_2d_regsize; + hal->z160_regspace.mmio_virt_base = (unsigned char *)ioremap(hal->z160_regspace.mmio_phys_base, hal->z160_regspace.sizebytes); + + if (hal->z160_regspace.mmio_virt_base == NULL) { + return GSL_FAILURE_SYSTEMERROR; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->z160_regspace.mmio_phys_base = 0x%p\n", __func__, (void *)hal->z160_regspace.mmio_phys_base); + printk(KERN_INFO "%s: hal->z160_regspace.mmio_virt_base = 0x%p\n", __func__, (void *)hal->z160_regspace.mmio_virt_base); + printk(KERN_INFO "%s: hal->z160_regspace.sizebytes = 0x%08x\n", __func__, hal->z160_regspace.sizebytes); +#endif + } + + if (gsl_driver.enable_mmu) { + totalsize = GSL_HAL_SHMEM_SIZE_EMEM2_MMU + GSL_HAL_SHMEM_SIZE_PHYS_MMU; + mem1size = GSL_HAL_SHMEM_SIZE_EMEM1_MMU; + if (gpu_reserved_mem && gpu_reserved_mem_size >= totalsize) { + pa = gpu_reserved_mem; + va = (unsigned int)ioremap(gpu_reserved_mem, totalsize); + } else { + va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL); + } + } else { + if (gpu_reserved_mem && gpu_reserved_mem_size >= SZ_8M) { + totalsize = gpu_reserved_mem_size; + pa = gpu_reserved_mem; + va = (unsigned int)ioremap(gpu_reserved_mem, gpu_reserved_mem_size); + } else { + gpu_reserved_mem = 0; + totalsize = GSL_HAL_SHMEM_SIZE_EMEM1_NOMMU + GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU + GSL_HAL_SHMEM_SIZE_PHYS_NOMMU; + va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL); + } + mem1size = totalsize - (GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU + GSL_HAL_SHMEM_SIZE_PHYS_NOMMU); + } + + if (va) { + kos_memset((void *)va, 0, totalsize); + + hal->memchunk.mmio_virt_base = (void *)va; + hal->memchunk.mmio_phys_base = pa; + hal->memchunk.sizebytes = totalsize; + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memchunk.mmio_phys_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_phys_base); + printk(KERN_INFO "%s: hal->memchunk.mmio_virt_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_virt_base); + printk(KERN_INFO "%s: hal->memchunk.sizebytes = 0x%08x\n", __func__, hal->memchunk.sizebytes); +#endif + + hal->memspace[GSL_HAL_MEM2].mmio_virt_base = (void *) va; + hal->memspace[GSL_HAL_MEM2].gpu_base = pa; + if (gsl_driver.enable_mmu) { + hal->memspace[GSL_HAL_MEM2].sizebytes = GSL_HAL_SHMEM_SIZE_EMEM2_MMU; + va += GSL_HAL_SHMEM_SIZE_EMEM2_MMU; + pa += GSL_HAL_SHMEM_SIZE_EMEM2_MMU; + } else { + hal->memspace[GSL_HAL_MEM2].sizebytes = GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU; + va += GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU; + pa += GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].gpu_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].mmio_virt_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM2].sizebytes); +#endif + + hal->memspace[GSL_HAL_MEM3].mmio_virt_base = (void *) va; + hal->memspace[GSL_HAL_MEM3].gpu_base = pa; + if (gsl_driver.enable_mmu) { + hal->memspace[GSL_HAL_MEM3].sizebytes = GSL_HAL_SHMEM_SIZE_PHYS_MMU; + va += GSL_HAL_SHMEM_SIZE_PHYS_MMU; + pa += GSL_HAL_SHMEM_SIZE_PHYS_MMU; + } else { + hal->memspace[GSL_HAL_MEM3].sizebytes = GSL_HAL_SHMEM_SIZE_PHYS_NOMMU; + va += GSL_HAL_SHMEM_SIZE_PHYS_NOMMU; + pa += GSL_HAL_SHMEM_SIZE_PHYS_NOMMU; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].gpu_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].mmio_virt_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM3].sizebytes); +#endif + + if (gsl_driver.enable_mmu) { + gsl_linux_map_init(); + hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *)GSL_LINUX_MAP_RANGE_START; + hal->memspace[GSL_HAL_MEM1].gpu_base = GSL_LINUX_MAP_RANGE_START; + hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size; + } else { + hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *) va; + hal->memspace[GSL_HAL_MEM1].gpu_base = pa; + hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].gpu_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].mmio_virt_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM1].sizebytes); +#endif + } else { + kgsl_hal_close(); + return GSL_FAILURE_SYSTEMERROR; + } + + return GSL_SUCCESS; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_close(void) +{ + gsl_hal_t *hal; + + if (gsl_driver.hal) { + /* overlay structure on hal memory */ + hal = (gsl_hal_t *) gsl_driver.hal; + + /* unmap registers */ + if (hal->has_z430 && hal->z430_regspace.mmio_virt_base) { + iounmap(hal->z430_regspace.mmio_virt_base); + } + + if (hal->has_z160 && hal->z160_regspace.mmio_virt_base) { + iounmap(hal->z160_regspace.mmio_virt_base); + } + + /* free physical block */ + if (hal->memchunk.mmio_virt_base && gpu_reserved_mem) { + iounmap(hal->memchunk.mmio_virt_base); + } else { + dma_free_coherent(0, hal->memchunk.sizebytes, hal->memchunk.mmio_virt_base, hal->memchunk.mmio_phys_base); + } + + if (gsl_driver.enable_mmu) { + gsl_linux_map_destroy(); + } + + /* release hal struct */ + kos_memset(hal, 0, sizeof(gsl_hal_t)); + kos_free(gsl_driver.hal); + gsl_driver.hal = NULL; + } + + return GSL_SUCCESS; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config) +{ + int status = GSL_FAILURE_DEVICEERROR; + gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; + + kos_memset(config, 0, sizeof(gsl_shmemconfig_t)); + + if (hal) { + config->numapertures = GSL_SHMEM_MAX_APERTURES; + + if (gsl_driver.enable_mmu) { + config->apertures[0].id = GSL_APERTURE_MMU; + } else { + config->apertures[0].id = GSL_APERTURE_EMEM; + } + config->apertures[0].channel = GSL_CHANNEL_1; + config->apertures[0].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM1].mmio_virt_base; + config->apertures[0].gpubase = hal->memspace[GSL_HAL_MEM1].gpu_base; + config->apertures[0].sizebytes = hal->memspace[GSL_HAL_MEM1].sizebytes; + + config->apertures[1].id = GSL_APERTURE_EMEM; + config->apertures[1].channel = GSL_CHANNEL_2; + config->apertures[1].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM2].mmio_virt_base; + config->apertures[1].gpubase = hal->memspace[GSL_HAL_MEM2].gpu_base; + config->apertures[1].sizebytes = hal->memspace[GSL_HAL_MEM2].sizebytes; + + config->apertures[2].id = GSL_APERTURE_PHYS; + config->apertures[2].channel = GSL_CHANNEL_1; + config->apertures[2].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM3].mmio_virt_base; + config->apertures[2].gpubase = hal->memspace[GSL_HAL_MEM3].gpu_base; + config->apertures[2].sizebytes = hal->memspace[GSL_HAL_MEM3].sizebytes; + + status = GSL_SUCCESS; + } + + return status; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config) +{ + int status = GSL_FAILURE_DEVICEERROR; + gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; + + kos_memset(config, 0, sizeof(gsl_devconfig_t)); + + if (hal) { + switch (device_id) { + case GSL_DEVICE_YAMATO: + { + if (hal->has_z430) { + mh_mmu_config_u mmu_config = {0}; + + config->gmemspace.gpu_base = 0; + config->gmemspace.mmio_virt_base = 0; + config->gmemspace.mmio_phys_base = 0; + if (gmem_size) { + config->gmemspace.sizebytes = gmem_size; + } else { + config->gmemspace.sizebytes = 0; + } + + config->regspace.gpu_base = 0; + config->regspace.mmio_virt_base = (unsigned char *)hal->z430_regspace.mmio_virt_base; + config->regspace.mmio_phys_base = (unsigned int) hal->z430_regspace.mmio_phys_base; + config->regspace.sizebytes = GSL_HAL_SIZE_REG_YDX; + + mmu_config.f.mmu_enable = 1; + + if (gsl_driver.enable_mmu) { + mmu_config.f.split_mode_enable = 0; + mmu_config.f.rb_w_clnt_behavior = 1; + mmu_config.f.cp_w_clnt_behavior = 1; + mmu_config.f.cp_r0_clnt_behavior = 1; + mmu_config.f.cp_r1_clnt_behavior = 1; + mmu_config.f.cp_r2_clnt_behavior = 1; + mmu_config.f.cp_r3_clnt_behavior = 1; + mmu_config.f.cp_r4_clnt_behavior = 1; + mmu_config.f.vgt_r0_clnt_behavior = 1; + mmu_config.f.vgt_r1_clnt_behavior = 1; + mmu_config.f.tc_r_clnt_behavior = 1; + mmu_config.f.pa_w_clnt_behavior = 1; + } + + config->mmu_config = mmu_config.val; + + if (gsl_driver.enable_mmu) { + config->va_base = hal->memspace[GSL_HAL_MEM1].gpu_base; + config->va_range = hal->memspace[GSL_HAL_MEM1].sizebytes; + } else { + config->va_base = 0x00000000; + config->va_range = 0x00000000; + } + + /* turn off memory protection unit by setting acceptable physical address range to include all pages */ + config->mpu_base = 0x00000000; /* hal->memchunk.mmio_virt_base; */ + config->mpu_range = 0xFFFFF000; /* hal->memchunk.sizebytes; */ + status = GSL_SUCCESS; + } + break; + } + + case GSL_DEVICE_G12: + { + mh_mmu_config_u mmu_config = {0}; + + config->regspace.gpu_base = 0; + config->regspace.mmio_virt_base = (unsigned char *)hal->z160_regspace.mmio_virt_base; + config->regspace.mmio_phys_base = (unsigned int) hal->z160_regspace.mmio_phys_base; + config->regspace.sizebytes = GSL_HAL_SIZE_REG_G12; + + mmu_config.f.mmu_enable = 1; + + if (gsl_driver.enable_mmu) { + config->mmu_config = 0x00555551; + config->va_base = hal->memspace[GSL_HAL_MEM1].gpu_base; + config->va_range = hal->memspace[GSL_HAL_MEM1].sizebytes; + } else { + config->mmu_config = mmu_config.val; + config->va_base = 0x00000000; + config->va_range = 0x00000000; + } + + config->mpu_base = 0x00000000; /* (unsigned int) hal->memchunk.mmio_virt_base; */ + config->mpu_range = 0xFFFFF000; /* hal->memchunk.sizebytes; */ + + status = GSL_SUCCESS; + break; + } + + default: + break; + } + } + + return status; +} + +/*---------------------------------------------------------------------------- + * kgsl_hal_getchipid + * + * The proper platform method, build from RBBM_PERIPHIDx and RBBM_PATCH_RELEASE + *---------------------------------------------------------------------------- + */ +KGSLHAL_API gsl_chipid_t +kgsl_hal_getchipid(gsl_deviceid_t device_id) +{ + gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; + gsl_device_t *device = &gsl_driver.device[device_id-1]; + gsl_chipid_t chipid = 0; + unsigned int coreid, majorid, minorid, patchid, revid; + + if (hal->has_z430 && (device_id == GSL_DEVICE_YAMATO)) { + device->ftbl.device_regread(device, mmRBBM_PERIPHID1, &coreid); + coreid &= 0xF; + + device->ftbl.device_regread(device, mmRBBM_PERIPHID2, &majorid); + majorid = (majorid >> 4) & 0xF; + + device->ftbl.device_regread(device, mmRBBM_PATCH_RELEASE, &revid); + + minorid = ((revid >> 0) & 0xFF); /* this is a 16bit field, but extremely unlikely it would ever get this high */ + + patchid = ((revid >> 16) & 0xFF); + + chipid = ((coreid << 24) | (majorid << 16) | (minorid << 8) | (patchid << 0)); + } + + return chipid; +} + +/* --------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value) +{ + gsl_device_t *device = &gsl_driver.device[device_id-1]; + struct clk *gpu_clk = NULL; + struct clk *garb_clk = NULL; + struct clk *emi_garb_clk = NULL; + + /* unreferenced formal parameters */ + (void) value; + + switch (device_id) { + case GSL_DEVICE_G12: + gpu_clk = clk_get(0, "gpu2d_clk"); + break; + case GSL_DEVICE_YAMATO: + gpu_clk = clk_get(0, "gpu3d_clk"); + garb_clk = clk_get(0, "garb_clk"); + emi_garb_clk = clk_get(0, "emi_garb_clk"); + break; + default: + return GSL_FAILURE_DEVICEERROR; + } + + if (!gpu_clk) { + return GSL_FAILURE_DEVICEERROR; + } + + switch (state) { + case GSL_PWRFLAGS_CLK_ON: + break; + case GSL_PWRFLAGS_POWER_ON: + clk_enable(gpu_clk); + if (garb_clk) { + clk_enable(garb_clk); + } + if (emi_garb_clk) { + clk_enable(emi_garb_clk); + } + kgsl_device_autogate_init(&gsl_driver.device[device_id-1]); + break; + case GSL_PWRFLAGS_CLK_OFF: + break; + case GSL_PWRFLAGS_POWER_OFF: + if (device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT) != GSL_SUCCESS) { + return GSL_FAILURE_DEVICEERROR; + } + kgsl_device_autogate_exit(&gsl_driver.device[device_id-1]); + clk_disable(gpu_clk); + if (garb_clk) { + clk_disable(garb_clk); + } + if (emi_garb_clk) { + clk_disable(emi_garb_clk); + } + break; + default: + break; + } + + return GSL_SUCCESS; +} + +KGSLHAL_API int kgsl_clock(gsl_deviceid_t dev, int enable) +{ + struct clk *gpu_clk = NULL; + struct clk *garb_clk = NULL; + struct clk *emi_garb_clk = NULL; + + switch (dev) { + case GSL_DEVICE_G12: + gpu_clk = clk_get(0, "gpu2d_clk"); + break; + case GSL_DEVICE_YAMATO: + gpu_clk = clk_get(0, "gpu3d_clk"); + garb_clk = clk_get(0, "garb_clk"); + emi_garb_clk = clk_get(0, "emi_garb_clk"); + break; + default: + printk(KERN_ERR "GPU device %d is invalid!\n", dev); + return GSL_FAILURE_DEVICEERROR; + } + + if (IS_ERR(gpu_clk)) { + printk(KERN_ERR "%s: GPU clock get failed!\n", __func__); + return GSL_FAILURE_DEVICEERROR; + } + + if (enable) { + clk_enable(gpu_clk); + if (garb_clk) { + clk_enable(garb_clk); + } + if (emi_garb_clk) { + clk_enable(emi_garb_clk); + } + } else { + clk_disable(gpu_clk); + if (garb_clk) { + clk_disable(garb_clk); + } + if (emi_garb_clk) { + clk_disable(emi_garb_clk); + } + } + + return GSL_SUCCESS; +} diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h new file mode 100644 index 000000000000..305b2ee9066d --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h @@ -0,0 +1,142 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_HWACCESS_LINUX_H +#define __GSL_HWACCESS_LINUX_H + +#ifdef _LINUX +#include "gsl_linux_map.h" +#endif + +#include +#include +#include + +OSINLINE void +kgsl_hwaccess_memread(void *dst, unsigned int gpubase, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace) +{ + if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) { + gsl_linux_map_read(dst, gpubase+gpuoffset, sizebytes, touserspace); + } else { + mb(); + dsb(); + if (touserspace) + { + if (copy_to_user(dst, (void *)(gpubase + gpuoffset), sizebytes)) + { + return; + } + } + else + { + kos_memcpy(dst, (void *) (gpubase + gpuoffset), sizebytes); + } + mb(); + dsb(); + } +} + +//---------------------------------------------------------------------------- + +OSINLINE void +kgsl_hwaccess_memwrite(unsigned int gpubase, unsigned int gpuoffset, void *src, unsigned int sizebytes, unsigned int fromuserspace) +{ + if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) { + gsl_linux_map_write(src, gpubase+gpuoffset, sizebytes, fromuserspace); + } else { + mb(); + dsb(); + if (fromuserspace) + { + if (copy_from_user((void *)(gpubase + gpuoffset), src, sizebytes)) + { + return; + } + } + else + { + kos_memcpy((void *)(gpubase + gpuoffset), src, sizebytes); + } + mb(); + dsb(); + } +} + +//---------------------------------------------------------------------------- + +OSINLINE void +kgsl_hwaccess_memset(unsigned int gpubase, unsigned int gpuoffset, unsigned int value, unsigned int sizebytes) +{ + if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) { + gsl_linux_map_set(gpuoffset+gpubase, value, sizebytes); + } else { + mb(); + dsb(); + kos_memset((void *)(gpubase + gpuoffset), value, sizebytes); + mb(); + dsb(); + } +} + +//---------------------------------------------------------------------------- + +OSINLINE void +kgsl_hwaccess_regread(gsl_deviceid_t device_id, unsigned int gpubase, unsigned int offsetwords, unsigned int *data) +{ + unsigned int *reg; + + // unreferenced formal parameter + (void) device_id; + + reg = (unsigned int *)(gpubase + (offsetwords << 2)); + + mb(); + dsb(); + *data = __raw_readl(reg); + mb(); + dsb(); +} + +//---------------------------------------------------------------------------- + +OSINLINE void +kgsl_hwaccess_regwrite(gsl_deviceid_t device_id, unsigned int gpubase, unsigned int offsetwords, unsigned int data) +{ + unsigned int *reg; + + // unreferenced formal parameter + (void) device_id; + + reg = (unsigned int *)(gpubase + (offsetwords << 2)); + mb(); + dsb(); + __raw_writel(data, reg); + mb(); + dsb(); +} +#endif // __GSL_HWACCESS_WINCE_MX51_H diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c new file mode 100644 index 000000000000..bef8684ad131 --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c @@ -0,0 +1,964 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl_types.h" +#include "gsl.h" +#include "gsl_buildconfig.h" +#include "gsl_halconfig.h" +#include "gsl_ioctl.h" +#include "gsl_kmod_cleanup.h" +#include "gsl_linux_map.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +int gpu_2d_irq, gpu_3d_irq; + +phys_addr_t gpu_2d_regbase; +int gpu_2d_regsize; +phys_addr_t gpu_3d_regbase; +int gpu_3d_regsize; +int gmem_size; +phys_addr_t gpu_reserved_mem; +int gpu_reserved_mem_size; +int z160_version; + +static ssize_t gsl_kmod_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr); +static ssize_t gsl_kmod_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr); +static int gsl_kmod_ioctl(struct inode *inode, struct file *fd, unsigned int cmd, unsigned long arg); +static int gsl_kmod_mmap(struct file *fd, struct vm_area_struct *vma); +static int gsl_kmod_fault(struct vm_area_struct *vma, struct vm_fault *vmf); +static int gsl_kmod_open(struct inode *inode, struct file *fd); +static int gsl_kmod_release(struct inode *inode, struct file *fd); +static irqreturn_t z160_irq_handler(int irq, void *dev_id); +static irqreturn_t z430_irq_handler(int irq, void *dev_id); + +static int gsl_kmod_major; +static struct class *gsl_kmod_class; +DEFINE_MUTEX(gsl_mutex); + +static const struct file_operations gsl_kmod_fops = +{ + .owner = THIS_MODULE, + .read = gsl_kmod_read, + .write = gsl_kmod_write, + .ioctl = gsl_kmod_ioctl, + .mmap = gsl_kmod_mmap, + .open = gsl_kmod_open, + .release = gsl_kmod_release +}; + +static struct vm_operations_struct gsl_kmod_vmops = +{ + .fault = gsl_kmod_fault, +}; + +static ssize_t gsl_kmod_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr) +{ + return 0; +} + +static ssize_t gsl_kmod_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr) +{ + return 0; +} + +static int gsl_kmod_ioctl(struct inode *inode, struct file *fd, unsigned int cmd, unsigned long arg) +{ + int kgslStatus = GSL_FAILURE; + + switch (cmd) { + case IOCTL_KGSL_DEVICE_START: + { + kgsl_device_start_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_start_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_start(param.device_id, param.flags); + break; + } + case IOCTL_KGSL_DEVICE_STOP: + { + kgsl_device_stop_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_stop_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_stop(param.device_id); + break; + } + case IOCTL_KGSL_DEVICE_IDLE: + { + kgsl_device_idle_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_idle_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_idle(param.device_id, param.timeout); + break; + } + case IOCTL_KGSL_DEVICE_GETPROPERTY: + { + kgsl_device_getproperty_t param; + void *tmp; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_getproperty_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + tmp = kmalloc(param.sizebytes, GFP_KERNEL); + if (!tmp) + { + printk(KERN_ERR "%s:kmalloc error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_getproperty(param.device_id, param.type, tmp, param.sizebytes); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.value, tmp, param.sizebytes)) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + kfree(tmp); + break; + } + } + else + { + printk(KERN_ERR "%s: kgsl_device_getproperty error\n", __func__); + } + kfree(tmp); + break; + } + case IOCTL_KGSL_DEVICE_SETPROPERTY: + { + kgsl_device_setproperty_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_setproperty_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_setproperty(param.device_id, param.type, param.value, param.sizebytes); + if (kgslStatus != GSL_SUCCESS) + { + printk(KERN_ERR "%s: kgsl_device_setproperty error\n", __func__); + } + break; + } + case IOCTL_KGSL_DEVICE_REGREAD: + { + kgsl_device_regread_t param; + unsigned int tmp; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_regread_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_regread(param.device_id, param.offsetwords, &tmp); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.value, &tmp, sizeof(unsigned int))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + } + break; + } + case IOCTL_KGSL_DEVICE_REGWRITE: + { + kgsl_device_regwrite_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_regwrite_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_regwrite(param.device_id, param.offsetwords, param.value); + break; + } + case IOCTL_KGSL_DEVICE_WAITIRQ: + { + kgsl_device_waitirq_t param; + unsigned int count; + + printk(KERN_ERR "IOCTL_KGSL_DEVICE_WAITIRQ obsoleted!\n"); +// kgslStatus = -ENOTTY; break; + + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_waitirq_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_waitirq(param.device_id, param.intr_id, &count, param.timeout); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.count, &count, sizeof(unsigned int))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + } + break; + } + case IOCTL_KGSL_CMDSTREAM_ISSUEIBCMDS: + { + kgsl_cmdstream_issueibcmds_t param; + gsl_timestamp_t tmp; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_cmdstream_issueibcmds_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_cmdstream_issueibcmds(param.device_id, param.drawctxt_index, param.ibaddr, param.sizedwords, &tmp, param.flags); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + } + break; + } + case IOCTL_KGSL_CMDSTREAM_READTIMESTAMP: + { + kgsl_cmdstream_readtimestamp_t param; + gsl_timestamp_t tmp; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_cmdstream_readtimestamp_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + tmp = kgsl_cmdstream_readtimestamp(param.device_id, param.type); + if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = GSL_SUCCESS; + break; + } + case IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP: + { + int err; + kgsl_cmdstream_freememontimestamp_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_cmdstream_freememontimestamp_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + err = del_memblock_from_allocated_list(fd, param.memdesc); + if(err) + { + /* tried to remove a block of memory that is not allocated! + * NOTE that -EINVAL is Linux kernel's error codes! + * the drivers error codes COULD mix up with kernel's. */ + kgslStatus = -EINVAL; + } + else + { + kgslStatus = kgsl_cmdstream_freememontimestamp(param.device_id, + param.memdesc, + param.timestamp, + param.type); + } + break; + } + case IOCTL_KGSL_CMDSTREAM_WAITTIMESTAMP: + { + kgsl_cmdstream_waittimestamp_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_cmdstream_waittimestamp_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_cmdstream_waittimestamp(param.device_id, param.timestamp, param.timeout); + break; + } + case IOCTL_KGSL_CMDWINDOW_WRITE: + { + kgsl_cmdwindow_write_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_cmdwindow_write_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_cmdwindow_write(param.device_id, param.target, param.addr, param.data); + break; + } + case IOCTL_KGSL_CONTEXT_CREATE: + { + kgsl_context_create_t param; + unsigned int tmp; + int tmpStatus; + + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_context_create_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_context_create(param.device_id, param.type, &tmp, param.flags); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.drawctxt_id, &tmp, sizeof(unsigned int))) + { + tmpStatus = kgsl_context_destroy(param.device_id, tmp); + /* is asserting ok? Basicly we should return the error from copy_to_user + * but will the user space interpret it correctly? Will the user space + * always check against GSL_SUCCESS or GSL_FAILURE as they are not the only + * return values. + */ + KOS_ASSERT(tmpStatus == GSL_SUCCESS); + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + else + { + add_device_context_to_array(fd, param.device_id, tmp); + } + } + break; + } + case IOCTL_KGSL_CONTEXT_DESTROY: + { + kgsl_context_destroy_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_context_destroy_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_context_destroy(param.device_id, param.drawctxt_id); + del_device_context_from_array(fd, param.device_id, param.drawctxt_id); + break; + } + case IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW: + { + kgsl_drawctxt_bind_gmem_shadow_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_drawctxt_bind_gmem_shadow_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_drawctxt_bind_gmem_shadow(param.device_id, param.drawctxt_id, param.gmem_rect, param.shadow_x, param.shadow_y, param.shadow_buffer, param.buffer_id); + break; + } + case IOCTL_KGSL_SHAREDMEM_ALLOC: + { + kgsl_sharedmem_alloc_t param; + gsl_memdesc_t tmp; + int tmpStatus; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_alloc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_alloc(param.device_id, param.flags, param.sizebytes, &tmp); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.memdesc, &tmp, sizeof(gsl_memdesc_t))) + { + tmpStatus = kgsl_sharedmem_free(&tmp); + KOS_ASSERT(tmpStatus == GSL_SUCCESS); + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + else + { + add_memblock_to_allocated_list(fd, &tmp); + } + } + break; + } + case IOCTL_KGSL_SHAREDMEM_FREE: + { + kgsl_sharedmem_free_t param; + gsl_memdesc_t tmp; + int err; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_free_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&tmp, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + err = del_memblock_from_allocated_list(fd, &tmp); + if(err) + { + printk(KERN_ERR "%s: tried to free memdesc that was not allocated!\n", __func__); + kgslStatus = err; + break; + } + kgslStatus = kgsl_sharedmem_free(&tmp); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.memdesc, &tmp, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + } + break; + } + case IOCTL_KGSL_SHAREDMEM_READ: + { + kgsl_sharedmem_read_t param; + gsl_memdesc_t memdesc; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_read_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_read(&memdesc, param.dst, param.offsetbytes, param.sizebytes, true); + if (kgslStatus != GSL_SUCCESS) + { + printk(KERN_ERR "%s: kgsl_sharedmem_read failed\n", __func__); + } + break; + } + case IOCTL_KGSL_SHAREDMEM_WRITE: + { + kgsl_sharedmem_write_t param; + gsl_memdesc_t memdesc; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_write_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_write(&memdesc, param.offsetbytes, param.src, param.sizebytes, true); + if (kgslStatus != GSL_SUCCESS) + { + printk(KERN_ERR "%s: kgsl_sharedmem_write failed\n", __func__); + } + + break; + } + case IOCTL_KGSL_SHAREDMEM_SET: + { + kgsl_sharedmem_set_t param; + gsl_memdesc_t memdesc; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_set_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_set(&memdesc, param.offsetbytes, param.value, param.sizebytes); + break; + } + case IOCTL_KGSL_SHAREDMEM_LARGESTFREEBLOCK: + { + kgsl_sharedmem_largestfreeblock_t param; + unsigned int largestfreeblock; + + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_largestfreeblock_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + largestfreeblock = kgsl_sharedmem_largestfreeblock(param.device_id, param.flags); + if (copy_to_user(param.largestfreeblock, &largestfreeblock, sizeof(unsigned int))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = GSL_SUCCESS; + break; + } + case IOCTL_KGSL_SHAREDMEM_CACHEOPERATION: + { + kgsl_sharedmem_cacheoperation_t param; + gsl_memdesc_t memdesc; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_cacheoperation_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_cacheoperation(&memdesc, param.offsetbytes, param.sizebytes, param.operation); + break; + } + case IOCTL_KGSL_SHAREDMEM_FROMHOSTPOINTER: + { + kgsl_sharedmem_fromhostpointer_t param; + gsl_memdesc_t memdesc; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_fromhostpointer_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_fromhostpointer(param.device_id, &memdesc, param.hostptr); + break; + } + case IOCTL_KGSL_ADD_TIMESTAMP: + { + kgsl_add_timestamp_t param; + gsl_timestamp_t tmp; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_add_timestamp_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + tmp = kgsl_add_timestamp(param.device_id, &tmp); + if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = GSL_SUCCESS; + break; + } + + case IOCTL_KGSL_DEVICE_CLOCK: + { + kgsl_device_clock_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_clock_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_clock(param.device, param.enable); + break; + } + default: + kgslStatus = -ENOTTY; + break; + } + + return kgslStatus; +} + +static int gsl_kmod_mmap(struct file *fd, struct vm_area_struct *vma) +{ + int status = 0; + unsigned long start = vma->vm_start; + unsigned long pfn = vma->vm_pgoff; + unsigned long size = vma->vm_end - vma->vm_start; + unsigned long prot = pgprot_writecombine(vma->vm_page_prot); + unsigned long addr = vma->vm_pgoff << PAGE_SHIFT; + void *va = NULL; + + if (gsl_driver.enable_mmu && (addr < GSL_LINUX_MAP_RANGE_END) && (addr >= GSL_LINUX_MAP_RANGE_START)) { + va = gsl_linux_map_find(addr); + while (size > 0) { + if (remap_pfn_range(vma, start, vmalloc_to_pfn(va), PAGE_SIZE, prot)) { + return -EAGAIN; + } + start += PAGE_SIZE; + va += PAGE_SIZE; + size -= PAGE_SIZE; + } + } else { + if (remap_pfn_range(vma, start, pfn, size, prot)) { + status = -EAGAIN; + } + } + + vma->vm_ops = &gsl_kmod_vmops; + + return status; +} + +static int gsl_kmod_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ + return VM_FAULT_SIGBUS; +} + +static int gsl_kmod_open(struct inode *inode, struct file *fd) +{ + gsl_flags_t flags = 0; + struct gsl_kmod_per_fd_data *datp; + int err = 0; + + if(mutex_lock_interruptible(&gsl_mutex)) + { + return -EINTR; + } + + if (kgsl_driver_entry(flags) != GSL_SUCCESS) + { + printk(KERN_INFO "%s: kgsl_driver_entry error\n", __func__); + err = -EIO; // TODO: not sure why did it fail? + } + else + { + /* allocate per file descriptor data structure */ + datp = (struct gsl_kmod_per_fd_data *)kzalloc( + sizeof(struct gsl_kmod_per_fd_data), + GFP_KERNEL); + if(datp) + { + init_created_contexts_array(datp->created_contexts_array[0]); + INIT_LIST_HEAD(&datp->allocated_blocks_head); + + fd->private_data = (void *)datp; + } + else + { + err = -ENOMEM; + } + } + + mutex_unlock(&gsl_mutex); + + return err; +} + +static int gsl_kmod_release(struct inode *inode, struct file *fd) +{ + struct gsl_kmod_per_fd_data *datp; + int err = 0; + + if(mutex_lock_interruptible(&gsl_mutex)) + { + return -EINTR; + } + + /* make sure contexts are destroyed */ + del_all_devices_contexts(fd); + + if (kgsl_driver_exit() != GSL_SUCCESS) + { + printk(KERN_INFO "%s: kgsl_driver_exit error\n", __func__); + err = -EIO; // TODO: find better error code + } + else + { + /* release per file descriptor data structure */ + datp = (struct gsl_kmod_per_fd_data *)fd->private_data; + del_all_memblocks_from_allocated_list(fd); + kfree(datp); + fd->private_data = 0; + } + + mutex_unlock(&gsl_mutex); + + return err; +} + +static struct class *gsl_kmod_class; + +static irqreturn_t z160_irq_handler(int irq, void *dev_id) +{ + kgsl_intr_isr(); + return IRQ_HANDLED; +} + +static irqreturn_t z430_irq_handler(int irq, void *dev_id) +{ + kgsl_intr_isr(); + return IRQ_HANDLED; +} + +static int gpu_probe(struct platform_device *pdev) +{ + int i; + struct resource *res; + struct device *dev; + + if (pdev->dev.platform_data) + z160_version = *((int *)(pdev->dev.platform_data)); + else + z160_version = 0; + + for(i = 0; i < 2; i++){ + res = platform_get_resource(pdev, IORESOURCE_IRQ, i); + if (!res) { + if (i == 0) { + printk(KERN_ERR "gpu: unable to get gpu irq\n"); + return -ENODEV; + } else { + break; + } + } + if(strcmp(res->name, "gpu_2d_irq") == 0){ + gpu_2d_irq = res->start; + }else if(strcmp(res->name, "gpu_3d_irq") == 0){ + gpu_3d_irq = res->start; + } + } + + for(i = 0; i < 4; i++){ + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!res) { + gpu_2d_regbase = 0; + gpu_2d_regsize = 0; + gpu_3d_regbase = 0; + gpu_2d_regsize = 0; + gmem_size = 0; + gpu_reserved_mem = 0; + gpu_reserved_mem_size = 0; + break; + }else{ + if(strcmp(res->name, "gpu_2d_registers") == 0){ + gpu_2d_regbase = res->start; + gpu_2d_regsize = res->end - res->start + 1; + }else if(strcmp(res->name, "gpu_3d_registers") == 0){ + gpu_3d_regbase = res->start; + gpu_3d_regsize = res->end - res->start + 1; + }else if(strcmp(res->name, "gpu_graphics_mem") == 0){ + gmem_size = res->end - res->start + 1; + }else if(strcmp(res->name, "gpu_reserved_mem") == 0){ + gpu_reserved_mem = res->start; + gpu_reserved_mem_size = res->end - res->start + 1; + } + } + } + + if (gpu_3d_irq > 0) + { + if (request_irq(gpu_3d_irq, z430_irq_handler, 0, "ydx", NULL) < 0) { + printk(KERN_ERR "%s: request_irq error\n", __func__); + gpu_3d_irq = 0; + goto request_irq_error; + } + } + + if (gpu_2d_irq > 0) + { + if (request_irq(gpu_2d_irq, z160_irq_handler, 0, "g12", NULL) < 0) { + printk(KERN_ERR "2D Acceleration Enabled, OpenVG Disabled!\n"); + gpu_2d_irq = 0; + } + } + + if (kgsl_driver_init() != GSL_SUCCESS) { + printk(KERN_ERR "%s: kgsl_driver_init error\n", __func__); + goto kgsl_driver_init_error; + } + + gsl_kmod_major = register_chrdev(0, "gsl_kmod", &gsl_kmod_fops); + gsl_kmod_vmops.fault = gsl_kmod_fault; + + if (gsl_kmod_major <= 0) + { + pr_err("%s: register_chrdev error\n", __func__); + goto register_chrdev_error; + } + + gsl_kmod_class = class_create(THIS_MODULE, "gsl_kmod"); + + if (IS_ERR(gsl_kmod_class)) + { + pr_err("%s: class_create error\n", __func__); + goto class_create_error; + } + + #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)) + dev = device_create(gsl_kmod_class, NULL, MKDEV(gsl_kmod_major, 0), "gsl_kmod"); + #else + dev = device_create(gsl_kmod_class, NULL, MKDEV(gsl_kmod_major, 0), NULL,"gsl_kmod"); + #endif + + if (!IS_ERR(dev)) + { + // gsl_kmod_data.device = dev; + return 0; + } + + pr_err("%s: device_create error\n", __func__); + +class_create_error: + class_destroy(gsl_kmod_class); + +register_chrdev_error: + unregister_chrdev(gsl_kmod_major, "gsl_kmod"); + +kgsl_driver_init_error: + kgsl_driver_close(); + if (gpu_2d_irq > 0) { + free_irq(gpu_2d_irq, NULL); + } + if (gpu_3d_irq > 0) { + free_irq(gpu_3d_irq, NULL); + } +request_irq_error: + return 0; // TODO: return proper error code +} + +static int gpu_remove(struct platform_device *pdev) +{ + device_destroy(gsl_kmod_class, MKDEV(gsl_kmod_major, 0)); + class_destroy(gsl_kmod_class); + unregister_chrdev(gsl_kmod_major, "gsl_kmod"); + + if (gpu_3d_irq) + { + free_irq(gpu_3d_irq, NULL); + } + + if (gpu_2d_irq) + { + free_irq(gpu_2d_irq, NULL); + } + + kgsl_driver_close(); + return 0; +} + +#ifdef CONFIG_PM +static int gpu_suspend(struct platform_device *pdev, pm_message_t state) +{ + int i; + gsl_powerprop_t power; + + power.flags = GSL_PWRFLAGS_POWER_OFF; + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + kgsl_device_setproperty( + (gsl_deviceid_t) (i+1), + GSL_PROP_DEVICE_POWER, + &power, + sizeof(gsl_powerprop_t)); + } + + return 0; +} + +static int gpu_resume(struct platform_device *pdev) +{ + int i; + gsl_powerprop_t power; + + power.flags = GSL_PWRFLAGS_POWER_ON; + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + kgsl_device_setproperty( + (gsl_deviceid_t) (i+1), + GSL_PROP_DEVICE_POWER, + &power, + sizeof(gsl_powerprop_t)); + } + + return 0; +} +#else +#define gpu_suspend NULL +#define gpu_resume NULL +#endif /* !CONFIG_PM */ + +/*! Driver definition + */ +static struct platform_driver gpu_driver = { + .driver = { + .name = "mxc_gpu", + }, + .probe = gpu_probe, + .remove = gpu_remove, + .suspend = gpu_suspend, + .resume = gpu_resume, +}; + +static int __init gsl_kmod_init(void) +{ + return platform_driver_register(&gpu_driver); +} + +static void __exit gsl_kmod_exit(void) +{ + platform_driver_unregister(&gpu_driver); +} + +module_init(gsl_kmod_init); +module_exit(gsl_kmod_exit); +MODULE_AUTHOR("Advanced Micro Devices"); +MODULE_DESCRIPTION("AMD graphics core driver for i.MX"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c new file mode 100644 index 000000000000..3685a5756baf --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c @@ -0,0 +1,269 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_kmod_cleanup.h" + +#include +#include + +/* + * Local helper functions to check and convert device/context id's (1 based) + * to index (0 based). + */ +static u32 device_id_to_device_index(gsl_deviceid_t device_id) +{ + KOS_ASSERT((GSL_DEVICE_ANY < device_id) && + (device_id <= GSL_DEVICE_MAX)); + return (u32)(device_id - 1); +} + +/* + * Local helper function to check and get pointer to per file descriptor data + */ +static struct gsl_kmod_per_fd_data *get_fd_private_data(struct file *fd) +{ + struct gsl_kmod_per_fd_data *datp; + + KOS_ASSERT(fd); + datp = (struct gsl_kmod_per_fd_data *)fd->private_data; + KOS_ASSERT(datp); + return datp; +} + +static s8 *find_first_entry_with(s8 *subarray, s8 context_id) +{ + s8 *entry = NULL; + int i; + +//printk(KERN_DEBUG "At %s, ctx_id = %d\n", __func__, context_id); + + KOS_ASSERT(context_id >= EMPTY_ENTRY); + KOS_ASSERT(context_id <= GSL_CONTEXT_MAX); // TODO: check the bound. + + for(i = 0; i < GSL_CONTEXT_MAX; i++) // TODO: check the bound. + { + if(subarray[i] == (s8)context_id) + { + entry = &subarray[i]; + break; + } + } + + return entry; +} + + +/* + * Add a memdesc into a list of allocated memory blocks for this file + * descriptor. The list is build in such a way that it implements FIFO (i.e. + * list). Traces of tiger, tiger_ri and VG11 CTs should be analysed to make + * informed choice. + * + * NOTE! gsl_memdesc_ts are COPIED so user space should NOT change them. + */ +int add_memblock_to_allocated_list(struct file *fd, + gsl_memdesc_t *allocated_block) +{ + int err = 0; + struct gsl_kmod_per_fd_data *datp; + struct gsl_kmod_alloc_list *lisp; + struct list_head *head; + + KOS_ASSERT(allocated_block); + + datp = get_fd_private_data(fd); + + head = &datp->allocated_blocks_head; + KOS_ASSERT(head); + + /* allocate and put new entry in the list of allocated memory descriptors */ + lisp = (struct gsl_kmod_alloc_list *)kzalloc(sizeof(struct gsl_kmod_alloc_list), GFP_KERNEL); + if(lisp) + { + INIT_LIST_HEAD(&lisp->node); + + /* builds FIFO (list_add() would build LIFO) */ + list_add_tail(&lisp->node, head); + memcpy(&lisp->allocated_block, allocated_block, sizeof(gsl_memdesc_t)); + lisp->allocation_number = datp->maximum_number_of_blocks; +// printk(KERN_DEBUG "List entry #%u allocated\n", lisp->allocation_number); + + datp->maximum_number_of_blocks++; + datp->number_of_allocated_blocks++; + + err = 0; + } + else + { + printk(KERN_ERR "%s: Could not allocate new list element\n", __func__); + err = -ENOMEM; + } + + return err; +} + +/* Delete a previously allocated memdesc from a list of allocated memory blocks */ +int del_memblock_from_allocated_list(struct file *fd, + gsl_memdesc_t *freed_block) +{ + struct gsl_kmod_per_fd_data *datp; + struct gsl_kmod_alloc_list *cursor, *next; + struct list_head *head; +// int is_different; + + KOS_ASSERT(freed_block); + + datp = get_fd_private_data(fd); + + head = &datp->allocated_blocks_head; + KOS_ASSERT(head); + + KOS_ASSERT(datp->number_of_allocated_blocks > 0); + + if(!list_empty(head)) + { + list_for_each_entry_safe(cursor, next, head, node) + { + if(cursor->allocated_block.gpuaddr == freed_block->gpuaddr) + { +// is_different = memcmp(&cursor->allocated_block, freed_block, sizeof(gsl_memdesc_t)); +// KOS_ASSERT(!is_different); + + list_del(&cursor->node); +// printk(KERN_DEBUG "List entry #%u freed\n", cursor->allocation_number); + kfree(cursor); + datp->number_of_allocated_blocks--; + return 0; + } + } + } + return -EINVAL; // tried to free entry not existing or from empty list. +} + +/* Delete all previously allocated memdescs from a list */ +int del_all_memblocks_from_allocated_list(struct file *fd) +{ + struct gsl_kmod_per_fd_data *datp; + struct gsl_kmod_alloc_list *cursor, *next; + struct list_head *head; + + datp = get_fd_private_data(fd); + + head = &datp->allocated_blocks_head; + KOS_ASSERT(head); + + if(!list_empty(head)) + { + printk(KERN_INFO "Not all allocated memory blocks were freed. Doing it now.\n"); + list_for_each_entry_safe(cursor, next, head, node) + { + printk(KERN_INFO "Freeing list entry #%u, gpuaddr=%x\n", (u32)cursor->allocation_number, cursor->allocated_block.gpuaddr); + kgsl_sharedmem_free(&cursor->allocated_block); + list_del(&cursor->node); + kfree(cursor); + } + } + + KOS_ASSERT(list_empty(head)); + datp->number_of_allocated_blocks = 0; + + return 0; +} + +void init_created_contexts_array(s8 *array) +{ + memset((void*)array, EMPTY_ENTRY, GSL_DEVICE_MAX * GSL_CONTEXT_MAX); +} + + +void add_device_context_to_array(struct file *fd, + gsl_deviceid_t device_id, + unsigned int context_id) +{ + struct gsl_kmod_per_fd_data *datp; + s8 *entry; + s8 *subarray; + u32 device_index = device_id_to_device_index(device_id); + + datp = get_fd_private_data(fd); + + subarray = datp->created_contexts_array[device_index]; + entry = find_first_entry_with(subarray, EMPTY_ENTRY); + + KOS_ASSERT(entry); + KOS_ASSERT((datp->created_contexts_array[device_index] <= entry) && + (entry < datp->created_contexts_array[device_index] + GSL_CONTEXT_MAX)); + KOS_ASSERT(context_id < 127); + *entry = (s8)context_id; +} + +void del_device_context_from_array(struct file *fd, + gsl_deviceid_t device_id, + unsigned int context_id) +{ + struct gsl_kmod_per_fd_data *datp; + u32 device_index = device_id_to_device_index(device_id); + s8 *entry; + s8 *subarray; + + datp = get_fd_private_data(fd); + + KOS_ASSERT(context_id < 127); + subarray = &(datp->created_contexts_array[device_index][0]); + entry = find_first_entry_with(subarray, context_id); + KOS_ASSERT(entry); + KOS_ASSERT((datp->created_contexts_array[device_index] <= entry) && + (entry < datp->created_contexts_array[device_index] + GSL_CONTEXT_MAX)); + *entry = EMPTY_ENTRY; +} + +void del_all_devices_contexts(struct file *fd) +{ + struct gsl_kmod_per_fd_data *datp; + gsl_deviceid_t id; + u32 device_index; + u32 ctx_array_index; + s8 ctx; + int err; + + datp = get_fd_private_data(fd); + + /* device_id is 1 based */ + for(id = GSL_DEVICE_ANY + 1; id <= GSL_DEVICE_MAX; id++) + { + device_index = device_id_to_device_index(id); + for(ctx_array_index = 0; ctx_array_index < GSL_CONTEXT_MAX; ctx_array_index++) + { + ctx = datp->created_contexts_array[device_index][ctx_array_index]; + if(ctx != EMPTY_ENTRY) + { + err = kgsl_context_destroy(id, ctx); + if(err != GSL_SUCCESS) + { + printk(KERN_ERR "%s: could not destroy context %d on device id = %u\n", __func__, ctx, id); + } + else + { + printk(KERN_DEBUG "%s: Destroyed context %d on device id = %u\n", __func__, ctx, id); + } + } + } + } +} + diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h new file mode 100644 index 000000000000..475ee3be2e50 --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h @@ -0,0 +1,90 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_KMOD_CLEANUP_H +#define __GSL_KMOD_CLEANUP_H +#include "gsl_types.h" + +#include +#include +#include +#include + +#if (GSL_CONTEXT_MAX > 127) + #error created_contexts_array supports context numbers only 127 or less. +#endif + +static const s8 EMPTY_ENTRY = -1; + +/* A structure to make list of allocated memory blocks. List per fd. */ +/* should probably be allocated from slab cache to minimise fragmentation */ +struct gsl_kmod_alloc_list +{ + struct list_head node; + gsl_memdesc_t allocated_block; + u32 allocation_number; +}; + +/* A structure to hold abovementioned list of blocks. Contain per fd data. */ +struct gsl_kmod_per_fd_data +{ + struct list_head allocated_blocks_head; // list head + u32 maximum_number_of_blocks; + u32 number_of_allocated_blocks; + s8 created_contexts_array[GSL_DEVICE_MAX][GSL_CONTEXT_MAX]; +}; + + +/* + * prototypes + */ + +/* allocated memory block tracking */ +int add_memblock_to_allocated_list(struct file *fd, + gsl_memdesc_t *allocated_block); + +int del_memblock_from_allocated_list(struct file *fd, + gsl_memdesc_t *freed_block); + +int del_all_memblocks_from_allocated_list(struct file *fd); + +/* created contexts tracking */ +void init_created_contexts_array(s8 *array); + +void add_device_context_to_array(struct file *fd, + gsl_deviceid_t device_id, + unsigned int context_id); + +void del_device_context_from_array(struct file *fd, + gsl_deviceid_t device_id, + unsigned int context_id); + +void del_all_devices_contexts(struct file *fd); + +#endif // __GSL_KMOD_CLEANUP_H + diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c new file mode 100644 index 000000000000..7fee7b814411 --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c @@ -0,0 +1,221 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "gsl_linux_map.h" + +struct gsl_linux_map +{ + struct list_head list; + unsigned int gpu_addr; + void *kernel_virtual_addr; + unsigned int size; +}; + +static LIST_HEAD(gsl_linux_map_list); +static DEFINE_MUTEX(gsl_linux_map_mutex); + +int gsl_linux_map_init() +{ + mutex_lock(&gsl_linux_map_mutex); + INIT_LIST_HEAD(&gsl_linux_map_list); + mutex_unlock(&gsl_linux_map_mutex); + + return 0; +} + +void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size) +{ + struct gsl_linux_map * map; + struct list_head *p; + void *va; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr == gpu_addr){ + mutex_unlock(&gsl_linux_map_mutex); + return map->kernel_virtual_addr; + } + } + + va = __vmalloc(size, GFP_KERNEL, pgprot_noncached(pgprot_kernel)); + if(va == NULL){ + mutex_unlock(&gsl_linux_map_mutex); + return NULL; + } + + map = (struct gsl_linux_map *)kmalloc(sizeof(*map), GFP_KERNEL); + map->gpu_addr = gpu_addr; + map->kernel_virtual_addr = va; + map->size = size; + + INIT_LIST_HEAD(&map->list); + list_add_tail(&map->list, &gsl_linux_map_list); + + mutex_unlock(&gsl_linux_map_mutex); + return va; +} + +void gsl_linux_map_free(unsigned int gpu_addr) +{ + int found = 0; + struct gsl_linux_map * map; + struct list_head *p; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr == gpu_addr){ + found = 1; + break; + } + } + + if(found){ + vfree(map->kernel_virtual_addr); + list_del(&map->list); + kfree(map); + } + + mutex_unlock(&gsl_linux_map_mutex); +} + +void *gsl_linux_map_find(unsigned int gpu_addr) +{ + struct gsl_linux_map * map; + struct list_head *p; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr == gpu_addr){ + mutex_unlock(&gsl_linux_map_mutex); + return map->kernel_virtual_addr; + } + } + + mutex_unlock(&gsl_linux_map_mutex); + return NULL; +} + +void *gsl_linux_map_read(void *dst, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace) +{ + struct gsl_linux_map * map; + struct list_head *p; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr <= gpuoffset && + (map->gpu_addr + map->size) > gpuoffset){ + void *src = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr); + mutex_unlock(&gsl_linux_map_mutex); + if (touserspace) + { + return (void *)copy_to_user(dst, map->kernel_virtual_addr + gpuoffset - map->gpu_addr, sizebytes); + } + else + { + return memcpy(dst, src, sizebytes); + } + } + } + + mutex_unlock(&gsl_linux_map_mutex); + return NULL; +} + +void *gsl_linux_map_write(void *src, unsigned int gpuoffset, unsigned int sizebytes, unsigned int fromuserspace) +{ + struct gsl_linux_map * map; + struct list_head *p; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr <= gpuoffset && + (map->gpu_addr + map->size) > gpuoffset){ + void *dst = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr); + mutex_unlock(&gsl_linux_map_mutex); + if (fromuserspace) + { + return (void *)copy_from_user(map->kernel_virtual_addr + gpuoffset - map->gpu_addr, src, sizebytes); + } + else + { + return memcpy(dst, src, sizebytes); + } + } + } + + mutex_unlock(&gsl_linux_map_mutex); + return NULL; +} + +void *gsl_linux_map_set(unsigned int gpuoffset, unsigned int value, unsigned int sizebytes) +{ + struct gsl_linux_map * map; + struct list_head *p; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr <= gpuoffset && + (map->gpu_addr + map->size) > gpuoffset){ + void *ptr = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr); + mutex_unlock(&gsl_linux_map_mutex); + return memset(ptr, value, sizebytes); + } + } + + mutex_unlock(&gsl_linux_map_mutex); + return NULL; +} + +int gsl_linux_map_destroy() +{ + struct gsl_linux_map * map; + struct list_head *p, *tmp; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each_safe(p, tmp, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + vfree(map->kernel_virtual_addr); + list_del(&map->list); + kfree(map); + } + + INIT_LIST_HEAD(&gsl_linux_map_list); + + mutex_unlock(&gsl_linux_map_mutex); + return 0; +} diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h new file mode 100644 index 000000000000..ebbe94a75e10 --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h @@ -0,0 +1,46 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_LINUX_MAP_H__ +#define __GSL_LINUX_MAP_H__ + +#include "gsl_halconfig.h" + +#define GSL_LINUX_MAP_RANGE_START (1024*1024) +#define GSL_LINUX_MAP_RANGE_END (GSL_LINUX_MAP_RANGE_START+GSL_HAL_SHMEM_SIZE_EMEM1_MMU) + +int gsl_linux_map_init(void); +void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size); +void gsl_linux_map_free(unsigned int gpu_addr); +void *gsl_linux_map_find(unsigned int gpu_addr); +void *gsl_linux_map_read(void *dst, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace); +void *gsl_linux_map_write(void *src, unsigned int gpuoffset, unsigned int sizebytes, unsigned int fromuserspace); +void *gsl_linux_map_set(unsigned int gpuoffset, unsigned int value, unsigned int sizebytes); +int gsl_linux_map_destroy(void); + +#endif diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/misc.c b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c new file mode 100644 index 000000000000..a356f334b187 --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include + +#include +#include +#include + +typedef struct _gsl_autogate_t { + struct timer_list timer; + spinlock_t lock; + int active; + int timeout; + gsl_device_t *dev; +} gsl_autogate_t; + + +#define KGSL_DEVICE_IDLE_TIMEOUT 5000 /* unit ms */ + +int kgsl_device_active(gsl_device_t *dev) +{ + unsigned long flags; + gsl_autogate_t *autogate = dev->autogate; + if (!autogate) { + printk(KERN_ERR "%s: autogate has exited!\n", __func__); + return 0; + } +// printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, dev->id, autogate->active); + + spin_lock_irqsave(&autogate->lock, flags); + if (!autogate->active) + kgsl_clock(autogate->dev->id, 1); + autogate->active = 1; + mod_timer(&autogate->timer, jiffies + msecs_to_jiffies(autogate->timeout)); + spin_unlock_irqrestore(&autogate->lock, flags); + return 0; +} + +static void kgsl_device_inactive(unsigned long data) +{ + gsl_autogate_t *autogate = (gsl_autogate_t *)data; + unsigned long flags; + +// printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, autogate->dev->id, autogate->active); + del_timer(&autogate->timer); + spin_lock_irqsave(&autogate->lock, flags); + WARN(!autogate->active, "GPU Device %d is already inactive\n", autogate->dev->id); + autogate->active = 0; + /* idle check may sleep, so don't use it */ +// if (autogate->dev->ftbl.device_idle) +// autogate->dev->ftbl.device_idle(autogate->dev, GSL_TIMEOUT_DEFAULT); + kgsl_clock(autogate->dev->id, 0); + spin_unlock_irqrestore(&autogate->lock, flags); +} + +int kgsl_device_clock(gsl_deviceid_t id, int enable) +{ + int ret = GSL_SUCCESS; + gsl_device_t *device; + + device = &gsl_driver.device[id-1]; // device_id is 1 based + if (device->flags & GSL_FLAGS_INITIALIZED) { + if (enable) + kgsl_device_active(device); + else + kgsl_device_inactive((unsigned long)device); + } else { + printk(KERN_ERR "%s: Dev %d clock is already off!\n", __func__, id); + ret = GSL_FAILURE; + } + + return ret; +} + +int kgsl_device_autogate_init(gsl_device_t *dev) +{ + gsl_autogate_t *autogate; + +// printk(KERN_ERR "%s:%d id %d\n", __func__, __LINE__, dev->id); + autogate = kmalloc(sizeof(gsl_autogate_t), GFP_KERNEL); + if (!autogate) { + printk(KERN_ERR "%s: out of memory!\n", __func__); + return -ENOMEM; + } + autogate->dev = dev; + autogate->active = 1; + spin_lock_init(&autogate->lock); + autogate->timeout = KGSL_DEVICE_IDLE_TIMEOUT; + init_timer(&autogate->timer); + autogate->timer.expires = jiffies + msecs_to_jiffies(autogate->timeout); + autogate->timer.function = kgsl_device_inactive; + autogate->timer.data = (unsigned long)autogate; + add_timer(&autogate->timer); + dev->autogate = autogate; + return 0; +} + +void kgsl_device_autogate_exit(gsl_device_t *dev) +{ + gsl_autogate_t *autogate = dev->autogate; + +// printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, dev->id, autogate->active); + if (autogate->active) + del_timer(&autogate->timer); + else + kgsl_clock(autogate->dev->id, 1); + + kfree(autogate); + dev->autogate = NULL; + +} diff --git a/drivers/net/fec_switch.c b/drivers/net/fec_switch.c new file mode 100644 index 000000000000..0485349dcd76 --- /dev/null +++ b/drivers/net/fec_switch.c @@ -0,0 +1,4255 @@ +/* + * L2 switch Controller (Etheren switch) driver for Mx28. + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Shrek Wu (B16972@freescale.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "fec_switch.h" + +#define SWITCH_MAX_PORTS 1 + +#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS) +#include +#define FEC_ALIGNMENT 0xf +#else +#define FEC_ALIGNMENT 0x3 +#endif + +/* The number of Tx and Rx buffers. These are allocated from the page + * pool. The code may assume these are power of two, so it it best + * to keep them that size. + * We don't need to allocate pages for the transmitter. We just use + * the skbuffer directly. + */ +#define FEC_ENET_RX_PAGES 8 +#define FEC_ENET_RX_FRSIZE 2048 +#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) +#define FEC_ENET_TX_FRSIZE 2048 +#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) +#define TX_RING_SIZE 16 /* Must be power of two */ +#define TX_RING_MOD_MASK 15 /* for this to work */ + +#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) +#error "FEC: descriptor ring size constants too large" +#endif + +/* Interrupt events/masks */ +#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ +#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ +#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ +#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ +#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ +#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ +#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ +#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ +#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ +#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ + +/* FEC MII MMFR bits definition */ +#define FEC_MMFR_ST (1 << 30) +#define FEC_MMFR_OP_READ (2 << 28) +#define FEC_MMFR_OP_WRITE (1 << 28) +#define FEC_MMFR_PA(v) ((v & 0x1f) << 23) +#define FEC_MMFR_RA(v) ((v & 0x1f) << 18) +#define FEC_MMFR_TA (2 << 16) +#define FEC_MMFR_DATA(v) (v & 0xffff) + +#ifdef FEC_PHY +static struct phy_device *g_phy_dev; +static struct mii_bus *fec_mii_bus; +#endif + +static int switch_enet_open(struct net_device *dev); +static int switch_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); +static irqreturn_t switch_enet_interrupt(int irq, void *dev_id); +static void switch_enet_tx(struct net_device *dev); +static void switch_enet_rx(struct net_device *dev); +static int switch_enet_close(struct net_device *dev); +static void set_multicast_list(struct net_device *dev); +static void switch_restart(struct net_device *dev, int duplex); +static void switch_stop(struct net_device *dev); + +#define NMII 20 + +/* Make MII read/write commands for the FEC */ +#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) +#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ + (VAL & 0xffff)) + +/* Transmitter timeout */ +#define TX_TIMEOUT (2*HZ) +#define FEC_MII_TIMEOUT 10 + +#ifdef CONFIG_ARCH_MXS +static void *swap_buffer(void *bufaddr, int len) +{ + int i; + unsigned int *buf = bufaddr; + + for (i = 0; i < (len + 3) / 4; i++, buf++) + *buf = __swab32(*buf); + + return bufaddr; +} +#endif + +/*last read entry from learning interface*/ +struct eswPortInfo g_info; + +#ifdef USE_DEFAULT_SWITCH_PORT0_MAC +static unsigned char switch_mac_default[] = { + 0x00, 0x08, 0x02, 0x6B, 0xA3, 0x1A, +}; +#else +static unsigned char switch_mac_default[ETH_ALEN]; +#endif + +static void switch_request_intrs(struct net_device *dev, + irqreturn_t switch_net_irq_handler(int irq, void *private), + void *irq_privatedata) +{ + struct switch_enet_private *fep; + + fep = netdev_priv(dev); + + /* Setup interrupt handlers */ + if (request_irq(dev->irq, + switch_net_irq_handler, IRQF_DISABLED, + "mxs-l2switch", irq_privatedata) != 0) + printk(KERN_ERR "FEC: Could not alloc %s IRQ(%d)!\n", + dev->name, dev->irq); +} + +static void switch_set_mii(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct switch_t *fecp; + + fecp = (struct switch_t *)fep->hwp; + + writel(MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE | + MCF_FEC_RCR_MAX_FL(1522), + fep->enet_addr + MCF_FEC_RCR0); + writel(MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE | + MCF_FEC_RCR_MAX_FL(1522), + fep->enet_addr + MCF_FEC_RCR1); + /* TCR */ + writel(MCF_FEC_TCR_FDEN, fep->enet_addr + MCF_FEC_TCR0); + writel(MCF_FEC_TCR_FDEN, fep->enet_addr + MCF_FEC_TCR1); + + /* ECR */ +#ifdef L2SWITCH_ENHANCED_BUFFER + writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588, + fep->enet_addr + MCF_FEC_ECR0); + writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588, + fep->enet_addr + MCF_FEC_ECR1); +#else /*legac buffer*/ + writel(MCF_FEC_ECR_ETHER_EN, fep->enet_addr + MCF_FEC_ECR0); + writel(MCF_FEC_ECR_ETHER_EN, fep->enet_addr + MCF_FEC_ECR1); +#endif + writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR0); + writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR1); + + /* + * Set MII speed to 2.5 MHz + */ + writel(DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1, + fep->enet_addr + MCF_FEC_MSCR0); + writel(DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1, + fep->enet_addr + MCF_FEC_MSCR1); + +#ifdef CONFIG_ARCH_MXS + /* Can't get phy(8720) ID when set to 2.5M on MX28, lower it*/ + fep->phy_speed = readl(fep->enet_addr + MCF_FEC_MSCR0) << 2; + writel(fep->phy_speed, fep->enet_addr + MCF_FEC_MSCR0); + writel(fep->phy_speed, fep->enet_addr + MCF_FEC_MSCR1); +#endif + +} + +static void switch_get_mac(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + unsigned char *iap, tmpaddr[ETH_ALEN]; + static int index; +#ifdef CONFIG_M5272 + if (FEC_FLASHMAC) { + /* + * Get MAC address from FLASH. + * If it is all 1's or 0's, use the default. + */ + iap = (unsigned char *)FEC_FLASHMAC; + if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && + (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) + iap = switch_mac_default; + if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && + (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) + iap = switch_mac_default; + } +#else + if (is_valid_ether_addr(switch_mac_default)) + iap = switch_mac_default; +#endif + else { + *((unsigned long *) &tmpaddr[0]) = + be32_to_cpu(readl(fep->enet_addr + + FEC_ADDR_LOW / sizeof(unsigned long))); + *((unsigned short *) &tmpaddr[4]) = + be16_to_cpu(readl(fep->enet_addr + + FEC_ADDR_HIGH / sizeof(unsigned long)) >> 16); + iap = &tmpaddr[0]; + } + + memcpy(dev->dev_addr, iap, ETH_ALEN); + + /* Adjust MAC if using default MAC address */ + if (iap == switch_mac_default) { + dev->dev_addr[ETH_ALEN-1] = + switch_mac_default[ETH_ALEN-1] + index; + index++; + } +} + +static void switch_enable_phy_intr(void) +{ +} + +static void switch_disable_phy_intr(void) +{ +} + +static void switch_phy_ack_intr(void) +{ +} + +static void switch_localhw_setup(void) +{ +} + +static void switch_uncache(unsigned long addr) +{ +} + +static void switch_platform_flush_cache(void) +{ +} + +/* + * Calculate Galois Field Arithmetic CRC for Polynom x^8+x^2+x+1. + * It omits the final shift in of 8 zeroes a "normal" CRC would do + * (getting the remainder). + * + * Examples (hexadecimal values):
+ * 10-11-12-13-14-15 => CRC=0xc2 + * 10-11-cc-dd-ee-00 => CRC=0xe6 + * + * param: pmacaddress + * A 6-byte array with the MAC address. + * The first byte is the first byte transmitted + * return The 8-bit CRC in bits 7:0 + */ +static int crc8_calc(unsigned char *pmacaddress) +{ + /* byte index */ + int byt; + /* bit index */ + int bit; + int inval; + int crc; + /* preset */ + crc = 0x12; + for (byt = 0; byt < 6; byt++) { + inval = (((int)pmacaddress[byt]) & 0xff); + /* + * shift bit 0 to bit 8 so all our bits + * travel through bit 8 + * (simplifies below calc) + */ + inval <<= 8; + + for (bit = 0; bit < 8; bit++) { + /* next input bit comes into d7 after shift */ + crc |= inval & 0x100; + if (crc & 0x01) + /* before shift */ + crc ^= 0x1c0; + + crc >>= 1; + inval >>= 1; + } + + } + /* upper bits are clean as we shifted in zeroes! */ + return crc; +} + +static void read_atable(struct switch_enet_private *fep, + int index, + unsigned long *read_lo, unsigned long *read_hi) +{ + unsigned long atable_base = (unsigned long)fep->hwentry; + + *read_lo = readl(atable_base + (index<<3)); + *read_hi = readl(atable_base + (index<<3) + 4); +} + +static void write_atable(struct switch_enet_private *fep, + int index, + unsigned long write_lo, unsigned long write_hi) +{ + unsigned long atable_base = (unsigned long)fep->hwentry; + + writel(write_lo, atable_base + (index<<3)); + writel(write_hi, atable_base + (index<<3) + 4); +} + +/* Read one element from the HW receive FIFO (Queue) + * if available and return it. + * return ms_HwPortInfo or null if no data is available + */ +static struct eswPortInfo *esw_portinfofifo_read( + struct switch_enet_private *fep) +{ + struct switch_t *fecp; + unsigned long tmp; + + fecp = fep->hwp; + if (fecp->ESW_LSR == 0) { + printk(KERN_ERR "%s: ESW_LSR = %lx\n", + __func__, fecp->ESW_LSR); + return NULL; + } + /* read word from FIFO */ + g_info.maclo = fecp->ESW_LREC0; + /* but verify that we actually did so + * (0=no data available) + */ + if (g_info.maclo == 0) { + printk(KERN_ERR "%s: mac lo %x\n", + __func__, g_info.maclo); + return NULL; + } + /* read 2nd word from FIFO */ + tmp = fecp->ESW_LREC1; + g_info.machi = tmp & 0xffff; + g_info.hash = (tmp >> 16) & 0xff; + g_info.port = (tmp >> 24) & 0xf; + + return &g_info; +} + + +/* + * Clear complete MAC Look Up Table + */ +static void esw_clear_atable(struct switch_enet_private *fep) +{ + int index; + for (index = 0; index < 2048; index++) + write_atable(fep, index, 0, 0); +} + +/* + * pdates MAC address lookup table with a static entry + * Searches if the MAC address is already there in the block and replaces + * the older entry with new one. If MAC address is not there then puts a + * new entry in the first empty slot available in the block + * + * mac_addr Pointer to the array containing MAC address to + * be put as static entry + * port Port bitmask numbers to be added in static entry, + * valid values are 1-7 + * priority Priority for the static entry in table + * + * return 0 for a successful update else -1 when no slot available + */ +static int esw_update_atable_static(unsigned char *mac_addr, + unsigned int port, unsigned int priority, + struct switch_enet_private *fep) +{ + unsigned long block_index, entry, index_end; + + unsigned long read_lo, read_hi; + unsigned long write_lo, write_hi; + + write_lo = (unsigned long)((mac_addr[3] << 24) | + (mac_addr[2] << 16) | + (mac_addr[1] << 8) | + mac_addr[0]); + write_hi = (unsigned long)(0 | + (port << AT_SENTRY_PORTMASK_shift) | + (priority << AT_SENTRY_PRIO_shift) | + (AT_ENTRY_TYPE_STATIC << AT_ENTRY_TYPE_shift) | + (AT_ENTRY_RECORD_VALID << AT_ENTRY_VALID_shift) | + (mac_addr[5] << 8) | (mac_addr[4])); + + block_index = GET_BLOCK_PTR(crc8_calc(mac_addr)); + index_end = block_index + ATABLE_ENTRY_PER_SLOT; + /* Now search all the entries in the selected block */ + for (entry = block_index; entry < index_end; entry++) { + read_atable(fep, entry, &read_lo, &read_hi); + /* + * MAC address matched, so update the + * existing entry + * even if its a dynamic one + */ + if ((read_lo == write_lo) && + ((read_hi & 0x0000ffff) == + (write_hi & 0x0000ffff))) { + write_atable(fep, entry, write_lo, write_hi); + return 0; + } else if (!(read_hi & (1 << 16))) { + /* + * Fill this empty slot (valid bit zero), + * assuming no holes in the block + */ + write_atable(fep, entry, write_lo, write_hi); + fep->atCurrEntries++; + return 0; + } + } + + /* No space available for this static entry */ + return -1; +} + +static int esw_update_atable_dynamic1(unsigned long write_lo, + unsigned long write_hi, int block_index, + unsigned int port, unsigned int currTime, + struct switch_enet_private *fep) +{ + unsigned long entry, index_end; + unsigned long read_lo, read_hi; + unsigned long tmp; + int time, timeold, indexold; + + /* prepare update port and timestamp */ + tmp = AT_ENTRY_RECORD_VALID << AT_ENTRY_VALID_shift; + tmp |= AT_ENTRY_TYPE_DYNAMIC << AT_ENTRY_TYPE_shift; + tmp |= currTime << AT_DENTRY_TIME_shift; + tmp |= port << AT_DENTRY_PORT_shift; + tmp |= write_hi; + + /* + * linear search through all slot + * entries and update if found + */ + index_end = block_index + ATABLE_ENTRY_PER_SLOT; + /* Now search all the entries in the selected block */ + for (entry = block_index; entry < index_end; entry++) { + read_atable(fep, entry, &read_lo, &read_hi); + if ((read_lo == write_lo) && + ((read_hi & 0x0000ffff) == + (write_hi & 0x0000ffff))) { + /* found correct address, + * update timestamp. + */ + write_atable(fep, entry, write_lo, tmp); + return 0; + } else if (!(read_hi & (1 << 16))) { + /* slot is empty, then use it + * for new entry + * Note: There are no holes, + * therefore cannot be any + * more that need to be compared. + */ + write_atable(fep, entry, write_lo, tmp); + /* statistics (we do it between writing + * .hi an .lo due to + * hardware limitation... + */ + fep->atCurrEntries++; + /* newly inserted */ + return 1; + } + } + + /* + * no more entry available in block ... + * overwrite oldest + */ + timeold = 0; + indexold = 0; + for (entry = block_index; entry < index_end; entry++) { + read_atable(fep, entry, &read_lo, &read_hi); + time = AT_EXTRACT_TIMESTAMP(read_hi); + printk(KERN_ERR "%s : time %x currtime %x\n", + __func__, time, currTime); + time = TIMEDELTA(currTime, time); + if (time > timeold) { + /* is it older ? */ + timeold = time; + indexold = entry; + } + } + + write_atable(fep, indexold, write_lo, tmp); + /* + * Statistics (do it inbetween + *writing to .lo and .hi + */ + fep->atBlockOverflows++; + printk(KERN_ERR "%s update time, atBlockOverflows %x\n", + __func__, fep->atBlockOverflows); + /* newly inserted */ + return 1; +} + +/* dynamicms MAC address table learn and migration */ +static int esw_atable_dynamicms_learn_migration( + struct switch_enet_private *fep, + int currTime) +{ + struct eswPortInfo *pESWPortInfo; + int index; + int inserted = 0; + + pESWPortInfo = esw_portinfofifo_read(fep); + /* Anything to learn */ + if (pESWPortInfo != 0) { + /* get block index from lookup table */ + index = GET_BLOCK_PTR(pESWPortInfo->hash); + inserted = esw_update_atable_dynamic1( + pESWPortInfo->maclo, + pESWPortInfo->machi, index, + pESWPortInfo->port, currTime, fep); + } else { + printk(KERN_ERR "%s:hav invalidate learned data \n", __func__); + return -1; + } + + return 0; + +} + +/* + * esw_forced_forward + * The frame is forwared to the forced destination ports. + * It only replace the MAC lookup function, + * all other filtering(eg.VLAN verification) act as normal + */ +static int esw_forced_forward(struct switch_enet_private *fep, + int port1, int port2, int enable) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + + /* Enable Forced forwarding for port num */ + if ((port1 == 1) && (port2 == 1)) + tmp |= MCF_ESW_P0FFEN_FD(3); + else if (port1 == 1) + /* Enable Forced forwarding for port 1 only */ + tmp |= MCF_ESW_P0FFEN_FD(1); + else if (port2 == 1) + /* Enable Forced forwarding for port 2 only */ + tmp |= MCF_ESW_P0FFEN_FD(2); + else { + printk(KERN_ERR "%s:do not support " + "the forced forward mode" + "port1 %x port2 %x\n", + __func__, port1, port2); + return -1; + } + + if (enable == 1) + tmp |= MCF_ESW_P0FFEN_FEN; + else if (enable == 0) + tmp &= ~MCF_ESW_P0FFEN_FEN; + else { + printk(KERN_ERR "%s: the enable %x is error\n", + __func__, enable); + return -2; + } + + fecp->ESW_P0FFEN = tmp; + return 0; +} + +static int esw_get_forced_forward( + struct switch_enet_private *fep, + unsigned long *ulForceForward) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulForceForward = fecp->ESW_P0FFEN; +#ifdef DEBUG_FORCED_FORWARD + printk(KERN_INFO "%s ESW_P0FFEN %#lx\n", + __func__, fecp->ESW_P0FFEN); +#endif + return 0; +} + +static void esw_get_port_enable( + struct switch_enet_private *fep, + unsigned long *ulPortEnable) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulPortEnable = fecp->ESW_PER; +#ifdef DEBUG_PORT_ENABLE + printk(KERN_INFO "%s fecp->ESW_PER %#lx\n", + __func__, fecp->ESW_PER); +#endif +} +/* + * enable or disable port n tx or rx + * tx_en 0 disable port n tx + * tx_en 1 enable port n tx + * rx_en 0 disbale port n rx + * rx_en 1 enable port n rx + */ +static int esw_port_enable_config(struct switch_enet_private *fep, + int port, int tx_en, int rx_en) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + tmp = fecp->ESW_PER; + if (tx_en == 1) { + if (port == 0) + tmp |= MCF_ESW_PER_TE0; + else if (port == 1) + tmp |= MCF_ESW_PER_TE1; + else if (port == 2) + tmp |= MCF_ESW_PER_TE2; + else { + printk(KERN_ERR "%s:do not support the" + " port %x tx enable %d\n", + __func__, port, tx_en); + return -1; + } + } else if (tx_en == 0) { + if (port == 0) + tmp &= (~MCF_ESW_PER_TE0); + else if (port == 1) + tmp &= (~MCF_ESW_PER_TE1); + else if (port == 2) + tmp &= (~MCF_ESW_PER_TE2); + else { + printk(KERN_ERR "%s:do not support " + "the port %x tx disable %d\n", + __func__, port, tx_en); + return -2; + } + } else { + printk(KERN_ERR "%s:do not support the port %x" + " tx op value %x\n", + __func__, port, tx_en); + return -3; + } + + if (rx_en == 1) { + if (port == 0) + tmp |= MCF_ESW_PER_RE0; + else if (port == 1) + tmp |= MCF_ESW_PER_RE1; + else if (port == 2) + tmp |= MCF_ESW_PER_RE2; + else { + printk(KERN_ERR "%s:do not support the " + "port %x rx enable %d\n", + __func__, port, tx_en); + return -4; + } + } else if (rx_en == 0) { + if (port == 0) + tmp &= (~MCF_ESW_PER_RE0); + else if (port == 1) + tmp &= (~MCF_ESW_PER_RE1); + else if (port == 2) + tmp &= (~MCF_ESW_PER_RE2); + else { + printk(KERN_ERR "%s:do not support the " + "port %x rx disable %d\n", + __func__, port, rx_en); + return -5; + } + } else { + printk(KERN_ERR "%s:do not support the port %x" + " rx op value %x\n", + __func__, port, tx_en); + return -6; + } + + fecp->ESW_PER = tmp; + return 0; +} + + +static void esw_get_port_broadcast( + struct switch_enet_private *fep, + unsigned long *ulPortBroadcast) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulPortBroadcast = fecp->ESW_DBCR; +#ifdef DEBUG_PORT_BROADCAST + printk(KERN_INFO "%s fecp->ESW_DBCR %#lx\n", + __func__, fecp->ESW_DBCR); +#endif +} + +static int esw_port_broadcast_config( + struct switch_enet_private *fep, + int port, int enable) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port > 2) || (port < 0)) { + printk(KERN_ERR "%s:do not support the port %x" + " default broadcast\n", + __func__, port); + return -1; + } + + tmp = fecp->ESW_DBCR; + if (enable == 1) { + if (port == 0) + tmp |= MCF_ESW_DBCR_P0; + else if (port == 1) + tmp |= MCF_ESW_DBCR_P1; + else if (port == 2) + tmp |= MCF_ESW_DBCR_P2; + } else if (enable == 0) { + if (port == 0) + tmp &= ~MCF_ESW_DBCR_P0; + else if (port == 1) + tmp &= ~MCF_ESW_DBCR_P1; + else if (port == 2) + tmp &= ~MCF_ESW_DBCR_P2; + } + + fecp->ESW_DBCR = tmp; + return 0; +} + + +static void esw_get_port_multicast( + struct switch_enet_private *fep, + unsigned long *ulPortMulticast) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulPortMulticast = fecp->ESW_DMCR; +#ifdef DEBUG_PORT_MULTICAST + printk(KERN_INFO "%s fecp->ESW_DMCR %#lx\n", + __func__, fecp->ESW_DMCR); +#endif +} + +static int esw_port_multicast_config( + struct switch_enet_private *fep, + int port, int enable) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port > 2) || (port < 0)) { + printk(KERN_ERR "%s:do not support the port %x" + " default broadcast\n", + __func__, port); + return -1; + } + + tmp = fecp->ESW_DMCR; + if (enable == 1) { + if (port == 0) + tmp |= MCF_ESW_DMCR_P0; + else if (port == 1) + tmp |= MCF_ESW_DMCR_P1; + else if (port == 2) + tmp |= MCF_ESW_DMCR_P2; + } else if (enable == 0) { + if (port == 0) + tmp &= ~MCF_ESW_DMCR_P0; + else if (port == 1) + tmp &= ~MCF_ESW_DMCR_P1; + else if (port == 2) + tmp &= ~MCF_ESW_DMCR_P2; + } + + fecp->ESW_DMCR = tmp; + return 0; +} + + +static void esw_get_port_blocking( + struct switch_enet_private *fep, + unsigned long *ulPortBlocking) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulPortBlocking = (fecp->ESW_BKLR & 0x00ff); +#ifdef DEBUG_PORT_BLOCKING + printk(KERN_INFO "%s fecp->ESW_BKLR %#lx\n", + __func__, fecp->ESW_BKLR); +#endif +} + +static int esw_port_blocking_config( + struct switch_enet_private *fep, + int port, int enable) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port > 2) || (port < 0)) { + printk(KERN_ERR "%s:do not support the port %x" + " default broadcast\n", + __func__, port); + return -1; + } + + tmp = fecp->ESW_BKLR; + if (enable == 1) { + if (port == 0) + tmp |= MCF_ESW_BKLR_BE0; + else if (port == 1) + tmp |= MCF_ESW_BKLR_BE1; + else if (port == 2) + tmp |= MCF_ESW_BKLR_BE2; + } else if (enable == 0) { + if (port == 0) + tmp &= ~MCF_ESW_BKLR_BE0; + else if (port == 1) + tmp &= ~MCF_ESW_BKLR_BE1; + else if (port == 2) + tmp &= ~MCF_ESW_BKLR_BE2; + } + + fecp->ESW_BKLR = tmp; + return 0; +} + + +static void esw_get_port_learning( + struct switch_enet_private *fep, + unsigned long *ulPortLearning) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulPortLearning = (fecp->ESW_BKLR & 0xff00) >> 16; +#ifdef DEBUG_PORT_LEARNING + printk(KERN_INFO "%s fecp->ESW_BKLR %#lx\n", + __func__, fecp->ESW_BKLR); +#endif +} + +static int esw_port_learning_config( + struct switch_enet_private *fep, + int port, int disable) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port > 2) || (port < 0)) { + printk(KERN_ERR "%s:do not support the port %x" + " default broadcast\n", + __func__, port); + return -1; + } + + tmp = fecp->ESW_BKLR; + if (disable == 1) { + fep->learning_irqhandle_enable = 0; + if (port == 0) + tmp |= MCF_ESW_BKLR_LD0; + else if (port == 1) + tmp |= MCF_ESW_BKLR_LD1; + else if (port == 2) + tmp |= MCF_ESW_BKLR_LD2; + } else if (disable == 0) { + fep->learning_irqhandle_enable = 1; + fecp->switch_imask |= MCF_ESW_IMR_LRN; + if (port == 0) + tmp &= ~MCF_ESW_BKLR_LD0; + else if (port == 1) + tmp &= ~MCF_ESW_BKLR_LD1; + else if (port == 2) + tmp &= ~MCF_ESW_BKLR_LD2; + } + + fecp->ESW_BKLR = tmp; +#ifdef DEBUG_PORT_LEARNING + printk(KERN_INFO "%s ESW_BKLR %#lx, switch_imask %#lx\n", + __func__, fecp->ESW_BKLR, fecp->switch_imask); +#endif + return 0; +} + +/* + * Checks IP Snoop options of handling the snooped frame. + * mode 0 : The snooped frame is forward only to management port + * mode 1 : The snooped frame is copy to management port and + * normal forwarding is checked. + * mode 2 : The snooped frame is discarded. + * mode 3 : Disable the ip snoop function + * ip_header_protocol : the IP header protocol field + */ +static int esw_ip_snoop_config(struct switch_enet_private *fep, + int num, int mode, unsigned long ip_header_protocol) +{ + struct switch_t *fecp; + unsigned long tmp = 0, protocol_type = 0; + + fecp = fep->hwp; + /* Config IP Snooping */ + if (mode == 0) { + /* Enable IP Snooping */ + tmp = MCF_ESW_IPSNP_EN; + tmp |= MCF_ESW_IPSNP_MODE(0);/*For Forward*/ + } else if (mode == 1) { + /* Enable IP Snooping */ + tmp = MCF_ESW_IPSNP_EN; + /*For Forward and copy_to_mangmnt_port*/ + tmp |= MCF_ESW_IPSNP_MODE(1); + } else if (mode == 2) { + /* Enable IP Snooping */ + tmp = MCF_ESW_IPSNP_EN; + tmp |= MCF_ESW_IPSNP_MODE(2);/*discard*/ + } else if (mode == 3) { + /* disable IP Snooping */ + tmp = MCF_ESW_IPSNP_EN; + tmp &= ~MCF_ESW_IPSNP_EN; + } else { + printk(KERN_ERR "%s: the mode %x " + "we do not support\n", __func__, mode); + return -1; + } + + protocol_type = ip_header_protocol; + fecp->ESW_IPSNP[num] = + tmp | MCF_ESW_IPSNP_PROTOCOL(protocol_type); + printk(KERN_INFO "%s : ESW_IPSNP[%d] %#lx\n", + __func__, num, fecp->ESW_IPSNP[num]); + return 0; +} + +static void esw_get_ip_snoop_config( + struct switch_enet_private *fep, + unsigned long *ulpESW_IPSNP) +{ + int i; + struct switch_t *fecp; + + fecp = fep->hwp; + for (i = 0; i < 8; i++) + *(ulpESW_IPSNP + i) = fecp->ESW_IPSNP[i]; +#ifdef DEBUG_IP_SNOOP + printk(KERN_INFO "%s ", __func__); + for (i = 0; i < 8; i++) + printk(KERN_INFO " reg(%d) %#lx", fecp->ESW_IPSNP[i]); + printk(KERN_INFO "\n"); +#endif + +} +/* + * Checks TCP/UDP Port Snoop options of handling the snooped frame. + * mode 0 : The snooped frame is forward only to management port + * mode 1 : The snooped frame is copy to management port and + * normal forwarding is checked. + * mode 2 : The snooped frame is discarded. + * compare_port : port number in the TCP/UDP header + * compare_num 1: TCP/UDP source port number is compared + * compare_num 2: TCP/UDP destination port number is compared + * compare_num 3: TCP/UDP source and destination port number is compared + */ +static int esw_tcpudp_port_snoop_config(struct switch_enet_private *fep, + int num, int mode, int compare_port, int compare_num) +{ + struct switch_t *fecp; + unsigned long tmp = 0; + + fecp = fep->hwp; + + /* Enable TCP/UDP port Snooping */ + tmp = MCF_ESW_PSNP_EN; + if (mode == 0) + tmp |= MCF_ESW_PSNP_MODE(0);/* For Forward */ + else if (mode == 1)/*For Forward and copy_to_mangmnt_port*/ + tmp |= MCF_ESW_PSNP_MODE(1); + else if (mode == 2) + tmp |= MCF_ESW_PSNP_MODE(2);/* discard */ + else if (mode == 3) /* disable the port function */ + tmp &= (~MCF_ESW_PSNP_EN); + else { + printk(KERN_ERR "%s: the mode %x we do not support\n", + __func__, mode); + return -1; + } + + if (compare_num == 1) + tmp |= MCF_ESW_PSNP_CS; + else if (compare_num == 2) + tmp |= MCF_ESW_PSNP_CD; + else if (compare_num == 3) + tmp |= MCF_ESW_PSNP_CD | MCF_ESW_PSNP_CS; + else { + printk(KERN_ERR "%s: the compare port address %x" + " we do not support\n", + __func__, compare_num); + return -1; + } + + fecp->ESW_PSNP[num] = tmp | + MCF_ESW_PSNP_PORT_COMPARE(compare_port); + printk(KERN_INFO "ESW_PSNP[%d] %#lx\n", + num, fecp->ESW_PSNP[num]); + return 0; +} + +static void esw_get_tcpudp_port_snoop_config( + struct switch_enet_private *fep, + unsigned long *ulpESW_PSNP) +{ + int i; + struct switch_t *fecp; + + fecp = fep->hwp; + for (i = 0; i < 8; i++) + *(ulpESW_PSNP + i) = fecp->ESW_PSNP[i]; +#ifdef DEBUG_TCPUDP_PORT_SNOOP + printk(KERN_INFO "%s ", __func__); + for (i = 0; i < 8; i++) + printk(KERN_INFO " reg(%d) %#lx", fecp->ESW_PSNP[i]); + printk(KERN_INFO "\n"); +#endif + +} + +static void esw_get_port_mirroring( + struct switch_enet_private *fep, + struct eswIoctlPortMirrorStatus *pPortMirrorStatus) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + pPortMirrorStatus->ESW_MCR = fecp->ESW_MCR; + pPortMirrorStatus->ESW_EGMAP = fecp->ESW_EGMAP; + pPortMirrorStatus->ESW_INGMAP = fecp->ESW_INGMAP; + pPortMirrorStatus->ESW_INGSAL = fecp->ESW_INGSAL; + pPortMirrorStatus->ESW_INGSAH = fecp->ESW_INGSAH; + pPortMirrorStatus->ESW_INGDAL = fecp->ESW_INGDAL; + pPortMirrorStatus->ESW_INGDAH = fecp->ESW_INGDAH; + pPortMirrorStatus->ESW_ENGSAL = fecp->ESW_ENGSAL; + pPortMirrorStatus->ESW_ENGSAH = fecp->ESW_ENGSAH; + pPortMirrorStatus->ESW_ENGDAL = fecp->ESW_ENGDAL; + pPortMirrorStatus->ESW_ENGDAH = fecp->ESW_ENGDAH; + pPortMirrorStatus->ESW_MCVAL = fecp->ESW_MCVAL; +#ifdef DEBUG_PORT_MIRROR + printk(KERN_INFO "%s : ESW_MCR %#lx, ESW_EGMAP %#lx\n" + "ESW_INGMAP %#lx, ESW_INGSAL %#lx, " + "ESW_INGSAH %#lx ESW_INGDAL %#lx, ESW_INGDAH %#lx\n" + "ESW_ENGSAL %#lx, ESW_ENGSAH%#lx, ESW_ENGDAL %#lx," + "ESW_ENGDAH %#lx, ESW_MCVAL %#lx\n", + __func__, fecp->ESW_MCR, fecp->ESW_EGMAP, fecp->ESW_INGMAP, + fecp->ESW_INGSAL, fecp->ESW_INGSAH, fecp->ESW_INGDAL, + fecp->ESW_INGDAH, fecp->ESW_ENGSAL, fecp->ESW_ENGSAH, + fecp->ESW_ENGDAL, fecp->ESW_ENGDAH, fecp->ESW_MCVAL); +#endif +} + +static int esw_port_mirroring_config(struct switch_enet_private *fep, + int mirror_port, int port, int mirror_enable, + unsigned char *src_mac, unsigned char *des_mac, + int egress_en, int ingress_en, + int egress_mac_src_en, int egress_mac_des_en, + int ingress_mac_src_en, int ingress_mac_des_en) +{ + struct switch_t *fecp; + unsigned long tmp = 0; + + fecp = fep->hwp; + + /*mirroring config*/ + tmp = 0; + if (egress_en == 1) { + tmp |= MCF_ESW_MCR_EGMAP; + if (port == 0) + fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG0; + else if (port == 1) + fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG1; + else if (port == 2) + fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG2; + else { + printk(KERN_ERR "%s: the port %x we do not support\n", + __func__, port); + return -1; + } + } else if (egress_en == 0) { + tmp &= (~MCF_ESW_MCR_EGMAP); + } else { + printk(KERN_ERR "%s: egress_en %x we do not support\n", + __func__, egress_en); + return -1; + } + + if (ingress_en == 1) { + tmp |= MCF_ESW_MCR_INGMAP; + if (port == 0) + fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING0; + else if (port == 1) + fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING1; + else if (port == 2) + fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING2; + else { + printk(KERN_ERR "%s: the port %x we do not support\n", + __func__, port); + return -1; + } + } else if (ingress_en == 0) { + tmp &= ~MCF_ESW_MCR_INGMAP; + } else{ + printk(KERN_ERR "%s: ingress_en %x we do not support\n", + __func__, ingress_en); + return -1; + } + + if (egress_mac_src_en == 1) { + tmp |= MCF_ESW_MCR_EGSA; + fecp->ESW_ENGSAH = (src_mac[5] << 8) | (src_mac[4]); + fecp->ESW_ENGSAL = (unsigned long)((src_mac[3] << 24) | + (src_mac[2] << 16) | + (src_mac[1] << 8) | + src_mac[0]); + } else if (egress_mac_src_en == 0) { + tmp &= ~MCF_ESW_MCR_EGSA; + } else { + printk(KERN_ERR "%s: egress_mac_src_en %x we do not support\n", + __func__, egress_mac_src_en); + return -1; + } + + if (egress_mac_des_en == 1) { + tmp |= MCF_ESW_MCR_EGDA; + fecp->ESW_ENGDAH = (des_mac[5] << 8) | (des_mac[4]); + fecp->ESW_ENGDAL = (unsigned long)((des_mac[3] << 24) | + (des_mac[2] << 16) | + (des_mac[1] << 8) | + des_mac[0]); + } else if (egress_mac_des_en == 0) { + tmp &= ~MCF_ESW_MCR_EGDA; + } else { + printk(KERN_ERR "%s: egress_mac_des_en %x we do not support\n", + __func__, egress_mac_des_en); + return -1; + } + + if (ingress_mac_src_en == 1) { + tmp |= MCF_ESW_MCR_INGSA; + fecp->ESW_INGSAH = (src_mac[5] << 8) | (src_mac[4]); + fecp->ESW_INGSAL = (unsigned long)((src_mac[3] << 24) | + (src_mac[2] << 16) | + (src_mac[1] << 8) | + src_mac[0]); + } else if (ingress_mac_src_en == 0) { + tmp &= ~MCF_ESW_MCR_INGSA; + } else { + printk(KERN_ERR "%s: ingress_mac_src_en %x we do not support\n", + __func__, ingress_mac_src_en); + return -1; + } + + if (ingress_mac_des_en == 1) { + tmp |= MCF_ESW_MCR_INGDA; + fecp->ESW_INGDAH = (des_mac[5] << 8) | (des_mac[4]); + fecp->ESW_INGDAL = (unsigned long)((des_mac[3] << 24) | + (des_mac[2] << 16) | + (des_mac[1] << 8) | + des_mac[0]); + } else if (ingress_mac_des_en == 0) { + tmp &= ~MCF_ESW_MCR_INGDA; + } else { + printk(KERN_ERR "%s: ingress_mac_des_en %x we do not support\n", + __func__, ingress_mac_des_en); + return -1; + } + + /*------------------------------------------------------------------*/ + if (mirror_enable == 1) + tmp |= MCF_ESW_MCR_MEN | MCF_ESW_MCR_PORT(mirror_port); + else if (mirror_enable == 0) + tmp &= ~MCF_ESW_MCR_MEN; + else + printk(KERN_ERR "%s: the mirror enable %x is error\n", + __func__, mirror_enable); + + + fecp->ESW_MCR = tmp; + printk(KERN_INFO "%s : MCR %#lx, EGMAP %#lx, INGMAP %#lx;\n" + "ENGSAH %#lx, ENGSAL %#lx ;ENGDAH %#lx, ENGDAL %#lx;\n" + "INGSAH %#lx, INGSAL %#lx\n;INGDAH %#lx, INGDAL %#lx;\n", + __func__, fecp->ESW_MCR, fecp->ESW_EGMAP, fecp->ESW_INGMAP, + fecp->ESW_ENGSAH, fecp->ESW_ENGSAL, + fecp->ESW_ENGDAH, fecp->ESW_ENGDAL, + fecp->ESW_INGSAH, fecp->ESW_INGSAL, + fecp->ESW_INGDAH, fecp->ESW_INGDAL); + return 0; +} + +static void esw_get_vlan_verification( + struct switch_enet_private *fep, + unsigned long *ulValue) +{ + struct switch_t *fecp; + fecp = fep->hwp; + *ulValue = fecp->ESW_VLANV; + +#ifdef DEBUG_VLAN_VERIFICATION_CONFIG + printk(KERN_INFO "%s: ESW_VLANV %#lx\n", + __func__, fecp->ESW_VLANV); +#endif +} + +static int esw_set_vlan_verification( + struct switch_enet_private *fep, int port, + int vlan_domain_verify_en, + int vlan_discard_unknown_en) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + if ((port < 0) || (port > 2)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + + if (vlan_domain_verify_en == 1) { + if (port == 0) + fecp->ESW_VLANV |= MCF_ESW_VLANV_VV0; + else if (port == 1) + fecp->ESW_VLANV |= MCF_ESW_VLANV_VV1; + else if (port == 2) + fecp->ESW_VLANV |= MCF_ESW_VLANV_VV2; + } else if (vlan_domain_verify_en == 0) { + if (port == 0) + fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV0; + else if (port == 1) + fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV1; + else if (port == 2) + fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV2; + } else { + printk(KERN_INFO "%s: donot support " + "vlan_domain_verify %x\n", + __func__, vlan_domain_verify_en); + return -2; + } + + if (vlan_discard_unknown_en == 1) { + if (port == 0) + fecp->ESW_VLANV |= MCF_ESW_VLANV_DU0; + else if (port == 1) + fecp->ESW_VLANV |= MCF_ESW_VLANV_DU1; + else if (port == 2) + fecp->ESW_VLANV |= MCF_ESW_VLANV_DU2; + } else if (vlan_discard_unknown_en == 0) { + if (port == 0) + fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU0; + else if (port == 1) + fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU1; + else if (port == 2) + fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU2; + } else { + printk(KERN_INFO "%s: donot support " + "vlan_discard_unknown %x\n", + __func__, vlan_discard_unknown_en); + return -3; + } + +#ifdef DEBUG_VLAN_VERIFICATION_CONFIG + printk(KERN_INFO "%s: ESW_VLANV %#lx\n", + __func__, fecp->ESW_VLANV); +#endif + return 0; +} + +static void esw_get_vlan_resolution_table( + struct switch_enet_private *fep, + int vlan_domain_num, + unsigned long *ulValue) +{ + struct switch_t *fecp; + fecp = fep->hwp; + + *ulValue = fecp->ESW_VRES[vlan_domain_num]; + +#ifdef DEBUG_VLAN_DOMAIN_TABLE + printk(KERN_INFO "%s: ESW_VRES[%d] = %#lx\n", + __func__, vlan_domain_num, + fecp->ESW_VRES[vlan_domain_num]); +#endif +} + +int esw_set_vlan_resolution_table( + struct switch_enet_private *fep, + unsigned short port_vlanid, + int vlan_domain_num, + int vlan_domain_port) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + if ((vlan_domain_num < 0) + || (vlan_domain_num > 31)) { + printk(KERN_ERR "%s: do not support the " + "vlan_domain_num %d\n", + __func__, vlan_domain_num); + return -1; + } + + if ((vlan_domain_port < 0) + || (vlan_domain_port > 7)) { + printk(KERN_ERR "%s: do not support the " + "vlan_domain_port %d\n", + __func__, vlan_domain_port); + return -2; + } + + fecp->ESW_VRES[vlan_domain_num] = + MCF_ESW_VRES_VLANID(port_vlanid) + | vlan_domain_port; + +#ifdef DEBUG_VLAN_DOMAIN_TABLE + printk(KERN_INFO "%s: ESW_VRES[%d] = %#lx\n", + __func__, vlan_domain_num, + fecp->ESW_VRES[vlan_domain_num]); +#endif + return 0; +} + +static void esw_get_vlan_input_config( + struct switch_enet_private *fep, + struct eswIoctlVlanInputStatus *pVlanInputConfig) +{ + struct switch_t *fecp; + int i; + + fecp = fep->hwp; + for (i = 0; i < 3; i++) + pVlanInputConfig->ESW_PID[i] = fecp->ESW_PID[i]; + + pVlanInputConfig->ESW_VLANV = fecp->ESW_VLANV; + pVlanInputConfig->ESW_VIMSEL = fecp->ESW_VIMSEL; + pVlanInputConfig->ESW_VIMEN = fecp->ESW_VIMEN; + + for (i = 0; i < 32; i++) + pVlanInputConfig->ESW_VRES[i] = fecp->ESW_VRES[i]; +#ifdef DEBUG_VLAN_INTPUT_CONFIG + printk(KERN_INFO "%s: ESW_VLANV %#lx, ESW_VIMSEL %#lx, " + "ESW_VIMEN %#lx, ESW_PID[0], ESW_PID[1] %#lx, " + "ESW_PID[2] %#lx", __func__, + fecp->ESW_VLANV, fecp->ESW_VIMSEL, fecp->ESW_VIMEN, + fecp->ESW_PID[0], fecp->ESW_PID[1], fecp->ESW_PID[2]); +#endif +} + + +static int esw_vlan_input_process(struct switch_enet_private *fep, + int port, int mode, unsigned short port_vlanid, + int vlan_verify_en, int vlan_domain_num, + int vlan_domain_port) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + /*we only support mode1 mode2 mode3 mode4*/ + if ((mode < 0) || (mode > 3)) { + printk(KERN_ERR "%s: do not support the" + " VLAN input processing mode %d\n", + __func__, mode); + return -1; + } + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, mode); + return -2; + } + + if ((vlan_verify_en == 1) && ((vlan_domain_num < 0) + || (vlan_domain_num > 32))) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, mode); + return -3; + } + + fecp->ESW_PID[port] = MCF_ESW_PID_VLANID(port_vlanid); + if (port == 0) { + if (vlan_verify_en == 1) + fecp->ESW_VRES[vlan_domain_num] = + MCF_ESW_VRES_VLANID(port_vlanid) + | MCF_ESW_VRES_P0; + + fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN0; + fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM0(mode); + } else if (port == 1) { + if (vlan_verify_en == 1) + fecp->ESW_VRES[vlan_domain_num] = + MCF_ESW_VRES_VLANID(port_vlanid) + | MCF_ESW_VRES_P1; + + fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN1; + fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM1(mode); + } else if (port == 2) { + if (vlan_verify_en == 1) + fecp->ESW_VRES[vlan_domain_num] = + MCF_ESW_VRES_VLANID(port_vlanid) + | MCF_ESW_VRES_P2; + + fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN2; + fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM2(mode); + } else { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -2; + } + + return 0; +} + +static void esw_get_vlan_output_config(struct switch_enet_private *fep, + unsigned long *ulVlanOutputConfig) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + *ulVlanOutputConfig = fecp->ESW_VOMSEL; +#ifdef DEBUG_VLAN_OUTPUT_CONFIG + printk(KERN_INFO "%s: ESW_VOMSEL %#lx", __func__, + fecp->ESW_VOMSEL); +#endif +} + +static int esw_vlan_output_process(struct switch_enet_private *fep, + int port, int mode) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port < 0) || (port > 2)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, mode); + return -1; + } + + if (port == 0) { + fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM0(mode); + } else if (port == 1) { + fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM1(mode); + } else if (port == 2) { + fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM2(mode); + } else { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + return 0; +} + +/* frame calssify and priority resolution */ +/* vlan priority lookup */ +static int esw_framecalssify_vlan_priority_lookup( + struct switch_enet_private *fep, + int port, int func_enable, + int vlan_pri_table_num, + int vlan_pri_table_value) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + + if (func_enable == 0) { + fecp->ESW_PRES[port] &= ~MCF_ESW_PRES_VLAN; + printk(KERN_ERR "%s: disable port %d VLAN priority " + "lookup function\n", __func__, port); + return 0; + } + + if ((vlan_pri_table_num < 0) || (vlan_pri_table_num > 7)) { + printk(KERN_ERR "%s: do not support the priority %d\n", + __func__, vlan_pri_table_num); + return -1; + } + + fecp->ESW_PVRES[port] |= ((vlan_pri_table_value & 0x3) + << (vlan_pri_table_num*3)); + /* enable port VLAN priority lookup function */ + fecp->ESW_PRES[port] |= MCF_ESW_PRES_VLAN; + + return 0; +} + +static int esw_framecalssify_ip_priority_lookup( + struct switch_enet_private *fep, + int port, int func_enable, int ipv4_en, + int ip_priority_num, + int ip_priority_value) +{ + struct switch_t *fecp; + unsigned long tmp = 0, tmp_prio = 0; + + fecp = fep->hwp; + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + + if (func_enable == 0) { + fecp->ESW_PRES[port] &= ~MCF_ESW_PRES_IP; + printk(KERN_ERR "%s: disable port %d ip priority " + "lookup function\n", __func__, port); + return 0; + } + + /* IPV4 priority 64 entry table lookup */ + /* IPv4 head 6 bit TOS field */ + if (ipv4_en == 1) { + if ((ip_priority_num < 0) || (ip_priority_num > 63)) { + printk(KERN_ERR "%s: do not support the table entry %d\n", + __func__, ip_priority_num); + return -2; + } + } else { /* IPV6 priority 256 entry table lookup */ + /* IPv6 head 8 bit COS field */ + if ((ip_priority_num < 0) || (ip_priority_num > 255)) { + printk(KERN_ERR "%s: do not support the table entry %d\n", + __func__, ip_priority_num); + return -3; + } + } + + /* IP priority table lookup : address */ + tmp = MCF_ESW_IPRES_ADDRESS(ip_priority_num); + /* IP priority table lookup : ipv4sel */ + if (ipv4_en == 1) + tmp = tmp | MCF_ESW_IPRES_IPV4SEL; + /* IP priority table lookup : priority */ + if (port == 0) + tmp |= MCF_ESW_IPRES_PRI0(ip_priority_value); + else if (port == 1) + tmp |= MCF_ESW_IPRES_PRI1(ip_priority_value); + else if (port == 2) + tmp |= MCF_ESW_IPRES_PRI2(ip_priority_value); + + /* configure */ + fecp->ESW_IPRES = MCF_ESW_IPRES_READ | + MCF_ESW_IPRES_ADDRESS(ip_priority_num); + tmp_prio = fecp->ESW_IPRES; + + fecp->ESW_IPRES = tmp | tmp_prio; + + fecp->ESW_IPRES = MCF_ESW_IPRES_READ | + MCF_ESW_IPRES_ADDRESS(ip_priority_num); + tmp_prio = fecp->ESW_IPRES; + + /* enable port IP priority lookup function */ + fecp->ESW_PRES[port] |= MCF_ESW_PRES_IP; + + return 0; +} + +static int esw_framecalssify_mac_priority_lookup( + struct switch_enet_private *fep, + int port) +{ + struct switch_t *fecp; + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + + fecp = fep->hwp; + fecp->ESW_PRES[port] |= MCF_ESW_PRES_MAC; + + return 0; +} + +static int esw_frame_calssify_priority_init( + struct switch_enet_private *fep, + int port, unsigned char priority_value) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + /* disable all priority lookup function */ + fecp->ESW_PRES[port] = 0; + fecp->ESW_PRES[port] = MCF_ESW_PRES_DFLT_PRI(priority_value & 0x7); + + return 0; +} + +static int esw_get_statistics_status( + struct switch_enet_private *fep, + struct esw_statistics_status *pStatistics) +{ + struct switch_t *fecp; + fecp = fep->hwp; + + pStatistics->ESW_DISCN = fecp->ESW_DISCN; + pStatistics->ESW_DISCB = fecp->ESW_DISCB; + pStatistics->ESW_NDISCN = fecp->ESW_NDISCN; + pStatistics->ESW_NDISCB = fecp->ESW_NDISCB; +#ifdef DEBUG_STATISTICS + printk(KERN_ERR "%s:ESW_DISCN %#lx, ESW_DISCB %#lx," + "ESW_NDISCN %#lx, ESW_NDISCB %#lx\n", + __func__, fecp->ESW_DISCN, fecp->ESW_DISCB, + fecp->ESW_NDISCN, fecp->ESW_NDISCB); +#endif + return 0; +} + +static int esw_get_port_statistics_status( + struct switch_enet_private *fep, + int port, + struct esw_port_statistics_status *pPortStatistics) +{ + struct switch_t *fecp; + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + + fecp = fep->hwp; + + pPortStatistics->MCF_ESW_POQC = + fecp->port_statistics_status[port].MCF_ESW_POQC; + pPortStatistics->MCF_ESW_PMVID = + fecp->port_statistics_status[port].MCF_ESW_PMVID; + pPortStatistics->MCF_ESW_PMVTAG = + fecp->port_statistics_status[port].MCF_ESW_PMVTAG; + pPortStatistics->MCF_ESW_PBL = + fecp->port_statistics_status[port].MCF_ESW_PBL; +#ifdef DEBUG_PORT_STATISTICS + printk(KERN_ERR "%s : port[%d].MCF_ESW_POQC %#lx, MCF_ESW_PMVID %#lx," + " MCF_ESW_PMVTAG %#lx, MCF_ESW_PBL %#lx\n", + __func__, port, + fecp->port_statistics_status[port].MCF_ESW_POQC, + fecp->port_statistics_status[port].MCF_ESW_PMVID, + fecp->port_statistics_status[port].MCF_ESW_PMVTAG, + fecp->port_statistics_status[port].MCF_ESW_PBL); +#endif + return 0; +} + +static int esw_get_output_queue_status( + struct switch_enet_private *fep, + struct esw_output_queue_status *pOutputQueue) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + pOutputQueue->ESW_MMSR = fecp->ESW_MMSR; + pOutputQueue->ESW_LMT = fecp->ESW_LMT; + pOutputQueue->ESW_LFC = fecp->ESW_LFC; + pOutputQueue->ESW_IOSR = fecp->ESW_IOSR; + pOutputQueue->ESW_PCSR = fecp->ESW_PCSR; + pOutputQueue->ESW_QWT = fecp->ESW_QWT; + pOutputQueue->ESW_P0BCT = fecp->ESW_P0BCT; +#ifdef DEBUG_OUTPUT_QUEUE + printk(KERN_ERR "%s:ESW_MMSR %#lx, ESW_LMT %#lx, ESW_LFC %#lx, " + "ESW_IOSR %#lx, ESW_PCSR %#lx, ESW_QWT %#lx, ESW_P0BCT %#lx\n", + __func__, fecp->ESW_MMSR, + fecp->ESW_LMT, fecp->ESW_LFC, + fecp->ESW_IOSR, fecp->ESW_PCSR, + fecp->ESW_QWT, fecp->ESW_P0BCT); +#endif + return 0; +} + +/* set output queue memory status and configure*/ +static int esw_set_output_queue_memory( + struct switch_enet_private *fep, + int fun_num, + struct esw_output_queue_status *pOutputQueue) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + if (fun_num == 1) { + /* memory manager status*/ + fecp->ESW_MMSR = pOutputQueue->ESW_MMSR; + } else if (fun_num == 2) { + /*low memory threshold*/ + fecp->ESW_LMT = pOutputQueue->ESW_LMT; + } else if (fun_num == 3) { + /*lowest number of free cells*/ + fecp->ESW_LFC = pOutputQueue->ESW_LFC; + } else if (fun_num == 4) { + /*queue weights*/ + fecp->ESW_QWT = pOutputQueue->ESW_QWT; + } else if (fun_num == 5) { + /*port 0 backpressure congenstion thresled*/ + fecp->ESW_P0BCT = pOutputQueue->ESW_P0BCT; + } else { + printk(KERN_INFO "%s: do not support the cmd %x\n", + __func__, fun_num); + return -1; + } +#ifdef DEBUG_OUTPUT_QUEUE + printk(KERN_ERR "%s:ESW_MMSR %#lx, ESW_LMT %#lx, ESW_LFC %#lx, " + "ESW_IOSR %#lx, ESW_PCSR %#lx, ESW_QWT %#lx, ESW_P0BCT %#lx\n", + __func__, fecp->ESW_MMSR, + fecp->ESW_LMT, fecp->ESW_LFC, + fecp->ESW_IOSR, fecp->ESW_PCSR, + fecp->ESW_QWT, fecp->ESW_P0BCT); +#endif + return 0; +} + +int esw_set_irq_mask( + struct switch_enet_private *fep, + unsigned long mask, int enable) +{ + struct switch_t *fecp; + + fecp = fep->hwp; +#ifdef DEBUG_IRQ + printk(KERN_INFO "%s: irq event %#lx, irq mask %#lx " + " mask %x, enable %x\n", + __func__, fecp->switch_ievent, + fecp->switch_imask, mask, enable); +#endif + if (enable == 1) + fecp->switch_imask |= mask; + else if (enable == 1) + fecp->switch_imask &= (~mask); + else { + printk(KERN_INFO "%s: enable %x is error value\n", + __func__, enable); + return -1; + } +#ifdef DEBUG_IRQ + printk(KERN_INFO "%s: irq event %#lx, irq mask %#lx, " + "rx_des_start %#lx, tx_des_start %#lx, " + "rx_buff_size %#lx, rx_des_active %#lx, " + "tx_des_active %#lx\n", + __func__, fecp->switch_ievent, fecp->switch_imask, + fecp->fec_r_des_start, fecp->fec_x_des_start, + fecp->fec_r_buff_size, fecp->fec_r_des_active, + fecp->fec_x_des_active); +#endif + return 0; +} + +static void esw_get_switch_mode( + struct switch_enet_private *fep, + unsigned long *ulModeConfig) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulModeConfig = fecp->ESW_MODE; +#ifdef DEBUG_SWITCH_MODE + printk(KERN_INFO "%s: mode %#lx \n", + __func__, fecp->ESW_MODE); +#endif +} + +static void esw_switch_mode_configure( + struct switch_enet_private *fep, + unsigned long configure) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + fecp->ESW_MODE |= configure; +#ifdef DEBUG_SWITCH_MODE + printk(KERN_INFO "%s: mode %#lx \n", + __func__, fecp->ESW_MODE); +#endif +} + + +static void esw_get_bridge_port( + struct switch_enet_private *fep, + unsigned long *ulBMPConfig) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulBMPConfig = fecp->ESW_BMPC; +#ifdef DEBUG_BRIDGE_PORT + printk(KERN_INFO "%s: bridge management port %#lx \n", + __func__, fecp->ESW_BMPC); +#endif +} + +static void esw_bridge_port_configure( + struct switch_enet_private *fep, + unsigned long configure) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + fecp->ESW_BMPC |= configure; +#ifdef DEBUG_BRIDGE_PORT + printk(KERN_INFO "%s: bridge management port %#lx \n", + __func__, fecp->ESW_BMPC); +#endif +} + +/* The timer should create an interrupt every 4 seconds*/ +static void l2switch_aging_timer(unsigned long data) +{ + struct switch_enet_private *fep; + + fep = (struct switch_enet_private *)data; + + if (fep) { + TIMEINCREMENT(fep->currTime); + fep->timeChanged++; + } + + mod_timer(&fep->timer_aging, jiffies + LEARNING_AGING_TIMER); +} + +void esw_check_rxb_txb_interrupt(struct switch_enet_private *fep) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + /*Enable Forced forwarding for port 1*/ + fecp->ESW_P0FFEN = MCF_ESW_P0FFEN_FEN | + MCF_ESW_P0FFEN_FD(1); + /*Disable learning for all ports*/ + + fecp->switch_imask = MCF_ESW_IMR_TXB | MCF_ESW_IMR_TXF | + MCF_ESW_IMR_LRN | MCF_ESW_IMR_RXB | MCF_ESW_IMR_RXF; + printk(KERN_ERR "%s: fecp->ESW_DBCR %#lx, fecp->ESW_P0FFEN %#lx" + " fecp->ESW_BKLR %#lx\n", __func__, fecp->ESW_DBCR, + fecp->ESW_P0FFEN, fecp->ESW_BKLR); +} + +static int esw_mac_addr_static(struct switch_enet_private *fep) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + fecp->ESW_DBCR = MCF_ESW_DBCR_P1; + + if (is_valid_ether_addr(fep->netdev->dev_addr)) + esw_update_atable_static(fep->netdev->dev_addr, 7, 7, fep); + else{ + printk(KERN_ERR "Can not add available mac address" + " for switch!!\n"); + return -EFAULT; + } + + return 0; +} + +static void esw_main(struct switch_enet_private *fep) +{ + struct switch_t *fecp; + fecp = fep->hwp; + + esw_mac_addr_static(fep); + fecp->ESW_BKLR = 0; + fecp->switch_imask = MCF_ESW_IMR_TXB | MCF_ESW_IMR_TXF | + MCF_ESW_IMR_LRN | MCF_ESW_IMR_RXB | MCF_ESW_IMR_RXF; + fecp->ESW_PER = 0x70007; + fecp->ESW_DBCR = MCF_ESW_DBCR_P1 | MCF_ESW_DBCR_P2; +} + +static int switch_enet_ioctl( + struct net_device *dev, + struct ifreq *ifr, int cmd) +{ + struct switch_enet_private *fep; + struct switch_t *fecp; + int ret = 0; + + printk(KERN_INFO "%s cmd %x\n", __func__, cmd); + fep = netdev_priv(dev); + fecp = (struct switch_t *)dev->base_addr; + + switch (cmd) { + case ESW_SET_PORTENABLE_CONF: + { + struct eswIoctlPortEnableConfig configData; + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlPortEnableConfig)); + if (ret) + return -EFAULT; + + ret = esw_port_enable_config(fep, + configData.port, + configData.tx_enable, + configData.rx_enable); + } + break; + case ESW_SET_BROADCAST_CONF: + { + struct eswIoctlPortConfig configData; + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortConfig)); + if (ret) + return -EFAULT; + + ret = esw_port_broadcast_config(fep, + configData.port, configData.enable); + } + break; + + case ESW_SET_MULTICAST_CONF: + { + struct eswIoctlPortConfig configData; + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortConfig)); + if (ret) + return -EFAULT; + + ret = esw_port_multicast_config(fep, + configData.port, configData.enable); + } + break; + + case ESW_SET_BLOCKING_CONF: + { + struct eswIoctlPortConfig configData; + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortConfig)); + + if (ret) + return -EFAULT; + + ret = esw_port_blocking_config(fep, + configData.port, configData.enable); + } + break; + + case ESW_SET_LEARNING_CONF: + { + struct eswIoctlPortConfig configData; + printk(KERN_INFO "ESW_SET_LEARNING_CONF\n"); + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortConfig)); + if (ret) + return -EFAULT; + printk(KERN_INFO "ESW_SET_LEARNING_CONF: %x %x\n", + configData.port, configData.enable); + ret = esw_port_learning_config(fep, + configData.port, configData.enable); + } + break; + + case ESW_SET_IP_SNOOP_CONF: + { + struct eswIoctlIpsnoopConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlIpsnoopConfig)); + if (ret) + return -EFAULT; + printk(KERN_INFO "ESW_SET_IP_SNOOP_CONF:: %x %x %x\n", + configData.num, configData.mode, + configData.ip_header_protocol); + ret = esw_ip_snoop_config(fep, + configData.num, configData.mode, + configData.ip_header_protocol); + } + break; + + case ESW_SET_PORT_SNOOP_CONF: + { + struct eswIoctlPortsnoopConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortsnoopConfig)); + if (ret) + return -EFAULT; + printk(KERN_INFO "ESW_SET_PORT_SNOOP_CONF:: %x %x %x %x\n", + configData.num, configData.mode, + configData.compare_port, configData.compare_num); + ret = esw_tcpudp_port_snoop_config(fep, + configData.num, configData.mode, + configData.compare_port, + configData.compare_num); + } + break; + + case ESW_SET_PORT_MIRROR_CONF: + { + struct eswIoctlPortMirrorConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortMirrorConfig)); + if (ret) + return -EFAULT; + printk(KERN_INFO "ESW_SET_PORT_MIRROR_CONF:: %x %x %x " + "%s %s\n %x %x %x %x %x %x\n", + configData.mirror_port, configData.port, + configData.mirror_enable, + configData.src_mac, configData.des_mac, + configData.egress_en, configData.ingress_en, + configData.egress_mac_src_en, + configData.egress_mac_des_en, + configData.ingress_mac_src_en, + configData.ingress_mac_des_en); + ret = esw_port_mirroring_config(fep, + configData.mirror_port, configData.port, + configData.mirror_enable, + configData.src_mac, configData.des_mac, + configData.egress_en, configData.ingress_en, + configData.egress_mac_src_en, + configData.egress_mac_des_en, + configData.ingress_mac_src_en, + configData.ingress_mac_des_en); + } + break; + + case ESW_SET_PIRORITY_VLAN: + { + struct eswIoctlPriorityVlanConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlPriorityVlanConfig)); + if (ret) + return -EFAULT; + + ret = esw_framecalssify_vlan_priority_lookup(fep, + configData.port, configData.func_enable, + configData.vlan_pri_table_num, + configData.vlan_pri_table_value); + } + break; + + case ESW_SET_PIRORITY_IP: + { + struct eswIoctlPriorityIPConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPriorityIPConfig)); + if (ret) + return -EFAULT; + + ret = esw_framecalssify_ip_priority_lookup(fep, + configData.port, configData.func_enable, + configData.ipv4_en, configData.ip_priority_num, + configData.ip_priority_value); + } + break; + + case ESW_SET_PIRORITY_MAC: + { + struct eswIoctlPriorityMacConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlPriorityMacConfig)); + if (ret) + return -EFAULT; + + ret = esw_framecalssify_mac_priority_lookup(fep, + configData.port); + } + break; + + case ESW_SET_PIRORITY_DEFAULT: + { + struct eswIoctlPriorityDefaultConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlPriorityDefaultConfig)); + if (ret) + return -EFAULT; + + ret = esw_frame_calssify_priority_init(fep, + configData.port, configData.priority_value); + } + break; + + case ESW_SET_P0_FORCED_FORWARD: + { + struct eswIoctlP0ForcedForwardConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlP0ForcedForwardConfig)); + if (ret) + return -EFAULT; + + ret = esw_forced_forward(fep, configData.port1, + configData.port2, configData.enable); + } + break; + + case ESW_SET_BRIDGE_CONFIG: + { + unsigned long configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(unsigned long)); + if (ret) + return -EFAULT; + + esw_bridge_port_configure(fep, configData); + } + break; + + case ESW_SET_SWITCH_MODE: + { + unsigned long configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(unsigned long)); + if (ret) + return -EFAULT; + + esw_switch_mode_configure(fep, configData); + } + break; + + case ESW_SET_OUTPUT_QUEUE_MEMORY: + { + struct eswIoctlOutputQueue configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlOutputQueue)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "ESW_SET_OUTPUT_QUEUE_MEMORY:: %#x \n" + "%#lx %#lx %#lx %#lx\n" + "%#lx %#lx %#lx\n", + configData.fun_num, + configData.sOutputQueue.ESW_MMSR, + configData.sOutputQueue.ESW_LMT, + configData.sOutputQueue.ESW_LFC, + configData.sOutputQueue.ESW_PCSR, + configData.sOutputQueue.ESW_IOSR, + configData.sOutputQueue.ESW_QWT, + configData.sOutputQueue.ESW_P0BCT); + ret = esw_set_output_queue_memory(fep, + configData.fun_num, &configData.sOutputQueue); + } + break; + + case ESW_SET_VLAN_OUTPUT_PROCESS: + { + struct eswIoctlVlanOutputConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlVlanOutputConfig)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "ESW_SET_VLAN_OUTPUT_PROCESS: %x %x\n", + configData.port, configData.mode); + ret = esw_vlan_output_process(fep, + configData.port, configData.mode); + } + break; + + case ESW_SET_VLAN_INPUT_PROCESS: + { + struct eswIoctlVlanInputConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlVlanInputConfig)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "ESW_SET_VLAN_INPUT_PROCESS: %x %x" + "%x %x %x %x\n", + configData.port, configData.mode, + configData.port_vlanid, + configData.vlan_verify_en, + configData.vlan_domain_num, + configData.vlan_domain_port); + ret = esw_vlan_input_process(fep, configData.port, + configData.mode, configData.port_vlanid, + configData.vlan_verify_en, + configData.vlan_domain_num, + configData.vlan_domain_port); + } + break; + + case ESW_SET_VLAN_DOMAIN_VERIFICATION: + { + struct eswIoctlVlanVerificationConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlVlanVerificationConfig)); + if (ret) + return -EFAULT; + + printk("ESW_SET_VLAN_DOMAIN_VERIFICATION: " + "%x %x %x\n", + configData.port, + configData.vlan_domain_verify_en, + configData.vlan_discard_unknown_en); + ret = esw_set_vlan_verification( + fep, configData.port, + configData.vlan_domain_verify_en, + configData.vlan_discard_unknown_en); + } + break; + + case ESW_SET_VLAN_RESOLUTION_TABLE: + { + struct eswIoctlVlanResoultionTable configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlVlanResoultionTable)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "ESW_SET_VLAN_RESOLUTION_TABLE: " + "%x %x %x\n", + configData.port_vlanid, + configData.vlan_domain_num, + configData.vlan_domain_port); + + ret = esw_set_vlan_resolution_table( + fep, configData.port_vlanid, + configData.vlan_domain_num, + configData.vlan_domain_port); + + } + break; + case ESW_UPDATE_STATIC_MACTABLE: + { + struct eswIoctlUpdateStaticMACtable configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlUpdateStaticMACtable)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "%s: ESW_UPDATE_STATIC_MACTABLE: mac %s, " + "port %x, priority %x\n", __func__, + configData.mac_addr, + configData.port, + configData.priority); + ret = esw_update_atable_static(configData.mac_addr, + configData.port, configData.priority, fep); + } + break; + + case ESW_CLEAR_ALL_MACTABLE: + { + esw_clear_atable(fep); + } + break; + + case ESW_GET_STATISTICS_STATUS: + { + struct esw_statistics_status Statistics; + ret = esw_get_statistics_status(fep, &Statistics); + if (ret != 0) { + printk(KERN_ERR "%s: cmd %x fail\n", + __func__, cmd); + return -1; + } + + ret = copy_to_user(ifr->ifr_data, &Statistics, + sizeof(struct esw_statistics_status)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORT0_STATISTICS_STATUS: + { + struct esw_port_statistics_status PortStatistics; + + ret = esw_get_port_statistics_status(fep, + 0, &PortStatistics); + if (ret != 0) { + printk(KERN_ERR "%s: cmd %x fail\n", + __func__, cmd); + return -1; + } + + ret = copy_to_user(ifr->ifr_data, &PortStatistics, + sizeof(struct esw_port_statistics_status)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORT1_STATISTICS_STATUS: + { + struct esw_port_statistics_status PortStatistics; + + ret = esw_get_port_statistics_status(fep, + 1, &PortStatistics); + if (ret != 0) { + printk(KERN_ERR "%s: cmd %x fail\n", + __func__, cmd); + return -1; + } + + ret = copy_to_user(ifr->ifr_data, &PortStatistics, + sizeof(struct esw_port_statistics_status)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORT2_STATISTICS_STATUS: + { + struct esw_port_statistics_status PortStatistics; + + ret = esw_get_port_statistics_status(fep, + 2, &PortStatistics); + if (ret != 0) { + printk(KERN_ERR "%s: cmd %x fail\n", + __func__, cmd); + return -1; + } + + ret = copy_to_user(ifr->ifr_data, &PortStatistics, + sizeof(struct esw_port_statistics_status)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_LEARNING_CONF: + { + unsigned long PortLearning; + + esw_get_port_learning(fep, &PortLearning); + ret = copy_to_user(ifr->ifr_data, &PortLearning, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_BLOCKING_CONF: + { + unsigned long PortBlocking; + + esw_get_port_blocking(fep, &PortBlocking); + ret = copy_to_user(ifr->ifr_data, &PortBlocking, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_MULTICAST_CONF: + { + unsigned long PortMulticast; + + esw_get_port_multicast(fep, &PortMulticast); + ret = copy_to_user(ifr->ifr_data, &PortMulticast, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_BROADCAST_CONF: + { + unsigned long PortBroadcast; + + esw_get_port_broadcast(fep, &PortBroadcast); + ret = copy_to_user(ifr->ifr_data, &PortBroadcast, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORTENABLE_CONF: + { + unsigned long PortEnable; + + esw_get_port_enable(fep, &PortEnable); + ret = copy_to_user(ifr->ifr_data, &PortEnable, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_IP_SNOOP_CONF: + { + unsigned long ESW_IPSNP[8]; + + esw_get_ip_snoop_config(fep, (unsigned long *)ESW_IPSNP); + ret = copy_to_user(ifr->ifr_data, ESW_IPSNP, + (8 * sizeof(unsigned long))); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORT_SNOOP_CONF: + { + unsigned long ESW_PSNP[8]; + + esw_get_tcpudp_port_snoop_config(fep, + (unsigned long *)ESW_PSNP); + ret = copy_to_user(ifr->ifr_data, ESW_PSNP, + (8 * sizeof(unsigned long))); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORT_MIRROR_CONF: + { + struct eswIoctlPortMirrorStatus PortMirrorStatus; + + esw_get_port_mirroring(fep, &PortMirrorStatus); + ret = copy_to_user(ifr->ifr_data, &PortMirrorStatus, + sizeof(struct eswIoctlPortMirrorStatus)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_P0_FORCED_FORWARD: + { + unsigned long ForceForward; + + esw_get_forced_forward(fep, &ForceForward); + ret = copy_to_user(ifr->ifr_data, &ForceForward, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_SWITCH_MODE: + { + unsigned long Config; + + esw_get_switch_mode(fep, &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_BRIDGE_CONFIG: + { + unsigned long Config; + + esw_get_bridge_port(fep, &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + case ESW_GET_OUTPUT_QUEUE_STATUS: + { + struct esw_output_queue_status Config; + esw_get_output_queue_status(fep, + &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(struct esw_output_queue_status)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_VLAN_OUTPUT_PROCESS: + { + unsigned long Config; + + esw_get_vlan_output_config(fep, &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_VLAN_INPUT_PROCESS: + { + struct eswIoctlVlanInputStatus Config; + + esw_get_vlan_input_config(fep, &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(struct eswIoctlVlanInputStatus)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_VLAN_RESOLUTION_TABLE: + { + unsigned long Config; + unsigned char ConfigData; + ret = copy_from_user(&ConfigData, + ifr->ifr_data, + sizeof(unsigned char)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "ESW_GET_VLAN_RESOLUTION_TABLE: %x \n", + ConfigData); + + esw_get_vlan_resolution_table(fep, ConfigData, &Config); + + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_VLAN_DOMAIN_VERIFICATION: + { + unsigned long Config; + + esw_get_vlan_verification(fep, &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + /*------------------------------------------------------------------*/ + default: + return -EOPNOTSUPP; + } + + + return ret; +} + +static int +switch_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct switch_enet_private *fep; + struct switch_t *fecp; + struct cbd_t *bdp; + void *bufaddr; + unsigned short status; + unsigned long flags; + + fep = netdev_priv(dev); + fecp = (struct switch_t *)fep->hwp; + + spin_lock_irqsave(&fep->hw_lock, flags); + /* Fill in a Tx ring entry */ + bdp = fep->cur_tx; + + status = bdp->cbd_sc; + + if (status & BD_ENET_TX_READY) { + /* + * Ooops. All transmit buffers are full. Bail out. + * This should not happen, since dev->tbusy should be set. + */ + printk(KERN_ERR "%s: tx queue full!.\n", dev->name); + spin_unlock_irqrestore(&fep->hw_lock, flags); + return NETDEV_TX_BUSY; + } + + /* Clear all of the status flags */ + status &= ~BD_ENET_TX_STATS; + + /* Set buffer length and buffer pointer */ + bufaddr = skb->data; + bdp->cbd_datlen = skb->len; + + /* + * On some FEC implementations data must be aligned on + * 4-byte boundaries. Use bounce buffers to copy data + * and get it aligned. Ugh. + */ + if ((unsigned long) bufaddr & FEC_ALIGNMENT) { + unsigned int index; + index = bdp - fep->tx_bd_base; + memcpy(fep->tx_bounce[index], + (void *)skb->data, skb->len); + bufaddr = fep->tx_bounce[index]; + } + +#ifdef CONFIG_ARCH_MXS + swap_buffer(bufaddr, skb->len); +#endif + + /* Save skb pointer. */ + fep->tx_skbuff[fep->skb_cur] = skb; + + dev->stats.tx_bytes += skb->len; + fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; + + /* + * Push the data cache so the CPM does not get stale memory + * data. + */ + bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr, + FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); + + /* + * Send it on its way. Tell FEC it's ready, interrupt when done, + * it's the last BD of the frame, and to put the CRC on the end. + */ + + status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR + | BD_ENET_TX_LAST | BD_ENET_TX_TC); + bdp->cbd_sc = status; +#ifdef L2SWITCH_ENHANCED_BUFFER + bdp->bdu = 0x00000000; + bdp->ebd_status = TX_BD_INT | TX_BD_TS; +#endif + dev->trans_start = jiffies; + + /* Trigger transmission start */ + fecp->fec_x_des_active = MCF_ESW_TDAR_X_DES_ACTIVE; + + /* If this was the last BD in the ring, + * start at the beginning again. + */ + if (status & BD_ENET_TX_WRAP) + bdp = fep->tx_bd_base; + else + bdp++; + + if (bdp == fep->dirty_tx) { + fep->tx_full = 1; + netif_stop_queue(dev); + printk(KERN_ERR "%s: net stop\n", __func__); + } + + fep->cur_tx = bdp; + + spin_unlock_irqrestore(&fep->hw_lock, flags); + + return 0; +} + +static void +switch_timeout(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + + printk(KERN_INFO "%s: transmit timed out.\n", dev->name); + dev->stats.tx_errors++; + { + int i; + struct cbd_t *bdp; + + printk(KERN_INFO "Ring data dump: cur_tx %lx%s," + "dirty_tx %lx cur_rx: %lx\n", + (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "", + (unsigned long)fep->dirty_tx, + (unsigned long)fep->cur_rx); + + bdp = fep->tx_bd_base; + printk(KERN_INFO " tx: %u buffers\n", TX_RING_SIZE); + for (i = 0 ; i < TX_RING_SIZE; i++) { + printk(KERN_INFO " %08x: %04x %04x %08x\n", + (uint) bdp, + bdp->cbd_sc, + bdp->cbd_datlen, + (int) bdp->cbd_bufaddr); + bdp++; + } + + bdp = fep->rx_bd_base; + printk(KERN_INFO " rx: %lu buffers\n", + (unsigned long) RX_RING_SIZE); + for (i = 0 ; i < RX_RING_SIZE; i++) { + printk(KERN_INFO " %08x: %04x %04x %08x\n", + (uint) bdp, + bdp->cbd_sc, + bdp->cbd_datlen, + (int) bdp->cbd_bufaddr); + bdp++; + } + } + switch_restart(dev, fep->full_duplex); + netif_wake_queue(dev); +} + +/* + * The interrupt handler. + * This is called from the MPC core interrupt. + */ +static irqreturn_t +switch_enet_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct switch_enet_private *fep = netdev_priv(dev); + struct switch_t *fecp; + uint int_events; + irqreturn_t ret = IRQ_NONE; + + fecp = (struct switch_t *)dev->base_addr; + + /* Get the interrupt events that caused us to be here */ + do { + int_events = fecp->switch_ievent; + fecp->switch_ievent = int_events; + /* Handle receive event in its own function. */ + + /* Transmit OK, or non-fatal error. Update the buffer + * descriptors. FEC handles all errors, we just discover + * them as part of the transmit process. + */ + if (int_events & MCF_ESW_ISR_LRN) { + if (fep->learning_irqhandle_enable) + esw_atable_dynamicms_learn_migration( + fep, fep->currTime); + ret = IRQ_HANDLED; + } + + if (int_events & MCF_ESW_ISR_OD0) + ret = IRQ_HANDLED; + + if (int_events & MCF_ESW_ISR_OD1) + ret = IRQ_HANDLED; + + if (int_events & MCF_ESW_ISR_OD2) + ret = IRQ_HANDLED; + + if (int_events & MCF_ESW_ISR_RXB) + ret = IRQ_HANDLED; + + if (int_events & MCF_ESW_ISR_RXF) { + ret = IRQ_HANDLED; + switch_enet_rx(dev); + } + + if (int_events & MCF_ESW_ISR_TXB) + ret = IRQ_HANDLED; + + if (int_events & MCF_ESW_ISR_TXF) { + ret = IRQ_HANDLED; + switch_enet_tx(dev); + } + + } while (int_events); + + return ret; +} + + +static void +switch_enet_tx(struct net_device *dev) +{ + struct switch_enet_private *fep; + struct cbd_t *bdp; + unsigned short status; + struct sk_buff *skb; + + fep = netdev_priv(dev); + spin_lock(&fep->hw_lock); + bdp = fep->dirty_tx; + + while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { + if (bdp == fep->cur_tx && fep->tx_full == 0) + break; + + dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, + FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); + bdp->cbd_bufaddr = 0; + skb = fep->tx_skbuff[fep->skb_dirty]; + /* Check for errors */ + if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | + BD_ENET_TX_RL | BD_ENET_TX_UN | + BD_ENET_TX_CSL)) { + dev->stats.tx_errors++; + if (status & BD_ENET_TX_HB) /* No heartbeat */ + dev->stats.tx_heartbeat_errors++; + if (status & BD_ENET_TX_LC) /* Late collision */ + dev->stats.tx_window_errors++; + if (status & BD_ENET_TX_RL) /* Retrans limit */ + dev->stats.tx_aborted_errors++; + if (status & BD_ENET_TX_UN) /* Underrun */ + dev->stats.tx_fifo_errors++; + if (status & BD_ENET_TX_CSL) /* Carrier lost */ + dev->stats.tx_carrier_errors++; + } else { + dev->stats.tx_packets++; + } + + if (status & BD_ENET_TX_READY) + printk(KERN_ERR "HEY! " + "Enet xmit interrupt and TX_READY.\n"); + /* + * Deferred means some collisions occurred during transmit, + * but we eventually sent the packet OK. + */ + if (status & BD_ENET_TX_DEF) + dev->stats.collisions++; + + /* Free the sk buffer associated with this last transmit */ + dev_kfree_skb_any(skb); + fep->tx_skbuff[fep->skb_dirty] = NULL; + fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; + + /* Update pointer to next buffer descriptor to be transmitted */ + if (status & BD_ENET_TX_WRAP) + bdp = fep->tx_bd_base; + else + bdp++; + + /* + * Since we have freed up a buffer, the ring is no longer + * full. + */ + if (fep->tx_full) { + fep->tx_full = 0; + printk(KERN_ERR "%s: tx full is zero\n", __func__); + if (netif_queue_stopped(dev)) + netif_wake_queue(dev); + } + } + fep->dirty_tx = bdp; + spin_unlock(&fep->hw_lock); +} + + +/* + * During a receive, the cur_rx points to the current incoming buffer. + * When we update through the ring, if the next incoming buffer has + * not been given to the system, we just set the empty indicator, + * effectively tossing the packet. + */ +static void +switch_enet_rx(struct net_device *dev) +{ + struct switch_enet_private *fep; + struct switch_t *fecp; + struct cbd_t *bdp; + unsigned short status; + struct sk_buff *skb; + ushort pkt_len; + __u8 *data; + +#ifdef CONFIG_M532x + flush_cache_all(); +#endif + + fep = netdev_priv(dev); + fecp = (struct switch_t *)fep->hwp; + + spin_lock(&fep->hw_lock); + /* + * First, grab all of the stats for the incoming packet. + * These get messed up if we get called due to a busy condition. + */ + bdp = fep->cur_rx; +#ifdef L2SWITCH_ENHANCED_BUFFER + printk(KERN_INFO "%s: cbd_sc %x cbd_datlen %x cbd_bufaddr %x " + "ebd_status %x bdu %x length_proto_type %x " + "payload_checksum %x\n", + __func__, bdp->cbd_sc, bdp->cbd_datlen, + bdp->cbd_bufaddr, bdp->ebd_status, bdp->bdu, + bdp->length_proto_type, bdp->payload_checksum); +#endif + +while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { + /* + * Since we have allocated space to hold a complete frame, + * the last indicator should be set. + */ + if ((status & BD_ENET_RX_LAST) == 0) + printk(KERN_INFO "SWITCH ENET: rcv is not +last\n"); + + if (!fep->opened) + goto rx_processing_done; + + /* Check for errors. */ + if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | + BD_ENET_RX_CR | BD_ENET_RX_OV)) { + dev->stats.rx_errors++; + if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { + /* Frame too long or too short. */ + dev->stats.rx_length_errors++; + } + if (status & BD_ENET_RX_NO) /* Frame alignment */ + dev->stats.rx_frame_errors++; + if (status & BD_ENET_RX_CR) /* CRC Error */ + dev->stats.rx_crc_errors++; + if (status & BD_ENET_RX_OV) /* FIFO overrun */ + dev->stats.rx_fifo_errors++; + } + + /* + * Report late collisions as a frame error. + * On this error, the BD is closed, but we don't know what we + * have in the buffer. So, just drop this frame on the floor. + */ + if (status & BD_ENET_RX_CL) { + dev->stats.rx_errors++; + dev->stats.rx_frame_errors++; + goto rx_processing_done; + } + + /* Process the incoming frame */ + dev->stats.rx_packets++; + pkt_len = bdp->cbd_datlen; + dev->stats.rx_bytes += pkt_len; + data = (__u8 *)__va(bdp->cbd_bufaddr); + + dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen, + DMA_FROM_DEVICE); +#ifdef CONFIG_ARCH_MXS + swap_buffer(data, pkt_len); +#endif + /* + * This does 16 byte alignment, exactly what we need. + * The packet length includes FCS, but we don't want to + * include that when passing upstream as it messes up + * bridging applications. + */ + skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN); + if (unlikely(!skb)) { + printk("%s: Memory squeeze, dropping packet.\n", + dev->name); + dev->stats.rx_dropped++; + } else { + skb_reserve(skb, NET_IP_ALIGN); + skb_put(skb, pkt_len - 4); /* Make room */ + skb_copy_to_linear_data(skb, data, pkt_len - 4); + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + } + + bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen, + DMA_FROM_DEVICE); + +rx_processing_done: + + /* Clear the status flags for this buffer */ + status &= ~BD_ENET_RX_STATS; + + /* Mark the buffer empty */ + status |= BD_ENET_RX_EMPTY; + bdp->cbd_sc = status; + + /* Update BD pointer to next entry */ + if (status & BD_ENET_RX_WRAP) + bdp = fep->rx_bd_base; + else + bdp++; + + /* + * Doing this here will keep the FEC running while we process + * incoming frames. On a heavily loaded network, we should be + * able to keep up at the expense of system resources. + */ + fecp->fec_r_des_active = MCF_ESW_RDAR_R_DES_ACTIVE; + } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */ + fep->cur_rx = bdp; + + spin_unlock(&fep->hw_lock); +} + +#ifdef FEC_PHY +static int fec_mdio_transfer(struct mii_bus *bus, int phy_id, + int reg, int regval) +{ + struct net_device *dev = bus->priv; + unsigned long flags; + struct switch_enet_private *fep; + int tries = 100; + int retval = 0; + + fep = netdev_priv(dev); + spin_lock_irqsave(&fep->mii_lock, flags); + + regval |= phy_id << 23; + writel(regval, fep->enet_addr + MCF_FEC_MMFR0); + + /* wait for it to finish, this takes about 23 us on lite5200b */ + while (!(readl(fep->enet_addr + MCF_FEC_EIR0) & FEC_ENET_MII) + && --tries) + udelay(5); + + if (!tries) { + printk(KERN_ERR "%s timeout\n", __func__); + return -ETIMEDOUT; + } + + writel(FEC_ENET_MII, fep->enet_addr + MCF_FEC_EIR0); + retval = readl(fep->enet_addr + MCF_FEC_MMFR0); + spin_unlock_irqrestore(&fep->mii_lock, flags); + + return retval; +} + +/* + * Phy section + */ +static void switch_adjust_link(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct phy_device *phy_dev = fep->phy_dev; + unsigned long flags; + int status_change = 0; + + phy_dev = g_phy_dev; + spin_lock_irqsave(&fep->hw_lock, flags); + + /* Prevent a state halted on mii error */ + if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { + phy_dev->state = PHY_RESUMING; + goto spin_unlock; + } + + /* Duplex link change */ + if (phy_dev->link) { + if (fep->full_duplex != phy_dev->duplex) { + switch_restart(dev, phy_dev->duplex); + status_change = 1; + } + } + + /* Link on or off change */ + if (phy_dev->link != fep->link) { + fep->link = phy_dev->link; + if (phy_dev->link) + switch_restart(dev, phy_dev->duplex); + else + switch_stop(dev); + status_change = 1; + } + +spin_unlock: + spin_unlock_irqrestore(&fep->hw_lock, flags); + + if (status_change) + phy_print_status(phy_dev); +} + +/* + * NOTE: a MII transaction is during around 25 us, so polling it... + */ +static int fec_enet_mdio_poll(struct switch_enet_private *fep) + { + int timeout = FEC_MII_TIMEOUT; + unsigned int reg = 0; + + fep->mii_timeout = 0; + + /* wait for end of transfer */ + reg = readl(fep->hwp + FEC_IEVENT); + while (!(reg & FEC_ENET_MII)) { + msleep(1); + if (timeout-- < 0) { + fep->mii_timeout = 1; + break; + } + } + + return 0; +} + +static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) +{ + struct switch_enet_private *fep = netdev_priv(bus->priv); + + + /* clear MII end of transfer bit */ + writel(FEC_ENET_MII, fep->enet_addr + FEC_IEVENT + / sizeof(unsigned long)); + + /* start a read op */ + writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | + FEC_MMFR_TA, fep->enet_addr + FEC_MII_DATA + / sizeof(unsigned long)); + + fec_enet_mdio_poll(fep); + + /* return value */ + return FEC_MMFR_DATA(readl(fep->enet_addr + FEC_MII_DATA + / sizeof(unsigned long))); +} + +static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, + u16 value) +{ + struct switch_enet_private *fep = netdev_priv(bus->priv); + + /* clear MII end of transfer bit */ + writel(FEC_ENET_MII, fep->enet_addr + FEC_IEVENT + / sizeof(unsigned long)); + + /* start a read op */ + writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | + FEC_MMFR_TA | FEC_MMFR_DATA(value), + fep->enet_addr + FEC_MII_DATA / sizeof(unsigned long)); + + fec_enet_mdio_poll(fep); + + return 0; +} + +static int fec_enet_mdio_reset(struct mii_bus *bus) +{ + return 0; +} + +static struct mii_bus *fec_enet_mii_init(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + int err = -ENXIO, i; + + fep->mii_timeout = 0; + /* + * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) + */ + fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1; +#ifdef CONFIG_ARCH_MXS + /* Can't get phy(8720) ID when set to 2.5M on MX28, lower it */ + fep->phy_speed <<= 2; +#endif + writel(fep->phy_speed, fep->enet_addr + FEC_MII_SPEED + / sizeof(unsigned long)); + + fep->mii_bus = mdiobus_alloc(); + if (fep->mii_bus == NULL) { + err = -ENOMEM; + goto err_out; + } + + fep->mii_bus->name = "fec_enet_mii_bus"; + fep->mii_bus->read = fec_enet_mdio_read; + fep->mii_bus->write = fec_enet_mdio_write; + fep->mii_bus->reset = fec_enet_mdio_reset; + snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", fep->pdev->id); + fep->mii_bus->priv = dev; + + fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); + if (!fep->mii_bus->irq) { + err = -ENOMEM; + goto err_out_free_mdiobus; + } + + for (i = 0; i < PHY_MAX_ADDR; i++) + fep->mii_bus->irq[i] = PHY_POLL; + + if (mdiobus_register(fep->mii_bus)) { + goto err_out_free_mdio_irq; + } + + return fep->mii_bus; + +err_out_free_mdio_irq: + kfree(fep->mii_bus->irq); +err_out_free_mdiobus: + mdiobus_free(fep->mii_bus); +err_out: + return ERR_PTR(err); +} +#endif + +static int fec_enet_get_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct phy_device *phydev = fep->phy_dev; + + if (!phydev) + return -ENODEV; + + return phy_ethtool_gset(phydev, cmd); +} + +static int fec_enet_set_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct phy_device *phydev = fep->phy_dev; + + if (!phydev) + return -ENODEV; + + return phy_ethtool_sset(phydev, cmd); +} + +static void fec_enet_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + struct switch_enet_private *fep = netdev_priv(dev); + + strcpy(info->driver, fep->pdev->dev.driver->name); + strcpy(info->version, "Revision: 1.0"); + strcpy(info->bus_info, dev_name(&dev->dev)); +} + +#ifdef FEC_PHY +static int fec_switch_init_phy(struct net_device *dev) +{ + struct switch_enet_private *priv = netdev_priv(dev); + struct phy_device *phydev = NULL; + int i; + + /* search for connect PHY device */ + for (i = 0; i < PHY_MAX_ADDR; i++) { + struct phy_device *const tmp_phydev = + priv->mdio_bus->phy_map[i]; + + if (!tmp_phydev) { +#ifdef FEC_DEBUG + printk(KERN_INFO "%s no PHY here at" + "mii_bus->phy_map[%d]\n", + __func__, i); +#endif + continue; /* no PHY here... */ + } + +#ifdef CONFIG_FEC_SHARED_PHY + if (priv->index == 0) + phydev = tmp_phydev; + else if (priv->index == 1) { + if (startnode == 1) { + phydev = tmp_phydev; + startnode = 0; + } else { + startnode++; + continue; + } + } else + printk(KERN_INFO "%s now we do not" + "support (%d) more than" + "2 phys shared " + "one mdio bus\n", + __func__, startnode); +#else + phydev = tmp_phydev; +#endif +#ifdef FEC_DEBUG + printk(KERN_INFO "%s find PHY here at" + "mii_bus->phy_map[%d]\n", + __func__, i); +#endif + break; /* found it */ + } + + /* now we are supposed to have a proper phydev, to attach to... */ + if (!phydev) { + printk(KERN_INFO "%s: Don't found any phy device at all\n", + dev->name); + return -ENODEV; + } + + priv->link = PHY_DOWN; + priv->old_link = PHY_DOWN; + priv->speed = 0; + priv->duplex = -1; + + phydev = phy_connect(dev, dev_name(&phydev->dev), + &switch_adjust_link, 0, PHY_INTERFACE_MODE_MII); + if (IS_ERR(phydev)) { + printk(KERN_ERR " %s phy_connect failed\n", __func__); + return PTR_ERR(phydev); + } + + printk(KERN_INFO "attached phy %i to driver %s\n", + phydev->addr, phydev->drv->name); + + priv->phydev = phydev; + g_phy_dev = phydev; + + return 0; +} +#endif + +static void fec_enet_free_buffers(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + int i; + struct sk_buff *skb; + struct cbd_t *bdp; + + bdp = fep->rx_bd_base; + for (i = 0; i < RX_RING_SIZE; i++) { + skb = fep->rx_skbuff[i]; + + if (bdp->cbd_bufaddr) + dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, + FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); + if (skb) + dev_kfree_skb(skb); + bdp++; + } + + bdp = fep->tx_bd_base; + for (i = 0; i < TX_RING_SIZE; i++) + kfree(fep->tx_bounce[i]); +} + +static int fec_enet_alloc_buffers(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + int i; + struct sk_buff *skb; + struct cbd_t *bdp; + + bdp = fep->rx_bd_base; + for (i = 0; i < RX_RING_SIZE; i++) { + skb = dev_alloc_skb(SWITCH_ENET_RX_FRSIZE); + if (!skb) { + fec_enet_free_buffers(dev); + return -ENOMEM; + } + fep->rx_skbuff[i] = skb; + + bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data, + SWITCH_ENET_RX_FRSIZE, DMA_FROM_DEVICE); + bdp->cbd_sc = BD_ENET_RX_EMPTY; +#ifdef L2SWITCH_ENHANCED_BUFFER + bdp->bdu = 0x00000000; + bdp->ebd_status = RX_BD_INT; +#endif +#ifdef CONFIG_FEC_1588 + bdp->cbd_esc = BD_ENET_RX_INT; +#endif + bdp++; + } + + /* Set the last buffer to wrap. */ + bdp--; + bdp->cbd_sc |= BD_SC_WRAP; + + bdp = fep->tx_bd_base; + for (i = 0; i < TX_RING_SIZE; i++) { + fep->tx_bounce[i] = kmalloc(SWITCH_ENET_TX_FRSIZE, GFP_KERNEL); + + bdp->cbd_sc = 0; + bdp->cbd_bufaddr = 0; +#ifdef CONFIG_FEC_1588 + bdp->cbd_esc = BD_ENET_TX_INT; +#endif + bdp++; + } + + /* Set the last buffer to wrap. */ + bdp--; + bdp->cbd_sc |= BD_SC_WRAP; + + return 0; +} + +static int +switch_enet_open(struct net_device *dev) +{ + int ret; + struct switch_enet_private *fep = netdev_priv(dev); + /* I should reset the ring buffers here, but I don't yet know + * a simple way to do that. + */ + clk_enable(fep->clk); + ret = fec_enet_alloc_buffers(dev); + if (ret) + return ret; + + fep->link = 0; +#ifdef FEC_PHY + clk_enable(fep->clk); + fec_switch_init_phy(dev); + phy_start(fep->phydev); +#endif + fep->old_link = 0; + if (fep->phydev) { + /* + * Set the initial link state to true. A lot of hardware + * based on this device does not implement a PHY interrupt, + * so we are never notified of link change. + */ + fep->link = 1; + } else { + fep->link = 1; + /* no phy, go full duplex, it's most likely a hub chip */ + switch_restart(dev, 1); + } + + /* + * if the fec is the fist open, we need to do nothing + * if the fec is not the fist open, we need to restart the FEC + */ + if (fep->sequence_done == 0) + switch_restart(dev, 1); + else + fep->sequence_done = 0; + + fep->currTime = 0; + fep->learning_irqhandle_enable = 0; + + esw_main(fep); + + netif_start_queue(dev); + fep->opened = 1; + + return 0; /* Success */ +} + +static int +switch_enet_close(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + + fep->opened = 0; + netif_stop_queue(dev); + switch_stop(dev); +#ifdef FEC_PHY + phy_disconnect(fep->phydev); + phy_stop(fep->phydev); + phy_write(fep->phydev, MII_BMCR, BMCR_PDOWN); +#endif + fec_enet_free_buffers(dev); + clk_disable(fep->clk); + + return 0; +} + +/* + * Set or clear the multicast filter for this adaptor. + * Skeleton taken from sunlance driver. + * The CPM Ethernet implementation allows Multicast as well as individual + * MAC address filtering. Some of the drivers check to make sure it is + * a group multicast address, and discard those that are not. I guess I + * will do the same for now, but just remove the test if you want + * individual filtering as well (do the upper net layers want or support + * this kind of feature?). + */ + +/* bits in hash */ +#define HASH_BITS 6 +#define CRC32_POLY 0xEDB88320 + +static void set_multicast_list(struct net_device *dev) +{ + struct switch_enet_private *fep; + struct switch_t *ep; + struct dev_mc_list *dmi; + unsigned int i, j, bit, data, crc; + + fep = netdev_priv(dev); + ep = fep->hwp; + + if (dev->flags & IFF_PROMISC) { + /* ep->fec_r_cntrl |= 0x0008; */ + printk(KERN_INFO "%s IFF_PROMISC\n", __func__); + } else { + + /* ep->fec_r_cntrl &= ~0x0008; */ + + if (dev->flags & IFF_ALLMULTI) { + /* + * Catch all multicast addresses, so set the + * filter to all 1's. + */ + printk(KERN_INFO "%s IFF_ALLMULTI\n", __func__); + } else { + /* + * Clear filter and add the addresses + * in hash register + */ + /* + * ep->fec_grp_hash_table_high = 0; + * ep->fec_grp_hash_table_low = 0; + */ + + dmi = dev->mc_list; + + for (j = 0; j < dev->mc_count; + j++, dmi = dmi->next) { + /* Only support group multicast for now */ + if (!(dmi->dmi_addr[0] & 1)) + continue; + + /* calculate crc32 value of mac address */ + crc = 0xffffffff; + + for (i = 0; i < dmi->dmi_addrlen; i++) { + data = dmi->dmi_addr[i]; + for (bit = 0; bit < 8; bit++, + data >>= 1) { + crc = (crc >> 1) ^ + (((crc ^ data) & 1) ? + CRC32_POLY : 0); + } + } + + } + } + } +} + +/* Set a MAC change in hardware */ +static int +switch_set_mac_address(struct net_device *dev, void *p) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct sockaddr *addr = p; + struct switch_t *fecp; + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + fecp = fep->hwp; + fecp->ESW_DBCR = MCF_ESW_DBCR_P1; + + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); + + writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | + (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), + fep->enet_addr + MCF_FEC_PAUR0); + writel((dev->dev_addr[5] << 16) + | ((dev->dev_addr[4]+(unsigned char)(0)) << 24), + fep->enet_addr + MCF_FEC_PAUR0); + + writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | + (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), + fep->enet_addr + MCF_FEC_PAUR1); + writel((dev->dev_addr[5] << 16) + | ((dev->dev_addr[4]+(unsigned char)(1)) << 24), + fep->enet_addr + MCF_FEC_PAUR1); + + esw_update_atable_static(dev->dev_addr, 7, 7, fep); + fecp->ESW_DBCR = MCF_ESW_DBCR_P1 | MCF_ESW_DBCR_P2; + + return 0; +} + +static struct ethtool_ops fec_enet_ethtool_ops = { + .get_settings = fec_enet_get_settings, + .set_settings = fec_enet_set_settings, + .get_drvinfo = fec_enet_get_drvinfo, + .get_link = ethtool_op_get_link, + }; +static const struct net_device_ops fec_netdev_ops = { + .ndo_open = switch_enet_open, + .ndo_stop = switch_enet_close, + .ndo_do_ioctl = switch_enet_ioctl, + .ndo_start_xmit = switch_enet_start_xmit, + .ndo_set_multicast_list = set_multicast_list, + .ndo_tx_timeout = switch_timeout, + .ndo_set_mac_address = switch_set_mac_address, +}; + +static int switch_mac_addr_setup(char *mac_addr) +{ + char *ptr, *p = mac_addr; + unsigned long tmp; + int i = 0, ret = 0; + + while (p && (*p) && i < 6) { + ptr = strchr(p, ':'); + if (ptr) + *ptr++ = '\0'; + if (strlen(p)) { + ret = strict_strtoul(p, 16, &tmp); + if (ret < 0 || tmp > 0xff) + break; + switch_mac_default[i++] = tmp; + } + p = ptr; + } + + return 0; +} + +__setup("fec_mac=", switch_mac_addr_setup); + +/* Initialize the FEC Ethernet */ +static int __init switch_enet_init(struct net_device *dev, + int slot, struct platform_device *pdev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct resource *r; + struct cbd_t *bdp; + struct cbd_t *cbd_base; + struct switch_t *fecp; + int i; + struct switch_platform_data *plat = pdev->dev.platform_data; + + /* Only allow us to be probed once. */ + if (slot >= SWITCH_MAX_PORTS) + return -ENXIO; + + /* Allocate memory for buffer descriptors */ + cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, + GFP_KERNEL); + if (!cbd_base) { + printk(KERN_ERR "FEC: allocate descriptor memory failed?\n"); + return -ENOMEM; + } + + spin_lock_init(&fep->hw_lock); + spin_lock_init(&fep->mii_lock); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) + return -ENXIO; + + r = request_mem_region(r->start, resource_size(r), pdev->name); + if (!r) + return -EBUSY; + + fep->enet_addr = ioremap(r->start, resource_size(r)); + + dev->irq = platform_get_irq(pdev, 0); + + /* + * Create an Ethernet device instance. + * The switch lookup address memory start 0x800FC000 + */ + fecp = (struct switch_t *)(fep->enet_addr + ENET_SWI_PHYS_ADDR_OFFSET + / sizeof(unsigned long)); + plat->switch_hw[1] = (unsigned long)fecp + MCF_ESW_LOOKUP_MEM_OFFSET; + + fep->index = slot; + fep->hwp = fecp; + fep->hwentry = (struct eswAddrTable_t *)plat->switch_hw[1]; + fep->netdev = dev; +#ifdef CONFIG_FEC_SHARED_PHY + fep->phy_hwp = (struct switch_t *) plat->switch_hw[slot & ~1]; +#else + fep->phy_hwp = fecp; +#endif + + fep->clk = clk_get(&pdev->dev, "fec_clk"); + if (IS_ERR(fep->clk)) + return PTR_ERR(fep->clk); + clk_enable(fep->clk); + + + /* PHY reset should be done during clock on */ + if (plat) { + fep->phy_interface = plat->fec_enet->phy; + if (plat->fec_enet->init && plat->fec_enet->init()) + return -EIO; + + /* + * The priority for getting MAC address is: + * (1) kernel command line fec_mac = xx:xx:xx... + * (2) platform data mac field got from fuse etc + * (3) bootloader set the FEC mac register + */ + + if (!is_valid_ether_addr(switch_mac_default) && + plat->fec_enet->mac && + is_valid_ether_addr(plat->fec_enet->mac)) + memcpy(switch_mac_default, plat->fec_enet->mac, + sizeof(switch_mac_default)); + } else + fep->phy_interface = PHY_INTERFACE_MODE_MII; + + /* + * SWITCH CONFIGURATION + */ + fecp->ESW_MODE = MCF_ESW_MODE_SW_RST; + udelay(10); + + /* enable switch*/ + fecp->ESW_MODE = MCF_ESW_MODE_STATRST; + fecp->ESW_MODE = MCF_ESW_MODE_SW_EN; + + /* Enable transmit/receive on all ports */ + fecp->ESW_PER = 0xffffffff; + /* Management port configuration, + * make port 0 as management port + */ + fecp->ESW_BMPC = 0; + + /* clear all switch irq */ + fecp->switch_ievent = 0xffffffff; + fecp->switch_imask = 0; + udelay(10); + + plat->request_intrs = switch_request_intrs; + plat->set_mii = switch_set_mii; + plat->get_mac = switch_get_mac; + plat->enable_phy_intr = switch_enable_phy_intr; + plat->disable_phy_intr = switch_disable_phy_intr; + plat->phy_ack_intr = switch_phy_ack_intr; + plat->localhw_setup = switch_localhw_setup; + plat->uncache = switch_uncache; + plat->platform_flush_cache = switch_platform_flush_cache; + + /* + * Set the Ethernet address. If using multiple Enets on the 8xx, + * this needs some work to get unique addresses. + * + * This is our default MAC address unless the user changes + * it via eth_mac_addr (our dev->set_mac_addr handler). + */ + if (plat && plat->get_mac) + plat->get_mac(dev); + + /* Set receive and transmit descriptor base */ + fep->rx_bd_base = cbd_base; + fep->tx_bd_base = cbd_base + RX_RING_SIZE; + + /* Initialize the receive buffer descriptors */ + bdp = fep->rx_bd_base; + for (i = 0; i < RX_RING_SIZE; i++) { + bdp->cbd_sc = 0; + +#ifdef L2SWITCH_ENHANCED_BUFFER + bdp->bdu = 0x00000000; + bdp->ebd_status = RX_BD_INT; +#endif + bdp++; + } + + /* Set the last buffer to wrap */ + bdp--; + bdp->cbd_sc |= BD_SC_WRAP; + + /* ...and the same for transmmit */ + bdp = fep->tx_bd_base; + for (i = 0; i < TX_RING_SIZE; i++) { + /* Initialize the BD for every fragment in the page */ + bdp->cbd_sc = 0; + bdp->cbd_bufaddr = 0; + bdp++; + } + + /* Set the last buffer to wrap */ + bdp--; + bdp->cbd_sc |= BD_SC_WRAP; + + /* + * Install our interrupt handlers. This varies depending on + * the architecture. + */ + if (plat && plat->request_intrs) + plat->request_intrs(dev, switch_enet_interrupt, dev); + + dev->base_addr = (unsigned long)fecp; + + /* The FEC Ethernet specific entries in the device structure. */ + dev->netdev_ops = &fec_netdev_ops; + dev->ethtool_ops = &fec_enet_ethtool_ops; + + /* setup MII interface */ + if (plat && plat->set_mii) + plat->set_mii(dev); + + +#ifndef CONFIG_FEC_SHARED_PHY + fep->phy_addr = 0; +#else + fep->phy_addr = fep->index; +#endif + + fep->sequence_done = 1; + return 0; +} + +static void enet_reset(struct net_device *dev, int duplex) +{ + struct switch_enet_private *fep = netdev_priv(dev); + + /* ECR */ +#ifdef L2SWITCH_ENHANCED_BUFFER + writel(MCF_FEC_ECR_ENA_1588 + | MCF_FEC_ECR_MAGIC_ENA, + fep->enet_addr + MCF_FEC_ECR0); + writel(MCF_FEC_ECR_ENA_1588, + | MCF_FEC_ECR_MAGIC_ENA, + fep->enet_addr + MCF_FEC_ECR1); +#else /*legac buffer*/ + writel(MCF_FEC_ECR_MAGIC_ENA, + fep->enet_addr + MCF_FEC_ECR0); + writel(MCF_FEC_ECR_MAGIC_ENA, + fep->enet_addr + MCF_FEC_ECR1); +#endif + /* EMRBR */ + writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR0); + writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR1); + + /* + * set the receive and transmit BDs ring base to + * hardware registers(ERDSR & ETDSR) + */ + writel(fep->bd_dma, fep->enet_addr + MCF_FEC_ERDSR0); + writel(fep->bd_dma, fep->enet_addr + MCF_FEC_ERDSR1); + writel((unsigned long)fep->bd_dma + sizeof(struct cbd_t) * RX_RING_SIZE, + fep->enet_addr + MCF_FEC_ETDSR0); + writel((unsigned long)fep->bd_dma + sizeof(struct cbd_t) * RX_RING_SIZE, + fep->enet_addr + MCF_FEC_ETDSR1); +#ifdef CONFIG_ARCH_MXS + /* Can't get phy(8720) ID when set to 2.5M on MX28, lower it */ + writel(fep->phy_speed, + fep->enet_addr + MCF_FEC_MSCR0); + writel(fep->phy_speed, + fep->enet_addr + MCF_FEC_MSCR1); +#endif + fep->full_duplex = duplex; + + /* EIR */ + writel(0, fep->enet_addr + MCF_FEC_EIR0); + writel(0, fep->enet_addr + MCF_FEC_EIR1); + + /* IAUR */ + writel(0, fep->enet_addr + MCF_FEC_IAUR0); + writel(0, fep->enet_addr + MCF_FEC_IAUR1); + + /* IALR */ + writel(0, fep->enet_addr + MCF_FEC_IALR0); + writel(0, fep->enet_addr + MCF_FEC_IALR1); + + /* GAUR */ + writel(0, fep->enet_addr + MCF_FEC_GAUR0); + writel(0, fep->enet_addr + MCF_FEC_GAUR1); + + /* GALR */ + writel(0, fep->enet_addr + MCF_FEC_GALR0); + writel(0, fep->enet_addr + MCF_FEC_GALR1); + + /* EMRBR */ + writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR0); + writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR1); + msleep(10); + + /* EIMR */ + writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR0); + writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR1); + + /* PALR PAUR */ + /* Set the station address for the ENET Adapter */ + writel(dev->dev_addr[3] | + dev->dev_addr[2]<<8 | + dev->dev_addr[1]<<16 | + dev->dev_addr[0]<<24, fep->enet_addr + MCF_FEC_PALR0); + writel(dev->dev_addr[5]<<16 | + (dev->dev_addr[4]+(unsigned char)(0))<<24, + fep->enet_addr + MCF_FEC_PAUR0); + writel(dev->dev_addr[3] | + dev->dev_addr[2]<<8 | + dev->dev_addr[1]<<16 | + dev->dev_addr[0]<<24, fep->enet_addr + MCF_FEC_PALR1); + writel(dev->dev_addr[5]<<16 | + (dev->dev_addr[4]+(unsigned char)(1))<<24, + fep->enet_addr + MCF_FEC_PAUR1); + + /* RCR */ + writel(readl(fep->enet_addr + MCF_FEC_RCR0) + | MCF_FEC_RCR_FCE | MCF_FEC_RCR_PROM, + fep->enet_addr + MCF_FEC_RCR0); + writel(readl(fep->enet_addr + MCF_FEC_RCR1) + | MCF_FEC_RCR_FCE | MCF_FEC_RCR_PROM, + fep->enet_addr + MCF_FEC_RCR1); + + /* TCR */ + writel(0x1c, fep->enet_addr + MCF_FEC_TCR0); + writel(0x1c, fep->enet_addr + MCF_FEC_TCR1); + + /* ECR */ + writel(readl(fep->enet_addr + MCF_FEC_ECR0) | MCF_FEC_ECR_ETHER_EN, + fep->enet_addr + MCF_FEC_ECR0); + writel(readl(fep->enet_addr + MCF_FEC_ECR1) | MCF_FEC_ECR_ETHER_EN, + fep->enet_addr + MCF_FEC_ECR1); +} + +/* + * This function is called to start or restart the FEC during a link + * change. This only happens when switching between half and full + * duplex. + */ +static void +switch_restart(struct net_device *dev, int duplex) +{ + struct switch_enet_private *fep; + struct switch_t *fecp; + int i; + struct switch_platform_data *plat; + + fep = netdev_priv(dev); + fecp = fep->hwp; + plat = fep->pdev->dev.platform_data; + /* + * Whack a reset. We should wait for this. + */ + /* fecp->fec_ecntrl = 1; */ + fecp->ESW_MODE = MCF_ESW_MODE_SW_RST; + udelay(10); + fecp->ESW_MODE = MCF_ESW_MODE_STATRST; + fecp->ESW_MODE = MCF_ESW_MODE_SW_EN; + + /* Enable transmit/receive on all ports */ + fecp->ESW_PER = 0xffffffff; + /* + * Management port configuration, + * make port 0 as management port + */ + fecp->ESW_BMPC = 0; + + /* Clear any outstanding interrupt */ + fecp->switch_ievent = 0xffffffff; + /*if (plat && plat->enable_phy_intr) + * plat->enable_phy_intr(); + */ + + /* Reset all multicast */ + /* + * fecp->fec_grp_hash_table_high = 0; + * fecp->fec_grp_hash_table_low = 0; + */ + + /* Set maximum receive buffer size */ + fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; + + if (plat && plat->localhw_setup) + plat->localhw_setup(); + + /* Set receive and transmit descriptor base */ + fecp->fec_r_des_start = fep->bd_dma; + fecp->fec_x_des_start = (unsigned long)fep->bd_dma + + sizeof(struct cbd_t) * RX_RING_SIZE; + + fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; + fep->cur_rx = fep->rx_bd_base; + + /* Reset SKB transmit buffers */ + fep->skb_cur = fep->skb_dirty = 0; + for (i = 0; i <= TX_RING_MOD_MASK; i++) { + if (fep->tx_skbuff[i] != NULL) { + dev_kfree_skb_any(fep->tx_skbuff[i]); + fep->tx_skbuff[i] = NULL; + } + } + + enet_reset(dev, duplex); + esw_clear_atable(fep); + + /* And last, enable the transmit and receive processing */ + fecp->fec_r_des_active = MCF_ESW_RDAR_R_DES_ACTIVE; + + /* Enable interrupts we wish to service */ + fecp->switch_ievent = 0xffffffff; + fecp->switch_imask = MCF_ESW_IMR_RXF | MCF_ESW_IMR_TXF | + MCF_ESW_IMR_RXB | MCF_ESW_IMR_TXB; + +#ifdef SWITCH_DEBUG + printk(KERN_INFO "%s: switch hw init over." + "isr %x mask %x rx_addr %x %x tx_addr %x %x." + "fec_r_buff_size %x\n", __func__, + fecp->switch_ievent, fecp->switch_imask, fecp->fec_r_des_start, + &fecp->fec_r_des_start, fecp->fec_x_des_start, + &fecp->fec_x_des_start, fecp->fec_r_buff_size); + printk(KERN_INFO "%s: fecp->ESW_DBCR %x, fecp->ESW_P0FFEN %x fecp->ESW_BKLR %x\n", + __func__, fecp->ESW_DBCR, fecp->ESW_P0FFEN, fecp->ESW_BKLR); + + printk(KERN_INFO "fecp->portstats[0].MCF_ESW_POQC %x," + "fecp->portstats[0].MCF_ESW_PMVID %x," + "fecp->portstats[0].MCF_ESW_PMVTAG %x," + "fecp->portstats[0].MCF_ESW_PBL %x\n", + fecp->port_statistics_status[0].MCF_ESW_POQC, + fecp->port_statistics_status[0].MCF_ESW_PMVID, + fecp->port_statistics_status[0].MCF_ESW_PMVTAG, + fecp->port_statistics_status[0].MCF_ESW_PBL); + + printk(KERN_INFO "fecp->portstats[1].MCF_ESW_POQC %x," + "fecp->portstats[1].MCF_ESW_PMVID %x," + "fecp->portstats[1].MCF_ESW_PMVTAG %x," + "fecp->portstats[1].MCF_ESW_PBL %x\n", + fecp->port_statistics_status[1].MCF_ESW_POQC, + fecp->port_statistics_status[1].MCF_ESW_PMVID, + fecp->port_statistics_status[1].MCF_ESW_PMVTAG, + fecp->port_statistics_status[1].MCF_ESW_PBL); + + printk(KERN_INFO "fecp->portstats[2].MCF_ESW_POQC %x," + "fecp->portstats[2].MCF_ESW_PMVID %x," + "fecp->portstats[2].MCF_ESW_PMVTAG %x," + "fecp->portstats[2].MCF_ESW_PBL %x\n", + fecp->port_statistics_status[2].MCF_ESW_POQC, + fecp->port_statistics_status[2].MCF_ESW_PMVID, + fecp->port_statistics_status[2].MCF_ESW_PMVTAG, + fecp->port_statistics_status[2].MCF_ESW_PBL); +#endif +} + +static void +switch_stop(struct net_device *dev) +{ + struct switch_t *fecp; + struct switch_enet_private *fep; + struct switch_platform_data *plat; + +#ifdef SWITCH_DEBUG + printk(KERN_ERR "%s\n", __func__); +#endif + fep = netdev_priv(dev); + fecp = fep->hwp; + plat = fep->pdev->dev.platform_data; + /* We cannot expect a graceful transmit stop without link !!! */ + if (fep->link) + udelay(10); + + /* Whack a reset. We should wait for this */ + udelay(10); +} + +#ifdef FEC_PHY +static int fec_mdio_register(struct net_device *dev, + int slot) +{ + int err = 0; + struct switch_enet_private *fep = netdev_priv(dev); + + fep->mdio_bus = mdiobus_alloc(); + if (!fep->mdio_bus) { + printk(KERN_ERR "ethernet switch mdiobus_alloc fail\n"); + return -ENOMEM; + } + + if (slot == 0) { + fep->mdio_bus->name = "FEC switch MII 0 Bus"; + strcpy(fep->mdio_bus->id, "0"); + } else if (slot == 1) { + fep->mdio_bus->name = "FEC switch MII 1 Bus"; + strcpy(fep->mdio_bus->id, "1"); + } else { + printk(KERN_ERR "Now Fec switch can not" + "support more than 2 mii bus\n"); + } + + fep->mdio_bus->read = &fec_enet_mdio_read; + fep->mdio_bus->write = &fec_enet_mdio_write; + fep->mdio_bus->priv = dev; + err = mdiobus_register(fep->mdio_bus); + if (err) { + mdiobus_free(fep->mdio_bus); + printk(KERN_ERR "%s: ethernet mdiobus_register fail\n", + dev->name); + return -EIO; + } + + printk(KERN_INFO "mdiobus_register %s ok\n", + fep->mdio_bus->name); + return err; +} +#endif + +static int __init eth_switch_probe(struct platform_device *pdev) +{ + struct net_device *dev; + int i, err; + struct switch_enet_private *fep; + struct switch_platform_private *chip; + + printk(KERN_INFO "Ethernet Switch Version 1.0\n"); + chip = kzalloc(sizeof(struct switch_platform_private) + + sizeof(struct switch_enet_private *) * SWITCH_MAX_PORTS, + GFP_KERNEL); + if (!chip) { + err = -ENOMEM; + printk(KERN_ERR "%s: kzalloc fail %x\n", __func__, + (unsigned int)chip); + return err; + } + + chip->pdev = pdev; + chip->num_slots = SWITCH_MAX_PORTS; + platform_set_drvdata(pdev, chip); + + for (i = 0; (i < chip->num_slots); i++) { + dev = alloc_etherdev(sizeof(struct switch_enet_private)); + if (!dev) { + printk(KERN_ERR "%s: ethernet switch\ + alloc_etherdev fail\n", + dev->name); + return -ENOMEM; + } + + fep = netdev_priv(dev); + fep->pdev = pdev; + printk(KERN_ERR "%s: ethernet switch port %d init\n", + __func__, i); + err = switch_enet_init(dev, i, pdev); + if (err) { + free_netdev(dev); + platform_set_drvdata(pdev, NULL); + kfree(chip); + continue; + } + + chip->fep_host[i] = fep; + /* disable mdio */ +#ifdef FEC_PHY +#ifdef CONFIG_FEC_SHARED_PHY + if (i == 0) + err = fec_mdio_register(dev, 0); + else { + fep->mdio_bus = chip->fep_host[0]->mdio_bus; + printk(KERN_INFO "FEC%d SHARED the %s ok\n", + i, fep->mdio_bus->name); + } +#else + err = fec_mdio_register(dev, i); +#endif + if (err) { + printk(KERN_ERR "%s: ethernet switch fec_mdio_register\n", + dev->name); + free_netdev(dev); + platform_set_drvdata(pdev, NULL); + kfree(chip); + return -ENOMEM; + } +#endif + /* setup timer for Learning Aging function */ + /* + * setup_timer(&fep->timer_aging, + * l2switch_aging_timer, (unsigned long)fep); + */ + init_timer(&fep->timer_aging); + fep->timer_aging.function = l2switch_aging_timer; + fep->timer_aging.data = (unsigned long) fep; + fep->timer_aging.expires = jiffies + LEARNING_AGING_TIMER; + + /* register network device */ + if (register_netdev(dev) != 0) { + free_netdev(dev); + platform_set_drvdata(pdev, NULL); + kfree(chip); + printk(KERN_ERR "%s: ethernet switch register_netdev fail\n", + dev->name); + return -EIO; + } + printk(KERN_INFO "%s: ethernet switch %pM\n", + dev->name, dev->dev_addr); + } + + return 0; +} + +static int eth_switch_remove(struct platform_device *pdev) +{ + int i; + struct net_device *dev; + struct switch_enet_private *fep; + struct switch_platform_private *chip; + + chip = platform_get_drvdata(pdev); + if (chip) { + for (i = 0; i < chip->num_slots; i++) { + fep = chip->fep_host[i]; + dev = fep->netdev; + fep->sequence_done = 1; + unregister_netdev(dev); + free_netdev(dev); + + del_timer_sync(&fep->timer_aging); + } + + platform_set_drvdata(pdev, NULL); + kfree(chip); + + } else + printk(KERN_ERR "%s: can not get the " + "switch_platform_private %x\n", __func__, + (unsigned int)chip); + + return 0; +} + +static struct platform_driver eth_switch_driver = { + .probe = eth_switch_probe, + .remove = eth_switch_remove, + .driver = { + .name = "mxs-l2switch", + .owner = THIS_MODULE, + }, +}; + +static int __init fec_l2switch_init(void) +{ + return platform_driver_register(ð_switch_driver);; +} + +static void __exit fec_l2_switch_exit(void) +{ + platform_driver_unregister(ð_switch_driver); +} + +module_init(fec_l2switch_init); +module_exit(fec_l2_switch_exit); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/fec_switch.h b/drivers/net/fec_switch.h new file mode 100644 index 000000000000..7b9f6a180f6a --- /dev/null +++ b/drivers/net/fec_switch.h @@ -0,0 +1,1121 @@ +/****************************************************************************/ + +/* + * mcfswitch -- L2 Switch Controller for Modelo ColdFire SoC + * processors. + * + * Copyright (C) 2010 Freescale Semiconductor,Inc.All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + * + */ + +/****************************************************************************/ +#ifndef SWITCH_H +#define SWITCH_H +/****************************************************************************/ +/* The Switch stores dest/src/type, data, and checksum for receive packets. + */ +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1520 + +/* + * The 5441x RX control register also contains maximum frame + * size bits. + */ +#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) + +/* + * Some hardware gets it MAC address out of local flash memory. + * if this is non-zero then assume it is the address to get MAC from. + */ +#define FEC_FLASHMAC 0 + +/* The number of Tx and Rx buffers. These are allocated from the page + * pool. The code may assume these are power of two, so it it best + * to keep them that size. + * We don't need to allocate pages for the transmitter. We just use + * the skbuffer directly. + */ +#ifdef CONFIG_SWITCH_DMA_USE_SRAM +#define SWITCH_ENET_RX_PAGES 6 +#else +#define SWITCH_ENET_RX_PAGES 8 +#endif + +#define SWITCH_ENET_RX_FRSIZE 2048 +#define SWITCH_ENET_RX_FRPPG (PAGE_SIZE / SWITCH_ENET_RX_FRSIZE) +#define RX_RING_SIZE (SWITCH_ENET_RX_FRPPG * SWITCH_ENET_RX_PAGES) +#define SWITCH_ENET_TX_FRSIZE 2048 +#define SWITCH_ENET_TX_FRPPG (PAGE_SIZE / SWITCH_ENET_TX_FRSIZE) + +#ifdef CONFIG_SWITCH_DMA_USE_SRAM +#define TX_RING_SIZE 8 /* Must be power of two */ +#define TX_RING_MOD_MASK 7 /* for this to work */ +#else +#define TX_RING_SIZE 16 /* Must be power of two */ +#define TX_RING_MOD_MASK 15 /* for this to work */ +#endif + +#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) +#error "L2SWITCH: descriptor ring size constants too large" +#endif +/*-----------------------------------------------------------------------*/ +struct esw_output_queue_status { + unsigned long ESW_MMSR; + unsigned long ESW_LMT; + unsigned long ESW_LFC; + unsigned long ESW_PCSR; + unsigned long ESW_IOSR; + unsigned long ESW_QWT; + unsigned long esw_reserved; + unsigned long ESW_P0BCT; +}; +struct esw_statistics_status { + /* + * Total number of incoming frames processed + * but discarded in switch + */ + unsigned long ESW_DISCN; + /*Sum of bytes of frames counted in ESW_DISCN*/ + unsigned long ESW_DISCB; + /* + * Total number of incoming frames processed + * but not discarded in switch + */ + unsigned long ESW_NDISCN; + /*Sum of bytes of frames counted in ESW_NDISCN*/ + unsigned long ESW_NDISCB; +}; + +struct esw_port_statistics_status { + /*outgoing frames discarded due to transmit queue congestion*/ + unsigned long MCF_ESW_POQC; + /*incoming frames discarded due to VLAN domain mismatch*/ + unsigned long MCF_ESW_PMVID; + /*incoming frames discarded due to untagged discard*/ + unsigned long MCF_ESW_PMVTAG; + /*incoming frames discarded due port is in blocking state*/ + unsigned long MCF_ESW_PBL; +}; + +struct switch_t { + unsigned long ESW_REVISION; + unsigned long ESW_SCRATCH; + unsigned long ESW_PER; + unsigned long reserved0[1]; + unsigned long ESW_VLANV; + unsigned long ESW_DBCR; + unsigned long ESW_DMCR; + unsigned long ESW_BKLR; + unsigned long ESW_BMPC; + unsigned long ESW_MODE; + unsigned long ESW_VIMSEL; + unsigned long ESW_VOMSEL; + unsigned long ESW_VIMEN; + unsigned long ESW_VID;/*0x34*/ + /*from 0x38 0x3C*/ + unsigned long esw_reserved0[2]; + unsigned long ESW_MCR;/*0x40*/ + unsigned long ESW_EGMAP; + unsigned long ESW_INGMAP; + unsigned long ESW_INGSAL; + unsigned long ESW_INGSAH; + unsigned long ESW_INGDAL; + unsigned long ESW_INGDAH; + unsigned long ESW_ENGSAL; + unsigned long ESW_ENGSAH; + unsigned long ESW_ENGDAL; + unsigned long ESW_ENGDAH; + unsigned long ESW_MCVAL;/*0x6C*/ + /*from 0x70--0x7C*/ + unsigned long esw_reserved1[4]; + unsigned long ESW_MMSR;/*0x80*/ + unsigned long ESW_LMT; + unsigned long ESW_LFC; + unsigned long ESW_PCSR; + unsigned long ESW_IOSR; + unsigned long ESW_QWT;/*0x94*/ + unsigned long esw_reserved2[1];/*0x98*/ + unsigned long ESW_P0BCT;/*0x9C*/ + /*from 0xA0-0xB8*/ + unsigned long esw_reserved3[7]; + unsigned long ESW_P0FFEN;/*0xBC*/ + unsigned long ESW_PSNP[8]; + unsigned long ESW_IPSNP[8]; + unsigned long ESW_PVRES[3]; + /*from 0x10C-0x13C*/ + unsigned long esw_reserved4[13]; + unsigned long ESW_IPRES;/*0x140*/ + /*from 0x144-0x17C*/ + unsigned long esw_reserved5[15]; + unsigned long ESW_PRES[3]; + /*from 0x18C-0x1FC*/ + unsigned long esw_reserved6[29]; + unsigned long ESW_PID[3]; + /*from 0x20C-0x27C*/ + unsigned long esw_reserved7[29]; + unsigned long ESW_VRES[32]; + unsigned long ESW_DISCN;/*0x300*/ + unsigned long ESW_DISCB; + unsigned long ESW_NDISCN; + unsigned long ESW_NDISCB;/*0xFC0DC30C*/ + struct esw_port_statistics_status port_statistics_status[3]; + /*from 0x340-0x400*/ + unsigned long esw_reserved8[48]; + + /*0xFC0DC400---0xFC0DC418*/ + /*unsigned long MCF_ESW_ISR;*/ + unsigned long switch_ievent; /* Interrupt event reg */ + /*unsigned long MCF_ESW_IMR;*/ + unsigned long switch_imask; /* Interrupt mask reg */ + /*unsigned long MCF_ESW_RDSR;*/ + unsigned long fec_r_des_start; /* Receive descriptor ring */ + /*unsigned long MCF_ESW_TDSR;*/ + unsigned long fec_x_des_start; /* Transmit descriptor ring */ + /*unsigned long MCF_ESW_MRBR;*/ + unsigned long fec_r_buff_size; /* Maximum receive buff size */ + /*unsigned long MCF_ESW_RDAR;*/ + unsigned long fec_r_des_active; /* Receive descriptor reg */ + /*unsigned long MCF_ESW_TDAR;*/ + unsigned long fec_x_des_active; /* Transmit descriptor reg */ + /*from 0x420-0x4FC*/ + unsigned long esw_reserved9[57]; + + /*0xFC0DC500---0xFC0DC508*/ + unsigned long ESW_LREC0; + unsigned long ESW_LREC1; + unsigned long ESW_LSR; +}; + +struct AddrTable64bEntry { + unsigned int lo; /* lower 32 bits */ + unsigned int hi; /* upper 32 bits */ +}; + +struct eswAddrTable_t { + struct AddrTable64bEntry eswTable64bEntry[2048]; +}; + +#define MCF_ESW_LOOKUP_MEM_OFFSET 0x4000 +#define ENET_SWI_PHYS_ADDR_OFFSET 0x8000 +#define MCF_ESW_PER (0x08 / sizeof(unsigned long)) +#define MCF_ESW_DBCR (0x14 / sizeof(unsigned long)) +#define MCF_ESW_IMR (0x404 / sizeof(unsigned long)) + +#define MCF_FEC_BASE_ADDR (fep->enet_addr) +#define MCF_FEC_EIR0 (0x04 / sizeof(unsigned long)) +#define MCF_FEC_EIR1 (0x4004 / sizeof(unsigned long)) +#define MCF_FEC_EIMR0 (0x08 / sizeof(unsigned long)) +#define MCF_FEC_EIMR1 (0x4008 / sizeof(unsigned long)) +#define MCF_FEC_MMFR0 (0x40 / sizeof(unsigned long)) +#define MCF_FEC_MMFR1 (0x4040 / sizeof(unsigned long)) +#define MCF_FEC_MSCR0 (0x44 / sizeof(unsigned long)) +#define MCF_FEC_MSCR1 (0x4044 / sizeof(unsigned long)) + +#define MCF_FEC_RCR0 (0x84 / sizeof(unsigned long)) +#define MCF_FEC_RCR1 (0x4084 / sizeof(unsigned long)) +#define MCF_FEC_TCR0 (0xC4 / sizeof(unsigned long)) +#define MCF_FEC_TCR1 (0x40C4 / sizeof(unsigned long)) +#define MCF_FEC_ECR0 (0x24 / sizeof(unsigned long)) +#define MCF_FEC_ECR1 (0x4024 / sizeof(unsigned long)) + +#define MCF_FEC_PALR0 (0xE4 / sizeof(unsigned long)) +#define MCF_FEC_PALR1 (0x40E4 / sizeof(unsigned long)) +#define MCF_FEC_PAUR0 (0xE8 / sizeof(unsigned long)) +#define MCF_FEC_PAUR1 (0x40E8 / sizeof(unsigned long)) + +#define MCF_FEC_ERDSR0 (0x180 / sizeof(unsigned long)) +#define MCF_FEC_ERDSR1 (0x4180 / sizeof(unsigned long)) +#define MCF_FEC_ETDSR0 (0x184 / sizeof(unsigned long)) +#define MCF_FEC_ETDSR1 (0x4184 / sizeof(unsigned long)) + +#define MCF_FEC_IAUR0 (0x118 / sizeof(unsigned long)) +#define MCF_FEC_IAUR1 (0x4118 / sizeof(unsigned long)) +#define MCF_FEC_IALR0 (0x11C / sizeof(unsigned long)) +#define MCF_FEC_IALR1 (0x411C / sizeof(unsigned long)) + +#define MCF_FEC_GAUR0 (0x120 / sizeof(unsigned long)) +#define MCF_FEC_GAUR1 (0x4120 / sizeof(unsigned long)) +#define MCF_FEC_GALR0 (0x124 / sizeof(unsigned long)) +#define MCF_FEC_GALR1 (0x4124 / sizeof(unsigned long)) + +#define MCF_FEC_EMRBR0 (0x188 / sizeof(unsigned long)) +#define MCF_FEC_EMRBR1 (0x4188 / sizeof(unsigned long)) + +#define MCF_FEC_RCR_DRT (0x00000002) +#define MCF_FEC_RCR_PROM (0x00000008) +#define MCF_FEC_RCR_FCE (0x00000020) +#define MCF_FEC_RCR_RMII_MODE (0x00000100) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x00003FFF)<<16) +#define MCF_FEC_RCR_CRC_FWD (0x00004000) +#define MCF_FEC_RCR_NO_LGTH_CHECK (0x40000000) +#define MCF_FEC_TCR_FDEN (0x00000004) + +#define MCF_FEC_ECR_RESET (0x00000001) +#define MCF_FEC_ECR_ETHER_EN (0x00000002) +#define MCF_FEC_ECR_MAGIC_ENA (0x00000004) +#define MCF_FEC_ECR_ENA_1588 (0x00000010) + +#define MCF_FEC_ERDSR(x) ((x) << 2) + +/*-------------ioctl command ---------------------------------------*/ +#define ESW_SET_LEARNING_CONF 0x9101 +#define ESW_GET_LEARNING_CONF 0x9201 +#define ESW_SET_BLOCKING_CONF 0x9102 +#define ESW_GET_BLOCKING_CONF 0x9202 +#define ESW_SET_MULTICAST_CONF 0x9103 +#define ESW_GET_MULTICAST_CONF 0x9203 +#define ESW_SET_BROADCAST_CONF 0x9104 +#define ESW_GET_BROADCAST_CONF 0x9204 +#define ESW_SET_PORTENABLE_CONF 0x9105 +#define ESW_GET_PORTENABLE_CONF 0x9205 +#define ESW_SET_IP_SNOOP_CONF 0x9106 +#define ESW_GET_IP_SNOOP_CONF 0x9206 +#define ESW_SET_PORT_SNOOP_CONF 0x9107 +#define ESW_GET_PORT_SNOOP_CONF 0x9207 +#define ESW_SET_PORT_MIRROR_CONF 0x9108 +#define ESW_GET_PORT_MIRROR_CONF 0x9208 +#define ESW_SET_PIRORITY_VLAN 0x9109 +#define ESW_GET_PIRORITY_VLAN 0x9209 +#define ESW_SET_PIRORITY_IP 0x910A +#define ESW_GET_PIRORITY_IP 0x920A +#define ESW_SET_PIRORITY_MAC 0x910B +#define ESW_GET_PIRORITY_MAC 0x920B +#define ESW_SET_PIRORITY_DEFAULT 0x910C +#define ESW_GET_PIRORITY_DEFAULT 0x920C +#define ESW_SET_P0_FORCED_FORWARD 0x910D +#define ESW_GET_P0_FORCED_FORWARD 0x920D +#define ESW_SET_SWITCH_MODE 0x910E +#define ESW_GET_SWITCH_MODE 0x920E +#define ESW_SET_BRIDGE_CONFIG 0x910F +#define ESW_GET_BRIDGE_CONFIG 0x920F +#define ESW_SET_VLAN_OUTPUT_PROCESS 0x9110 +#define ESW_GET_VLAN_OUTPUT_PROCESS 0x9210 +#define ESW_SET_VLAN_INPUT_PROCESS 0x9111 +#define ESW_GET_VLAN_INPUT_PROCESS 0x9211 +#define ESW_SET_VLAN_DOMAIN_VERIFICATION 0x9112 +#define ESW_GET_VLAN_DOMAIN_VERIFICATION 0x9212 +#define ESW_SET_VLAN_RESOLUTION_TABLE 0x9113 +#define ESW_GET_VLAN_RESOLUTION_TABLE 0x9213 + + +#define ESW_GET_STATISTICS_STATUS 0x9221 +#define ESW_GET_PORT0_STATISTICS_STATUS 0x9222 +#define ESW_GET_PORT1_STATISTICS_STATUS 0x9223 +#define ESW_GET_PORT2_STATISTICS_STATUS 0x9224 +#define ESW_SET_OUTPUT_QUEUE_MEMORY 0x9125 +#define ESW_GET_OUTPUT_QUEUE_STATUS 0x9225 +#define ESW_UPDATE_STATIC_MACTABLE 0x9226 +#define ESW_CLEAR_ALL_MACTABLE 0x9227 + +struct eswIoctlPortConfig { + int port; + int enable; +}; + +struct eswIoctlPortEnableConfig { + int port; + int tx_enable; + int rx_enable; +}; + +struct eswIoctlIpsnoopConfig { + int num; + int mode; + unsigned char ip_header_protocol; +}; + +struct eswIoctlP0ForcedForwardConfig { + int port1; + int port2; + int enable; +}; + +struct eswIoctlPortsnoopConfig { + int num; + int mode; + unsigned short compare_port; + int compare_num; +}; + +struct eswIoctlPortMirrorConfig { + int mirror_port; + int port; + int egress_en; + int ingress_en; + int egress_mac_src_en; + int egress_mac_des_en; + int ingress_mac_src_en; + int ingress_mac_des_en; + unsigned char *src_mac; + unsigned char *des_mac; + int mirror_enable; +}; + +struct eswIoctlPriorityVlanConfig { + int port; + int func_enable; + int vlan_pri_table_num; + int vlan_pri_table_value; +}; + +struct eswIoctlPriorityIPConfig { + int port; + int func_enable; + int ipv4_en; + int ip_priority_num; + int ip_priority_value; +}; + +struct eswIoctlPriorityMacConfig { + int port; +}; + +struct eswIoctlPriorityDefaultConfig{ + int port; + unsigned char priority_value; +}; + +struct eswIoctlIrqStatus { + unsigned long isr; + unsigned long imr; + unsigned long rx_buf_pointer; + unsigned long tx_buf_pointer; + unsigned long rx_max_size; + unsigned long rx_buf_active; + unsigned long tx_buf_active; +}; + +struct eswIoctlPortMirrorStatus { + unsigned long ESW_MCR; + unsigned long ESW_EGMAP; + unsigned long ESW_INGMAP; + unsigned long ESW_INGSAL; + unsigned long ESW_INGSAH; + unsigned long ESW_INGDAL; + unsigned long ESW_INGDAH; + unsigned long ESW_ENGSAL; + unsigned long ESW_ENGSAH; + unsigned long ESW_ENGDAL; + unsigned long ESW_ENGDAH; + unsigned long ESW_MCVAL; +}; + +struct eswIoctlVlanOutputConfig { + int port; + int mode; +}; + +struct eswIoctlVlanInputConfig { + int port; + int mode; + unsigned short port_vlanid; + int vlan_verify_en; + int vlan_domain_num; + int vlan_domain_port; +}; + +struct eswIoctlVlanVerificationConfig { + int port; + int vlan_domain_verify_en; + int vlan_discard_unknown_en; +}; + +struct eswIoctlVlanResoultionTable { + unsigned short port_vlanid; + int vlan_domain_num; + int vlan_domain_port; +}; + +struct eswIoctlVlanInputStatus { + unsigned long ESW_VLANV; + unsigned long ESW_PID[3]; + unsigned long ESW_VIMSEL; + unsigned long ESW_VIMEN; + unsigned long ESW_VRES[32]; +}; + +struct eswIoctlUpdateStaticMACtable { + unsigned char *mac_addr; + int port; + int priority; +}; + +struct eswIoctlOutputQueue { + int fun_num; + struct esw_output_queue_status sOutputQueue; +}; + +/*=============================================================*/ +#define LEARNING_AGING_TIMER (10 * HZ) +/* + * Info received from Hardware Learning FIFO, + * holding MAC address and corresponding Hash Value and + * port number where the frame was received (disassembled). + */ +struct eswPortInfo { + /* MAC lower 32 bits (first byte is 7:0). */ + unsigned int maclo; + /* MAC upper 16 bits (47:32). */ + unsigned int machi; + /* the hash value for this MAC address. */ + unsigned int hash; + /* the port number this MAC address is associated with. */ + unsigned int port; +}; + +/* + * Hardware Look up Address Table 64-bit element. + */ +struct eswTable64bitEntry { + unsigned int lo; /* lower 32 bits */ + unsigned int hi; /* upper 32 bits */ +}; + +/* + * Disassembled element stored in Address Table. + */ +struct eswAddrTableDynamicEntry { + /* MAC lower 32 bits (first byte is 7:0). */ + unsigned int maclo; + /* MAC upper 16 bits (47:32). */ + unsigned int machi; + /* timestamp of this entry */ + unsigned int timestamp; + /* the port number this MAC address is associated with */ + unsigned int port; +}; + +struct eswAddrTableStaticEntry { + /* MAC lower 32 bits (first byte is 7:0). */ + unsigned int maclo; + /* MAC upper 16 bits (47:32). */ + unsigned int machi; + /* priority of this entry */ + unsigned int priority; + /* the port bitmask this MAC address is associated with */ + unsigned int portbitmask; +}; +/* + * Define the buffer descriptor structure. + */ +struct cbd_t { +#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS) + unsigned short cbd_datlen; /* Data length */ + unsigned short cbd_sc; /* Control and status info */ +#else + unsigned short cbd_sc; /* Control and status info */ + unsigned short cbd_datlen; /* Data length */ +#endif + unsigned long cbd_bufaddr; /* Buffer address */ +#ifdef L2SWITCH_ENHANCED_BUFFER + unsigned long ebd_status; + unsigned short length_proto_type; + unsigned short payload_checksum; + unsigned long bdu; + unsigned long timestamp; + unsigned long reserverd_word1; + unsigned long reserverd_word2; +#endif +}; + +/* Forward declarations of some structures to support different PHYs + */ +struct phy_cmd_t { + uint mii_data; + void (*funct)(uint mii_reg, struct net_device *dev); +}; + +struct phy_info_t { + uint id; + char *name; + + const struct phy_cmd_t *config; + const struct phy_cmd_t *startup; + const struct phy_cmd_t *ack_int; + const struct phy_cmd_t *shutdown; +}; + +/* The switch buffer descriptors track the ring buffers. The rx_bd_base and + * tx_bd_base always point to the base of the buffer descriptors. The + * cur_rx and cur_tx point to the currently available buffer. + * The dirty_tx tracks the current buffer that is being sent by the + * controller. The cur_tx and dirty_tx are equal under both completely + * empty and completely full conditions. The empty/ready indicator in + * the buffer descriptor determines the actual condition. + */ +struct switch_enet_private { + /* Hardware registers of the switch device */ + struct switch_t *hwp; + struct eswAddrTable_t *hwentry; + unsigned long *enet_addr; + + struct net_device *netdev; + struct platform_device *pdev; + struct clk *clk; + /* The saved address of a sent-in-place packet/buffer, for skfree(). */ + unsigned char *tx_bounce[TX_RING_SIZE]; + struct sk_buff *tx_skbuff[TX_RING_SIZE]; + struct sk_buff *rx_skbuff[RX_RING_SIZE]; + ushort skb_cur; + ushort skb_dirty; + + /* CPM dual port RAM relative addresses */ + dma_addr_t bd_dma; + struct cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ + struct cbd_t *tx_bd_base; + struct cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ + struct cbd_t *dirty_tx; /* The ring entries to be free()ed. */ + uint tx_full; + /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ + spinlock_t hw_lock; + + /* hold while accessing the mii_list_t() elements */ + spinlock_t mii_lock; + struct mii_bus *mdio_bus; + struct phy_device *phydev; + phy_interface_t phy_interface; + + uint phy_id; + uint phy_id_done; + uint phy_status; + struct phy_info_t const *phy; + struct work_struct phy_task; + struct switch_t *phy_hwp; + + uint sequence_done; + uint mii_phy_task_queued; + + uint phy_addr; + + int opened; + int old_link; + int duplex; + int speed; + int msg_enable; + + /* --------------Statistics--------------------------- */ + /* when a new element deleted a element with in + * a block due to lack of space */ + int atBlockOverflows; + /* Peak number of valid entries in the address table */ + int atMaxEntries; + /* current number of valid entries in the address table */ + int atCurrEntries; + /* maximum entries within a block found + * (updated within ageing)*/ + int atMaxEntriesPerBlock; + + /* -------------------ageing function------------------ */ + /* maximum age allowed for an entry */ + int ageMax; + /* last LUT entry to block that was + * inspected by the Ageing task*/ + int ageLutIdx; + /* last element within block inspected by the Ageing task */ + int ageBlockElemIdx; + /* complete table has been processed by ageing process */ + int ageCompleted; + /* delay setting */ + int ageDelay; + /* current delay Counter */ + int ageDelayCnt; + + /* ----------------timer related---------------------------- */ + /* current time (for timestamping) */ + int currTime; + /* flag set by timer when currTime changed + * and cleared by serving function*/ + int timeChanged; + + /**/ + /* Timer for Aging */ + struct timer_list timer_aging; + int learning_irqhandle_enable; + /* Phylib and MDIO interface */ + struct mii_bus *mii_bus; + struct phy_device *phy_dev; + int mii_timeout; + uint phy_speed; + int index; + int link; + int full_duplex; +}; + +struct switch_platform_private { + struct platform_device *pdev; + + unsigned long quirks; + int num_slots; /* Slots on controller */ + struct switch_enet_private *fep_host[0]; /* Pointers to hosts */ +}; + +/******************************************************************************/ +#define FEC_IEVENT 0x004 /* Interrupt event reg */ +#define FEC_IMASK 0x008 /* Interrupt mask reg */ +#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ +#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ +#define FEC_ECNTRL 0x024 /* Ethernet control reg */ +#define FEC_MII_DATA 0x040 /* MII manage frame reg */ +#define FEC_MII_SPEED 0x044 /* MII speed control reg */ +#define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ +#define FEC_R_CNTRL 0x084 /* Receive control reg */ +#define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ +#define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ +#define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ +#define FEC_OPD 0x0ec /* Opcode + Pause duration */ +#define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ +#define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ +#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ +#define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ +#define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ +#define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ +#define FEC_R_FSTART 0x150 /* FIFO receive start reg */ +#define FEC_R_DES_START 0x180 /* Receive descriptor ring */ +#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */ +#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */ +#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK config register */ +#define FEC_MIIGSK_ENR 0x308 /* MIIGSK enable register */ + +/* Recieve is empty */ +#define BD_SC_EMPTY ((unsigned short)0x8000) +/* Transmit is ready */ +#define BD_SC_READY ((unsigned short)0x8000) +/* Last buffer descriptor */ +#define BD_SC_WRAP ((unsigned short)0x2000) +/* Interrupt on change */ +#define BD_SC_INTRPT ((unsigned short)0x1000) +/* Continous mode */ +#define BD_SC_CM ((unsigned short)0x0200) +/* Rec'd too many idles */ +#define BD_SC_ID ((unsigned short)0x0100) +/* xmt preamble */ +#define BD_SC_P ((unsigned short)0x0100) +/* Break received */ +#define BD_SC_BR ((unsigned short)0x0020) +/* Framing error */ +#define BD_SC_FR ((unsigned short)0x0010) +/* Parity error */ +#define BD_SC_PR ((unsigned short)0x0008) +/* Overrun */ +#define BD_SC_OV ((unsigned short)0x0002) +#define BD_SC_CD ((unsigned short)0x0001) + +/* Buffer descriptor control/status used by Ethernet receive. +*/ +#define BD_ENET_RX_EMPTY ((unsigned short)0x8000) +#define BD_ENET_RX_WRAP ((unsigned short)0x2000) +#define BD_ENET_RX_INTR ((unsigned short)0x1000) +#define BD_ENET_RX_LAST ((unsigned short)0x0800) +#define BD_ENET_RX_FIRST ((unsigned short)0x0400) +#define BD_ENET_RX_MISS ((unsigned short)0x0100) +#define BD_ENET_RX_LG ((unsigned short)0x0020) +#define BD_ENET_RX_NO ((unsigned short)0x0010) +#define BD_ENET_RX_SH ((unsigned short)0x0008) +#define BD_ENET_RX_CR ((unsigned short)0x0004) +#define BD_ENET_RX_OV ((unsigned short)0x0002) +#define BD_ENET_RX_CL ((unsigned short)0x0001) +/* All status bits */ +#define BD_ENET_RX_STATS ((unsigned short)0x013f) + +/* Buffer descriptor control/status used by Ethernet transmit. +*/ +#define BD_ENET_TX_READY ((unsigned short)0x8000) +#define BD_ENET_TX_PAD ((unsigned short)0x4000) +#define BD_ENET_TX_WRAP ((unsigned short)0x2000) +#define BD_ENET_TX_INTR ((unsigned short)0x1000) +#define BD_ENET_TX_LAST ((unsigned short)0x0800) +#define BD_ENET_TX_TC ((unsigned short)0x0400) +#define BD_ENET_TX_DEF ((unsigned short)0x0200) +#define BD_ENET_TX_HB ((unsigned short)0x0100) +#define BD_ENET_TX_LC ((unsigned short)0x0080) +#define BD_ENET_TX_RL ((unsigned short)0x0040) +#define BD_ENET_TX_RCMASK ((unsigned short)0x003c) +#define BD_ENET_TX_UN ((unsigned short)0x0002) +#define BD_ENET_TX_CSL ((unsigned short)0x0001) +/* All status bits */ +#define BD_ENET_TX_STATS ((unsigned short)0x03ff) + +/*Copy from validation code */ +#define RX_BUFFER_SIZE 256 +#define TX_BUFFER_SIZE 256 +#define NUM_RXBDS 20 +#define NUM_TXBDS 20 + +#define TX_BD_R 0x8000 +#define TX_BD_TO1 0x4000 +#define TX_BD_W 0x2000 +#define TX_BD_TO2 0x1000 +#define TX_BD_L 0x0800 +#define TX_BD_TC 0x0400 + +#define TX_BD_INT 0x40000000 +#define TX_BD_TS 0x20000000 +#define TX_BD_PINS 0x10000000 +#define TX_BD_IINS 0x08000000 +#define TX_BD_TXE 0x00008000 +#define TX_BD_UE 0x00002000 +#define TX_BD_EE 0x00001000 +#define TX_BD_FE 0x00000800 +#define TX_BD_LCE 0x00000400 +#define TX_BD_OE 0x00000200 +#define TX_BD_TSE 0x00000100 +#define TX_BD_BDU 0x80000000 + +#define RX_BD_E 0x8000 +#define RX_BD_R01 0x4000 +#define RX_BD_W 0x2000 +#define RX_BD_R02 0x1000 +#define RX_BD_L 0x0800 +#define RX_BD_M 0x0100 +#define RX_BD_BC 0x0080 +#define RX_BD_MC 0x0040 +#define RX_BD_LG 0x0020 +#define RX_BD_NO 0x0010 +#define RX_BD_CR 0x0004 +#define RX_BD_OV 0x0002 +#define RX_BD_TR 0x0001 + +#define RX_BD_ME 0x80000000 +#define RX_BD_PE 0x04000000 +#define RX_BD_CE 0x02000000 +#define RX_BD_UC 0x01000000 +#define RX_BD_INT 0x00800000 +#define RX_BD_ICE 0x00000020 +#define RX_BD_PCR 0x00000010 +#define RX_BD_VLAN 0x00000004 +#define RX_BD_IPV6 0x00000002 +#define RX_BD_FRAG 0x00000001 +#define RX_BD_BDU 0x80000000 +/****************************************************************************/ + +/* Address Table size in bytes(2048 64bit entry ) */ +#define ESW_ATABLE_MEM_SIZE (2048*8) +/* How many 64-bit elements fit in the address table */ +#define ESW_ATABLE_MEM_NUM_ENTRIES (2048) +/* Address Table Maximum number of entries in each Slot */ +#define ATABLE_ENTRY_PER_SLOT 8 +/* log2(ATABLE_ENTRY_PER_SLOT)*/ +#define ATABLE_ENTRY_PER_SLOT_bits 3 +/* entry size in byte */ +#define ATABLE_ENTRY_SIZE 8 +/* slot size in byte */ +#define ATABLE_SLOT_SIZE (ATABLE_ENTRY_PER_SLOT * ATABLE_ENTRY_SIZE) +/* width of timestamp variable (bits) within address table entry */ +#define AT_DENTRY_TIMESTAMP_WIDTH 10 +/* number of bits for port number storage */ +#define AT_DENTRY_PORT_WIDTH 4 +/* number of bits for port bitmask number storage */ +#define AT_SENTRY_PORT_WIDTH 11 +/* address table static entry port bitmask start address bit */ +#define AT_SENTRY_PORTMASK_shift 21 +/* address table static entry priority start address bit */ +#define AT_SENTRY_PRIO_shift 18 +/* address table dynamic entry port start address bit */ +#define AT_DENTRY_PORT_shift 28 +/* address table dynamic entry timestamp start address bit */ +#define AT_DENTRY_TIME_shift 18 +/* address table entry record type start address bit */ +#define AT_ENTRY_TYPE_shift 17 +/* address table entry record type bit: 1 static, 0 dynamic */ +#define AT_ENTRY_TYPE_STATIC 1 +#define AT_ENTRY_TYPE_DYNAMIC 0 +/* address table entry record valid start address bit */ +#define AT_ENTRY_VALID_shift 16 +#define AT_ENTRY_RECORD_VALID 1 + + +/* return block corresponding to the 8 bit hash value calculated */ +#define GET_BLOCK_PTR(hash) (hash << 3) +#define AT_EXTRACT_TIMESTAMP(x) \ + ((x >> AT_DENTRY_TIME_shift) & ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1)) +#define AT_EXTRACT_PORT(x) \ + ((x >> AT_DENTRY_PORT_shift) & ((1 << AT_DENTRY_PORT_WIDTH)-1)) +#define TIMEDELTA(newtime, oldtime) \ + ((newtime - oldtime) & \ + ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1)) +/* increment time value respecting modulo. */ +#define TIMEINCREMENT(time) \ + ((time) = ((time)+1) & ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1)) +/* ------------------------------------------------------------------------- */ +/* Bit definitions and macros for MCF_ESW_REVISION */ +#define MCF_ESW_REVISION_CORE_REVISION(x) (((x)&0x0000FFFF)<<0) +#define MCF_ESW_REVISION_CUSTOMER_REVISION(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_ESW_PER */ +#define MCF_ESW_PER_TE0 (0x00000001) +#define MCF_ESW_PER_TE1 (0x00000002) +#define MCF_ESW_PER_TE2 (0x00000004) +#define MCF_ESW_PER_RE0 (0x00010000) +#define MCF_ESW_PER_RE1 (0x00020000) +#define MCF_ESW_PER_RE2 (0x00040000) + +/* Bit definitions and macros for MCF_ESW_VLANV */ +#define MCF_ESW_VLANV_VV0 (0x00000001) +#define MCF_ESW_VLANV_VV1 (0x00000002) +#define MCF_ESW_VLANV_VV2 (0x00000004) +#define MCF_ESW_VLANV_DU0 (0x00010000) +#define MCF_ESW_VLANV_DU1 (0x00020000) +#define MCF_ESW_VLANV_DU2 (0x00040000) + +/* Bit definitions and macros for MCF_ESW_DBCR */ +#define MCF_ESW_DBCR_P0 (0x00000001) +#define MCF_ESW_DBCR_P1 (0x00000002) +#define MCF_ESW_DBCR_P2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_DMCR */ +#define MCF_ESW_DMCR_P0 (0x00000001) +#define MCF_ESW_DMCR_P1 (0x00000002) +#define MCF_ESW_DMCR_P2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_BKLR */ +#define MCF_ESW_BKLR_BE0 (0x00000001) +#define MCF_ESW_BKLR_BE1 (0x00000002) +#define MCF_ESW_BKLR_BE2 (0x00000004) +#define MCF_ESW_BKLR_LD0 (0x00010000) +#define MCF_ESW_BKLR_LD1 (0x00020000) +#define MCF_ESW_BKLR_LD2 (0x00040000) + +/* Bit definitions and macros for MCF_ESW_BMPC */ +#define MCF_ESW_BMPC_PORT(x) (((x)&0x0000000F)<<0) +#define MCF_ESW_BMPC_MSG_TX (0x00000020) +#define MCF_ESW_BMPC_EN (0x00000040) +#define MCF_ESW_BMPC_DIS (0x00000080) +#define MCF_ESW_BMPC_PRIORITY(x) (((x)&0x00000007)<<13) +#define MCF_ESW_BMPC_PORTMASK(x) (((x)&0x00000007)<<16) + +/* Bit definitions and macros for MCF_ESW_MODE */ +#define MCF_ESW_MODE_SW_RST (0x00000001) +#define MCF_ESW_MODE_SW_EN (0x00000002) +#define MCF_ESW_MODE_STOP (0x00000080) +#define MCF_ESW_MODE_CRC_TRAN (0x00000100) +#define MCF_ESW_MODE_P0CT (0x00000200) +#define MCF_ESW_MODE_STATRST (0x80000000) + +/* Bit definitions and macros for MCF_ESW_VIMSEL */ +#define MCF_ESW_VIMSEL_IM0(x) (((x)&0x00000003)<<0) +#define MCF_ESW_VIMSEL_IM1(x) (((x)&0x00000003)<<2) +#define MCF_ESW_VIMSEL_IM2(x) (((x)&0x00000003)<<4) + +/* Bit definitions and macros for MCF_ESW_VOMSEL */ +#define MCF_ESW_VOMSEL_OM0(x) (((x)&0x00000003)<<0) +#define MCF_ESW_VOMSEL_OM1(x) (((x)&0x00000003)<<2) +#define MCF_ESW_VOMSEL_OM2(x) (((x)&0x00000003)<<4) + +/* Bit definitions and macros for MCF_ESW_VIMEN */ +#define MCF_ESW_VIMEN_EN0 (0x00000001) +#define MCF_ESW_VIMEN_EN1 (0x00000002) +#define MCF_ESW_VIMEN_EN2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_VID */ +#define MCF_ESW_VID_TAG(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_MCR */ +#define MCF_ESW_MCR_PORT(x) (((x)&0x0000000F)<<0) +#define MCF_ESW_MCR_MEN (0x00000010) +#define MCF_ESW_MCR_INGMAP (0x00000020) +#define MCF_ESW_MCR_EGMAP (0x00000040) +#define MCF_ESW_MCR_INGSA (0x00000080) +#define MCF_ESW_MCR_INGDA (0x00000100) +#define MCF_ESW_MCR_EGSA (0x00000200) +#define MCF_ESW_MCR_EGDA (0x00000400) + +/* Bit definitions and macros for MCF_ESW_EGMAP */ +#define MCF_ESW_EGMAP_EG0 (0x00000001) +#define MCF_ESW_EGMAP_EG1 (0x00000002) +#define MCF_ESW_EGMAP_EG2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_INGMAP */ +#define MCF_ESW_INGMAP_ING0 (0x00000001) +#define MCF_ESW_INGMAP_ING1 (0x00000002) +#define MCF_ESW_INGMAP_ING2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_INGSAL */ +#define MCF_ESW_INGSAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_INGSAH */ +#define MCF_ESW_INGSAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_INGDAL */ +#define MCF_ESW_INGDAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_INGDAH */ +#define MCF_ESW_INGDAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_ENGSAL */ +#define MCF_ESW_ENGSAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_ENGSAH */ +#define MCF_ESW_ENGSAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_ENGDAL */ +#define MCF_ESW_ENGDAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_ENGDAH */ +#define MCF_ESW_ENGDAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_MCVAL */ +#define MCF_ESW_MCVAL_COUNT(x) (((x)&0x000000FF)<<0) + +/* Bit definitions and macros for MCF_ESW_MMSR */ +#define MCF_ESW_MMSR_BUSY (0x00000001) +#define MCF_ESW_MMSR_NOCELL (0x00000002) +#define MCF_ESW_MMSR_MEMFULL (0x00000004) +#define MCF_ESW_MMSR_MFLATCH (0x00000008) +#define MCF_ESW_MMSR_DQ_GRNT (0x00000040) +#define MCF_ESW_MMSR_CELLS_AVAIL(x) (((x)&0x000000FF)<<16) + +/* Bit definitions and macros for MCF_ESW_LMT */ +#define MCF_ESW_LMT_THRESH(x) (((x)&0x000000FF)<<0) + +/* Bit definitions and macros for MCF_ESW_LFC */ +#define MCF_ESW_LFC_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_PCSR */ +#define MCF_ESW_PCSR_PC0 (0x00000001) +#define MCF_ESW_PCSR_PC1 (0x00000002) +#define MCF_ESW_PCSR_PC2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_IOSR */ +#define MCF_ESW_IOSR_OR0 (0x00000001) +#define MCF_ESW_IOSR_OR1 (0x00000002) +#define MCF_ESW_IOSR_OR2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_QWT */ +#define MCF_ESW_QWT_Q0WT(x) (((x)&0x0000001F)<<0) +#define MCF_ESW_QWT_Q1WT(x) (((x)&0x0000001F)<<8) +#define MCF_ESW_QWT_Q2WT(x) (((x)&0x0000001F)<<16) +#define MCF_ESW_QWT_Q3WT(x) (((x)&0x0000001F)<<24) + +/* Bit definitions and macros for MCF_ESW_P0BCT */ +#define MCF_ESW_P0BCT_THRESH(x) (((x)&0x000000FF)<<0) + +/* Bit definitions and macros for MCF_ESW_P0FFEN */ +#define MCF_ESW_P0FFEN_FEN (0x00000001) +#define MCF_ESW_P0FFEN_FD(x) (((x)&0x00000003)<<2) + +/* Bit definitions and macros for MCF_ESW_PSNP */ +#define MCF_ESW_PSNP_EN (0x00000001) +#define MCF_ESW_PSNP_MODE(x) (((x)&0x00000003)<<1) +#define MCF_ESW_PSNP_CD (0x00000008) +#define MCF_ESW_PSNP_CS (0x00000010) +#define MCF_ESW_PSNP_PORT_COMPARE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_ESW_IPSNP */ +#define MCF_ESW_IPSNP_EN (0x00000001) +#define MCF_ESW_IPSNP_MODE(x) (((x)&0x00000003)<<1) +#define MCF_ESW_IPSNP_PROTOCOL(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_ESW_PVRES */ +#define MCF_ESW_PVRES_PRI0(x) (((x)&0x00000007)<<0) +#define MCF_ESW_PVRES_PRI1(x) (((x)&0x00000007)<<3) +#define MCF_ESW_PVRES_PRI2(x) (((x)&0x00000007)<<6) +#define MCF_ESW_PVRES_PRI3(x) (((x)&0x00000007)<<9) +#define MCF_ESW_PVRES_PRI4(x) (((x)&0x00000007)<<12) +#define MCF_ESW_PVRES_PRI5(x) (((x)&0x00000007)<<15) +#define MCF_ESW_PVRES_PRI6(x) (((x)&0x00000007)<<18) +#define MCF_ESW_PVRES_PRI7(x) (((x)&0x00000007)<<21) + +/* Bit definitions and macros for MCF_ESW_IPRES */ +#define MCF_ESW_IPRES_ADDRESS(x) (((x)&0x000000FF)<<0) +#define MCF_ESW_IPRES_IPV4SEL (0x00000100) +#define MCF_ESW_IPRES_PRI0(x) (((x)&0x00000003)<<9) +#define MCF_ESW_IPRES_PRI1(x) (((x)&0x00000003)<<11) +#define MCF_ESW_IPRES_PRI2(x) (((x)&0x00000003)<<13) +#define MCF_ESW_IPRES_READ (0x80000000) + +/* Bit definitions and macros for MCF_ESW_PRES */ +#define MCF_ESW_PRES_VLAN (0x00000001) +#define MCF_ESW_PRES_IP (0x00000002) +#define MCF_ESW_PRES_MAC (0x00000004) +#define MCF_ESW_PRES_DFLT_PRI(x) (((x)&0x00000007)<<4) + +/* Bit definitions and macros for MCF_ESW_PID */ +#define MCF_ESW_PID_VLANID(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_VRES */ +#define MCF_ESW_VRES_P0 (0x00000001) +#define MCF_ESW_VRES_P1 (0x00000002) +#define MCF_ESW_VRES_P2 (0x00000004) +#define MCF_ESW_VRES_VLANID(x) (((x)&0x00000FFF)<<3) + +/* Bit definitions and macros for MCF_ESW_DISCN */ +#define MCF_ESW_DISCN_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_DISCB */ +#define MCF_ESW_DISCB_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_NDISCN */ +#define MCF_ESW_NDISCN_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_NDISCB */ +#define MCF_ESW_NDISCB_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_POQC */ +#define MCF_ESW_POQC_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_PMVID */ +#define MCF_ESW_PMVID_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_PMVTAG */ +#define MCF_ESW_PMVTAG_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_PBL */ +#define MCF_ESW_PBL_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_ISR */ +#define MCF_ESW_ISR_EBERR (0x00000001) +#define MCF_ESW_ISR_RXB (0x00000002) +#define MCF_ESW_ISR_RXF (0x00000004) +#define MCF_ESW_ISR_TXB (0x00000008) +#define MCF_ESW_ISR_TXF (0x00000010) +#define MCF_ESW_ISR_QM (0x00000020) +#define MCF_ESW_ISR_OD0 (0x00000040) +#define MCF_ESW_ISR_OD1 (0x00000080) +#define MCF_ESW_ISR_OD2 (0x00000100) +#define MCF_ESW_ISR_LRN (0x00000200) + +/* Bit definitions and macros for MCF_ESW_IMR */ +#define MCF_ESW_IMR_EBERR (0x00000001) +#define MCF_ESW_IMR_RXB (0x00000002) +#define MCF_ESW_IMR_RXF (0x00000004) +#define MCF_ESW_IMR_TXB (0x00000008) +#define MCF_ESW_IMR_TXF (0x00000010) +#define MCF_ESW_IMR_QM (0x00000020) +#define MCF_ESW_IMR_OD0 (0x00000040) +#define MCF_ESW_IMR_OD1 (0x00000080) +#define MCF_ESW_IMR_OD2 (0x00000100) +#define MCF_ESW_IMR_LRN (0x00000200) + +/* Bit definitions and macros for MCF_ESW_RDSR */ +#define MCF_ESW_RDSR_ADDRESS(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_ESW_TDSR */ +#define MCF_ESW_TDSR_ADDRESS(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_ESW_MRBR */ +#define MCF_ESW_MRBR_SIZE(x) (((x)&0x000003FF)<<4) + +/* Bit definitions and macros for MCF_ESW_RDAR */ +#define MCF_ESW_RDAR_R_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_ESW_TDAR */ +#define MCF_ESW_TDAR_X_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_ESW_LREC0 */ +#define MCF_ESW_LREC0_MACADDR0(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_LREC1 */ +#define MCF_ESW_LREC1_MACADDR1(x) (((x)&0x0000FFFF)<<0) +#define MCF_ESW_LREC1_HASH(x) (((x)&0x000000FF)<<16) +#define MCF_ESW_LREC1_SWPORT(x) (((x)&0x00000003)<<24) + +/* Bit definitions and macros for MCF_ESW_LSR */ +#define MCF_ESW_LSR_DA (0x00000001) + +#endif /* SWITCH_H */ diff --git a/drivers/regulator/max17135-regulator.c b/drivers/regulator/max17135-regulator.c new file mode 100644 index 000000000000..a667c2f7cf59 --- /dev/null +++ b/drivers/regulator/max17135-regulator.c @@ -0,0 +1,749 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * PMIC Register Addresses + */ +enum { + REG_MAX17135_EXT_TEMP = 0x0, + REG_MAX17135_CONFIG, + REG_MAX17135_INT_TEMP = 0x4, + REG_MAX17135_STATUS, + REG_MAX17135_PRODUCT_REV, + REG_MAX17135_PRODUCT_ID, + REG_MAX17135_DVR, + REG_MAX17135_ENABLE, + REG_MAX17135_FAULT, /*0x0A*/ + REG_MAX17135_HVINP, + REG_MAX17135_PRGM_CTRL, + REG_MAX17135_TIMING1 = 0x10, /* Timing regs base address is 0x10 */ + REG_MAX17135_TIMING2, + REG_MAX17135_TIMING3, + REG_MAX17135_TIMING4, + REG_MAX17135_TIMING5, + REG_MAX17135_TIMING6, + REG_MAX17135_TIMING7, + REG_MAX17135_TIMING8, +}; +#define MAX17135_REG_NUM 21 +#define MAX17135_MAX_REGISTER 0xFF + +/* + * Bitfield macros that use rely on bitfield width/shift information. + */ +#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH)) +#define BITFVAL(field, val) ((val) << (field ## _LSH)) +#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH)) + +/* + * Shift and width values for each register bitfield + */ +#define EXT_TEMP_LSH 7 +#define EXT_TEMP_WID 9 + +#define THERMAL_SHUTDOWN_LSH 0 +#define THERMAL_SHUTDOWN_WID 1 + +#define INT_TEMP_LSH 7 +#define INT_TEMP_WID 9 + +#define STAT_BUSY_LSH 0 +#define STAT_BUSY_WID 1 +#define STAT_OPEN_LSH 1 +#define STAT_OPEN_WID 1 +#define STAT_SHRT_LSH 2 +#define STAT_SHRT_WID 1 + +#define PROD_REV_LSH 0 +#define PROD_REV_WID 8 + +#define PROD_ID_LSH 0 +#define PROD_ID_WID 8 + +#define DVR_LSH 0 +#define DVR_WID 8 + +#define ENABLE_LSH 0 +#define ENABLE_WID 1 +#define VCOM_ENABLE_LSH 1 +#define VCOM_ENABLE_WID 1 + +#define FAULT_FBPG_LSH 0 +#define FAULT_FBPG_WID 1 +#define FAULT_HVINP_LSH 1 +#define FAULT_HVINP_WID 1 +#define FAULT_HVINN_LSH 2 +#define FAULT_HVINN_WID 1 +#define FAULT_FBNG_LSH 3 +#define FAULT_FBNG_WID 1 +#define FAULT_HVINPSC_LSH 4 +#define FAULT_HVINPSC_WID 1 +#define FAULT_HVINNSC_LSH 5 +#define FAULT_HVINNSC_WID 1 +#define FAULT_OT_LSH 6 +#define FAULT_OT_WID 1 +#define FAULT_POK_LSH 7 +#define FAULT_POK_WID 1 + +#define HVINP_LSH 0 +#define HVINP_WID 4 + +#define CTRL_DVR_LSH 0 +#define CTRL_DVR_WID 1 +#define CTRL_TIMING_LSH 1 +#define CTRL_TIMING_WID 1 + +#define TIMING1_LSH 0 +#define TIMING1_WID 8 +#define TIMING2_LSH 0 +#define TIMING2_WID 8 +#define TIMING3_LSH 0 +#define TIMING3_WID 8 +#define TIMING4_LSH 0 +#define TIMING4_WID 8 +#define TIMING5_LSH 0 +#define TIMING5_WID 8 +#define TIMING6_LSH 0 +#define TIMING6_WID 8 +#define TIMING7_LSH 0 +#define TIMING7_WID 8 +#define TIMING8_LSH 0 +#define TIMING8_WID 8 + +/* + * Regulator definitions + * *_MIN_uV - minimum microvolt for regulator + * *_MAX_uV - maximum microvolt for regulator + * *_STEP_uV - microvolts between regulator output levels + * *_MIN_VAL - minimum register field value for regulator + * *_MAX_VAL - maximum register field value for regulator + */ +#define MAX17135_HVINP_MIN_uV 5000000 +#define MAX17135_HVINP_MAX_uV 20000000 +#define MAX17135_HVINP_STEP_uV 1000000 +#define MAX17135_HVINP_MIN_VAL 0 +#define MAX17135_HVINP_MAX_VAL 1 + +#define MAX17135_HVINN_MIN_uV 5000000 +#define MAX17135_HVINN_MAX_uV 20000000 +#define MAX17135_HVINN_STEP_uV 1000000 +#define MAX17135_HVINN_MIN_VAL 0 +#define MAX17135_HVINN_MAX_VAL 1 + +#define MAX17135_GVDD_MIN_uV 5000000 +#define MAX17135_GVDD_MAX_uV 20000000 +#define MAX17135_GVDD_STEP_uV 1000000 +#define MAX17135_GVDD_MIN_VAL 0 +#define MAX17135_GVDD_MAX_VAL 1 + +#define MAX17135_GVEE_MIN_uV 5000000 +#define MAX17135_GVEE_MAX_uV 20000000 +#define MAX17135_GVEE_STEP_uV 1000000 +#define MAX17135_GVEE_MIN_VAL 0 +#define MAX17135_GVEE_MAX_VAL 1 + +#define MAX17135_VCOM_MIN_VAL 0 +#define MAX17135_VCOM_MAX_VAL 255 + +#define MAX17135_VNEG_MIN_uV 5000000 +#define MAX17135_VNEG_MAX_uV 20000000 +#define MAX17135_VNEG_STEP_uV 1000000 +#define MAX17135_VNEG_MIN_VAL 0 +#define MAX17135_VNEG_MAX_VAL 1 + +#define MAX17135_VPOS_MIN_uV 5000000 +#define MAX17135_VPOS_MAX_uV 20000000 +#define MAX17135_VPOS_STEP_uV 1000000 +#define MAX17135_VPOS_MIN_VAL 0 +#define MAX17135_VPOS_MAX_VAL 1 + +struct max17135_vcom_programming_data { + int vcom_min_uV; + int vcom_max_uV; + int vcom_step_uV; +}; + +struct max17135_vcom_programming_data vcom_data[2] = { + { + -4325000, + -500000, + 15000, + }, + { + -3050000, + -500000, + 10000, + }, +}; + +struct max17135 { + /* chip revision */ + int rev; + + struct device *dev; + + /* Platform connection */ + struct i2c_client *i2c_client; + + /* Client devices */ + struct platform_device *pdev[MAX17135_REG_NUM]; + + /* GPIOs */ + int gpio_pmic_pwrgood; + int gpio_pmic_vcom_ctrl; + int gpio_pmic_wakeup; + int gpio_pmic_intr; + + int pass_num; + int vcom_uV; + + bool vcom_setup; + + int max_wait; +}; + +/* + * Regulator operations + */ +static int max17135_hvinp_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int reg_val; + unsigned int fld_val; + struct max17135 *max17135 = rdev_get_drvdata(reg); + struct i2c_client *client = max17135->i2c_client; + + if ((uV >= MAX17135_HVINP_MIN_uV) && + (uV <= MAX17135_HVINP_MAX_uV)) + fld_val = (uV - MAX17135_HVINP_MIN_uV) / + MAX17135_HVINP_STEP_uV; + else + return -EINVAL; + + reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_HVINP); + + reg_val &= ~BITFMASK(HVINP); + reg_val |= BITFVAL(HVINP, fld_val); /* shift to correct bit */ + + return i2c_smbus_write_byte_data(client, REG_MAX17135_HVINP, reg_val); +} + +static int max17135_hvinp_get_voltage(struct regulator_dev *reg) +{ + unsigned int reg_val; + unsigned int fld_val; + int volt; + struct max17135 *max17135 = rdev_get_drvdata(reg); + struct i2c_client *client = max17135->i2c_client; + + reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_HVINP); + + fld_val = (reg_val & BITFMASK(HVINP)) >> HVINP_LSH; + + if ((fld_val >= MAX17135_HVINP_MIN_VAL) && + (fld_val <= MAX17135_HVINP_MAX_VAL)) { + volt = (fld_val * MAX17135_HVINP_STEP_uV) + + MAX17135_HVINP_MIN_uV; + } else { + printk(KERN_ERR "MAX17135: HVINP voltage is out of range\n"); + volt = 0; + } + return volt; +} + +static int max17135_hvinp_enable(struct regulator_dev *reg) +{ + return 0; +} + +static int max17135_hvinp_disable(struct regulator_dev *reg) +{ + return 0; +} + +/* Convert uV to the VCOM register bitfield setting */ +static inline int vcom_uV_to_rs(int uV, int pass_num) +{ + return (vcom_data[pass_num].vcom_max_uV - uV) + / vcom_data[pass_num].vcom_step_uV; +} + +/* Convert the VCOM register bitfield setting to uV */ +static inline int vcom_rs_to_uV(int rs, int pass_num) +{ + return vcom_data[pass_num].vcom_max_uV + - (vcom_data[pass_num].vcom_step_uV * rs); +} + +static int max17135_vcom_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + struct i2c_client *client = max17135->i2c_client; + unsigned int reg_val; + int vcom_read; + + if ((uV < vcom_data[max17135->pass_num-1].vcom_min_uV) + || (uV > vcom_data[max17135->pass_num-1].vcom_max_uV)) + return -EINVAL; + + reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_DVR); + + /* + * Only program VCOM if it is not set to the desired value. + * Programming VCOM excessively degrades ability to keep + * DVR register value persistent. + */ + vcom_read = vcom_rs_to_uV(reg_val, max17135->pass_num-1); + if (vcom_read != max17135->vcom_uV) { + reg_val &= ~BITFMASK(DVR); + reg_val |= BITFVAL(DVR, vcom_uV_to_rs(uV, + max17135->pass_num-1)); + i2c_smbus_write_byte_data(client, REG_MAX17135_DVR, reg_val); + + reg_val = BITFVAL(CTRL_DVR, true); /* shift to correct bit */ + return i2c_smbus_write_byte_data(client, + REG_MAX17135_PRGM_CTRL, reg_val); + } +} + +static int max17135_vcom_get_voltage(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + struct i2c_client *client = max17135->i2c_client; + unsigned int reg_val; + + reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_DVR); + return vcom_rs_to_uV(BITFEXT(reg_val, DVR), max17135->pass_num-1); +} + +static int max17135_vcom_enable(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + + /* + * Check to see if we need to set the VCOM voltage. + * Should only be done one time. And, we can + * only change vcom voltage if we have been enabled. + */ + if (!max17135->vcom_setup + && gpio_get_value(max17135->gpio_pmic_pwrgood)) { + max17135_vcom_set_voltage(reg, + max17135->vcom_uV, + max17135->vcom_uV); + max17135->vcom_setup = true; + } + + /* enable VCOM regulator output */ + if (max17135->pass_num == 1) + gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 1); + else { + struct i2c_client *client = max17135->i2c_client; + unsigned int reg_val; + + reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_ENABLE); + reg_val &= ~BITFMASK(VCOM_ENABLE); + reg_val |= BITFVAL(VCOM_ENABLE, 1); /* shift to correct bit */ + i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, reg_val); + } + + return 0; +} + +static int max17135_vcom_disable(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + if (max17135->pass_num == 1) + gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 0); + else { + struct i2c_client *client = max17135->i2c_client; + unsigned int reg_val; + + reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_ENABLE); + reg_val &= ~BITFMASK(VCOM_ENABLE); + i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, reg_val); + } + + return 0; +} + +static int max17135_wait_power_good(struct max17135 *max17135) +{ + int i; + + for (i = 0; i < max17135->max_wait * 3; i++) { + if (gpio_get_value(max17135->gpio_pmic_pwrgood)) + return 0; + + msleep(1); + } + return -ETIMEDOUT; +} + +static int max17135_display_enable(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + + /* The Pass 1 parts cannot turn on the PMIC via I2C. */ + if (max17135->pass_num == 1) + gpio_set_value(max17135->gpio_pmic_wakeup, 1); + else { + struct i2c_client *client = max17135->i2c_client; + unsigned int reg_val; + + reg_val = i2c_smbus_read_byte_data(client, + REG_MAX17135_ENABLE); + reg_val &= ~BITFMASK(ENABLE); + reg_val |= BITFVAL(ENABLE, 1); + i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, + reg_val); + } + + return max17135_wait_power_good(max17135); +} + +static int max17135_display_disable(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + + if (max17135->pass_num == 1) + gpio_set_value(max17135->gpio_pmic_wakeup, 0); + else { + struct i2c_client *client = max17135->i2c_client; + unsigned int reg_val; + + reg_val = i2c_smbus_read_byte_data(client, + REG_MAX17135_ENABLE); + reg_val &= ~BITFMASK(ENABLE); + i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, + reg_val); + } + + return 0; +} + +static int max17135_display_is_enabled(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + int gpio = gpio_get_value(max17135->gpio_pmic_wakeup); + + if (gpio == 0) + return 0; + else + return 1; +} + +/* + * Regulator operations + */ + +static struct regulator_ops max17135_display_ops = { + .enable = max17135_display_enable, + .disable = max17135_display_disable, + .is_enabled = max17135_display_is_enabled, +}; + +static struct regulator_ops max17135_gvdd_ops = { +}; + +static struct regulator_ops max17135_gvee_ops = { +}; + +static struct regulator_ops max17135_hvinn_ops = { +}; + +static struct regulator_ops max17135_hvinp_ops = { + .enable = max17135_hvinp_enable, + .disable = max17135_hvinp_disable, + .get_voltage = max17135_hvinp_get_voltage, + .set_voltage = max17135_hvinp_set_voltage, +}; + +static struct regulator_ops max17135_vcom_ops = { + .enable = max17135_vcom_enable, + .disable = max17135_vcom_disable, + .get_voltage = max17135_vcom_get_voltage, + .set_voltage = max17135_vcom_set_voltage, +}; + +static struct regulator_ops max17135_vneg_ops = { +}; + +static struct regulator_ops max17135_vpos_ops = { +}; + +/* + * Regulator descriptors + */ +static struct regulator_desc max17135_reg[MAX17135_NUM_REGULATORS] = { +{ + .name = "DISPLAY", + .id = MAX17135_DISPLAY, + .ops = &max17135_display_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "GVDD", + .id = MAX17135_GVDD, + .ops = &max17135_gvdd_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "GVEE", + .id = MAX17135_GVEE, + .ops = &max17135_gvee_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "HVINN", + .id = MAX17135_HVINN, + .ops = &max17135_hvinn_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "HVINP", + .id = MAX17135_HVINP, + .ops = &max17135_hvinp_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "VCOM", + .id = MAX17135_VCOM, + .ops = &max17135_vcom_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "VNEG", + .id = MAX17135_VNEG, + .ops = &max17135_vneg_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "VPOS", + .id = MAX17135_VPOS, + .ops = &max17135_vpos_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +}; + +/* + * Regulator init/probing/exit functions + */ +static int max17135_regulator_probe(struct platform_device *pdev) +{ + struct regulator_dev *rdev; + + rdev = regulator_register(&max17135_reg[pdev->id], &pdev->dev, + pdev->dev.platform_data, + dev_get_drvdata(&pdev->dev)); + + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + max17135_reg[pdev->id].name); + return PTR_ERR(rdev); + } + + return 0; +} + +static int max17135_regulator_remove(struct platform_device *pdev) +{ + struct regulator_dev *rdev = platform_get_drvdata(pdev); + regulator_unregister(rdev); + return 0; +} + +static struct platform_driver max17135_regulator_driver = { + .probe = max17135_regulator_probe, + .remove = max17135_regulator_remove, + .driver = { + .name = "max17135-reg", + }, +}; + +static int max17135_register_regulator(struct max17135 *max17135, int reg, + struct regulator_init_data *initdata) +{ + struct platform_device *pdev; + int ret; + + struct i2c_client *client = max17135->i2c_client; + /* If we can't find PMIC via I2C, we should not register regulators */ + if (i2c_smbus_read_byte_data(client, + REG_MAX17135_PRODUCT_REV >= 0)) { + dev_err(max17135->dev, + "Max17135 PMIC not found!\n"); + return -ENXIO; + } + + if (max17135->pdev[reg]) + return -EBUSY; + + pdev = platform_device_alloc("max17135-reg", reg); + if (!pdev) + return -ENOMEM; + + max17135->pdev[reg] = pdev; + + initdata->driver_data = max17135; + + pdev->dev.platform_data = initdata; + pdev->dev.parent = max17135->dev; + platform_set_drvdata(pdev, max17135); + + ret = platform_device_add(pdev); + + if (ret != 0) { + dev_err(max17135->dev, + "Failed to register regulator %d: %d\n", + reg, ret); + platform_device_del(pdev); + max17135->pdev[reg] = NULL; + } + + return ret; +} + +static int max17135_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int i; + struct max17135 *max17135; + struct max17135_platform_data *pdata = client->dev.platform_data; + int ret = 0; + + if (!pdata || !pdata->regulator_init) + return -ENODEV; + + /* Create the PMIC data structure */ + max17135 = kzalloc(sizeof(struct max17135), GFP_KERNEL); + if (max17135 == NULL) { + kfree(client); + return -ENOMEM; + } + + /* Initialize the PMIC data structure */ + i2c_set_clientdata(client, max17135); + max17135->dev = &client->dev; + max17135->i2c_client = client; + + max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood; + max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl; + max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup; + max17135->gpio_pmic_intr = pdata->gpio_pmic_intr; + + max17135->pass_num = pdata->pass_num; + max17135->vcom_uV = pdata->vcom_uV; + + max17135->vcom_setup = false; + + ret = platform_driver_register(&max17135_regulator_driver); + if (ret < 0) + goto err; + + for (i = 0; i <= MAX17135_VPOS; i++) { + ret = max17135_register_regulator(max17135, i, &pdata->regulator_init[i]); + if (ret != 0) { + dev_err(max17135->dev, "Platform init() failed: %d\n", + ret); + goto err; + } + } + + max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup + + pdata->gvdd_pwrup + pdata->gvee_pwrup; + + /* Initialize the PMIC device */ + dev_info(&client->dev, "PMIC MAX17135 for eInk display\n"); + + return ret; +err: + kfree(max17135); + + return ret; +} + + +static int max17135_i2c_remove(struct i2c_client *i2c) +{ + struct max17135 *max17135 = i2c_get_clientdata(i2c); + int i; + + for (i = 0; i < ARRAY_SIZE(max17135->pdev); i++) + platform_device_unregister(max17135->pdev[i]); + + platform_driver_unregister(&max17135_regulator_driver); + + kfree(max17135); + + return 0; +} + +static const struct i2c_device_id max17135_i2c_id[] = { + { "max17135", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, max17135_i2c_id); + + +static struct i2c_driver max17135_i2c_driver = { + .driver = { + .name = "max17135", + .owner = THIS_MODULE, + }, + .probe = max17135_i2c_probe, + .remove = max17135_i2c_remove, + .id_table = max17135_i2c_id, +}; + +static int __init max17135_init(void) +{ + return i2c_add_driver(&max17135_i2c_driver); +} +module_init(max17135_init); + +static void __exit max17135_exit(void) +{ + i2c_del_driver(&max17135_i2c_driver); +} +module_exit(max17135_exit); + +/* Module information */ +MODULE_DESCRIPTION("MAX17135 regulator driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/alarm.c b/drivers/rtc/alarm.c new file mode 100644 index 000000000000..9f6134b5fdc8 --- /dev/null +++ b/drivers/rtc/alarm.c @@ -0,0 +1,567 @@ +/* drivers/rtc/alarm.c + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ANDROID_ALARM_PRINT_ERRORS (1U << 0) +#define ANDROID_ALARM_PRINT_INIT_STATUS (1U << 1) +#define ANDROID_ALARM_PRINT_INFO (1U << 2) +#define ANDROID_ALARM_PRINT_IO (1U << 3) +#define ANDROID_ALARM_PRINT_INT (1U << 4) +#define ANDROID_ALARM_PRINT_FLOW (1U << 5) + +#if 0 +#define ANDROID_ALARM_DPRINTF_MASK (~0) +#define ANDROID_ALARM_DPRINTF(debug_level_mask, args...) \ + do { \ + if (ANDROID_ALARM_DPRINTF_MASK & debug_level_mask) { \ + printk(args); \ + } \ + } while (0) +#else +#define ANDROID_ALARM_DPRINTF(args...) +#endif + +#define ANDROID_ALARM_WAKEUP_MASK ( \ + ANDROID_ALARM_RTC_WAKEUP_MASK | \ + ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK) + +/* support old usespace code */ +#define ANDROID_ALARM_SET_OLD _IOW('a', 2, time_t) /* set alarm */ +#define ANDROID_ALARM_SET_AND_WAIT_OLD _IOW('a', 3, time_t) + +static struct rtc_device *alarm_rtc_dev; +static int alarm_opened; +static DEFINE_SPINLOCK(alarm_slock); +static DEFINE_MUTEX(alarm_setrtc_mutex); +static struct wake_lock alarm_wake_lock; +static struct wake_lock alarm_rtc_wake_lock; +static DECLARE_WAIT_QUEUE_HEAD(alarm_wait_queue); +static uint32_t alarm_pending; +static uint32_t alarm_enabled; +static uint32_t wait_pending; +static struct platform_device *alarm_platform_dev; +static struct hrtimer alarm_timer[ANDROID_ALARM_TYPE_COUNT]; +static struct timespec alarm_time[ANDROID_ALARM_TYPE_COUNT]; +static struct timespec elapsed_rtc_delta; + +static void alarm_start_hrtimer(enum android_alarm_type alarm_type) +{ + struct timespec hr_alarm_time; + if (!(alarm_enabled & (1U << alarm_type))) + return; + hr_alarm_time = alarm_time[alarm_type]; + if (alarm_type == ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP || + alarm_type == ANDROID_ALARM_ELAPSED_REALTIME) + set_normalized_timespec(&hr_alarm_time, + hr_alarm_time.tv_sec + elapsed_rtc_delta.tv_sec, + hr_alarm_time.tv_nsec + elapsed_rtc_delta.tv_nsec); + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, + "alarm start hrtimer %d at %ld.%09ld\n", + alarm_type, hr_alarm_time.tv_sec, hr_alarm_time.tv_nsec); + hrtimer_start(&alarm_timer[alarm_type], + timespec_to_ktime(hr_alarm_time), HRTIMER_MODE_ABS); +} + +static long alarm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int rv = 0; + unsigned long flags; + int i; + struct timespec new_alarm_time; + struct timespec new_rtc_time; + struct timespec tmp_time; + struct rtc_time rtc_new_rtc_time; + enum android_alarm_type alarm_type = ANDROID_ALARM_IOCTL_TO_TYPE(cmd); + uint32_t alarm_type_mask = 1U << alarm_type; + + if (alarm_type >= ANDROID_ALARM_TYPE_COUNT) + return -EINVAL; + + if (ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_GET_TIME(0)) { + if ((file->f_flags & O_ACCMODE) == O_RDONLY) + return -EPERM; + if (file->private_data == NULL && + cmd != ANDROID_ALARM_SET_RTC) { + spin_lock_irqsave(&alarm_slock, flags); + if (alarm_opened) { + spin_unlock_irqrestore(&alarm_slock, flags); + return -EBUSY; + } + alarm_opened = 1; + file->private_data = (void *)1; + spin_unlock_irqrestore(&alarm_slock, flags); + } + } + + switch (ANDROID_ALARM_BASE_CMD(cmd)) { + case ANDROID_ALARM_CLEAR(0): + spin_lock_irqsave(&alarm_slock, flags); + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, + "alarm %d clear\n", alarm_type); + hrtimer_try_to_cancel(&alarm_timer[alarm_type]); + if (alarm_pending) { + alarm_pending &= ~alarm_type_mask; + if (!alarm_pending && !wait_pending) + wake_unlock(&alarm_wake_lock); + } + alarm_enabled &= ~alarm_type_mask; + spin_unlock_irqrestore(&alarm_slock, flags); + break; + + case ANDROID_ALARM_SET_OLD: + case ANDROID_ALARM_SET_AND_WAIT_OLD: + if (get_user(new_alarm_time.tv_sec, (int __user *)arg)) { + rv = -EFAULT; + goto err1; + } + new_alarm_time.tv_nsec = 0; + goto from_old_alarm_set; + + case ANDROID_ALARM_SET_AND_WAIT(0): + case ANDROID_ALARM_SET(0): + if (copy_from_user(&new_alarm_time, (void __user *)arg, + sizeof(new_alarm_time))) { + rv = -EFAULT; + goto err1; + } +from_old_alarm_set: + spin_lock_irqsave(&alarm_slock, flags); + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, + "alarm %d set %ld.%09ld\n", alarm_type, + new_alarm_time.tv_sec, new_alarm_time.tv_nsec); + alarm_time[alarm_type] = new_alarm_time; + alarm_enabled |= alarm_type_mask; + alarm_start_hrtimer(alarm_type); + spin_unlock_irqrestore(&alarm_slock, flags); + if (ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_SET_AND_WAIT(0) + && cmd != ANDROID_ALARM_SET_AND_WAIT_OLD) + break; + /* fall though */ + case ANDROID_ALARM_WAIT: + spin_lock_irqsave(&alarm_slock, flags); + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, "alarm wait\n"); + if (!alarm_pending && wait_pending) { + wake_unlock(&alarm_wake_lock); + wait_pending = 0; + } + spin_unlock_irqrestore(&alarm_slock, flags); + rv = wait_event_interruptible(alarm_wait_queue, alarm_pending); + if (rv) + goto err1; + spin_lock_irqsave(&alarm_slock, flags); + rv = alarm_pending; + wait_pending = 1; + alarm_pending = 0; + if (rv & ANDROID_ALARM_WAKEUP_MASK) + wake_unlock(&alarm_rtc_wake_lock); + spin_unlock_irqrestore(&alarm_slock, flags); + break; + case ANDROID_ALARM_SET_RTC: + if (copy_from_user(&new_rtc_time, (void __user *)arg, + sizeof(new_rtc_time))) { + rv = -EFAULT; + goto err1; + } + rtc_time_to_tm(new_rtc_time.tv_sec, &rtc_new_rtc_time); + + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, + "set rtc %ld %ld - rtc %02d:%02d:%02d %02d/%02d/%04d\n", + new_rtc_time.tv_sec, new_rtc_time.tv_nsec, + rtc_new_rtc_time.tm_hour, rtc_new_rtc_time.tm_min, + rtc_new_rtc_time.tm_sec, rtc_new_rtc_time.tm_mon + 1, + rtc_new_rtc_time.tm_mday, + rtc_new_rtc_time.tm_year + 1900); + + mutex_lock(&alarm_setrtc_mutex); + spin_lock_irqsave(&alarm_slock, flags); + for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++) + hrtimer_try_to_cancel(&alarm_timer[i]); + getnstimeofday(&tmp_time); + elapsed_rtc_delta = timespec_sub(elapsed_rtc_delta, + timespec_sub(tmp_time, new_rtc_time)); + spin_unlock_irqrestore(&alarm_slock, flags); + rv = do_settimeofday(&new_rtc_time); + spin_lock_irqsave(&alarm_slock, flags); + for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++) + alarm_start_hrtimer(i); + spin_unlock_irqrestore(&alarm_slock, flags); + if (rv < 0) { + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_ERRORS, + "Failed to set time\n"); + mutex_unlock(&alarm_setrtc_mutex); + goto err1; + } + rv = rtc_set_time(alarm_rtc_dev, &rtc_new_rtc_time); + spin_lock_irqsave(&alarm_slock, flags); + alarm_pending |= ANDROID_ALARM_TIME_CHANGE_MASK; + wake_up(&alarm_wait_queue); + spin_unlock_irqrestore(&alarm_slock, flags); + mutex_unlock(&alarm_setrtc_mutex); + if (rv < 0) { + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_ERRORS, + "Failed to set RTC, time will be lost on reboot\n"); + goto err1; + } + break; + case ANDROID_ALARM_GET_TIME(0): + mutex_lock(&alarm_setrtc_mutex); + spin_lock_irqsave(&alarm_slock, flags); + if (alarm_type != ANDROID_ALARM_SYSTEMTIME) { + getnstimeofday(&tmp_time); + if (alarm_type >= ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP) + tmp_time = timespec_sub(tmp_time, + elapsed_rtc_delta); + } else + ktime_get_ts(&tmp_time); + spin_unlock_irqrestore(&alarm_slock, flags); + mutex_unlock(&alarm_setrtc_mutex); + if (copy_to_user((void __user *)arg, &tmp_time, + sizeof(tmp_time))) { + rv = -EFAULT; + goto err1; + } + break; + + default: + rv = -EINVAL; + goto err1; + } +err1: + return rv; +} + +static int alarm_open(struct inode *inode, struct file *file) +{ + file->private_data = NULL; + return 0; +} + +static int alarm_release(struct inode *inode, struct file *file) +{ + int i; + unsigned long flags; + + spin_lock_irqsave(&alarm_slock, flags); + if (file->private_data != 0) { + for (i = 0; i < ANDROID_ALARM_TYPE_COUNT; i++) { + uint32_t alarm_type_mask = 1U << i; + if (alarm_enabled & alarm_type_mask) { + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, + "alarm_release: clear alarm, " + "pending %d\n", + !!(alarm_pending & alarm_type_mask)); + alarm_enabled &= ~alarm_type_mask; + } + spin_unlock_irqrestore(&alarm_slock, flags); + hrtimer_cancel(&alarm_timer[i]); + spin_lock_irqsave(&alarm_slock, flags); + } + if (alarm_pending | wait_pending) { + if (alarm_pending) + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, + "alarm_release: clear pending alarms " + "%x\n", alarm_pending); + wake_unlock(&alarm_wake_lock); + wait_pending = 0; + alarm_pending = 0; + } + alarm_opened = 0; + } + spin_unlock_irqrestore(&alarm_slock, flags); + return 0; +} + +static enum hrtimer_restart alarm_timer_triggered(struct hrtimer *timer) +{ + unsigned long flags; + enum android_alarm_type alarm_type = (timer - alarm_timer); + uint32_t alarm_type_mask = 1U << alarm_type; + + + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INT, + "alarm_timer_triggered type %d\n", alarm_type); + spin_lock_irqsave(&alarm_slock, flags); + if (alarm_enabled & alarm_type_mask) { + wake_lock_timeout(&alarm_wake_lock, 5 * HZ); + alarm_enabled &= ~alarm_type_mask; + alarm_pending |= alarm_type_mask; + wake_up(&alarm_wait_queue); + } + spin_unlock_irqrestore(&alarm_slock, flags); + return HRTIMER_NORESTART; +} + +static void alarm_triggered_func(void *p) +{ + struct rtc_device *rtc = alarm_rtc_dev; + if (!(rtc->irq_data & RTC_AF)) + return; + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INT, "rtc alarm triggered\n"); + wake_lock_timeout(&alarm_rtc_wake_lock, 1 * HZ); +} + +int alarm_suspend(struct platform_device *pdev, pm_message_t state) +{ + int err = 0; + unsigned long flags; + struct rtc_wkalrm rtc_alarm; + struct rtc_time rtc_current_rtc_time; + unsigned long rtc_current_time; + unsigned long rtc_alarm_time; + struct timespec rtc_current_timespec; + struct timespec rtc_delta; + struct timespec elapsed_realtime_alarm_time; + + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, + "alarm_suspend(%p, %d)\n", pdev, state.event); + spin_lock_irqsave(&alarm_slock, flags); + if (alarm_pending && !wake_lock_active(&alarm_wake_lock)) { + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, + "alarm pending\n"); + err = -EBUSY; + goto err1; + } + if (alarm_enabled & ANDROID_ALARM_WAKEUP_MASK) { + spin_unlock_irqrestore(&alarm_slock, flags); + if (alarm_enabled & ANDROID_ALARM_RTC_WAKEUP_MASK) + hrtimer_cancel(&alarm_timer[ANDROID_ALARM_RTC_WAKEUP]); + if (alarm_enabled & ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK) + hrtimer_cancel(&alarm_timer[ + ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP]); + + rtc_read_time(alarm_rtc_dev, &rtc_current_rtc_time); + rtc_current_timespec.tv_nsec = 0; + rtc_tm_to_time(&rtc_current_rtc_time, + &rtc_current_timespec.tv_sec); + save_time_delta(&rtc_delta, &rtc_current_timespec); + set_normalized_timespec(&elapsed_realtime_alarm_time, + alarm_time[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP] + .tv_sec + elapsed_rtc_delta.tv_sec, + alarm_time[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP] + .tv_nsec + elapsed_rtc_delta.tv_nsec); + if ((alarm_enabled & ANDROID_ALARM_RTC_WAKEUP_MASK) && + (!(alarm_enabled & + ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK) || + timespec_compare(&alarm_time[ANDROID_ALARM_RTC_WAKEUP], + &elapsed_realtime_alarm_time) < 0)) + rtc_alarm_time = timespec_sub( + alarm_time[ANDROID_ALARM_RTC_WAKEUP], + rtc_delta).tv_sec; + else + rtc_alarm_time = timespec_sub( + elapsed_realtime_alarm_time, rtc_delta).tv_sec; + rtc_time_to_tm(rtc_alarm_time, &rtc_alarm.time); + rtc_alarm.enabled = 1; + rtc_set_alarm(alarm_rtc_dev, &rtc_alarm); + rtc_read_time(alarm_rtc_dev, &rtc_current_rtc_time); + rtc_tm_to_time(&rtc_current_rtc_time, &rtc_current_time); + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, + "rtc alarm set at %ld, now %ld, rtc delta %ld.%09ld\n", + rtc_alarm_time, rtc_current_time, + rtc_delta.tv_sec, rtc_delta.tv_nsec); + if (rtc_current_time + 1 >= rtc_alarm_time) { + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, + "alarm about to go off\n"); + memset(&rtc_alarm, 0, sizeof(rtc_alarm)); + rtc_alarm.enabled = 0; + rtc_set_alarm(alarm_rtc_dev, &rtc_alarm); + + spin_lock_irqsave(&alarm_slock, flags); + wake_lock_timeout(&alarm_rtc_wake_lock, 2 * HZ); + alarm_start_hrtimer(ANDROID_ALARM_RTC_WAKEUP); + alarm_start_hrtimer( + ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP); + err = -EBUSY; + spin_unlock_irqrestore(&alarm_slock, flags); + } + } else { +err1: + spin_unlock_irqrestore(&alarm_slock, flags); + } + return err; +} + +int alarm_resume(struct platform_device *pdev) +{ + struct rtc_wkalrm alarm; + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, + "alarm_resume(%p)\n", pdev); + if (alarm_enabled & ANDROID_ALARM_WAKEUP_MASK) { + memset(&alarm, 0, sizeof(alarm)); + alarm.enabled = 0; + rtc_set_alarm(alarm_rtc_dev, &alarm); + alarm_start_hrtimer(ANDROID_ALARM_RTC_WAKEUP); + alarm_start_hrtimer(ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP); + } + return 0; +} + +static struct rtc_task alarm_rtc_task = { + .func = alarm_triggered_func +}; + +static struct file_operations alarm_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = alarm_ioctl, + .open = alarm_open, + .release = alarm_release, +}; + +static struct miscdevice alarm_device = { + .minor = MISC_DYNAMIC_MINOR, + .name = "alarm", + .fops = &alarm_fops, +}; + +static int rtc_alarm_add_device(struct device *dev, + struct class_interface *class_intf) +{ + int err; + struct rtc_device *rtc = to_rtc_device(dev); + + mutex_lock(&alarm_setrtc_mutex); + + if (alarm_rtc_dev) { + err = -EBUSY; + goto err1; + } + + err = misc_register(&alarm_device); + if (err) + goto err1; + alarm_platform_dev = + platform_device_register_simple("alarm", -1, NULL, 0); + if (IS_ERR(alarm_platform_dev)) { + err = PTR_ERR(alarm_platform_dev); + goto err2; + } + err = rtc_irq_register(rtc, &alarm_rtc_task); + if (err) + goto err3; + alarm_rtc_dev = rtc; + mutex_unlock(&alarm_setrtc_mutex); + + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm: parent %p\n", + alarm_platform_dev->dev.power.pm_parent); + return 0; + +err3: + platform_device_unregister(alarm_platform_dev); +err2: + misc_deregister(&alarm_device); +err1: + mutex_unlock(&alarm_setrtc_mutex); + return err; +} + +static void rtc_alarm_remove_device(struct device *dev, + struct class_interface *class_intf) +{ + if (dev == &alarm_rtc_dev->dev) { + rtc_irq_unregister(alarm_rtc_dev, &alarm_rtc_task); + platform_device_unregister(alarm_platform_dev); + misc_deregister(&alarm_device); + alarm_rtc_dev = NULL; + } +} + +static struct class_interface rtc_alarm_interface = { + .add_dev = &rtc_alarm_add_device, + .remove_dev = &rtc_alarm_remove_device, +}; + +static struct platform_driver alarm_driver = { + .suspend = alarm_suspend, + .resume = alarm_resume, + .driver = { + .name = "alarm" + } +}; + +static int __init alarm_late_init(void) +{ + unsigned long flags; + struct timespec system_time; + + /* this needs to run after the rtc is read at boot */ + spin_lock_irqsave(&alarm_slock, flags); + /* We read the current rtc and system time so we can later calulate + * elasped realtime to be (boot_systemtime + rtc - boot_rtc) == + * (rtc - (boot_rtc - boot_systemtime)) + */ + getnstimeofday(&elapsed_rtc_delta); + ktime_get_ts(&system_time); + elapsed_rtc_delta = timespec_sub(elapsed_rtc_delta, system_time); + spin_unlock_irqrestore(&alarm_slock, flags); + + ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, + "alarm_late_init: rtc to elapsed realtime delta %ld.%09ld\n", + elapsed_rtc_delta.tv_sec, elapsed_rtc_delta.tv_nsec); + return 0; +} + +static int __init alarm_init(void) +{ + int err; + int i; + + for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++) { + hrtimer_init(&alarm_timer[i], CLOCK_REALTIME, HRTIMER_MODE_ABS); + alarm_timer[i].function = alarm_timer_triggered; + } + hrtimer_init(&alarm_timer[ANDROID_ALARM_SYSTEMTIME], + CLOCK_MONOTONIC, HRTIMER_MODE_ABS); + alarm_timer[ANDROID_ALARM_SYSTEMTIME].function = alarm_timer_triggered; + err = platform_driver_register(&alarm_driver); + if (err < 0) + goto err1; + wake_lock_init(&alarm_wake_lock, WAKE_LOCK_SUSPEND, "alarm"); + wake_lock_init(&alarm_rtc_wake_lock, WAKE_LOCK_SUSPEND, "alarm_rtc"); + rtc_alarm_interface.class = rtc_class; + err = class_interface_register(&rtc_alarm_interface); + if (err < 0) + goto err2; + + return 0; + +err2: + wake_lock_destroy(&alarm_rtc_wake_lock); + wake_lock_destroy(&alarm_wake_lock); + platform_driver_unregister(&alarm_driver); +err1: + return err; +} + +static void __exit alarm_exit(void) +{ + class_interface_unregister(&rtc_alarm_interface); + wake_lock_destroy(&alarm_rtc_wake_lock); + wake_lock_destroy(&alarm_wake_lock); + platform_driver_unregister(&alarm_driver); +} + +late_initcall(alarm_late_init); +module_init(alarm_init); +module_exit(alarm_exit); + diff --git a/drivers/spi/spi_mxs.c b/drivers/spi/spi_mxs.c new file mode 100644 index 000000000000..744be68d9433 --- /dev/null +++ b/drivers/spi/spi_mxs.c @@ -0,0 +1,711 @@ +/* + * Freescale MXS SPI master driver + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "spi_mxs.h" + +/* 0 means DMA modei(recommended, default), !0 - PIO mode */ +static int pio /* = 0 */ ; +static int debug; + +/** + * mxs_spi_init_hw + * + * Initialize the SSP port + */ +static int mxs_spi_init_hw(struct mxs_spi *ss) +{ + int err; + + ss->clk = clk_get(NULL, "ssp.0"); + if (IS_ERR(ss->clk)) { + err = PTR_ERR(ss->clk); + goto out; + } + clk_enable(ss->clk); + + mxs_reset_block((void *)ss->regs, 0); + mxs_dma_reset(ss->dma); + + return 0; + +out: + return err; +} + +static void mxs_spi_release_hw(struct mxs_spi *ss) +{ + if (ss->clk && !IS_ERR(ss->clk)) { + clk_disable(ss->clk); + clk_put(ss->clk); + } +} + +static int mxs_spi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) +{ + u8 bits_per_word; + u32 hz; + struct mxs_spi *ss /* = spi_master_get_devdata(spi->master) */ ; + u16 rate; + + ss = spi_master_get_devdata(spi->master); + + bits_per_word = spi->bits_per_word; + if (t && t->bits_per_word) + bits_per_word = t->bits_per_word; + + /* + Calculate speed: + - by default, use maximum speed from ssp clk + - if device overrides it, use it + - if transfer specifies other speed, use transfer's one + */ + hz = 1000 * ss->speed_khz / ss->divider; + if (spi->max_speed_hz) + hz = min(hz, spi->max_speed_hz); + if (t && t->speed_hz) + hz = min(hz, t->speed_hz); + + if (hz == 0) { + dev_err(&spi->dev, "Cannot continue with zero clock\n"); + return -EINVAL; + } + + if (bits_per_word != 8) { + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", + __func__, bits_per_word); + return -EINVAL; + } + + dev_dbg(&spi->dev, "Requested clk rate = %uHz, max = %ukHz/%d = %uHz\n", + hz, ss->speed_khz, ss->divider, + ss->speed_khz * 1000 / ss->divider); + + if (ss->speed_khz * 1000 / ss->divider < hz) { + dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n", + __func__, hz); + return -EINVAL; + } + + rate = 1000 * ss->speed_khz / ss->divider / hz; + + __raw_writel(BF_SSP_TIMING_CLOCK_DIVIDE(ss->divider) | + BF_SSP_TIMING_CLOCK_RATE(rate - 1), + ss->regs + HW_SSP_TIMING); + + __raw_writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | + BF_SSP_CTRL1_WORD_LENGTH + (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) | + ((spi->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) | + ((spi->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0) | + (pio ? 0 : BM_SSP_CTRL1_DMA_ENABLE), + ss->regs + HW_SSP_CTRL1); + + __raw_writel(0x00, ss->regs + HW_SSP_CMD0_SET); + + return 0; +} + +static void mxs_spi_cleanup(struct spi_device *spi) +{ + struct mxs_spi_platform_data *pdata = spi->dev.platform_data; + + if (pdata && pdata->hw_pin_release) + pdata->hw_pin_release(); +} + +/* the spi->mode bits understood by this driver: */ +#define MODEBITS (SPI_CPOL | SPI_CPHA) +static int mxs_spi_setup(struct spi_device *spi) +{ + struct mxs_spi_platform_data *pdata; + struct mxs_spi *ss; + int err = 0; + + ss = spi_master_get_devdata(spi->master); + + if (!spi->bits_per_word) + spi->bits_per_word = 8; + + if (spi->mode & ~MODEBITS) { + dev_err(&spi->dev, "%s: unsupported mode bits %x\n", + __func__, spi->mode & ~MODEBITS); + err = -EINVAL; + goto out; + } + + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w\n", + __func__, spi->mode & MODEBITS, spi->bits_per_word); + + pdata = spi->dev.platform_data; + + if (pdata && pdata->hw_pin_init) { + err = pdata->hw_pin_init(); + if (err) + goto out; + } + + err = mxs_spi_setup_transfer(spi, NULL); + if (err) + goto out2; + return 0; + +out2: + if (pdata && pdata->hw_pin_release) + pdata->hw_pin_release(); +out: + dev_err(&spi->dev, "Failed to setup transfer, error = %d\n", err); + return err; +} + +static inline u32 mxs_spi_cs(unsigned cs) +{ + return ((cs & 1) ? BM_SSP_CTRL0_WAIT_FOR_CMD : 0) | + ((cs & 2) ? BM_SSP_CTRL0_WAIT_FOR_IRQ : 0); +} + +static int mxs_spi_txrx_dma(struct mxs_spi *ss, int cs, + unsigned char *buf, dma_addr_t dma_buf, int len, + int *first, int *last, int write) +{ + u32 c0 = 0; + dma_addr_t spi_buf_dma = dma_buf; + int count, status = 0; + enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; + + c0 |= (*first ? BM_SSP_CTRL0_LOCK_CS : 0); + c0 |= (*last ? BM_SSP_CTRL0_IGNORE_CRC : 0); + c0 |= (write ? 0 : BM_SSP_CTRL0_READ); + c0 |= BM_SSP_CTRL0_DATA_XFER; + + c0 |= mxs_spi_cs(cs); + + c0 |= BF_SSP_CTRL0_XFER_COUNT(len); + + if (!dma_buf) + spi_buf_dma = dma_map_single(ss->master_dev, buf, len, dir); + + ss->pdesc->cmd.cmd.bits.bytes = len; + ss->pdesc->cmd.cmd.bits.pio_words = 1; + ss->pdesc->cmd.cmd.bits.wait4end = 1; + ss->pdesc->cmd.cmd.bits.dec_sem = 1; + ss->pdesc->cmd.cmd.bits.irq = 1; + ss->pdesc->cmd.cmd.bits.command = write ? DMA_READ : DMA_WRITE; + ss->pdesc->cmd.address = spi_buf_dma; + ss->pdesc->cmd.pio_words[0] = c0; + mxs_dma_desc_append(ss->dma, ss->pdesc); + + mxs_dma_reset(ss->dma); + mxs_dma_ack_irq(ss->dma); + mxs_dma_enable_irq(ss->dma, 1); + init_completion(&ss->done); + mxs_dma_enable(ss->dma); + wait_for_completion(&ss->done); + count = 10000; + while ((__raw_readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN) + && count--) + continue; + if (count <= 0) { + printk(KERN_ERR "%c: timeout on line %s:%d\n", + write ? 'W' : 'C', __func__, __LINE__); + status = -ETIMEDOUT; + } + + if (!dma_buf) + dma_unmap_single(ss->master_dev, spi_buf_dma, len, dir); + + return status; +} + +static inline void mxs_spi_enable(struct mxs_spi *ss) +{ + __raw_writel(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0_SET); + __raw_writel(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0_CLR); +} + +static inline void mxs_spi_disable(struct mxs_spi *ss) +{ + __raw_writel(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0_CLR); + __raw_writel(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0_SET); +} + +static int mxs_spi_txrx_pio(struct mxs_spi *ss, int cs, + unsigned char *buf, int len, + int *first, int *last, int write) +{ + int count; + + if (*first) { + mxs_spi_enable(ss); + *first = 0; + } + + __raw_writel(mxs_spi_cs(cs), ss->regs + HW_SSP_CTRL0_SET); + + while (len--) { + if (*last && len == 0) { + mxs_spi_disable(ss); + *last = 0; + } + __raw_writel(BM_SSP_CTRL0_XFER_COUNT, + ss->regs + HW_SSP_CTRL0_CLR); + __raw_writel(1, ss->regs + HW_SSP_CTRL0_SET); /* byte-by-byte */ + + if (write) + __raw_writel(BM_SSP_CTRL0_READ, + ss->regs + HW_SSP_CTRL0_CLR); + else + __raw_writel(BM_SSP_CTRL0_READ, + ss->regs + HW_SSP_CTRL0_SET); + + /* Run! */ + __raw_writel(BM_SSP_CTRL0_RUN, ss->regs + HW_SSP_CTRL0_SET); + count = 10000; + while (((__raw_readl(ss->regs + HW_SSP_CTRL0) & + BM_SSP_CTRL0_RUN) == 0) && count--) + continue; + if (count <= 0) { + printk(KERN_ERR "%c: timeout on line %s:%d\n", + write ? 'W' : 'C', __func__, __LINE__); + break; + } + + if (write) + __raw_writel(*buf, ss->regs + HW_SSP_DATA); + + /* Set TRANSFER */ + __raw_writel(BM_SSP_CTRL0_DATA_XFER, + ss->regs + HW_SSP_CTRL0_SET); + + if (!write) { + count = 10000; + while (count-- && + (__raw_readl(ss->regs + HW_SSP_STATUS) & + BM_SSP_STATUS_FIFO_EMPTY)) + continue; + if (count <= 0) { + printk(KERN_ERR "%c: timeout on line %s:%d\n", + write ? 'W' : 'C', __func__, __LINE__); + break; + } + *buf = (__raw_readl(ss->regs + HW_SSP_DATA) & 0xFF); + } + + count = 10000; + while ((__raw_readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN) + && count--) + continue; + if (count <= 0) { + printk(KERN_ERR "%c: timeout on line %s:%d\n", + write ? 'W' : 'C', __func__, __LINE__); + break; + } + + /* advance to the next byte */ + buf++; + } + return len < 0 ? 0 : -ETIMEDOUT; +} + +static int mxs_spi_handle_message(struct mxs_spi *ss, struct spi_message *m) +{ + int first, last; + struct spi_transfer *t, *tmp_t; + int status = 0; + int cs; + + first = last = 0; + + cs = m->spi->chip_select; + + list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) { + + mxs_spi_setup_transfer(m->spi, t); + + if (&t->transfer_list == m->transfers.next) + first = !0; + if (&t->transfer_list == m->transfers.prev) + last = !0; + if (t->rx_buf && t->tx_buf) { + pr_debug("%s: cannot send and receive simultaneously\n", + __func__); + return -EINVAL; + } + + /* + REVISIT: + here driver completely ignores setting of t->cs_change + */ + if (t->tx_buf) { + status = pio ? + mxs_spi_txrx_pio(ss, cs, (void *)t->tx_buf, + t->len, &first, &last, 1) : + mxs_spi_txrx_dma(ss, cs, (void *)t->tx_buf, + t->tx_dma, t->len, &first, &last, + 1); + if (debug) { + if (t->len < 0x10) + print_hex_dump_bytes("Tx ", + DUMP_PREFIX_OFFSET, + t->tx_buf, t->len); + else + pr_debug("Tx: %d bytes\n", t->len); + } + } + if (t->rx_buf) { + status = pio ? + mxs_spi_txrx_pio(ss, cs, t->rx_buf, + t->len, &first, &last, 0) : + mxs_spi_txrx_dma(ss, cs, t->rx_buf, + t->rx_dma, t->len, &first, &last, + 0); + if (debug) { + if (t->len < 0x10) + print_hex_dump_bytes("Rx ", + DUMP_PREFIX_OFFSET, + t->rx_buf, t->len); + else + pr_debug("Rx: %d bytes\n", t->len); + } + } + + if (status) + break; + + first = last = 0; + + } + return status; +} + +/** + * mxs_spi_handle + * + * The workhorse of the driver - it handles messages from the list + * + **/ +static void mxs_spi_handle(struct work_struct *w) +{ + struct mxs_spi *ss = container_of(w, struct mxs_spi, work); + unsigned long flags; + struct spi_message *m; + + BUG_ON(w == NULL); + + spin_lock_irqsave(&ss->lock, flags); + while (!list_empty(&ss->queue)) { + m = list_entry(ss->queue.next, struct spi_message, queue); + list_del_init(&m->queue); + spin_unlock_irqrestore(&ss->lock, flags); + + m->status = mxs_spi_handle_message(ss, m); + if (m->complete) + m->complete(m->context); + + spin_lock_irqsave(&ss->lock, flags); + } + spin_unlock_irqrestore(&ss->lock, flags); + + return; +} + +/** + * mxs_spi_transfer + * + * Called indirectly from spi_async, queues all the messages to + * spi_handle_message + * + * @spi: spi device + * @m: message to be queued +**/ +static int mxs_spi_transfer(struct spi_device *spi, struct spi_message *m) +{ + struct mxs_spi *ss = spi_master_get_devdata(spi->master); + unsigned long flags; + + m->status = -EINPROGRESS; + spin_lock_irqsave(&ss->lock, flags); + list_add_tail(&m->queue, &ss->queue); + queue_work(ss->workqueue, &ss->work); + spin_unlock_irqrestore(&ss->lock, flags); + return 0; +} + +static irqreturn_t mxs_spi_irq_dma(int irq, void *dev_id) +{ + struct mxs_spi *ss = dev_id; + + mxs_dma_ack_irq(ss->dma); + mxs_dma_cooked(ss->dma, NULL); + complete(&ss->done); + return IRQ_HANDLED; +} + +static irqreturn_t mxs_spi_irq_err(int irq, void *dev_id) +{ + struct mxs_spi *ss = dev_id; + u32 c1, st; + + c1 = __raw_readl(ss->regs + HW_SSP_CTRL1); + st = __raw_readl(ss->regs + HW_SSP_STATUS); + printk(KERN_ERR "IRQ - ERROR!, status = 0x%08X, c1 = 0x%08X\n", st, c1); + __raw_writel(c1 & 0xCCCC0000, ss->regs + HW_SSP_CTRL1_CLR); + + return IRQ_HANDLED; +} + +static int __init mxs_spi_probe(struct platform_device *dev) +{ + int err = 0; + struct spi_master *master; + struct mxs_spi *ss; + struct resource *r; + u32 mem; + + /* Get resources(memory, IRQ) associated with the device */ + master = spi_alloc_master(&dev->dev, sizeof(struct mxs_spi)); + + if (master == NULL) { + err = -ENOMEM; + goto out0; + } + + platform_set_drvdata(dev, master); + + r = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (r == NULL) { + err = -ENODEV; + goto out_put_master; + } + + ss = spi_master_get_devdata(master); + ss->master_dev = &dev->dev; + + INIT_WORK(&ss->work, mxs_spi_handle); + INIT_LIST_HEAD(&ss->queue); + spin_lock_init(&ss->lock); + ss->workqueue = create_singlethread_workqueue(dev_name(&dev->dev)); + master->transfer = mxs_spi_transfer; + master->setup = mxs_spi_setup; + master->cleanup = mxs_spi_cleanup; + + if (!request_mem_region(r->start, + resource_size(r), dev_name(&dev->dev))) { + err = -ENXIO; + goto out_put_master; + } + mem = r->start; + + ss->regs = IO_ADDRESS(r->start); + + ss->irq_dma = platform_get_irq(dev, 0); + if (ss->irq_dma < 0) { + err = -ENXIO; + goto out_put_master; + } + ss->irq_err = platform_get_irq(dev, 1); + if (ss->irq_err < 0) { + err = -ENXIO; + goto out_put_master; + } + + r = platform_get_resource(dev, IORESOURCE_DMA, 0); + if (r == NULL) { + err = -ENODEV; + goto out_put_master; + } + + ss->dma = r->start; + err = mxs_dma_request(ss->dma, &dev->dev, (char *)dev_name(&dev->dev)); + if (err) + goto out_put_master; + + ss->pdesc = mxs_dma_alloc_desc(); + if (ss->pdesc == NULL || IS_ERR(ss->pdesc)) { + err = -ENOMEM; + goto out_free_dma; + } + + master->bus_num = dev->id + 1; + master->num_chipselect = 1; + + /* SPI controller initializations */ + err = mxs_spi_init_hw(ss); + if (err) { + dev_dbg(&dev->dev, "cannot initialize hardware\n"); + goto out_free_dma_desc; + } + + clk_set_rate(ss->clk, 120 * 1000 * 1000); + ss->speed_khz = clk_get_rate(ss->clk) / 1000; + ss->divider = 2; + dev_info(&dev->dev, "Max possible speed %d = %ld/%d kHz\n", + ss->speed_khz, clk_get_rate(ss->clk), ss->divider); + + /* Register for SPI Interrupt */ + err = request_irq(ss->irq_dma, mxs_spi_irq_dma, 0, + dev_name(&dev->dev), ss); + if (err) { + dev_dbg(&dev->dev, "request_irq failed, %d\n", err); + goto out_release_hw; + } + err = request_irq(ss->irq_err, mxs_spi_irq_err, IRQF_SHARED, + dev_name(&dev->dev), ss); + if (err) { + dev_dbg(&dev->dev, "request_irq(error) failed, %d\n", err); + goto out_free_irq; + } + + err = spi_register_master(master); + if (err) { + dev_dbg(&dev->dev, "cannot register spi master, %d\n", err); + goto out_free_irq_2; + } + dev_info(&dev->dev, "at 0x%08X mapped to 0x%08X, irq=%d, bus %d, %s\n", + mem, (u32) ss->regs, ss->irq_dma, + master->bus_num, pio ? "PIO" : "DMA"); + return 0; + +out_free_irq_2: + free_irq(ss->irq_err, ss); +out_free_irq: + free_irq(ss->irq_dma, ss); +out_free_dma_desc: + mxs_dma_free_desc(ss->pdesc); +out_free_dma: + mxs_dma_release(ss->dma, &dev->dev); +out_release_hw: + mxs_spi_release_hw(ss); +out_put_master: + spi_master_put(master); +out0: + return err; +} + +static int __devexit mxs_spi_remove(struct platform_device *dev) +{ + struct mxs_spi *ss; + struct spi_master *master; + + master = platform_get_drvdata(dev); + if (master == NULL) + goto out0; + ss = spi_master_get_devdata(master); + if (ss == NULL) + goto out1; + free_irq(ss->irq_err, ss); + free_irq(ss->irq_dma, ss); + if (ss->workqueue) + destroy_workqueue(ss->workqueue); + mxs_dma_free_desc(ss->pdesc); + mxs_dma_release(ss->dma, &dev->dev); + mxs_spi_release_hw(ss); + platform_set_drvdata(dev, 0); +out1: + spi_master_put(master); +out0: + return 0; +} + +#ifdef CONFIG_PM +static int mxs_spi_suspend(struct platform_device *pdev, pm_message_t pmsg) +{ + struct mxs_spi *ss; + struct spi_master *master; + + master = platform_get_drvdata(pdev); + ss = spi_master_get_devdata(master); + + ss->saved_timings = __raw_readl(ss->regs + HW_SSP_TIMING); + clk_disable(ss->clk); + + return 0; +} + +static int mxs_spi_resume(struct platform_device *pdev) +{ + struct mxs_spi *ss; + struct spi_master *master; + + master = platform_get_drvdata(pdev); + ss = spi_master_get_devdata(master); + + clk_enable(ss->clk); + __raw_writel(BM_SSP_CTRL0_SFTRST | BM_SSP_CTRL0_CLKGATE, + ss->regs + HW_SSP_CTRL0_CLR); + __raw_writel(ss->saved_timings, ss->regs + HW_SSP_TIMING); + + return 0; +} + +#else +#define mxs_spi_suspend NULL +#define mxs_spi_resume NULL +#endif + +static struct platform_driver mxs_spi_driver = { + .probe = mxs_spi_probe, + .remove = __devexit_p(mxs_spi_remove), + .driver = { + .name = "mxs-spi", + .owner = THIS_MODULE, + }, + .suspend = mxs_spi_suspend, + .resume = mxs_spi_resume, +}; + +static int __init mxs_spi_init(void) +{ + return platform_driver_register(&mxs_spi_driver); +} + +static void __exit mxs_spi_exit(void) +{ + platform_driver_unregister(&mxs_spi_driver); +} + +module_init(mxs_spi_init); +module_exit(mxs_spi_exit); +module_param(pio, int, S_IRUGO); +module_param(debug, int, S_IRUGO); +MODULE_AUTHOR("dmitry pervushin "); +MODULE_DESCRIPTION("MXS SPI/SSP"); +MODULE_LICENSE("GPL"); diff --git a/drivers/spi/spi_mxs.h b/drivers/spi/spi_mxs.h new file mode 100644 index 000000000000..ba605bf3b56e --- /dev/null +++ b/drivers/spi/spi_mxs.h @@ -0,0 +1,52 @@ +/* + * Freescale MXS SPI master driver + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __SPI_STMP_H +#define __SPI_STMP_H + +#include + +struct mxs_spi { + void __iomem *regs; /* vaddr of the control registers */ + + u32 irq_dma; + u32 irq_err; + u32 dma; + struct mxs_dma_desc *pdesc; + + u32 speed_khz; + u32 saved_timings; + u32 divider; + + struct clk *clk; + struct device *master_dev; + + struct work_struct work; + struct workqueue_struct *workqueue; + spinlock_t lock; + struct list_head queue; + + struct completion done; +}; + +#endif /* __SPI_STMP_H */ diff --git a/drivers/switch/Kconfig b/drivers/switch/Kconfig new file mode 100644 index 000000000000..52385914b9ae --- /dev/null +++ b/drivers/switch/Kconfig @@ -0,0 +1,15 @@ +menuconfig SWITCH + tristate "Switch class support" + help + Say Y here to enable switch class support. This allows + monitoring switches by userspace via sysfs and uevent. + +if SWITCH + +config SWITCH_GPIO + tristate "GPIO Swith support" + depends on GENERIC_GPIO + help + Say Y here to enable GPIO based switch support. + +endif # SWITCH diff --git a/drivers/switch/Makefile b/drivers/switch/Makefile new file mode 100644 index 000000000000..f7606ed4a719 --- /dev/null +++ b/drivers/switch/Makefile @@ -0,0 +1,4 @@ +# Switch Class Driver +obj-$(CONFIG_SWITCH) += switch_class.o +obj-$(CONFIG_SWITCH_GPIO) += switch_gpio.o + diff --git a/drivers/switch/switch_class.c b/drivers/switch/switch_class.c new file mode 100644 index 000000000000..e05fc2591147 --- /dev/null +++ b/drivers/switch/switch_class.c @@ -0,0 +1,174 @@ +/* + * drivers/switch/switch_class.c + * + * Copyright (C) 2008 Google, Inc. + * Author: Mike Lockwood + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * +*/ + +#include +#include +#include +#include +#include +#include +#include + +struct class *switch_class; +static atomic_t device_count; + +static ssize_t state_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct switch_dev *sdev = (struct switch_dev *) + dev_get_drvdata(dev); + + if (sdev->print_state) { + int ret = sdev->print_state(sdev, buf); + if (ret >= 0) + return ret; + } + return sprintf(buf, "%d\n", sdev->state); +} + +static ssize_t name_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct switch_dev *sdev = (struct switch_dev *) + dev_get_drvdata(dev); + + if (sdev->print_name) { + int ret = sdev->print_name(sdev, buf); + if (ret >= 0) + return ret; + } + return sprintf(buf, "%s\n", sdev->name); +} + +static DEVICE_ATTR(state, S_IRUGO | S_IWUSR, state_show, NULL); +static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, name_show, NULL); + +void switch_set_state(struct switch_dev *sdev, int state) +{ + char name_buf[120]; + char state_buf[120]; + char *prop_buf; + char *envp[3]; + int env_offset = 0; + int length; + + if (sdev->state != state) { + sdev->state = state; + + prop_buf = (char *)get_zeroed_page(GFP_KERNEL); + if (prop_buf) { + length = name_show(sdev->dev, NULL, prop_buf); + if (length > 0) { + if (prop_buf[length - 1] == '\n') + prop_buf[length - 1] = 0; + snprintf(name_buf, sizeof(name_buf), + "SWITCH_NAME=%s", prop_buf); + envp[env_offset++] = name_buf; + } + length = state_show(sdev->dev, NULL, prop_buf); + if (length > 0) { + if (prop_buf[length - 1] == '\n') + prop_buf[length - 1] = 0; + snprintf(state_buf, sizeof(state_buf), + "SWITCH_STATE=%s", prop_buf); + envp[env_offset++] = state_buf; + } + envp[env_offset] = NULL; + kobject_uevent_env(&sdev->dev->kobj, KOBJ_CHANGE, envp); + free_page((unsigned long)prop_buf); + } else { + printk(KERN_ERR "out of memory in switch_set_state\n"); + kobject_uevent(&sdev->dev->kobj, KOBJ_CHANGE); + } + } +} +EXPORT_SYMBOL_GPL(switch_set_state); + +static int create_switch_class(void) +{ + if (!switch_class) { + switch_class = class_create(THIS_MODULE, "switch"); + if (IS_ERR(switch_class)) + return PTR_ERR(switch_class); + atomic_set(&device_count, 0); + } + + return 0; +} + +int switch_dev_register(struct switch_dev *sdev) +{ + int ret; + + if (!switch_class) { + ret = create_switch_class(); + if (ret < 0) + return ret; + } + + sdev->index = atomic_inc_return(&device_count); + sdev->dev = device_create(switch_class, NULL, + MKDEV(0, sdev->index), NULL, sdev->name); + if (IS_ERR(sdev->dev)) + return PTR_ERR(sdev->dev); + + ret = device_create_file(sdev->dev, &dev_attr_state); + if (ret < 0) + goto err_create_file_1; + ret = device_create_file(sdev->dev, &dev_attr_name); + if (ret < 0) + goto err_create_file_2; + + dev_set_drvdata(sdev->dev, sdev); + sdev->state = 0; + return 0; + +err_create_file_2: + device_remove_file(sdev->dev, &dev_attr_state); +err_create_file_1: + device_destroy(switch_class, MKDEV(0, sdev->index)); + printk(KERN_ERR "switch: Failed to register driver %s\n", sdev->name); + + return ret; +} +EXPORT_SYMBOL_GPL(switch_dev_register); + +void switch_dev_unregister(struct switch_dev *sdev) +{ + device_remove_file(sdev->dev, &dev_attr_name); + device_remove_file(sdev->dev, &dev_attr_state); + device_destroy(switch_class, MKDEV(0, sdev->index)); + dev_set_drvdata(sdev->dev, NULL); +} +EXPORT_SYMBOL_GPL(switch_dev_unregister); + +static int __init switch_class_init(void) +{ + return create_switch_class(); +} + +static void __exit switch_class_exit(void) +{ + class_destroy(switch_class); +} + +module_init(switch_class_init); +module_exit(switch_class_exit); + +MODULE_AUTHOR("Mike Lockwood "); +MODULE_DESCRIPTION("Switch class driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/switch/switch_gpio.c b/drivers/switch/switch_gpio.c new file mode 100644 index 000000000000..b5f98ca0b2e1 --- /dev/null +++ b/drivers/switch/switch_gpio.c @@ -0,0 +1,171 @@ +/* + * drivers/switch/switch_gpio.c + * + * Copyright (C) 2008 Google, Inc. + * Author: Mike Lockwood + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct gpio_switch_data { + struct switch_dev sdev; + unsigned gpio; + const char *name_on; + const char *name_off; + const char *state_on; + const char *state_off; + int irq; + struct work_struct work; +}; + +static void gpio_switch_work(struct work_struct *work) +{ + int state; + struct gpio_switch_data *data = + container_of(work, struct gpio_switch_data, work); + + state = gpio_get_value(data->gpio); + switch_set_state(&data->sdev, state); +} + +static irqreturn_t gpio_irq_handler(int irq, void *dev_id) +{ + struct gpio_switch_data *switch_data = + (struct gpio_switch_data *)dev_id; + + schedule_work(&switch_data->work); + return IRQ_HANDLED; +} + +static ssize_t switch_gpio_print_state(struct switch_dev *sdev, char *buf) +{ + struct gpio_switch_data *switch_data = + container_of(sdev, struct gpio_switch_data, sdev); + const char *state; + if (switch_get_state(sdev)) + state = switch_data->state_on; + else + state = switch_data->state_off; + + if (state) + return sprintf(buf, "%s\n", state); + return -1; +} + +static int gpio_switch_probe(struct platform_device *pdev) +{ + struct gpio_switch_platform_data *pdata = pdev->dev.platform_data; + struct gpio_switch_data *switch_data; + int ret = 0; + + if (!pdata) + return -EBUSY; + + switch_data = kzalloc(sizeof(struct gpio_switch_data), GFP_KERNEL); + if (!switch_data) + return -ENOMEM; + + switch_data->sdev.name = pdata->name; + switch_data->gpio = pdata->gpio; + switch_data->name_on = pdata->name_on; + switch_data->name_off = pdata->name_off; + switch_data->state_on = pdata->state_on; + switch_data->state_off = pdata->state_off; + switch_data->sdev.print_state = switch_gpio_print_state; + + ret = switch_dev_register(&switch_data->sdev); + if (ret < 0) + goto err_switch_dev_register; + + ret = gpio_request(switch_data->gpio, pdev->name); + if (ret < 0) + goto err_request_gpio; + + ret = gpio_direction_input(switch_data->gpio); + if (ret < 0) + goto err_set_gpio_input; + + INIT_WORK(&switch_data->work, gpio_switch_work); + + switch_data->irq = gpio_to_irq(switch_data->gpio); + if (switch_data->irq < 0) { + ret = switch_data->irq; + goto err_detect_irq_num_failed; + } + + ret = request_irq(switch_data->irq, gpio_irq_handler, + IRQF_TRIGGER_LOW, pdev->name, switch_data); + if (ret < 0) + goto err_request_irq; + + /* Perform initial detection */ + gpio_switch_work(&switch_data->work); + + return 0; + +err_request_irq: +err_detect_irq_num_failed: +err_set_gpio_input: + gpio_free(switch_data->gpio); +err_request_gpio: + switch_dev_unregister(&switch_data->sdev); +err_switch_dev_register: + kfree(switch_data); + + return ret; +} + +static int __devexit gpio_switch_remove(struct platform_device *pdev) +{ + struct gpio_switch_data *switch_data = platform_get_drvdata(pdev); + + cancel_work_sync(&switch_data->work); + gpio_free(switch_data->gpio); + switch_dev_unregister(&switch_data->sdev); + kfree(switch_data); + + return 0; +} + +static struct platform_driver gpio_switch_driver = { + .probe = gpio_switch_probe, + .remove = __devexit_p(gpio_switch_remove), + .driver = { + .name = "switch-gpio", + .owner = THIS_MODULE, + }, +}; + +static int __init gpio_switch_init(void) +{ + return platform_driver_register(&gpio_switch_driver); +} + +static void __exit gpio_switch_exit(void) +{ + platform_driver_unregister(&gpio_switch_driver); +} + +module_init(gpio_switch_init); +module_exit(gpio_switch_exit); + +MODULE_AUTHOR("Mike Lockwood "); +MODULE_DESCRIPTION("GPIO Switch driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/usb/gadget/android.c b/drivers/usb/gadget/android.c new file mode 100644 index 000000000000..0c36e3f36907 --- /dev/null +++ b/drivers/usb/gadget/android.c @@ -0,0 +1,376 @@ +/* + * Gadget Driver for Android + * + * Copyright (C) 2008 Google, Inc. + * Author: Mike Lockwood + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* #define DEBUG */ +/* #define VERBOSE_DEBUG */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "f_mass_storage.h" +#include "f_adb.h" + +#include "gadget_chips.h" + +/* + * Kbuild is not very cooperative with respect to linking separately + * compiled library objects into one module. So for now we won't use + * separate compilation ... ensuring init/exit sections work to shrink + * the runtime footprint, and giving us at least some parts of what + * a "gcc --combine ... part1.c part2.c part3.c ... " build would. + */ +#include "usbstring.c" +#include "config.c" +#include "epautoconf.c" +#include "composite.c" + +MODULE_AUTHOR("Mike Lockwood"); +MODULE_DESCRIPTION("Android Composite USB Driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); + +static const char longname[] = "Gadget Android"; + +/* Default vendor and product IDs, overridden by platform data */ +#define VENDOR_ID 0x18D1 +#define PRODUCT_ID 0x0001 +#define ADB_PRODUCT_ID 0x0002 + +struct android_dev { + struct usb_composite_dev *cdev; + + int product_id; + int adb_product_id; + int version; + + int adb_enabled; + int nluns; +}; + +static atomic_t adb_enable_excl; +static struct android_dev *_android_dev; + +/* string IDs are assigned dynamically */ + +#define STRING_MANUFACTURER_IDX 0 +#define STRING_PRODUCT_IDX 1 +#define STRING_SERIAL_IDX 2 + +/* String Table */ +static struct usb_string strings_dev[] = { + /* These dummy values should be overridden by platform data */ + [STRING_MANUFACTURER_IDX].s = "Android", + [STRING_PRODUCT_IDX].s = "Android", + [STRING_SERIAL_IDX].s = "0123456789ABCDEF", + { } /* end of list */ +}; + +static struct usb_gadget_strings stringtab_dev = { + .language = 0x0409, /* en-us */ + .strings = strings_dev, +}; + +static struct usb_gadget_strings *dev_strings[] = { + &stringtab_dev, + NULL, +}; + +static struct usb_device_descriptor device_desc = { + .bLength = sizeof(device_desc), + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = __constant_cpu_to_le16(0x0200), + .bDeviceClass = USB_CLASS_PER_INTERFACE, + .idVendor = __constant_cpu_to_le16(VENDOR_ID), + .idProduct = __constant_cpu_to_le16(PRODUCT_ID), + .bcdDevice = __constant_cpu_to_le16(0xffff), + .bNumConfigurations = 1, +}; + +void android_usb_set_connected(int connected) +{ + if (_android_dev && _android_dev->cdev && _android_dev->cdev->gadget) { + if (connected) + usb_gadget_connect(_android_dev->cdev->gadget); + else + usb_gadget_disconnect(_android_dev->cdev->gadget); + } +} + +static int __init android_bind_config(struct usb_configuration *c) +{ + struct android_dev *dev = _android_dev; + int ret; + printk(KERN_DEBUG "android_bind_config\n"); + + ret = mass_storage_function_add(dev->cdev, c, dev->nluns); + if (ret) + return ret; + return adb_function_add(dev->cdev, c); +} + +static int android_setup_config(struct usb_configuration *c, + const struct usb_ctrlrequest *ctrl); + +static struct usb_configuration android_config_driver = { + .label = "android", + .bind = android_bind_config, + .setup = android_setup_config, + .bConfigurationValue = 1, + .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER, + .bMaxPower = 0xFA, /* 500ma */ +}; + +static int android_setup_config(struct usb_configuration *c, + const struct usb_ctrlrequest *ctrl) +{ + int i; + int ret = -EOPNOTSUPP; + + for (i = 0; i < android_config_driver.next_interface_id; i++) { + if (android_config_driver.interface[i]->setup) { + ret = android_config_driver.interface[i]->setup( + android_config_driver.interface[i], ctrl); + if (ret >= 0) + return ret; + } + } + return ret; +} + +static int __init android_bind(struct usb_composite_dev *cdev) +{ + struct android_dev *dev = _android_dev; + struct usb_gadget *gadget = cdev->gadget; + int gcnum; + int id; + int ret; + + printk(KERN_INFO "android_bind\n"); + + /* Allocate string descriptor numbers ... note that string + * contents can be overridden by the composite_dev glue. + */ + id = usb_string_id(cdev); + if (id < 0) + return id; + strings_dev[STRING_MANUFACTURER_IDX].id = id; + device_desc.iManufacturer = id; + + id = usb_string_id(cdev); + if (id < 0) + return id; + strings_dev[STRING_PRODUCT_IDX].id = id; + device_desc.iProduct = id; + + id = usb_string_id(cdev); + if (id < 0) + return id; + strings_dev[STRING_SERIAL_IDX].id = id; + device_desc.iSerialNumber = id; + + if (gadget->ops->wakeup) + android_config_driver.bmAttributes |= USB_CONFIG_ATT_WAKEUP; + + /* register our configuration */ + ret = usb_add_config(cdev, &android_config_driver); + if (ret) { + printk(KERN_ERR "usb_add_config failed\n"); + return ret; + } + + gcnum = usb_gadget_controller_number(gadget); + if (gcnum >= 0) + device_desc.bcdDevice = cpu_to_le16(0x0200 + gcnum); + else { + /* gadget zero is so simple (for now, no altsettings) that + * it SHOULD NOT have problems with bulk-capable hardware. + * so just warn about unrcognized controllers -- don't panic. + * + * things like configuration and altsetting numbering + * can need hardware-specific attention though. + */ + pr_warning("%s: controller '%s' not recognized\n", + longname, gadget->name); + device_desc.bcdDevice = __constant_cpu_to_le16(0x9999); + } + + usb_gadget_set_selfpowered(gadget); + dev->cdev = cdev; + + return 0; +} + +static struct usb_composite_driver android_usb_driver = { + .name = "android_usb", + .dev = &device_desc, + .strings = dev_strings, + .bind = android_bind, +}; + +static void enable_adb(struct android_dev *dev, int enable) +{ + if (enable != dev->adb_enabled) { + dev->adb_enabled = enable; + adb_function_enable(enable); + + /* set product ID to the appropriate value */ + if (enable) + device_desc.idProduct = + __constant_cpu_to_le16(dev->adb_product_id); + else + device_desc.idProduct = + __constant_cpu_to_le16(dev->product_id); + if (dev->cdev) + dev->cdev->desc.idProduct = device_desc.idProduct; + + /* force reenumeration */ + if (dev->cdev && dev->cdev->gadget && + dev->cdev->gadget->speed != USB_SPEED_UNKNOWN) { + usb_gadget_disconnect(dev->cdev->gadget); + msleep(10); + usb_gadget_connect(dev->cdev->gadget); + usb_gadget_vbus_connect(dev->cdev->gadget); + } + } +} + +static int adb_enable_open(struct inode *ip, struct file *fp) +{ + if (atomic_inc_return(&adb_enable_excl) != 1) { + atomic_dec(&adb_enable_excl); + return -EBUSY; + } + + printk(KERN_INFO "enabling adb\n"); + enable_adb(_android_dev, 1); + + return 0; +} + +static int adb_enable_release(struct inode *ip, struct file *fp) +{ + printk(KERN_INFO "disabling adb\n"); + enable_adb(_android_dev, 0); + atomic_dec(&adb_enable_excl); + return 0; +} + +static const struct file_operations adb_enable_fops = { + .owner = THIS_MODULE, + .open = adb_enable_open, + .release = adb_enable_release, +}; + +static struct miscdevice adb_enable_device = { + .minor = MISC_DYNAMIC_MINOR, + .name = "android_adb_enable", + .fops = &adb_enable_fops, +}; + +static int __init android_probe(struct platform_device *pdev) +{ + struct android_usb_platform_data *pdata = pdev->dev.platform_data; + struct android_dev *dev = _android_dev; + + printk(KERN_INFO "android_probe pdata: %p\n", pdata); + + if (pdata) { + if (pdata->vendor_id) + device_desc.idVendor = + __constant_cpu_to_le16(pdata->vendor_id); + if (pdata->product_id) { + dev->product_id = pdata->product_id; + device_desc.idProduct = + __constant_cpu_to_le16(pdata->product_id); + } + if (pdata->adb_product_id) + dev->adb_product_id = pdata->adb_product_id; + if (pdata->version) + dev->version = pdata->version; + + if (pdata->product_name) + strings_dev[STRING_PRODUCT_IDX].s = pdata->product_name; + if (pdata->manufacturer_name) + strings_dev[STRING_MANUFACTURER_IDX].s = + pdata->manufacturer_name; + if (pdata->serial_number) + strings_dev[STRING_SERIAL_IDX].s = pdata->serial_number; + dev->nluns = pdata->nluns; + } + + return 0; +} + +static struct platform_driver android_platform_driver = { + .driver = { .name = "android_usb", }, + .probe = android_probe, +}; + +static int __init init(void) +{ + struct android_dev *dev; + int ret; + + printk(KERN_INFO "android init\n"); + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + /* set default values, which should be overridden by platform data */ + dev->product_id = PRODUCT_ID; + dev->adb_product_id = ADB_PRODUCT_ID; + _android_dev = dev; + + ret = platform_driver_register(&android_platform_driver); + if (ret) + return ret; + ret = misc_register(&adb_enable_device); + if (ret) { + platform_driver_unregister(&android_platform_driver); + return ret; + } + ret = usb_composite_register(&android_usb_driver); + if (ret) { + misc_deregister(&adb_enable_device); + platform_driver_unregister(&android_platform_driver); + } + return ret; +} +late_initcall(init); + +static void __exit cleanup(void) +{ + usb_composite_unregister(&android_usb_driver); + misc_deregister(&adb_enable_device); + platform_driver_unregister(&android_platform_driver); + kfree(_android_dev); + _android_dev = NULL; +} +module_exit(cleanup); diff --git a/drivers/usb/gadget/f_acm.h b/drivers/usb/gadget/f_acm.h new file mode 100644 index 000000000000..8e27b3440635 --- /dev/null +++ b/drivers/usb/gadget/f_acm.h @@ -0,0 +1,24 @@ +/* + * Gadget Driver for Android ACM + * + * Copyright (C) 2009 Motorola, Inc. + * Author: + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __F_ACM_H +#define __F_ACM_H + +int acm_function_add(struct usb_composite_dev *cdev, + struct usb_configuration *c); + +#endif /* __F_ACM_H */ diff --git a/drivers/usb/gadget/f_adb.c b/drivers/usb/gadget/f_adb.c new file mode 100644 index 000000000000..8cead67c3060 --- /dev/null +++ b/drivers/usb/gadget/f_adb.c @@ -0,0 +1,685 @@ +/* + * Gadget Driver for Android ADB + * + * Copyright (C) 2008 Google, Inc. + * Author: Mike Lockwood + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* #define DEBUG */ +/* #define VERBOSE_DEBUG */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "f_adb.h" + +#define ADB_BULK_BUFFER_SIZE 4096 + +/* number of rx and tx requests to allocate */ +#define RX_REQ_MAX 4 +#define TX_REQ_MAX 4 + +static const char shortname[] = "android_adb"; + +struct adb_dev { + struct usb_function function; + struct usb_composite_dev *cdev; + spinlock_t lock; + + struct usb_ep *ep_in; + struct usb_ep *ep_out; + + int online; + int error; + + atomic_t read_excl; + atomic_t write_excl; + atomic_t open_excl; + + struct list_head tx_idle; + struct list_head rx_idle; + struct list_head rx_done; + + wait_queue_head_t read_wq; + wait_queue_head_t write_wq; + + /* the request we're currently reading from */ + struct usb_request *read_req; + unsigned char *read_buf; + unsigned read_count; + + struct wake_lock wake_lock; +}; + +static struct usb_interface_descriptor adb_interface_desc = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bNumEndpoints = 2, + .bInterfaceClass = 0xFF, + .bInterfaceSubClass = 0x42, + .bInterfaceProtocol = 1, +}; + +static struct usb_endpoint_descriptor adb_highspeed_in_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = __constant_cpu_to_le16(512), +}; + +static struct usb_endpoint_descriptor adb_highspeed_out_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = __constant_cpu_to_le16(512), +}; + +static struct usb_endpoint_descriptor adb_fullspeed_in_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, +}; + +static struct usb_endpoint_descriptor adb_fullspeed_out_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, +}; + +static struct usb_descriptor_header *fs_adb_descs[] = { + (struct usb_descriptor_header *) &adb_interface_desc, + (struct usb_descriptor_header *) &adb_fullspeed_in_desc, + (struct usb_descriptor_header *) &adb_fullspeed_out_desc, + NULL, +}; + +static struct usb_descriptor_header *hs_adb_descs[] = { + (struct usb_descriptor_header *) &adb_interface_desc, + (struct usb_descriptor_header *) &adb_highspeed_in_desc, + (struct usb_descriptor_header *) &adb_highspeed_out_desc, + NULL, +}; + +/* used when adb function is disabled */ +static struct usb_descriptor_header *null_adb_descs[] = { + NULL, +}; + + +/* temporary variable used between adb_open() and adb_gadget_bind() */ +static struct adb_dev *_adb_dev; + +static inline struct adb_dev *func_to_dev(struct usb_function *f) +{ + return container_of(f, struct adb_dev, function); +} + + +static struct usb_request *adb_request_new(struct usb_ep *ep, int buffer_size) +{ + struct usb_request *req = usb_ep_alloc_request(ep, GFP_KERNEL); + if (!req) + return NULL; + + /* now allocate buffers for the requests */ + req->buf = kmalloc(buffer_size, GFP_KERNEL); + if (!req->buf) { + usb_ep_free_request(ep, req); + return NULL; + } + + return req; +} + +static void adb_request_free(struct usb_request *req, struct usb_ep *ep) +{ + if (req) { + kfree(req->buf); + usb_ep_free_request(ep, req); + } +} + +static inline int _lock(atomic_t *excl) +{ + if (atomic_inc_return(excl) == 1) { + return 0; + } else { + atomic_dec(excl); + return -1; + } +} + +static inline void _unlock(atomic_t *excl) +{ + atomic_dec(excl); +} + +/* add a request to the tail of a list */ +void req_put(struct adb_dev *dev, struct list_head *head, + struct usb_request *req) +{ + unsigned long flags; + + spin_lock_irqsave(&dev->lock, flags); + list_add_tail(&req->list, head); + spin_unlock_irqrestore(&dev->lock, flags); +} + +/* remove a request from the head of a list */ +struct usb_request *req_get(struct adb_dev *dev, struct list_head *head) +{ + unsigned long flags; + struct usb_request *req; + + spin_lock_irqsave(&dev->lock, flags); + if (list_empty(head)) { + req = 0; + } else { + req = list_first_entry(head, struct usb_request, list); + list_del(&req->list); + } + spin_unlock_irqrestore(&dev->lock, flags); + return req; +} + +static void adb_complete_in(struct usb_ep *ep, struct usb_request *req) +{ + struct adb_dev *dev = _adb_dev; + + if (req->status != 0) + dev->error = 1; + + req_put(dev, &dev->tx_idle, req); + + wake_up(&dev->write_wq); +} + +static void adb_complete_out(struct usb_ep *ep, struct usb_request *req) +{ + struct adb_dev *dev = _adb_dev; + + if (req->status != 0) { + dev->error = 1; + req_put(dev, &dev->rx_idle, req); + } else { + req_put(dev, &dev->rx_done, req); + } + + wake_up(&dev->read_wq); +} + +static int __init create_bulk_endpoints(struct adb_dev *dev, + struct usb_endpoint_descriptor *in_desc, + struct usb_endpoint_descriptor *out_desc) +{ + struct usb_composite_dev *cdev = dev->cdev; + struct usb_request *req; + struct usb_ep *ep; + int i; + + DBG(cdev, "create_bulk_endpoints dev: %p\n", dev); + + ep = usb_ep_autoconfig(cdev->gadget, in_desc); + if (!ep) { + DBG(cdev, "usb_ep_autoconfig for ep_in failed\n"); + return -ENODEV; + } + DBG(cdev, "usb_ep_autoconfig for ep_in got %s\n", ep->name); + dev->ep_in = ep; + + ep = usb_ep_autoconfig(cdev->gadget, out_desc); + if (!ep) { + DBG(cdev, "usb_ep_autoconfig for ep_out failed\n"); + return -ENODEV; + } + DBG(cdev, "usb_ep_autoconfig for adb ep_out got %s\n", ep->name); + dev->ep_out = ep; + + /* now allocate requests for our endpoints */ + for (i = 0; i < RX_REQ_MAX; i++) { + req = adb_request_new(dev->ep_out, ADB_BULK_BUFFER_SIZE); + if (!req) + goto fail; + req->complete = adb_complete_out; + req_put(dev, &dev->rx_idle, req); + } + + for (i = 0; i < TX_REQ_MAX; i++) { + req = adb_request_new(dev->ep_in, ADB_BULK_BUFFER_SIZE); + if (!req) + goto fail; + req->complete = adb_complete_in; + req_put(dev, &dev->tx_idle, req); + } + + return 0; + +fail: + printk(KERN_ERR "adb_bind() could not allocate requests\n"); + return -1; +} + +static ssize_t adb_read(struct file *fp, char __user *buf, + size_t count, loff_t *pos) +{ + struct adb_dev *dev = fp->private_data; + struct usb_composite_dev *cdev = dev->cdev; + struct usb_request *req; + int r = count, xfer; + int ret; + + DBG(cdev, "adb_read(%d)\n", count); + + if (_lock(&dev->read_excl)) + return -EBUSY; + + /* we will block until we're online */ + while (!(dev->online || dev->error)) { + DBG(cdev, "adb_read: waiting for online state\n"); + ret = wait_event_interruptible(dev->read_wq, + (dev->online || dev->error)); + if (ret < 0) { + _unlock(&dev->read_excl); + return ret; + } + } + + while (count > 0) { + if (dev->error) { + DBG(cdev, "adb_read dev->error\n"); + r = -EIO; + break; + } + + /* if we have idle read requests, get them queued */ + while ((req = req_get(dev, &dev->rx_idle))) { +requeue_req: + req->length = ADB_BULK_BUFFER_SIZE; + ret = usb_ep_queue(dev->ep_out, req, GFP_ATOMIC); + + if (ret < 0) { + r = -EIO; + dev->error = 1; + req_put(dev, &dev->rx_idle, req); + goto fail; + } else { + DBG(cdev, "rx %p queue\n", req); + } + } + + /* if we have data pending, give it to userspace */ + if (dev->read_count > 0) { + if (dev->read_count < count) + xfer = dev->read_count; + else + xfer = count; + + if (copy_to_user(buf, dev->read_buf, xfer)) { + r = -EFAULT; + break; + } + dev->read_buf += xfer; + dev->read_count -= xfer; + buf += xfer; + count -= xfer; + + /* if we've emptied the buffer, release the request */ + if (dev->read_count == 0) { + req_put(dev, &dev->rx_idle, dev->read_req); + dev->read_req = 0; + } + continue; + } + + /* wait for a request to complete */ + req = 0; + ret = wait_event_interruptible(dev->read_wq, + ((req = req_get(dev, &dev->rx_done)) || dev->error)); + if (req != 0) { + /* if we got a 0-len one we need to put it back into + ** service. if we made it the current read req we'd + ** be stuck forever + */ + if (req->actual == 0) + goto requeue_req; + + dev->read_req = req; + dev->read_count = req->actual; + dev->read_buf = req->buf; + DBG(cdev, "rx %p %d\n", req, req->actual); + } + + if (ret < 0) { + r = ret; + break; + } + } + +fail: + _unlock(&dev->read_excl); + DBG(cdev, "adb_read returning %d\n", r); + return r; +} + +static ssize_t adb_write(struct file *fp, const char __user *buf, + size_t count, loff_t *pos) +{ + struct adb_dev *dev = fp->private_data; + struct usb_composite_dev *cdev = dev->cdev; + struct usb_request *req = 0; + int r = count, xfer; + int ret; + + DBG(cdev, "adb_write(%d)\n", count); + + if (_lock(&dev->write_excl)) + return -EBUSY; + + while (count > 0) { + if (dev->error) { + DBG(cdev, "adb_write dev->error\n"); + r = -EIO; + break; + } + + /* get an idle tx request to use */ + req = 0; + ret = wait_event_interruptible(dev->write_wq, + ((req = req_get(dev, &dev->tx_idle)) || dev->error)); + + if (ret < 0) { + r = ret; + break; + } + + if (req != 0) { + if (count > ADB_BULK_BUFFER_SIZE) + xfer = ADB_BULK_BUFFER_SIZE; + else + xfer = count; + if (copy_from_user(req->buf, buf, xfer)) { + r = -EFAULT; + break; + } + + req->length = xfer; + ret = usb_ep_queue(dev->ep_in, req, GFP_ATOMIC); + if (ret < 0) { + DBG(cdev, "adb_write: xfer error %d\n", ret); + dev->error = 1; + r = -EIO; + break; + } + + buf += xfer; + count -= xfer; + + /* zero this so we don't try to free it on error exit */ + req = 0; + } + } + + if (req) + req_put(dev, &dev->tx_idle, req); + + _unlock(&dev->write_excl); + DBG(cdev, "adb_write returning %d\n", r); + return r; +} + +static int adb_open(struct inode *ip, struct file *fp) +{ + printk(KERN_INFO "adb_open\n"); + if (_lock(&_adb_dev->open_excl)) + return -EBUSY; + + fp->private_data = _adb_dev; + + /* clear the error latch */ + _adb_dev->error = 0; + + return 0; +} + +static int adb_release(struct inode *ip, struct file *fp) +{ + printk(KERN_INFO "adb_release\n"); + _unlock(&_adb_dev->open_excl); + return 0; +} + +/* file operations for ADB device /dev/android_adb */ +static struct file_operations adb_fops = { + .owner = THIS_MODULE, + .read = adb_read, + .write = adb_write, + .open = adb_open, + .release = adb_release, +}; + +static struct miscdevice adb_device = { + .minor = MISC_DYNAMIC_MINOR, + .name = shortname, + .fops = &adb_fops, +}; + +static int __init +adb_function_bind(struct usb_configuration *c, struct usb_function *f) +{ + struct usb_composite_dev *cdev = c->cdev; + struct adb_dev *dev = func_to_dev(f); + int id; + int ret; + + dev->cdev = cdev; + DBG(cdev, "adb_function_bind dev: %p\n", dev); + + /* allocate interface ID(s) */ + id = usb_interface_id(c, f); + if (id < 0) + return id; + adb_interface_desc.bInterfaceNumber = id; + + /* allocate endpoints */ + ret = create_bulk_endpoints(dev, &adb_fullspeed_in_desc, + &adb_fullspeed_out_desc); + if (ret) + return ret; + + /* support high speed hardware */ + if (gadget_is_dualspeed(c->cdev->gadget)) { + adb_highspeed_in_desc.bEndpointAddress = + adb_fullspeed_in_desc.bEndpointAddress; + adb_highspeed_out_desc.bEndpointAddress = + adb_fullspeed_out_desc.bEndpointAddress; + } + + DBG(cdev, "%s speed %s: IN/%s, OUT/%s\n", + gadget_is_dualspeed(c->cdev->gadget) ? "dual" : "full", + f->name, dev->ep_in->name, dev->ep_out->name); + return 0; +} + +static void +adb_function_unbind(struct usb_configuration *c, struct usb_function *f) +{ + struct adb_dev *dev = func_to_dev(f); + struct usb_request *req; + + spin_lock_irq(&dev->lock); + + while ((req = req_get(dev, &dev->rx_idle))) + adb_request_free(req, dev->ep_out); + while ((req = req_get(dev, &dev->tx_idle))) + adb_request_free(req, dev->ep_in); + + dev->online = 0; + dev->error = 1; + spin_unlock_irq(&dev->lock); + + misc_deregister(&adb_device); + kfree(_adb_dev); + _adb_dev = NULL; +} + +static int adb_function_set_alt(struct usb_function *f, + unsigned intf, unsigned alt) +{ + struct adb_dev *dev = func_to_dev(f); + struct usb_composite_dev *cdev = f->config->cdev; + int ret; + + DBG(cdev, "adb_function_set_alt intf: %d alt: %d\n", intf, alt); + ret = usb_ep_enable(dev->ep_in, + ep_choose(cdev->gadget, + &adb_highspeed_in_desc, + &adb_fullspeed_in_desc)); + if (ret) + return ret; + ret = usb_ep_enable(dev->ep_out, + ep_choose(cdev->gadget, + &adb_highspeed_out_desc, + &adb_fullspeed_out_desc)); + if (ret) { + usb_ep_disable(dev->ep_in); + return ret; + } + dev->online = 1; + + wake_lock(&dev->wake_lock); + /* readers may be blocked waiting for us to go online */ + wake_up(&dev->read_wq); + return 0; +} + +static void adb_function_disable(struct usb_function *f) +{ + struct adb_dev *dev = func_to_dev(f); + struct usb_composite_dev *cdev = dev->cdev; + + DBG(cdev, "adb_function_disable\n"); + dev->online = 0; + dev->error = 1; + usb_ep_disable(dev->ep_in); + usb_ep_disable(dev->ep_out); + + /* readers may be blocked waiting for us to go online */ + wake_up(&dev->read_wq); + + VDBG(cdev, "%s disabled\n", dev->function.name); +} + +static void adb_function_suspend(struct usb_function *f) +{ + struct adb_dev *dev = func_to_dev(f); + struct usb_composite_dev *cdev = dev->cdev; + wake_unlock(&dev->wake_lock); + DBG(cdev, "adb function suspend\n"); +} + +int __init adb_function_add(struct usb_composite_dev *cdev, + struct usb_configuration *c) +{ + struct adb_dev *dev; + int ret; + + printk(KERN_INFO "adb_function_add\n"); + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + spin_lock_init(&dev->lock); + + init_waitqueue_head(&dev->read_wq); + init_waitqueue_head(&dev->write_wq); + + atomic_set(&dev->open_excl, 0); + atomic_set(&dev->read_excl, 0); + atomic_set(&dev->write_excl, 0); + + INIT_LIST_HEAD(&dev->rx_idle); + INIT_LIST_HEAD(&dev->rx_done); + INIT_LIST_HEAD(&dev->tx_idle); + + wake_lock_init(&dev->wake_lock, WAKE_LOCK_SUSPEND, + "usb_adb"); + + dev->cdev = cdev; + dev->function.name = "adb"; + dev->function.descriptors = null_adb_descs; + dev->function.hs_descriptors = null_adb_descs; + dev->function.bind = adb_function_bind; + dev->function.unbind = adb_function_unbind; + dev->function.set_alt = adb_function_set_alt; + dev->function.disable = adb_function_disable; + dev->function.suspend = adb_function_suspend; + + /* _adb_dev must be set before calling usb_gadget_register_driver */ + _adb_dev = dev; + + ret = misc_register(&adb_device); + if (ret) + goto err1; + ret = usb_add_function(c, &dev->function); + if (ret) + goto err2; + + return 0; + +err2: + misc_deregister(&adb_device); +err1: + wake_lock_destroy(&dev->wake_lock); + kfree(dev); + printk(KERN_ERR "adb gadget driver failed to initialize\n"); + return ret; +} + +void adb_function_enable(int enable) +{ + struct adb_dev *dev = _adb_dev; + + if (dev) { + DBG(dev->cdev, "adb_function_enable(%s)\n", + enable ? "true" : "false"); + + if (enable) { + dev->function.descriptors = fs_adb_descs; + dev->function.hs_descriptors = hs_adb_descs; + } else { + dev->function.descriptors = null_adb_descs; + dev->function.hs_descriptors = null_adb_descs; + } + } +} + diff --git a/drivers/usb/gadget/f_adb.h b/drivers/usb/gadget/f_adb.h new file mode 100644 index 000000000000..4854ff629797 --- /dev/null +++ b/drivers/usb/gadget/f_adb.h @@ -0,0 +1,25 @@ +/* + * Gadget Driver for Android ADB + * + * Copyright (C) 2008 Google, Inc. + * Author: Mike Lockwood + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __F_ADB_H +#define __F_ADB_H + +int adb_function_add(struct usb_composite_dev *cdev, + struct usb_configuration *c); +void adb_function_enable(int enable); + +#endif /* __F_ADB_H */ diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c new file mode 100755 index 000000000000..617cbee8e8bb --- /dev/null +++ b/drivers/usb/gadget/f_mass_storage.c @@ -0,0 +1,3025 @@ +/* + * drivers/usb/gadget/f_mass_storage.c + * + * Function Driver for USB Mass Storage + * + * Copyright (C) 2008 Google, Inc. + * Author: Mike Lockwood + * + * Based heavily on the file_storage gadget driver in + * drivers/usb/gadget/file_storage.c and licensed under the same terms: + * + * Copyright (C) 2003-2007 Alan Stern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* #define DEBUG */ +/* #define VERBOSE_DEBUG */ +/* #define DUMP_MSGS */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "f_mass_storage.h" +#include "gadget_chips.h" + + +#define BULK_BUFFER_SIZE 16384 + +/* flush after every 4 meg of writes to avoid excessive block level caching */ +#define MAX_UNFLUSHED_BYTES (4 * 1024 * 1024) + +/*-------------------------------------------------------------------------*/ + +#define DRIVER_NAME "usb_mass_storage" +#define MAX_LUNS 8 + +static const char shortname[] = DRIVER_NAME; + +#ifdef DEBUG +#define LDBG(lun, fmt, args...) \ + dev_dbg(&(lun)->dev , fmt , ## args) +#define MDBG(fmt,args...) \ + printk(KERN_DEBUG DRIVER_NAME ": " fmt , ## args) +#else +#define LDBG(lun, fmt, args...) \ + do { } while (0) +#define MDBG(fmt,args...) \ + do { } while (0) +#undef VERBOSE_DEBUG +#undef DUMP_MSGS +#endif /* DEBUG */ + +#ifdef VERBOSE_DEBUG +#define VLDBG LDBG +#else +#define VLDBG(lun, fmt, args...) \ + do { } while (0) +#endif /* VERBOSE_DEBUG */ + +#define LERROR(lun, fmt, args...) \ + dev_err(&(lun)->dev , fmt , ## args) +#define LWARN(lun, fmt, args...) \ + dev_warn(&(lun)->dev , fmt , ## args) +#define LINFO(lun, fmt, args...) \ + dev_info(&(lun)->dev , fmt , ## args) + +#define MINFO(fmt,args...) \ + printk(KERN_INFO DRIVER_NAME ": " fmt , ## args) + +#undef DBG +#undef VDBG +#undef ERROR +#undef WARNING +#undef INFO +#define DBG(d, fmt, args...) \ + dev_dbg(&(d)->cdev->gadget->dev , fmt , ## args) +#define VDBG(d, fmt, args...) \ + dev_vdbg(&(d)->cdev->gadget->dev , fmt , ## args) +#define ERROR(d, fmt, args...) \ + dev_err(&(d)->cdev->gadget->dev , fmt , ## args) +#define WARNING(d, fmt, args...) \ + dev_warn(&(d)->cdev->gadget->dev , fmt , ## args) +#define INFO(d, fmt, args...) \ + dev_info(&(d)->cdev->gadget->dev , fmt , ## args) + + +/*-------------------------------------------------------------------------*/ + +/* Bulk-only data structures */ + +/* Command Block Wrapper */ +struct bulk_cb_wrap { + __le32 Signature; /* Contains 'USBC' */ + u32 Tag; /* Unique per command id */ + __le32 DataTransferLength; /* Size of the data */ + u8 Flags; /* Direction in bit 7 */ + u8 Lun; /* LUN (normally 0) */ + u8 Length; /* Of the CDB, <= MAX_COMMAND_SIZE */ + u8 CDB[16]; /* Command Data Block */ +}; + +#define USB_BULK_CB_WRAP_LEN 31 +#define USB_BULK_CB_SIG 0x43425355 /* Spells out USBC */ +#define USB_BULK_IN_FLAG 0x80 + +/* Command Status Wrapper */ +struct bulk_cs_wrap { + __le32 Signature; /* Should = 'USBS' */ + u32 Tag; /* Same as original command */ + __le32 Residue; /* Amount not transferred */ + u8 Status; /* See below */ +}; + +#define USB_BULK_CS_WRAP_LEN 13 +#define USB_BULK_CS_SIG 0x53425355 /* Spells out 'USBS' */ +#define USB_STATUS_PASS 0 +#define USB_STATUS_FAIL 1 +#define USB_STATUS_PHASE_ERROR 2 + +/* Bulk-only class specific requests */ +#define USB_BULK_RESET_REQUEST 0xff +#define USB_BULK_GET_MAX_LUN_REQUEST 0xfe + +/* Length of a SCSI Command Data Block */ +#define MAX_COMMAND_SIZE 16 + +/* SCSI commands that we recognize */ +#define SC_FORMAT_UNIT 0x04 +#define SC_INQUIRY 0x12 +#define SC_MODE_SELECT_6 0x15 +#define SC_MODE_SELECT_10 0x55 +#define SC_MODE_SENSE_6 0x1a +#define SC_MODE_SENSE_10 0x5a +#define SC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e +#define SC_READ_6 0x08 +#define SC_READ_10 0x28 +#define SC_READ_12 0xa8 +#define SC_READ_CAPACITY 0x25 +#define SC_READ_FORMAT_CAPACITIES 0x23 +#define SC_RELEASE 0x17 +#define SC_REQUEST_SENSE 0x03 +#define SC_RESERVE 0x16 +#define SC_SEND_DIAGNOSTIC 0x1d +#define SC_START_STOP_UNIT 0x1b +#define SC_SYNCHRONIZE_CACHE 0x35 +#define SC_TEST_UNIT_READY 0x00 +#define SC_VERIFY 0x2f +#define SC_WRITE_6 0x0a +#define SC_WRITE_10 0x2a +#define SC_WRITE_12 0xaa + +/* SCSI Sense Key/Additional Sense Code/ASC Qualifier values */ +#define SS_NO_SENSE 0 +#define SS_COMMUNICATION_FAILURE 0x040800 +#define SS_INVALID_COMMAND 0x052000 +#define SS_INVALID_FIELD_IN_CDB 0x052400 +#define SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x052100 +#define SS_LOGICAL_UNIT_NOT_SUPPORTED 0x052500 +#define SS_MEDIUM_NOT_PRESENT 0x023a00 +#define SS_MEDIUM_REMOVAL_PREVENTED 0x055302 +#define SS_NOT_READY_TO_READY_TRANSITION 0x062800 +#define SS_RESET_OCCURRED 0x062900 +#define SS_SAVING_PARAMETERS_NOT_SUPPORTED 0x053900 +#define SS_UNRECOVERED_READ_ERROR 0x031100 +#define SS_WRITE_ERROR 0x030c02 +#define SS_WRITE_PROTECTED 0x072700 + +#define SK(x) ((u8) ((x) >> 16)) /* Sense Key byte, etc. */ +#define ASC(x) ((u8) ((x) >> 8)) +#define ASCQ(x) ((u8) (x)) + + +/*-------------------------------------------------------------------------*/ + +struct lun { + struct file *filp; + loff_t file_length; + loff_t num_sectors; + unsigned int unflushed_bytes; + + unsigned int ro : 1; + unsigned int prevent_medium_removal : 1; + unsigned int registered : 1; + unsigned int info_valid : 1; + + u32 sense_data; + u32 sense_data_info; + u32 unit_attention_data; + + struct device dev; +}; + +#define backing_file_is_open(curlun) ((curlun)->filp != NULL) + + +static struct lun *dev_to_lun(struct device *dev) +{ + return container_of(dev, struct lun, dev); +} + +/* Big enough to hold our biggest descriptor */ +#define EP0_BUFSIZE 256 +#define DELAYED_STATUS (EP0_BUFSIZE + 999) // An impossibly large value + +/* Number of buffers we will use. 2 is enough for double-buffering */ +#define NUM_BUFFERS 2 + +enum fsg_buffer_state { + BUF_STATE_EMPTY = 0, + BUF_STATE_FULL, + BUF_STATE_BUSY +}; + +struct fsg_buffhd { + void *buf; + enum fsg_buffer_state state; + struct fsg_buffhd *next; + + /* The NetChip 2280 is faster, and handles some protocol faults + * better, if we don't submit any short bulk-out read requests. + * So we will record the intended request length here. */ + unsigned int bulk_out_intended_length; + + struct usb_request *inreq; + int inreq_busy; + struct usb_request *outreq; + int outreq_busy; +}; + +enum fsg_state { + /* This one isn't used anywhere */ + FSG_STATE_COMMAND_PHASE = -10, + + FSG_STATE_DATA_PHASE, + FSG_STATE_STATUS_PHASE, + + FSG_STATE_IDLE = 0, + FSG_STATE_ABORT_BULK_OUT, + FSG_STATE_RESET, + FSG_STATE_CONFIG_CHANGE, + FSG_STATE_EXIT, + FSG_STATE_TERMINATED +}; + +enum data_direction { + DATA_DIR_UNKNOWN = 0, + DATA_DIR_FROM_HOST, + DATA_DIR_TO_HOST, + DATA_DIR_NONE +}; + +struct fsg_dev { + struct usb_function function; + struct usb_composite_dev *cdev; + + /* optional "usb_mass_storage" platform device */ + struct platform_device *pdev; + + /* lock protects: state and all the req_busy's */ + spinlock_t lock; + + /* filesem protects: backing files in use */ + struct rw_semaphore filesem; + + /* reference counting: wait until all LUNs are released */ + struct kref ref; + + unsigned int bulk_out_maxpacket; + enum fsg_state state; /* For exception handling */ + + u8 config, new_config; + + unsigned int running : 1; + unsigned int bulk_in_enabled : 1; + unsigned int bulk_out_enabled : 1; + unsigned int phase_error : 1; + unsigned int short_packet_received : 1; + unsigned int bad_lun_okay : 1; + + unsigned long atomic_bitflags; +#define REGISTERED 0 +#define CLEAR_BULK_HALTS 1 +#define SUSPENDED 2 + + struct usb_ep *bulk_in; + struct usb_ep *bulk_out; + + struct fsg_buffhd *next_buffhd_to_fill; + struct fsg_buffhd *next_buffhd_to_drain; + struct fsg_buffhd buffhds[NUM_BUFFERS]; + + int thread_wakeup_needed; + struct completion thread_notifier; + struct task_struct *thread_task; + + int cmnd_size; + u8 cmnd[MAX_COMMAND_SIZE]; + enum data_direction data_dir; + u32 data_size; + u32 data_size_from_cmnd; + u32 tag; + unsigned int lun; + u32 residue; + u32 usb_amount_left; + + unsigned int nluns; + struct lun *luns; + struct lun *curlun; + + u32 buf_size; + const char *vendor; + const char *product; + int release; + + struct switch_dev sdev; + + struct wake_lock wake_lock; +}; + +static inline struct fsg_dev *func_to_dev(struct usb_function *f) +{ + return container_of(f, struct fsg_dev, function); +} + +static int exception_in_progress(struct fsg_dev *fsg) +{ + return (fsg->state > FSG_STATE_IDLE); +} + +/* Make bulk-out requests be divisible by the maxpacket size */ +static void set_bulk_out_req_length(struct fsg_dev *fsg, + struct fsg_buffhd *bh, unsigned int length) +{ + unsigned int rem; + + bh->bulk_out_intended_length = length; + rem = length % fsg->bulk_out_maxpacket; + if (rem > 0) + length += fsg->bulk_out_maxpacket - rem; + bh->outreq->length = length; +} + +static struct fsg_dev *the_fsg; + +static void close_backing_file(struct fsg_dev *fsg, struct lun *curlun); +static void close_all_backing_files(struct fsg_dev *fsg); +static int fsync_sub(struct lun *curlun); + +/*-------------------------------------------------------------------------*/ + +#ifdef DUMP_MSGS + +static void dump_msg(struct fsg_dev *fsg, const char *label, + const u8 *buf, unsigned int length) +{ + if (length < 512) { + DBG(fsg, "%s, length %u:\n", label, length); + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, + 16, 1, buf, length, 0); + } +} + +static void dump_cdb(struct fsg_dev *fsg) +{} + +#else + +static void dump_msg(struct fsg_dev *fsg, const char *label, + const u8 *buf, unsigned int length) +{} + +#ifdef VERBOSE_DEBUG + +static void dump_cdb(struct fsg_dev *fsg) +{ + print_hex_dump(KERN_DEBUG, "SCSI CDB: ", DUMP_PREFIX_NONE, + 16, 1, fsg->cmnd, fsg->cmnd_size, 0); +} + +#else + +static void dump_cdb(struct fsg_dev *fsg) +{} + +#endif /* VERBOSE_DEBUG */ +#endif /* DUMP_MSGS */ + + +/*-------------------------------------------------------------------------*/ + +/* Routines for unaligned data access */ + +static u16 get_be16(u8 *buf) +{ + return ((u16) buf[0] << 8) | ((u16) buf[1]); +} + +static u32 get_be32(u8 *buf) +{ + return ((u32) buf[0] << 24) | ((u32) buf[1] << 16) | + ((u32) buf[2] << 8) | ((u32) buf[3]); +} + +static void put_be16(u8 *buf, u16 val) +{ + buf[0] = val >> 8; + buf[1] = val; +} + +static void put_be32(u8 *buf, u32 val) +{ + buf[0] = val >> 24; + buf[1] = val >> 16; + buf[2] = val >> 8; + buf[3] = val & 0xff; +} + +/*-------------------------------------------------------------------------*/ + +/* + * DESCRIPTORS ... most are static, but strings and (full) configuration + * descriptors are built on demand. Also the (static) config and interface + * descriptors are adjusted during fsg_bind(). + */ + +/* There is only one interface. */ + +static struct usb_interface_descriptor +intf_desc = { + .bLength = sizeof intf_desc, + .bDescriptorType = USB_DT_INTERFACE, + + .bNumEndpoints = 2, /* Adjusted during fsg_bind() */ + .bInterfaceClass = USB_CLASS_MASS_STORAGE, + .bInterfaceSubClass = US_SC_SCSI, + .bInterfaceProtocol = US_PR_BULK, +}; + +/* Three full-speed endpoint descriptors: bulk-in, bulk-out, + * and interrupt-in. */ + +static struct usb_endpoint_descriptor +fs_bulk_in_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + /* wMaxPacketSize set by autoconfiguration */ +}; + +static struct usb_endpoint_descriptor +fs_bulk_out_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + /* wMaxPacketSize set by autoconfiguration */ +}; + +static struct usb_descriptor_header *fs_function[] = { + (struct usb_descriptor_header *) &intf_desc, + (struct usb_descriptor_header *) &fs_bulk_in_desc, + (struct usb_descriptor_header *) &fs_bulk_out_desc, + NULL, +}; +#define FS_FUNCTION_PRE_EP_ENTRIES 2 + + +static struct usb_endpoint_descriptor +hs_bulk_in_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + /* bEndpointAddress copied from fs_bulk_in_desc during fsg_bind() */ + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = __constant_cpu_to_le16(512), +}; + +static struct usb_endpoint_descriptor +hs_bulk_out_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + /* bEndpointAddress copied from fs_bulk_out_desc during fsg_bind() */ + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = __constant_cpu_to_le16(512), + .bInterval = 1, /* NAK every 1 uframe */ +}; + + +static struct usb_descriptor_header *hs_function[] = { + (struct usb_descriptor_header *) &intf_desc, + (struct usb_descriptor_header *) &hs_bulk_in_desc, + (struct usb_descriptor_header *) &hs_bulk_out_desc, + NULL, +}; + +/* Maxpacket and other transfer characteristics vary by speed. */ +static struct usb_endpoint_descriptor * +ep_desc(struct usb_gadget *g, struct usb_endpoint_descriptor *fs, + struct usb_endpoint_descriptor *hs) +{ + if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH) + return hs; + return fs; +} + +/*-------------------------------------------------------------------------*/ + +/* These routines may be called in process context or in_irq */ + +/* Caller must hold fsg->lock */ +static void wakeup_thread(struct fsg_dev *fsg) +{ + /* Tell the main thread that something has happened */ + fsg->thread_wakeup_needed = 1; + if (fsg->thread_task) + wake_up_process(fsg->thread_task); +} + + +static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state) +{ + unsigned long flags; + + DBG(fsg, "raise_exception %d\n", (int)new_state); + /* Do nothing if a higher-priority exception is already in progress. + * If a lower-or-equal priority exception is in progress, preempt it + * and notify the main thread by sending it a signal. */ + spin_lock_irqsave(&fsg->lock, flags); + if (fsg->state <= new_state) { + fsg->state = new_state; + if (fsg->thread_task) + send_sig_info(SIGUSR1, SEND_SIG_FORCED, + fsg->thread_task); + } + spin_unlock_irqrestore(&fsg->lock, flags); +} + + +/*-------------------------------------------------------------------------*/ + +/* Bulk and interrupt endpoint completion handlers. + * These always run in_irq. */ + +static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req) +{ + struct fsg_dev *fsg = ep->driver_data; + struct fsg_buffhd *bh = req->context; + unsigned long flags; + + if (req->status || req->actual != req->length) + DBG(fsg, "%s --> %d, %u/%u\n", __func__, + req->status, req->actual, req->length); + + /* Hold the lock while we update the request and buffer states */ + smp_wmb(); + spin_lock_irqsave(&fsg->lock, flags); + bh->inreq_busy = 0; + bh->state = BUF_STATE_EMPTY; + wakeup_thread(fsg); + spin_unlock_irqrestore(&fsg->lock, flags); +} + +static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req) +{ + struct fsg_dev *fsg = ep->driver_data; + struct fsg_buffhd *bh = req->context; + unsigned long flags; + + dump_msg(fsg, "bulk-out", req->buf, req->actual); + if (req->status || req->actual != bh->bulk_out_intended_length) + DBG(fsg, "%s --> %d, %u/%u\n", __func__, + req->status, req->actual, + bh->bulk_out_intended_length); + + /* Hold the lock while we update the request and buffer states */ + smp_wmb(); + spin_lock_irqsave(&fsg->lock, flags); + bh->outreq_busy = 0; + bh->state = BUF_STATE_FULL; + wakeup_thread(fsg); + spin_unlock_irqrestore(&fsg->lock, flags); +} + +static int fsg_function_setup(struct usb_function *f, + const struct usb_ctrlrequest *ctrl) +{ + struct fsg_dev *fsg = func_to_dev(f); + struct usb_composite_dev *cdev = fsg->cdev; + int value = -EOPNOTSUPP; + u16 w_index = le16_to_cpu(ctrl->wIndex); + u16 w_value = le16_to_cpu(ctrl->wValue); + u16 w_length = le16_to_cpu(ctrl->wLength); + + DBG(fsg, "fsg_function_setup\n"); + /* Handle Bulk-only class-specific requests */ + if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS) { + DBG(fsg, "USB_TYPE_CLASS\n"); + switch (ctrl->bRequest) { + case USB_BULK_RESET_REQUEST: + if (ctrl->bRequestType != (USB_DIR_OUT | + USB_TYPE_CLASS | USB_RECIP_INTERFACE)) + break; + if (w_index != 0 || w_value != 0) { + value = -EDOM; + break; + } + + /* Raise an exception to stop the current operation + * and reinitialize our state. */ + DBG(fsg, "bulk reset request\n"); + raise_exception(fsg, FSG_STATE_RESET); + value = 0; + break; + + case USB_BULK_GET_MAX_LUN_REQUEST: + if (ctrl->bRequestType != (USB_DIR_IN | + USB_TYPE_CLASS | USB_RECIP_INTERFACE)) + break; + if (w_index != 0 || w_value != 0) { + value = -EDOM; + break; + } + VDBG(fsg, "get max LUN\n"); + *(u8 *)cdev->req->buf = fsg->nluns - 1; + value = 1; + break; + } + } + + /* respond with data transfer or status phase? */ + if (value >= 0) { + int rc; + cdev->req->zero = value < w_length; + cdev->req->length = value; + rc = usb_ep_queue(cdev->gadget->ep0, cdev->req, GFP_ATOMIC); + if (rc < 0) + printk("%s setup response queue error\n", __func__); + } + + if (value == -EOPNOTSUPP) + VDBG(fsg, + "unknown class-specific control req " + "%02x.%02x v%04x i%04x l%u\n", + ctrl->bRequestType, ctrl->bRequest, + le16_to_cpu(ctrl->wValue), w_index, w_length); + + return value; +} + +/*-------------------------------------------------------------------------*/ + +/* All the following routines run in process context */ + + +/* Use this for bulk or interrupt transfers, not ep0 */ +static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep, + struct usb_request *req, int *pbusy, + enum fsg_buffer_state *state) +{ + int rc; + unsigned long flags; + + DBG(fsg, "start_transfer req: %p, req->buf: %p\n", req, req->buf); + if (ep == fsg->bulk_in) + dump_msg(fsg, "bulk-in", req->buf, req->length); + + spin_lock_irqsave(&fsg->lock, flags); + *pbusy = 1; + *state = BUF_STATE_BUSY; + spin_unlock_irqrestore(&fsg->lock, flags); + rc = usb_ep_queue(ep, req, GFP_KERNEL); + if (rc != 0) { + *pbusy = 0; + *state = BUF_STATE_EMPTY; + + /* We can't do much more than wait for a reset */ + + /* Note: currently the net2280 driver fails zero-length + * submissions if DMA is enabled. */ + if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP && + req->length == 0)) + WARN(fsg, "error in submission: %s --> %d\n", + (ep == fsg->bulk_in ? "bulk-in" : "bulk-out"), + rc); + } +} + + +static int sleep_thread(struct fsg_dev *fsg) +{ + int rc = 0; + + /* Wait until a signal arrives or we are woken up */ + for (;;) { + try_to_freeze(); + set_current_state(TASK_INTERRUPTIBLE); + if (signal_pending(current)) { + rc = -EINTR; + break; + } + if (fsg->thread_wakeup_needed) + break; + schedule(); + } + __set_current_state(TASK_RUNNING); + fsg->thread_wakeup_needed = 0; + return rc; +} + + +/*-------------------------------------------------------------------------*/ + +static int do_read(struct fsg_dev *fsg) +{ + struct lun *curlun = fsg->curlun; + u32 lba; + struct fsg_buffhd *bh; + int rc; + u32 amount_left; + loff_t file_offset, file_offset_tmp; + unsigned int amount; + unsigned int partial_page; + ssize_t nread; + + /* Get the starting Logical Block Address and check that it's + * not too big */ + if (fsg->cmnd[0] == SC_READ_6) + lba = (fsg->cmnd[1] << 16) | get_be16(&fsg->cmnd[2]); + else { + lba = get_be32(&fsg->cmnd[2]); + + /* We allow DPO (Disable Page Out = don't save data in the + * cache) and FUA (Force Unit Access = don't read from the + * cache), but we don't implement them. */ + if ((fsg->cmnd[1] & ~0x18) != 0) { + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + } + if (lba >= curlun->num_sectors) { + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + return -EINVAL; + } + file_offset = ((loff_t) lba) << 9; + + /* Carry out the file reads */ + amount_left = fsg->data_size_from_cmnd; + if (unlikely(amount_left == 0)) + return -EIO; /* No default reply */ + + for (;;) { + + /* Figure out how much we need to read: + * Try to read the remaining amount. + * But don't read more than the buffer size. + * And don't try to read past the end of the file. + * Finally, if we're not at a page boundary, don't read past + * the next page. + * If this means reading 0 then we were asked to read past + * the end of file. */ + amount = min((unsigned int) amount_left, + (unsigned int)fsg->buf_size); + amount = min((loff_t) amount, + curlun->file_length - file_offset); + partial_page = file_offset & (PAGE_CACHE_SIZE - 1); + if (partial_page > 0) + amount = min(amount, (unsigned int) PAGE_CACHE_SIZE - + partial_page); + + /* Wait for the next buffer to become available */ + bh = fsg->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(fsg); + if (rc) + return rc; + } + + /* If we were asked to read past the end of file, + * end with an empty buffer. */ + if (amount == 0) { + curlun->sense_data = + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + curlun->sense_data_info = file_offset >> 9; + curlun->info_valid = 1; + bh->inreq->length = 0; + bh->state = BUF_STATE_FULL; + break; + } + + /* Perform the read */ + file_offset_tmp = file_offset; + nread = vfs_read(curlun->filp, + (char __user *) bh->buf, + amount, &file_offset_tmp); + VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, + (unsigned long long) file_offset, + (int) nread); + if (signal_pending(current)) + return -EINTR; + + if (nread < 0) { + LDBG(curlun, "error in file read: %d\n", + (int) nread); + nread = 0; + } else if (nread < amount) { + LDBG(curlun, "partial file read: %d/%u\n", + (int) nread, amount); + nread -= (nread & 511); /* Round down to a block */ + } + file_offset += nread; + amount_left -= nread; + fsg->residue -= nread; + bh->inreq->length = nread; + bh->state = BUF_STATE_FULL; + + /* If an error occurred, report it and its position */ + if (nread < amount) { + curlun->sense_data = SS_UNRECOVERED_READ_ERROR; + curlun->sense_data_info = file_offset >> 9; + curlun->info_valid = 1; + break; + } + + if (amount_left == 0) + break; /* No more left to read */ + + /* Send this buffer and go read some more */ + start_transfer(fsg, fsg->bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state); + fsg->next_buffhd_to_fill = bh->next; + } + + return -EIO; /* No default reply */ +} + + +/*-------------------------------------------------------------------------*/ + +static int do_write(struct fsg_dev *fsg) +{ + struct lun *curlun = fsg->curlun; + u32 lba; + struct fsg_buffhd *bh; + int get_some_more; + u32 amount_left_to_req, amount_left_to_write; + loff_t usb_offset, file_offset, file_offset_tmp; + unsigned int amount; + unsigned int partial_page; + ssize_t nwritten; + int rc; + + if (curlun->ro) { + curlun->sense_data = SS_WRITE_PROTECTED; + return -EINVAL; + } + curlun->filp->f_flags &= ~O_SYNC; /* Default is not to wait */ + + /* Get the starting Logical Block Address and check that it's + * not too big */ + if (fsg->cmnd[0] == SC_WRITE_6) + lba = (fsg->cmnd[1] << 16) | get_be16(&fsg->cmnd[2]); + else { + lba = get_be32(&fsg->cmnd[2]); + + /* We allow DPO (Disable Page Out = don't save data in the + * cache) and FUA (Force Unit Access = write directly to the + * medium). We don't implement DPO; we implement FUA by + * performing synchronous output. */ + if ((fsg->cmnd[1] & ~0x18) != 0) { + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + if (fsg->cmnd[1] & 0x08) /* FUA */ + curlun->filp->f_flags |= O_SYNC; + } + if (lba >= curlun->num_sectors) { + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + return -EINVAL; + } + + /* Carry out the file writes */ + get_some_more = 1; + file_offset = usb_offset = ((loff_t) lba) << 9; + amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd; + + while (amount_left_to_write > 0) { + + /* Queue a request for more data from the host */ + bh = fsg->next_buffhd_to_fill; + if (bh->state == BUF_STATE_EMPTY && get_some_more) { + + /* Figure out how much we want to get: + * Try to get the remaining amount. + * But don't get more than the buffer size. + * And don't try to go past the end of the file. + * If we're not at a page boundary, + * don't go past the next page. + * If this means getting 0, then we were asked + * to write past the end of file. + * Finally, round down to a block boundary. */ + amount = min(amount_left_to_req, (u32)fsg->buf_size); + amount = min((loff_t) amount, curlun->file_length - + usb_offset); + partial_page = usb_offset & (PAGE_CACHE_SIZE - 1); + if (partial_page > 0) + amount = min(amount, + (unsigned int) PAGE_CACHE_SIZE - partial_page); + + if (amount == 0) { + get_some_more = 0; + curlun->sense_data = + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + curlun->sense_data_info = usb_offset >> 9; + curlun->info_valid = 1; + continue; + } + amount -= (amount & 511); + if (amount == 0) { + + /* Why were we were asked to transfer a + * partial block? */ + get_some_more = 0; + continue; + } + + /* Get the next buffer */ + usb_offset += amount; + fsg->usb_amount_left -= amount; + amount_left_to_req -= amount; + if (amount_left_to_req == 0) + get_some_more = 0; + + /* amount is always divisible by 512, hence by + * the bulk-out maxpacket size */ + bh->outreq->length = bh->bulk_out_intended_length = + amount; + start_transfer(fsg, fsg->bulk_out, bh->outreq, + &bh->outreq_busy, &bh->state); + fsg->next_buffhd_to_fill = bh->next; + continue; + } + + /* Write the received data to the backing file */ + bh = fsg->next_buffhd_to_drain; + if (bh->state == BUF_STATE_EMPTY && !get_some_more) + break; /* We stopped early */ + if (bh->state == BUF_STATE_FULL) { + smp_rmb(); + fsg->next_buffhd_to_drain = bh->next; + bh->state = BUF_STATE_EMPTY; + + /* Did something go wrong with the transfer? */ + if (bh->outreq->status != 0) { + curlun->sense_data = SS_COMMUNICATION_FAILURE; + curlun->sense_data_info = file_offset >> 9; + curlun->info_valid = 1; + break; + } + + amount = bh->outreq->actual; + if (curlun->file_length - file_offset < amount) { + LERROR(curlun, + "write %u @ %llu beyond end %llu\n", + amount, (unsigned long long) file_offset, + (unsigned long long) curlun->file_length); + amount = curlun->file_length - file_offset; + } + + /* Perform the write */ + file_offset_tmp = file_offset; + nwritten = vfs_write(curlun->filp, + (char __user *) bh->buf, + amount, &file_offset_tmp); + VLDBG(curlun, "file write %u @ %llu -> %d\n", amount, + (unsigned long long) file_offset, + (int) nwritten); + if (signal_pending(current)) + return -EINTR; /* Interrupted! */ + + if (nwritten < 0) { + LDBG(curlun, "error in file write: %d\n", + (int) nwritten); + nwritten = 0; + } else if (nwritten < amount) { + LDBG(curlun, "partial file write: %d/%u\n", + (int) nwritten, amount); + nwritten -= (nwritten & 511); + /* Round down to a block */ + } + file_offset += nwritten; + amount_left_to_write -= nwritten; + fsg->residue -= nwritten; + +#ifdef MAX_UNFLUSHED_BYTES + curlun->unflushed_bytes += nwritten; + if (curlun->unflushed_bytes >= MAX_UNFLUSHED_BYTES) { + fsync_sub(curlun); + curlun->unflushed_bytes = 0; + } +#endif + /* If an error occurred, report it and its position */ + if (nwritten < amount) { + curlun->sense_data = SS_WRITE_ERROR; + curlun->sense_data_info = file_offset >> 9; + curlun->info_valid = 1; + break; + } + + /* Did the host decide to stop early? */ + if (bh->outreq->actual != bh->outreq->length) { + fsg->short_packet_received = 1; + break; + } + continue; + } + + /* Wait for something to happen */ + rc = sleep_thread(fsg); + if (rc) + return rc; + } + + return -EIO; /* No default reply */ +} + + +/*-------------------------------------------------------------------------*/ + +/* Sync the file data, don't bother with the metadata. + * The caller must own fsg->filesem. + * This code was copied from fs/buffer.c:sys_fdatasync(). */ +static int fsync_sub(struct lun *curlun) +{ + struct file *filp = curlun->filp; + struct inode *inode; + int rc, err; + + if (curlun->ro || !filp) + return 0; + if (!filp->f_op->fsync) + return -EINVAL; + + inode = filp->f_path.dentry->d_inode; + mutex_lock(&inode->i_mutex); + rc = filemap_fdatawrite(inode->i_mapping); + err = filp->f_op->fsync(filp, filp->f_path.dentry, 1); + if (!rc) + rc = err; + err = filemap_fdatawait(inode->i_mapping); + if (!rc) + rc = err; + mutex_unlock(&inode->i_mutex); + VLDBG(curlun, "fdatasync -> %d\n", rc); + return rc; +} + +static void fsync_all(struct fsg_dev *fsg) +{ + int i; + + for (i = 0; i < fsg->nluns; ++i) + fsync_sub(&fsg->luns[i]); +} + +static int do_synchronize_cache(struct fsg_dev *fsg) +{ + struct lun *curlun = fsg->curlun; + int rc; + + /* We ignore the requested LBA and write out all file's + * dirty data buffers. */ + rc = fsync_sub(curlun); + if (rc) + curlun->sense_data = SS_WRITE_ERROR; + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +static void invalidate_sub(struct lun *curlun) +{ + struct file *filp = curlun->filp; + struct inode *inode = filp->f_path.dentry->d_inode; + unsigned long rc; + + rc = invalidate_mapping_pages(inode->i_mapping, 0, -1); + VLDBG(curlun, "invalidate_inode_pages -> %ld\n", rc); +} + +static int do_verify(struct fsg_dev *fsg) +{ + struct lun *curlun = fsg->curlun; + u32 lba; + u32 verification_length; + struct fsg_buffhd *bh = fsg->next_buffhd_to_fill; + loff_t file_offset, file_offset_tmp; + u32 amount_left; + unsigned int amount; + ssize_t nread; + + /* Get the starting Logical Block Address and check that it's + * not too big */ + lba = get_be32(&fsg->cmnd[2]); + if (lba >= curlun->num_sectors) { + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + return -EINVAL; + } + + /* We allow DPO (Disable Page Out = don't save data in the + * cache) but we don't implement it. */ + if ((fsg->cmnd[1] & ~0x10) != 0) { + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + + verification_length = get_be16(&fsg->cmnd[7]); + if (unlikely(verification_length == 0)) + return -EIO; /* No default reply */ + + /* Prepare to carry out the file verify */ + amount_left = verification_length << 9; + file_offset = ((loff_t) lba) << 9; + + /* Write out all the dirty buffers before invalidating them */ + fsync_sub(curlun); + if (signal_pending(current)) + return -EINTR; + + invalidate_sub(curlun); + if (signal_pending(current)) + return -EINTR; + + /* Just try to read the requested blocks */ + while (amount_left > 0) { + + /* Figure out how much we need to read: + * Try to read the remaining amount, but not more than + * the buffer size. + * And don't try to read past the end of the file. + * If this means reading 0 then we were asked to read + * past the end of file. */ + amount = min((unsigned int) amount_left, + (unsigned int)fsg->buf_size); + amount = min((loff_t) amount, + curlun->file_length - file_offset); + if (amount == 0) { + curlun->sense_data = + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + curlun->sense_data_info = file_offset >> 9; + curlun->info_valid = 1; + break; + } + + /* Perform the read */ + file_offset_tmp = file_offset; + nread = vfs_read(curlun->filp, + (char __user *) bh->buf, + amount, &file_offset_tmp); + VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, + (unsigned long long) file_offset, + (int) nread); + if (signal_pending(current)) + return -EINTR; + + if (nread < 0) { + LDBG(curlun, "error in file verify: %d\n", + (int) nread); + nread = 0; + } else if (nread < amount) { + LDBG(curlun, "partial file verify: %d/%u\n", + (int) nread, amount); + nread -= (nread & 511); /* Round down to a sector */ + } + if (nread == 0) { + curlun->sense_data = SS_UNRECOVERED_READ_ERROR; + curlun->sense_data_info = file_offset >> 9; + curlun->info_valid = 1; + break; + } + file_offset += nread; + amount_left -= nread; + } + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh) +{ + u8 *buf = (u8 *) bh->buf; + + if (!fsg->curlun) { /* Unsupported LUNs are okay */ + fsg->bad_lun_okay = 1; + memset(buf, 0, 36); + buf[0] = 0x7f; /* Unsupported, no device-type */ + return 36; + } + + memset(buf, 0, 8); /* Non-removable, direct-access device */ + + buf[1] = 0x80; /* set removable bit */ + buf[2] = 2; /* ANSI SCSI level 2 */ + buf[3] = 2; /* SCSI-2 INQUIRY data format */ + buf[4] = 31; /* Additional length */ + /* No special options */ + sprintf(buf + 8, "%-8s%-16s%04x", fsg->vendor, + fsg->product, fsg->release); + return 36; +} + + +static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh) +{ + struct lun *curlun = fsg->curlun; + u8 *buf = (u8 *) bh->buf; + u32 sd, sdinfo; + int valid; + + /* + * From the SCSI-2 spec., section 7.9 (Unit attention condition): + * + * If a REQUEST SENSE command is received from an initiator + * with a pending unit attention condition (before the target + * generates the contingent allegiance condition), then the + * target shall either: + * a) report any pending sense data and preserve the unit + * attention condition on the logical unit, or, + * b) report the unit attention condition, may discard any + * pending sense data, and clear the unit attention + * condition on the logical unit for that initiator. + * + * FSG normally uses option a); enable this code to use option b). + */ +#if 0 + if (curlun && curlun->unit_attention_data != SS_NO_SENSE) { + curlun->sense_data = curlun->unit_attention_data; + curlun->unit_attention_data = SS_NO_SENSE; + } +#endif + + if (!curlun) { /* Unsupported LUNs are okay */ + fsg->bad_lun_okay = 1; + sd = SS_LOGICAL_UNIT_NOT_SUPPORTED; + sdinfo = 0; + valid = 0; + } else { + sd = curlun->sense_data; + sdinfo = curlun->sense_data_info; + valid = curlun->info_valid << 7; + curlun->sense_data = SS_NO_SENSE; + curlun->sense_data_info = 0; + curlun->info_valid = 0; + } + + memset(buf, 0, 18); + buf[0] = valid | 0x70; /* Valid, current error */ + buf[2] = SK(sd); + put_be32(&buf[3], sdinfo); /* Sense information */ + buf[7] = 18 - 8; /* Additional sense length */ + buf[12] = ASC(sd); + buf[13] = ASCQ(sd); + return 18; +} + + +static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh) +{ + struct lun *curlun = fsg->curlun; + u32 lba = get_be32(&fsg->cmnd[2]); + int pmi = fsg->cmnd[8]; + u8 *buf = (u8 *) bh->buf; + + /* Check the PMI and LBA fields */ + if (pmi > 1 || (pmi == 0 && lba != 0)) { + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + + put_be32(&buf[0], curlun->num_sectors - 1); /* Max logical block */ + put_be32(&buf[4], 512); /* Block length */ + return 8; +} + + +static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh) +{ + struct lun *curlun = fsg->curlun; + int mscmnd = fsg->cmnd[0]; + u8 *buf = (u8 *) bh->buf; + u8 *buf0 = buf; + int pc, page_code; + int changeable_values, all_pages; + int valid_page = 0; + int len, limit; + + if ((fsg->cmnd[1] & ~0x08) != 0) { /* Mask away DBD */ + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + pc = fsg->cmnd[2] >> 6; + page_code = fsg->cmnd[2] & 0x3f; + if (pc == 3) { + curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED; + return -EINVAL; + } + changeable_values = (pc == 1); + all_pages = (page_code == 0x3f); + + /* Write the mode parameter header. Fixed values are: default + * medium type, no cache control (DPOFUA), and no block descriptors. + * The only variable value is the WriteProtect bit. We will fill in + * the mode data length later. */ + memset(buf, 0, 8); + if (mscmnd == SC_MODE_SENSE_6) { + buf[2] = (curlun->ro ? 0x80 : 0x00); /* WP, DPOFUA */ + buf += 4; + limit = 255; + } else { /* SC_MODE_SENSE_10 */ + buf[3] = (curlun->ro ? 0x80 : 0x00); /* WP, DPOFUA */ + buf += 8; + limit = 65535; + } + + /* No block descriptors */ + + /* Disabled to workaround USB reset problems with a Vista host. + */ +#if 0 + /* The mode pages, in numerical order. The only page we support + * is the Caching page. */ + if (page_code == 0x08 || all_pages) { + valid_page = 1; + buf[0] = 0x08; /* Page code */ + buf[1] = 10; /* Page length */ + memset(buf+2, 0, 10); /* None of the fields are changeable */ + + if (!changeable_values) { + buf[2] = 0x04; /* Write cache enable, */ + /* Read cache not disabled */ + /* No cache retention priorities */ + put_be16(&buf[4], 0xffff); /* Don't disable prefetch */ + /* Minimum prefetch = 0 */ + put_be16(&buf[8], 0xffff); /* Maximum prefetch */ + /* Maximum prefetch ceiling */ + put_be16(&buf[10], 0xffff); + } + buf += 12; + } +#else + valid_page = 1; +#endif + + /* Check that a valid page was requested and the mode data length + * isn't too long. */ + len = buf - buf0; + if (!valid_page || len > limit) { + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + + /* Store the mode data length */ + if (mscmnd == SC_MODE_SENSE_6) { + /* WIN Vista expects len = 0xC0 */ + if (fsg->data_size_from_cmnd > len) + len = fsg->data_size_from_cmnd; + buf0[0] = len - 1; + } else { + put_be16(buf0, len - 2); + } + return len; +} + +static int do_start_stop(struct fsg_dev *fsg) +{ + struct lun *curlun = fsg->curlun; + int loej, start; + + /* int immed = fsg->cmnd[1] & 0x01; */ + loej = fsg->cmnd[4] & 0x02; + start = fsg->cmnd[4] & 0x01; + + if (loej) { + /* eject request from the host */ + if (backing_file_is_open(curlun)) { + close_backing_file(fsg, curlun); + curlun->unit_attention_data = SS_MEDIUM_NOT_PRESENT; + } + } + + return 0; +} + +static int do_prevent_allow(struct fsg_dev *fsg) +{ + struct lun *curlun = fsg->curlun; + int prevent; + + prevent = fsg->cmnd[4] & 0x01; + if ((fsg->cmnd[4] & ~0x01) != 0) { /* Mask away Prevent */ + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + + if (curlun->prevent_medium_removal && !prevent) + fsync_sub(curlun); + curlun->prevent_medium_removal = prevent; + return 0; +} + + +static int do_read_format_capacities(struct fsg_dev *fsg, + struct fsg_buffhd *bh) +{ + struct lun *curlun = fsg->curlun; + u8 *buf = (u8 *) bh->buf; + + buf[0] = buf[1] = buf[2] = 0; + buf[3] = 8; /* Only the Current/Maximum Capacity Descriptor */ + buf += 4; + + put_be32(&buf[0], curlun->num_sectors); /* Number of blocks */ + put_be32(&buf[4], 512); /* Block length */ + buf[4] = 0x02; /* Current capacity */ + return 12; +} + + +static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh) +{ + struct lun *curlun = fsg->curlun; + + /* We don't support MODE SELECT */ + curlun->sense_data = SS_INVALID_COMMAND; + return -EINVAL; +} + + +/*-------------------------------------------------------------------------*/ +#if 0 +static int write_zero(struct fsg_dev *fsg) +{ + struct fsg_buffhd *bh; + int rc; + + DBG(fsg, "write_zero\n"); + /* Wait for the next buffer to become available */ + bh = fsg->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(fsg); + if (rc) + return rc; + } + + bh->inreq->length = 0; + start_transfer(fsg, fsg->bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state); + + fsg->next_buffhd_to_fill = bh->next; + return 0; +} +#endif + +static int throw_away_data(struct fsg_dev *fsg) +{ + struct fsg_buffhd *bh; + u32 amount; + int rc; + + DBG(fsg, "throw_away_data\n"); + while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY || + fsg->usb_amount_left > 0) { + + /* Throw away the data in a filled buffer */ + if (bh->state == BUF_STATE_FULL) { + smp_rmb(); + bh->state = BUF_STATE_EMPTY; + fsg->next_buffhd_to_drain = bh->next; + + /* A short packet or an error ends everything */ + if (bh->outreq->actual != bh->outreq->length || + bh->outreq->status != 0) { + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); + return -EINTR; + } + continue; + } + + /* Try to submit another request if we need one */ + bh = fsg->next_buffhd_to_fill; + if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) { + amount = min(fsg->usb_amount_left, (u32) fsg->buf_size); + + /* amount is always divisible by 512, hence by + * the bulk-out maxpacket size */ + bh->outreq->length = bh->bulk_out_intended_length = + amount; + start_transfer(fsg, fsg->bulk_out, bh->outreq, + &bh->outreq_busy, &bh->state); + fsg->next_buffhd_to_fill = bh->next; + fsg->usb_amount_left -= amount; + continue; + } + + /* Otherwise wait for something to happen */ + rc = sleep_thread(fsg); + if (rc) + return rc; + } + return 0; +} + + +static int finish_reply(struct fsg_dev *fsg) +{ + struct fsg_buffhd *bh = fsg->next_buffhd_to_fill; + int rc = 0; + + switch (fsg->data_dir) { + case DATA_DIR_NONE: + break; /* Nothing to send */ + + case DATA_DIR_UNKNOWN: + rc = -EINVAL; + break; + + /* All but the last buffer of data must have already been sent */ + case DATA_DIR_TO_HOST: + if (fsg->data_size == 0) + ; /* Nothing to send */ + + /* If there's no residue, simply send the last buffer */ + else if (fsg->residue == 0) { + start_transfer(fsg, fsg->bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state); + fsg->next_buffhd_to_fill = bh->next; + } else { + start_transfer(fsg, fsg->bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state); + fsg->next_buffhd_to_fill = bh->next; +#if 0 + /* this is unnecessary, and was causing problems with MacOS */ + if (bh->inreq->length > 0) + write_zero(fsg); +#endif + } + break; + + /* We have processed all we want from the data the host has sent. + * There may still be outstanding bulk-out requests. */ + case DATA_DIR_FROM_HOST: + if (fsg->residue == 0) + ; /* Nothing to receive */ + + /* Did the host stop sending unexpectedly early? */ + else if (fsg->short_packet_received) { + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); + rc = -EINTR; + } + + /* We haven't processed all the incoming data. Even though + * we may be allowed to stall, doing so would cause a race. + * The controller may already have ACK'ed all the remaining + * bulk-out packets, in which case the host wouldn't see a + * STALL. Not realizing the endpoint was halted, it wouldn't + * clear the halt -- leading to problems later on. */ +#if 0 + fsg_set_halt(fsg, fsg->bulk_out); + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); + rc = -EINTR; +#endif + + /* We can't stall. Read in the excess data and throw it + * all away. */ + else + rc = throw_away_data(fsg); + break; + } + return rc; +} + + +static int send_status(struct fsg_dev *fsg) +{ + struct lun *curlun = fsg->curlun; + struct fsg_buffhd *bh; + int rc; + u8 status = USB_STATUS_PASS; + u32 sd, sdinfo = 0; + struct bulk_cs_wrap *csw; + + DBG(fsg, "send_status\n"); + /* Wait for the next buffer to become available */ + bh = fsg->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(fsg); + if (rc) + return rc; + } + + if (curlun) { + sd = curlun->sense_data; + sdinfo = curlun->sense_data_info; + } else if (fsg->bad_lun_okay) + sd = SS_NO_SENSE; + else + sd = SS_LOGICAL_UNIT_NOT_SUPPORTED; + + if (fsg->phase_error) { + DBG(fsg, "sending phase-error status\n"); + status = USB_STATUS_PHASE_ERROR; + sd = SS_INVALID_COMMAND; + } else if (sd != SS_NO_SENSE) { + DBG(fsg, "sending command-failure status\n"); + status = USB_STATUS_FAIL; + VDBG(fsg, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;" + " info x%x\n", + SK(sd), ASC(sd), ASCQ(sd), sdinfo); + } + + csw = bh->buf; + + /* Store and send the Bulk-only CSW */ + csw->Signature = __constant_cpu_to_le32(USB_BULK_CS_SIG); + csw->Tag = fsg->tag; + csw->Residue = cpu_to_le32(fsg->residue); + csw->Status = status; + + bh->inreq->length = USB_BULK_CS_WRAP_LEN; + start_transfer(fsg, fsg->bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state); + + fsg->next_buffhd_to_fill = bh->next; + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +/* Check whether the command is properly formed and whether its data size + * and direction agree with the values we already have. */ +static int check_command(struct fsg_dev *fsg, int cmnd_size, + enum data_direction data_dir, unsigned int mask, + int needs_medium, const char *name) +{ + int i; + int lun = fsg->cmnd[1] >> 5; + static const char dirletter[4] = {'u', 'o', 'i', 'n'}; + char hdlen[20]; + struct lun *curlun; + + hdlen[0] = 0; + if (fsg->data_dir != DATA_DIR_UNKNOWN) + sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir], + fsg->data_size); + VDBG(fsg, "SCSI command: %s; Dc=%d, D%c=%u; Hc=%d%s\n", + name, cmnd_size, dirletter[(int) data_dir], + fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen); + + /* We can't reply at all until we know the correct data direction + * and size. */ + if (fsg->data_size_from_cmnd == 0) + data_dir = DATA_DIR_NONE; + if (fsg->data_dir == DATA_DIR_UNKNOWN) { /* CB or CBI */ + fsg->data_dir = data_dir; + fsg->data_size = fsg->data_size_from_cmnd; + + } else { /* Bulk-only */ + if (fsg->data_size < fsg->data_size_from_cmnd) { + + /* Host data size < Device data size is a phase error. + * Carry out the command, but only transfer as much + * as we are allowed. */ + DBG(fsg, "phase error 1\n"); + fsg->data_size_from_cmnd = fsg->data_size; + fsg->phase_error = 1; + } + } + fsg->residue = fsg->usb_amount_left = fsg->data_size; + + /* Conflicting data directions is a phase error */ + if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) { + fsg->phase_error = 1; + DBG(fsg, "phase error 2\n"); + return -EINVAL; + } + + /* Verify the length of the command itself */ + if (cmnd_size != fsg->cmnd_size) { + + /* Special case workaround: MS-Windows issues REQUEST SENSE + * and INQUIRY with cbw->Length == 12 (it should be 6). */ + if ((fsg->cmnd[0] == SC_REQUEST_SENSE || fsg->cmnd[0] == SC_INQUIRY) + && fsg->cmnd_size == 12) + cmnd_size = fsg->cmnd_size; + else { + fsg->phase_error = 1; + return -EINVAL; + } + } + + /* Check that the LUN values are consistent */ + if (fsg->lun != lun) + DBG(fsg, "using LUN %d from CBW, " + "not LUN %d from CDB\n", + fsg->lun, lun); + + /* Check the LUN */ + if (fsg->lun >= 0 && fsg->lun < fsg->nluns) { + fsg->curlun = curlun = &fsg->luns[fsg->lun]; + if (fsg->cmnd[0] != SC_REQUEST_SENSE) { + curlun->sense_data = SS_NO_SENSE; + curlun->sense_data_info = 0; + curlun->info_valid = 0; + } + } else { + fsg->curlun = curlun = NULL; + fsg->bad_lun_okay = 0; + + /* INQUIRY and REQUEST SENSE commands are explicitly allowed + * to use unsupported LUNs; all others may not. */ + if (fsg->cmnd[0] != SC_INQUIRY && + fsg->cmnd[0] != SC_REQUEST_SENSE) { + DBG(fsg, "unsupported LUN %d\n", fsg->lun); + return -EINVAL; + } + } + + /* If a unit attention condition exists, only INQUIRY and + * REQUEST SENSE commands are allowed; anything else must fail. */ + if (curlun && curlun->unit_attention_data != SS_NO_SENSE && + fsg->cmnd[0] != SC_INQUIRY && + fsg->cmnd[0] != SC_REQUEST_SENSE) { + curlun->sense_data = curlun->unit_attention_data; + curlun->unit_attention_data = SS_NO_SENSE; + return -EINVAL; + } + + /* Check that only command bytes listed in the mask are non-zero */ + fsg->cmnd[1] &= 0x1f; /* Mask away the LUN */ + for (i = 1; i < cmnd_size; ++i) { + if (fsg->cmnd[i] && !(mask & (1 << i))) { + if (curlun) + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + DBG(fsg, "SS_INVALID_FIELD_IN_CDB\n"); + return -EINVAL; + } + } + + /* If the medium isn't mounted and the command needs to access + * it, return an error. */ + if (curlun && !backing_file_is_open(curlun) && needs_medium) { + curlun->sense_data = SS_MEDIUM_NOT_PRESENT; + DBG(fsg, "SS_MEDIUM_NOT_PRESENT\n"); + return -EINVAL; + } + + return 0; +} + + +static int do_scsi_command(struct fsg_dev *fsg) +{ + struct fsg_buffhd *bh; + int rc; + int reply = -EINVAL; + int i; + static char unknown[16]; + + dump_cdb(fsg); + + /* Wait for the next buffer to become available for data or status */ + bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(fsg); + if (rc) + return rc; + } + fsg->phase_error = 0; + fsg->short_packet_received = 0; + + down_read(&fsg->filesem); /* We're using the backing file */ + switch (fsg->cmnd[0]) { + + case SC_INQUIRY: + fsg->data_size_from_cmnd = fsg->cmnd[4]; + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, + (1<<4), 0, + "INQUIRY")) == 0) + reply = do_inquiry(fsg, bh); + break; + + case SC_MODE_SELECT_6: + fsg->data_size_from_cmnd = fsg->cmnd[4]; + if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST, + (1<<1) | (1<<4), 0, + "MODE SELECT(6)")) == 0) + reply = do_mode_select(fsg, bh); + break; + + case SC_MODE_SELECT_10: + fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]); + if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST, + (1<<1) | (3<<7), 0, + "MODE SELECT(10)")) == 0) + reply = do_mode_select(fsg, bh); + break; + + case SC_MODE_SENSE_6: + fsg->data_size_from_cmnd = fsg->cmnd[4]; + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, + (1<<1) | (1<<2) | (1<<4), 0, + "MODE SENSE(6)")) == 0) + reply = do_mode_sense(fsg, bh); + break; + + case SC_MODE_SENSE_10: + fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]); + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, + (1<<1) | (1<<2) | (3<<7), 0, + "MODE SENSE(10)")) == 0) + reply = do_mode_sense(fsg, bh); + break; + + case SC_PREVENT_ALLOW_MEDIUM_REMOVAL: + fsg->data_size_from_cmnd = 0; + if ((reply = check_command(fsg, 6, DATA_DIR_NONE, + (1<<4), 0, + "PREVENT-ALLOW MEDIUM REMOVAL")) == 0) + reply = do_prevent_allow(fsg); + break; + + case SC_READ_6: + i = fsg->cmnd[4]; + fsg->data_size_from_cmnd = (i == 0 ? 256 : i) << 9; + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, + (7<<1) | (1<<4), 1, + "READ(6)")) == 0) + reply = do_read(fsg); + break; + + case SC_READ_10: + fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]) << 9; + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, + (1<<1) | (0xf<<2) | (3<<7), 1, + "READ(10)")) == 0) + reply = do_read(fsg); + break; + + case SC_READ_12: + fsg->data_size_from_cmnd = get_be32(&fsg->cmnd[6]) << 9; + if ((reply = check_command(fsg, 12, DATA_DIR_TO_HOST, + (1<<1) | (0xf<<2) | (0xf<<6), 1, + "READ(12)")) == 0) + reply = do_read(fsg); + break; + + case SC_READ_CAPACITY: + fsg->data_size_from_cmnd = 8; + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, + (0xf<<2) | (1<<8), 1, + "READ CAPACITY")) == 0) + reply = do_read_capacity(fsg, bh); + break; + + case SC_READ_FORMAT_CAPACITIES: + fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]); + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, + (3<<7), 1, + "READ FORMAT CAPACITIES")) == 0) + reply = do_read_format_capacities(fsg, bh); + break; + + case SC_REQUEST_SENSE: + fsg->data_size_from_cmnd = fsg->cmnd[4]; + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, + (1<<4), 0, + "REQUEST SENSE")) == 0) + reply = do_request_sense(fsg, bh); + break; + + case SC_START_STOP_UNIT: + fsg->data_size_from_cmnd = 0; + if ((reply = check_command(fsg, 6, DATA_DIR_NONE, + (1<<1) | (1<<4), 0, + "START-STOP UNIT")) == 0) + reply = do_start_stop(fsg); + break; + + case SC_SYNCHRONIZE_CACHE: + fsg->data_size_from_cmnd = 0; + if ((reply = check_command(fsg, 10, DATA_DIR_NONE, + (0xf<<2) | (3<<7), 1, + "SYNCHRONIZE CACHE")) == 0) + reply = do_synchronize_cache(fsg); + break; + + case SC_TEST_UNIT_READY: + fsg->data_size_from_cmnd = 0; + reply = check_command(fsg, 6, DATA_DIR_NONE, + 0, 1, + "TEST UNIT READY"); + break; + + /* Although optional, this command is used by MS-Windows. We + * support a minimal version: BytChk must be 0. */ + case SC_VERIFY: + fsg->data_size_from_cmnd = 0; + if ((reply = check_command(fsg, 10, DATA_DIR_NONE, + (1<<1) | (0xf<<2) | (3<<7), 1, + "VERIFY")) == 0) + reply = do_verify(fsg); + break; + + case SC_WRITE_6: + i = fsg->cmnd[4]; + fsg->data_size_from_cmnd = (i == 0 ? 256 : i) << 9; + if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST, + (7<<1) | (1<<4), 1, + "WRITE(6)")) == 0) + reply = do_write(fsg); + break; + + case SC_WRITE_10: + fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]) << 9; + if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST, + (1<<1) | (0xf<<2) | (3<<7), 1, + "WRITE(10)")) == 0) + reply = do_write(fsg); + break; + + case SC_WRITE_12: + fsg->data_size_from_cmnd = get_be32(&fsg->cmnd[6]) << 9; + if ((reply = check_command(fsg, 12, DATA_DIR_FROM_HOST, + (1<<1) | (0xf<<2) | (0xf<<6), 1, + "WRITE(12)")) == 0) + reply = do_write(fsg); + break; + + /* Some mandatory commands that we recognize but don't implement. + * They don't mean much in this setting. It's left as an exercise + * for anyone interested to implement RESERVE and RELEASE in terms + * of Posix locks. */ + case SC_FORMAT_UNIT: + case SC_RELEASE: + case SC_RESERVE: + case SC_SEND_DIAGNOSTIC: + /* Fall through */ + + default: + fsg->data_size_from_cmnd = 0; + sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]); + if ((reply = check_command(fsg, fsg->cmnd_size, + DATA_DIR_UNKNOWN, 0xff, 0, unknown)) == 0) { + fsg->curlun->sense_data = SS_INVALID_COMMAND; + reply = -EINVAL; + } + break; + } + up_read(&fsg->filesem); + + VDBG(fsg, "reply: %d, fsg->data_size_from_cmnd: %d\n", + reply, fsg->data_size_from_cmnd); + if (reply == -EINTR || signal_pending(current)) + return -EINTR; + + /* Set up the single reply buffer for finish_reply() */ + if (reply == -EINVAL) + reply = 0; /* Error reply length */ + if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) { + reply = min((u32) reply, fsg->data_size_from_cmnd); + bh->inreq->length = reply; + bh->state = BUF_STATE_FULL; + fsg->residue -= reply; + } /* Otherwise it's already set */ + + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh) +{ + struct usb_request *req = bh->outreq; + struct bulk_cb_wrap *cbw = req->buf; + + /* Was this a real packet? */ + if (req->status) + return -EINVAL; + + /* Is the CBW valid? */ + if (req->actual != USB_BULK_CB_WRAP_LEN || + cbw->Signature != __constant_cpu_to_le32( + USB_BULK_CB_SIG)) { + DBG(fsg, "invalid CBW: len %u sig 0x%x\n", + req->actual, + le32_to_cpu(cbw->Signature)); + return -EINVAL; + } + + /* Is the CBW meaningful? */ + if (cbw->Lun >= MAX_LUNS || cbw->Flags & ~USB_BULK_IN_FLAG || + cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) { + DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, " + "cmdlen %u\n", + cbw->Lun, cbw->Flags, cbw->Length); + return -EINVAL; + } + + /* Save the command for later */ + fsg->cmnd_size = cbw->Length; + memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size); + if (cbw->Flags & USB_BULK_IN_FLAG) + fsg->data_dir = DATA_DIR_TO_HOST; + else + fsg->data_dir = DATA_DIR_FROM_HOST; + fsg->data_size = le32_to_cpu(cbw->DataTransferLength); + if (fsg->data_size == 0) + fsg->data_dir = DATA_DIR_NONE; + fsg->lun = cbw->Lun; + fsg->tag = cbw->Tag; + return 0; +} + + +static int get_next_command(struct fsg_dev *fsg) +{ + struct fsg_buffhd *bh; + int rc = 0; + + /* Wait for the next buffer to become available */ + bh = fsg->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(fsg); + if (rc) { + usb_ep_dequeue(fsg->bulk_out, bh->outreq); + bh->outreq_busy = 0; + bh->state = BUF_STATE_EMPTY; + return rc; + } + } + + /* Queue a request to read a Bulk-only CBW */ + set_bulk_out_req_length(fsg, bh, USB_BULK_CB_WRAP_LEN); + start_transfer(fsg, fsg->bulk_out, bh->outreq, + &bh->outreq_busy, &bh->state); + + /* We will drain the buffer in software, which means we + * can reuse it for the next filling. No need to advance + * next_buffhd_to_fill. */ + + /* Wait for the CBW to arrive */ + while (bh->state != BUF_STATE_FULL) { + rc = sleep_thread(fsg); + if (rc) { + usb_ep_dequeue(fsg->bulk_out, bh->outreq); + bh->outreq_busy = 0; + bh->state = BUF_STATE_EMPTY; + return rc; + } + } + smp_rmb(); + rc = received_cbw(fsg, bh); + bh->state = BUF_STATE_EMPTY; + + return rc; +} + + +/*-------------------------------------------------------------------------*/ + +static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep, + const struct usb_endpoint_descriptor *d) +{ + int rc; + + DBG(fsg, "usb_ep_enable %s\n", ep->name); + ep->driver_data = fsg; + rc = usb_ep_enable(ep, d); + if (rc) + ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc); + return rc; +} + +static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep, + struct usb_request **preq) +{ + *preq = usb_ep_alloc_request(ep, GFP_ATOMIC); + if (*preq) + return 0; + ERROR(fsg, "can't allocate request for %s\n", ep->name); + return -ENOMEM; +} + +/* + * Reset interface setting and re-init endpoint state (toggle etc). + * Call with altsetting < 0 to disable the interface. The only other + * available altsetting is 0, which enables the interface. + */ +static int do_set_interface(struct fsg_dev *fsg, int altsetting) +{ + struct usb_composite_dev *cdev = fsg->cdev; + int rc = 0; + int i; + const struct usb_endpoint_descriptor *d; + + if (fsg->running) + DBG(fsg, "reset interface\n"); +reset: + /* Disable the endpoints */ + if (fsg->bulk_in_enabled) { + DBG(fsg, "usb_ep_disable %s\n", fsg->bulk_in->name); + usb_ep_disable(fsg->bulk_in); + fsg->bulk_in_enabled = 0; + } + if (fsg->bulk_out_enabled) { + DBG(fsg, "usb_ep_disable %s\n", fsg->bulk_out->name); + usb_ep_disable(fsg->bulk_out); + fsg->bulk_out_enabled = 0; + } + + /* Deallocate the requests */ + for (i = 0; i < NUM_BUFFERS; ++i) { + struct fsg_buffhd *bh = &fsg->buffhds[i]; + if (bh->inreq) { + usb_ep_free_request(fsg->bulk_in, bh->inreq); + bh->inreq = NULL; + } + if (bh->outreq) { + usb_ep_free_request(fsg->bulk_out, bh->outreq); + bh->outreq = NULL; + } + } + + + fsg->running = 0; + if (altsetting < 0 || rc != 0) + return rc; + + DBG(fsg, "set interface %d\n", altsetting); + + /* Enable the endpoints */ + d = ep_desc(cdev->gadget, &fs_bulk_in_desc, &hs_bulk_in_desc); + if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0) + goto reset; + fsg->bulk_in_enabled = 1; + + d = ep_desc(cdev->gadget, &fs_bulk_out_desc, &hs_bulk_out_desc); + if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0) + goto reset; + fsg->bulk_out_enabled = 1; + fsg->bulk_out_maxpacket = le16_to_cpu(d->wMaxPacketSize); + + /* Allocate the requests */ + for (i = 0; i < NUM_BUFFERS; ++i) { + struct fsg_buffhd *bh = &fsg->buffhds[i]; + + rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq); + if (rc != 0) + goto reset; + rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq); + if (rc != 0) + goto reset; + bh->inreq->buf = bh->outreq->buf = bh->buf; + bh->inreq->context = bh->outreq->context = bh; + bh->inreq->complete = bulk_in_complete; + bh->outreq->complete = bulk_out_complete; + } + + fsg->running = 1; + for (i = 0; i < fsg->nluns; ++i) + fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED; + + return rc; +} + +static void adjust_wake_lock(struct fsg_dev *fsg) +{ + int ums_active = 0; + int i; + unsigned long flags; + + spin_lock_irqsave(&fsg->lock, flags); + + if (fsg->config) { + for (i = 0; i < fsg->nluns; ++i) { + if (backing_file_is_open(&fsg->luns[i])) + ums_active = 1; + } + } + + if (ums_active) + wake_lock(&fsg->wake_lock); + else + wake_unlock(&fsg->wake_lock); + + spin_unlock_irqrestore(&fsg->lock, flags); +} + +/* + * Change our operational configuration. This code must agree with the code + * that returns config descriptors, and with interface altsetting code. + * + * It's also responsible for power management interactions. Some + * configurations might not work with our current power sources. + * For now we just assume the gadget is always self-powered. + */ +static int do_set_config(struct fsg_dev *fsg, u8 new_config) +{ + int rc = 0; + + /* Disable the single interface */ + if (fsg->config != 0) { + DBG(fsg, "reset config\n"); + fsg->config = 0; + rc = do_set_interface(fsg, -1); + } + + /* Enable the interface */ + if (new_config != 0) { + fsg->config = new_config; + if ((rc = do_set_interface(fsg, 0)) != 0) + fsg->config = 0; // Reset on errors + } + + switch_set_state(&fsg->sdev, new_config); + adjust_wake_lock(fsg); + return rc; +} + + +/*-------------------------------------------------------------------------*/ + +static void handle_exception(struct fsg_dev *fsg) +{ + siginfo_t info; + int sig; + int i; + int num_active; + struct fsg_buffhd *bh; + enum fsg_state old_state; + u8 new_config; + struct lun *curlun; + int rc; + unsigned long flags; + + DBG(fsg, "handle_exception state: %d\n", (int)fsg->state); + /* Clear the existing signals. Anything but SIGUSR1 is converted + * into a high-priority EXIT exception. */ + for (;;) { + sig = dequeue_signal_lock(current, ¤t->blocked, &info); + if (!sig) + break; + if (sig != SIGUSR1) { + if (fsg->state < FSG_STATE_EXIT) + DBG(fsg, "Main thread exiting on signal\n"); + raise_exception(fsg, FSG_STATE_EXIT); + } + } + + /* Cancel all the pending transfers */ + for (i = 0; i < NUM_BUFFERS; ++i) { + bh = &fsg->buffhds[i]; + if (bh->inreq_busy) + usb_ep_dequeue(fsg->bulk_in, bh->inreq); + if (bh->outreq_busy) + usb_ep_dequeue(fsg->bulk_out, bh->outreq); + } + + /* Wait until everything is idle */ + for (;;) { + num_active = 0; + for (i = 0; i < NUM_BUFFERS; ++i) { + bh = &fsg->buffhds[i]; + num_active += bh->outreq_busy; + } + if (num_active == 0) + break; + if (sleep_thread(fsg)) + return; + } + + /* + * Do NOT flush the fifo after set_interface() + * Otherwise, it results in some data being lost + */ + if ((fsg->state != FSG_STATE_CONFIG_CHANGE) || + (fsg->new_config != 1)) { + /* Clear out the controller's fifos */ + if (fsg->bulk_in_enabled) + usb_ep_fifo_flush(fsg->bulk_in); + if (fsg->bulk_out_enabled) + usb_ep_fifo_flush(fsg->bulk_out); + } + /* Reset the I/O buffer states and pointers, the SCSI + * state, and the exception. Then invoke the handler. */ + spin_lock_irqsave(&fsg->lock, flags); + + for (i = 0; i < NUM_BUFFERS; ++i) { + bh = &fsg->buffhds[i]; + bh->state = BUF_STATE_EMPTY; + } + fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain = + &fsg->buffhds[0]; + + new_config = fsg->new_config; + old_state = fsg->state; + + if (old_state == FSG_STATE_ABORT_BULK_OUT) + fsg->state = FSG_STATE_STATUS_PHASE; + else { + for (i = 0; i < fsg->nluns; ++i) { + curlun = &fsg->luns[i]; + curlun->prevent_medium_removal = 0; + curlun->sense_data = curlun->unit_attention_data = + SS_NO_SENSE; + curlun->sense_data_info = 0; + curlun->info_valid = 0; + } + fsg->state = FSG_STATE_IDLE; + } + spin_unlock_irqrestore(&fsg->lock, flags); + + /* Carry out any extra actions required for the exception */ + switch (old_state) { + default: + break; + + case FSG_STATE_ABORT_BULK_OUT: + DBG(fsg, "FSG_STATE_ABORT_BULK_OUT\n"); + spin_lock_irqsave(&fsg->lock, flags); + if (fsg->state == FSG_STATE_STATUS_PHASE) + fsg->state = FSG_STATE_IDLE; + spin_unlock_irqrestore(&fsg->lock, flags); + break; + + case FSG_STATE_RESET: + /* really not much to do here */ + break; + + case FSG_STATE_CONFIG_CHANGE: + rc = do_set_config(fsg, new_config); + if (new_config == 0) { + /* We're using the backing file */ + down_read(&fsg->filesem); + fsync_all(fsg); + up_read(&fsg->filesem); + } + break; + + case FSG_STATE_EXIT: + case FSG_STATE_TERMINATED: + do_set_config(fsg, 0); /* Free resources */ + spin_lock_irqsave(&fsg->lock, flags); + fsg->state = FSG_STATE_TERMINATED; /* Stop the thread */ + spin_unlock_irqrestore(&fsg->lock, flags); + break; + } +} + + +/*-------------------------------------------------------------------------*/ + +static int fsg_main_thread(void *fsg_) +{ + struct fsg_dev *fsg = fsg_; + unsigned long flags; + + /* Allow the thread to be killed by a signal, but set the signal mask + * to block everything but INT, TERM, KILL, and USR1. */ + allow_signal(SIGINT); + allow_signal(SIGTERM); + allow_signal(SIGKILL); + allow_signal(SIGUSR1); + + /* Allow the thread to be frozen */ + set_freezable(); + + /* Arrange for userspace references to be interpreted as kernel + * pointers. That way we can pass a kernel pointer to a routine + * that expects a __user pointer and it will work okay. */ + set_fs(get_ds()); + + /* The main loop */ + while (fsg->state != FSG_STATE_TERMINATED) { + if (exception_in_progress(fsg) || signal_pending(current)) { + handle_exception(fsg); + continue; + } + + if (!fsg->running) { + sleep_thread(fsg); + continue; + } + + if (get_next_command(fsg)) + continue; + + spin_lock_irqsave(&fsg->lock, flags); + if (!exception_in_progress(fsg)) + fsg->state = FSG_STATE_DATA_PHASE; + spin_unlock_irqrestore(&fsg->lock, flags); + + if (do_scsi_command(fsg) || finish_reply(fsg)) + continue; + + spin_lock_irqsave(&fsg->lock, flags); + if (!exception_in_progress(fsg)) + fsg->state = FSG_STATE_STATUS_PHASE; + spin_unlock_irqrestore(&fsg->lock, flags); + + if (send_status(fsg)) + continue; + + spin_lock_irqsave(&fsg->lock, flags); + if (!exception_in_progress(fsg)) + fsg->state = FSG_STATE_IDLE; + spin_unlock_irqrestore(&fsg->lock, flags); + } + + spin_lock_irqsave(&fsg->lock, flags); + fsg->thread_task = NULL; + spin_unlock_irqrestore(&fsg->lock, flags); + + /* In case we are exiting because of a signal, unregister the + * gadget driver and close the backing file. */ + if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags)) + close_all_backing_files(fsg); + + /* Let the unbind and cleanup routines know the thread has exited */ + complete_and_exit(&fsg->thread_notifier, 0); +} + + +/*-------------------------------------------------------------------------*/ + +/* If the next two routines are called while the gadget is registered, + * the caller must own fsg->filesem for writing. */ + +static int open_backing_file(struct fsg_dev *fsg, struct lun *curlun, + const char *filename) +{ + int ro; + struct file *filp = NULL; + int rc = -EINVAL; + struct inode *inode = NULL; + loff_t size; + loff_t num_sectors; + + /* R/W if we can, R/O if we must */ + ro = curlun->ro; + if (!ro) { + filp = filp_open(filename, O_RDWR | O_LARGEFILE, 0); + if (-EROFS == PTR_ERR(filp)) + ro = 1; + } + if (ro) + filp = filp_open(filename, O_RDONLY | O_LARGEFILE, 0); + if (IS_ERR(filp)) { + LINFO(curlun, "unable to open backing file: %s\n", filename); + return PTR_ERR(filp); + } + + if (!(filp->f_mode & FMODE_WRITE)) + ro = 1; + + if (filp->f_path.dentry) + inode = filp->f_path.dentry->d_inode; + if (inode && S_ISBLK(inode->i_mode)) { + if (bdev_read_only(inode->i_bdev)) + ro = 1; + } else if (!inode || !S_ISREG(inode->i_mode)) { + LINFO(curlun, "invalid file type: %s\n", filename); + goto out; + } + + /* If we can't read the file, it's no good. + * If we can't write the file, use it read-only. */ + if (!filp->f_op || !(filp->f_op->read || filp->f_op->aio_read)) { + LINFO(curlun, "file not readable: %s\n", filename); + goto out; + } + if (!(filp->f_op->write || filp->f_op->aio_write)) + ro = 1; + + size = i_size_read(inode->i_mapping->host); + if (size < 0) { + LINFO(curlun, "unable to find file size: %s\n", filename); + rc = (int) size; + goto out; + } + num_sectors = size >> 9; /* File size in 512-byte sectors */ + if (num_sectors == 0) { + LINFO(curlun, "file too small: %s\n", filename); + rc = -ETOOSMALL; + goto out; + } + + get_file(filp); + curlun->ro = ro; + curlun->filp = filp; + curlun->file_length = size; + curlun->unflushed_bytes = 0; + curlun->num_sectors = num_sectors; + LDBG(curlun, "open backing file: %s size: %lld num_sectors: %lld\n", + filename, size, num_sectors); + rc = 0; + adjust_wake_lock(fsg); + +out: + filp_close(filp, current->files); + return rc; +} + + +static void close_backing_file(struct fsg_dev *fsg, struct lun *curlun) +{ + if (curlun->filp) { + int rc; + + /* + * XXX: San: Ugly hack here added to ensure that + * our pages get synced to disk. + * Also drop caches here just to be extra-safe + */ + rc = vfs_fsync(curlun->filp, curlun->filp->f_path.dentry, 1); + if (rc < 0) + printk(KERN_ERR "ums: Error syncing data (%d)\n", rc); + /* drop_pagecache and drop_slab are no longer available */ + /* drop_pagecache(); */ + /* drop_slab(); */ + + LDBG(curlun, "close backing file\n"); + fput(curlun->filp); + curlun->filp = NULL; + adjust_wake_lock(fsg); + } +} + +static void close_all_backing_files(struct fsg_dev *fsg) +{ + int i; + + for (i = 0; i < fsg->nluns; ++i) + close_backing_file(fsg, &fsg->luns[i]); +} + +static ssize_t show_file(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct lun *curlun = dev_to_lun(dev); + struct fsg_dev *fsg = dev_get_drvdata(dev); + char *p; + ssize_t rc; + + down_read(&fsg->filesem); + if (backing_file_is_open(curlun)) { /* Get the complete pathname */ + p = d_path(&curlun->filp->f_path, buf, PAGE_SIZE - 1); + if (IS_ERR(p)) + rc = PTR_ERR(p); + else { + rc = strlen(p); + memmove(buf, p, rc); + buf[rc] = '\n'; /* Add a newline */ + buf[++rc] = 0; + } + } else { /* No file, return 0 bytes */ + *buf = 0; + rc = 0; + } + up_read(&fsg->filesem); + return rc; +} + +static ssize_t store_file(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct lun *curlun = dev_to_lun(dev); + struct fsg_dev *fsg = dev_get_drvdata(dev); + int rc = 0; + + DBG(fsg, "store_file: \"%s\"\n", buf); +#if 0 + /* disabled because we need to allow closing the backing file if the media was removed */ + if (curlun->prevent_medium_removal && backing_file_is_open(curlun)) { + LDBG(curlun, "eject attempt prevented\n"); + return -EBUSY; /* "Door is locked" */ + } +#endif + + /* Remove a trailing newline */ + if (count > 0 && buf[count-1] == '\n') + ((char *) buf)[count-1] = 0; + + /* Eject current medium */ + down_write(&fsg->filesem); + if (backing_file_is_open(curlun)) { + close_backing_file(fsg, curlun); + curlun->unit_attention_data = SS_MEDIUM_NOT_PRESENT; + } + + /* Load new medium */ + if (count > 0 && buf[0]) { + rc = open_backing_file(fsg, curlun, buf); + if (rc == 0) + curlun->unit_attention_data = + SS_NOT_READY_TO_READY_TRANSITION; + } + up_write(&fsg->filesem); + return (rc < 0 ? rc : count); +} + + +static DEVICE_ATTR(file, 0444, show_file, store_file); + +/*-------------------------------------------------------------------------*/ + +static void fsg_release(struct kref *ref) +{ + struct fsg_dev *fsg = container_of(ref, struct fsg_dev, ref); + + kfree(fsg->luns); + kfree(fsg); +} + +static void lun_release(struct device *dev) +{ + struct fsg_dev *fsg = dev_get_drvdata(dev); + + kref_put(&fsg->ref, fsg_release); +} + + +/*-------------------------------------------------------------------------*/ + +static int __init fsg_alloc(void) +{ + struct fsg_dev *fsg; + + fsg = kzalloc(sizeof *fsg, GFP_KERNEL); + if (!fsg) + return -ENOMEM; + spin_lock_init(&fsg->lock); + init_rwsem(&fsg->filesem); + kref_init(&fsg->ref); + init_completion(&fsg->thread_notifier); + + the_fsg = fsg; + return 0; +} + +static ssize_t print_switch_name(struct switch_dev *sdev, char *buf) +{ + return sprintf(buf, "%s\n", DRIVER_NAME); +} + +static ssize_t print_switch_state(struct switch_dev *sdev, char *buf) +{ + struct fsg_dev *fsg = container_of(sdev, struct fsg_dev, sdev); + return sprintf(buf, "%s\n", (fsg->config ? "online" : "offline")); +} + +static void +fsg_function_unbind(struct usb_configuration *c, struct usb_function *f) +{ + struct fsg_dev *fsg = func_to_dev(f); + int i; + struct lun *curlun; + + DBG(fsg, "fsg_function_unbind\n"); + clear_bit(REGISTERED, &fsg->atomic_bitflags); + + /* Unregister the sysfs attribute files and the LUNs */ + for (i = 0; i < fsg->nluns; ++i) { + curlun = &fsg->luns[i]; + if (curlun->registered) { + device_remove_file(&curlun->dev, &dev_attr_file); + device_unregister(&curlun->dev); + curlun->registered = 0; + } + } + + /* If the thread isn't already dead, tell it to exit now */ + if (fsg->state != FSG_STATE_TERMINATED) { + raise_exception(fsg, FSG_STATE_EXIT); + wait_for_completion(&fsg->thread_notifier); + + /* The cleanup routine waits for this completion also */ + complete(&fsg->thread_notifier); + } + + /* Free the data buffers */ + for (i = 0; i < NUM_BUFFERS; ++i) + kfree(fsg->buffhds[i].buf); + switch_dev_unregister(&fsg->sdev); +} + +static int __init +fsg_function_bind(struct usb_configuration *c, struct usb_function *f) +{ + struct usb_composite_dev *cdev = c->cdev; + struct fsg_dev *fsg = func_to_dev(f); + int rc; + int i; + int id; + struct lun *curlun; + struct usb_ep *ep; + char *pathbuf, *p; + + fsg->cdev = cdev; + DBG(fsg, "fsg_function_bind\n"); + + dev_attr_file.attr.mode = 0644; + + /* Find out how many LUNs there should be */ + i = fsg->nluns; + if (i == 0) + i = 1; + if (i > MAX_LUNS) { + ERROR(fsg, "invalid number of LUNs: %d\n", i); + rc = -EINVAL; + goto out; + } + + /* Create the LUNs, open their backing files, and register the + * LUN devices in sysfs. */ + fsg->luns = kzalloc(i * sizeof(struct lun), GFP_KERNEL); + if (!fsg->luns) { + rc = -ENOMEM; + goto out; + } + fsg->nluns = i; + + for (i = 0; i < fsg->nluns; ++i) { + curlun = &fsg->luns[i]; + curlun->ro = 0; + curlun->dev.release = lun_release; + /* use "usb_mass_storage" platform device as parent if available */ + if (fsg->pdev) + curlun->dev.parent = &fsg->pdev->dev; + else + curlun->dev.parent = &cdev->gadget->dev; + dev_set_drvdata(&curlun->dev, fsg); + + if (kobject_set_name(&curlun->dev.kobj, "lun%d", i)) { + INFO(fsg, "failed to alloc kobj dev name\n"); + goto out; + } + + rc = device_register(&curlun->dev); + if (rc != 0) { + INFO(fsg, "failed to register LUN%d: %d\n", i, rc); + goto out; + } + rc = device_create_file(&curlun->dev, &dev_attr_file); + if (rc != 0) { + ERROR(fsg, "device_create_file failed: %d\n", rc); + device_unregister(&curlun->dev); + goto out; + } + curlun->registered = 1; + kref_get(&fsg->ref); + } + + /* allocate interface ID(s) */ + id = usb_interface_id(c, f); + if (id < 0) + return id; + intf_desc.bInterfaceNumber = id; + + ep = usb_ep_autoconfig(cdev->gadget, &fs_bulk_in_desc); + if (!ep) + goto autoconf_fail; + ep->driver_data = fsg; /* claim the endpoint */ + fsg->bulk_in = ep; + + ep = usb_ep_autoconfig(cdev->gadget, &fs_bulk_out_desc); + if (!ep) + goto autoconf_fail; + ep->driver_data = fsg; /* claim the endpoint */ + fsg->bulk_out = ep; + + rc = -ENOMEM; + + if (gadget_is_dualspeed(cdev->gadget)) { + /* Assume endpoint addresses are the same for both speeds */ + hs_bulk_in_desc.bEndpointAddress = + fs_bulk_in_desc.bEndpointAddress; + hs_bulk_out_desc.bEndpointAddress = + fs_bulk_out_desc.bEndpointAddress; + + f->hs_descriptors = hs_function; + } + + /* Allocate the data buffers */ + for (i = 0; i < NUM_BUFFERS; ++i) { + struct fsg_buffhd *bh = &fsg->buffhds[i]; + + /* Allocate for the bulk-in endpoint. We assume that + * the buffer will also work with the bulk-out (and + * interrupt-in) endpoint. */ + bh->buf = kmalloc(fsg->buf_size, GFP_KERNEL); + if (!bh->buf) + goto out; + bh->next = bh + 1; + } + fsg->buffhds[NUM_BUFFERS - 1].next = &fsg->buffhds[0]; + + fsg->thread_task = kthread_create(fsg_main_thread, fsg, + shortname); + if (IS_ERR(fsg->thread_task)) { + rc = PTR_ERR(fsg->thread_task); + ERROR(fsg, "kthread_create failed: %d\n", rc); + goto out; + } + + INFO(fsg, "Number of LUNs=%d\n", fsg->nluns); + + pathbuf = kmalloc(PATH_MAX, GFP_KERNEL); + for (i = 0; i < fsg->nluns; ++i) { + curlun = &fsg->luns[i]; + if (backing_file_is_open(curlun)) { + p = NULL; + if (pathbuf) { + p = d_path(&curlun->filp->f_path, + pathbuf, PATH_MAX); + if (IS_ERR(p)) + p = NULL; + } + LINFO(curlun, "ro=%d, file: %s\n", + curlun->ro, (p ? p : "(error)")); + } + } + kfree(pathbuf); + + set_bit(REGISTERED, &fsg->atomic_bitflags); + + /* Tell the thread to start working */ + wake_up_process(fsg->thread_task); + return 0; + +autoconf_fail: + ERROR(fsg, "unable to autoconfigure all endpoints\n"); + rc = -ENOTSUPP; + +out: + DBG(fsg, "fsg_function_bind failed: %d\n", rc); + fsg->state = FSG_STATE_TERMINATED; /* The thread is dead */ + fsg_function_unbind(c, f); + close_all_backing_files(fsg); + return rc; +} + +static int fsg_function_set_alt(struct usb_function *f, + unsigned intf, unsigned alt) +{ + struct fsg_dev *fsg = func_to_dev(f); + DBG(fsg, "fsg_function_set_alt intf: %d alt: %d\n", intf, alt); + fsg->new_config = 1; + raise_exception(fsg, FSG_STATE_CONFIG_CHANGE); + return 0; +} + +static void fsg_function_disable(struct usb_function *f) +{ + struct fsg_dev *fsg = func_to_dev(f); + DBG(fsg, "fsg_function_disable\n"); + if (fsg->new_config) + do_set_interface(fsg, -1); + fsg->new_config = 0; + if (fsg->config != 0) { + fsg->config = 0; + do_set_interface(fsg, -1); + } + raise_exception(fsg, FSG_STATE_CONFIG_CHANGE); +} + +static int __init fsg_probe(struct platform_device *pdev) +{ + struct usb_mass_storage_platform_data *pdata = pdev->dev.platform_data; + struct fsg_dev *fsg = the_fsg; + + fsg->pdev = pdev; + printk(KERN_INFO "fsg_probe pdata: %p\n", pdata); + + if (pdata) { + if (pdata->vendor) + fsg->vendor = pdata->vendor; + + if (pdata->product) + fsg->product = pdata->product; + + if (pdata->release) + fsg->release = pdata->release; + } + + return 0; +} + +static struct platform_driver fsg_platform_driver = { + .driver = { .name = "usb_mass_storage", }, + .probe = fsg_probe, +}; + +int __init mass_storage_function_add(struct usb_composite_dev *cdev, + struct usb_configuration *c, int nluns) +{ + int rc; + struct fsg_dev *fsg; + + printk(KERN_INFO "mass_storage_function_add\n"); + rc = fsg_alloc(); + if (rc) + return rc; + fsg = the_fsg; + fsg->nluns = nluns; + + spin_lock_init(&fsg->lock); + init_rwsem(&fsg->filesem); + kref_init(&fsg->ref); + init_completion(&fsg->thread_notifier); + + the_fsg->buf_size = BULK_BUFFER_SIZE; + the_fsg->sdev.name = DRIVER_NAME; + the_fsg->sdev.print_name = print_switch_name; + the_fsg->sdev.print_state = print_switch_state; + rc = switch_dev_register(&the_fsg->sdev); + if (rc < 0) + goto err_switch_dev_register; + + rc = platform_driver_register(&fsg_platform_driver); + if (rc != 0) + goto err_platform_driver_register; + + wake_lock_init(&the_fsg->wake_lock, WAKE_LOCK_SUSPEND, + "usb_mass_storage"); + + fsg->cdev = cdev; + fsg->function.name = shortname; + fsg->function.descriptors = fs_function; + fsg->function.bind = fsg_function_bind; + fsg->function.unbind = fsg_function_unbind; + fsg->function.setup = fsg_function_setup; + fsg->function.set_alt = fsg_function_set_alt; + fsg->function.disable = fsg_function_disable; + + rc = usb_add_function(c, &fsg->function); + if (rc != 0) + goto err_usb_add_function; + + return 0; + +err_usb_add_function: + wake_lock_destroy(&the_fsg->wake_lock); + platform_driver_unregister(&fsg_platform_driver); +err_platform_driver_register: + switch_dev_unregister(&the_fsg->sdev); +err_switch_dev_register: + kref_put(&the_fsg->ref, fsg_release); + + return rc; +} + + diff --git a/drivers/usb/gadget/f_mass_storage.h b/drivers/usb/gadget/f_mass_storage.h new file mode 100644 index 000000000000..8e63ac0cbe93 --- /dev/null +++ b/drivers/usb/gadget/f_mass_storage.h @@ -0,0 +1,52 @@ +/* + * drivers/usb/gadget/f_mass_storage.h + * + * Function Driver for USB Mass Storage + * + * Copyright (C) 2008 Google, Inc. + * Author: Mike Lockwood + * + * Based heavily on the file_storage gadget driver in + * drivers/usb/gadget/file_storage.c and licensed under the same terms: + * + * Copyright (C) 2003-2007 Alan Stern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __F_MASS_STORAGE_H +#define __F_MASS_STORAGE_H + +int mass_storage_function_add(struct usb_composite_dev *cdev, + struct usb_configuration *c, int nluns); + +#endif /* __F_MASS_STORAGE_H */ diff --git a/drivers/video/mxc/ad9389.c b/drivers/video/mxc/ad9389.c new file mode 100644 index 000000000000..9765cfd1a17f --- /dev/null +++ b/drivers/video/mxc/ad9389.c @@ -0,0 +1,815 @@ +/* + * ad9389.c + * + * Copyright 2010 - Digi International, Inc. All Rights Reserved. + * + * Based on ad9889.c driver from Armadeus: + * Copyright (C) 2009 Armadeus Systems + * And also on mxcfb_sii9022.c from Pegatron: + * Copyright 2009 Pegatron Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include